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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
1767e931 PG |
32 | #include <linux/moduleparam.h> |
33 | #include <linux/export.h> | |
448353ca | 34 | #include <linux/swap.h> |
05da4558 | 35 | #include <linux/hugetlb.h> |
2f333bcb | 36 | #include <linux/compiler.h> |
bc6678a3 | 37 | #include <linux/srcu.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
3f07c014 | 39 | #include <linux/sched/signal.h> |
bf998156 | 40 | #include <linux/uaccess.h> |
114df303 | 41 | #include <linux/hash.h> |
f160c7b7 | 42 | #include <linux/kern_levels.h> |
6aa8b732 | 43 | |
e495606d AK |
44 | #include <asm/page.h> |
45 | #include <asm/cmpxchg.h> | |
4e542370 | 46 | #include <asm/io.h> |
13673a90 | 47 | #include <asm/vmx.h> |
3d0c27ad | 48 | #include <asm/kvm_page_track.h> |
1261bfa3 | 49 | #include "trace.h" |
6aa8b732 | 50 | |
18552672 JR |
51 | /* |
52 | * When setting this variable to true it enables Two-Dimensional-Paging | |
53 | * where the hardware walks 2 page tables: | |
54 | * 1. the guest-virtual to guest-physical | |
55 | * 2. while doing 1. it walks guest-physical to host-physical | |
56 | * If the hardware supports that we don't need to do shadow paging. | |
57 | */ | |
2f333bcb | 58 | bool tdp_enabled = false; |
18552672 | 59 | |
8b1fe17c XG |
60 | enum { |
61 | AUDIT_PRE_PAGE_FAULT, | |
62 | AUDIT_POST_PAGE_FAULT, | |
63 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
64 | AUDIT_POST_PTE_WRITE, |
65 | AUDIT_PRE_SYNC, | |
66 | AUDIT_POST_SYNC | |
8b1fe17c | 67 | }; |
37a7d8b0 | 68 | |
8b1fe17c | 69 | #undef MMU_DEBUG |
37a7d8b0 AK |
70 | |
71 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
72 | static bool dbg = 0; |
73 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
74 | |
75 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
76 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 77 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 78 | #else |
37a7d8b0 AK |
79 | #define pgprintk(x...) do { } while (0) |
80 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 81 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 82 | #endif |
6aa8b732 | 83 | |
957ed9ef XG |
84 | #define PTE_PREFETCH_NUM 8 |
85 | ||
00763e41 | 86 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
87 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
88 | ||
6aa8b732 AK |
89 | #define PT64_LEVEL_BITS 9 |
90 | ||
91 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 92 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 93 | |
6aa8b732 AK |
94 | #define PT64_INDEX(address, level)\ |
95 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
96 | ||
97 | ||
98 | #define PT32_LEVEL_BITS 10 | |
99 | ||
100 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 101 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 102 | |
e04da980 JR |
103 | #define PT32_LVL_OFFSET_MASK(level) \ |
104 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
105 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
106 | |
107 | #define PT32_INDEX(address, level)\ | |
108 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
109 | ||
110 | ||
27aba766 | 111 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
112 | #define PT64_DIR_BASE_ADDR_MASK \ |
113 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
114 | #define PT64_LVL_ADDR_MASK(level) \ |
115 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
116 | * PT64_LEVEL_BITS))) - 1)) | |
117 | #define PT64_LVL_OFFSET_MASK(level) \ | |
118 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
119 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
120 | |
121 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
122 | #define PT32_DIR_BASE_ADDR_MASK \ | |
123 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
124 | #define PT32_LVL_ADDR_MASK(level) \ |
125 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 127 | |
53166229 GN |
128 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
129 | | shadow_x_mask | shadow_nx_mask) | |
6aa8b732 | 130 | |
fe135d2c AK |
131 | #define ACC_EXEC_MASK 1 |
132 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
133 | #define ACC_USER_MASK PT_USER_MASK | |
134 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
135 | ||
f160c7b7 JS |
136 | /* The mask for the R/X bits in EPT PTEs */ |
137 | #define PT64_EPT_READABLE_MASK 0x1ull | |
138 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
139 | ||
90bb6fc5 AK |
140 | #include <trace/events/kvm.h> |
141 | ||
07420171 AK |
142 | #define CREATE_TRACE_POINTS |
143 | #include "mmutrace.h" | |
144 | ||
49fde340 XG |
145 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
146 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 147 | |
135f8c2b AK |
148 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
149 | ||
220f773a TY |
150 | /* make pte_list_desc fit well in cache line */ |
151 | #define PTE_LIST_EXT 3 | |
152 | ||
53c07b18 XG |
153 | struct pte_list_desc { |
154 | u64 *sptes[PTE_LIST_EXT]; | |
155 | struct pte_list_desc *more; | |
cd4a4e53 AK |
156 | }; |
157 | ||
2d11123a AK |
158 | struct kvm_shadow_walk_iterator { |
159 | u64 addr; | |
160 | hpa_t shadow_addr; | |
2d11123a | 161 | u64 *sptep; |
dd3bfd59 | 162 | int level; |
2d11123a AK |
163 | unsigned index; |
164 | }; | |
165 | ||
166 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
167 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
168 | shadow_walk_okay(&(_walker)); \ | |
169 | shadow_walk_next(&(_walker))) | |
170 | ||
c2a2ac2b XG |
171 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
172 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
173 | shadow_walk_okay(&(_walker)) && \ | |
174 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
175 | __shadow_walk_next(&(_walker), spte)) | |
176 | ||
53c07b18 | 177 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 178 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 179 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 180 | |
7b52345e SY |
181 | static u64 __read_mostly shadow_nx_mask; |
182 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
183 | static u64 __read_mostly shadow_user_mask; | |
184 | static u64 __read_mostly shadow_accessed_mask; | |
185 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 186 | static u64 __read_mostly shadow_mmio_mask; |
dcdca5fe | 187 | static u64 __read_mostly shadow_mmio_value; |
ffb128c8 | 188 | static u64 __read_mostly shadow_present_mask; |
ce88decf | 189 | |
f160c7b7 | 190 | /* |
ac8d57e5 PF |
191 | * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value. |
192 | * Non-present SPTEs with shadow_acc_track_value set are in place for access | |
193 | * tracking. | |
f160c7b7 JS |
194 | */ |
195 | static u64 __read_mostly shadow_acc_track_mask; | |
196 | static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK; | |
197 | ||
198 | /* | |
199 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
200 | * as not-present for access tracking purposes. We do not save the W bit as the | |
201 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
202 | * restored only when a write is attempted to the page. | |
203 | */ | |
204 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
205 | PT64_EPT_EXECUTABLE_MASK; | |
206 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
207 | ||
ce88decf | 208 | static void mmu_spte_set(u64 *sptep, u64 spte); |
e676505a | 209 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf | 210 | |
dcdca5fe | 211 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value) |
ce88decf | 212 | { |
dcdca5fe PF |
213 | BUG_ON((mmio_mask & mmio_value) != mmio_value); |
214 | shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK; | |
312b616b | 215 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
ce88decf XG |
216 | } |
217 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
218 | ||
ac8d57e5 PF |
219 | static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) |
220 | { | |
221 | return sp->role.ad_disabled; | |
222 | } | |
223 | ||
224 | static inline bool spte_ad_enabled(u64 spte) | |
225 | { | |
226 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
227 | return !(spte & shadow_acc_track_value); | |
228 | } | |
229 | ||
230 | static inline u64 spte_shadow_accessed_mask(u64 spte) | |
231 | { | |
232 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
233 | return spte_ad_enabled(spte) ? shadow_accessed_mask : 0; | |
234 | } | |
235 | ||
236 | static inline u64 spte_shadow_dirty_mask(u64 spte) | |
237 | { | |
238 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
239 | return spte_ad_enabled(spte) ? shadow_dirty_mask : 0; | |
240 | } | |
241 | ||
f160c7b7 JS |
242 | static inline bool is_access_track_spte(u64 spte) |
243 | { | |
ac8d57e5 | 244 | return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0; |
f160c7b7 JS |
245 | } |
246 | ||
f2fd125d | 247 | /* |
ee3d1570 DM |
248 | * the low bit of the generation number is always presumed to be zero. |
249 | * This disables mmio caching during memslot updates. The concept is | |
250 | * similar to a seqcount but instead of retrying the access we just punt | |
251 | * and ignore the cache. | |
252 | * | |
253 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
254 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 255 | */ |
ee3d1570 | 256 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
257 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
258 | ||
ee3d1570 DM |
259 | #define MMIO_GEN_SHIFT 20 |
260 | #define MMIO_GEN_LOW_SHIFT 10 | |
261 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 262 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
263 | |
264 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
265 | { | |
266 | u64 mask; | |
267 | ||
842bb26a | 268 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
269 | |
270 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
271 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
272 | return mask; | |
273 | } | |
274 | ||
275 | static unsigned int get_mmio_spte_generation(u64 spte) | |
276 | { | |
277 | unsigned int gen; | |
278 | ||
279 | spte &= ~shadow_mmio_mask; | |
280 | ||
281 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
282 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
283 | return gen; | |
284 | } | |
285 | ||
54bf36aa | 286 | static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu) |
f8f55942 | 287 | { |
54bf36aa | 288 | return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
289 | } |
290 | ||
54bf36aa | 291 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 292 | unsigned access) |
ce88decf | 293 | { |
54bf36aa | 294 | unsigned int gen = kvm_current_mmio_generation(vcpu); |
f8f55942 | 295 | u64 mask = generation_mmio_spte_mask(gen); |
95b0430d | 296 | |
ce88decf | 297 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
dcdca5fe | 298 | mask |= shadow_mmio_value | access | gfn << PAGE_SHIFT; |
f2fd125d | 299 | |
f8f55942 | 300 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 301 | mmu_spte_set(sptep, mask); |
ce88decf XG |
302 | } |
303 | ||
304 | static bool is_mmio_spte(u64 spte) | |
305 | { | |
dcdca5fe | 306 | return (spte & shadow_mmio_mask) == shadow_mmio_value; |
ce88decf XG |
307 | } |
308 | ||
309 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
310 | { | |
842bb26a | 311 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 312 | return (spte & ~mask) >> PAGE_SHIFT; |
ce88decf XG |
313 | } |
314 | ||
315 | static unsigned get_mmio_spte_access(u64 spte) | |
316 | { | |
842bb26a | 317 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 318 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
319 | } |
320 | ||
54bf36aa | 321 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 322 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
323 | { |
324 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 325 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
326 | return true; |
327 | } | |
328 | ||
329 | return false; | |
330 | } | |
c7addb90 | 331 | |
54bf36aa | 332 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 333 | { |
089504c0 XG |
334 | unsigned int kvm_gen, spte_gen; |
335 | ||
54bf36aa | 336 | kvm_gen = kvm_current_mmio_generation(vcpu); |
089504c0 XG |
337 | spte_gen = get_mmio_spte_generation(spte); |
338 | ||
339 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
340 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
341 | } |
342 | ||
ce00053b PF |
343 | /* |
344 | * Sets the shadow PTE masks used by the MMU. | |
345 | * | |
346 | * Assumptions: | |
347 | * - Setting either @accessed_mask or @dirty_mask requires setting both | |
348 | * - At least one of @accessed_mask or @acc_track_mask must be set | |
349 | */ | |
7b52345e | 350 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 JS |
351 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
352 | u64 acc_track_mask) | |
7b52345e | 353 | { |
ce00053b PF |
354 | BUG_ON(!dirty_mask != !accessed_mask); |
355 | BUG_ON(!accessed_mask && !acc_track_mask); | |
ac8d57e5 | 356 | BUG_ON(acc_track_mask & shadow_acc_track_value); |
312b616b | 357 | |
7b52345e SY |
358 | shadow_user_mask = user_mask; |
359 | shadow_accessed_mask = accessed_mask; | |
360 | shadow_dirty_mask = dirty_mask; | |
361 | shadow_nx_mask = nx_mask; | |
362 | shadow_x_mask = x_mask; | |
ffb128c8 | 363 | shadow_present_mask = p_mask; |
f160c7b7 | 364 | shadow_acc_track_mask = acc_track_mask; |
7b52345e SY |
365 | } |
366 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
367 | ||
f160c7b7 JS |
368 | void kvm_mmu_clear_all_pte_masks(void) |
369 | { | |
370 | shadow_user_mask = 0; | |
371 | shadow_accessed_mask = 0; | |
372 | shadow_dirty_mask = 0; | |
373 | shadow_nx_mask = 0; | |
374 | shadow_x_mask = 0; | |
375 | shadow_mmio_mask = 0; | |
376 | shadow_present_mask = 0; | |
377 | shadow_acc_track_mask = 0; | |
378 | } | |
379 | ||
6aa8b732 AK |
380 | static int is_cpuid_PSE36(void) |
381 | { | |
382 | return 1; | |
383 | } | |
384 | ||
73b1087e AK |
385 | static int is_nx(struct kvm_vcpu *vcpu) |
386 | { | |
f6801dff | 387 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
388 | } |
389 | ||
c7addb90 AK |
390 | static int is_shadow_present_pte(u64 pte) |
391 | { | |
f160c7b7 | 392 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
393 | } |
394 | ||
05da4558 MT |
395 | static int is_large_pte(u64 pte) |
396 | { | |
397 | return pte & PT_PAGE_SIZE_MASK; | |
398 | } | |
399 | ||
776e6633 MT |
400 | static int is_last_spte(u64 pte, int level) |
401 | { | |
402 | if (level == PT_PAGE_TABLE_LEVEL) | |
403 | return 1; | |
852e3c19 | 404 | if (is_large_pte(pte)) |
776e6633 MT |
405 | return 1; |
406 | return 0; | |
407 | } | |
408 | ||
d3e328f2 JS |
409 | static bool is_executable_pte(u64 spte) |
410 | { | |
411 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
412 | } | |
413 | ||
ba049e93 | 414 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 415 | { |
35149e21 | 416 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
417 | } |
418 | ||
da928521 AK |
419 | static gfn_t pse36_gfn_delta(u32 gpte) |
420 | { | |
421 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
422 | ||
423 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
424 | } | |
425 | ||
603e0651 | 426 | #ifdef CONFIG_X86_64 |
d555c333 | 427 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 428 | { |
b19ee2ff | 429 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
430 | } |
431 | ||
603e0651 | 432 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 433 | { |
b19ee2ff | 434 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
435 | } |
436 | ||
437 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
438 | { | |
439 | return xchg(sptep, spte); | |
440 | } | |
c2a2ac2b XG |
441 | |
442 | static u64 __get_spte_lockless(u64 *sptep) | |
443 | { | |
444 | return ACCESS_ONCE(*sptep); | |
445 | } | |
a9221dd5 | 446 | #else |
603e0651 XG |
447 | union split_spte { |
448 | struct { | |
449 | u32 spte_low; | |
450 | u32 spte_high; | |
451 | }; | |
452 | u64 spte; | |
453 | }; | |
a9221dd5 | 454 | |
c2a2ac2b XG |
455 | static void count_spte_clear(u64 *sptep, u64 spte) |
456 | { | |
457 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
458 | ||
459 | if (is_shadow_present_pte(spte)) | |
460 | return; | |
461 | ||
462 | /* Ensure the spte is completely set before we increase the count */ | |
463 | smp_wmb(); | |
464 | sp->clear_spte_count++; | |
465 | } | |
466 | ||
603e0651 XG |
467 | static void __set_spte(u64 *sptep, u64 spte) |
468 | { | |
469 | union split_spte *ssptep, sspte; | |
a9221dd5 | 470 | |
603e0651 XG |
471 | ssptep = (union split_spte *)sptep; |
472 | sspte = (union split_spte)spte; | |
473 | ||
474 | ssptep->spte_high = sspte.spte_high; | |
475 | ||
476 | /* | |
477 | * If we map the spte from nonpresent to present, We should store | |
478 | * the high bits firstly, then set present bit, so cpu can not | |
479 | * fetch this spte while we are setting the spte. | |
480 | */ | |
481 | smp_wmb(); | |
482 | ||
b19ee2ff | 483 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
484 | } |
485 | ||
603e0651 XG |
486 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
487 | { | |
488 | union split_spte *ssptep, sspte; | |
489 | ||
490 | ssptep = (union split_spte *)sptep; | |
491 | sspte = (union split_spte)spte; | |
492 | ||
b19ee2ff | 493 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
494 | |
495 | /* | |
496 | * If we map the spte from present to nonpresent, we should clear | |
497 | * present bit firstly to avoid vcpu fetch the old high bits. | |
498 | */ | |
499 | smp_wmb(); | |
500 | ||
501 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 502 | count_spte_clear(sptep, spte); |
603e0651 XG |
503 | } |
504 | ||
505 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
506 | { | |
507 | union split_spte *ssptep, sspte, orig; | |
508 | ||
509 | ssptep = (union split_spte *)sptep; | |
510 | sspte = (union split_spte)spte; | |
511 | ||
512 | /* xchg acts as a barrier before the setting of the high bits */ | |
513 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
514 | orig.spte_high = ssptep->spte_high; |
515 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 516 | count_spte_clear(sptep, spte); |
603e0651 XG |
517 | |
518 | return orig.spte; | |
519 | } | |
c2a2ac2b XG |
520 | |
521 | /* | |
522 | * The idea using the light way get the spte on x86_32 guest is from | |
523 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
524 | * |
525 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
526 | * coalesces them and we are running out of the MMU lock. Therefore | |
527 | * we need to protect against in-progress updates of the spte. | |
528 | * | |
529 | * Reading the spte while an update is in progress may get the old value | |
530 | * for the high part of the spte. The race is fine for a present->non-present | |
531 | * change (because the high part of the spte is ignored for non-present spte), | |
532 | * but for a present->present change we must reread the spte. | |
533 | * | |
534 | * All such changes are done in two steps (present->non-present and | |
535 | * non-present->present), hence it is enough to count the number of | |
536 | * present->non-present updates: if it changed while reading the spte, | |
537 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
538 | */ |
539 | static u64 __get_spte_lockless(u64 *sptep) | |
540 | { | |
541 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
542 | union split_spte spte, *orig = (union split_spte *)sptep; | |
543 | int count; | |
544 | ||
545 | retry: | |
546 | count = sp->clear_spte_count; | |
547 | smp_rmb(); | |
548 | ||
549 | spte.spte_low = orig->spte_low; | |
550 | smp_rmb(); | |
551 | ||
552 | spte.spte_high = orig->spte_high; | |
553 | smp_rmb(); | |
554 | ||
555 | if (unlikely(spte.spte_low != orig->spte_low || | |
556 | count != sp->clear_spte_count)) | |
557 | goto retry; | |
558 | ||
559 | return spte.spte; | |
560 | } | |
603e0651 XG |
561 | #endif |
562 | ||
ea4114bc | 563 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 564 | { |
feb3eb70 GN |
565 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
566 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
567 | } |
568 | ||
8672b721 XG |
569 | static bool spte_has_volatile_bits(u64 spte) |
570 | { | |
f160c7b7 JS |
571 | if (!is_shadow_present_pte(spte)) |
572 | return false; | |
573 | ||
c7ba5b48 | 574 | /* |
6a6256f9 | 575 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
576 | * out of mmu-lock, it can ensure dirty bit is not lost, |
577 | * also, it can help us to get a stable is_writable_pte() | |
578 | * to ensure tlb flush is not missed. | |
579 | */ | |
f160c7b7 JS |
580 | if (spte_can_locklessly_be_made_writable(spte) || |
581 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
582 | return true; |
583 | ||
ac8d57e5 | 584 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
585 | if ((spte & shadow_accessed_mask) == 0 || |
586 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
587 | return true; | |
588 | } | |
8672b721 | 589 | |
f160c7b7 | 590 | return false; |
8672b721 XG |
591 | } |
592 | ||
83ef6c81 | 593 | static bool is_accessed_spte(u64 spte) |
4132779b | 594 | { |
ac8d57e5 PF |
595 | u64 accessed_mask = spte_shadow_accessed_mask(spte); |
596 | ||
597 | return accessed_mask ? spte & accessed_mask | |
598 | : !is_access_track_spte(spte); | |
4132779b XG |
599 | } |
600 | ||
83ef6c81 | 601 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 602 | { |
ac8d57e5 PF |
603 | u64 dirty_mask = spte_shadow_dirty_mask(spte); |
604 | ||
605 | return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
606 | } |
607 | ||
1df9f2dc XG |
608 | /* Rules for using mmu_spte_set: |
609 | * Set the sptep from nonpresent to present. | |
610 | * Note: the sptep being assigned *must* be either not present | |
611 | * or in a state where the hardware will not attempt to update | |
612 | * the spte. | |
613 | */ | |
614 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
615 | { | |
616 | WARN_ON(is_shadow_present_pte(*sptep)); | |
617 | __set_spte(sptep, new_spte); | |
618 | } | |
619 | ||
f39a058d JS |
620 | /* |
621 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
622 | * accessed/dirty status. | |
1df9f2dc | 623 | */ |
f39a058d | 624 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 625 | { |
c7ba5b48 | 626 | u64 old_spte = *sptep; |
4132779b | 627 | |
afd28fe1 | 628 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 629 | |
6e7d0354 XG |
630 | if (!is_shadow_present_pte(old_spte)) { |
631 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 632 | return old_spte; |
6e7d0354 | 633 | } |
4132779b | 634 | |
c7ba5b48 | 635 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 636 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 637 | else |
603e0651 | 638 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 639 | |
83ef6c81 JS |
640 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
641 | ||
f39a058d JS |
642 | return old_spte; |
643 | } | |
644 | ||
645 | /* Rules for using mmu_spte_update: | |
646 | * Update the state bits, it means the mapped pfn is not changed. | |
647 | * | |
648 | * Whenever we overwrite a writable spte with a read-only one we | |
649 | * should flush remote TLBs. Otherwise rmap_write_protect | |
650 | * will find a read-only spte, even though the writable spte | |
651 | * might be cached on a CPU's TLB, the return value indicates this | |
652 | * case. | |
653 | * | |
654 | * Returns true if the TLB needs to be flushed | |
655 | */ | |
656 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
657 | { | |
658 | bool flush = false; | |
659 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
660 | ||
661 | if (!is_shadow_present_pte(old_spte)) | |
662 | return false; | |
663 | ||
c7ba5b48 XG |
664 | /* |
665 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 666 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
667 | * spte_has_volatile_bits(). |
668 | */ | |
ea4114bc | 669 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 670 | !is_writable_pte(new_spte)) |
83ef6c81 | 671 | flush = true; |
4132779b | 672 | |
7e71a59b | 673 | /* |
83ef6c81 | 674 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
675 | * to guarantee consistency between TLB and page tables. |
676 | */ | |
7e71a59b | 677 | |
83ef6c81 JS |
678 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
679 | flush = true; | |
4132779b | 680 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
681 | } |
682 | ||
683 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
684 | flush = true; | |
4132779b | 685 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 686 | } |
6e7d0354 | 687 | |
83ef6c81 | 688 | return flush; |
b79b93f9 AK |
689 | } |
690 | ||
1df9f2dc XG |
691 | /* |
692 | * Rules for using mmu_spte_clear_track_bits: | |
693 | * It sets the sptep from present to nonpresent, and track the | |
694 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 695 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
696 | */ |
697 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
698 | { | |
ba049e93 | 699 | kvm_pfn_t pfn; |
1df9f2dc XG |
700 | u64 old_spte = *sptep; |
701 | ||
702 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 703 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 704 | else |
603e0651 | 705 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 706 | |
afd28fe1 | 707 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
708 | return 0; |
709 | ||
710 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
711 | |
712 | /* | |
713 | * KVM does not hold the refcount of the page used by | |
714 | * kvm mmu, before reclaiming the page, we should | |
715 | * unmap it from mmu first. | |
716 | */ | |
bf4bea8e | 717 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 718 | |
83ef6c81 | 719 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 720 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
721 | |
722 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 723 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 724 | |
1df9f2dc XG |
725 | return 1; |
726 | } | |
727 | ||
728 | /* | |
729 | * Rules for using mmu_spte_clear_no_track: | |
730 | * Directly clear spte without caring the state bits of sptep, | |
731 | * it is used to set the upper level spte. | |
732 | */ | |
733 | static void mmu_spte_clear_no_track(u64 *sptep) | |
734 | { | |
603e0651 | 735 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
736 | } |
737 | ||
c2a2ac2b XG |
738 | static u64 mmu_spte_get_lockless(u64 *sptep) |
739 | { | |
740 | return __get_spte_lockless(sptep); | |
741 | } | |
742 | ||
f160c7b7 JS |
743 | static u64 mark_spte_for_access_track(u64 spte) |
744 | { | |
ac8d57e5 | 745 | if (spte_ad_enabled(spte)) |
f160c7b7 JS |
746 | return spte & ~shadow_accessed_mask; |
747 | ||
ac8d57e5 | 748 | if (is_access_track_spte(spte)) |
f160c7b7 JS |
749 | return spte; |
750 | ||
751 | /* | |
20d65236 JS |
752 | * Making an Access Tracking PTE will result in removal of write access |
753 | * from the PTE. So, verify that we will be able to restore the write | |
754 | * access in the fast page fault path later on. | |
f160c7b7 JS |
755 | */ |
756 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
757 | !spte_can_locklessly_be_made_writable(spte), | |
758 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
759 | ||
760 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
761 | shadow_acc_track_saved_bits_shift), | |
762 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
763 | ||
764 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
765 | shadow_acc_track_saved_bits_shift; | |
766 | spte &= ~shadow_acc_track_mask; | |
f160c7b7 JS |
767 | |
768 | return spte; | |
769 | } | |
770 | ||
d3e328f2 JS |
771 | /* Restore an acc-track PTE back to a regular PTE */ |
772 | static u64 restore_acc_track_spte(u64 spte) | |
773 | { | |
774 | u64 new_spte = spte; | |
775 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
776 | & shadow_acc_track_saved_bits_mask; | |
777 | ||
ac8d57e5 | 778 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
779 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
780 | ||
781 | new_spte &= ~shadow_acc_track_mask; | |
782 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
783 | shadow_acc_track_saved_bits_shift); | |
784 | new_spte |= saved_bits; | |
785 | ||
786 | return new_spte; | |
787 | } | |
788 | ||
f160c7b7 JS |
789 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
790 | static bool mmu_spte_age(u64 *sptep) | |
791 | { | |
792 | u64 spte = mmu_spte_get_lockless(sptep); | |
793 | ||
794 | if (!is_accessed_spte(spte)) | |
795 | return false; | |
796 | ||
ac8d57e5 | 797 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
798 | clear_bit((ffs(shadow_accessed_mask) - 1), |
799 | (unsigned long *)sptep); | |
800 | } else { | |
801 | /* | |
802 | * Capture the dirty status of the page, so that it doesn't get | |
803 | * lost when the SPTE is marked for access tracking. | |
804 | */ | |
805 | if (is_writable_pte(spte)) | |
806 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
807 | ||
808 | spte = mark_spte_for_access_track(spte); | |
809 | mmu_spte_update_no_track(sptep, spte); | |
810 | } | |
811 | ||
812 | return true; | |
813 | } | |
814 | ||
c2a2ac2b XG |
815 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
816 | { | |
c142786c AK |
817 | /* |
818 | * Prevent page table teardown by making any free-er wait during | |
819 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
820 | */ | |
821 | local_irq_disable(); | |
36ca7e0a | 822 | |
c142786c AK |
823 | /* |
824 | * Make sure a following spte read is not reordered ahead of the write | |
825 | * to vcpu->mode. | |
826 | */ | |
36ca7e0a | 827 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
828 | } |
829 | ||
830 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
831 | { | |
c142786c AK |
832 | /* |
833 | * Make sure the write to vcpu->mode is not reordered in front of | |
834 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
835 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
836 | */ | |
36ca7e0a | 837 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 838 | local_irq_enable(); |
c2a2ac2b XG |
839 | } |
840 | ||
e2dec939 | 841 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 842 | struct kmem_cache *base_cache, int min) |
714b93da AK |
843 | { |
844 | void *obj; | |
845 | ||
846 | if (cache->nobjs >= min) | |
e2dec939 | 847 | return 0; |
714b93da | 848 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 849 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 850 | if (!obj) |
e2dec939 | 851 | return -ENOMEM; |
714b93da AK |
852 | cache->objects[cache->nobjs++] = obj; |
853 | } | |
e2dec939 | 854 | return 0; |
714b93da AK |
855 | } |
856 | ||
f759e2b4 XG |
857 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
858 | { | |
859 | return cache->nobjs; | |
860 | } | |
861 | ||
e8ad9a70 XG |
862 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
863 | struct kmem_cache *cache) | |
714b93da AK |
864 | { |
865 | while (mc->nobjs) | |
e8ad9a70 | 866 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
867 | } |
868 | ||
c1158e63 | 869 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 870 | int min) |
c1158e63 | 871 | { |
842f22ed | 872 | void *page; |
c1158e63 AK |
873 | |
874 | if (cache->nobjs >= min) | |
875 | return 0; | |
876 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 877 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
878 | if (!page) |
879 | return -ENOMEM; | |
842f22ed | 880 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
881 | } |
882 | return 0; | |
883 | } | |
884 | ||
885 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
886 | { | |
887 | while (mc->nobjs) | |
c4d198d5 | 888 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
889 | } |
890 | ||
2e3e5882 | 891 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 892 | { |
e2dec939 AK |
893 | int r; |
894 | ||
53c07b18 | 895 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 896 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
897 | if (r) |
898 | goto out; | |
ad312c7c | 899 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
900 | if (r) |
901 | goto out; | |
ad312c7c | 902 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 903 | mmu_page_header_cache, 4); |
e2dec939 AK |
904 | out: |
905 | return r; | |
714b93da AK |
906 | } |
907 | ||
908 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
909 | { | |
53c07b18 XG |
910 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
911 | pte_list_desc_cache); | |
ad312c7c | 912 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
913 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
914 | mmu_page_header_cache); | |
714b93da AK |
915 | } |
916 | ||
80feb89a | 917 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
918 | { |
919 | void *p; | |
920 | ||
921 | BUG_ON(!mc->nobjs); | |
922 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
923 | return p; |
924 | } | |
925 | ||
53c07b18 | 926 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 927 | { |
80feb89a | 928 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
929 | } |
930 | ||
53c07b18 | 931 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 932 | { |
53c07b18 | 933 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
934 | } |
935 | ||
2032a93d LJ |
936 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
937 | { | |
938 | if (!sp->role.direct) | |
939 | return sp->gfns[index]; | |
940 | ||
941 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
942 | } | |
943 | ||
944 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
945 | { | |
946 | if (sp->role.direct) | |
947 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
948 | else | |
949 | sp->gfns[index] = gfn; | |
950 | } | |
951 | ||
05da4558 | 952 | /* |
d4dbf470 TY |
953 | * Return the pointer to the large page information for a given gfn, |
954 | * handling slots that are not large page aligned. | |
05da4558 | 955 | */ |
d4dbf470 TY |
956 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
957 | struct kvm_memory_slot *slot, | |
958 | int level) | |
05da4558 MT |
959 | { |
960 | unsigned long idx; | |
961 | ||
fb03cb6f | 962 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 963 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
964 | } |
965 | ||
547ffaed XG |
966 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
967 | gfn_t gfn, int count) | |
968 | { | |
969 | struct kvm_lpage_info *linfo; | |
970 | int i; | |
971 | ||
972 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
973 | linfo = lpage_info_slot(gfn, slot, i); | |
974 | linfo->disallow_lpage += count; | |
975 | WARN_ON(linfo->disallow_lpage < 0); | |
976 | } | |
977 | } | |
978 | ||
979 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
980 | { | |
981 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
982 | } | |
983 | ||
984 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
985 | { | |
986 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
987 | } | |
988 | ||
3ed1a478 | 989 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 990 | { |
699023e2 | 991 | struct kvm_memslots *slots; |
d25797b2 | 992 | struct kvm_memory_slot *slot; |
3ed1a478 | 993 | gfn_t gfn; |
05da4558 | 994 | |
56ca57f9 | 995 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 996 | gfn = sp->gfn; |
699023e2 PB |
997 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
998 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
999 | |
1000 | /* the non-leaf shadow pages are keeping readonly. */ | |
1001 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
1002 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
1003 | KVM_PAGE_TRACK_WRITE); | |
1004 | ||
547ffaed | 1005 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
1006 | } |
1007 | ||
3ed1a478 | 1008 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1009 | { |
699023e2 | 1010 | struct kvm_memslots *slots; |
d25797b2 | 1011 | struct kvm_memory_slot *slot; |
3ed1a478 | 1012 | gfn_t gfn; |
05da4558 | 1013 | |
56ca57f9 | 1014 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 1015 | gfn = sp->gfn; |
699023e2 PB |
1016 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1017 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1018 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
1019 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1020 | KVM_PAGE_TRACK_WRITE); | |
1021 | ||
547ffaed | 1022 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
1023 | } |
1024 | ||
92f94f1e XG |
1025 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
1026 | struct kvm_memory_slot *slot) | |
05da4558 | 1027 | { |
d4dbf470 | 1028 | struct kvm_lpage_info *linfo; |
05da4558 MT |
1029 | |
1030 | if (slot) { | |
d4dbf470 | 1031 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 1032 | return !!linfo->disallow_lpage; |
05da4558 MT |
1033 | } |
1034 | ||
92f94f1e | 1035 | return true; |
05da4558 MT |
1036 | } |
1037 | ||
92f94f1e XG |
1038 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
1039 | int level) | |
5225fdf8 TY |
1040 | { |
1041 | struct kvm_memory_slot *slot; | |
1042 | ||
1043 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 1044 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
1045 | } |
1046 | ||
d25797b2 | 1047 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 1048 | { |
8f0b1ab6 | 1049 | unsigned long page_size; |
d25797b2 | 1050 | int i, ret = 0; |
05da4558 | 1051 | |
8f0b1ab6 | 1052 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 1053 | |
8a3d08f1 | 1054 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
1055 | if (page_size >= KVM_HPAGE_SIZE(i)) |
1056 | ret = i; | |
1057 | else | |
1058 | break; | |
1059 | } | |
1060 | ||
4c2155ce | 1061 | return ret; |
05da4558 MT |
1062 | } |
1063 | ||
d8aacf5d TY |
1064 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
1065 | bool no_dirty_log) | |
1066 | { | |
1067 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
1068 | return false; | |
1069 | if (no_dirty_log && slot->dirty_bitmap) | |
1070 | return false; | |
1071 | ||
1072 | return true; | |
1073 | } | |
1074 | ||
5d163b1c XG |
1075 | static struct kvm_memory_slot * |
1076 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1077 | bool no_dirty_log) | |
05da4558 MT |
1078 | { |
1079 | struct kvm_memory_slot *slot; | |
5d163b1c | 1080 | |
54bf36aa | 1081 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 1082 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
1083 | slot = NULL; |
1084 | ||
1085 | return slot; | |
1086 | } | |
1087 | ||
fd136902 TY |
1088 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
1089 | bool *force_pt_level) | |
936a5fe6 AA |
1090 | { |
1091 | int host_level, level, max_level; | |
d8aacf5d TY |
1092 | struct kvm_memory_slot *slot; |
1093 | ||
8c85ac1c TY |
1094 | if (unlikely(*force_pt_level)) |
1095 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 1096 | |
8c85ac1c TY |
1097 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
1098 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
1099 | if (unlikely(*force_pt_level)) |
1100 | return PT_PAGE_TABLE_LEVEL; | |
1101 | ||
d25797b2 JR |
1102 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
1103 | ||
1104 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
1105 | return host_level; | |
1106 | ||
55dd98c3 | 1107 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
1108 | |
1109 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 1110 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 1111 | break; |
d25797b2 JR |
1112 | |
1113 | return level - 1; | |
05da4558 MT |
1114 | } |
1115 | ||
290fc38d | 1116 | /* |
018aabb5 | 1117 | * About rmap_head encoding: |
cd4a4e53 | 1118 | * |
018aabb5 TY |
1119 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1120 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1121 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1122 | */ |
1123 | ||
1124 | /* | |
1125 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1126 | */ |
53c07b18 | 1127 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1128 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1129 | { |
53c07b18 | 1130 | struct pte_list_desc *desc; |
53a27b39 | 1131 | int i, count = 0; |
cd4a4e53 | 1132 | |
018aabb5 | 1133 | if (!rmap_head->val) { |
53c07b18 | 1134 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1135 | rmap_head->val = (unsigned long)spte; |
1136 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1137 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1138 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1139 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1140 | desc->sptes[1] = spte; |
018aabb5 | 1141 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1142 | ++count; |
cd4a4e53 | 1143 | } else { |
53c07b18 | 1144 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1145 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1146 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1147 | desc = desc->more; |
53c07b18 | 1148 | count += PTE_LIST_EXT; |
53a27b39 | 1149 | } |
53c07b18 XG |
1150 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1151 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1152 | desc = desc->more; |
1153 | } | |
d555c333 | 1154 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1155 | ++count; |
d555c333 | 1156 | desc->sptes[i] = spte; |
cd4a4e53 | 1157 | } |
53a27b39 | 1158 | return count; |
cd4a4e53 AK |
1159 | } |
1160 | ||
53c07b18 | 1161 | static void |
018aabb5 TY |
1162 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1163 | struct pte_list_desc *desc, int i, | |
1164 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1165 | { |
1166 | int j; | |
1167 | ||
53c07b18 | 1168 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1169 | ; |
d555c333 AK |
1170 | desc->sptes[i] = desc->sptes[j]; |
1171 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1172 | if (j != 0) |
1173 | return; | |
1174 | if (!prev_desc && !desc->more) | |
018aabb5 | 1175 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
1176 | else |
1177 | if (prev_desc) | |
1178 | prev_desc->more = desc->more; | |
1179 | else | |
018aabb5 | 1180 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1181 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1182 | } |
1183 | ||
018aabb5 | 1184 | static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1185 | { |
53c07b18 XG |
1186 | struct pte_list_desc *desc; |
1187 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1188 | int i; |
1189 | ||
018aabb5 | 1190 | if (!rmap_head->val) { |
53c07b18 | 1191 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 1192 | BUG(); |
018aabb5 | 1193 | } else if (!(rmap_head->val & 1)) { |
53c07b18 | 1194 | rmap_printk("pte_list_remove: %p 1->0\n", spte); |
018aabb5 | 1195 | if ((u64 *)rmap_head->val != spte) { |
53c07b18 | 1196 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
1197 | BUG(); |
1198 | } | |
018aabb5 | 1199 | rmap_head->val = 0; |
cd4a4e53 | 1200 | } else { |
53c07b18 | 1201 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
018aabb5 | 1202 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1203 | prev_desc = NULL; |
1204 | while (desc) { | |
018aabb5 | 1205 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1206 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1207 | pte_list_desc_remove_entry(rmap_head, |
1208 | desc, i, prev_desc); | |
cd4a4e53 AK |
1209 | return; |
1210 | } | |
018aabb5 | 1211 | } |
cd4a4e53 AK |
1212 | prev_desc = desc; |
1213 | desc = desc->more; | |
1214 | } | |
53c07b18 | 1215 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1216 | BUG(); |
1217 | } | |
1218 | } | |
1219 | ||
018aabb5 TY |
1220 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1221 | struct kvm_memory_slot *slot) | |
53c07b18 | 1222 | { |
77d11309 | 1223 | unsigned long idx; |
53c07b18 | 1224 | |
77d11309 | 1225 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1226 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1227 | } |
1228 | ||
018aabb5 TY |
1229 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1230 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1231 | { |
699023e2 | 1232 | struct kvm_memslots *slots; |
9b9b1492 TY |
1233 | struct kvm_memory_slot *slot; |
1234 | ||
699023e2 PB |
1235 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1236 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1237 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1238 | } |
1239 | ||
f759e2b4 XG |
1240 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1241 | { | |
1242 | struct kvm_mmu_memory_cache *cache; | |
1243 | ||
1244 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1245 | return mmu_memory_cache_free_objects(cache); | |
1246 | } | |
1247 | ||
53c07b18 XG |
1248 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1249 | { | |
1250 | struct kvm_mmu_page *sp; | |
018aabb5 | 1251 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1252 | |
53c07b18 XG |
1253 | sp = page_header(__pa(spte)); |
1254 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1255 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1256 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1257 | } |
1258 | ||
53c07b18 XG |
1259 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1260 | { | |
1261 | struct kvm_mmu_page *sp; | |
1262 | gfn_t gfn; | |
018aabb5 | 1263 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1264 | |
1265 | sp = page_header(__pa(spte)); | |
1266 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 TY |
1267 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
1268 | pte_list_remove(spte, rmap_head); | |
53c07b18 XG |
1269 | } |
1270 | ||
1e3f42f0 TY |
1271 | /* |
1272 | * Used by the following functions to iterate through the sptes linked by a | |
1273 | * rmap. All fields are private and not assumed to be used outside. | |
1274 | */ | |
1275 | struct rmap_iterator { | |
1276 | /* private fields */ | |
1277 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1278 | int pos; /* index of the sptep */ | |
1279 | }; | |
1280 | ||
1281 | /* | |
1282 | * Iteration must be started by this function. This should also be used after | |
1283 | * removing/dropping sptes from the rmap link because in such cases the | |
1284 | * information in the itererator may not be valid. | |
1285 | * | |
1286 | * Returns sptep if found, NULL otherwise. | |
1287 | */ | |
018aabb5 TY |
1288 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1289 | struct rmap_iterator *iter) | |
1e3f42f0 | 1290 | { |
77fbbbd2 TY |
1291 | u64 *sptep; |
1292 | ||
018aabb5 | 1293 | if (!rmap_head->val) |
1e3f42f0 TY |
1294 | return NULL; |
1295 | ||
018aabb5 | 1296 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1297 | iter->desc = NULL; |
77fbbbd2 TY |
1298 | sptep = (u64 *)rmap_head->val; |
1299 | goto out; | |
1e3f42f0 TY |
1300 | } |
1301 | ||
018aabb5 | 1302 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1303 | iter->pos = 0; |
77fbbbd2 TY |
1304 | sptep = iter->desc->sptes[iter->pos]; |
1305 | out: | |
1306 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1307 | return sptep; | |
1e3f42f0 TY |
1308 | } |
1309 | ||
1310 | /* | |
1311 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1312 | * | |
1313 | * Returns sptep if found, NULL otherwise. | |
1314 | */ | |
1315 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1316 | { | |
77fbbbd2 TY |
1317 | u64 *sptep; |
1318 | ||
1e3f42f0 TY |
1319 | if (iter->desc) { |
1320 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1321 | ++iter->pos; |
1322 | sptep = iter->desc->sptes[iter->pos]; | |
1323 | if (sptep) | |
77fbbbd2 | 1324 | goto out; |
1e3f42f0 TY |
1325 | } |
1326 | ||
1327 | iter->desc = iter->desc->more; | |
1328 | ||
1329 | if (iter->desc) { | |
1330 | iter->pos = 0; | |
1331 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1332 | sptep = iter->desc->sptes[iter->pos]; |
1333 | goto out; | |
1e3f42f0 TY |
1334 | } |
1335 | } | |
1336 | ||
1337 | return NULL; | |
77fbbbd2 TY |
1338 | out: |
1339 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1340 | return sptep; | |
1e3f42f0 TY |
1341 | } |
1342 | ||
018aabb5 TY |
1343 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1344 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1345 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1346 | |
c3707958 | 1347 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1348 | { |
1df9f2dc | 1349 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1350 | rmap_remove(kvm, sptep); |
be38d276 AK |
1351 | } |
1352 | ||
8e22f955 XG |
1353 | |
1354 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1355 | { | |
1356 | if (is_large_pte(*sptep)) { | |
1357 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1358 | PT_PAGE_TABLE_LEVEL); | |
1359 | drop_spte(kvm, sptep); | |
1360 | --kvm->stat.lpages; | |
1361 | return true; | |
1362 | } | |
1363 | ||
1364 | return false; | |
1365 | } | |
1366 | ||
1367 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1368 | { | |
1369 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1370 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1371 | } | |
1372 | ||
1373 | /* | |
49fde340 | 1374 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1375 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1376 | * |
b4619660 | 1377 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1378 | * protection: |
1379 | * - for dirty logging, the spte can be set to writable at anytime if | |
1380 | * its dirty bitmap is properly set. | |
1381 | * - for spte protection, the spte can be writable only after unsync-ing | |
1382 | * shadow page. | |
8e22f955 | 1383 | * |
c126d94f | 1384 | * Return true if tlb need be flushed. |
8e22f955 | 1385 | */ |
c4f138b4 | 1386 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1387 | { |
1388 | u64 spte = *sptep; | |
1389 | ||
49fde340 | 1390 | if (!is_writable_pte(spte) && |
ea4114bc | 1391 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1392 | return false; |
1393 | ||
1394 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1395 | ||
49fde340 XG |
1396 | if (pt_protect) |
1397 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1398 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1399 | |
c126d94f | 1400 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1401 | } |
1402 | ||
018aabb5 TY |
1403 | static bool __rmap_write_protect(struct kvm *kvm, |
1404 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1405 | bool pt_protect) |
98348e95 | 1406 | { |
1e3f42f0 TY |
1407 | u64 *sptep; |
1408 | struct rmap_iterator iter; | |
d13bc5b5 | 1409 | bool flush = false; |
374cbac0 | 1410 | |
018aabb5 | 1411 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1412 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1413 | |
d13bc5b5 | 1414 | return flush; |
a0ed4607 TY |
1415 | } |
1416 | ||
c4f138b4 | 1417 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1418 | { |
1419 | u64 spte = *sptep; | |
1420 | ||
1421 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1422 | ||
1423 | spte &= ~shadow_dirty_mask; | |
1424 | ||
1425 | return mmu_spte_update(sptep, spte); | |
1426 | } | |
1427 | ||
ac8d57e5 PF |
1428 | static bool wrprot_ad_disabled_spte(u64 *sptep) |
1429 | { | |
1430 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1431 | (unsigned long *)sptep); | |
1432 | if (was_writable) | |
1433 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); | |
1434 | ||
1435 | return was_writable; | |
1436 | } | |
1437 | ||
1438 | /* | |
1439 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1440 | * - D bit on ad-enabled SPTEs, and | |
1441 | * - W bit on ad-disabled SPTEs. | |
1442 | * Returns true iff any D or W bits were cleared. | |
1443 | */ | |
018aabb5 | 1444 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1445 | { |
1446 | u64 *sptep; | |
1447 | struct rmap_iterator iter; | |
1448 | bool flush = false; | |
1449 | ||
018aabb5 | 1450 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1451 | if (spte_ad_enabled(*sptep)) |
1452 | flush |= spte_clear_dirty(sptep); | |
1453 | else | |
1454 | flush |= wrprot_ad_disabled_spte(sptep); | |
f4b4b180 KH |
1455 | |
1456 | return flush; | |
1457 | } | |
1458 | ||
c4f138b4 | 1459 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1460 | { |
1461 | u64 spte = *sptep; | |
1462 | ||
1463 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1464 | ||
1465 | spte |= shadow_dirty_mask; | |
1466 | ||
1467 | return mmu_spte_update(sptep, spte); | |
1468 | } | |
1469 | ||
018aabb5 | 1470 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1471 | { |
1472 | u64 *sptep; | |
1473 | struct rmap_iterator iter; | |
1474 | bool flush = false; | |
1475 | ||
018aabb5 | 1476 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1477 | if (spte_ad_enabled(*sptep)) |
1478 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1479 | |
1480 | return flush; | |
1481 | } | |
1482 | ||
5dc99b23 | 1483 | /** |
3b0f1d01 | 1484 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1485 | * @kvm: kvm instance |
1486 | * @slot: slot to protect | |
1487 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1488 | * @mask: indicates which pages we should protect | |
1489 | * | |
1490 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1491 | * logging we do not have any such mappings. | |
1492 | */ | |
3b0f1d01 | 1493 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1494 | struct kvm_memory_slot *slot, |
1495 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1496 | { |
018aabb5 | 1497 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1498 | |
5dc99b23 | 1499 | while (mask) { |
018aabb5 TY |
1500 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1501 | PT_PAGE_TABLE_LEVEL, slot); | |
1502 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1503 | |
5dc99b23 TY |
1504 | /* clear the first set bit */ |
1505 | mask &= mask - 1; | |
1506 | } | |
374cbac0 AK |
1507 | } |
1508 | ||
f4b4b180 | 1509 | /** |
ac8d57e5 PF |
1510 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1511 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1512 | * @kvm: kvm instance |
1513 | * @slot: slot to clear D-bit | |
1514 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1515 | * @mask: indicates which pages we should clear D-bit | |
1516 | * | |
1517 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1518 | */ | |
1519 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1520 | struct kvm_memory_slot *slot, | |
1521 | gfn_t gfn_offset, unsigned long mask) | |
1522 | { | |
018aabb5 | 1523 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1524 | |
1525 | while (mask) { | |
018aabb5 TY |
1526 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1527 | PT_PAGE_TABLE_LEVEL, slot); | |
1528 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1529 | |
1530 | /* clear the first set bit */ | |
1531 | mask &= mask - 1; | |
1532 | } | |
1533 | } | |
1534 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1535 | ||
3b0f1d01 KH |
1536 | /** |
1537 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1538 | * PT level pages. | |
1539 | * | |
1540 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1541 | * enable dirty logging for them. | |
1542 | * | |
1543 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1544 | * logging we do not have any such mappings. | |
1545 | */ | |
1546 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1547 | struct kvm_memory_slot *slot, | |
1548 | gfn_t gfn_offset, unsigned long mask) | |
1549 | { | |
88178fd4 KH |
1550 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1551 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1552 | mask); | |
1553 | else | |
1554 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1555 | } |
1556 | ||
bab4165e BD |
1557 | /** |
1558 | * kvm_arch_write_log_dirty - emulate dirty page logging | |
1559 | * @vcpu: Guest mode vcpu | |
1560 | * | |
1561 | * Emulate arch specific page modification logging for the | |
1562 | * nested hypervisor | |
1563 | */ | |
1564 | int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu) | |
1565 | { | |
1566 | if (kvm_x86_ops->write_log_dirty) | |
1567 | return kvm_x86_ops->write_log_dirty(vcpu); | |
1568 | ||
1569 | return 0; | |
1570 | } | |
1571 | ||
aeecee2e XG |
1572 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1573 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1574 | { |
018aabb5 | 1575 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1576 | int i; |
2f84569f | 1577 | bool write_protected = false; |
95d4c16c | 1578 | |
8a3d08f1 | 1579 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1580 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1581 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1582 | } |
1583 | ||
1584 | return write_protected; | |
95d4c16c TY |
1585 | } |
1586 | ||
aeecee2e XG |
1587 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1588 | { | |
1589 | struct kvm_memory_slot *slot; | |
1590 | ||
1591 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1592 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1593 | } | |
1594 | ||
018aabb5 | 1595 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1596 | { |
1e3f42f0 TY |
1597 | u64 *sptep; |
1598 | struct rmap_iterator iter; | |
6a49f85c | 1599 | bool flush = false; |
e930bffe | 1600 | |
018aabb5 | 1601 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1602 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 TY |
1603 | |
1604 | drop_spte(kvm, sptep); | |
6a49f85c | 1605 | flush = true; |
e930bffe | 1606 | } |
1e3f42f0 | 1607 | |
6a49f85c XG |
1608 | return flush; |
1609 | } | |
1610 | ||
018aabb5 | 1611 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1612 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1613 | unsigned long data) | |
1614 | { | |
018aabb5 | 1615 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1616 | } |
1617 | ||
018aabb5 | 1618 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1619 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1620 | unsigned long data) | |
3da0dd43 | 1621 | { |
1e3f42f0 TY |
1622 | u64 *sptep; |
1623 | struct rmap_iterator iter; | |
3da0dd43 | 1624 | int need_flush = 0; |
1e3f42f0 | 1625 | u64 new_spte; |
3da0dd43 | 1626 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1627 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1628 | |
1629 | WARN_ON(pte_huge(*ptep)); | |
1630 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1631 | |
0d536790 | 1632 | restart: |
018aabb5 | 1633 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1634 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1635 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1636 | |
3da0dd43 | 1637 | need_flush = 1; |
1e3f42f0 | 1638 | |
3da0dd43 | 1639 | if (pte_write(*ptep)) { |
1e3f42f0 | 1640 | drop_spte(kvm, sptep); |
0d536790 | 1641 | goto restart; |
3da0dd43 | 1642 | } else { |
1e3f42f0 | 1643 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1644 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1645 | ||
1646 | new_spte &= ~PT_WRITABLE_MASK; | |
1647 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1648 | |
1649 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1650 | |
1651 | mmu_spte_clear_track_bits(sptep); | |
1652 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1653 | } |
1654 | } | |
1e3f42f0 | 1655 | |
3da0dd43 IE |
1656 | if (need_flush) |
1657 | kvm_flush_remote_tlbs(kvm); | |
1658 | ||
1659 | return 0; | |
1660 | } | |
1661 | ||
6ce1f4e2 XG |
1662 | struct slot_rmap_walk_iterator { |
1663 | /* input fields. */ | |
1664 | struct kvm_memory_slot *slot; | |
1665 | gfn_t start_gfn; | |
1666 | gfn_t end_gfn; | |
1667 | int start_level; | |
1668 | int end_level; | |
1669 | ||
1670 | /* output fields. */ | |
1671 | gfn_t gfn; | |
018aabb5 | 1672 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1673 | int level; |
1674 | ||
1675 | /* private field. */ | |
018aabb5 | 1676 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1677 | }; |
1678 | ||
1679 | static void | |
1680 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1681 | { | |
1682 | iterator->level = level; | |
1683 | iterator->gfn = iterator->start_gfn; | |
1684 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1685 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1686 | iterator->slot); | |
1687 | } | |
1688 | ||
1689 | static void | |
1690 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1691 | struct kvm_memory_slot *slot, int start_level, | |
1692 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1693 | { | |
1694 | iterator->slot = slot; | |
1695 | iterator->start_level = start_level; | |
1696 | iterator->end_level = end_level; | |
1697 | iterator->start_gfn = start_gfn; | |
1698 | iterator->end_gfn = end_gfn; | |
1699 | ||
1700 | rmap_walk_init_level(iterator, iterator->start_level); | |
1701 | } | |
1702 | ||
1703 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1704 | { | |
1705 | return !!iterator->rmap; | |
1706 | } | |
1707 | ||
1708 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1709 | { | |
1710 | if (++iterator->rmap <= iterator->end_rmap) { | |
1711 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1712 | return; | |
1713 | } | |
1714 | ||
1715 | if (++iterator->level > iterator->end_level) { | |
1716 | iterator->rmap = NULL; | |
1717 | return; | |
1718 | } | |
1719 | ||
1720 | rmap_walk_init_level(iterator, iterator->level); | |
1721 | } | |
1722 | ||
1723 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1724 | _start_gfn, _end_gfn, _iter_) \ | |
1725 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1726 | _end_level_, _start_gfn, _end_gfn); \ | |
1727 | slot_rmap_walk_okay(_iter_); \ | |
1728 | slot_rmap_walk_next(_iter_)) | |
1729 | ||
84504ef3 TY |
1730 | static int kvm_handle_hva_range(struct kvm *kvm, |
1731 | unsigned long start, | |
1732 | unsigned long end, | |
1733 | unsigned long data, | |
1734 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1735 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1736 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1737 | gfn_t gfn, |
1738 | int level, | |
84504ef3 | 1739 | unsigned long data)) |
e930bffe | 1740 | { |
bc6678a3 | 1741 | struct kvm_memslots *slots; |
be6ba0f0 | 1742 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1743 | struct slot_rmap_walk_iterator iterator; |
1744 | int ret = 0; | |
9da0e4d5 | 1745 | int i; |
bc6678a3 | 1746 | |
9da0e4d5 PB |
1747 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1748 | slots = __kvm_memslots(kvm, i); | |
1749 | kvm_for_each_memslot(memslot, slots) { | |
1750 | unsigned long hva_start, hva_end; | |
1751 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1752 | |
9da0e4d5 PB |
1753 | hva_start = max(start, memslot->userspace_addr); |
1754 | hva_end = min(end, memslot->userspace_addr + | |
1755 | (memslot->npages << PAGE_SHIFT)); | |
1756 | if (hva_start >= hva_end) | |
1757 | continue; | |
1758 | /* | |
1759 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1760 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1761 | */ | |
1762 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1763 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1764 | ||
1765 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1766 | PT_MAX_HUGEPAGE_LEVEL, | |
1767 | gfn_start, gfn_end - 1, | |
1768 | &iterator) | |
1769 | ret |= handler(kvm, iterator.rmap, memslot, | |
1770 | iterator.gfn, iterator.level, data); | |
1771 | } | |
e930bffe AA |
1772 | } |
1773 | ||
f395302e | 1774 | return ret; |
e930bffe AA |
1775 | } |
1776 | ||
84504ef3 TY |
1777 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1778 | unsigned long data, | |
018aabb5 TY |
1779 | int (*handler)(struct kvm *kvm, |
1780 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1781 | struct kvm_memory_slot *slot, |
8a9522d2 | 1782 | gfn_t gfn, int level, |
84504ef3 TY |
1783 | unsigned long data)) |
1784 | { | |
1785 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1786 | } |
1787 | ||
1788 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1789 | { | |
3da0dd43 IE |
1790 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1791 | } | |
1792 | ||
b3ae2096 TY |
1793 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1794 | { | |
1795 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1796 | } | |
1797 | ||
3da0dd43 IE |
1798 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1799 | { | |
8a8365c5 | 1800 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1801 | } |
1802 | ||
018aabb5 | 1803 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1804 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1805 | unsigned long data) | |
e930bffe | 1806 | { |
1e3f42f0 | 1807 | u64 *sptep; |
79f702a6 | 1808 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1809 | int young = 0; |
1810 | ||
f160c7b7 JS |
1811 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1812 | young |= mmu_spte_age(sptep); | |
0d536790 | 1813 | |
8a9522d2 | 1814 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1815 | return young; |
1816 | } | |
1817 | ||
018aabb5 | 1818 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1819 | struct kvm_memory_slot *slot, gfn_t gfn, |
1820 | int level, unsigned long data) | |
8ee53820 | 1821 | { |
1e3f42f0 TY |
1822 | u64 *sptep; |
1823 | struct rmap_iterator iter; | |
8ee53820 | 1824 | |
83ef6c81 JS |
1825 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1826 | if (is_accessed_spte(*sptep)) | |
1827 | return 1; | |
83ef6c81 | 1828 | return 0; |
8ee53820 AA |
1829 | } |
1830 | ||
53a27b39 MT |
1831 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1832 | ||
852e3c19 | 1833 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1834 | { |
018aabb5 | 1835 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1836 | struct kvm_mmu_page *sp; |
1837 | ||
1838 | sp = page_header(__pa(spte)); | |
53a27b39 | 1839 | |
018aabb5 | 1840 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1841 | |
018aabb5 | 1842 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
53a27b39 MT |
1843 | kvm_flush_remote_tlbs(vcpu->kvm); |
1844 | } | |
1845 | ||
57128468 | 1846 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1847 | { |
57128468 | 1848 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
1849 | } |
1850 | ||
8ee53820 AA |
1851 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1852 | { | |
1853 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1854 | } | |
1855 | ||
d6c69ee9 | 1856 | #ifdef MMU_DEBUG |
47ad8e68 | 1857 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1858 | { |
139bdb2d AK |
1859 | u64 *pos; |
1860 | u64 *end; | |
1861 | ||
47ad8e68 | 1862 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1863 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1864 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1865 | pos, *pos); |
6aa8b732 | 1866 | return 0; |
139bdb2d | 1867 | } |
6aa8b732 AK |
1868 | return 1; |
1869 | } | |
d6c69ee9 | 1870 | #endif |
6aa8b732 | 1871 | |
45221ab6 DH |
1872 | /* |
1873 | * This value is the sum of all of the kvm instances's | |
1874 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1875 | * aggregate version in order to make the slab shrinker | |
1876 | * faster | |
1877 | */ | |
1878 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1879 | { | |
1880 | kvm->arch.n_used_mmu_pages += nr; | |
1881 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1882 | } | |
1883 | ||
834be0d8 | 1884 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1885 | { |
fa4a2c08 | 1886 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1887 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1888 | list_del(&sp->link); |
1889 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1890 | if (!sp->role.direct) |
1891 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1892 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1893 | } |
1894 | ||
cea0f0e7 AK |
1895 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1896 | { | |
114df303 | 1897 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1898 | } |
1899 | ||
714b93da | 1900 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1901 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1902 | { |
cea0f0e7 AK |
1903 | if (!parent_pte) |
1904 | return; | |
cea0f0e7 | 1905 | |
67052b35 | 1906 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1907 | } |
1908 | ||
4db35314 | 1909 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1910 | u64 *parent_pte) |
1911 | { | |
67052b35 | 1912 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1913 | } |
1914 | ||
bcdd9a93 XG |
1915 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1916 | u64 *parent_pte) | |
1917 | { | |
1918 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1919 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1920 | } |
1921 | ||
47005792 | 1922 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1923 | { |
67052b35 | 1924 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1925 | |
80feb89a TY |
1926 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1927 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1928 | if (!direct) |
80feb89a | 1929 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1930 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1931 | |
1932 | /* | |
1933 | * The active_mmu_pages list is the FIFO list, do not move the | |
1934 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1935 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1936 | */ | |
67052b35 | 1937 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1938 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1939 | return sp; | |
ad8cfbe3 MT |
1940 | } |
1941 | ||
67052b35 | 1942 | static void mark_unsync(u64 *spte); |
1047df1f | 1943 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1944 | { |
74c4e63a TY |
1945 | u64 *sptep; |
1946 | struct rmap_iterator iter; | |
1947 | ||
1948 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1949 | mark_unsync(sptep); | |
1950 | } | |
0074ff63 MT |
1951 | } |
1952 | ||
67052b35 | 1953 | static void mark_unsync(u64 *spte) |
0074ff63 | 1954 | { |
67052b35 | 1955 | struct kvm_mmu_page *sp; |
1047df1f | 1956 | unsigned int index; |
0074ff63 | 1957 | |
67052b35 | 1958 | sp = page_header(__pa(spte)); |
1047df1f XG |
1959 | index = spte - sp->spt; |
1960 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1961 | return; |
1047df1f | 1962 | if (sp->unsync_children++) |
0074ff63 | 1963 | return; |
1047df1f | 1964 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1965 | } |
1966 | ||
e8bc217a | 1967 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1968 | struct kvm_mmu_page *sp) |
e8bc217a | 1969 | { |
1f50f1b3 | 1970 | return 0; |
e8bc217a MT |
1971 | } |
1972 | ||
a7052897 MT |
1973 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1974 | { | |
1975 | } | |
1976 | ||
0f53b5b1 XG |
1977 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1978 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1979 | const void *pte) |
0f53b5b1 XG |
1980 | { |
1981 | WARN_ON(1); | |
1982 | } | |
1983 | ||
60c8aec6 MT |
1984 | #define KVM_PAGE_ARRAY_NR 16 |
1985 | ||
1986 | struct kvm_mmu_pages { | |
1987 | struct mmu_page_and_offset { | |
1988 | struct kvm_mmu_page *sp; | |
1989 | unsigned int idx; | |
1990 | } page[KVM_PAGE_ARRAY_NR]; | |
1991 | unsigned int nr; | |
1992 | }; | |
1993 | ||
cded19f3 HE |
1994 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1995 | int idx) | |
4731d4c7 | 1996 | { |
60c8aec6 | 1997 | int i; |
4731d4c7 | 1998 | |
60c8aec6 MT |
1999 | if (sp->unsync) |
2000 | for (i=0; i < pvec->nr; i++) | |
2001 | if (pvec->page[i].sp == sp) | |
2002 | return 0; | |
2003 | ||
2004 | pvec->page[pvec->nr].sp = sp; | |
2005 | pvec->page[pvec->nr].idx = idx; | |
2006 | pvec->nr++; | |
2007 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
2008 | } | |
2009 | ||
fd951457 TY |
2010 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
2011 | { | |
2012 | --sp->unsync_children; | |
2013 | WARN_ON((int)sp->unsync_children < 0); | |
2014 | __clear_bit(idx, sp->unsync_child_bitmap); | |
2015 | } | |
2016 | ||
60c8aec6 MT |
2017 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
2018 | struct kvm_mmu_pages *pvec) | |
2019 | { | |
2020 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 2021 | |
37178b8b | 2022 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 2023 | struct kvm_mmu_page *child; |
4731d4c7 MT |
2024 | u64 ent = sp->spt[i]; |
2025 | ||
fd951457 TY |
2026 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
2027 | clear_unsync_child_bit(sp, i); | |
2028 | continue; | |
2029 | } | |
7a8f1a74 XG |
2030 | |
2031 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
2032 | ||
2033 | if (child->unsync_children) { | |
2034 | if (mmu_pages_add(pvec, child, i)) | |
2035 | return -ENOSPC; | |
2036 | ||
2037 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
2038 | if (!ret) { |
2039 | clear_unsync_child_bit(sp, i); | |
2040 | continue; | |
2041 | } else if (ret > 0) { | |
7a8f1a74 | 2042 | nr_unsync_leaf += ret; |
fd951457 | 2043 | } else |
7a8f1a74 XG |
2044 | return ret; |
2045 | } else if (child->unsync) { | |
2046 | nr_unsync_leaf++; | |
2047 | if (mmu_pages_add(pvec, child, i)) | |
2048 | return -ENOSPC; | |
2049 | } else | |
fd951457 | 2050 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2051 | } |
2052 | ||
60c8aec6 MT |
2053 | return nr_unsync_leaf; |
2054 | } | |
2055 | ||
e23d3fef XG |
2056 | #define INVALID_INDEX (-1) |
2057 | ||
60c8aec6 MT |
2058 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2059 | struct kvm_mmu_pages *pvec) | |
2060 | { | |
0a47cd85 | 2061 | pvec->nr = 0; |
60c8aec6 MT |
2062 | if (!sp->unsync_children) |
2063 | return 0; | |
2064 | ||
e23d3fef | 2065 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2066 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2067 | } |
2068 | ||
4731d4c7 MT |
2069 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2070 | { | |
2071 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2072 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2073 | sp->unsync = 0; |
2074 | --kvm->stat.mmu_unsync; | |
2075 | } | |
2076 | ||
7775834a XG |
2077 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2078 | struct list_head *invalid_list); | |
2079 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
2080 | struct list_head *invalid_list); | |
4731d4c7 | 2081 | |
f34d251d XG |
2082 | /* |
2083 | * NOTE: we should pay more attention on the zapped-obsolete page | |
2084 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
2085 | * since it has been deleted from active_mmu_pages but still can be found | |
2086 | * at hast list. | |
2087 | * | |
f3414bc7 | 2088 | * for_each_valid_sp() has skipped that kind of pages. |
f34d251d | 2089 | */ |
f3414bc7 | 2090 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2091 | hlist_for_each_entry(_sp, \ |
2092 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
f3414bc7 DM |
2093 | if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \ |
2094 | } else | |
1044b030 TY |
2095 | |
2096 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2097 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2098 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2099 | |
f918b443 | 2100 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2101 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2102 | struct list_head *invalid_list) | |
4731d4c7 | 2103 | { |
5b7e0102 | 2104 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 2105 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2106 | return false; |
4731d4c7 MT |
2107 | } |
2108 | ||
1f50f1b3 | 2109 | if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) { |
d98ba053 | 2110 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2111 | return false; |
4731d4c7 MT |
2112 | } |
2113 | ||
1f50f1b3 | 2114 | return true; |
4731d4c7 MT |
2115 | } |
2116 | ||
35a70510 PB |
2117 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2118 | struct list_head *invalid_list, | |
2119 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2120 | { |
35a70510 PB |
2121 | if (!list_empty(invalid_list)) { |
2122 | kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list); | |
2123 | return; | |
2124 | } | |
d98ba053 | 2125 | |
35a70510 PB |
2126 | if (remote_flush) |
2127 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2128 | else if (local_flush) | |
2129 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
1d9dc7e0 XG |
2130 | } |
2131 | ||
e37fa785 XG |
2132 | #ifdef CONFIG_KVM_MMU_AUDIT |
2133 | #include "mmu_audit.c" | |
2134 | #else | |
2135 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2136 | static void mmu_audit_disable(void) { } | |
2137 | #endif | |
2138 | ||
46971a2f XG |
2139 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2140 | { | |
2141 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2142 | } | |
2143 | ||
1f50f1b3 | 2144 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2145 | struct list_head *invalid_list) |
1d9dc7e0 | 2146 | { |
9a43c5d9 PB |
2147 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2148 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2149 | } |
2150 | ||
9f1a122f | 2151 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2152 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2153 | struct list_head *invalid_list) | |
9f1a122f | 2154 | { |
9f1a122f | 2155 | struct kvm_mmu_page *s; |
2a74003a | 2156 | bool ret = false; |
9f1a122f | 2157 | |
b67bfe0d | 2158 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2159 | if (!s->unsync) |
9f1a122f XG |
2160 | continue; |
2161 | ||
2162 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2163 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2164 | } |
2165 | ||
2a74003a | 2166 | return ret; |
9f1a122f XG |
2167 | } |
2168 | ||
60c8aec6 | 2169 | struct mmu_page_path { |
0a47cd85 PB |
2170 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL]; |
2171 | unsigned int idx[PT64_ROOT_LEVEL]; | |
4731d4c7 MT |
2172 | }; |
2173 | ||
60c8aec6 | 2174 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2175 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2176 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2177 | i = mmu_pages_next(&pvec, &parents, i)) | |
2178 | ||
cded19f3 HE |
2179 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2180 | struct mmu_page_path *parents, | |
2181 | int i) | |
60c8aec6 MT |
2182 | { |
2183 | int n; | |
2184 | ||
2185 | for (n = i+1; n < pvec->nr; n++) { | |
2186 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2187 | unsigned idx = pvec->page[n].idx; |
2188 | int level = sp->role.level; | |
60c8aec6 | 2189 | |
0a47cd85 PB |
2190 | parents->idx[level-1] = idx; |
2191 | if (level == PT_PAGE_TABLE_LEVEL) | |
2192 | break; | |
60c8aec6 | 2193 | |
0a47cd85 | 2194 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2195 | } |
2196 | ||
2197 | return n; | |
2198 | } | |
2199 | ||
0a47cd85 PB |
2200 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2201 | struct mmu_page_path *parents) | |
2202 | { | |
2203 | struct kvm_mmu_page *sp; | |
2204 | int level; | |
2205 | ||
2206 | if (pvec->nr == 0) | |
2207 | return 0; | |
2208 | ||
e23d3fef XG |
2209 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2210 | ||
0a47cd85 PB |
2211 | sp = pvec->page[0].sp; |
2212 | level = sp->role.level; | |
2213 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2214 | ||
2215 | parents->parent[level-2] = sp; | |
2216 | ||
2217 | /* Also set up a sentinel. Further entries in pvec are all | |
2218 | * children of sp, so this element is never overwritten. | |
2219 | */ | |
2220 | parents->parent[level-1] = NULL; | |
2221 | return mmu_pages_next(pvec, parents, 0); | |
2222 | } | |
2223 | ||
cded19f3 | 2224 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2225 | { |
60c8aec6 MT |
2226 | struct kvm_mmu_page *sp; |
2227 | unsigned int level = 0; | |
2228 | ||
2229 | do { | |
2230 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2231 | sp = parents->parent[level]; |
2232 | if (!sp) | |
2233 | return; | |
2234 | ||
e23d3fef | 2235 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2236 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2237 | level++; |
0a47cd85 | 2238 | } while (!sp->unsync_children); |
60c8aec6 | 2239 | } |
4731d4c7 | 2240 | |
60c8aec6 MT |
2241 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2242 | struct kvm_mmu_page *parent) | |
2243 | { | |
2244 | int i; | |
2245 | struct kvm_mmu_page *sp; | |
2246 | struct mmu_page_path parents; | |
2247 | struct kvm_mmu_pages pages; | |
d98ba053 | 2248 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2249 | bool flush = false; |
60c8aec6 | 2250 | |
60c8aec6 | 2251 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2252 | bool protected = false; |
b1a36821 MT |
2253 | |
2254 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2255 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2256 | |
50c9e6f3 | 2257 | if (protected) { |
b1a36821 | 2258 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2259 | flush = false; |
2260 | } | |
b1a36821 | 2261 | |
60c8aec6 | 2262 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2263 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2264 | mmu_pages_clear_parents(&parents); |
2265 | } | |
50c9e6f3 PB |
2266 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2267 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2268 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2269 | flush = false; | |
2270 | } | |
60c8aec6 | 2271 | } |
50c9e6f3 PB |
2272 | |
2273 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2274 | } |
2275 | ||
a30f47cb XG |
2276 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2277 | { | |
e5691a81 | 2278 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2279 | } |
2280 | ||
2281 | static void clear_sp_write_flooding_count(u64 *spte) | |
2282 | { | |
2283 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2284 | ||
2285 | __clear_sp_write_flooding_count(sp); | |
2286 | } | |
2287 | ||
cea0f0e7 AK |
2288 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2289 | gfn_t gfn, | |
2290 | gva_t gaddr, | |
2291 | unsigned level, | |
f6e2c02b | 2292 | int direct, |
bb11c6c9 | 2293 | unsigned access) |
cea0f0e7 AK |
2294 | { |
2295 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2296 | unsigned quadrant; |
9f1a122f | 2297 | struct kvm_mmu_page *sp; |
9f1a122f | 2298 | bool need_sync = false; |
2a74003a | 2299 | bool flush = false; |
f3414bc7 | 2300 | int collisions = 0; |
2a74003a | 2301 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2302 | |
a770f6f2 | 2303 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 2304 | role.level = level; |
f6e2c02b | 2305 | role.direct = direct; |
84b0c8c6 | 2306 | if (role.direct) |
5b7e0102 | 2307 | role.cr4_pae = 0; |
41074d07 | 2308 | role.access = access; |
c5a78f2b JR |
2309 | if (!vcpu->arch.mmu.direct_map |
2310 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2311 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2312 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2313 | role.quadrant = quadrant; | |
2314 | } | |
f3414bc7 DM |
2315 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2316 | if (sp->gfn != gfn) { | |
2317 | collisions++; | |
2318 | continue; | |
2319 | } | |
2320 | ||
7ae680eb XG |
2321 | if (!need_sync && sp->unsync) |
2322 | need_sync = true; | |
4731d4c7 | 2323 | |
7ae680eb XG |
2324 | if (sp->role.word != role.word) |
2325 | continue; | |
4731d4c7 | 2326 | |
2a74003a PB |
2327 | if (sp->unsync) { |
2328 | /* The page is good, but __kvm_sync_page might still end | |
2329 | * up zapping it. If so, break in order to rebuild it. | |
2330 | */ | |
2331 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2332 | break; | |
2333 | ||
2334 | WARN_ON(!list_empty(&invalid_list)); | |
2335 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2336 | } | |
e02aa901 | 2337 | |
98bba238 | 2338 | if (sp->unsync_children) |
a8eeb04a | 2339 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2340 | |
a30f47cb | 2341 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2342 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2343 | goto out; |
7ae680eb | 2344 | } |
47005792 | 2345 | |
dfc5aa00 | 2346 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2347 | |
2348 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2349 | ||
4db35314 AK |
2350 | sp->gfn = gfn; |
2351 | sp->role = role; | |
7ae680eb XG |
2352 | hlist_add_head(&sp->hash_link, |
2353 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2354 | if (!direct) { |
56ca57f9 XG |
2355 | /* |
2356 | * we should do write protection before syncing pages | |
2357 | * otherwise the content of the synced shadow page may | |
2358 | * be inconsistent with guest page table. | |
2359 | */ | |
2360 | account_shadowed(vcpu->kvm, sp); | |
2361 | if (level == PT_PAGE_TABLE_LEVEL && | |
2362 | rmap_write_protect(vcpu, gfn)) | |
b1a36821 | 2363 | kvm_flush_remote_tlbs(vcpu->kvm); |
9f1a122f | 2364 | |
9f1a122f | 2365 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2366 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2367 | } |
5304b8d3 | 2368 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2369 | clear_page(sp->spt); |
f691fe1d | 2370 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2371 | |
2372 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2373 | out: |
2374 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2375 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2376 | return sp; |
cea0f0e7 AK |
2377 | } |
2378 | ||
2d11123a AK |
2379 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2380 | struct kvm_vcpu *vcpu, u64 addr) | |
2381 | { | |
2382 | iterator->addr = addr; | |
2383 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
2384 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
2385 | |
2386 | if (iterator->level == PT64_ROOT_LEVEL && | |
2387 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
2388 | !vcpu->arch.mmu.direct_map) | |
2389 | --iterator->level; | |
2390 | ||
2d11123a AK |
2391 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2392 | iterator->shadow_addr | |
2393 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2394 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2395 | --iterator->level; | |
2396 | if (!iterator->shadow_addr) | |
2397 | iterator->level = 0; | |
2398 | } | |
2399 | } | |
2400 | ||
2401 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2402 | { | |
2403 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2404 | return false; | |
4d88954d | 2405 | |
2d11123a AK |
2406 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2407 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2408 | return true; | |
2409 | } | |
2410 | ||
c2a2ac2b XG |
2411 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2412 | u64 spte) | |
2d11123a | 2413 | { |
c2a2ac2b | 2414 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2415 | iterator->level = 0; |
2416 | return; | |
2417 | } | |
2418 | ||
c2a2ac2b | 2419 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2420 | --iterator->level; |
2421 | } | |
2422 | ||
c2a2ac2b XG |
2423 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2424 | { | |
2425 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2426 | } | |
2427 | ||
98bba238 TY |
2428 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2429 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2430 | { |
2431 | u64 spte; | |
2432 | ||
ffb128c8 | 2433 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2434 | |
ffb128c8 | 2435 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
ac8d57e5 PF |
2436 | shadow_user_mask | shadow_x_mask; |
2437 | ||
2438 | if (sp_ad_disabled(sp)) | |
2439 | spte |= shadow_acc_track_value; | |
2440 | else | |
2441 | spte |= shadow_accessed_mask; | |
24db2734 | 2442 | |
1df9f2dc | 2443 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2444 | |
2445 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2446 | ||
2447 | if (sp->unsync_children || sp->unsync) | |
2448 | mark_unsync(sptep); | |
32ef26a3 AK |
2449 | } |
2450 | ||
a357bd22 AK |
2451 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2452 | unsigned direct_access) | |
2453 | { | |
2454 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2455 | struct kvm_mmu_page *child; | |
2456 | ||
2457 | /* | |
2458 | * For the direct sp, if the guest pte's dirty bit | |
2459 | * changed form clean to dirty, it will corrupt the | |
2460 | * sp's access: allow writable in the read-only sp, | |
2461 | * so we should update the spte at this point to get | |
2462 | * a new sp with the correct access. | |
2463 | */ | |
2464 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2465 | if (child->role.access == direct_access) | |
2466 | return; | |
2467 | ||
bcdd9a93 | 2468 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2469 | kvm_flush_remote_tlbs(vcpu->kvm); |
2470 | } | |
2471 | } | |
2472 | ||
505aef8f | 2473 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2474 | u64 *spte) |
2475 | { | |
2476 | u64 pte; | |
2477 | struct kvm_mmu_page *child; | |
2478 | ||
2479 | pte = *spte; | |
2480 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2481 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2482 | drop_spte(kvm, spte); |
505aef8f XG |
2483 | if (is_large_pte(pte)) |
2484 | --kvm->stat.lpages; | |
2485 | } else { | |
38e3b2b2 | 2486 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2487 | drop_parent_pte(child, spte); |
38e3b2b2 | 2488 | } |
505aef8f XG |
2489 | return true; |
2490 | } | |
2491 | ||
2492 | if (is_mmio_spte(pte)) | |
ce88decf | 2493 | mmu_spte_clear_no_track(spte); |
c3707958 | 2494 | |
505aef8f | 2495 | return false; |
38e3b2b2 XG |
2496 | } |
2497 | ||
90cb0529 | 2498 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2499 | struct kvm_mmu_page *sp) |
a436036b | 2500 | { |
697fe2e2 | 2501 | unsigned i; |
697fe2e2 | 2502 | |
38e3b2b2 XG |
2503 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2504 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2505 | } |
2506 | ||
31aa2b44 | 2507 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2508 | { |
1e3f42f0 TY |
2509 | u64 *sptep; |
2510 | struct rmap_iterator iter; | |
a436036b | 2511 | |
018aabb5 | 2512 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2513 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2514 | } |
2515 | ||
60c8aec6 | 2516 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2517 | struct kvm_mmu_page *parent, |
2518 | struct list_head *invalid_list) | |
4731d4c7 | 2519 | { |
60c8aec6 MT |
2520 | int i, zapped = 0; |
2521 | struct mmu_page_path parents; | |
2522 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2523 | |
60c8aec6 | 2524 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2525 | return 0; |
60c8aec6 | 2526 | |
60c8aec6 MT |
2527 | while (mmu_unsync_walk(parent, &pages)) { |
2528 | struct kvm_mmu_page *sp; | |
2529 | ||
2530 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2531 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2532 | mmu_pages_clear_parents(&parents); |
77662e00 | 2533 | zapped++; |
60c8aec6 | 2534 | } |
60c8aec6 MT |
2535 | } |
2536 | ||
2537 | return zapped; | |
4731d4c7 MT |
2538 | } |
2539 | ||
7775834a XG |
2540 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2541 | struct list_head *invalid_list) | |
31aa2b44 | 2542 | { |
4731d4c7 | 2543 | int ret; |
f691fe1d | 2544 | |
7775834a | 2545 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2546 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2547 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2548 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2549 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2550 | |
f6e2c02b | 2551 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2552 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2553 | |
4731d4c7 MT |
2554 | if (sp->unsync) |
2555 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2556 | if (!sp->root_count) { |
54a4f023 GJ |
2557 | /* Count self */ |
2558 | ret++; | |
7775834a | 2559 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2560 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2561 | } else { |
5b5c6a5a | 2562 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2563 | |
2564 | /* | |
2565 | * The obsolete pages can not be used on any vcpus. | |
2566 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2567 | */ | |
2568 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2569 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2570 | } |
7775834a XG |
2571 | |
2572 | sp->role.invalid = 1; | |
4731d4c7 | 2573 | return ret; |
a436036b AK |
2574 | } |
2575 | ||
7775834a XG |
2576 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2577 | struct list_head *invalid_list) | |
2578 | { | |
945315b9 | 2579 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2580 | |
2581 | if (list_empty(invalid_list)) | |
2582 | return; | |
2583 | ||
c142786c | 2584 | /* |
9753f529 LT |
2585 | * We need to make sure everyone sees our modifications to |
2586 | * the page tables and see changes to vcpu->mode here. The barrier | |
2587 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2588 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2589 | * | |
2590 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2591 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2592 | */ |
2593 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2594 | |
945315b9 | 2595 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2596 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2597 | kvm_mmu_free_page(sp); |
945315b9 | 2598 | } |
7775834a XG |
2599 | } |
2600 | ||
5da59607 TY |
2601 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2602 | struct list_head *invalid_list) | |
2603 | { | |
2604 | struct kvm_mmu_page *sp; | |
2605 | ||
2606 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2607 | return false; | |
2608 | ||
d74c0e6b GT |
2609 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2610 | struct kvm_mmu_page, link); | |
42bcbebf | 2611 | return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
5da59607 TY |
2612 | } |
2613 | ||
82ce2c96 IE |
2614 | /* |
2615 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2616 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2617 | */ |
49d5ca26 | 2618 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2619 | { |
d98ba053 | 2620 | LIST_HEAD(invalid_list); |
82ce2c96 | 2621 | |
b34cb590 TY |
2622 | spin_lock(&kvm->mmu_lock); |
2623 | ||
49d5ca26 | 2624 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2625 | /* Need to free some mmu pages to achieve the goal. */ |
2626 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2627 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2628 | break; | |
82ce2c96 | 2629 | |
aa6bd187 | 2630 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2631 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2632 | } |
82ce2c96 | 2633 | |
49d5ca26 | 2634 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2635 | |
2636 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2637 | } |
2638 | ||
1cb3f3ae | 2639 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2640 | { |
4db35314 | 2641 | struct kvm_mmu_page *sp; |
d98ba053 | 2642 | LIST_HEAD(invalid_list); |
a436036b AK |
2643 | int r; |
2644 | ||
9ad17b10 | 2645 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2646 | r = 0; |
1cb3f3ae | 2647 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2648 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2649 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2650 | sp->role.word); |
2651 | r = 1; | |
f41d335a | 2652 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2653 | } |
d98ba053 | 2654 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2655 | spin_unlock(&kvm->mmu_lock); |
2656 | ||
a436036b | 2657 | return r; |
cea0f0e7 | 2658 | } |
1cb3f3ae | 2659 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2660 | |
5c520e90 | 2661 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2662 | { |
2663 | trace_kvm_mmu_unsync_page(sp); | |
2664 | ++vcpu->kvm->stat.mmu_unsync; | |
2665 | sp->unsync = 1; | |
2666 | ||
2667 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2668 | } |
2669 | ||
3d0c27ad XG |
2670 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2671 | bool can_unsync) | |
4731d4c7 | 2672 | { |
5c520e90 | 2673 | struct kvm_mmu_page *sp; |
4731d4c7 | 2674 | |
3d0c27ad XG |
2675 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2676 | return true; | |
9cf5cf5a | 2677 | |
5c520e90 | 2678 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2679 | if (!can_unsync) |
3d0c27ad | 2680 | return true; |
36a2e677 | 2681 | |
5c520e90 XG |
2682 | if (sp->unsync) |
2683 | continue; | |
9cf5cf5a | 2684 | |
5c520e90 XG |
2685 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2686 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2687 | } |
3d0c27ad XG |
2688 | |
2689 | return false; | |
4731d4c7 MT |
2690 | } |
2691 | ||
ba049e93 | 2692 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2693 | { |
2694 | if (pfn_valid(pfn)) | |
2695 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)); | |
2696 | ||
2697 | return true; | |
2698 | } | |
2699 | ||
d555c333 | 2700 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2701 | unsigned pte_access, int level, |
ba049e93 | 2702 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2703 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2704 | { |
ffb128c8 | 2705 | u64 spte = 0; |
1e73f9dd | 2706 | int ret = 0; |
ac8d57e5 | 2707 | struct kvm_mmu_page *sp; |
64d4d521 | 2708 | |
54bf36aa | 2709 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2710 | return 0; |
2711 | ||
ac8d57e5 PF |
2712 | sp = page_header(__pa(sptep)); |
2713 | if (sp_ad_disabled(sp)) | |
2714 | spte |= shadow_acc_track_value; | |
2715 | ||
d95c5568 BD |
2716 | /* |
2717 | * For the EPT case, shadow_present_mask is 0 if hardware | |
2718 | * supports exec-only page table entries. In that case, | |
2719 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
2720 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
2721 | */ | |
ffb128c8 | 2722 | spte |= shadow_present_mask; |
947da538 | 2723 | if (!speculative) |
ac8d57e5 | 2724 | spte |= spte_shadow_accessed_mask(spte); |
640d9b0d | 2725 | |
7b52345e SY |
2726 | if (pte_access & ACC_EXEC_MASK) |
2727 | spte |= shadow_x_mask; | |
2728 | else | |
2729 | spte |= shadow_nx_mask; | |
49fde340 | 2730 | |
1c4f1fd6 | 2731 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2732 | spte |= shadow_user_mask; |
49fde340 | 2733 | |
852e3c19 | 2734 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2735 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2736 | if (tdp_enabled) |
4b12f0de | 2737 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2738 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2739 | |
9bdbba13 | 2740 | if (host_writable) |
1403283a | 2741 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2742 | else |
2743 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2744 | |
35149e21 | 2745 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2746 | |
c2288505 | 2747 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2748 | |
c2193463 | 2749 | /* |
7751babd XG |
2750 | * Other vcpu creates new sp in the window between |
2751 | * mapping_level() and acquiring mmu-lock. We can | |
2752 | * allow guest to retry the access, the mapping can | |
2753 | * be fixed if guest refault. | |
c2193463 | 2754 | */ |
852e3c19 | 2755 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2756 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2757 | goto done; |
38187c83 | 2758 | |
49fde340 | 2759 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2760 | |
ecc5589f MT |
2761 | /* |
2762 | * Optimization: for pte sync, if spte was writable the hash | |
2763 | * lookup is unnecessary (and expensive). Write protection | |
2764 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2765 | * Same reasoning can be applied to dirty page accounting. | |
2766 | */ | |
8dae4445 | 2767 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2768 | goto set_pte; |
2769 | ||
4731d4c7 | 2770 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2771 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2772 | __func__, gfn); |
1e73f9dd | 2773 | ret = 1; |
1c4f1fd6 | 2774 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2775 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2776 | } |
2777 | } | |
2778 | ||
9b51a630 | 2779 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2780 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
ac8d57e5 | 2781 | spte |= spte_shadow_dirty_mask(spte); |
9b51a630 | 2782 | } |
1c4f1fd6 | 2783 | |
f160c7b7 JS |
2784 | if (speculative) |
2785 | spte = mark_spte_for_access_track(spte); | |
2786 | ||
38187c83 | 2787 | set_pte: |
6e7d0354 | 2788 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2789 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2790 | done: |
1e73f9dd MT |
2791 | return ret; |
2792 | } | |
2793 | ||
029499b4 | 2794 | static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
ba049e93 | 2795 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, |
029499b4 | 2796 | bool speculative, bool host_writable) |
1e73f9dd MT |
2797 | { |
2798 | int was_rmapped = 0; | |
53a27b39 | 2799 | int rmap_count; |
029499b4 | 2800 | bool emulate = false; |
1e73f9dd | 2801 | |
f7616203 XG |
2802 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2803 | *sptep, write_fault, gfn); | |
1e73f9dd | 2804 | |
afd28fe1 | 2805 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2806 | /* |
2807 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2808 | * the parent of the now unreachable PTE. | |
2809 | */ | |
852e3c19 JR |
2810 | if (level > PT_PAGE_TABLE_LEVEL && |
2811 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2812 | struct kvm_mmu_page *child; |
d555c333 | 2813 | u64 pte = *sptep; |
1e73f9dd MT |
2814 | |
2815 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2816 | drop_parent_pte(child, sptep); |
3be2264b | 2817 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2818 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2819 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2820 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2821 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2822 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2823 | } else |
2824 | was_rmapped = 1; | |
1e73f9dd | 2825 | } |
852e3c19 | 2826 | |
c2288505 XG |
2827 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2828 | true, host_writable)) { | |
1e73f9dd | 2829 | if (write_fault) |
029499b4 | 2830 | emulate = true; |
77c3913b | 2831 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 2832 | } |
1e73f9dd | 2833 | |
029499b4 TY |
2834 | if (unlikely(is_mmio_spte(*sptep))) |
2835 | emulate = true; | |
ce88decf | 2836 | |
d555c333 | 2837 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2838 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2839 | is_large_pte(*sptep)? "2MB" : "4kB", |
f160c7b7 | 2840 | *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn, |
a205bc19 | 2841 | *sptep, sptep); |
d555c333 | 2842 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2843 | ++vcpu->kvm->stat.lpages; |
2844 | ||
ffb61bb3 | 2845 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2846 | if (!was_rmapped) { |
2847 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2848 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2849 | rmap_recycle(vcpu, sptep, gfn); | |
2850 | } | |
1c4f1fd6 | 2851 | } |
cb9aaa30 | 2852 | |
f3ac1a4b | 2853 | kvm_release_pfn_clean(pfn); |
029499b4 TY |
2854 | |
2855 | return emulate; | |
1c4f1fd6 AK |
2856 | } |
2857 | ||
ba049e93 | 2858 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2859 | bool no_dirty_log) |
2860 | { | |
2861 | struct kvm_memory_slot *slot; | |
957ed9ef | 2862 | |
5d163b1c | 2863 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2864 | if (!slot) |
6c8ee57b | 2865 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2866 | |
037d92dc | 2867 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2868 | } |
2869 | ||
2870 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2871 | struct kvm_mmu_page *sp, | |
2872 | u64 *start, u64 *end) | |
2873 | { | |
2874 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2875 | struct kvm_memory_slot *slot; |
957ed9ef XG |
2876 | unsigned access = sp->role.access; |
2877 | int i, ret; | |
2878 | gfn_t gfn; | |
2879 | ||
2880 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2881 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2882 | if (!slot) | |
957ed9ef XG |
2883 | return -1; |
2884 | ||
d9ef13c2 | 2885 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2886 | if (ret <= 0) |
2887 | return -1; | |
2888 | ||
2889 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
2890 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
2891 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
2892 | |
2893 | return 0; | |
2894 | } | |
2895 | ||
2896 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2897 | struct kvm_mmu_page *sp, u64 *sptep) | |
2898 | { | |
2899 | u64 *spte, *start = NULL; | |
2900 | int i; | |
2901 | ||
2902 | WARN_ON(!sp->role.direct); | |
2903 | ||
2904 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2905 | spte = sp->spt + i; | |
2906 | ||
2907 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2908 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2909 | if (!start) |
2910 | continue; | |
2911 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2912 | break; | |
2913 | start = NULL; | |
2914 | } else if (!start) | |
2915 | start = spte; | |
2916 | } | |
2917 | } | |
2918 | ||
2919 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2920 | { | |
2921 | struct kvm_mmu_page *sp; | |
2922 | ||
ac8d57e5 PF |
2923 | sp = page_header(__pa(sptep)); |
2924 | ||
957ed9ef | 2925 | /* |
ac8d57e5 PF |
2926 | * Without accessed bits, there's no way to distinguish between |
2927 | * actually accessed translations and prefetched, so disable pte | |
2928 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2929 | */ |
ac8d57e5 | 2930 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2931 | return; |
2932 | ||
957ed9ef XG |
2933 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
2934 | return; | |
2935 | ||
2936 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2937 | } | |
2938 | ||
7ee0e5b2 | 2939 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 2940 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 2941 | { |
9f652d21 | 2942 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2943 | struct kvm_mmu_page *sp; |
b90a0e6c | 2944 | int emulate = 0; |
140754bc | 2945 | gfn_t pseudo_gfn; |
6aa8b732 | 2946 | |
989c6b34 MT |
2947 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2948 | return 0; | |
2949 | ||
9f652d21 | 2950 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2951 | if (iterator.level == level) { |
029499b4 TY |
2952 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
2953 | write, level, gfn, pfn, prefault, | |
2954 | map_writable); | |
957ed9ef | 2955 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2956 | ++vcpu->stat.pf_fixed; |
2957 | break; | |
6aa8b732 AK |
2958 | } |
2959 | ||
404381c5 | 2960 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 2961 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2962 | u64 base_addr = iterator.addr; |
2963 | ||
2964 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2965 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 2966 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 2967 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 2968 | |
98bba238 | 2969 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
2970 | } |
2971 | } | |
b90a0e6c | 2972 | return emulate; |
6aa8b732 AK |
2973 | } |
2974 | ||
77db5cbd | 2975 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2976 | { |
77db5cbd HY |
2977 | siginfo_t info; |
2978 | ||
2979 | info.si_signo = SIGBUS; | |
2980 | info.si_errno = 0; | |
2981 | info.si_code = BUS_MCEERR_AR; | |
2982 | info.si_addr = (void __user *)address; | |
2983 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2984 | |
77db5cbd | 2985 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2986 | } |
2987 | ||
ba049e93 | 2988 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2989 | { |
4d8b81ab XG |
2990 | /* |
2991 | * Do not cache the mmio info caused by writing the readonly gfn | |
2992 | * into the spte otherwise read access on readonly gfn also can | |
2993 | * caused mmio page fault and treat it as mmio access. | |
2994 | * Return 1 to tell kvm to emulate it. | |
2995 | */ | |
2996 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2997 | return 1; | |
2998 | ||
e6c1502b | 2999 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3000 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
bf998156 | 3001 | return 0; |
d7c55201 | 3002 | } |
edba23e5 | 3003 | |
d7c55201 | 3004 | return -EFAULT; |
bf998156 HY |
3005 | } |
3006 | ||
936a5fe6 | 3007 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
3008 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
3009 | int *levelp) | |
936a5fe6 | 3010 | { |
ba049e93 | 3011 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
3012 | gfn_t gfn = *gfnp; |
3013 | int level = *levelp; | |
3014 | ||
3015 | /* | |
3016 | * Check if it's a transparent hugepage. If this would be an | |
3017 | * hugetlbfs page, level wouldn't be set to | |
3018 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
3019 | * here. | |
3020 | */ | |
bf4bea8e | 3021 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 | 3022 | level == PT_PAGE_TABLE_LEVEL && |
127393fb | 3023 | PageTransCompoundMap(pfn_to_page(pfn)) && |
92f94f1e | 3024 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
3025 | unsigned long mask; |
3026 | /* | |
3027 | * mmu_notifier_retry was successful and we hold the | |
3028 | * mmu_lock here, so the pmd can't become splitting | |
3029 | * from under us, and in turn | |
3030 | * __split_huge_page_refcount() can't run from under | |
3031 | * us and we can safely transfer the refcount from | |
3032 | * PG_tail to PG_head as we switch the pfn to tail to | |
3033 | * head. | |
3034 | */ | |
3035 | *levelp = level = PT_DIRECTORY_LEVEL; | |
3036 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
3037 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
3038 | if (pfn & mask) { | |
3039 | gfn &= ~mask; | |
3040 | *gfnp = gfn; | |
3041 | kvm_release_pfn_clean(pfn); | |
3042 | pfn &= ~mask; | |
c3586667 | 3043 | kvm_get_pfn(pfn); |
936a5fe6 AA |
3044 | *pfnp = pfn; |
3045 | } | |
3046 | } | |
3047 | } | |
3048 | ||
d7c55201 | 3049 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 3050 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 3051 | { |
d7c55201 | 3052 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3053 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3054 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3055 | return true; |
d7c55201 XG |
3056 | } |
3057 | ||
ce88decf | 3058 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 3059 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 3060 | |
798e88b3 | 3061 | return false; |
d7c55201 XG |
3062 | } |
3063 | ||
e5552fd2 | 3064 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3065 | { |
1c118b82 XG |
3066 | /* |
3067 | * Do not fix the mmio spte with invalid generation number which | |
3068 | * need to be updated by slow page fault path. | |
3069 | */ | |
3070 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3071 | return false; | |
3072 | ||
f160c7b7 JS |
3073 | /* See if the page fault is due to an NX violation */ |
3074 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3075 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3076 | return false; | |
3077 | ||
c7ba5b48 | 3078 | /* |
f160c7b7 JS |
3079 | * #PF can be fast if: |
3080 | * 1. The shadow page table entry is not present, which could mean that | |
3081 | * the fault is potentially caused by access tracking (if enabled). | |
3082 | * 2. The shadow page table entry is present and the fault | |
3083 | * is caused by write-protect, that means we just need change the W | |
3084 | * bit of the spte which can be done out of mmu-lock. | |
3085 | * | |
3086 | * However, if access tracking is disabled we know that a non-present | |
3087 | * page must be a genuine page fault where we have to create a new SPTE. | |
3088 | * So, if access tracking is disabled, we return true only for write | |
3089 | * accesses to a present page. | |
c7ba5b48 | 3090 | */ |
c7ba5b48 | 3091 | |
f160c7b7 JS |
3092 | return shadow_acc_track_mask != 0 || |
3093 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3094 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3095 | } |
3096 | ||
97dceba2 JS |
3097 | /* |
3098 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3099 | * someone else modified the SPTE from its original value. | |
3100 | */ | |
c7ba5b48 | 3101 | static bool |
92a476cb | 3102 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3103 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3104 | { |
c7ba5b48 XG |
3105 | gfn_t gfn; |
3106 | ||
3107 | WARN_ON(!sp->role.direct); | |
3108 | ||
9b51a630 KH |
3109 | /* |
3110 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3111 | * order to eliminate unnecessary PML logging. See comments in | |
3112 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3113 | * enabled, so we do not do this. This might result in the same GPA | |
3114 | * to be logged in PML buffer again when the write really happens, and | |
3115 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3116 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3117 | * so non-PML cases won't be impacted. | |
3118 | * | |
3119 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3120 | */ | |
f160c7b7 | 3121 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3122 | return false; |
3123 | ||
d3e328f2 | 3124 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3125 | /* |
3126 | * The gfn of direct spte is stable since it is | |
3127 | * calculated by sp->gfn. | |
3128 | */ | |
3129 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3130 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3131 | } | |
c7ba5b48 XG |
3132 | |
3133 | return true; | |
3134 | } | |
3135 | ||
d3e328f2 JS |
3136 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3137 | { | |
3138 | if (fault_err_code & PFERR_FETCH_MASK) | |
3139 | return is_executable_pte(spte); | |
3140 | ||
3141 | if (fault_err_code & PFERR_WRITE_MASK) | |
3142 | return is_writable_pte(spte); | |
3143 | ||
3144 | /* Fault was on Read access */ | |
3145 | return spte & PT_PRESENT_MASK; | |
3146 | } | |
3147 | ||
c7ba5b48 XG |
3148 | /* |
3149 | * Return value: | |
3150 | * - true: let the vcpu to access on the same address again. | |
3151 | * - false: let the real page fault path to fix it. | |
3152 | */ | |
3153 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
3154 | u32 error_code) | |
3155 | { | |
3156 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3157 | struct kvm_mmu_page *sp; |
97dceba2 | 3158 | bool fault_handled = false; |
c7ba5b48 | 3159 | u64 spte = 0ull; |
97dceba2 | 3160 | uint retry_count = 0; |
c7ba5b48 | 3161 | |
37f6a4e2 MT |
3162 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3163 | return false; | |
3164 | ||
e5552fd2 | 3165 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3166 | return false; |
3167 | ||
3168 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3169 | |
97dceba2 | 3170 | do { |
d3e328f2 | 3171 | u64 new_spte; |
c7ba5b48 | 3172 | |
d162f30a JS |
3173 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) |
3174 | if (!is_shadow_present_pte(spte) || | |
3175 | iterator.level < level) | |
3176 | break; | |
3177 | ||
97dceba2 JS |
3178 | sp = page_header(__pa(iterator.sptep)); |
3179 | if (!is_last_spte(spte, sp->role.level)) | |
3180 | break; | |
c7ba5b48 | 3181 | |
97dceba2 | 3182 | /* |
f160c7b7 JS |
3183 | * Check whether the memory access that caused the fault would |
3184 | * still cause it if it were to be performed right now. If not, | |
3185 | * then this is a spurious fault caused by TLB lazily flushed, | |
3186 | * or some other CPU has already fixed the PTE after the | |
3187 | * current CPU took the fault. | |
97dceba2 JS |
3188 | * |
3189 | * Need not check the access of upper level table entries since | |
3190 | * they are always ACC_ALL. | |
3191 | */ | |
d3e328f2 JS |
3192 | if (is_access_allowed(error_code, spte)) { |
3193 | fault_handled = true; | |
3194 | break; | |
3195 | } | |
f160c7b7 | 3196 | |
d3e328f2 JS |
3197 | new_spte = spte; |
3198 | ||
3199 | if (is_access_track_spte(spte)) | |
3200 | new_spte = restore_acc_track_spte(new_spte); | |
3201 | ||
3202 | /* | |
3203 | * Currently, to simplify the code, write-protection can | |
3204 | * be removed in the fast path only if the SPTE was | |
3205 | * write-protected for dirty-logging or access tracking. | |
3206 | */ | |
3207 | if ((error_code & PFERR_WRITE_MASK) && | |
3208 | spte_can_locklessly_be_made_writable(spte)) | |
3209 | { | |
3210 | new_spte |= PT_WRITABLE_MASK; | |
f160c7b7 JS |
3211 | |
3212 | /* | |
d3e328f2 JS |
3213 | * Do not fix write-permission on the large spte. Since |
3214 | * we only dirty the first page into the dirty-bitmap in | |
3215 | * fast_pf_fix_direct_spte(), other pages are missed | |
3216 | * if its slot has dirty logging enabled. | |
3217 | * | |
3218 | * Instead, we let the slow page fault path create a | |
3219 | * normal spte to fix the access. | |
3220 | * | |
3221 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3222 | */ |
d3e328f2 | 3223 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3224 | break; |
97dceba2 | 3225 | } |
c7ba5b48 | 3226 | |
f160c7b7 | 3227 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3228 | if (new_spte == spte || |
3229 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3230 | break; |
3231 | ||
3232 | /* | |
3233 | * Currently, fast page fault only works for direct mapping | |
3234 | * since the gfn is not stable for indirect shadow page. See | |
3235 | * Documentation/virtual/kvm/locking.txt to get more detail. | |
3236 | */ | |
3237 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3238 | iterator.sptep, spte, |
d3e328f2 | 3239 | new_spte); |
97dceba2 JS |
3240 | if (fault_handled) |
3241 | break; | |
3242 | ||
3243 | if (++retry_count > 4) { | |
3244 | printk_once(KERN_WARNING | |
3245 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3246 | break; | |
3247 | } | |
3248 | ||
97dceba2 | 3249 | } while (true); |
c126d94f | 3250 | |
a72faf25 | 3251 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
97dceba2 | 3252 | spte, fault_handled); |
c7ba5b48 XG |
3253 | walk_shadow_page_lockless_end(vcpu); |
3254 | ||
97dceba2 | 3255 | return fault_handled; |
c7ba5b48 XG |
3256 | } |
3257 | ||
78b2c54a | 3258 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3259 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
26eeb53c | 3260 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3261 | |
c7ba5b48 XG |
3262 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3263 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3264 | { |
3265 | int r; | |
852e3c19 | 3266 | int level; |
fd136902 | 3267 | bool force_pt_level = false; |
ba049e93 | 3268 | kvm_pfn_t pfn; |
e930bffe | 3269 | unsigned long mmu_seq; |
c7ba5b48 | 3270 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3271 | |
fd136902 | 3272 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3273 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3274 | /* |
3275 | * This path builds a PAE pagetable - so we can map | |
3276 | * 2mb pages at maximum. Therefore check if the level | |
3277 | * is larger than that. | |
3278 | */ | |
3279 | if (level > PT_DIRECTORY_LEVEL) | |
3280 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3281 | |
936a5fe6 | 3282 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3283 | } |
05da4558 | 3284 | |
c7ba5b48 XG |
3285 | if (fast_page_fault(vcpu, v, level, error_code)) |
3286 | return 0; | |
3287 | ||
e930bffe | 3288 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3289 | smp_rmb(); |
060c2abe | 3290 | |
78b2c54a | 3291 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 3292 | return 0; |
aaee2c94 | 3293 | |
d7c55201 XG |
3294 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3295 | return r; | |
d196e343 | 3296 | |
aaee2c94 | 3297 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3298 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3299 | goto out_unlock; |
26eeb53c WL |
3300 | if (make_mmu_pages_available(vcpu) < 0) |
3301 | goto out_unlock; | |
936a5fe6 AA |
3302 | if (likely(!force_pt_level)) |
3303 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3304 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3305 | spin_unlock(&vcpu->kvm->mmu_lock); |
3306 | ||
10589a46 | 3307 | return r; |
e930bffe AA |
3308 | |
3309 | out_unlock: | |
3310 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3311 | kvm_release_pfn_clean(pfn); | |
3312 | return 0; | |
10589a46 MT |
3313 | } |
3314 | ||
3315 | ||
17ac10ad AK |
3316 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
3317 | { | |
3318 | int i; | |
4db35314 | 3319 | struct kvm_mmu_page *sp; |
d98ba053 | 3320 | LIST_HEAD(invalid_list); |
17ac10ad | 3321 | |
ad312c7c | 3322 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 3323 | return; |
35af577a | 3324 | |
81407ca5 JR |
3325 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
3326 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
3327 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 3328 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3329 | |
35af577a | 3330 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
3331 | sp = page_header(root); |
3332 | --sp->root_count; | |
d98ba053 XG |
3333 | if (!sp->root_count && sp->role.invalid) { |
3334 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
3335 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
3336 | } | |
aaee2c94 | 3337 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 3338 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3339 | return; |
3340 | } | |
35af577a GN |
3341 | |
3342 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3343 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3344 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3345 | |
417726a3 | 3346 | if (root) { |
417726a3 | 3347 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
3348 | sp = page_header(root); |
3349 | --sp->root_count; | |
2e53d63a | 3350 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
3351 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
3352 | &invalid_list); | |
417726a3 | 3353 | } |
ad312c7c | 3354 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3355 | } |
d98ba053 | 3356 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3357 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3358 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3359 | } |
3360 | ||
8986ecc0 MT |
3361 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3362 | { | |
3363 | int ret = 0; | |
3364 | ||
3365 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3366 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3367 | ret = 1; |
3368 | } | |
3369 | ||
3370 | return ret; | |
3371 | } | |
3372 | ||
651dd37a JR |
3373 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3374 | { | |
3375 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3376 | unsigned i; |
651dd37a JR |
3377 | |
3378 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3379 | spin_lock(&vcpu->kvm->mmu_lock); | |
26eeb53c WL |
3380 | if(make_mmu_pages_available(vcpu) < 0) { |
3381 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3382 | return 1; | |
3383 | } | |
bb11c6c9 | 3384 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3385 | ++sp->root_count; |
3386 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3387 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3388 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3389 | for (i = 0; i < 4; ++i) { | |
3390 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3391 | ||
fa4a2c08 | 3392 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3393 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3394 | if (make_mmu_pages_available(vcpu) < 0) { |
3395 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3396 | return 1; | |
3397 | } | |
649497d1 | 3398 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3399 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3400 | root = __pa(sp->spt); |
3401 | ++sp->root_count; | |
3402 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3403 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3404 | } |
6292757f | 3405 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3406 | } else |
3407 | BUG(); | |
3408 | ||
3409 | return 0; | |
3410 | } | |
3411 | ||
3412 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3413 | { |
4db35314 | 3414 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3415 | u64 pdptr, pm_mask; |
3416 | gfn_t root_gfn; | |
3417 | int i; | |
3bb65a22 | 3418 | |
5777ed34 | 3419 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3420 | |
651dd37a JR |
3421 | if (mmu_check_root(vcpu, root_gfn)) |
3422 | return 1; | |
3423 | ||
3424 | /* | |
3425 | * Do we shadow a long mode page table? If so we need to | |
3426 | * write-protect the guests page table root. | |
3427 | */ | |
3428 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3429 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3430 | |
fa4a2c08 | 3431 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3432 | |
8facbbff | 3433 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3434 | if (make_mmu_pages_available(vcpu) < 0) { |
3435 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3436 | return 1; | |
3437 | } | |
651dd37a | 3438 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
bb11c6c9 | 3439 | 0, ACC_ALL); |
4db35314 AK |
3440 | root = __pa(sp->spt); |
3441 | ++sp->root_count; | |
8facbbff | 3442 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3443 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3444 | return 0; |
17ac10ad | 3445 | } |
f87f9288 | 3446 | |
651dd37a JR |
3447 | /* |
3448 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3449 | * or a PAE 3-level page table. In either case we need to be aware that |
3450 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3451 | */ |
81407ca5 JR |
3452 | pm_mask = PT_PRESENT_MASK; |
3453 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3454 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3455 | ||
17ac10ad | 3456 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3457 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3458 | |
fa4a2c08 | 3459 | MMU_WARN_ON(VALID_PAGE(root)); |
ad312c7c | 3460 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3461 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
812f30b2 | 3462 | if (!(pdptr & PT_PRESENT_MASK)) { |
ad312c7c | 3463 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3464 | continue; |
3465 | } | |
6de4f3ad | 3466 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3467 | if (mmu_check_root(vcpu, root_gfn)) |
3468 | return 1; | |
5a7388c2 | 3469 | } |
8facbbff | 3470 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3471 | if (make_mmu_pages_available(vcpu) < 0) { |
3472 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3473 | return 1; | |
3474 | } | |
bb11c6c9 TY |
3475 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3476 | 0, ACC_ALL); | |
4db35314 AK |
3477 | root = __pa(sp->spt); |
3478 | ++sp->root_count; | |
8facbbff AK |
3479 | spin_unlock(&vcpu->kvm->mmu_lock); |
3480 | ||
81407ca5 | 3481 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3482 | } |
6292757f | 3483 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3484 | |
3485 | /* | |
3486 | * If we shadow a 32 bit page table with a long mode page | |
3487 | * table we enter this path. | |
3488 | */ | |
3489 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3490 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3491 | /* | |
3492 | * The additional page necessary for this is only | |
3493 | * allocated on demand. | |
3494 | */ | |
3495 | ||
3496 | u64 *lm_root; | |
3497 | ||
3498 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3499 | if (lm_root == NULL) | |
3500 | return 1; | |
3501 | ||
3502 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3503 | ||
3504 | vcpu->arch.mmu.lm_root = lm_root; | |
3505 | } | |
3506 | ||
3507 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3508 | } | |
3509 | ||
8986ecc0 | 3510 | return 0; |
17ac10ad AK |
3511 | } |
3512 | ||
651dd37a JR |
3513 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3514 | { | |
3515 | if (vcpu->arch.mmu.direct_map) | |
3516 | return mmu_alloc_direct_roots(vcpu); | |
3517 | else | |
3518 | return mmu_alloc_shadow_roots(vcpu); | |
3519 | } | |
3520 | ||
0ba73cda MT |
3521 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3522 | { | |
3523 | int i; | |
3524 | struct kvm_mmu_page *sp; | |
3525 | ||
81407ca5 JR |
3526 | if (vcpu->arch.mmu.direct_map) |
3527 | return; | |
3528 | ||
0ba73cda MT |
3529 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3530 | return; | |
6903074c | 3531 | |
56f17dd3 | 3532 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
0375f7fa | 3533 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3534 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3535 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3536 | sp = page_header(root); | |
3537 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3538 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3539 | return; |
3540 | } | |
3541 | for (i = 0; i < 4; ++i) { | |
3542 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3543 | ||
8986ecc0 | 3544 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3545 | root &= PT64_BASE_ADDR_MASK; |
3546 | sp = page_header(root); | |
3547 | mmu_sync_children(vcpu, sp); | |
3548 | } | |
3549 | } | |
0375f7fa | 3550 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3551 | } |
3552 | ||
3553 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3554 | { | |
3555 | spin_lock(&vcpu->kvm->mmu_lock); | |
3556 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3557 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3558 | } |
bfd0a56b | 3559 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3560 | |
1871c602 | 3561 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3562 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3563 | { |
ab9ae313 AK |
3564 | if (exception) |
3565 | exception->error_code = 0; | |
6aa8b732 AK |
3566 | return vaddr; |
3567 | } | |
3568 | ||
6539e738 | 3569 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3570 | u32 access, |
3571 | struct x86_exception *exception) | |
6539e738 | 3572 | { |
ab9ae313 AK |
3573 | if (exception) |
3574 | exception->error_code = 0; | |
54987b7a | 3575 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3576 | } |
3577 | ||
d625b155 XG |
3578 | static bool |
3579 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3580 | { | |
3581 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3582 | ||
3583 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3584 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3585 | } | |
3586 | ||
3587 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3588 | { | |
3589 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3590 | } | |
3591 | ||
3592 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3593 | { | |
3594 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3595 | } | |
3596 | ||
ded58749 | 3597 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3598 | { |
9034e6e8 PB |
3599 | /* |
3600 | * A nested guest cannot use the MMIO cache if it is using nested | |
3601 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3602 | */ | |
3603 | if (mmu_is_nested(vcpu)) | |
3604 | return false; | |
3605 | ||
ce88decf XG |
3606 | if (direct) |
3607 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3608 | ||
3609 | return vcpu_match_mmio_gva(vcpu, addr); | |
3610 | } | |
3611 | ||
47ab8751 XG |
3612 | /* return true if reserved bit is detected on spte. */ |
3613 | static bool | |
3614 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3615 | { |
3616 | struct kvm_shadow_walk_iterator iterator; | |
47ab8751 XG |
3617 | u64 sptes[PT64_ROOT_LEVEL], spte = 0ull; |
3618 | int root, leaf; | |
3619 | bool reserved = false; | |
ce88decf | 3620 | |
37f6a4e2 | 3621 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
47ab8751 | 3622 | goto exit; |
37f6a4e2 | 3623 | |
ce88decf | 3624 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3625 | |
29ecd660 PB |
3626 | for (shadow_walk_init(&iterator, vcpu, addr), |
3627 | leaf = root = iterator.level; | |
47ab8751 XG |
3628 | shadow_walk_okay(&iterator); |
3629 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3630 | spte = mmu_spte_get_lockless(iterator.sptep); |
3631 | ||
3632 | sptes[leaf - 1] = spte; | |
29ecd660 | 3633 | leaf--; |
47ab8751 | 3634 | |
ce88decf XG |
3635 | if (!is_shadow_present_pte(spte)) |
3636 | break; | |
47ab8751 XG |
3637 | |
3638 | reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, | |
58c95070 | 3639 | iterator.level); |
47ab8751 XG |
3640 | } |
3641 | ||
ce88decf XG |
3642 | walk_shadow_page_lockless_end(vcpu); |
3643 | ||
47ab8751 XG |
3644 | if (reserved) { |
3645 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3646 | __func__, addr); | |
29ecd660 | 3647 | while (root > leaf) { |
47ab8751 XG |
3648 | pr_err("------ spte 0x%llx level %d.\n", |
3649 | sptes[root - 1], root); | |
3650 | root--; | |
3651 | } | |
3652 | } | |
3653 | exit: | |
3654 | *sptep = spte; | |
3655 | return reserved; | |
ce88decf XG |
3656 | } |
3657 | ||
e08d26f0 PB |
3658 | /* |
3659 | * Return values of handle_mmio_page_fault: | |
3660 | * RET_MMIO_PF_EMULATE: it is a real mmio page fault, emulate the instruction | |
3661 | * directly. | |
3662 | * RET_MMIO_PF_INVALID: invalid spte is detected then let the real page | |
3663 | * fault path update the mmio spte. | |
3664 | * RET_MMIO_PF_RETRY: let CPU fault again on the address. | |
3665 | * RET_MMIO_PF_BUG: a bug was detected (and a WARN was printed). | |
3666 | */ | |
3667 | enum { | |
3668 | RET_MMIO_PF_EMULATE = 1, | |
3669 | RET_MMIO_PF_INVALID = 2, | |
3670 | RET_MMIO_PF_RETRY = 0, | |
3671 | RET_MMIO_PF_BUG = -1 | |
3672 | }; | |
3673 | ||
3674 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) | |
ce88decf XG |
3675 | { |
3676 | u64 spte; | |
47ab8751 | 3677 | bool reserved; |
ce88decf | 3678 | |
ded58749 | 3679 | if (mmio_info_in_cache(vcpu, addr, direct)) |
b37fbea6 | 3680 | return RET_MMIO_PF_EMULATE; |
ce88decf | 3681 | |
47ab8751 | 3682 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3683 | if (WARN_ON(reserved)) |
47ab8751 | 3684 | return RET_MMIO_PF_BUG; |
ce88decf XG |
3685 | |
3686 | if (is_mmio_spte(spte)) { | |
3687 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3688 | unsigned access = get_mmio_spte_access(spte); | |
3689 | ||
54bf36aa | 3690 | if (!check_mmio_spte(vcpu, spte)) |
f8f55942 XG |
3691 | return RET_MMIO_PF_INVALID; |
3692 | ||
ce88decf XG |
3693 | if (direct) |
3694 | addr = 0; | |
4f022648 XG |
3695 | |
3696 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3697 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
b37fbea6 | 3698 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3699 | } |
3700 | ||
ce88decf XG |
3701 | /* |
3702 | * If the page table is zapped by other cpus, let CPU fault again on | |
3703 | * the address. | |
3704 | */ | |
b37fbea6 | 3705 | return RET_MMIO_PF_RETRY; |
ce88decf | 3706 | } |
450869d6 | 3707 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault); |
ce88decf | 3708 | |
3d0c27ad XG |
3709 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3710 | u32 error_code, gfn_t gfn) | |
3711 | { | |
3712 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3713 | return false; | |
3714 | ||
3715 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3716 | !(error_code & PFERR_WRITE_MASK)) | |
3717 | return false; | |
3718 | ||
3719 | /* | |
3720 | * guest is writing the page which is write tracked which can | |
3721 | * not be fixed by page fault handler. | |
3722 | */ | |
3723 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3724 | return true; | |
3725 | ||
3726 | return false; | |
3727 | } | |
3728 | ||
e5691a81 XG |
3729 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3730 | { | |
3731 | struct kvm_shadow_walk_iterator iterator; | |
3732 | u64 spte; | |
3733 | ||
3734 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3735 | return; | |
3736 | ||
3737 | walk_shadow_page_lockless_begin(vcpu); | |
3738 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3739 | clear_sp_write_flooding_count(iterator.sptep); | |
3740 | if (!is_shadow_present_pte(spte)) | |
3741 | break; | |
3742 | } | |
3743 | walk_shadow_page_lockless_end(vcpu); | |
3744 | } | |
3745 | ||
6aa8b732 | 3746 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3747 | u32 error_code, bool prefault) |
6aa8b732 | 3748 | { |
3d0c27ad | 3749 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3750 | int r; |
6aa8b732 | 3751 | |
b8688d51 | 3752 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3753 | |
3d0c27ad XG |
3754 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3755 | return 1; | |
ce88decf | 3756 | |
e2dec939 AK |
3757 | r = mmu_topup_memory_caches(vcpu); |
3758 | if (r) | |
3759 | return r; | |
714b93da | 3760 | |
fa4a2c08 | 3761 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3762 | |
6aa8b732 | 3763 | |
e833240f | 3764 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3765 | error_code, gfn, prefault); |
6aa8b732 AK |
3766 | } |
3767 | ||
7e1fbeac | 3768 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3769 | { |
3770 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3771 | |
7c90705b | 3772 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3773 | arch.gfn = gfn; |
c4806acd | 3774 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3775 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3776 | |
54bf36aa | 3777 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3778 | } |
3779 | ||
9bc1f09f | 3780 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) |
af585b92 | 3781 | { |
35754c98 | 3782 | if (unlikely(!lapic_in_kernel(vcpu) || |
af585b92 GN |
3783 | kvm_event_needs_reinjection(vcpu))) |
3784 | return false; | |
3785 | ||
52a5c155 | 3786 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) |
9bc1f09f WL |
3787 | return false; |
3788 | ||
af585b92 GN |
3789 | return kvm_x86_ops->interrupt_allowed(vcpu); |
3790 | } | |
3791 | ||
78b2c54a | 3792 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3793 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 3794 | { |
3520469d | 3795 | struct kvm_memory_slot *slot; |
af585b92 GN |
3796 | bool async; |
3797 | ||
54bf36aa | 3798 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
3799 | async = false; |
3800 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3801 | if (!async) |
3802 | return false; /* *pfn has correct page already */ | |
3803 | ||
9bc1f09f | 3804 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
c9b263d2 | 3805 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3806 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3807 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3808 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3809 | return true; | |
3810 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3811 | return true; | |
3812 | } | |
3813 | ||
3520469d | 3814 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3815 | return false; |
3816 | } | |
3817 | ||
1261bfa3 WL |
3818 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
3819 | u64 fault_address, char *insn, int insn_len, | |
3820 | bool need_unprotect) | |
3821 | { | |
3822 | int r = 1; | |
3823 | ||
3824 | switch (vcpu->arch.apf.host_apf_reason) { | |
3825 | default: | |
3826 | trace_kvm_page_fault(fault_address, error_code); | |
3827 | ||
3828 | if (need_unprotect && kvm_event_needs_reinjection(vcpu)) | |
3829 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); | |
3830 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3831 | insn_len); | |
3832 | break; | |
3833 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
3834 | vcpu->arch.apf.host_apf_reason = 0; | |
3835 | local_irq_disable(); | |
3836 | kvm_async_pf_task_wait(fault_address); | |
3837 | local_irq_enable(); | |
3838 | break; | |
3839 | case KVM_PV_REASON_PAGE_READY: | |
3840 | vcpu->arch.apf.host_apf_reason = 0; | |
3841 | local_irq_disable(); | |
3842 | kvm_async_pf_task_wake(fault_address); | |
3843 | local_irq_enable(); | |
3844 | break; | |
3845 | } | |
3846 | return r; | |
3847 | } | |
3848 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3849 | ||
6a39bbc5 XG |
3850 | static bool |
3851 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
3852 | { | |
3853 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
3854 | ||
3855 | gfn &= ~(page_num - 1); | |
3856 | ||
3857 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
3858 | } | |
3859 | ||
56028d08 | 3860 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3861 | bool prefault) |
fb72d167 | 3862 | { |
ba049e93 | 3863 | kvm_pfn_t pfn; |
fb72d167 | 3864 | int r; |
852e3c19 | 3865 | int level; |
cd1872f0 | 3866 | bool force_pt_level; |
05da4558 | 3867 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3868 | unsigned long mmu_seq; |
612819c3 MT |
3869 | int write = error_code & PFERR_WRITE_MASK; |
3870 | bool map_writable; | |
fb72d167 | 3871 | |
fa4a2c08 | 3872 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
fb72d167 | 3873 | |
3d0c27ad XG |
3874 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3875 | return 1; | |
ce88decf | 3876 | |
fb72d167 JR |
3877 | r = mmu_topup_memory_caches(vcpu); |
3878 | if (r) | |
3879 | return r; | |
3880 | ||
fd136902 TY |
3881 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
3882 | PT_DIRECTORY_LEVEL); | |
3883 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 3884 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
3885 | if (level > PT_DIRECTORY_LEVEL && |
3886 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
3887 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 3888 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3889 | } |
852e3c19 | 3890 | |
c7ba5b48 XG |
3891 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3892 | return 0; | |
3893 | ||
e930bffe | 3894 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3895 | smp_rmb(); |
af585b92 | 3896 | |
78b2c54a | 3897 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3898 | return 0; |
3899 | ||
d7c55201 XG |
3900 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3901 | return r; | |
3902 | ||
fb72d167 | 3903 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3904 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3905 | goto out_unlock; |
26eeb53c WL |
3906 | if (make_mmu_pages_available(vcpu) < 0) |
3907 | goto out_unlock; | |
936a5fe6 AA |
3908 | if (likely(!force_pt_level)) |
3909 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3910 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 3911 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3912 | |
3913 | return r; | |
e930bffe AA |
3914 | |
3915 | out_unlock: | |
3916 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3917 | kvm_release_pfn_clean(pfn); | |
3918 | return 0; | |
fb72d167 JR |
3919 | } |
3920 | ||
8a3c1a33 PB |
3921 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3922 | struct kvm_mmu *context) | |
6aa8b732 | 3923 | { |
6aa8b732 | 3924 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3925 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3926 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3927 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3928 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3929 | context->root_level = 0; |
6aa8b732 | 3930 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3931 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3932 | context->direct_map = true; |
2d48a985 | 3933 | context->nx = false; |
6aa8b732 AK |
3934 | } |
3935 | ||
d8d173da | 3936 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu) |
6aa8b732 | 3937 | { |
cea0f0e7 | 3938 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3939 | } |
3940 | ||
5777ed34 JR |
3941 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3942 | { | |
9f8fe504 | 3943 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3944 | } |
3945 | ||
6389ee94 AK |
3946 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3947 | struct x86_exception *fault) | |
6aa8b732 | 3948 | { |
6389ee94 | 3949 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3950 | } |
3951 | ||
54bf36aa | 3952 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 3953 | unsigned access, int *nr_present) |
ce88decf XG |
3954 | { |
3955 | if (unlikely(is_mmio_spte(*sptep))) { | |
3956 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3957 | mmu_spte_clear_no_track(sptep); | |
3958 | return true; | |
3959 | } | |
3960 | ||
3961 | (*nr_present)++; | |
54bf36aa | 3962 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3963 | return true; |
3964 | } | |
3965 | ||
3966 | return false; | |
3967 | } | |
3968 | ||
6bb69c9b PB |
3969 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
3970 | unsigned level, unsigned gpte) | |
6fd01b71 | 3971 | { |
6bb69c9b PB |
3972 | /* |
3973 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
3974 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
3975 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
3976 | */ | |
3977 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
6fd01b71 | 3978 | |
6bb69c9b PB |
3979 | /* |
3980 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
3981 | * If it is clear, there are no large pages at this level, so clear | |
3982 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
3983 | */ | |
3984 | gpte &= level - mmu->last_nonleaf_level; | |
3985 | ||
3986 | return gpte & PT_PAGE_SIZE_MASK; | |
6fd01b71 AK |
3987 | } |
3988 | ||
37406aaa NHE |
3989 | #define PTTYPE_EPT 18 /* arbitrary */ |
3990 | #define PTTYPE PTTYPE_EPT | |
3991 | #include "paging_tmpl.h" | |
3992 | #undef PTTYPE | |
3993 | ||
6aa8b732 AK |
3994 | #define PTTYPE 64 |
3995 | #include "paging_tmpl.h" | |
3996 | #undef PTTYPE | |
3997 | ||
3998 | #define PTTYPE 32 | |
3999 | #include "paging_tmpl.h" | |
4000 | #undef PTTYPE | |
4001 | ||
6dc98b86 XG |
4002 | static void |
4003 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4004 | struct rsvd_bits_validate *rsvd_check, | |
4005 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 4006 | bool pse, bool amd) |
82725b20 | 4007 | { |
82725b20 | 4008 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 4009 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4010 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 4011 | |
a0a64f50 | 4012 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4013 | |
6dc98b86 | 4014 | if (!nx) |
82725b20 | 4015 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 4016 | if (!gbpages) |
5f7dde7b | 4017 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
4018 | |
4019 | /* | |
4020 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4021 | * leaf entries) on AMD CPUs only. | |
4022 | */ | |
6fec2144 | 4023 | if (amd) |
a0c0feb5 PB |
4024 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4025 | ||
6dc98b86 | 4026 | switch (level) { |
82725b20 DE |
4027 | case PT32_ROOT_LEVEL: |
4028 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4029 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4030 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4031 | rsvd_check->rsvd_bits_mask[1][0] = | |
4032 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4033 | |
6dc98b86 | 4034 | if (!pse) { |
a0a64f50 | 4035 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4036 | break; |
4037 | } | |
4038 | ||
82725b20 DE |
4039 | if (is_cpuid_PSE36()) |
4040 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4041 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4042 | else |
4043 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4044 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4045 | break; |
4046 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 4047 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 4048 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 4049 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 4050 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 4051 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 4052 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 4053 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 4054 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
4055 | rsvd_bits(maxphyaddr, 62) | |
4056 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4057 | rsvd_check->rsvd_bits_mask[1][0] = |
4058 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4059 | break; |
4060 | case PT64_ROOT_LEVEL: | |
a0a64f50 XG |
4061 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
4062 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 4063 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4064 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
4065 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 4066 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4067 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4068 | rsvd_bits(maxphyaddr, 51); | |
4069 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4070 | rsvd_bits(maxphyaddr, 51); | |
4071 | rsvd_check->rsvd_bits_mask[1][3] = | |
4072 | rsvd_check->rsvd_bits_mask[0][3]; | |
4073 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4074 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4075 | rsvd_bits(13, 29); |
a0a64f50 | 4076 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4077 | rsvd_bits(maxphyaddr, 51) | |
4078 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4079 | rsvd_check->rsvd_bits_mask[1][0] = |
4080 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4081 | break; |
4082 | } | |
4083 | } | |
4084 | ||
6dc98b86 XG |
4085 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4086 | struct kvm_mmu *context) | |
4087 | { | |
4088 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4089 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4090 | context->nx, |
4091 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
6fec2144 | 4092 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
4093 | } |
4094 | ||
81b8eebb XG |
4095 | static void |
4096 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4097 | int maxphyaddr, bool execonly) | |
25d92081 | 4098 | { |
951f9fd7 | 4099 | u64 bad_mt_xwr; |
25d92081 | 4100 | |
a0a64f50 | 4101 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4102 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4103 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4104 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4105 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4106 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4107 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4108 | |
4109 | /* large page */ | |
a0a64f50 XG |
4110 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4111 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4112 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4113 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4114 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4115 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4116 | |
951f9fd7 PB |
4117 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4118 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4119 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4120 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4121 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4122 | if (!execonly) { | |
4123 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4124 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4125 | } |
951f9fd7 | 4126 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4127 | } |
4128 | ||
81b8eebb XG |
4129 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4130 | struct kvm_mmu *context, bool execonly) | |
4131 | { | |
4132 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4133 | cpuid_maxphyaddr(vcpu), execonly); | |
4134 | } | |
4135 | ||
c258b62b XG |
4136 | /* |
4137 | * the page table on host is the shadow page table for the page | |
4138 | * table in guest or amd nested guest, its mmu features completely | |
4139 | * follow the features in guest. | |
4140 | */ | |
4141 | void | |
4142 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4143 | { | |
5f0b8199 PB |
4144 | bool uses_nx = context->nx || context->base_role.smep_andnot_wp; |
4145 | ||
6fec2144 PB |
4146 | /* |
4147 | * Passing "true" to the last argument is okay; it adds a check | |
4148 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4149 | */ | |
c258b62b XG |
4150 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
4151 | boot_cpu_data.x86_phys_bits, | |
5f0b8199 | 4152 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4153 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4154 | is_pse(vcpu), true); | |
c258b62b XG |
4155 | } |
4156 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4157 | ||
6fec2144 PB |
4158 | static inline bool boot_cpu_is_amd(void) |
4159 | { | |
4160 | WARN_ON_ONCE(!tdp_enabled); | |
4161 | return shadow_x_mask == 0; | |
4162 | } | |
4163 | ||
c258b62b XG |
4164 | /* |
4165 | * the direct page table on host, use as much mmu features as | |
4166 | * possible, however, kvm currently does not do execution-protection. | |
4167 | */ | |
4168 | static void | |
4169 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4170 | struct kvm_mmu *context) | |
4171 | { | |
6fec2144 | 4172 | if (boot_cpu_is_amd()) |
c258b62b XG |
4173 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
4174 | boot_cpu_data.x86_phys_bits, | |
4175 | context->shadow_root_level, false, | |
b8291adc BP |
4176 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4177 | true, true); | |
c258b62b XG |
4178 | else |
4179 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4180 | boot_cpu_data.x86_phys_bits, | |
4181 | false); | |
4182 | ||
4183 | } | |
4184 | ||
4185 | /* | |
4186 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4187 | * is the shadow page table for intel nested guest. | |
4188 | */ | |
4189 | static void | |
4190 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4191 | struct kvm_mmu *context, bool execonly) | |
4192 | { | |
4193 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4194 | boot_cpu_data.x86_phys_bits, execonly); | |
4195 | } | |
4196 | ||
edc90b7d XG |
4197 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4198 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 AK |
4199 | { |
4200 | unsigned bit, byte, pfec; | |
4201 | u8 map; | |
66386ade | 4202 | bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0; |
97d64b78 | 4203 | |
66386ade | 4204 | cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
97ec8c06 | 4205 | cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
97d64b78 AK |
4206 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
4207 | pfec = byte << 1; | |
4208 | map = 0; | |
4209 | wf = pfec & PFERR_WRITE_MASK; | |
4210 | uf = pfec & PFERR_USER_MASK; | |
4211 | ff = pfec & PFERR_FETCH_MASK; | |
97ec8c06 FW |
4212 | /* |
4213 | * PFERR_RSVD_MASK bit is set in PFEC if the access is not | |
4214 | * subject to SMAP restrictions, and cleared otherwise. The | |
4215 | * bit is only meaningful if the SMAP bit is set in CR4. | |
4216 | */ | |
4217 | smapf = !(pfec & PFERR_RSVD_MASK); | |
97d64b78 AK |
4218 | for (bit = 0; bit < 8; ++bit) { |
4219 | x = bit & ACC_EXEC_MASK; | |
4220 | w = bit & ACC_WRITE_MASK; | |
4221 | u = bit & ACC_USER_MASK; | |
4222 | ||
25d92081 YZ |
4223 | if (!ept) { |
4224 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4225 | x |= !mmu->nx; | |
4226 | /* Allow supervisor writes if !cr0.wp */ | |
4227 | w |= !is_write_protection(vcpu) && !uf; | |
4228 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
66386ade | 4229 | x &= !(cr4_smep && u && !uf); |
97ec8c06 FW |
4230 | |
4231 | /* | |
4232 | * SMAP:kernel-mode data accesses from user-mode | |
4233 | * mappings should fault. A fault is considered | |
4234 | * as a SMAP violation if all of the following | |
4235 | * conditions are ture: | |
4236 | * - X86_CR4_SMAP is set in CR4 | |
9332ef9d | 4237 | * - A user page is accessed |
97ec8c06 FW |
4238 | * - Page fault in kernel mode |
4239 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4240 | * | |
4241 | * Here, we cover the first three conditions. | |
4242 | * The fourth is computed dynamically in | |
4243 | * permission_fault() and is in smapf. | |
4244 | * | |
4245 | * Also, SMAP does not affect instruction | |
4246 | * fetches, add the !ff check here to make it | |
4247 | * clearer. | |
4248 | */ | |
4249 | smap = cr4_smap && u && !uf && !ff; | |
d95c5568 | 4250 | } |
97d64b78 | 4251 | |
97ec8c06 FW |
4252 | fault = (ff && !x) || (uf && !u) || (wf && !w) || |
4253 | (smapf && smap); | |
97d64b78 AK |
4254 | map |= fault << bit; |
4255 | } | |
4256 | mmu->permissions[byte] = map; | |
4257 | } | |
4258 | } | |
4259 | ||
2d344105 HH |
4260 | /* |
4261 | * PKU is an additional mechanism by which the paging controls access to | |
4262 | * user-mode addresses based on the value in the PKRU register. Protection | |
4263 | * key violations are reported through a bit in the page fault error code. | |
4264 | * Unlike other bits of the error code, the PK bit is not known at the | |
4265 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4266 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4267 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4268 | * | |
4269 | * In particular the following conditions come from the error code, the | |
4270 | * page tables and the machine state: | |
4271 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4272 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4273 | * - PK is always zero if U=0 in the page tables | |
4274 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4275 | * | |
4276 | * The PKRU bitmask caches the result of these four conditions. The error | |
4277 | * code (minus the P bit) and the page table's U bit form an index into the | |
4278 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4279 | * with the two bits of the PKRU register corresponding to the protection key. | |
4280 | * For the first three conditions above the bits will be 00, thus masking | |
4281 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4282 | * only will be masked away. | |
4283 | */ | |
4284 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4285 | bool ept) | |
4286 | { | |
4287 | unsigned bit; | |
4288 | bool wp; | |
4289 | ||
4290 | if (ept) { | |
4291 | mmu->pkru_mask = 0; | |
4292 | return; | |
4293 | } | |
4294 | ||
4295 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4296 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4297 | mmu->pkru_mask = 0; | |
4298 | return; | |
4299 | } | |
4300 | ||
4301 | wp = is_write_protection(vcpu); | |
4302 | ||
4303 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4304 | unsigned pfec, pkey_bits; | |
4305 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4306 | ||
4307 | pfec = bit << 1; | |
4308 | ff = pfec & PFERR_FETCH_MASK; | |
4309 | uf = pfec & PFERR_USER_MASK; | |
4310 | wf = pfec & PFERR_WRITE_MASK; | |
4311 | ||
4312 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4313 | pte_user = pfec & PFERR_RSVD_MASK; | |
4314 | ||
4315 | /* | |
4316 | * Only need to check the access which is not an | |
4317 | * instruction fetch and is to a user page. | |
4318 | */ | |
4319 | check_pkey = (!ff && pte_user); | |
4320 | /* | |
4321 | * write access is controlled by PKRU if it is a | |
4322 | * user access or CR0.WP = 1. | |
4323 | */ | |
4324 | check_write = check_pkey && wf && (uf || wp); | |
4325 | ||
4326 | /* PKRU.AD stops both read and write access. */ | |
4327 | pkey_bits = !!check_pkey; | |
4328 | /* PKRU.WD stops write access. */ | |
4329 | pkey_bits |= (!!check_write) << 1; | |
4330 | ||
4331 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4332 | } | |
4333 | } | |
4334 | ||
6bb69c9b | 4335 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4336 | { |
6bb69c9b PB |
4337 | unsigned root_level = mmu->root_level; |
4338 | ||
4339 | mmu->last_nonleaf_level = root_level; | |
4340 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4341 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4342 | } |
4343 | ||
8a3c1a33 PB |
4344 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4345 | struct kvm_mmu *context, | |
4346 | int level) | |
6aa8b732 | 4347 | { |
2d48a985 | 4348 | context->nx = is_nx(vcpu); |
4d6931c3 | 4349 | context->root_level = level; |
2d48a985 | 4350 | |
4d6931c3 | 4351 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4352 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4353 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4354 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4355 | |
fa4a2c08 | 4356 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4357 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4358 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4359 | context->sync_page = paging64_sync_page; |
a7052897 | 4360 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4361 | context->update_pte = paging64_update_pte; |
17ac10ad | 4362 | context->shadow_root_level = level; |
17c3ba9d | 4363 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4364 | context->direct_map = false; |
6aa8b732 AK |
4365 | } |
4366 | ||
8a3c1a33 PB |
4367 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4368 | struct kvm_mmu *context) | |
17ac10ad | 4369 | { |
8a3c1a33 | 4370 | paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
4371 | } |
4372 | ||
8a3c1a33 PB |
4373 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4374 | struct kvm_mmu *context) | |
6aa8b732 | 4375 | { |
2d48a985 | 4376 | context->nx = false; |
4d6931c3 | 4377 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4378 | |
4d6931c3 | 4379 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4380 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4381 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4382 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4383 | |
6aa8b732 | 4384 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4385 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4386 | context->sync_page = paging32_sync_page; |
a7052897 | 4387 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4388 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4389 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 4390 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4391 | context->direct_map = false; |
6aa8b732 AK |
4392 | } |
4393 | ||
8a3c1a33 PB |
4394 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4395 | struct kvm_mmu *context) | |
6aa8b732 | 4396 | { |
8a3c1a33 | 4397 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4398 | } |
4399 | ||
8a3c1a33 | 4400 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4401 | { |
ad896af0 | 4402 | struct kvm_mmu *context = &vcpu->arch.mmu; |
fb72d167 | 4403 | |
c445f8ef | 4404 | context->base_role.word = 0; |
699023e2 | 4405 | context->base_role.smm = is_smm(vcpu); |
ac8d57e5 | 4406 | context->base_role.ad_disabled = (shadow_accessed_mask == 0); |
fb72d167 | 4407 | context->page_fault = tdp_page_fault; |
e8bc217a | 4408 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4409 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4410 | context->update_pte = nonpaging_update_pte; |
67253af5 | 4411 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 4412 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4413 | context->direct_map = true; |
1c97f0a0 | 4414 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4415 | context->get_cr3 = get_cr3; |
e4e517b4 | 4416 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4417 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4418 | |
4419 | if (!is_paging(vcpu)) { | |
2d48a985 | 4420 | context->nx = false; |
fb72d167 JR |
4421 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4422 | context->root_level = 0; | |
4423 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4424 | context->nx = is_nx(vcpu); |
fb72d167 | 4425 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
4426 | reset_rsvds_bits_mask(vcpu, context); |
4427 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4428 | } else if (is_pae(vcpu)) { |
2d48a985 | 4429 | context->nx = is_nx(vcpu); |
fb72d167 | 4430 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4431 | reset_rsvds_bits_mask(vcpu, context); |
4432 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4433 | } else { |
2d48a985 | 4434 | context->nx = false; |
fb72d167 | 4435 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4436 | reset_rsvds_bits_mask(vcpu, context); |
4437 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4438 | } |
4439 | ||
25d92081 | 4440 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4441 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4442 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4443 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4444 | } |
4445 | ||
ad896af0 | 4446 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) |
6aa8b732 | 4447 | { |
411c588d | 4448 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
edc90b7d | 4449 | bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
ad896af0 PB |
4450 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4451 | ||
fa4a2c08 | 4452 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
6aa8b732 AK |
4453 | |
4454 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4455 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4456 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4457 | paging64_init_context(vcpu, context); |
6aa8b732 | 4458 | else if (is_pae(vcpu)) |
8a3c1a33 | 4459 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4460 | else |
8a3c1a33 | 4461 | paging32_init_context(vcpu, context); |
a770f6f2 | 4462 | |
ad896af0 PB |
4463 | context->base_role.nxe = is_nx(vcpu); |
4464 | context->base_role.cr4_pae = !!is_pae(vcpu); | |
4465 | context->base_role.cr0_wp = is_write_protection(vcpu); | |
4466 | context->base_role.smep_andnot_wp | |
411c588d | 4467 | = smep && !is_write_protection(vcpu); |
edc90b7d XG |
4468 | context->base_role.smap_andnot_wp |
4469 | = smap && !is_write_protection(vcpu); | |
699023e2 | 4470 | context->base_role.smm = is_smm(vcpu); |
c258b62b | 4471 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4472 | } |
4473 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4474 | ||
ae1e2d10 PB |
4475 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
4476 | bool accessed_dirty) | |
155a97a3 | 4477 | { |
ad896af0 PB |
4478 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4479 | ||
fa4a2c08 | 4480 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
155a97a3 NHE |
4481 | |
4482 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); | |
4483 | ||
4484 | context->nx = true; | |
ae1e2d10 | 4485 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4486 | context->page_fault = ept_page_fault; |
4487 | context->gva_to_gpa = ept_gva_to_gpa; | |
4488 | context->sync_page = ept_sync_page; | |
4489 | context->invlpg = ept_invlpg; | |
4490 | context->update_pte = ept_update_pte; | |
155a97a3 NHE |
4491 | context->root_level = context->shadow_root_level; |
4492 | context->root_hpa = INVALID_PAGE; | |
4493 | context->direct_map = false; | |
995f00a6 | 4494 | context->base_role.ad_disabled = !accessed_dirty; |
155a97a3 NHE |
4495 | |
4496 | update_permission_bitmask(vcpu, context, true); | |
2d344105 | 4497 | update_pkru_bitmask(vcpu, context, true); |
155a97a3 | 4498 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4499 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4500 | } |
4501 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4502 | ||
8a3c1a33 | 4503 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4504 | { |
ad896af0 PB |
4505 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4506 | ||
4507 | kvm_init_shadow_mmu(vcpu); | |
4508 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4509 | context->get_cr3 = get_cr3; | |
4510 | context->get_pdptr = kvm_pdptr_read; | |
4511 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4512 | } |
4513 | ||
8a3c1a33 | 4514 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
4515 | { |
4516 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
4517 | ||
4518 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 4519 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4520 | g_context->inject_page_fault = kvm_inject_page_fault; |
4521 | ||
4522 | /* | |
0af2593b DM |
4523 | * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using |
4524 | * L1's nested page tables (e.g. EPT12). The nested translation | |
4525 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4526 | * L2's page tables as the first level of translation and L1's | |
4527 | * nested page tables as the second level of translation. Basically | |
4528 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4529 | */ |
4530 | if (!is_paging(vcpu)) { | |
2d48a985 | 4531 | g_context->nx = false; |
02f59dc9 JR |
4532 | g_context->root_level = 0; |
4533 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4534 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4535 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4536 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 4537 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4538 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4539 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4540 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4541 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4542 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4543 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4544 | } else { | |
2d48a985 | 4545 | g_context->nx = false; |
02f59dc9 | 4546 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4547 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4548 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4549 | } | |
4550 | ||
25d92081 | 4551 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4552 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4553 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4554 | } |
4555 | ||
8a3c1a33 | 4556 | static void init_kvm_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4557 | { |
02f59dc9 | 4558 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4559 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4560 | else if (tdp_enabled) |
e0c6db3e | 4561 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4562 | else |
e0c6db3e | 4563 | init_kvm_softmmu(vcpu); |
fb72d167 JR |
4564 | } |
4565 | ||
8a3c1a33 | 4566 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4567 | { |
95f93af4 | 4568 | kvm_mmu_unload(vcpu); |
8a3c1a33 | 4569 | init_kvm_mmu(vcpu); |
17c3ba9d | 4570 | } |
8668a3c4 | 4571 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4572 | |
4573 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4574 | { |
714b93da AK |
4575 | int r; |
4576 | ||
e2dec939 | 4577 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
4578 | if (r) |
4579 | goto out; | |
8986ecc0 | 4580 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4581 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4582 | if (r) |
4583 | goto out; | |
3662cb1c | 4584 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 4585 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
4586 | out: |
4587 | return r; | |
6aa8b732 | 4588 | } |
17c3ba9d AK |
4589 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4590 | ||
4591 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4592 | { | |
4593 | mmu_free_roots(vcpu); | |
95f93af4 | 4594 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 4595 | } |
4b16184c | 4596 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4597 | |
0028425f | 4598 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4599 | struct kvm_mmu_page *sp, u64 *spte, |
4600 | const void *new) | |
0028425f | 4601 | { |
30945387 | 4602 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
4603 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4604 | return; | |
30945387 | 4605 | } |
0028425f | 4606 | |
4cee5764 | 4607 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 4608 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
4609 | } |
4610 | ||
79539cec AK |
4611 | static bool need_remote_flush(u64 old, u64 new) |
4612 | { | |
4613 | if (!is_shadow_present_pte(old)) | |
4614 | return false; | |
4615 | if (!is_shadow_present_pte(new)) | |
4616 | return true; | |
4617 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4618 | return true; | |
53166229 GN |
4619 | old ^= shadow_nx_mask; |
4620 | new ^= shadow_nx_mask; | |
79539cec AK |
4621 | return (old & ~new & PT64_PERM_MASK) != 0; |
4622 | } | |
4623 | ||
889e5cbc XG |
4624 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
4625 | const u8 *new, int *bytes) | |
da4a00f0 | 4626 | { |
889e5cbc XG |
4627 | u64 gentry; |
4628 | int r; | |
72016f3a | 4629 | |
72016f3a AK |
4630 | /* |
4631 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4632 | * as the current vcpu paging mode since we update the sptes only |
4633 | * when they have the same mode. | |
72016f3a | 4634 | */ |
889e5cbc | 4635 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4636 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4637 | *gpa &= ~(gpa_t)7; |
4638 | *bytes = 8; | |
54bf36aa | 4639 | r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8); |
72016f3a AK |
4640 | if (r) |
4641 | gentry = 0; | |
08e850c6 AK |
4642 | new = (const u8 *)&gentry; |
4643 | } | |
4644 | ||
889e5cbc | 4645 | switch (*bytes) { |
08e850c6 AK |
4646 | case 4: |
4647 | gentry = *(const u32 *)new; | |
4648 | break; | |
4649 | case 8: | |
4650 | gentry = *(const u64 *)new; | |
4651 | break; | |
4652 | default: | |
4653 | gentry = 0; | |
4654 | break; | |
72016f3a AK |
4655 | } |
4656 | ||
889e5cbc XG |
4657 | return gentry; |
4658 | } | |
4659 | ||
4660 | /* | |
4661 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4662 | * or we may be forking, in which case it is better to unmap the page. | |
4663 | */ | |
a138fe75 | 4664 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4665 | { |
a30f47cb XG |
4666 | /* |
4667 | * Skip write-flooding detected for the sp whose level is 1, because | |
4668 | * it can become unsync, then the guest page is not write-protected. | |
4669 | */ | |
f71fa31f | 4670 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4671 | return false; |
3246af0e | 4672 | |
e5691a81 XG |
4673 | atomic_inc(&sp->write_flooding_count); |
4674 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4675 | } |
4676 | ||
4677 | /* | |
4678 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4679 | * indicate a page is not used as a page table. | |
4680 | */ | |
4681 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4682 | int bytes) | |
4683 | { | |
4684 | unsigned offset, pte_size, misaligned; | |
4685 | ||
4686 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4687 | gpa, bytes, sp->role.word); | |
4688 | ||
4689 | offset = offset_in_page(gpa); | |
4690 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4691 | |
4692 | /* | |
4693 | * Sometimes, the OS only writes the last one bytes to update status | |
4694 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4695 | */ | |
4696 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4697 | return false; | |
4698 | ||
889e5cbc XG |
4699 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4700 | misaligned |= bytes < 4; | |
4701 | ||
4702 | return misaligned; | |
4703 | } | |
4704 | ||
4705 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4706 | { | |
4707 | unsigned page_offset, quadrant; | |
4708 | u64 *spte; | |
4709 | int level; | |
4710 | ||
4711 | page_offset = offset_in_page(gpa); | |
4712 | level = sp->role.level; | |
4713 | *nspte = 1; | |
4714 | if (!sp->role.cr4_pae) { | |
4715 | page_offset <<= 1; /* 32->64 */ | |
4716 | /* | |
4717 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4718 | * only 2MB. So we need to double the offset again | |
4719 | * and zap two pdes instead of one. | |
4720 | */ | |
4721 | if (level == PT32_ROOT_LEVEL) { | |
4722 | page_offset &= ~7; /* kill rounding error */ | |
4723 | page_offset <<= 1; | |
4724 | *nspte = 2; | |
4725 | } | |
4726 | quadrant = page_offset >> PAGE_SHIFT; | |
4727 | page_offset &= ~PAGE_MASK; | |
4728 | if (quadrant != sp->role.quadrant) | |
4729 | return NULL; | |
4730 | } | |
4731 | ||
4732 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4733 | return spte; | |
4734 | } | |
4735 | ||
13d268ca | 4736 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
4737 | const u8 *new, int bytes, |
4738 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
4739 | { |
4740 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4741 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4742 | LIST_HEAD(invalid_list); |
4743 | u64 entry, gentry, *spte; | |
4744 | int npte; | |
b8c67b7a | 4745 | bool remote_flush, local_flush; |
4141259b AM |
4746 | union kvm_mmu_page_role mask = { }; |
4747 | ||
4748 | mask.cr0_wp = 1; | |
4749 | mask.cr4_pae = 1; | |
4750 | mask.nxe = 1; | |
4751 | mask.smep_andnot_wp = 1; | |
4752 | mask.smap_andnot_wp = 1; | |
699023e2 | 4753 | mask.smm = 1; |
ac8d57e5 | 4754 | mask.ad_disabled = 1; |
889e5cbc XG |
4755 | |
4756 | /* | |
4757 | * If we don't have indirect shadow pages, it means no page is | |
4758 | * write-protected, so we can exit simply. | |
4759 | */ | |
4760 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4761 | return; | |
4762 | ||
b8c67b7a | 4763 | remote_flush = local_flush = false; |
889e5cbc XG |
4764 | |
4765 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4766 | ||
4767 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4768 | ||
4769 | /* | |
4770 | * No need to care whether allocation memory is successful | |
4771 | * or not since pte prefetch is skiped if it does not have | |
4772 | * enough objects in the cache. | |
4773 | */ | |
4774 | mmu_topup_memory_caches(vcpu); | |
4775 | ||
4776 | spin_lock(&vcpu->kvm->mmu_lock); | |
4777 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4778 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4779 | |
b67bfe0d | 4780 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4781 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4782 | detect_write_flooding(sp)) { |
b8c67b7a | 4783 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4784 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4785 | continue; |
4786 | } | |
889e5cbc XG |
4787 | |
4788 | spte = get_written_sptes(sp, gpa, &npte); | |
4789 | if (!spte) | |
4790 | continue; | |
4791 | ||
0671a8e7 | 4792 | local_flush = true; |
ac1b714e | 4793 | while (npte--) { |
79539cec | 4794 | entry = *spte; |
38e3b2b2 | 4795 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4796 | if (gentry && |
4797 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4798 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4799 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4800 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4801 | remote_flush = true; |
ac1b714e | 4802 | ++spte; |
9b7a0325 | 4803 | } |
9b7a0325 | 4804 | } |
b8c67b7a | 4805 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 4806 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4807 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4808 | } |
4809 | ||
a436036b AK |
4810 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4811 | { | |
10589a46 MT |
4812 | gpa_t gpa; |
4813 | int r; | |
a436036b | 4814 | |
c5a78f2b | 4815 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4816 | return 0; |
4817 | ||
1871c602 | 4818 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4819 | |
10589a46 | 4820 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4821 | |
10589a46 | 4822 | return r; |
a436036b | 4823 | } |
577bdc49 | 4824 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4825 | |
26eeb53c | 4826 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4827 | { |
d98ba053 | 4828 | LIST_HEAD(invalid_list); |
103ad25a | 4829 | |
81f4f76b | 4830 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
26eeb53c | 4831 | return 0; |
81f4f76b | 4832 | |
5da59607 TY |
4833 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4834 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4835 | break; | |
ebeace86 | 4836 | |
4cee5764 | 4837 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4838 | } |
aa6bd187 | 4839 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
26eeb53c WL |
4840 | |
4841 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
4842 | return -ENOSPC; | |
4843 | return 0; | |
ebeace86 | 4844 | } |
ebeace86 | 4845 | |
14727754 | 4846 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code, |
dc25e89e | 4847 | void *insn, int insn_len) |
3067714c | 4848 | { |
1cb3f3ae | 4849 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c | 4850 | enum emulation_result er; |
9034e6e8 | 4851 | bool direct = vcpu->arch.mmu.direct_map; |
3067714c | 4852 | |
618232e2 BS |
4853 | /* With shadow page tables, fault_address contains a GVA or nGPA. */ |
4854 | if (vcpu->arch.mmu.direct_map) { | |
4855 | vcpu->arch.gpa_available = true; | |
4856 | vcpu->arch.gpa_val = cr2; | |
4857 | } | |
4858 | ||
e9ee956e TY |
4859 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
4860 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
4861 | if (r == RET_MMIO_PF_EMULATE) { | |
4862 | emulation_type = 0; | |
4863 | goto emulate; | |
4864 | } | |
4865 | if (r == RET_MMIO_PF_RETRY) | |
4866 | return 1; | |
4867 | if (r < 0) | |
4868 | return r; | |
e08d26f0 | 4869 | /* Must be RET_MMIO_PF_INVALID. */ |
e9ee956e | 4870 | } |
3067714c | 4871 | |
14727754 TL |
4872 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code), |
4873 | false); | |
3067714c | 4874 | if (r < 0) |
e9ee956e TY |
4875 | return r; |
4876 | if (!r) | |
4877 | return 1; | |
3067714c | 4878 | |
14727754 TL |
4879 | /* |
4880 | * Before emulating the instruction, check if the error code | |
4881 | * was due to a RO violation while translating the guest page. | |
4882 | * This can occur when using nested virtualization with nested | |
4883 | * paging in both guests. If true, we simply unprotect the page | |
4884 | * and resume the guest. | |
14727754 | 4885 | */ |
64531a3b | 4886 | if (vcpu->arch.mmu.direct_map && |
eebed243 | 4887 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
14727754 TL |
4888 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2)); |
4889 | return 1; | |
4890 | } | |
4891 | ||
ded58749 | 4892 | if (mmio_info_in_cache(vcpu, cr2, direct)) |
1cb3f3ae | 4893 | emulation_type = 0; |
e9ee956e | 4894 | emulate: |
1cb3f3ae | 4895 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
4896 | |
4897 | switch (er) { | |
4898 | case EMULATE_DONE: | |
4899 | return 1; | |
ac0a48c3 | 4900 | case EMULATE_USER_EXIT: |
3067714c | 4901 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 4902 | /* fall through */ |
3067714c | 4903 | case EMULATE_FAIL: |
3f5d18a9 | 4904 | return 0; |
3067714c AK |
4905 | default: |
4906 | BUG(); | |
4907 | } | |
3067714c AK |
4908 | } |
4909 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4910 | ||
a7052897 MT |
4911 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4912 | { | |
a7052897 | 4913 | vcpu->arch.mmu.invlpg(vcpu, gva); |
77c3913b | 4914 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a7052897 MT |
4915 | ++vcpu->stat.invlpg; |
4916 | } | |
4917 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4918 | ||
18552672 JR |
4919 | void kvm_enable_tdp(void) |
4920 | { | |
4921 | tdp_enabled = true; | |
4922 | } | |
4923 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4924 | ||
5f4cb662 JR |
4925 | void kvm_disable_tdp(void) |
4926 | { | |
4927 | tdp_enabled = false; | |
4928 | } | |
4929 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4930 | ||
6aa8b732 AK |
4931 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4932 | { | |
ad312c7c | 4933 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4934 | if (vcpu->arch.mmu.lm_root != NULL) |
4935 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4936 | } |
4937 | ||
4938 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4939 | { | |
17ac10ad | 4940 | struct page *page; |
6aa8b732 AK |
4941 | int i; |
4942 | ||
17ac10ad AK |
4943 | /* |
4944 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4945 | * Therefore we need to allocate shadow page tables in the first | |
4946 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4947 | */ | |
4948 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4949 | if (!page) | |
d7fa6ab2 WY |
4950 | return -ENOMEM; |
4951 | ||
ad312c7c | 4952 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4953 | for (i = 0; i < 4; ++i) |
ad312c7c | 4954 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4955 | |
6aa8b732 | 4956 | return 0; |
6aa8b732 AK |
4957 | } |
4958 | ||
8018c27b | 4959 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4960 | { |
e459e322 XG |
4961 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
4962 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4963 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4964 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4965 | |
8018c27b IM |
4966 | return alloc_mmu_pages(vcpu); |
4967 | } | |
6aa8b732 | 4968 | |
8a3c1a33 | 4969 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b | 4970 | { |
fa4a2c08 | 4971 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4972 | |
8a3c1a33 | 4973 | init_kvm_mmu(vcpu); |
6aa8b732 AK |
4974 | } |
4975 | ||
b5f5fdca | 4976 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
4977 | struct kvm_memory_slot *slot, |
4978 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca XC |
4979 | { |
4980 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
4981 | } | |
4982 | ||
13d268ca XG |
4983 | void kvm_mmu_init_vm(struct kvm *kvm) |
4984 | { | |
4985 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
4986 | ||
4987 | node->track_write = kvm_mmu_pte_write; | |
b5f5fdca | 4988 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca XG |
4989 | kvm_page_track_register_notifier(kvm, node); |
4990 | } | |
4991 | ||
4992 | void kvm_mmu_uninit_vm(struct kvm *kvm) | |
4993 | { | |
4994 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
4995 | ||
4996 | kvm_page_track_unregister_notifier(kvm, node); | |
4997 | } | |
4998 | ||
1bad2b2a | 4999 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 5000 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
5001 | |
5002 | /* The caller should hold mmu-lock before calling this function. */ | |
5003 | static bool | |
5004 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5005 | slot_level_handler fn, int start_level, int end_level, | |
5006 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5007 | { | |
5008 | struct slot_rmap_walk_iterator iterator; | |
5009 | bool flush = false; | |
5010 | ||
5011 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5012 | end_gfn, &iterator) { | |
5013 | if (iterator.rmap) | |
5014 | flush |= fn(kvm, iterator.rmap); | |
5015 | ||
5016 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5017 | if (flush && lock_flush_tlb) { | |
5018 | kvm_flush_remote_tlbs(kvm); | |
5019 | flush = false; | |
5020 | } | |
5021 | cond_resched_lock(&kvm->mmu_lock); | |
5022 | } | |
5023 | } | |
5024 | ||
5025 | if (flush && lock_flush_tlb) { | |
5026 | kvm_flush_remote_tlbs(kvm); | |
5027 | flush = false; | |
5028 | } | |
5029 | ||
5030 | return flush; | |
5031 | } | |
5032 | ||
5033 | static bool | |
5034 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5035 | slot_level_handler fn, int start_level, int end_level, | |
5036 | bool lock_flush_tlb) | |
5037 | { | |
5038 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5039 | end_level, memslot->base_gfn, | |
5040 | memslot->base_gfn + memslot->npages - 1, | |
5041 | lock_flush_tlb); | |
5042 | } | |
5043 | ||
5044 | static bool | |
5045 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5046 | slot_level_handler fn, bool lock_flush_tlb) | |
5047 | { | |
5048 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5049 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5050 | } | |
5051 | ||
5052 | static bool | |
5053 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5054 | slot_level_handler fn, bool lock_flush_tlb) | |
5055 | { | |
5056 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
5057 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5058 | } | |
5059 | ||
5060 | static bool | |
5061 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5062 | slot_level_handler fn, bool lock_flush_tlb) | |
5063 | { | |
5064 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5065 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
5066 | } | |
5067 | ||
efdfe536 XG |
5068 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5069 | { | |
5070 | struct kvm_memslots *slots; | |
5071 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5072 | int i; |
efdfe536 XG |
5073 | |
5074 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
5075 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5076 | slots = __kvm_memslots(kvm, i); | |
5077 | kvm_for_each_memslot(memslot, slots) { | |
5078 | gfn_t start, end; | |
5079 | ||
5080 | start = max(gfn_start, memslot->base_gfn); | |
5081 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5082 | if (start >= end) | |
5083 | continue; | |
efdfe536 | 5084 | |
9da0e4d5 PB |
5085 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
5086 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
5087 | start, end - 1, true); | |
5088 | } | |
efdfe536 XG |
5089 | } |
5090 | ||
5091 | spin_unlock(&kvm->mmu_lock); | |
5092 | } | |
5093 | ||
018aabb5 TY |
5094 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5095 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5096 | { |
018aabb5 | 5097 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5098 | } |
5099 | ||
1c91cad4 KH |
5100 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
5101 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 5102 | { |
d77aa73c | 5103 | bool flush; |
6aa8b732 | 5104 | |
9d1beefb | 5105 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
5106 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
5107 | false); | |
9d1beefb | 5108 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
5109 | |
5110 | /* | |
5111 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
5112 | * which do tlb flush out of mmu-lock should be serialized by | |
5113 | * kvm->slots_lock otherwise tlb flush would be missed. | |
5114 | */ | |
5115 | lockdep_assert_held(&kvm->slots_lock); | |
5116 | ||
5117 | /* | |
5118 | * We can flush all the TLBs out of the mmu lock without TLB | |
5119 | * corruption since we just change the spte from writable to | |
5120 | * readonly so that we only need to care the case of changing | |
5121 | * spte from present to present (changing the spte from present | |
5122 | * to nonpresent will flush all the TLBs immediately), in other | |
5123 | * words, the only case we care is mmu_spte_update() where we | |
5124 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
5125 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
5126 | * on PT_WRITABLE_MASK anymore. | |
5127 | */ | |
d91ffee9 KH |
5128 | if (flush) |
5129 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 5130 | } |
37a7d8b0 | 5131 | |
3ea3b7fa | 5132 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5133 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5134 | { |
5135 | u64 *sptep; | |
5136 | struct rmap_iterator iter; | |
5137 | int need_tlb_flush = 0; | |
ba049e93 | 5138 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5139 | struct kvm_mmu_page *sp; |
5140 | ||
0d536790 | 5141 | restart: |
018aabb5 | 5142 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
5143 | sp = page_header(__pa(sptep)); |
5144 | pfn = spte_to_pfn(*sptep); | |
5145 | ||
5146 | /* | |
decf6333 XG |
5147 | * We cannot do huge page mapping for indirect shadow pages, |
5148 | * which are found on the last rmap (level = 1) when not using | |
5149 | * tdp; such shadow pages are synced with the page table in | |
5150 | * the guest, and the guest page table is using 4K page size | |
5151 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
5152 | */ |
5153 | if (sp->role.direct && | |
5154 | !kvm_is_reserved_pfn(pfn) && | |
127393fb | 5155 | PageTransCompoundMap(pfn_to_page(pfn))) { |
3ea3b7fa | 5156 | drop_spte(kvm, sptep); |
3ea3b7fa | 5157 | need_tlb_flush = 1; |
0d536790 XG |
5158 | goto restart; |
5159 | } | |
3ea3b7fa WL |
5160 | } |
5161 | ||
5162 | return need_tlb_flush; | |
5163 | } | |
5164 | ||
5165 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5166 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5167 | { |
f36f3f28 | 5168 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5169 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5170 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5171 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5172 | spin_unlock(&kvm->mmu_lock); |
5173 | } | |
5174 | ||
f4b4b180 KH |
5175 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5176 | struct kvm_memory_slot *memslot) | |
5177 | { | |
d77aa73c | 5178 | bool flush; |
f4b4b180 KH |
5179 | |
5180 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5181 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5182 | spin_unlock(&kvm->mmu_lock); |
5183 | ||
5184 | lockdep_assert_held(&kvm->slots_lock); | |
5185 | ||
5186 | /* | |
5187 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5188 | * function is only used for dirty logging, in which case flushing TLB | |
5189 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5190 | * dirty_bitmap. | |
5191 | */ | |
5192 | if (flush) | |
5193 | kvm_flush_remote_tlbs(kvm); | |
5194 | } | |
5195 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5196 | ||
5197 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5198 | struct kvm_memory_slot *memslot) | |
5199 | { | |
d77aa73c | 5200 | bool flush; |
f4b4b180 KH |
5201 | |
5202 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5203 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5204 | false); | |
f4b4b180 KH |
5205 | spin_unlock(&kvm->mmu_lock); |
5206 | ||
5207 | /* see kvm_mmu_slot_remove_write_access */ | |
5208 | lockdep_assert_held(&kvm->slots_lock); | |
5209 | ||
5210 | if (flush) | |
5211 | kvm_flush_remote_tlbs(kvm); | |
5212 | } | |
5213 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5214 | ||
5215 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5216 | struct kvm_memory_slot *memslot) | |
5217 | { | |
d77aa73c | 5218 | bool flush; |
f4b4b180 KH |
5219 | |
5220 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5221 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5222 | spin_unlock(&kvm->mmu_lock); |
5223 | ||
5224 | lockdep_assert_held(&kvm->slots_lock); | |
5225 | ||
5226 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
5227 | if (flush) | |
5228 | kvm_flush_remote_tlbs(kvm); | |
5229 | } | |
5230 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5231 | ||
e7d11c7a | 5232 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
5233 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5234 | { | |
5235 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 5236 | int batch = 0; |
5304b8d3 XG |
5237 | |
5238 | restart: | |
5239 | list_for_each_entry_safe_reverse(sp, node, | |
5240 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
5241 | int ret; |
5242 | ||
5304b8d3 XG |
5243 | /* |
5244 | * No obsolete page exists before new created page since | |
5245 | * active_mmu_pages is the FIFO list. | |
5246 | */ | |
5247 | if (!is_obsolete_sp(kvm, sp)) | |
5248 | break; | |
5249 | ||
5250 | /* | |
5304b8d3 XG |
5251 | * Since we are reversely walking the list and the invalid |
5252 | * list will be moved to the head, skip the invalid page | |
5253 | * can help us to avoid the infinity list walking. | |
5254 | */ | |
5255 | if (sp->role.invalid) | |
5256 | continue; | |
5257 | ||
f34d251d XG |
5258 | /* |
5259 | * Need not flush tlb since we only zap the sp with invalid | |
5260 | * generation number. | |
5261 | */ | |
e7d11c7a | 5262 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 5263 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 5264 | batch = 0; |
5304b8d3 XG |
5265 | goto restart; |
5266 | } | |
5267 | ||
365c8868 XG |
5268 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
5269 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
5270 | batch += ret; |
5271 | ||
5272 | if (ret) | |
5304b8d3 XG |
5273 | goto restart; |
5274 | } | |
5275 | ||
f34d251d XG |
5276 | /* |
5277 | * Should flush tlb before free page tables since lockless-walking | |
5278 | * may use the pages. | |
5279 | */ | |
365c8868 | 5280 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
5281 | } |
5282 | ||
5283 | /* | |
5284 | * Fast invalidate all shadow pages and use lock-break technique | |
5285 | * to zap obsolete pages. | |
5286 | * | |
5287 | * It's required when memslot is being deleted or VM is being | |
5288 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5289 | * not use any resource of the being-deleted slot or all slots | |
5290 | * after calling the function. | |
5291 | */ | |
5292 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
5293 | { | |
5294 | spin_lock(&kvm->mmu_lock); | |
35006126 | 5295 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
5296 | kvm->arch.mmu_valid_gen++; |
5297 | ||
f34d251d XG |
5298 | /* |
5299 | * Notify all vcpus to reload its shadow page table | |
5300 | * and flush TLB. Then all vcpus will switch to new | |
5301 | * shadow page table with the new mmu_valid_gen. | |
5302 | * | |
5303 | * Note: we should do this under the protection of | |
5304 | * mmu-lock, otherwise, vcpu would purge shadow page | |
5305 | * but miss tlb flush. | |
5306 | */ | |
5307 | kvm_reload_remote_mmus(kvm); | |
5308 | ||
5304b8d3 XG |
5309 | kvm_zap_obsolete_pages(kvm); |
5310 | spin_unlock(&kvm->mmu_lock); | |
5311 | } | |
5312 | ||
365c8868 XG |
5313 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5314 | { | |
5315 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5316 | } | |
5317 | ||
54bf36aa | 5318 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots) |
f8f55942 XG |
5319 | { |
5320 | /* | |
5321 | * The very rare case: if the generation-number is round, | |
5322 | * zap all shadow pages. | |
f8f55942 | 5323 | */ |
54bf36aa | 5324 | if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) { |
ae0f5499 | 5325 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 5326 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 5327 | } |
f8f55942 XG |
5328 | } |
5329 | ||
70534a73 DC |
5330 | static unsigned long |
5331 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5332 | { |
5333 | struct kvm *kvm; | |
1495f230 | 5334 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5335 | unsigned long freed = 0; |
3ee16c81 | 5336 | |
2f303b74 | 5337 | spin_lock(&kvm_lock); |
3ee16c81 IE |
5338 | |
5339 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5340 | int idx; |
d98ba053 | 5341 | LIST_HEAD(invalid_list); |
3ee16c81 | 5342 | |
35f2d16b TY |
5343 | /* |
5344 | * Never scan more than sc->nr_to_scan VM instances. | |
5345 | * Will not hit this condition practically since we do not try | |
5346 | * to shrink more than one VM and it is very unlikely to see | |
5347 | * !n_used_mmu_pages so many times. | |
5348 | */ | |
5349 | if (!nr_to_scan--) | |
5350 | break; | |
19526396 GN |
5351 | /* |
5352 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5353 | * here. We may skip a VM instance errorneosly, but we do not | |
5354 | * want to shrink a VM that only started to populate its MMU | |
5355 | * anyway. | |
5356 | */ | |
365c8868 XG |
5357 | if (!kvm->arch.n_used_mmu_pages && |
5358 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5359 | continue; |
19526396 | 5360 | |
f656ce01 | 5361 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5362 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5363 | |
365c8868 XG |
5364 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5365 | kvm_mmu_commit_zap_page(kvm, | |
5366 | &kvm->arch.zapped_obsolete_pages); | |
5367 | goto unlock; | |
5368 | } | |
5369 | ||
70534a73 DC |
5370 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5371 | freed++; | |
d98ba053 | 5372 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5373 | |
365c8868 | 5374 | unlock: |
3ee16c81 | 5375 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5376 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5377 | |
70534a73 DC |
5378 | /* |
5379 | * unfair on small ones | |
5380 | * per-vm shrinkers cry out | |
5381 | * sadness comes quickly | |
5382 | */ | |
19526396 GN |
5383 | list_move_tail(&kvm->vm_list, &vm_list); |
5384 | break; | |
3ee16c81 | 5385 | } |
3ee16c81 | 5386 | |
2f303b74 | 5387 | spin_unlock(&kvm_lock); |
70534a73 | 5388 | return freed; |
70534a73 DC |
5389 | } |
5390 | ||
5391 | static unsigned long | |
5392 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5393 | { | |
45221ab6 | 5394 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5395 | } |
5396 | ||
5397 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5398 | .count_objects = mmu_shrink_count, |
5399 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5400 | .seeks = DEFAULT_SEEKS * 10, |
5401 | }; | |
5402 | ||
2ddfd20e | 5403 | static void mmu_destroy_caches(void) |
b5a33a75 | 5404 | { |
53c07b18 XG |
5405 | if (pte_list_desc_cache) |
5406 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
5407 | if (mmu_page_header_cache) |
5408 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5409 | } |
5410 | ||
5411 | int kvm_mmu_module_init(void) | |
5412 | { | |
f160c7b7 JS |
5413 | kvm_mmu_clear_all_pte_masks(); |
5414 | ||
53c07b18 XG |
5415 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5416 | sizeof(struct pte_list_desc), | |
20c2df83 | 5417 | 0, 0, NULL); |
53c07b18 | 5418 | if (!pte_list_desc_cache) |
b5a33a75 AK |
5419 | goto nomem; |
5420 | ||
d3d25b04 AK |
5421 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5422 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 5423 | 0, 0, NULL); |
d3d25b04 AK |
5424 | if (!mmu_page_header_cache) |
5425 | goto nomem; | |
5426 | ||
908c7f19 | 5427 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
45bf21a8 WY |
5428 | goto nomem; |
5429 | ||
3ee16c81 IE |
5430 | register_shrinker(&mmu_shrinker); |
5431 | ||
b5a33a75 AK |
5432 | return 0; |
5433 | ||
5434 | nomem: | |
3ee16c81 | 5435 | mmu_destroy_caches(); |
b5a33a75 AK |
5436 | return -ENOMEM; |
5437 | } | |
5438 | ||
3ad82a7e ZX |
5439 | /* |
5440 | * Caculate mmu pages needed for kvm. | |
5441 | */ | |
5442 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
5443 | { | |
3ad82a7e ZX |
5444 | unsigned int nr_mmu_pages; |
5445 | unsigned int nr_pages = 0; | |
bc6678a3 | 5446 | struct kvm_memslots *slots; |
be6ba0f0 | 5447 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5448 | int i; |
3ad82a7e | 5449 | |
9da0e4d5 PB |
5450 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5451 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5452 | |
9da0e4d5 PB |
5453 | kvm_for_each_memslot(memslot, slots) |
5454 | nr_pages += memslot->npages; | |
5455 | } | |
3ad82a7e ZX |
5456 | |
5457 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
5458 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 5459 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5460 | |
5461 | return nr_mmu_pages; | |
5462 | } | |
5463 | ||
c42fffe3 XG |
5464 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5465 | { | |
95f93af4 | 5466 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
5467 | free_mmu_pages(vcpu); |
5468 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
5469 | } |
5470 | ||
b034cf01 XG |
5471 | void kvm_mmu_module_exit(void) |
5472 | { | |
5473 | mmu_destroy_caches(); | |
5474 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5475 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5476 | mmu_audit_disable(); |
5477 | } |