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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
1767e931 PG |
32 | #include <linux/moduleparam.h> |
33 | #include <linux/export.h> | |
448353ca | 34 | #include <linux/swap.h> |
05da4558 | 35 | #include <linux/hugetlb.h> |
2f333bcb | 36 | #include <linux/compiler.h> |
bc6678a3 | 37 | #include <linux/srcu.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
3f07c014 | 39 | #include <linux/sched/signal.h> |
bf998156 | 40 | #include <linux/uaccess.h> |
114df303 | 41 | #include <linux/hash.h> |
f160c7b7 | 42 | #include <linux/kern_levels.h> |
6aa8b732 | 43 | |
e495606d | 44 | #include <asm/page.h> |
aa2e063a | 45 | #include <asm/pat.h> |
e495606d | 46 | #include <asm/cmpxchg.h> |
0c55671f | 47 | #include <asm/e820/api.h> |
4e542370 | 48 | #include <asm/io.h> |
13673a90 | 49 | #include <asm/vmx.h> |
3d0c27ad | 50 | #include <asm/kvm_page_track.h> |
1261bfa3 | 51 | #include "trace.h" |
6aa8b732 | 52 | |
18552672 JR |
53 | /* |
54 | * When setting this variable to true it enables Two-Dimensional-Paging | |
55 | * where the hardware walks 2 page tables: | |
56 | * 1. the guest-virtual to guest-physical | |
57 | * 2. while doing 1. it walks guest-physical to host-physical | |
58 | * If the hardware supports that we don't need to do shadow paging. | |
59 | */ | |
2f333bcb | 60 | bool tdp_enabled = false; |
18552672 | 61 | |
8b1fe17c XG |
62 | enum { |
63 | AUDIT_PRE_PAGE_FAULT, | |
64 | AUDIT_POST_PAGE_FAULT, | |
65 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
66 | AUDIT_POST_PTE_WRITE, |
67 | AUDIT_PRE_SYNC, | |
68 | AUDIT_POST_SYNC | |
8b1fe17c | 69 | }; |
37a7d8b0 | 70 | |
8b1fe17c | 71 | #undef MMU_DEBUG |
37a7d8b0 AK |
72 | |
73 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
74 | static bool dbg = 0; |
75 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
76 | |
77 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
78 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 79 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 80 | #else |
37a7d8b0 AK |
81 | #define pgprintk(x...) do { } while (0) |
82 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 83 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 84 | #endif |
6aa8b732 | 85 | |
957ed9ef XG |
86 | #define PTE_PREFETCH_NUM 8 |
87 | ||
00763e41 | 88 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
89 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
90 | ||
6aa8b732 AK |
91 | #define PT64_LEVEL_BITS 9 |
92 | ||
93 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 94 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 95 | |
6aa8b732 AK |
96 | #define PT64_INDEX(address, level)\ |
97 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
98 | ||
99 | ||
100 | #define PT32_LEVEL_BITS 10 | |
101 | ||
102 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 103 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 104 | |
e04da980 JR |
105 | #define PT32_LVL_OFFSET_MASK(level) \ |
106 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
107 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
108 | |
109 | #define PT32_INDEX(address, level)\ | |
110 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
111 | ||
112 | ||
8acc0993 KH |
113 | #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK |
114 | #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1)) | |
115 | #else | |
116 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) | |
117 | #endif | |
e04da980 JR |
118 | #define PT64_LVL_ADDR_MASK(level) \ |
119 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
120 | * PT64_LEVEL_BITS))) - 1)) | |
121 | #define PT64_LVL_OFFSET_MASK(level) \ | |
122 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
124 | |
125 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
126 | #define PT32_DIR_BASE_ADDR_MASK \ | |
127 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
128 | #define PT32_LVL_ADDR_MASK(level) \ |
129 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
130 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 131 | |
53166229 | 132 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
d0ec49d4 | 133 | | shadow_x_mask | shadow_nx_mask | shadow_me_mask) |
6aa8b732 | 134 | |
fe135d2c AK |
135 | #define ACC_EXEC_MASK 1 |
136 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
137 | #define ACC_USER_MASK PT_USER_MASK | |
138 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
139 | ||
f160c7b7 JS |
140 | /* The mask for the R/X bits in EPT PTEs */ |
141 | #define PT64_EPT_READABLE_MASK 0x1ull | |
142 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
143 | ||
90bb6fc5 AK |
144 | #include <trace/events/kvm.h> |
145 | ||
07420171 AK |
146 | #define CREATE_TRACE_POINTS |
147 | #include "mmutrace.h" | |
148 | ||
49fde340 XG |
149 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
150 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 151 | |
135f8c2b AK |
152 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
153 | ||
220f773a TY |
154 | /* make pte_list_desc fit well in cache line */ |
155 | #define PTE_LIST_EXT 3 | |
156 | ||
9b8ebbdb PB |
157 | /* |
158 | * Return values of handle_mmio_page_fault and mmu.page_fault: | |
159 | * RET_PF_RETRY: let CPU fault again on the address. | |
160 | * RET_PF_EMULATE: mmio page fault, emulate the instruction directly. | |
161 | * | |
162 | * For handle_mmio_page_fault only: | |
163 | * RET_PF_INVALID: the spte is invalid, let the real page fault path update it. | |
164 | */ | |
165 | enum { | |
166 | RET_PF_RETRY = 0, | |
167 | RET_PF_EMULATE = 1, | |
168 | RET_PF_INVALID = 2, | |
169 | }; | |
170 | ||
53c07b18 XG |
171 | struct pte_list_desc { |
172 | u64 *sptes[PTE_LIST_EXT]; | |
173 | struct pte_list_desc *more; | |
cd4a4e53 AK |
174 | }; |
175 | ||
2d11123a AK |
176 | struct kvm_shadow_walk_iterator { |
177 | u64 addr; | |
178 | hpa_t shadow_addr; | |
2d11123a | 179 | u64 *sptep; |
dd3bfd59 | 180 | int level; |
2d11123a AK |
181 | unsigned index; |
182 | }; | |
183 | ||
9fa72119 JS |
184 | static const union kvm_mmu_page_role mmu_base_role_mask = { |
185 | .cr0_wp = 1, | |
47c42e6b | 186 | .gpte_is_8_bytes = 1, |
9fa72119 JS |
187 | .nxe = 1, |
188 | .smep_andnot_wp = 1, | |
189 | .smap_andnot_wp = 1, | |
190 | .smm = 1, | |
191 | .guest_mode = 1, | |
192 | .ad_disabled = 1, | |
193 | }; | |
194 | ||
7eb77e9f JS |
195 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
196 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
197 | (_root), (_addr)); \ | |
198 | shadow_walk_okay(&(_walker)); \ | |
199 | shadow_walk_next(&(_walker))) | |
200 | ||
201 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
202 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
203 | shadow_walk_okay(&(_walker)); \ | |
204 | shadow_walk_next(&(_walker))) | |
205 | ||
c2a2ac2b XG |
206 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
207 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
208 | shadow_walk_okay(&(_walker)) && \ | |
209 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
210 | __shadow_walk_next(&(_walker), spte)) | |
211 | ||
53c07b18 | 212 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 213 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 214 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 215 | |
7b52345e SY |
216 | static u64 __read_mostly shadow_nx_mask; |
217 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
218 | static u64 __read_mostly shadow_user_mask; | |
219 | static u64 __read_mostly shadow_accessed_mask; | |
220 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 221 | static u64 __read_mostly shadow_mmio_mask; |
dcdca5fe | 222 | static u64 __read_mostly shadow_mmio_value; |
ffb128c8 | 223 | static u64 __read_mostly shadow_present_mask; |
d0ec49d4 | 224 | static u64 __read_mostly shadow_me_mask; |
ce88decf | 225 | |
f160c7b7 | 226 | /* |
ac8d57e5 PF |
227 | * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value. |
228 | * Non-present SPTEs with shadow_acc_track_value set are in place for access | |
229 | * tracking. | |
f160c7b7 JS |
230 | */ |
231 | static u64 __read_mostly shadow_acc_track_mask; | |
232 | static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK; | |
233 | ||
234 | /* | |
235 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
236 | * as not-present for access tracking purposes. We do not save the W bit as the | |
237 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
238 | * restored only when a write is attempted to the page. | |
239 | */ | |
240 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
241 | PT64_EPT_EXECUTABLE_MASK; | |
242 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
243 | ||
28a1f3ac JS |
244 | /* |
245 | * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order | |
246 | * to guard against L1TF attacks. | |
247 | */ | |
248 | static u64 __read_mostly shadow_nonpresent_or_rsvd_mask; | |
249 | ||
250 | /* | |
251 | * The number of high-order 1 bits to use in the mask above. | |
252 | */ | |
253 | static const u64 shadow_nonpresent_or_rsvd_mask_len = 5; | |
254 | ||
daa07cbc SC |
255 | /* |
256 | * In some cases, we need to preserve the GFN of a non-present or reserved | |
257 | * SPTE when we usurp the upper five bits of the physical address space to | |
258 | * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll | |
259 | * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask | |
260 | * left into the reserved bits, i.e. the GFN in the SPTE will be split into | |
261 | * high and low parts. This mask covers the lower bits of the GFN. | |
262 | */ | |
263 | static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; | |
264 | ||
f3ecb59d KH |
265 | /* |
266 | * The number of non-reserved physical address bits irrespective of features | |
267 | * that repurpose legal bits, e.g. MKTME. | |
268 | */ | |
269 | static u8 __read_mostly shadow_phys_bits; | |
daa07cbc | 270 | |
ce88decf | 271 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
272 | static union kvm_mmu_page_role |
273 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 274 | |
40ef75a7 LT |
275 | |
276 | static inline bool kvm_available_flush_tlb_with_range(void) | |
277 | { | |
278 | return kvm_x86_ops->tlb_remote_flush_with_range; | |
279 | } | |
280 | ||
281 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
282 | struct kvm_tlb_range *range) | |
283 | { | |
284 | int ret = -ENOTSUPP; | |
285 | ||
286 | if (range && kvm_x86_ops->tlb_remote_flush_with_range) | |
287 | ret = kvm_x86_ops->tlb_remote_flush_with_range(kvm, range); | |
288 | ||
289 | if (ret) | |
290 | kvm_flush_remote_tlbs(kvm); | |
291 | } | |
292 | ||
293 | static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, | |
294 | u64 start_gfn, u64 pages) | |
295 | { | |
296 | struct kvm_tlb_range range; | |
297 | ||
298 | range.start_gfn = start_gfn; | |
299 | range.pages = pages; | |
300 | ||
301 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
302 | } | |
303 | ||
dcdca5fe | 304 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value) |
ce88decf | 305 | { |
dcdca5fe PF |
306 | BUG_ON((mmio_mask & mmio_value) != mmio_value); |
307 | shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK; | |
312b616b | 308 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
ce88decf XG |
309 | } |
310 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
311 | ||
ac8d57e5 PF |
312 | static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) |
313 | { | |
314 | return sp->role.ad_disabled; | |
315 | } | |
316 | ||
317 | static inline bool spte_ad_enabled(u64 spte) | |
318 | { | |
319 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
320 | return !(spte & shadow_acc_track_value); | |
321 | } | |
322 | ||
323 | static inline u64 spte_shadow_accessed_mask(u64 spte) | |
324 | { | |
325 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
326 | return spte_ad_enabled(spte) ? shadow_accessed_mask : 0; | |
327 | } | |
328 | ||
329 | static inline u64 spte_shadow_dirty_mask(u64 spte) | |
330 | { | |
331 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
332 | return spte_ad_enabled(spte) ? shadow_dirty_mask : 0; | |
333 | } | |
334 | ||
f160c7b7 JS |
335 | static inline bool is_access_track_spte(u64 spte) |
336 | { | |
ac8d57e5 | 337 | return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0; |
f160c7b7 JS |
338 | } |
339 | ||
f2fd125d | 340 | /* |
cae7ed3c SC |
341 | * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of |
342 | * the memslots generation and is derived as follows: | |
ee3d1570 | 343 | * |
164bf7e5 SC |
344 | * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11 |
345 | * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61 | |
cae7ed3c | 346 | * |
164bf7e5 SC |
347 | * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in |
348 | * the MMIO generation number, as doing so would require stealing a bit from | |
349 | * the "real" generation number and thus effectively halve the maximum number | |
350 | * of MMIO generations that can be handled before encountering a wrap (which | |
351 | * requires a full MMU zap). The flag is instead explicitly queried when | |
352 | * checking for MMIO spte cache hits. | |
f2fd125d | 353 | */ |
164bf7e5 | 354 | #define MMIO_SPTE_GEN_MASK GENMASK_ULL(18, 0) |
f2fd125d | 355 | |
cae7ed3c SC |
356 | #define MMIO_SPTE_GEN_LOW_START 3 |
357 | #define MMIO_SPTE_GEN_LOW_END 11 | |
358 | #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \ | |
359 | MMIO_SPTE_GEN_LOW_START) | |
f2fd125d | 360 | |
cae7ed3c SC |
361 | #define MMIO_SPTE_GEN_HIGH_START 52 |
362 | #define MMIO_SPTE_GEN_HIGH_END 61 | |
363 | #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \ | |
364 | MMIO_SPTE_GEN_HIGH_START) | |
5192f9b9 | 365 | static u64 generation_mmio_spte_mask(u64 gen) |
f2fd125d XG |
366 | { |
367 | u64 mask; | |
368 | ||
cae7ed3c | 369 | WARN_ON(gen & ~MMIO_SPTE_GEN_MASK); |
f2fd125d | 370 | |
cae7ed3c SC |
371 | mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK; |
372 | mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK; | |
f2fd125d XG |
373 | return mask; |
374 | } | |
375 | ||
5192f9b9 | 376 | static u64 get_mmio_spte_generation(u64 spte) |
f2fd125d | 377 | { |
5192f9b9 | 378 | u64 gen; |
f2fd125d XG |
379 | |
380 | spte &= ~shadow_mmio_mask; | |
381 | ||
cae7ed3c SC |
382 | gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START; |
383 | gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START; | |
f2fd125d XG |
384 | return gen; |
385 | } | |
386 | ||
54bf36aa | 387 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 388 | unsigned access) |
ce88decf | 389 | { |
cae7ed3c | 390 | u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; |
f8f55942 | 391 | u64 mask = generation_mmio_spte_mask(gen); |
28a1f3ac | 392 | u64 gpa = gfn << PAGE_SHIFT; |
95b0430d | 393 | |
ce88decf | 394 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
28a1f3ac JS |
395 | mask |= shadow_mmio_value | access; |
396 | mask |= gpa | shadow_nonpresent_or_rsvd_mask; | |
397 | mask |= (gpa & shadow_nonpresent_or_rsvd_mask) | |
398 | << shadow_nonpresent_or_rsvd_mask_len; | |
f2fd125d | 399 | |
4771450c SC |
400 | page_header(__pa(sptep))->mmio_cached = true; |
401 | ||
f8f55942 | 402 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 403 | mmu_spte_set(sptep, mask); |
ce88decf XG |
404 | } |
405 | ||
406 | static bool is_mmio_spte(u64 spte) | |
407 | { | |
dcdca5fe | 408 | return (spte & shadow_mmio_mask) == shadow_mmio_value; |
ce88decf XG |
409 | } |
410 | ||
411 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
412 | { | |
daa07cbc | 413 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac JS |
414 | |
415 | gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len) | |
416 | & shadow_nonpresent_or_rsvd_mask; | |
417 | ||
418 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
419 | } |
420 | ||
421 | static unsigned get_mmio_spte_access(u64 spte) | |
422 | { | |
cae7ed3c | 423 | u64 mask = generation_mmio_spte_mask(MMIO_SPTE_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 424 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
425 | } |
426 | ||
54bf36aa | 427 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 428 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
429 | { |
430 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 431 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
432 | return true; |
433 | } | |
434 | ||
435 | return false; | |
436 | } | |
c7addb90 | 437 | |
54bf36aa | 438 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 439 | { |
cae7ed3c | 440 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 441 | |
cae7ed3c SC |
442 | gen = kvm_vcpu_memslots(vcpu)->generation; |
443 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
444 | return false; | |
089504c0 | 445 | |
cae7ed3c | 446 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
447 | spte_gen = get_mmio_spte_generation(spte); |
448 | ||
449 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
450 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
451 | } |
452 | ||
ce00053b PF |
453 | /* |
454 | * Sets the shadow PTE masks used by the MMU. | |
455 | * | |
456 | * Assumptions: | |
457 | * - Setting either @accessed_mask or @dirty_mask requires setting both | |
458 | * - At least one of @accessed_mask or @acc_track_mask must be set | |
459 | */ | |
7b52345e | 460 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 461 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 462 | u64 acc_track_mask, u64 me_mask) |
7b52345e | 463 | { |
ce00053b PF |
464 | BUG_ON(!dirty_mask != !accessed_mask); |
465 | BUG_ON(!accessed_mask && !acc_track_mask); | |
ac8d57e5 | 466 | BUG_ON(acc_track_mask & shadow_acc_track_value); |
312b616b | 467 | |
7b52345e SY |
468 | shadow_user_mask = user_mask; |
469 | shadow_accessed_mask = accessed_mask; | |
470 | shadow_dirty_mask = dirty_mask; | |
471 | shadow_nx_mask = nx_mask; | |
472 | shadow_x_mask = x_mask; | |
ffb128c8 | 473 | shadow_present_mask = p_mask; |
f160c7b7 | 474 | shadow_acc_track_mask = acc_track_mask; |
d0ec49d4 | 475 | shadow_me_mask = me_mask; |
7b52345e SY |
476 | } |
477 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
478 | ||
f3ecb59d KH |
479 | static u8 kvm_get_shadow_phys_bits(void) |
480 | { | |
481 | /* | |
482 | * boot_cpu_data.x86_phys_bits is reduced when MKTME is detected | |
483 | * in CPU detection code, but MKTME treats those reduced bits as | |
484 | * 'keyID' thus they are not reserved bits. Therefore for MKTME | |
485 | * we should still return physical address bits reported by CPUID. | |
486 | */ | |
487 | if (!boot_cpu_has(X86_FEATURE_TME) || | |
488 | WARN_ON_ONCE(boot_cpu_data.extended_cpuid_level < 0x80000008)) | |
489 | return boot_cpu_data.x86_phys_bits; | |
490 | ||
491 | return cpuid_eax(0x80000008) & 0xff; | |
492 | } | |
493 | ||
28a1f3ac | 494 | static void kvm_mmu_reset_all_pte_masks(void) |
f160c7b7 | 495 | { |
daa07cbc SC |
496 | u8 low_phys_bits; |
497 | ||
f160c7b7 JS |
498 | shadow_user_mask = 0; |
499 | shadow_accessed_mask = 0; | |
500 | shadow_dirty_mask = 0; | |
501 | shadow_nx_mask = 0; | |
502 | shadow_x_mask = 0; | |
503 | shadow_mmio_mask = 0; | |
504 | shadow_present_mask = 0; | |
505 | shadow_acc_track_mask = 0; | |
28a1f3ac | 506 | |
f3ecb59d KH |
507 | shadow_phys_bits = kvm_get_shadow_phys_bits(); |
508 | ||
28a1f3ac JS |
509 | /* |
510 | * If the CPU has 46 or less physical address bits, then set an | |
511 | * appropriate mask to guard against L1TF attacks. Otherwise, it is | |
512 | * assumed that the CPU is not vulnerable to L1TF. | |
61455bf2 KH |
513 | * |
514 | * Some Intel CPUs address the L1 cache using more PA bits than are | |
515 | * reported by CPUID. Use the PA width of the L1 cache when possible | |
516 | * to achieve more effective mitigation, e.g. if system RAM overlaps | |
517 | * the most significant bits of legal physical address space. | |
28a1f3ac | 518 | */ |
61455bf2 KH |
519 | shadow_nonpresent_or_rsvd_mask = 0; |
520 | low_phys_bits = boot_cpu_data.x86_cache_bits; | |
521 | if (boot_cpu_data.x86_cache_bits < | |
daa07cbc | 522 | 52 - shadow_nonpresent_or_rsvd_mask_len) { |
28a1f3ac | 523 | shadow_nonpresent_or_rsvd_mask = |
61455bf2 | 524 | rsvd_bits(boot_cpu_data.x86_cache_bits - |
28a1f3ac | 525 | shadow_nonpresent_or_rsvd_mask_len, |
61455bf2 | 526 | boot_cpu_data.x86_cache_bits - 1); |
daa07cbc | 527 | low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len; |
61455bf2 KH |
528 | } else |
529 | WARN_ON_ONCE(boot_cpu_has_bug(X86_BUG_L1TF)); | |
530 | ||
daa07cbc SC |
531 | shadow_nonpresent_or_rsvd_lower_gfn_mask = |
532 | GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); | |
f160c7b7 JS |
533 | } |
534 | ||
6aa8b732 AK |
535 | static int is_cpuid_PSE36(void) |
536 | { | |
537 | return 1; | |
538 | } | |
539 | ||
73b1087e AK |
540 | static int is_nx(struct kvm_vcpu *vcpu) |
541 | { | |
f6801dff | 542 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
543 | } |
544 | ||
c7addb90 AK |
545 | static int is_shadow_present_pte(u64 pte) |
546 | { | |
f160c7b7 | 547 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
548 | } |
549 | ||
05da4558 MT |
550 | static int is_large_pte(u64 pte) |
551 | { | |
552 | return pte & PT_PAGE_SIZE_MASK; | |
553 | } | |
554 | ||
776e6633 MT |
555 | static int is_last_spte(u64 pte, int level) |
556 | { | |
557 | if (level == PT_PAGE_TABLE_LEVEL) | |
558 | return 1; | |
852e3c19 | 559 | if (is_large_pte(pte)) |
776e6633 MT |
560 | return 1; |
561 | return 0; | |
562 | } | |
563 | ||
d3e328f2 JS |
564 | static bool is_executable_pte(u64 spte) |
565 | { | |
566 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
567 | } | |
568 | ||
ba049e93 | 569 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 570 | { |
35149e21 | 571 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
572 | } |
573 | ||
da928521 AK |
574 | static gfn_t pse36_gfn_delta(u32 gpte) |
575 | { | |
576 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
577 | ||
578 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
579 | } | |
580 | ||
603e0651 | 581 | #ifdef CONFIG_X86_64 |
d555c333 | 582 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 583 | { |
b19ee2ff | 584 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
585 | } |
586 | ||
603e0651 | 587 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 588 | { |
b19ee2ff | 589 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
590 | } |
591 | ||
592 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
593 | { | |
594 | return xchg(sptep, spte); | |
595 | } | |
c2a2ac2b XG |
596 | |
597 | static u64 __get_spte_lockless(u64 *sptep) | |
598 | { | |
6aa7de05 | 599 | return READ_ONCE(*sptep); |
c2a2ac2b | 600 | } |
a9221dd5 | 601 | #else |
603e0651 XG |
602 | union split_spte { |
603 | struct { | |
604 | u32 spte_low; | |
605 | u32 spte_high; | |
606 | }; | |
607 | u64 spte; | |
608 | }; | |
a9221dd5 | 609 | |
c2a2ac2b XG |
610 | static void count_spte_clear(u64 *sptep, u64 spte) |
611 | { | |
612 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
613 | ||
614 | if (is_shadow_present_pte(spte)) | |
615 | return; | |
616 | ||
617 | /* Ensure the spte is completely set before we increase the count */ | |
618 | smp_wmb(); | |
619 | sp->clear_spte_count++; | |
620 | } | |
621 | ||
603e0651 XG |
622 | static void __set_spte(u64 *sptep, u64 spte) |
623 | { | |
624 | union split_spte *ssptep, sspte; | |
a9221dd5 | 625 | |
603e0651 XG |
626 | ssptep = (union split_spte *)sptep; |
627 | sspte = (union split_spte)spte; | |
628 | ||
629 | ssptep->spte_high = sspte.spte_high; | |
630 | ||
631 | /* | |
632 | * If we map the spte from nonpresent to present, We should store | |
633 | * the high bits firstly, then set present bit, so cpu can not | |
634 | * fetch this spte while we are setting the spte. | |
635 | */ | |
636 | smp_wmb(); | |
637 | ||
b19ee2ff | 638 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
639 | } |
640 | ||
603e0651 XG |
641 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
642 | { | |
643 | union split_spte *ssptep, sspte; | |
644 | ||
645 | ssptep = (union split_spte *)sptep; | |
646 | sspte = (union split_spte)spte; | |
647 | ||
b19ee2ff | 648 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
649 | |
650 | /* | |
651 | * If we map the spte from present to nonpresent, we should clear | |
652 | * present bit firstly to avoid vcpu fetch the old high bits. | |
653 | */ | |
654 | smp_wmb(); | |
655 | ||
656 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 657 | count_spte_clear(sptep, spte); |
603e0651 XG |
658 | } |
659 | ||
660 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
661 | { | |
662 | union split_spte *ssptep, sspte, orig; | |
663 | ||
664 | ssptep = (union split_spte *)sptep; | |
665 | sspte = (union split_spte)spte; | |
666 | ||
667 | /* xchg acts as a barrier before the setting of the high bits */ | |
668 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
669 | orig.spte_high = ssptep->spte_high; |
670 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 671 | count_spte_clear(sptep, spte); |
603e0651 XG |
672 | |
673 | return orig.spte; | |
674 | } | |
c2a2ac2b XG |
675 | |
676 | /* | |
677 | * The idea using the light way get the spte on x86_32 guest is from | |
678 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
679 | * |
680 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
681 | * coalesces them and we are running out of the MMU lock. Therefore | |
682 | * we need to protect against in-progress updates of the spte. | |
683 | * | |
684 | * Reading the spte while an update is in progress may get the old value | |
685 | * for the high part of the spte. The race is fine for a present->non-present | |
686 | * change (because the high part of the spte is ignored for non-present spte), | |
687 | * but for a present->present change we must reread the spte. | |
688 | * | |
689 | * All such changes are done in two steps (present->non-present and | |
690 | * non-present->present), hence it is enough to count the number of | |
691 | * present->non-present updates: if it changed while reading the spte, | |
692 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
693 | */ |
694 | static u64 __get_spte_lockless(u64 *sptep) | |
695 | { | |
696 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
697 | union split_spte spte, *orig = (union split_spte *)sptep; | |
698 | int count; | |
699 | ||
700 | retry: | |
701 | count = sp->clear_spte_count; | |
702 | smp_rmb(); | |
703 | ||
704 | spte.spte_low = orig->spte_low; | |
705 | smp_rmb(); | |
706 | ||
707 | spte.spte_high = orig->spte_high; | |
708 | smp_rmb(); | |
709 | ||
710 | if (unlikely(spte.spte_low != orig->spte_low || | |
711 | count != sp->clear_spte_count)) | |
712 | goto retry; | |
713 | ||
714 | return spte.spte; | |
715 | } | |
603e0651 XG |
716 | #endif |
717 | ||
ea4114bc | 718 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 719 | { |
feb3eb70 GN |
720 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
721 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
722 | } |
723 | ||
8672b721 XG |
724 | static bool spte_has_volatile_bits(u64 spte) |
725 | { | |
f160c7b7 JS |
726 | if (!is_shadow_present_pte(spte)) |
727 | return false; | |
728 | ||
c7ba5b48 | 729 | /* |
6a6256f9 | 730 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
731 | * out of mmu-lock, it can ensure dirty bit is not lost, |
732 | * also, it can help us to get a stable is_writable_pte() | |
733 | * to ensure tlb flush is not missed. | |
734 | */ | |
f160c7b7 JS |
735 | if (spte_can_locklessly_be_made_writable(spte) || |
736 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
737 | return true; |
738 | ||
ac8d57e5 | 739 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
740 | if ((spte & shadow_accessed_mask) == 0 || |
741 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
742 | return true; | |
743 | } | |
8672b721 | 744 | |
f160c7b7 | 745 | return false; |
8672b721 XG |
746 | } |
747 | ||
83ef6c81 | 748 | static bool is_accessed_spte(u64 spte) |
4132779b | 749 | { |
ac8d57e5 PF |
750 | u64 accessed_mask = spte_shadow_accessed_mask(spte); |
751 | ||
752 | return accessed_mask ? spte & accessed_mask | |
753 | : !is_access_track_spte(spte); | |
4132779b XG |
754 | } |
755 | ||
83ef6c81 | 756 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 757 | { |
ac8d57e5 PF |
758 | u64 dirty_mask = spte_shadow_dirty_mask(spte); |
759 | ||
760 | return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
761 | } |
762 | ||
1df9f2dc XG |
763 | /* Rules for using mmu_spte_set: |
764 | * Set the sptep from nonpresent to present. | |
765 | * Note: the sptep being assigned *must* be either not present | |
766 | * or in a state where the hardware will not attempt to update | |
767 | * the spte. | |
768 | */ | |
769 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
770 | { | |
771 | WARN_ON(is_shadow_present_pte(*sptep)); | |
772 | __set_spte(sptep, new_spte); | |
773 | } | |
774 | ||
f39a058d JS |
775 | /* |
776 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
777 | * accessed/dirty status. | |
1df9f2dc | 778 | */ |
f39a058d | 779 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 780 | { |
c7ba5b48 | 781 | u64 old_spte = *sptep; |
4132779b | 782 | |
afd28fe1 | 783 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 784 | |
6e7d0354 XG |
785 | if (!is_shadow_present_pte(old_spte)) { |
786 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 787 | return old_spte; |
6e7d0354 | 788 | } |
4132779b | 789 | |
c7ba5b48 | 790 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 791 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 792 | else |
603e0651 | 793 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 794 | |
83ef6c81 JS |
795 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
796 | ||
f39a058d JS |
797 | return old_spte; |
798 | } | |
799 | ||
800 | /* Rules for using mmu_spte_update: | |
801 | * Update the state bits, it means the mapped pfn is not changed. | |
802 | * | |
803 | * Whenever we overwrite a writable spte with a read-only one we | |
804 | * should flush remote TLBs. Otherwise rmap_write_protect | |
805 | * will find a read-only spte, even though the writable spte | |
806 | * might be cached on a CPU's TLB, the return value indicates this | |
807 | * case. | |
808 | * | |
809 | * Returns true if the TLB needs to be flushed | |
810 | */ | |
811 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
812 | { | |
813 | bool flush = false; | |
814 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
815 | ||
816 | if (!is_shadow_present_pte(old_spte)) | |
817 | return false; | |
818 | ||
c7ba5b48 XG |
819 | /* |
820 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 821 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
822 | * spte_has_volatile_bits(). |
823 | */ | |
ea4114bc | 824 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 825 | !is_writable_pte(new_spte)) |
83ef6c81 | 826 | flush = true; |
4132779b | 827 | |
7e71a59b | 828 | /* |
83ef6c81 | 829 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
830 | * to guarantee consistency between TLB and page tables. |
831 | */ | |
7e71a59b | 832 | |
83ef6c81 JS |
833 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
834 | flush = true; | |
4132779b | 835 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
836 | } |
837 | ||
838 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
839 | flush = true; | |
4132779b | 840 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 841 | } |
6e7d0354 | 842 | |
83ef6c81 | 843 | return flush; |
b79b93f9 AK |
844 | } |
845 | ||
1df9f2dc XG |
846 | /* |
847 | * Rules for using mmu_spte_clear_track_bits: | |
848 | * It sets the sptep from present to nonpresent, and track the | |
849 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 850 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
851 | */ |
852 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
853 | { | |
ba049e93 | 854 | kvm_pfn_t pfn; |
1df9f2dc XG |
855 | u64 old_spte = *sptep; |
856 | ||
857 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 858 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 859 | else |
603e0651 | 860 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 861 | |
afd28fe1 | 862 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
863 | return 0; |
864 | ||
865 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
866 | |
867 | /* | |
868 | * KVM does not hold the refcount of the page used by | |
869 | * kvm mmu, before reclaiming the page, we should | |
870 | * unmap it from mmu first. | |
871 | */ | |
bf4bea8e | 872 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 873 | |
83ef6c81 | 874 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 875 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
876 | |
877 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 878 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 879 | |
1df9f2dc XG |
880 | return 1; |
881 | } | |
882 | ||
883 | /* | |
884 | * Rules for using mmu_spte_clear_no_track: | |
885 | * Directly clear spte without caring the state bits of sptep, | |
886 | * it is used to set the upper level spte. | |
887 | */ | |
888 | static void mmu_spte_clear_no_track(u64 *sptep) | |
889 | { | |
603e0651 | 890 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
891 | } |
892 | ||
c2a2ac2b XG |
893 | static u64 mmu_spte_get_lockless(u64 *sptep) |
894 | { | |
895 | return __get_spte_lockless(sptep); | |
896 | } | |
897 | ||
f160c7b7 JS |
898 | static u64 mark_spte_for_access_track(u64 spte) |
899 | { | |
ac8d57e5 | 900 | if (spte_ad_enabled(spte)) |
f160c7b7 JS |
901 | return spte & ~shadow_accessed_mask; |
902 | ||
ac8d57e5 | 903 | if (is_access_track_spte(spte)) |
f160c7b7 JS |
904 | return spte; |
905 | ||
906 | /* | |
20d65236 JS |
907 | * Making an Access Tracking PTE will result in removal of write access |
908 | * from the PTE. So, verify that we will be able to restore the write | |
909 | * access in the fast page fault path later on. | |
f160c7b7 JS |
910 | */ |
911 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
912 | !spte_can_locklessly_be_made_writable(spte), | |
913 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
914 | ||
915 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
916 | shadow_acc_track_saved_bits_shift), | |
917 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
918 | ||
919 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
920 | shadow_acc_track_saved_bits_shift; | |
921 | spte &= ~shadow_acc_track_mask; | |
f160c7b7 JS |
922 | |
923 | return spte; | |
924 | } | |
925 | ||
d3e328f2 JS |
926 | /* Restore an acc-track PTE back to a regular PTE */ |
927 | static u64 restore_acc_track_spte(u64 spte) | |
928 | { | |
929 | u64 new_spte = spte; | |
930 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
931 | & shadow_acc_track_saved_bits_mask; | |
932 | ||
ac8d57e5 | 933 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
934 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
935 | ||
936 | new_spte &= ~shadow_acc_track_mask; | |
937 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
938 | shadow_acc_track_saved_bits_shift); | |
939 | new_spte |= saved_bits; | |
940 | ||
941 | return new_spte; | |
942 | } | |
943 | ||
f160c7b7 JS |
944 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
945 | static bool mmu_spte_age(u64 *sptep) | |
946 | { | |
947 | u64 spte = mmu_spte_get_lockless(sptep); | |
948 | ||
949 | if (!is_accessed_spte(spte)) | |
950 | return false; | |
951 | ||
ac8d57e5 | 952 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
953 | clear_bit((ffs(shadow_accessed_mask) - 1), |
954 | (unsigned long *)sptep); | |
955 | } else { | |
956 | /* | |
957 | * Capture the dirty status of the page, so that it doesn't get | |
958 | * lost when the SPTE is marked for access tracking. | |
959 | */ | |
960 | if (is_writable_pte(spte)) | |
961 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
962 | ||
963 | spte = mark_spte_for_access_track(spte); | |
964 | mmu_spte_update_no_track(sptep, spte); | |
965 | } | |
966 | ||
967 | return true; | |
968 | } | |
969 | ||
c2a2ac2b XG |
970 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
971 | { | |
c142786c AK |
972 | /* |
973 | * Prevent page table teardown by making any free-er wait during | |
974 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
975 | */ | |
976 | local_irq_disable(); | |
36ca7e0a | 977 | |
c142786c AK |
978 | /* |
979 | * Make sure a following spte read is not reordered ahead of the write | |
980 | * to vcpu->mode. | |
981 | */ | |
36ca7e0a | 982 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
983 | } |
984 | ||
985 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
986 | { | |
c142786c AK |
987 | /* |
988 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 989 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
990 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
991 | */ | |
36ca7e0a | 992 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 993 | local_irq_enable(); |
c2a2ac2b XG |
994 | } |
995 | ||
e2dec939 | 996 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 997 | struct kmem_cache *base_cache, int min) |
714b93da AK |
998 | { |
999 | void *obj; | |
1000 | ||
1001 | if (cache->nobjs >= min) | |
e2dec939 | 1002 | return 0; |
714b93da | 1003 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
254272ce | 1004 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT); |
714b93da | 1005 | if (!obj) |
daefb794 | 1006 | return cache->nobjs >= min ? 0 : -ENOMEM; |
714b93da AK |
1007 | cache->objects[cache->nobjs++] = obj; |
1008 | } | |
e2dec939 | 1009 | return 0; |
714b93da AK |
1010 | } |
1011 | ||
f759e2b4 XG |
1012 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
1013 | { | |
1014 | return cache->nobjs; | |
1015 | } | |
1016 | ||
e8ad9a70 XG |
1017 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
1018 | struct kmem_cache *cache) | |
714b93da AK |
1019 | { |
1020 | while (mc->nobjs) | |
e8ad9a70 | 1021 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
1022 | } |
1023 | ||
c1158e63 | 1024 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 1025 | int min) |
c1158e63 | 1026 | { |
842f22ed | 1027 | void *page; |
c1158e63 AK |
1028 | |
1029 | if (cache->nobjs >= min) | |
1030 | return 0; | |
1031 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
d97e5e61 | 1032 | page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT); |
c1158e63 | 1033 | if (!page) |
daefb794 | 1034 | return cache->nobjs >= min ? 0 : -ENOMEM; |
842f22ed | 1035 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
1036 | } |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
1041 | { | |
1042 | while (mc->nobjs) | |
c4d198d5 | 1043 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
1044 | } |
1045 | ||
2e3e5882 | 1046 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 1047 | { |
e2dec939 AK |
1048 | int r; |
1049 | ||
53c07b18 | 1050 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 1051 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
1052 | if (r) |
1053 | goto out; | |
ad312c7c | 1054 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
1055 | if (r) |
1056 | goto out; | |
ad312c7c | 1057 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 1058 | mmu_page_header_cache, 4); |
e2dec939 AK |
1059 | out: |
1060 | return r; | |
714b93da AK |
1061 | } |
1062 | ||
1063 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
1064 | { | |
53c07b18 XG |
1065 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
1066 | pte_list_desc_cache); | |
ad312c7c | 1067 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
1068 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
1069 | mmu_page_header_cache); | |
714b93da AK |
1070 | } |
1071 | ||
80feb89a | 1072 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
1073 | { |
1074 | void *p; | |
1075 | ||
1076 | BUG_ON(!mc->nobjs); | |
1077 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
1078 | return p; |
1079 | } | |
1080 | ||
53c07b18 | 1081 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 1082 | { |
80feb89a | 1083 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
1084 | } |
1085 | ||
53c07b18 | 1086 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 1087 | { |
53c07b18 | 1088 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
1089 | } |
1090 | ||
2032a93d LJ |
1091 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
1092 | { | |
1093 | if (!sp->role.direct) | |
1094 | return sp->gfns[index]; | |
1095 | ||
1096 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
1097 | } | |
1098 | ||
1099 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
1100 | { | |
1101 | if (sp->role.direct) | |
1102 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
1103 | else | |
1104 | sp->gfns[index] = gfn; | |
1105 | } | |
1106 | ||
05da4558 | 1107 | /* |
d4dbf470 TY |
1108 | * Return the pointer to the large page information for a given gfn, |
1109 | * handling slots that are not large page aligned. | |
05da4558 | 1110 | */ |
d4dbf470 TY |
1111 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
1112 | struct kvm_memory_slot *slot, | |
1113 | int level) | |
05da4558 MT |
1114 | { |
1115 | unsigned long idx; | |
1116 | ||
fb03cb6f | 1117 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 1118 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
1119 | } |
1120 | ||
547ffaed XG |
1121 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
1122 | gfn_t gfn, int count) | |
1123 | { | |
1124 | struct kvm_lpage_info *linfo; | |
1125 | int i; | |
1126 | ||
1127 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
1128 | linfo = lpage_info_slot(gfn, slot, i); | |
1129 | linfo->disallow_lpage += count; | |
1130 | WARN_ON(linfo->disallow_lpage < 0); | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1135 | { | |
1136 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
1137 | } | |
1138 | ||
1139 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1140 | { | |
1141 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
1142 | } | |
1143 | ||
3ed1a478 | 1144 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1145 | { |
699023e2 | 1146 | struct kvm_memslots *slots; |
d25797b2 | 1147 | struct kvm_memory_slot *slot; |
3ed1a478 | 1148 | gfn_t gfn; |
05da4558 | 1149 | |
56ca57f9 | 1150 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 1151 | gfn = sp->gfn; |
699023e2 PB |
1152 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1153 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1154 | |
1155 | /* the non-leaf shadow pages are keeping readonly. */ | |
1156 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
1157 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
1158 | KVM_PAGE_TRACK_WRITE); | |
1159 | ||
547ffaed | 1160 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
1161 | } |
1162 | ||
3ed1a478 | 1163 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1164 | { |
699023e2 | 1165 | struct kvm_memslots *slots; |
d25797b2 | 1166 | struct kvm_memory_slot *slot; |
3ed1a478 | 1167 | gfn_t gfn; |
05da4558 | 1168 | |
56ca57f9 | 1169 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 1170 | gfn = sp->gfn; |
699023e2 PB |
1171 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1172 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1173 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
1174 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1175 | KVM_PAGE_TRACK_WRITE); | |
1176 | ||
547ffaed | 1177 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
1178 | } |
1179 | ||
92f94f1e XG |
1180 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
1181 | struct kvm_memory_slot *slot) | |
05da4558 | 1182 | { |
d4dbf470 | 1183 | struct kvm_lpage_info *linfo; |
05da4558 MT |
1184 | |
1185 | if (slot) { | |
d4dbf470 | 1186 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 1187 | return !!linfo->disallow_lpage; |
05da4558 MT |
1188 | } |
1189 | ||
92f94f1e | 1190 | return true; |
05da4558 MT |
1191 | } |
1192 | ||
92f94f1e XG |
1193 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
1194 | int level) | |
5225fdf8 TY |
1195 | { |
1196 | struct kvm_memory_slot *slot; | |
1197 | ||
1198 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 1199 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
1200 | } |
1201 | ||
d25797b2 | 1202 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 1203 | { |
8f0b1ab6 | 1204 | unsigned long page_size; |
d25797b2 | 1205 | int i, ret = 0; |
05da4558 | 1206 | |
8f0b1ab6 | 1207 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 1208 | |
8a3d08f1 | 1209 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
1210 | if (page_size >= KVM_HPAGE_SIZE(i)) |
1211 | ret = i; | |
1212 | else | |
1213 | break; | |
1214 | } | |
1215 | ||
4c2155ce | 1216 | return ret; |
05da4558 MT |
1217 | } |
1218 | ||
d8aacf5d TY |
1219 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
1220 | bool no_dirty_log) | |
1221 | { | |
1222 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
1223 | return false; | |
1224 | if (no_dirty_log && slot->dirty_bitmap) | |
1225 | return false; | |
1226 | ||
1227 | return true; | |
1228 | } | |
1229 | ||
5d163b1c XG |
1230 | static struct kvm_memory_slot * |
1231 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1232 | bool no_dirty_log) | |
05da4558 MT |
1233 | { |
1234 | struct kvm_memory_slot *slot; | |
5d163b1c | 1235 | |
54bf36aa | 1236 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 1237 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
1238 | slot = NULL; |
1239 | ||
1240 | return slot; | |
1241 | } | |
1242 | ||
fd136902 TY |
1243 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
1244 | bool *force_pt_level) | |
936a5fe6 AA |
1245 | { |
1246 | int host_level, level, max_level; | |
d8aacf5d TY |
1247 | struct kvm_memory_slot *slot; |
1248 | ||
8c85ac1c TY |
1249 | if (unlikely(*force_pt_level)) |
1250 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 1251 | |
8c85ac1c TY |
1252 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
1253 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
1254 | if (unlikely(*force_pt_level)) |
1255 | return PT_PAGE_TABLE_LEVEL; | |
1256 | ||
d25797b2 JR |
1257 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
1258 | ||
1259 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
1260 | return host_level; | |
1261 | ||
55dd98c3 | 1262 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
1263 | |
1264 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 1265 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 1266 | break; |
d25797b2 JR |
1267 | |
1268 | return level - 1; | |
05da4558 MT |
1269 | } |
1270 | ||
290fc38d | 1271 | /* |
018aabb5 | 1272 | * About rmap_head encoding: |
cd4a4e53 | 1273 | * |
018aabb5 TY |
1274 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1275 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1276 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1277 | */ |
1278 | ||
1279 | /* | |
1280 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1281 | */ |
53c07b18 | 1282 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1283 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1284 | { |
53c07b18 | 1285 | struct pte_list_desc *desc; |
53a27b39 | 1286 | int i, count = 0; |
cd4a4e53 | 1287 | |
018aabb5 | 1288 | if (!rmap_head->val) { |
53c07b18 | 1289 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1290 | rmap_head->val = (unsigned long)spte; |
1291 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1292 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1293 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1294 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1295 | desc->sptes[1] = spte; |
018aabb5 | 1296 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1297 | ++count; |
cd4a4e53 | 1298 | } else { |
53c07b18 | 1299 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1300 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1301 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1302 | desc = desc->more; |
53c07b18 | 1303 | count += PTE_LIST_EXT; |
53a27b39 | 1304 | } |
53c07b18 XG |
1305 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1306 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1307 | desc = desc->more; |
1308 | } | |
d555c333 | 1309 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1310 | ++count; |
d555c333 | 1311 | desc->sptes[i] = spte; |
cd4a4e53 | 1312 | } |
53a27b39 | 1313 | return count; |
cd4a4e53 AK |
1314 | } |
1315 | ||
53c07b18 | 1316 | static void |
018aabb5 TY |
1317 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1318 | struct pte_list_desc *desc, int i, | |
1319 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1320 | { |
1321 | int j; | |
1322 | ||
53c07b18 | 1323 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1324 | ; |
d555c333 AK |
1325 | desc->sptes[i] = desc->sptes[j]; |
1326 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1327 | if (j != 0) |
1328 | return; | |
1329 | if (!prev_desc && !desc->more) | |
018aabb5 | 1330 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
1331 | else |
1332 | if (prev_desc) | |
1333 | prev_desc->more = desc->more; | |
1334 | else | |
018aabb5 | 1335 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1336 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1337 | } |
1338 | ||
8daf3462 | 1339 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1340 | { |
53c07b18 XG |
1341 | struct pte_list_desc *desc; |
1342 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1343 | int i; |
1344 | ||
018aabb5 | 1345 | if (!rmap_head->val) { |
8daf3462 | 1346 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 1347 | BUG(); |
018aabb5 | 1348 | } else if (!(rmap_head->val & 1)) { |
8daf3462 | 1349 | rmap_printk("%s: %p 1->0\n", __func__, spte); |
018aabb5 | 1350 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 1351 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
1352 | BUG(); |
1353 | } | |
018aabb5 | 1354 | rmap_head->val = 0; |
cd4a4e53 | 1355 | } else { |
8daf3462 | 1356 | rmap_printk("%s: %p many->many\n", __func__, spte); |
018aabb5 | 1357 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1358 | prev_desc = NULL; |
1359 | while (desc) { | |
018aabb5 | 1360 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1361 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1362 | pte_list_desc_remove_entry(rmap_head, |
1363 | desc, i, prev_desc); | |
cd4a4e53 AK |
1364 | return; |
1365 | } | |
018aabb5 | 1366 | } |
cd4a4e53 AK |
1367 | prev_desc = desc; |
1368 | desc = desc->more; | |
1369 | } | |
8daf3462 | 1370 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
1371 | BUG(); |
1372 | } | |
1373 | } | |
1374 | ||
e7912386 WY |
1375 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
1376 | { | |
1377 | mmu_spte_clear_track_bits(sptep); | |
1378 | __pte_list_remove(sptep, rmap_head); | |
1379 | } | |
1380 | ||
018aabb5 TY |
1381 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1382 | struct kvm_memory_slot *slot) | |
53c07b18 | 1383 | { |
77d11309 | 1384 | unsigned long idx; |
53c07b18 | 1385 | |
77d11309 | 1386 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1387 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1388 | } |
1389 | ||
018aabb5 TY |
1390 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1391 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1392 | { |
699023e2 | 1393 | struct kvm_memslots *slots; |
9b9b1492 TY |
1394 | struct kvm_memory_slot *slot; |
1395 | ||
699023e2 PB |
1396 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1397 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1398 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1399 | } |
1400 | ||
f759e2b4 XG |
1401 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1402 | { | |
1403 | struct kvm_mmu_memory_cache *cache; | |
1404 | ||
1405 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1406 | return mmu_memory_cache_free_objects(cache); | |
1407 | } | |
1408 | ||
53c07b18 XG |
1409 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1410 | { | |
1411 | struct kvm_mmu_page *sp; | |
018aabb5 | 1412 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1413 | |
53c07b18 XG |
1414 | sp = page_header(__pa(spte)); |
1415 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1416 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1417 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1418 | } |
1419 | ||
53c07b18 XG |
1420 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1421 | { | |
1422 | struct kvm_mmu_page *sp; | |
1423 | gfn_t gfn; | |
018aabb5 | 1424 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1425 | |
1426 | sp = page_header(__pa(spte)); | |
1427 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 | 1428 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 1429 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
1430 | } |
1431 | ||
1e3f42f0 TY |
1432 | /* |
1433 | * Used by the following functions to iterate through the sptes linked by a | |
1434 | * rmap. All fields are private and not assumed to be used outside. | |
1435 | */ | |
1436 | struct rmap_iterator { | |
1437 | /* private fields */ | |
1438 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1439 | int pos; /* index of the sptep */ | |
1440 | }; | |
1441 | ||
1442 | /* | |
1443 | * Iteration must be started by this function. This should also be used after | |
1444 | * removing/dropping sptes from the rmap link because in such cases the | |
1445 | * information in the itererator may not be valid. | |
1446 | * | |
1447 | * Returns sptep if found, NULL otherwise. | |
1448 | */ | |
018aabb5 TY |
1449 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1450 | struct rmap_iterator *iter) | |
1e3f42f0 | 1451 | { |
77fbbbd2 TY |
1452 | u64 *sptep; |
1453 | ||
018aabb5 | 1454 | if (!rmap_head->val) |
1e3f42f0 TY |
1455 | return NULL; |
1456 | ||
018aabb5 | 1457 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1458 | iter->desc = NULL; |
77fbbbd2 TY |
1459 | sptep = (u64 *)rmap_head->val; |
1460 | goto out; | |
1e3f42f0 TY |
1461 | } |
1462 | ||
018aabb5 | 1463 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1464 | iter->pos = 0; |
77fbbbd2 TY |
1465 | sptep = iter->desc->sptes[iter->pos]; |
1466 | out: | |
1467 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1468 | return sptep; | |
1e3f42f0 TY |
1469 | } |
1470 | ||
1471 | /* | |
1472 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1473 | * | |
1474 | * Returns sptep if found, NULL otherwise. | |
1475 | */ | |
1476 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1477 | { | |
77fbbbd2 TY |
1478 | u64 *sptep; |
1479 | ||
1e3f42f0 TY |
1480 | if (iter->desc) { |
1481 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1482 | ++iter->pos; |
1483 | sptep = iter->desc->sptes[iter->pos]; | |
1484 | if (sptep) | |
77fbbbd2 | 1485 | goto out; |
1e3f42f0 TY |
1486 | } |
1487 | ||
1488 | iter->desc = iter->desc->more; | |
1489 | ||
1490 | if (iter->desc) { | |
1491 | iter->pos = 0; | |
1492 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1493 | sptep = iter->desc->sptes[iter->pos]; |
1494 | goto out; | |
1e3f42f0 TY |
1495 | } |
1496 | } | |
1497 | ||
1498 | return NULL; | |
77fbbbd2 TY |
1499 | out: |
1500 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1501 | return sptep; | |
1e3f42f0 TY |
1502 | } |
1503 | ||
018aabb5 TY |
1504 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1505 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1506 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1507 | |
c3707958 | 1508 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1509 | { |
1df9f2dc | 1510 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1511 | rmap_remove(kvm, sptep); |
be38d276 AK |
1512 | } |
1513 | ||
8e22f955 XG |
1514 | |
1515 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1516 | { | |
1517 | if (is_large_pte(*sptep)) { | |
1518 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1519 | PT_PAGE_TABLE_LEVEL); | |
1520 | drop_spte(kvm, sptep); | |
1521 | --kvm->stat.lpages; | |
1522 | return true; | |
1523 | } | |
1524 | ||
1525 | return false; | |
1526 | } | |
1527 | ||
1528 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1529 | { | |
c3134ce2 LT |
1530 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
1531 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
1532 | ||
1533 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1534 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1535 | } | |
8e22f955 XG |
1536 | } |
1537 | ||
1538 | /* | |
49fde340 | 1539 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1540 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1541 | * |
b4619660 | 1542 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1543 | * protection: |
1544 | * - for dirty logging, the spte can be set to writable at anytime if | |
1545 | * its dirty bitmap is properly set. | |
1546 | * - for spte protection, the spte can be writable only after unsync-ing | |
1547 | * shadow page. | |
8e22f955 | 1548 | * |
c126d94f | 1549 | * Return true if tlb need be flushed. |
8e22f955 | 1550 | */ |
c4f138b4 | 1551 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1552 | { |
1553 | u64 spte = *sptep; | |
1554 | ||
49fde340 | 1555 | if (!is_writable_pte(spte) && |
ea4114bc | 1556 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1557 | return false; |
1558 | ||
1559 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1560 | ||
49fde340 XG |
1561 | if (pt_protect) |
1562 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1563 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1564 | |
c126d94f | 1565 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1566 | } |
1567 | ||
018aabb5 TY |
1568 | static bool __rmap_write_protect(struct kvm *kvm, |
1569 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1570 | bool pt_protect) |
98348e95 | 1571 | { |
1e3f42f0 TY |
1572 | u64 *sptep; |
1573 | struct rmap_iterator iter; | |
d13bc5b5 | 1574 | bool flush = false; |
374cbac0 | 1575 | |
018aabb5 | 1576 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1577 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1578 | |
d13bc5b5 | 1579 | return flush; |
a0ed4607 TY |
1580 | } |
1581 | ||
c4f138b4 | 1582 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1583 | { |
1584 | u64 spte = *sptep; | |
1585 | ||
1586 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1587 | ||
1588 | spte &= ~shadow_dirty_mask; | |
1589 | ||
1590 | return mmu_spte_update(sptep, spte); | |
1591 | } | |
1592 | ||
ac8d57e5 PF |
1593 | static bool wrprot_ad_disabled_spte(u64 *sptep) |
1594 | { | |
1595 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1596 | (unsigned long *)sptep); | |
1597 | if (was_writable) | |
1598 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); | |
1599 | ||
1600 | return was_writable; | |
1601 | } | |
1602 | ||
1603 | /* | |
1604 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1605 | * - D bit on ad-enabled SPTEs, and | |
1606 | * - W bit on ad-disabled SPTEs. | |
1607 | * Returns true iff any D or W bits were cleared. | |
1608 | */ | |
018aabb5 | 1609 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1610 | { |
1611 | u64 *sptep; | |
1612 | struct rmap_iterator iter; | |
1613 | bool flush = false; | |
1614 | ||
018aabb5 | 1615 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1616 | if (spte_ad_enabled(*sptep)) |
1617 | flush |= spte_clear_dirty(sptep); | |
1618 | else | |
1619 | flush |= wrprot_ad_disabled_spte(sptep); | |
f4b4b180 KH |
1620 | |
1621 | return flush; | |
1622 | } | |
1623 | ||
c4f138b4 | 1624 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1625 | { |
1626 | u64 spte = *sptep; | |
1627 | ||
1628 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1629 | ||
1630 | spte |= shadow_dirty_mask; | |
1631 | ||
1632 | return mmu_spte_update(sptep, spte); | |
1633 | } | |
1634 | ||
018aabb5 | 1635 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1636 | { |
1637 | u64 *sptep; | |
1638 | struct rmap_iterator iter; | |
1639 | bool flush = false; | |
1640 | ||
018aabb5 | 1641 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1642 | if (spte_ad_enabled(*sptep)) |
1643 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1644 | |
1645 | return flush; | |
1646 | } | |
1647 | ||
5dc99b23 | 1648 | /** |
3b0f1d01 | 1649 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1650 | * @kvm: kvm instance |
1651 | * @slot: slot to protect | |
1652 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1653 | * @mask: indicates which pages we should protect | |
1654 | * | |
1655 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1656 | * logging we do not have any such mappings. | |
1657 | */ | |
3b0f1d01 | 1658 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1659 | struct kvm_memory_slot *slot, |
1660 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1661 | { |
018aabb5 | 1662 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1663 | |
5dc99b23 | 1664 | while (mask) { |
018aabb5 TY |
1665 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1666 | PT_PAGE_TABLE_LEVEL, slot); | |
1667 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1668 | |
5dc99b23 TY |
1669 | /* clear the first set bit */ |
1670 | mask &= mask - 1; | |
1671 | } | |
374cbac0 AK |
1672 | } |
1673 | ||
f4b4b180 | 1674 | /** |
ac8d57e5 PF |
1675 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1676 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1677 | * @kvm: kvm instance |
1678 | * @slot: slot to clear D-bit | |
1679 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1680 | * @mask: indicates which pages we should clear D-bit | |
1681 | * | |
1682 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1683 | */ | |
1684 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1685 | struct kvm_memory_slot *slot, | |
1686 | gfn_t gfn_offset, unsigned long mask) | |
1687 | { | |
018aabb5 | 1688 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1689 | |
1690 | while (mask) { | |
018aabb5 TY |
1691 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1692 | PT_PAGE_TABLE_LEVEL, slot); | |
1693 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1694 | |
1695 | /* clear the first set bit */ | |
1696 | mask &= mask - 1; | |
1697 | } | |
1698 | } | |
1699 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1700 | ||
3b0f1d01 KH |
1701 | /** |
1702 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1703 | * PT level pages. | |
1704 | * | |
1705 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1706 | * enable dirty logging for them. | |
1707 | * | |
1708 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1709 | * logging we do not have any such mappings. | |
1710 | */ | |
1711 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1712 | struct kvm_memory_slot *slot, | |
1713 | gfn_t gfn_offset, unsigned long mask) | |
1714 | { | |
88178fd4 KH |
1715 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1716 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1717 | mask); | |
1718 | else | |
1719 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1720 | } |
1721 | ||
bab4165e BD |
1722 | /** |
1723 | * kvm_arch_write_log_dirty - emulate dirty page logging | |
1724 | * @vcpu: Guest mode vcpu | |
1725 | * | |
1726 | * Emulate arch specific page modification logging for the | |
1727 | * nested hypervisor | |
1728 | */ | |
1729 | int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu) | |
1730 | { | |
1731 | if (kvm_x86_ops->write_log_dirty) | |
1732 | return kvm_x86_ops->write_log_dirty(vcpu); | |
1733 | ||
1734 | return 0; | |
1735 | } | |
1736 | ||
aeecee2e XG |
1737 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1738 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1739 | { |
018aabb5 | 1740 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1741 | int i; |
2f84569f | 1742 | bool write_protected = false; |
95d4c16c | 1743 | |
8a3d08f1 | 1744 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1745 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1746 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1747 | } |
1748 | ||
1749 | return write_protected; | |
95d4c16c TY |
1750 | } |
1751 | ||
aeecee2e XG |
1752 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1753 | { | |
1754 | struct kvm_memory_slot *slot; | |
1755 | ||
1756 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1757 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1758 | } | |
1759 | ||
018aabb5 | 1760 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1761 | { |
1e3f42f0 TY |
1762 | u64 *sptep; |
1763 | struct rmap_iterator iter; | |
6a49f85c | 1764 | bool flush = false; |
e930bffe | 1765 | |
018aabb5 | 1766 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1767 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 | 1768 | |
e7912386 | 1769 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1770 | flush = true; |
e930bffe | 1771 | } |
1e3f42f0 | 1772 | |
6a49f85c XG |
1773 | return flush; |
1774 | } | |
1775 | ||
018aabb5 | 1776 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1777 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1778 | unsigned long data) | |
1779 | { | |
018aabb5 | 1780 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1781 | } |
1782 | ||
018aabb5 | 1783 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1784 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1785 | unsigned long data) | |
3da0dd43 | 1786 | { |
1e3f42f0 TY |
1787 | u64 *sptep; |
1788 | struct rmap_iterator iter; | |
3da0dd43 | 1789 | int need_flush = 0; |
1e3f42f0 | 1790 | u64 new_spte; |
3da0dd43 | 1791 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1792 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1793 | |
1794 | WARN_ON(pte_huge(*ptep)); | |
1795 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1796 | |
0d536790 | 1797 | restart: |
018aabb5 | 1798 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1799 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1800 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1801 | |
3da0dd43 | 1802 | need_flush = 1; |
1e3f42f0 | 1803 | |
3da0dd43 | 1804 | if (pte_write(*ptep)) { |
e7912386 | 1805 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1806 | goto restart; |
3da0dd43 | 1807 | } else { |
1e3f42f0 | 1808 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1809 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1810 | ||
1811 | new_spte &= ~PT_WRITABLE_MASK; | |
1812 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1813 | |
1814 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1815 | |
1816 | mmu_spte_clear_track_bits(sptep); | |
1817 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1818 | } |
1819 | } | |
1e3f42f0 | 1820 | |
3cc5ea94 LT |
1821 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1822 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1823 | return 0; | |
1824 | } | |
1825 | ||
0cf853c5 | 1826 | return need_flush; |
3da0dd43 IE |
1827 | } |
1828 | ||
6ce1f4e2 XG |
1829 | struct slot_rmap_walk_iterator { |
1830 | /* input fields. */ | |
1831 | struct kvm_memory_slot *slot; | |
1832 | gfn_t start_gfn; | |
1833 | gfn_t end_gfn; | |
1834 | int start_level; | |
1835 | int end_level; | |
1836 | ||
1837 | /* output fields. */ | |
1838 | gfn_t gfn; | |
018aabb5 | 1839 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1840 | int level; |
1841 | ||
1842 | /* private field. */ | |
018aabb5 | 1843 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1844 | }; |
1845 | ||
1846 | static void | |
1847 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1848 | { | |
1849 | iterator->level = level; | |
1850 | iterator->gfn = iterator->start_gfn; | |
1851 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1852 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1853 | iterator->slot); | |
1854 | } | |
1855 | ||
1856 | static void | |
1857 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1858 | struct kvm_memory_slot *slot, int start_level, | |
1859 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1860 | { | |
1861 | iterator->slot = slot; | |
1862 | iterator->start_level = start_level; | |
1863 | iterator->end_level = end_level; | |
1864 | iterator->start_gfn = start_gfn; | |
1865 | iterator->end_gfn = end_gfn; | |
1866 | ||
1867 | rmap_walk_init_level(iterator, iterator->start_level); | |
1868 | } | |
1869 | ||
1870 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1871 | { | |
1872 | return !!iterator->rmap; | |
1873 | } | |
1874 | ||
1875 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1876 | { | |
1877 | if (++iterator->rmap <= iterator->end_rmap) { | |
1878 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1879 | return; | |
1880 | } | |
1881 | ||
1882 | if (++iterator->level > iterator->end_level) { | |
1883 | iterator->rmap = NULL; | |
1884 | return; | |
1885 | } | |
1886 | ||
1887 | rmap_walk_init_level(iterator, iterator->level); | |
1888 | } | |
1889 | ||
1890 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1891 | _start_gfn, _end_gfn, _iter_) \ | |
1892 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1893 | _end_level_, _start_gfn, _end_gfn); \ | |
1894 | slot_rmap_walk_okay(_iter_); \ | |
1895 | slot_rmap_walk_next(_iter_)) | |
1896 | ||
84504ef3 TY |
1897 | static int kvm_handle_hva_range(struct kvm *kvm, |
1898 | unsigned long start, | |
1899 | unsigned long end, | |
1900 | unsigned long data, | |
1901 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1902 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1903 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1904 | gfn_t gfn, |
1905 | int level, | |
84504ef3 | 1906 | unsigned long data)) |
e930bffe | 1907 | { |
bc6678a3 | 1908 | struct kvm_memslots *slots; |
be6ba0f0 | 1909 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1910 | struct slot_rmap_walk_iterator iterator; |
1911 | int ret = 0; | |
9da0e4d5 | 1912 | int i; |
bc6678a3 | 1913 | |
9da0e4d5 PB |
1914 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1915 | slots = __kvm_memslots(kvm, i); | |
1916 | kvm_for_each_memslot(memslot, slots) { | |
1917 | unsigned long hva_start, hva_end; | |
1918 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1919 | |
9da0e4d5 PB |
1920 | hva_start = max(start, memslot->userspace_addr); |
1921 | hva_end = min(end, memslot->userspace_addr + | |
1922 | (memslot->npages << PAGE_SHIFT)); | |
1923 | if (hva_start >= hva_end) | |
1924 | continue; | |
1925 | /* | |
1926 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1927 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1928 | */ | |
1929 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1930 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1931 | ||
1932 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1933 | PT_MAX_HUGEPAGE_LEVEL, | |
1934 | gfn_start, gfn_end - 1, | |
1935 | &iterator) | |
1936 | ret |= handler(kvm, iterator.rmap, memslot, | |
1937 | iterator.gfn, iterator.level, data); | |
1938 | } | |
e930bffe AA |
1939 | } |
1940 | ||
f395302e | 1941 | return ret; |
e930bffe AA |
1942 | } |
1943 | ||
84504ef3 TY |
1944 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1945 | unsigned long data, | |
018aabb5 TY |
1946 | int (*handler)(struct kvm *kvm, |
1947 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1948 | struct kvm_memory_slot *slot, |
8a9522d2 | 1949 | gfn_t gfn, int level, |
84504ef3 TY |
1950 | unsigned long data)) |
1951 | { | |
1952 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1953 | } |
1954 | ||
b3ae2096 TY |
1955 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1956 | { | |
1957 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1958 | } | |
1959 | ||
748c0e31 | 1960 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
3da0dd43 | 1961 | { |
0cf853c5 | 1962 | return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1963 | } |
1964 | ||
018aabb5 | 1965 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1966 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1967 | unsigned long data) | |
e930bffe | 1968 | { |
1e3f42f0 | 1969 | u64 *sptep; |
79f702a6 | 1970 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1971 | int young = 0; |
1972 | ||
f160c7b7 JS |
1973 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1974 | young |= mmu_spte_age(sptep); | |
0d536790 | 1975 | |
8a9522d2 | 1976 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1977 | return young; |
1978 | } | |
1979 | ||
018aabb5 | 1980 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1981 | struct kvm_memory_slot *slot, gfn_t gfn, |
1982 | int level, unsigned long data) | |
8ee53820 | 1983 | { |
1e3f42f0 TY |
1984 | u64 *sptep; |
1985 | struct rmap_iterator iter; | |
8ee53820 | 1986 | |
83ef6c81 JS |
1987 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1988 | if (is_accessed_spte(*sptep)) | |
1989 | return 1; | |
83ef6c81 | 1990 | return 0; |
8ee53820 AA |
1991 | } |
1992 | ||
53a27b39 MT |
1993 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1994 | ||
852e3c19 | 1995 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1996 | { |
018aabb5 | 1997 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1998 | struct kvm_mmu_page *sp; |
1999 | ||
2000 | sp = page_header(__pa(spte)); | |
53a27b39 | 2001 | |
018aabb5 | 2002 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 2003 | |
018aabb5 | 2004 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
c3134ce2 LT |
2005 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
2006 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
2007 | } |
2008 | ||
57128468 | 2009 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 2010 | { |
57128468 | 2011 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
2012 | } |
2013 | ||
8ee53820 AA |
2014 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
2015 | { | |
2016 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
2017 | } | |
2018 | ||
d6c69ee9 | 2019 | #ifdef MMU_DEBUG |
47ad8e68 | 2020 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 2021 | { |
139bdb2d AK |
2022 | u64 *pos; |
2023 | u64 *end; | |
2024 | ||
47ad8e68 | 2025 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 2026 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 2027 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 2028 | pos, *pos); |
6aa8b732 | 2029 | return 0; |
139bdb2d | 2030 | } |
6aa8b732 AK |
2031 | return 1; |
2032 | } | |
d6c69ee9 | 2033 | #endif |
6aa8b732 | 2034 | |
45221ab6 DH |
2035 | /* |
2036 | * This value is the sum of all of the kvm instances's | |
2037 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
2038 | * aggregate version in order to make the slab shrinker | |
2039 | * faster | |
2040 | */ | |
bc8a3d89 | 2041 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) |
45221ab6 DH |
2042 | { |
2043 | kvm->arch.n_used_mmu_pages += nr; | |
2044 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
2045 | } | |
2046 | ||
834be0d8 | 2047 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 2048 | { |
fa4a2c08 | 2049 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 2050 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
2051 | list_del(&sp->link); |
2052 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
2053 | if (!sp->role.direct) |
2054 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 2055 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
2056 | } |
2057 | ||
cea0f0e7 AK |
2058 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
2059 | { | |
114df303 | 2060 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
2061 | } |
2062 | ||
714b93da | 2063 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2064 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2065 | { |
cea0f0e7 AK |
2066 | if (!parent_pte) |
2067 | return; | |
cea0f0e7 | 2068 | |
67052b35 | 2069 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
2070 | } |
2071 | ||
4db35314 | 2072 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
2073 | u64 *parent_pte) |
2074 | { | |
8daf3462 | 2075 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
2076 | } |
2077 | ||
bcdd9a93 XG |
2078 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
2079 | u64 *parent_pte) | |
2080 | { | |
2081 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 2082 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
2083 | } |
2084 | ||
47005792 | 2085 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 2086 | { |
67052b35 | 2087 | struct kvm_mmu_page *sp; |
7ddca7e4 | 2088 | |
80feb89a TY |
2089 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
2090 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 2091 | if (!direct) |
80feb89a | 2092 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 XG |
2093 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
2094 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
67052b35 XG |
2095 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
2096 | return sp; | |
ad8cfbe3 MT |
2097 | } |
2098 | ||
67052b35 | 2099 | static void mark_unsync(u64 *spte); |
1047df1f | 2100 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 2101 | { |
74c4e63a TY |
2102 | u64 *sptep; |
2103 | struct rmap_iterator iter; | |
2104 | ||
2105 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
2106 | mark_unsync(sptep); | |
2107 | } | |
0074ff63 MT |
2108 | } |
2109 | ||
67052b35 | 2110 | static void mark_unsync(u64 *spte) |
0074ff63 | 2111 | { |
67052b35 | 2112 | struct kvm_mmu_page *sp; |
1047df1f | 2113 | unsigned int index; |
0074ff63 | 2114 | |
67052b35 | 2115 | sp = page_header(__pa(spte)); |
1047df1f XG |
2116 | index = spte - sp->spt; |
2117 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 2118 | return; |
1047df1f | 2119 | if (sp->unsync_children++) |
0074ff63 | 2120 | return; |
1047df1f | 2121 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
2122 | } |
2123 | ||
e8bc217a | 2124 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 2125 | struct kvm_mmu_page *sp) |
e8bc217a | 2126 | { |
1f50f1b3 | 2127 | return 0; |
e8bc217a MT |
2128 | } |
2129 | ||
7eb77e9f | 2130 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root) |
a7052897 MT |
2131 | { |
2132 | } | |
2133 | ||
0f53b5b1 XG |
2134 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
2135 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 2136 | const void *pte) |
0f53b5b1 XG |
2137 | { |
2138 | WARN_ON(1); | |
2139 | } | |
2140 | ||
60c8aec6 MT |
2141 | #define KVM_PAGE_ARRAY_NR 16 |
2142 | ||
2143 | struct kvm_mmu_pages { | |
2144 | struct mmu_page_and_offset { | |
2145 | struct kvm_mmu_page *sp; | |
2146 | unsigned int idx; | |
2147 | } page[KVM_PAGE_ARRAY_NR]; | |
2148 | unsigned int nr; | |
2149 | }; | |
2150 | ||
cded19f3 HE |
2151 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
2152 | int idx) | |
4731d4c7 | 2153 | { |
60c8aec6 | 2154 | int i; |
4731d4c7 | 2155 | |
60c8aec6 MT |
2156 | if (sp->unsync) |
2157 | for (i=0; i < pvec->nr; i++) | |
2158 | if (pvec->page[i].sp == sp) | |
2159 | return 0; | |
2160 | ||
2161 | pvec->page[pvec->nr].sp = sp; | |
2162 | pvec->page[pvec->nr].idx = idx; | |
2163 | pvec->nr++; | |
2164 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
2165 | } | |
2166 | ||
fd951457 TY |
2167 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
2168 | { | |
2169 | --sp->unsync_children; | |
2170 | WARN_ON((int)sp->unsync_children < 0); | |
2171 | __clear_bit(idx, sp->unsync_child_bitmap); | |
2172 | } | |
2173 | ||
60c8aec6 MT |
2174 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
2175 | struct kvm_mmu_pages *pvec) | |
2176 | { | |
2177 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 2178 | |
37178b8b | 2179 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 2180 | struct kvm_mmu_page *child; |
4731d4c7 MT |
2181 | u64 ent = sp->spt[i]; |
2182 | ||
fd951457 TY |
2183 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
2184 | clear_unsync_child_bit(sp, i); | |
2185 | continue; | |
2186 | } | |
7a8f1a74 XG |
2187 | |
2188 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
2189 | ||
2190 | if (child->unsync_children) { | |
2191 | if (mmu_pages_add(pvec, child, i)) | |
2192 | return -ENOSPC; | |
2193 | ||
2194 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
2195 | if (!ret) { |
2196 | clear_unsync_child_bit(sp, i); | |
2197 | continue; | |
2198 | } else if (ret > 0) { | |
7a8f1a74 | 2199 | nr_unsync_leaf += ret; |
fd951457 | 2200 | } else |
7a8f1a74 XG |
2201 | return ret; |
2202 | } else if (child->unsync) { | |
2203 | nr_unsync_leaf++; | |
2204 | if (mmu_pages_add(pvec, child, i)) | |
2205 | return -ENOSPC; | |
2206 | } else | |
fd951457 | 2207 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2208 | } |
2209 | ||
60c8aec6 MT |
2210 | return nr_unsync_leaf; |
2211 | } | |
2212 | ||
e23d3fef XG |
2213 | #define INVALID_INDEX (-1) |
2214 | ||
60c8aec6 MT |
2215 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2216 | struct kvm_mmu_pages *pvec) | |
2217 | { | |
0a47cd85 | 2218 | pvec->nr = 0; |
60c8aec6 MT |
2219 | if (!sp->unsync_children) |
2220 | return 0; | |
2221 | ||
e23d3fef | 2222 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2223 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2224 | } |
2225 | ||
4731d4c7 MT |
2226 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2227 | { | |
2228 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2229 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2230 | sp->unsync = 0; |
2231 | --kvm->stat.mmu_unsync; | |
2232 | } | |
2233 | ||
83cdb568 SC |
2234 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2235 | struct list_head *invalid_list); | |
7775834a XG |
2236 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2237 | struct list_head *invalid_list); | |
4731d4c7 | 2238 | |
47c42e6b | 2239 | |
f3414bc7 | 2240 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2241 | hlist_for_each_entry(_sp, \ |
2242 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
ea145aac | 2243 | if ((_sp)->role.invalid) { \ |
f3414bc7 | 2244 | } else |
1044b030 TY |
2245 | |
2246 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2247 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2248 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2249 | |
47c42e6b SC |
2250 | static inline bool is_ept_sp(struct kvm_mmu_page *sp) |
2251 | { | |
2252 | return sp->role.cr0_wp && sp->role.smap_andnot_wp; | |
2253 | } | |
2254 | ||
f918b443 | 2255 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2256 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2257 | struct list_head *invalid_list) | |
4731d4c7 | 2258 | { |
47c42e6b SC |
2259 | if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) || |
2260 | vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { | |
d98ba053 | 2261 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2262 | return false; |
4731d4c7 MT |
2263 | } |
2264 | ||
1f50f1b3 | 2265 | return true; |
4731d4c7 MT |
2266 | } |
2267 | ||
a2113634 SC |
2268 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
2269 | struct list_head *invalid_list, | |
2270 | bool remote_flush) | |
2271 | { | |
cfd32acf | 2272 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
2273 | return false; |
2274 | ||
2275 | if (!list_empty(invalid_list)) | |
2276 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
2277 | else | |
2278 | kvm_flush_remote_tlbs(kvm); | |
2279 | return true; | |
2280 | } | |
2281 | ||
35a70510 PB |
2282 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2283 | struct list_head *invalid_list, | |
2284 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2285 | { |
a2113634 | 2286 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 2287 | return; |
d98ba053 | 2288 | |
a2113634 | 2289 | if (local_flush) |
35a70510 | 2290 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
1d9dc7e0 XG |
2291 | } |
2292 | ||
e37fa785 XG |
2293 | #ifdef CONFIG_KVM_MMU_AUDIT |
2294 | #include "mmu_audit.c" | |
2295 | #else | |
2296 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2297 | static void mmu_audit_disable(void) { } | |
2298 | #endif | |
2299 | ||
1f50f1b3 | 2300 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2301 | struct list_head *invalid_list) |
1d9dc7e0 | 2302 | { |
9a43c5d9 PB |
2303 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2304 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2305 | } |
2306 | ||
9f1a122f | 2307 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2308 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2309 | struct list_head *invalid_list) | |
9f1a122f | 2310 | { |
9f1a122f | 2311 | struct kvm_mmu_page *s; |
2a74003a | 2312 | bool ret = false; |
9f1a122f | 2313 | |
b67bfe0d | 2314 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2315 | if (!s->unsync) |
9f1a122f XG |
2316 | continue; |
2317 | ||
2318 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2319 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2320 | } |
2321 | ||
2a74003a | 2322 | return ret; |
9f1a122f XG |
2323 | } |
2324 | ||
60c8aec6 | 2325 | struct mmu_page_path { |
2a7266a8 YZ |
2326 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
2327 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
2328 | }; |
2329 | ||
60c8aec6 | 2330 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2331 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2332 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2333 | i = mmu_pages_next(&pvec, &parents, i)) | |
2334 | ||
cded19f3 HE |
2335 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2336 | struct mmu_page_path *parents, | |
2337 | int i) | |
60c8aec6 MT |
2338 | { |
2339 | int n; | |
2340 | ||
2341 | for (n = i+1; n < pvec->nr; n++) { | |
2342 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2343 | unsigned idx = pvec->page[n].idx; |
2344 | int level = sp->role.level; | |
60c8aec6 | 2345 | |
0a47cd85 PB |
2346 | parents->idx[level-1] = idx; |
2347 | if (level == PT_PAGE_TABLE_LEVEL) | |
2348 | break; | |
60c8aec6 | 2349 | |
0a47cd85 | 2350 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2351 | } |
2352 | ||
2353 | return n; | |
2354 | } | |
2355 | ||
0a47cd85 PB |
2356 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2357 | struct mmu_page_path *parents) | |
2358 | { | |
2359 | struct kvm_mmu_page *sp; | |
2360 | int level; | |
2361 | ||
2362 | if (pvec->nr == 0) | |
2363 | return 0; | |
2364 | ||
e23d3fef XG |
2365 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2366 | ||
0a47cd85 PB |
2367 | sp = pvec->page[0].sp; |
2368 | level = sp->role.level; | |
2369 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2370 | ||
2371 | parents->parent[level-2] = sp; | |
2372 | ||
2373 | /* Also set up a sentinel. Further entries in pvec are all | |
2374 | * children of sp, so this element is never overwritten. | |
2375 | */ | |
2376 | parents->parent[level-1] = NULL; | |
2377 | return mmu_pages_next(pvec, parents, 0); | |
2378 | } | |
2379 | ||
cded19f3 | 2380 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2381 | { |
60c8aec6 MT |
2382 | struct kvm_mmu_page *sp; |
2383 | unsigned int level = 0; | |
2384 | ||
2385 | do { | |
2386 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2387 | sp = parents->parent[level]; |
2388 | if (!sp) | |
2389 | return; | |
2390 | ||
e23d3fef | 2391 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2392 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2393 | level++; |
0a47cd85 | 2394 | } while (!sp->unsync_children); |
60c8aec6 | 2395 | } |
4731d4c7 | 2396 | |
60c8aec6 MT |
2397 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2398 | struct kvm_mmu_page *parent) | |
2399 | { | |
2400 | int i; | |
2401 | struct kvm_mmu_page *sp; | |
2402 | struct mmu_page_path parents; | |
2403 | struct kvm_mmu_pages pages; | |
d98ba053 | 2404 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2405 | bool flush = false; |
60c8aec6 | 2406 | |
60c8aec6 | 2407 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2408 | bool protected = false; |
b1a36821 MT |
2409 | |
2410 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2411 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2412 | |
50c9e6f3 | 2413 | if (protected) { |
b1a36821 | 2414 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2415 | flush = false; |
2416 | } | |
b1a36821 | 2417 | |
60c8aec6 | 2418 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2419 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2420 | mmu_pages_clear_parents(&parents); |
2421 | } | |
50c9e6f3 PB |
2422 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2423 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2424 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2425 | flush = false; | |
2426 | } | |
60c8aec6 | 2427 | } |
50c9e6f3 PB |
2428 | |
2429 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2430 | } |
2431 | ||
a30f47cb XG |
2432 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2433 | { | |
e5691a81 | 2434 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2435 | } |
2436 | ||
2437 | static void clear_sp_write_flooding_count(u64 *spte) | |
2438 | { | |
2439 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2440 | ||
2441 | __clear_sp_write_flooding_count(sp); | |
2442 | } | |
2443 | ||
cea0f0e7 AK |
2444 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2445 | gfn_t gfn, | |
2446 | gva_t gaddr, | |
2447 | unsigned level, | |
f6e2c02b | 2448 | int direct, |
bb11c6c9 | 2449 | unsigned access) |
cea0f0e7 AK |
2450 | { |
2451 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2452 | unsigned quadrant; |
9f1a122f | 2453 | struct kvm_mmu_page *sp; |
9f1a122f | 2454 | bool need_sync = false; |
2a74003a | 2455 | bool flush = false; |
f3414bc7 | 2456 | int collisions = 0; |
2a74003a | 2457 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2458 | |
36d9594d | 2459 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2460 | role.level = level; |
f6e2c02b | 2461 | role.direct = direct; |
84b0c8c6 | 2462 | if (role.direct) |
47c42e6b | 2463 | role.gpte_is_8_bytes = true; |
41074d07 | 2464 | role.access = access; |
44dd3ffa VK |
2465 | if (!vcpu->arch.mmu->direct_map |
2466 | && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2467 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2468 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2469 | role.quadrant = quadrant; | |
2470 | } | |
f3414bc7 DM |
2471 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2472 | if (sp->gfn != gfn) { | |
2473 | collisions++; | |
2474 | continue; | |
2475 | } | |
2476 | ||
7ae680eb XG |
2477 | if (!need_sync && sp->unsync) |
2478 | need_sync = true; | |
4731d4c7 | 2479 | |
7ae680eb XG |
2480 | if (sp->role.word != role.word) |
2481 | continue; | |
4731d4c7 | 2482 | |
2a74003a PB |
2483 | if (sp->unsync) { |
2484 | /* The page is good, but __kvm_sync_page might still end | |
2485 | * up zapping it. If so, break in order to rebuild it. | |
2486 | */ | |
2487 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2488 | break; | |
2489 | ||
2490 | WARN_ON(!list_empty(&invalid_list)); | |
2491 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2492 | } | |
e02aa901 | 2493 | |
98bba238 | 2494 | if (sp->unsync_children) |
a8eeb04a | 2495 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2496 | |
a30f47cb | 2497 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2498 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2499 | goto out; |
7ae680eb | 2500 | } |
47005792 | 2501 | |
dfc5aa00 | 2502 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2503 | |
2504 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2505 | ||
4db35314 AK |
2506 | sp->gfn = gfn; |
2507 | sp->role = role; | |
7ae680eb XG |
2508 | hlist_add_head(&sp->hash_link, |
2509 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2510 | if (!direct) { |
56ca57f9 XG |
2511 | /* |
2512 | * we should do write protection before syncing pages | |
2513 | * otherwise the content of the synced shadow page may | |
2514 | * be inconsistent with guest page table. | |
2515 | */ | |
2516 | account_shadowed(vcpu->kvm, sp); | |
2517 | if (level == PT_PAGE_TABLE_LEVEL && | |
2518 | rmap_write_protect(vcpu, gfn)) | |
c3134ce2 | 2519 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
9f1a122f | 2520 | |
9f1a122f | 2521 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2522 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2523 | } |
77492664 | 2524 | clear_page(sp->spt); |
f691fe1d | 2525 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2526 | |
2527 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2528 | out: |
2529 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2530 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2531 | return sp; |
cea0f0e7 AK |
2532 | } |
2533 | ||
7eb77e9f JS |
2534 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2535 | struct kvm_vcpu *vcpu, hpa_t root, | |
2536 | u64 addr) | |
2d11123a AK |
2537 | { |
2538 | iterator->addr = addr; | |
7eb77e9f | 2539 | iterator->shadow_addr = root; |
44dd3ffa | 2540 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2541 | |
2a7266a8 | 2542 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2543 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2544 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2545 | --iterator->level; |
2546 | ||
2d11123a | 2547 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2548 | /* |
2549 | * prev_root is currently only used for 64-bit hosts. So only | |
2550 | * the active root_hpa is valid here. | |
2551 | */ | |
44dd3ffa | 2552 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2553 | |
2d11123a | 2554 | iterator->shadow_addr |
44dd3ffa | 2555 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2556 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2557 | --iterator->level; | |
2558 | if (!iterator->shadow_addr) | |
2559 | iterator->level = 0; | |
2560 | } | |
2561 | } | |
2562 | ||
7eb77e9f JS |
2563 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2564 | struct kvm_vcpu *vcpu, u64 addr) | |
2565 | { | |
44dd3ffa | 2566 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2567 | addr); |
2568 | } | |
2569 | ||
2d11123a AK |
2570 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2571 | { | |
2572 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2573 | return false; | |
4d88954d | 2574 | |
2d11123a AK |
2575 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2576 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2577 | return true; | |
2578 | } | |
2579 | ||
c2a2ac2b XG |
2580 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2581 | u64 spte) | |
2d11123a | 2582 | { |
c2a2ac2b | 2583 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2584 | iterator->level = 0; |
2585 | return; | |
2586 | } | |
2587 | ||
c2a2ac2b | 2588 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2589 | --iterator->level; |
2590 | } | |
2591 | ||
c2a2ac2b XG |
2592 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2593 | { | |
bb606a9b | 2594 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2595 | } |
2596 | ||
98bba238 TY |
2597 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2598 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2599 | { |
2600 | u64 spte; | |
2601 | ||
ffb128c8 | 2602 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2603 | |
ffb128c8 | 2604 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
d0ec49d4 | 2605 | shadow_user_mask | shadow_x_mask | shadow_me_mask; |
ac8d57e5 PF |
2606 | |
2607 | if (sp_ad_disabled(sp)) | |
2608 | spte |= shadow_acc_track_value; | |
2609 | else | |
2610 | spte |= shadow_accessed_mask; | |
24db2734 | 2611 | |
1df9f2dc | 2612 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2613 | |
2614 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2615 | ||
2616 | if (sp->unsync_children || sp->unsync) | |
2617 | mark_unsync(sptep); | |
32ef26a3 AK |
2618 | } |
2619 | ||
a357bd22 AK |
2620 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2621 | unsigned direct_access) | |
2622 | { | |
2623 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2624 | struct kvm_mmu_page *child; | |
2625 | ||
2626 | /* | |
2627 | * For the direct sp, if the guest pte's dirty bit | |
2628 | * changed form clean to dirty, it will corrupt the | |
2629 | * sp's access: allow writable in the read-only sp, | |
2630 | * so we should update the spte at this point to get | |
2631 | * a new sp with the correct access. | |
2632 | */ | |
2633 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2634 | if (child->role.access == direct_access) | |
2635 | return; | |
2636 | ||
bcdd9a93 | 2637 | drop_parent_pte(child, sptep); |
c3134ce2 | 2638 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2639 | } |
2640 | } | |
2641 | ||
505aef8f | 2642 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2643 | u64 *spte) |
2644 | { | |
2645 | u64 pte; | |
2646 | struct kvm_mmu_page *child; | |
2647 | ||
2648 | pte = *spte; | |
2649 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2650 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2651 | drop_spte(kvm, spte); |
505aef8f XG |
2652 | if (is_large_pte(pte)) |
2653 | --kvm->stat.lpages; | |
2654 | } else { | |
38e3b2b2 | 2655 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2656 | drop_parent_pte(child, spte); |
38e3b2b2 | 2657 | } |
505aef8f XG |
2658 | return true; |
2659 | } | |
2660 | ||
2661 | if (is_mmio_spte(pte)) | |
ce88decf | 2662 | mmu_spte_clear_no_track(spte); |
c3707958 | 2663 | |
505aef8f | 2664 | return false; |
38e3b2b2 XG |
2665 | } |
2666 | ||
90cb0529 | 2667 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2668 | struct kvm_mmu_page *sp) |
a436036b | 2669 | { |
697fe2e2 | 2670 | unsigned i; |
697fe2e2 | 2671 | |
38e3b2b2 XG |
2672 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2673 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2674 | } |
2675 | ||
31aa2b44 | 2676 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2677 | { |
1e3f42f0 TY |
2678 | u64 *sptep; |
2679 | struct rmap_iterator iter; | |
a436036b | 2680 | |
018aabb5 | 2681 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2682 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2683 | } |
2684 | ||
60c8aec6 | 2685 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2686 | struct kvm_mmu_page *parent, |
2687 | struct list_head *invalid_list) | |
4731d4c7 | 2688 | { |
60c8aec6 MT |
2689 | int i, zapped = 0; |
2690 | struct mmu_page_path parents; | |
2691 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2692 | |
60c8aec6 | 2693 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2694 | return 0; |
60c8aec6 | 2695 | |
60c8aec6 MT |
2696 | while (mmu_unsync_walk(parent, &pages)) { |
2697 | struct kvm_mmu_page *sp; | |
2698 | ||
2699 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2700 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2701 | mmu_pages_clear_parents(&parents); |
77662e00 | 2702 | zapped++; |
60c8aec6 | 2703 | } |
60c8aec6 MT |
2704 | } |
2705 | ||
2706 | return zapped; | |
4731d4c7 MT |
2707 | } |
2708 | ||
83cdb568 SC |
2709 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2710 | struct kvm_mmu_page *sp, | |
2711 | struct list_head *invalid_list, | |
2712 | int *nr_zapped) | |
31aa2b44 | 2713 | { |
83cdb568 | 2714 | bool list_unstable; |
f691fe1d | 2715 | |
7775834a | 2716 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2717 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2718 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2719 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2720 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2721 | |
83cdb568 SC |
2722 | /* Zapping children means active_mmu_pages has become unstable. */ |
2723 | list_unstable = *nr_zapped; | |
2724 | ||
f6e2c02b | 2725 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2726 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2727 | |
4731d4c7 MT |
2728 | if (sp->unsync) |
2729 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2730 | if (!sp->root_count) { |
54a4f023 | 2731 | /* Count self */ |
83cdb568 | 2732 | (*nr_zapped)++; |
7775834a | 2733 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2734 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2735 | } else { |
5b5c6a5a | 2736 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 | 2737 | |
5ff05683 | 2738 | if (!sp->role.invalid) |
05988d72 | 2739 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2740 | } |
7775834a XG |
2741 | |
2742 | sp->role.invalid = 1; | |
83cdb568 SC |
2743 | return list_unstable; |
2744 | } | |
2745 | ||
2746 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2747 | struct list_head *invalid_list) | |
2748 | { | |
2749 | int nr_zapped; | |
2750 | ||
2751 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2752 | return nr_zapped; | |
a436036b AK |
2753 | } |
2754 | ||
7775834a XG |
2755 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2756 | struct list_head *invalid_list) | |
2757 | { | |
945315b9 | 2758 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2759 | |
2760 | if (list_empty(invalid_list)) | |
2761 | return; | |
2762 | ||
c142786c | 2763 | /* |
9753f529 LT |
2764 | * We need to make sure everyone sees our modifications to |
2765 | * the page tables and see changes to vcpu->mode here. The barrier | |
2766 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2767 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2768 | * | |
2769 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2770 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2771 | */ |
2772 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2773 | |
945315b9 | 2774 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2775 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2776 | kvm_mmu_free_page(sp); |
945315b9 | 2777 | } |
7775834a XG |
2778 | } |
2779 | ||
5da59607 TY |
2780 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2781 | struct list_head *invalid_list) | |
2782 | { | |
2783 | struct kvm_mmu_page *sp; | |
2784 | ||
2785 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2786 | return false; | |
2787 | ||
d74c0e6b GT |
2788 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2789 | struct kvm_mmu_page, link); | |
42bcbebf | 2790 | return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
5da59607 TY |
2791 | } |
2792 | ||
82ce2c96 IE |
2793 | /* |
2794 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2795 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2796 | */ |
bc8a3d89 | 2797 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2798 | { |
d98ba053 | 2799 | LIST_HEAD(invalid_list); |
82ce2c96 | 2800 | |
b34cb590 TY |
2801 | spin_lock(&kvm->mmu_lock); |
2802 | ||
49d5ca26 | 2803 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2804 | /* Need to free some mmu pages to achieve the goal. */ |
2805 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2806 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2807 | break; | |
82ce2c96 | 2808 | |
aa6bd187 | 2809 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2810 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2811 | } |
82ce2c96 | 2812 | |
49d5ca26 | 2813 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2814 | |
2815 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2816 | } |
2817 | ||
1cb3f3ae | 2818 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2819 | { |
4db35314 | 2820 | struct kvm_mmu_page *sp; |
d98ba053 | 2821 | LIST_HEAD(invalid_list); |
a436036b AK |
2822 | int r; |
2823 | ||
9ad17b10 | 2824 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2825 | r = 0; |
1cb3f3ae | 2826 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2827 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2828 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2829 | sp->role.word); |
2830 | r = 1; | |
f41d335a | 2831 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2832 | } |
d98ba053 | 2833 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2834 | spin_unlock(&kvm->mmu_lock); |
2835 | ||
a436036b | 2836 | return r; |
cea0f0e7 | 2837 | } |
1cb3f3ae | 2838 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2839 | |
5c520e90 | 2840 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2841 | { |
2842 | trace_kvm_mmu_unsync_page(sp); | |
2843 | ++vcpu->kvm->stat.mmu_unsync; | |
2844 | sp->unsync = 1; | |
2845 | ||
2846 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2847 | } |
2848 | ||
3d0c27ad XG |
2849 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2850 | bool can_unsync) | |
4731d4c7 | 2851 | { |
5c520e90 | 2852 | struct kvm_mmu_page *sp; |
4731d4c7 | 2853 | |
3d0c27ad XG |
2854 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2855 | return true; | |
9cf5cf5a | 2856 | |
5c520e90 | 2857 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2858 | if (!can_unsync) |
3d0c27ad | 2859 | return true; |
36a2e677 | 2860 | |
5c520e90 XG |
2861 | if (sp->unsync) |
2862 | continue; | |
9cf5cf5a | 2863 | |
5c520e90 XG |
2864 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2865 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2866 | } |
3d0c27ad | 2867 | |
578e1c4d JS |
2868 | /* |
2869 | * We need to ensure that the marking of unsync pages is visible | |
2870 | * before the SPTE is updated to allow writes because | |
2871 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2872 | * the MMU lock and so can race with this. If the SPTE was updated | |
2873 | * before the page had been marked as unsync-ed, something like the | |
2874 | * following could happen: | |
2875 | * | |
2876 | * CPU 1 CPU 2 | |
2877 | * --------------------------------------------------------------------- | |
2878 | * 1.2 Host updates SPTE | |
2879 | * to be writable | |
2880 | * 2.1 Guest writes a GPTE for GVA X. | |
2881 | * (GPTE being in the guest page table shadowed | |
2882 | * by the SP from CPU 1.) | |
2883 | * This reads SPTE during the page table walk. | |
2884 | * Since SPTE.W is read as 1, there is no | |
2885 | * fault. | |
2886 | * | |
2887 | * 2.2 Guest issues TLB flush. | |
2888 | * That causes a VM Exit. | |
2889 | * | |
2890 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2891 | * Since it is false, so it just returns. | |
2892 | * | |
2893 | * 2.4 Guest accesses GVA X. | |
2894 | * Since the mapping in the SP was not updated, | |
2895 | * so the old mapping for GVA X incorrectly | |
2896 | * gets used. | |
2897 | * 1.1 Host marks SP | |
2898 | * as unsync | |
2899 | * (sp->unsync = true) | |
2900 | * | |
2901 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2902 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2903 | * pairs with this write barrier. | |
2904 | */ | |
2905 | smp_wmb(); | |
2906 | ||
3d0c27ad | 2907 | return false; |
4731d4c7 MT |
2908 | } |
2909 | ||
ba049e93 | 2910 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2911 | { |
2912 | if (pfn_valid(pfn)) | |
aa2e063a HZ |
2913 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && |
2914 | /* | |
2915 | * Some reserved pages, such as those from NVDIMM | |
2916 | * DAX devices, are not for MMIO, and can be mapped | |
2917 | * with cached memory type for better performance. | |
2918 | * However, the above check misconceives those pages | |
2919 | * as MMIO, and results in KVM mapping them with UC | |
2920 | * memory type, which would hurt the performance. | |
2921 | * Therefore, we check the host memory type in addition | |
2922 | * and only treat UC/UC-/WC pages as MMIO. | |
2923 | */ | |
2924 | (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); | |
d1fe9219 | 2925 | |
0c55671f KA |
2926 | return !e820__mapped_raw_any(pfn_to_hpa(pfn), |
2927 | pfn_to_hpa(pfn + 1) - 1, | |
2928 | E820_TYPE_RAM); | |
d1fe9219 PB |
2929 | } |
2930 | ||
5ce4786f JS |
2931 | /* Bits which may be returned by set_spte() */ |
2932 | #define SET_SPTE_WRITE_PROTECTED_PT BIT(0) | |
2933 | #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1) | |
2934 | ||
d555c333 | 2935 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2936 | unsigned pte_access, int level, |
ba049e93 | 2937 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2938 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2939 | { |
ffb128c8 | 2940 | u64 spte = 0; |
1e73f9dd | 2941 | int ret = 0; |
ac8d57e5 | 2942 | struct kvm_mmu_page *sp; |
64d4d521 | 2943 | |
54bf36aa | 2944 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2945 | return 0; |
2946 | ||
ac8d57e5 PF |
2947 | sp = page_header(__pa(sptep)); |
2948 | if (sp_ad_disabled(sp)) | |
2949 | spte |= shadow_acc_track_value; | |
2950 | ||
d95c5568 BD |
2951 | /* |
2952 | * For the EPT case, shadow_present_mask is 0 if hardware | |
2953 | * supports exec-only page table entries. In that case, | |
2954 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
2955 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
2956 | */ | |
ffb128c8 | 2957 | spte |= shadow_present_mask; |
947da538 | 2958 | if (!speculative) |
ac8d57e5 | 2959 | spte |= spte_shadow_accessed_mask(spte); |
640d9b0d | 2960 | |
7b52345e SY |
2961 | if (pte_access & ACC_EXEC_MASK) |
2962 | spte |= shadow_x_mask; | |
2963 | else | |
2964 | spte |= shadow_nx_mask; | |
49fde340 | 2965 | |
1c4f1fd6 | 2966 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2967 | spte |= shadow_user_mask; |
49fde340 | 2968 | |
852e3c19 | 2969 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2970 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2971 | if (tdp_enabled) |
4b12f0de | 2972 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2973 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2974 | |
9bdbba13 | 2975 | if (host_writable) |
1403283a | 2976 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2977 | else |
2978 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2979 | |
daaf216c TL |
2980 | if (!kvm_is_mmio_pfn(pfn)) |
2981 | spte |= shadow_me_mask; | |
2982 | ||
35149e21 | 2983 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2984 | |
c2288505 | 2985 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2986 | |
c2193463 | 2987 | /* |
7751babd XG |
2988 | * Other vcpu creates new sp in the window between |
2989 | * mapping_level() and acquiring mmu-lock. We can | |
2990 | * allow guest to retry the access, the mapping can | |
2991 | * be fixed if guest refault. | |
c2193463 | 2992 | */ |
852e3c19 | 2993 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2994 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2995 | goto done; |
38187c83 | 2996 | |
49fde340 | 2997 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2998 | |
ecc5589f MT |
2999 | /* |
3000 | * Optimization: for pte sync, if spte was writable the hash | |
3001 | * lookup is unnecessary (and expensive). Write protection | |
3002 | * is responsibility of mmu_get_page / kvm_sync_page. | |
3003 | * Same reasoning can be applied to dirty page accounting. | |
3004 | */ | |
8dae4445 | 3005 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
3006 | goto set_pte; |
3007 | ||
4731d4c7 | 3008 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 3009 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 3010 | __func__, gfn); |
5ce4786f | 3011 | ret |= SET_SPTE_WRITE_PROTECTED_PT; |
1c4f1fd6 | 3012 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 3013 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
3014 | } |
3015 | } | |
3016 | ||
9b51a630 | 3017 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 3018 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
ac8d57e5 | 3019 | spte |= spte_shadow_dirty_mask(spte); |
9b51a630 | 3020 | } |
1c4f1fd6 | 3021 | |
f160c7b7 JS |
3022 | if (speculative) |
3023 | spte = mark_spte_for_access_track(spte); | |
3024 | ||
38187c83 | 3025 | set_pte: |
6e7d0354 | 3026 | if (mmu_spte_update(sptep, spte)) |
5ce4786f | 3027 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
be38d276 | 3028 | done: |
1e73f9dd MT |
3029 | return ret; |
3030 | } | |
3031 | ||
9b8ebbdb PB |
3032 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
3033 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, | |
3034 | bool speculative, bool host_writable) | |
1e73f9dd MT |
3035 | { |
3036 | int was_rmapped = 0; | |
53a27b39 | 3037 | int rmap_count; |
5ce4786f | 3038 | int set_spte_ret; |
9b8ebbdb | 3039 | int ret = RET_PF_RETRY; |
c2a4eadf | 3040 | bool flush = false; |
1e73f9dd | 3041 | |
f7616203 XG |
3042 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
3043 | *sptep, write_fault, gfn); | |
1e73f9dd | 3044 | |
afd28fe1 | 3045 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
3046 | /* |
3047 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
3048 | * the parent of the now unreachable PTE. | |
3049 | */ | |
852e3c19 JR |
3050 | if (level > PT_PAGE_TABLE_LEVEL && |
3051 | !is_large_pte(*sptep)) { | |
1e73f9dd | 3052 | struct kvm_mmu_page *child; |
d555c333 | 3053 | u64 pte = *sptep; |
1e73f9dd MT |
3054 | |
3055 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 3056 | drop_parent_pte(child, sptep); |
c2a4eadf | 3057 | flush = true; |
d555c333 | 3058 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 3059 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 3060 | spte_to_pfn(*sptep), pfn); |
c3707958 | 3061 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 3062 | flush = true; |
6bed6b9e JR |
3063 | } else |
3064 | was_rmapped = 1; | |
1e73f9dd | 3065 | } |
852e3c19 | 3066 | |
5ce4786f JS |
3067 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
3068 | speculative, true, host_writable); | |
3069 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 3070 | if (write_fault) |
9b8ebbdb | 3071 | ret = RET_PF_EMULATE; |
77c3913b | 3072 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 3073 | } |
c3134ce2 | 3074 | |
c2a4eadf | 3075 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
3076 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
3077 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 3078 | |
029499b4 | 3079 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 3080 | ret = RET_PF_EMULATE; |
ce88decf | 3081 | |
d555c333 | 3082 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 3083 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 3084 | is_large_pte(*sptep)? "2MB" : "4kB", |
f160c7b7 | 3085 | *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn, |
a205bc19 | 3086 | *sptep, sptep); |
d555c333 | 3087 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
3088 | ++vcpu->kvm->stat.lpages; |
3089 | ||
ffb61bb3 | 3090 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
3091 | if (!was_rmapped) { |
3092 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
3093 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
3094 | rmap_recycle(vcpu, sptep, gfn); | |
3095 | } | |
1c4f1fd6 | 3096 | } |
cb9aaa30 | 3097 | |
9b8ebbdb | 3098 | return ret; |
1c4f1fd6 AK |
3099 | } |
3100 | ||
ba049e93 | 3101 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
3102 | bool no_dirty_log) |
3103 | { | |
3104 | struct kvm_memory_slot *slot; | |
957ed9ef | 3105 | |
5d163b1c | 3106 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 3107 | if (!slot) |
6c8ee57b | 3108 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 3109 | |
037d92dc | 3110 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
3111 | } |
3112 | ||
3113 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
3114 | struct kvm_mmu_page *sp, | |
3115 | u64 *start, u64 *end) | |
3116 | { | |
3117 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 3118 | struct kvm_memory_slot *slot; |
957ed9ef XG |
3119 | unsigned access = sp->role.access; |
3120 | int i, ret; | |
3121 | gfn_t gfn; | |
3122 | ||
3123 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
3124 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
3125 | if (!slot) | |
957ed9ef XG |
3126 | return -1; |
3127 | ||
d9ef13c2 | 3128 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
3129 | if (ret <= 0) |
3130 | return -1; | |
3131 | ||
43fdcda9 | 3132 | for (i = 0; i < ret; i++, gfn++, start++) { |
029499b4 TY |
3133 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
3134 | page_to_pfn(pages[i]), true, true); | |
43fdcda9 JS |
3135 | put_page(pages[i]); |
3136 | } | |
957ed9ef XG |
3137 | |
3138 | return 0; | |
3139 | } | |
3140 | ||
3141 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
3142 | struct kvm_mmu_page *sp, u64 *sptep) | |
3143 | { | |
3144 | u64 *spte, *start = NULL; | |
3145 | int i; | |
3146 | ||
3147 | WARN_ON(!sp->role.direct); | |
3148 | ||
3149 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
3150 | spte = sp->spt + i; | |
3151 | ||
3152 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 3153 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
3154 | if (!start) |
3155 | continue; | |
3156 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
3157 | break; | |
3158 | start = NULL; | |
3159 | } else if (!start) | |
3160 | start = spte; | |
3161 | } | |
3162 | } | |
3163 | ||
3164 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
3165 | { | |
3166 | struct kvm_mmu_page *sp; | |
3167 | ||
ac8d57e5 PF |
3168 | sp = page_header(__pa(sptep)); |
3169 | ||
957ed9ef | 3170 | /* |
ac8d57e5 PF |
3171 | * Without accessed bits, there's no way to distinguish between |
3172 | * actually accessed translations and prefetched, so disable pte | |
3173 | * prefetch if accessed bits aren't available. | |
957ed9ef | 3174 | */ |
ac8d57e5 | 3175 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
3176 | return; |
3177 | ||
957ed9ef XG |
3178 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
3179 | return; | |
3180 | ||
3181 | __direct_pte_prefetch(vcpu, sp, sptep); | |
3182 | } | |
3183 | ||
3fcf2d1b PB |
3184 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, int write, |
3185 | int map_writable, int level, kvm_pfn_t pfn, | |
3186 | bool prefault) | |
140754bc | 3187 | { |
3fcf2d1b | 3188 | struct kvm_shadow_walk_iterator it; |
140754bc | 3189 | struct kvm_mmu_page *sp; |
3fcf2d1b PB |
3190 | int ret; |
3191 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
3192 | gfn_t base_gfn = gfn; | |
6aa8b732 | 3193 | |
44dd3ffa | 3194 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
3fcf2d1b | 3195 | return RET_PF_RETRY; |
989c6b34 | 3196 | |
3fcf2d1b PB |
3197 | for_each_shadow_entry(vcpu, gpa, it) { |
3198 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); | |
3199 | if (it.level == level) | |
9f652d21 | 3200 | break; |
6aa8b732 | 3201 | |
3fcf2d1b PB |
3202 | drop_large_spte(vcpu, it.sptep); |
3203 | if (!is_shadow_present_pte(*it.sptep)) { | |
3204 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
3205 | it.level - 1, true, ACC_ALL); | |
c9fa0b3b | 3206 | |
3fcf2d1b | 3207 | link_shadow_page(vcpu, it.sptep, sp); |
9f652d21 AK |
3208 | } |
3209 | } | |
3fcf2d1b PB |
3210 | |
3211 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
3212 | write, level, base_gfn, pfn, prefault, | |
3213 | map_writable); | |
3214 | direct_pte_prefetch(vcpu, it.sptep); | |
3215 | ++vcpu->stat.pf_fixed; | |
3216 | return ret; | |
6aa8b732 AK |
3217 | } |
3218 | ||
77db5cbd | 3219 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 3220 | { |
585a8b9b | 3221 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
3222 | } |
3223 | ||
ba049e93 | 3224 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 3225 | { |
4d8b81ab XG |
3226 | /* |
3227 | * Do not cache the mmio info caused by writing the readonly gfn | |
3228 | * into the spte otherwise read access on readonly gfn also can | |
3229 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
3230 | */ |
3231 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 3232 | return RET_PF_EMULATE; |
4d8b81ab | 3233 | |
e6c1502b | 3234 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3235 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 3236 | return RET_PF_RETRY; |
d7c55201 | 3237 | } |
edba23e5 | 3238 | |
2c151b25 | 3239 | return -EFAULT; |
bf998156 HY |
3240 | } |
3241 | ||
936a5fe6 | 3242 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
d679b326 | 3243 | gfn_t gfn, kvm_pfn_t *pfnp, |
ba049e93 | 3244 | int *levelp) |
936a5fe6 | 3245 | { |
ba049e93 | 3246 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
3247 | int level = *levelp; |
3248 | ||
3249 | /* | |
3250 | * Check if it's a transparent hugepage. If this would be an | |
3251 | * hugetlbfs page, level wouldn't be set to | |
3252 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
3253 | * here. | |
3254 | */ | |
bf4bea8e | 3255 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 | 3256 | level == PT_PAGE_TABLE_LEVEL && |
127393fb | 3257 | PageTransCompoundMap(pfn_to_page(pfn)) && |
92f94f1e | 3258 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
3259 | unsigned long mask; |
3260 | /* | |
3261 | * mmu_notifier_retry was successful and we hold the | |
3262 | * mmu_lock here, so the pmd can't become splitting | |
3263 | * from under us, and in turn | |
3264 | * __split_huge_page_refcount() can't run from under | |
3265 | * us and we can safely transfer the refcount from | |
3266 | * PG_tail to PG_head as we switch the pfn to tail to | |
3267 | * head. | |
3268 | */ | |
3269 | *levelp = level = PT_DIRECTORY_LEVEL; | |
3270 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
3271 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
3272 | if (pfn & mask) { | |
936a5fe6 AA |
3273 | kvm_release_pfn_clean(pfn); |
3274 | pfn &= ~mask; | |
c3586667 | 3275 | kvm_get_pfn(pfn); |
936a5fe6 AA |
3276 | *pfnp = pfn; |
3277 | } | |
3278 | } | |
3279 | } | |
3280 | ||
d7c55201 | 3281 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 3282 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 3283 | { |
d7c55201 | 3284 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3285 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3286 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3287 | return true; |
d7c55201 XG |
3288 | } |
3289 | ||
ce88decf | 3290 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 3291 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 3292 | |
798e88b3 | 3293 | return false; |
d7c55201 XG |
3294 | } |
3295 | ||
e5552fd2 | 3296 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3297 | { |
1c118b82 XG |
3298 | /* |
3299 | * Do not fix the mmio spte with invalid generation number which | |
3300 | * need to be updated by slow page fault path. | |
3301 | */ | |
3302 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3303 | return false; | |
3304 | ||
f160c7b7 JS |
3305 | /* See if the page fault is due to an NX violation */ |
3306 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3307 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3308 | return false; | |
3309 | ||
c7ba5b48 | 3310 | /* |
f160c7b7 JS |
3311 | * #PF can be fast if: |
3312 | * 1. The shadow page table entry is not present, which could mean that | |
3313 | * the fault is potentially caused by access tracking (if enabled). | |
3314 | * 2. The shadow page table entry is present and the fault | |
3315 | * is caused by write-protect, that means we just need change the W | |
3316 | * bit of the spte which can be done out of mmu-lock. | |
3317 | * | |
3318 | * However, if access tracking is disabled we know that a non-present | |
3319 | * page must be a genuine page fault where we have to create a new SPTE. | |
3320 | * So, if access tracking is disabled, we return true only for write | |
3321 | * accesses to a present page. | |
c7ba5b48 | 3322 | */ |
c7ba5b48 | 3323 | |
f160c7b7 JS |
3324 | return shadow_acc_track_mask != 0 || |
3325 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3326 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3327 | } |
3328 | ||
97dceba2 JS |
3329 | /* |
3330 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3331 | * someone else modified the SPTE from its original value. | |
3332 | */ | |
c7ba5b48 | 3333 | static bool |
92a476cb | 3334 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3335 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3336 | { |
c7ba5b48 XG |
3337 | gfn_t gfn; |
3338 | ||
3339 | WARN_ON(!sp->role.direct); | |
3340 | ||
9b51a630 KH |
3341 | /* |
3342 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3343 | * order to eliminate unnecessary PML logging. See comments in | |
3344 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3345 | * enabled, so we do not do this. This might result in the same GPA | |
3346 | * to be logged in PML buffer again when the write really happens, and | |
3347 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3348 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3349 | * so non-PML cases won't be impacted. | |
3350 | * | |
3351 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3352 | */ | |
f160c7b7 | 3353 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3354 | return false; |
3355 | ||
d3e328f2 | 3356 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3357 | /* |
3358 | * The gfn of direct spte is stable since it is | |
3359 | * calculated by sp->gfn. | |
3360 | */ | |
3361 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3362 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3363 | } | |
c7ba5b48 XG |
3364 | |
3365 | return true; | |
3366 | } | |
3367 | ||
d3e328f2 JS |
3368 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3369 | { | |
3370 | if (fault_err_code & PFERR_FETCH_MASK) | |
3371 | return is_executable_pte(spte); | |
3372 | ||
3373 | if (fault_err_code & PFERR_WRITE_MASK) | |
3374 | return is_writable_pte(spte); | |
3375 | ||
3376 | /* Fault was on Read access */ | |
3377 | return spte & PT_PRESENT_MASK; | |
3378 | } | |
3379 | ||
c7ba5b48 XG |
3380 | /* |
3381 | * Return value: | |
3382 | * - true: let the vcpu to access on the same address again. | |
3383 | * - false: let the real page fault path to fix it. | |
3384 | */ | |
3385 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
3386 | u32 error_code) | |
3387 | { | |
3388 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3389 | struct kvm_mmu_page *sp; |
97dceba2 | 3390 | bool fault_handled = false; |
c7ba5b48 | 3391 | u64 spte = 0ull; |
97dceba2 | 3392 | uint retry_count = 0; |
c7ba5b48 | 3393 | |
44dd3ffa | 3394 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
37f6a4e2 MT |
3395 | return false; |
3396 | ||
e5552fd2 | 3397 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3398 | return false; |
3399 | ||
3400 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3401 | |
97dceba2 | 3402 | do { |
d3e328f2 | 3403 | u64 new_spte; |
c7ba5b48 | 3404 | |
d162f30a JS |
3405 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) |
3406 | if (!is_shadow_present_pte(spte) || | |
3407 | iterator.level < level) | |
3408 | break; | |
3409 | ||
97dceba2 JS |
3410 | sp = page_header(__pa(iterator.sptep)); |
3411 | if (!is_last_spte(spte, sp->role.level)) | |
3412 | break; | |
c7ba5b48 | 3413 | |
97dceba2 | 3414 | /* |
f160c7b7 JS |
3415 | * Check whether the memory access that caused the fault would |
3416 | * still cause it if it were to be performed right now. If not, | |
3417 | * then this is a spurious fault caused by TLB lazily flushed, | |
3418 | * or some other CPU has already fixed the PTE after the | |
3419 | * current CPU took the fault. | |
97dceba2 JS |
3420 | * |
3421 | * Need not check the access of upper level table entries since | |
3422 | * they are always ACC_ALL. | |
3423 | */ | |
d3e328f2 JS |
3424 | if (is_access_allowed(error_code, spte)) { |
3425 | fault_handled = true; | |
3426 | break; | |
3427 | } | |
f160c7b7 | 3428 | |
d3e328f2 JS |
3429 | new_spte = spte; |
3430 | ||
3431 | if (is_access_track_spte(spte)) | |
3432 | new_spte = restore_acc_track_spte(new_spte); | |
3433 | ||
3434 | /* | |
3435 | * Currently, to simplify the code, write-protection can | |
3436 | * be removed in the fast path only if the SPTE was | |
3437 | * write-protected for dirty-logging or access tracking. | |
3438 | */ | |
3439 | if ((error_code & PFERR_WRITE_MASK) && | |
3440 | spte_can_locklessly_be_made_writable(spte)) | |
3441 | { | |
3442 | new_spte |= PT_WRITABLE_MASK; | |
f160c7b7 JS |
3443 | |
3444 | /* | |
d3e328f2 JS |
3445 | * Do not fix write-permission on the large spte. Since |
3446 | * we only dirty the first page into the dirty-bitmap in | |
3447 | * fast_pf_fix_direct_spte(), other pages are missed | |
3448 | * if its slot has dirty logging enabled. | |
3449 | * | |
3450 | * Instead, we let the slow page fault path create a | |
3451 | * normal spte to fix the access. | |
3452 | * | |
3453 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3454 | */ |
d3e328f2 | 3455 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3456 | break; |
97dceba2 | 3457 | } |
c7ba5b48 | 3458 | |
f160c7b7 | 3459 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3460 | if (new_spte == spte || |
3461 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3462 | break; |
3463 | ||
3464 | /* | |
3465 | * Currently, fast page fault only works for direct mapping | |
3466 | * since the gfn is not stable for indirect shadow page. See | |
3467 | * Documentation/virtual/kvm/locking.txt to get more detail. | |
3468 | */ | |
3469 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3470 | iterator.sptep, spte, |
d3e328f2 | 3471 | new_spte); |
97dceba2 JS |
3472 | if (fault_handled) |
3473 | break; | |
3474 | ||
3475 | if (++retry_count > 4) { | |
3476 | printk_once(KERN_WARNING | |
3477 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3478 | break; | |
3479 | } | |
3480 | ||
97dceba2 | 3481 | } while (true); |
c126d94f | 3482 | |
a72faf25 | 3483 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
97dceba2 | 3484 | spte, fault_handled); |
c7ba5b48 XG |
3485 | walk_shadow_page_lockless_end(vcpu); |
3486 | ||
97dceba2 | 3487 | return fault_handled; |
c7ba5b48 XG |
3488 | } |
3489 | ||
78b2c54a | 3490 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3491 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
26eeb53c | 3492 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3493 | |
c7ba5b48 XG |
3494 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3495 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3496 | { |
3497 | int r; | |
852e3c19 | 3498 | int level; |
fd136902 | 3499 | bool force_pt_level = false; |
ba049e93 | 3500 | kvm_pfn_t pfn; |
e930bffe | 3501 | unsigned long mmu_seq; |
c7ba5b48 | 3502 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3503 | |
fd136902 | 3504 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3505 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3506 | /* |
3507 | * This path builds a PAE pagetable - so we can map | |
3508 | * 2mb pages at maximum. Therefore check if the level | |
3509 | * is larger than that. | |
3510 | */ | |
3511 | if (level > PT_DIRECTORY_LEVEL) | |
3512 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3513 | |
936a5fe6 | 3514 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3515 | } |
05da4558 | 3516 | |
c7ba5b48 | 3517 | if (fast_page_fault(vcpu, v, level, error_code)) |
9b8ebbdb | 3518 | return RET_PF_RETRY; |
c7ba5b48 | 3519 | |
e930bffe | 3520 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3521 | smp_rmb(); |
060c2abe | 3522 | |
78b2c54a | 3523 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
9b8ebbdb | 3524 | return RET_PF_RETRY; |
aaee2c94 | 3525 | |
d7c55201 XG |
3526 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3527 | return r; | |
d196e343 | 3528 | |
43fdcda9 | 3529 | r = RET_PF_RETRY; |
aaee2c94 | 3530 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3531 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3532 | goto out_unlock; |
26eeb53c WL |
3533 | if (make_mmu_pages_available(vcpu) < 0) |
3534 | goto out_unlock; | |
936a5fe6 | 3535 | if (likely(!force_pt_level)) |
d679b326 | 3536 | transparent_hugepage_adjust(vcpu, gfn, &pfn, &level); |
3fcf2d1b | 3537 | r = __direct_map(vcpu, v, write, map_writable, level, pfn, prefault); |
e930bffe AA |
3538 | out_unlock: |
3539 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3540 | kvm_release_pfn_clean(pfn); | |
43fdcda9 | 3541 | return r; |
10589a46 MT |
3542 | } |
3543 | ||
74b566e6 JS |
3544 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3545 | struct list_head *invalid_list) | |
17ac10ad | 3546 | { |
4db35314 | 3547 | struct kvm_mmu_page *sp; |
17ac10ad | 3548 | |
74b566e6 | 3549 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3550 | return; |
35af577a | 3551 | |
74b566e6 JS |
3552 | sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK); |
3553 | --sp->root_count; | |
3554 | if (!sp->root_count && sp->role.invalid) | |
3555 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3556 | |
74b566e6 JS |
3557 | *root_hpa = INVALID_PAGE; |
3558 | } | |
3559 | ||
08fb59d8 | 3560 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3561 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3562 | ulong roots_to_free) | |
74b566e6 JS |
3563 | { |
3564 | int i; | |
3565 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3566 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3567 | |
b94742c9 | 3568 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3569 | |
08fb59d8 | 3570 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3571 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3572 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3573 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3574 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3575 | break; | |
3576 | ||
3577 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3578 | return; | |
3579 | } | |
35af577a GN |
3580 | |
3581 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3582 | |
b94742c9 JS |
3583 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3584 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
3585 | mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa, | |
3586 | &invalid_list); | |
7c390d35 | 3587 | |
08fb59d8 JS |
3588 | if (free_active_root) { |
3589 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3590 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
3591 | mmu_free_root_page(vcpu->kvm, &mmu->root_hpa, | |
3592 | &invalid_list); | |
3593 | } else { | |
3594 | for (i = 0; i < 4; ++i) | |
3595 | if (mmu->pae_root[i] != 0) | |
3596 | mmu_free_root_page(vcpu->kvm, | |
3597 | &mmu->pae_root[i], | |
3598 | &invalid_list); | |
3599 | mmu->root_hpa = INVALID_PAGE; | |
3600 | } | |
ad7dc69a | 3601 | mmu->root_cr3 = 0; |
17ac10ad | 3602 | } |
74b566e6 | 3603 | |
d98ba053 | 3604 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3605 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad | 3606 | } |
74b566e6 | 3607 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3608 | |
8986ecc0 MT |
3609 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3610 | { | |
3611 | int ret = 0; | |
3612 | ||
3613 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3614 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3615 | ret = 1; |
3616 | } | |
3617 | ||
3618 | return ret; | |
3619 | } | |
3620 | ||
651dd37a JR |
3621 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3622 | { | |
3623 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3624 | unsigned i; |
651dd37a | 3625 | |
44dd3ffa | 3626 | if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) { |
651dd37a | 3627 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3628 | if(make_mmu_pages_available(vcpu) < 0) { |
3629 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3630 | return -ENOSPC; |
26eeb53c | 3631 | } |
855feb67 | 3632 | sp = kvm_mmu_get_page(vcpu, 0, 0, |
44dd3ffa | 3633 | vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL); |
651dd37a JR |
3634 | ++sp->root_count; |
3635 | spin_unlock(&vcpu->kvm->mmu_lock); | |
44dd3ffa VK |
3636 | vcpu->arch.mmu->root_hpa = __pa(sp->spt); |
3637 | } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) { | |
651dd37a | 3638 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3639 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
651dd37a | 3640 | |
fa4a2c08 | 3641 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3642 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3643 | if (make_mmu_pages_available(vcpu) < 0) { |
3644 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3645 | return -ENOSPC; |
26eeb53c | 3646 | } |
649497d1 | 3647 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3648 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3649 | root = __pa(sp->spt); |
3650 | ++sp->root_count; | |
3651 | spin_unlock(&vcpu->kvm->mmu_lock); | |
44dd3ffa | 3652 | vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK; |
651dd37a | 3653 | } |
44dd3ffa | 3654 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
651dd37a JR |
3655 | } else |
3656 | BUG(); | |
ad7dc69a | 3657 | vcpu->arch.mmu->root_cr3 = vcpu->arch.mmu->get_cr3(vcpu); |
651dd37a JR |
3658 | |
3659 | return 0; | |
3660 | } | |
3661 | ||
3662 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3663 | { |
4db35314 | 3664 | struct kvm_mmu_page *sp; |
81407ca5 | 3665 | u64 pdptr, pm_mask; |
ad7dc69a | 3666 | gfn_t root_gfn, root_cr3; |
81407ca5 | 3667 | int i; |
3bb65a22 | 3668 | |
ad7dc69a VK |
3669 | root_cr3 = vcpu->arch.mmu->get_cr3(vcpu); |
3670 | root_gfn = root_cr3 >> PAGE_SHIFT; | |
17ac10ad | 3671 | |
651dd37a JR |
3672 | if (mmu_check_root(vcpu, root_gfn)) |
3673 | return 1; | |
3674 | ||
3675 | /* | |
3676 | * Do we shadow a long mode page table? If so we need to | |
3677 | * write-protect the guests page table root. | |
3678 | */ | |
44dd3ffa VK |
3679 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3680 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
17ac10ad | 3681 | |
fa4a2c08 | 3682 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3683 | |
8facbbff | 3684 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3685 | if (make_mmu_pages_available(vcpu) < 0) { |
3686 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3687 | return -ENOSPC; |
26eeb53c | 3688 | } |
855feb67 | 3689 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
44dd3ffa | 3690 | vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL); |
4db35314 AK |
3691 | root = __pa(sp->spt); |
3692 | ++sp->root_count; | |
8facbbff | 3693 | spin_unlock(&vcpu->kvm->mmu_lock); |
44dd3ffa | 3694 | vcpu->arch.mmu->root_hpa = root; |
ad7dc69a | 3695 | goto set_root_cr3; |
17ac10ad | 3696 | } |
f87f9288 | 3697 | |
651dd37a JR |
3698 | /* |
3699 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3700 | * or a PAE 3-level page table. In either case we need to be aware that |
3701 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3702 | */ |
81407ca5 | 3703 | pm_mask = PT_PRESENT_MASK; |
44dd3ffa | 3704 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
81407ca5 JR |
3705 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3706 | ||
17ac10ad | 3707 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3708 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
17ac10ad | 3709 | |
fa4a2c08 | 3710 | MMU_WARN_ON(VALID_PAGE(root)); |
44dd3ffa VK |
3711 | if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) { |
3712 | pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i); | |
812f30b2 | 3713 | if (!(pdptr & PT_PRESENT_MASK)) { |
44dd3ffa | 3714 | vcpu->arch.mmu->pae_root[i] = 0; |
417726a3 AK |
3715 | continue; |
3716 | } | |
6de4f3ad | 3717 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3718 | if (mmu_check_root(vcpu, root_gfn)) |
3719 | return 1; | |
5a7388c2 | 3720 | } |
8facbbff | 3721 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3722 | if (make_mmu_pages_available(vcpu) < 0) { |
3723 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3724 | return -ENOSPC; |
26eeb53c | 3725 | } |
bb11c6c9 TY |
3726 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3727 | 0, ACC_ALL); | |
4db35314 AK |
3728 | root = __pa(sp->spt); |
3729 | ++sp->root_count; | |
8facbbff AK |
3730 | spin_unlock(&vcpu->kvm->mmu_lock); |
3731 | ||
44dd3ffa | 3732 | vcpu->arch.mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3733 | } |
44dd3ffa | 3734 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
81407ca5 JR |
3735 | |
3736 | /* | |
3737 | * If we shadow a 32 bit page table with a long mode page | |
3738 | * table we enter this path. | |
3739 | */ | |
44dd3ffa VK |
3740 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
3741 | if (vcpu->arch.mmu->lm_root == NULL) { | |
81407ca5 JR |
3742 | /* |
3743 | * The additional page necessary for this is only | |
3744 | * allocated on demand. | |
3745 | */ | |
3746 | ||
3747 | u64 *lm_root; | |
3748 | ||
254272ce | 3749 | lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
81407ca5 JR |
3750 | if (lm_root == NULL) |
3751 | return 1; | |
3752 | ||
44dd3ffa | 3753 | lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask; |
81407ca5 | 3754 | |
44dd3ffa | 3755 | vcpu->arch.mmu->lm_root = lm_root; |
81407ca5 JR |
3756 | } |
3757 | ||
44dd3ffa | 3758 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root); |
81407ca5 JR |
3759 | } |
3760 | ||
ad7dc69a VK |
3761 | set_root_cr3: |
3762 | vcpu->arch.mmu->root_cr3 = root_cr3; | |
3763 | ||
8986ecc0 | 3764 | return 0; |
17ac10ad AK |
3765 | } |
3766 | ||
651dd37a JR |
3767 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3768 | { | |
44dd3ffa | 3769 | if (vcpu->arch.mmu->direct_map) |
651dd37a JR |
3770 | return mmu_alloc_direct_roots(vcpu); |
3771 | else | |
3772 | return mmu_alloc_shadow_roots(vcpu); | |
3773 | } | |
3774 | ||
578e1c4d | 3775 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3776 | { |
3777 | int i; | |
3778 | struct kvm_mmu_page *sp; | |
3779 | ||
44dd3ffa | 3780 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3781 | return; |
3782 | ||
44dd3ffa | 3783 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3784 | return; |
6903074c | 3785 | |
56f17dd3 | 3786 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3787 | |
44dd3ffa VK |
3788 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3789 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
0ba73cda | 3790 | sp = page_header(root); |
578e1c4d JS |
3791 | |
3792 | /* | |
3793 | * Even if another CPU was marking the SP as unsync-ed | |
3794 | * simultaneously, any guest page table changes are not | |
3795 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3796 | * flush strictly after those changes are made. We only need to | |
3797 | * ensure that the other CPU sets these flags before any actual | |
3798 | * changes to the page tables are made. The comments in | |
3799 | * mmu_need_write_protect() describe what could go wrong if this | |
3800 | * requirement isn't satisfied. | |
3801 | */ | |
3802 | if (!smp_load_acquire(&sp->unsync) && | |
3803 | !smp_load_acquire(&sp->unsync_children)) | |
3804 | return; | |
3805 | ||
3806 | spin_lock(&vcpu->kvm->mmu_lock); | |
3807 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3808 | ||
0ba73cda | 3809 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3810 | |
0375f7fa | 3811 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
578e1c4d | 3812 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3813 | return; |
3814 | } | |
578e1c4d JS |
3815 | |
3816 | spin_lock(&vcpu->kvm->mmu_lock); | |
3817 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3818 | ||
0ba73cda | 3819 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3820 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3821 | |
8986ecc0 | 3822 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3823 | root &= PT64_BASE_ADDR_MASK; |
3824 | sp = page_header(root); | |
3825 | mmu_sync_children(vcpu, sp); | |
3826 | } | |
3827 | } | |
0ba73cda | 3828 | |
578e1c4d | 3829 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
6cffe8ca | 3830 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3831 | } |
bfd0a56b | 3832 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3833 | |
1871c602 | 3834 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3835 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3836 | { |
ab9ae313 AK |
3837 | if (exception) |
3838 | exception->error_code = 0; | |
6aa8b732 AK |
3839 | return vaddr; |
3840 | } | |
3841 | ||
6539e738 | 3842 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3843 | u32 access, |
3844 | struct x86_exception *exception) | |
6539e738 | 3845 | { |
ab9ae313 AK |
3846 | if (exception) |
3847 | exception->error_code = 0; | |
54987b7a | 3848 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3849 | } |
3850 | ||
d625b155 XG |
3851 | static bool |
3852 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3853 | { | |
3854 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3855 | ||
3856 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3857 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3858 | } | |
3859 | ||
3860 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3861 | { | |
3862 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3863 | } | |
3864 | ||
3865 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3866 | { | |
3867 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3868 | } | |
3869 | ||
ded58749 | 3870 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3871 | { |
9034e6e8 PB |
3872 | /* |
3873 | * A nested guest cannot use the MMIO cache if it is using nested | |
3874 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3875 | */ | |
3876 | if (mmu_is_nested(vcpu)) | |
3877 | return false; | |
3878 | ||
ce88decf XG |
3879 | if (direct) |
3880 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3881 | ||
3882 | return vcpu_match_mmio_gva(vcpu, addr); | |
3883 | } | |
3884 | ||
47ab8751 XG |
3885 | /* return true if reserved bit is detected on spte. */ |
3886 | static bool | |
3887 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3888 | { |
3889 | struct kvm_shadow_walk_iterator iterator; | |
2a7266a8 | 3890 | u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull; |
47ab8751 XG |
3891 | int root, leaf; |
3892 | bool reserved = false; | |
ce88decf | 3893 | |
44dd3ffa | 3894 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
47ab8751 | 3895 | goto exit; |
37f6a4e2 | 3896 | |
ce88decf | 3897 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3898 | |
29ecd660 PB |
3899 | for (shadow_walk_init(&iterator, vcpu, addr), |
3900 | leaf = root = iterator.level; | |
47ab8751 XG |
3901 | shadow_walk_okay(&iterator); |
3902 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3903 | spte = mmu_spte_get_lockless(iterator.sptep); |
3904 | ||
3905 | sptes[leaf - 1] = spte; | |
29ecd660 | 3906 | leaf--; |
47ab8751 | 3907 | |
ce88decf XG |
3908 | if (!is_shadow_present_pte(spte)) |
3909 | break; | |
47ab8751 | 3910 | |
44dd3ffa | 3911 | reserved |= is_shadow_zero_bits_set(vcpu->arch.mmu, spte, |
58c95070 | 3912 | iterator.level); |
47ab8751 XG |
3913 | } |
3914 | ||
ce88decf XG |
3915 | walk_shadow_page_lockless_end(vcpu); |
3916 | ||
47ab8751 XG |
3917 | if (reserved) { |
3918 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3919 | __func__, addr); | |
29ecd660 | 3920 | while (root > leaf) { |
47ab8751 XG |
3921 | pr_err("------ spte 0x%llx level %d.\n", |
3922 | sptes[root - 1], root); | |
3923 | root--; | |
3924 | } | |
3925 | } | |
3926 | exit: | |
3927 | *sptep = spte; | |
3928 | return reserved; | |
ce88decf XG |
3929 | } |
3930 | ||
e08d26f0 | 3931 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3932 | { |
3933 | u64 spte; | |
47ab8751 | 3934 | bool reserved; |
ce88decf | 3935 | |
ded58749 | 3936 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3937 | return RET_PF_EMULATE; |
ce88decf | 3938 | |
47ab8751 | 3939 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3940 | if (WARN_ON(reserved)) |
9b8ebbdb | 3941 | return -EINVAL; |
ce88decf XG |
3942 | |
3943 | if (is_mmio_spte(spte)) { | |
3944 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3945 | unsigned access = get_mmio_spte_access(spte); | |
3946 | ||
54bf36aa | 3947 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3948 | return RET_PF_INVALID; |
f8f55942 | 3949 | |
ce88decf XG |
3950 | if (direct) |
3951 | addr = 0; | |
4f022648 XG |
3952 | |
3953 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3954 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3955 | return RET_PF_EMULATE; |
ce88decf XG |
3956 | } |
3957 | ||
ce88decf XG |
3958 | /* |
3959 | * If the page table is zapped by other cpus, let CPU fault again on | |
3960 | * the address. | |
3961 | */ | |
9b8ebbdb | 3962 | return RET_PF_RETRY; |
ce88decf | 3963 | } |
ce88decf | 3964 | |
3d0c27ad XG |
3965 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3966 | u32 error_code, gfn_t gfn) | |
3967 | { | |
3968 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3969 | return false; | |
3970 | ||
3971 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3972 | !(error_code & PFERR_WRITE_MASK)) | |
3973 | return false; | |
3974 | ||
3975 | /* | |
3976 | * guest is writing the page which is write tracked which can | |
3977 | * not be fixed by page fault handler. | |
3978 | */ | |
3979 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3980 | return true; | |
3981 | ||
3982 | return false; | |
3983 | } | |
3984 | ||
e5691a81 XG |
3985 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3986 | { | |
3987 | struct kvm_shadow_walk_iterator iterator; | |
3988 | u64 spte; | |
3989 | ||
44dd3ffa | 3990 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
e5691a81 XG |
3991 | return; |
3992 | ||
3993 | walk_shadow_page_lockless_begin(vcpu); | |
3994 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3995 | clear_sp_write_flooding_count(iterator.sptep); | |
3996 | if (!is_shadow_present_pte(spte)) | |
3997 | break; | |
3998 | } | |
3999 | walk_shadow_page_lockless_end(vcpu); | |
4000 | } | |
4001 | ||
6aa8b732 | 4002 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 4003 | u32 error_code, bool prefault) |
6aa8b732 | 4004 | { |
3d0c27ad | 4005 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 4006 | int r; |
6aa8b732 | 4007 | |
b8688d51 | 4008 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 4009 | |
3d0c27ad | 4010 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 4011 | return RET_PF_EMULATE; |
ce88decf | 4012 | |
e2dec939 AK |
4013 | r = mmu_topup_memory_caches(vcpu); |
4014 | if (r) | |
4015 | return r; | |
714b93da | 4016 | |
44dd3ffa | 4017 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)); |
6aa8b732 | 4018 | |
6aa8b732 | 4019 | |
e833240f | 4020 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 4021 | error_code, gfn, prefault); |
6aa8b732 AK |
4022 | } |
4023 | ||
7e1fbeac | 4024 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
4025 | { |
4026 | struct kvm_arch_async_pf arch; | |
fb67e14f | 4027 | |
7c90705b | 4028 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 4029 | arch.gfn = gfn; |
44dd3ffa VK |
4030 | arch.direct_map = vcpu->arch.mmu->direct_map; |
4031 | arch.cr3 = vcpu->arch.mmu->get_cr3(vcpu); | |
af585b92 | 4032 | |
54bf36aa | 4033 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
4034 | } |
4035 | ||
78b2c54a | 4036 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 4037 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 4038 | { |
3520469d | 4039 | struct kvm_memory_slot *slot; |
af585b92 GN |
4040 | bool async; |
4041 | ||
3a2936de JM |
4042 | /* |
4043 | * Don't expose private memslots to L2. | |
4044 | */ | |
4045 | if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
4046 | *pfn = KVM_PFN_NOSLOT; | |
4047 | return false; | |
4048 | } | |
4049 | ||
54bf36aa | 4050 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
4051 | async = false; |
4052 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
4053 | if (!async) |
4054 | return false; /* *pfn has correct page already */ | |
4055 | ||
9bc1f09f | 4056 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
c9b263d2 | 4057 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
4058 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
4059 | trace_kvm_async_pf_doublefault(gva, gfn); | |
4060 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
4061 | return true; | |
4062 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
4063 | return true; | |
4064 | } | |
4065 | ||
3520469d | 4066 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
4067 | return false; |
4068 | } | |
4069 | ||
1261bfa3 | 4070 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 4071 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
4072 | { |
4073 | int r = 1; | |
4074 | ||
c595ceee | 4075 | vcpu->arch.l1tf_flush_l1d = true; |
1261bfa3 WL |
4076 | switch (vcpu->arch.apf.host_apf_reason) { |
4077 | default: | |
4078 | trace_kvm_page_fault(fault_address, error_code); | |
4079 | ||
d0006530 | 4080 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
4081 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
4082 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
4083 | insn_len); | |
4084 | break; | |
4085 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
4086 | vcpu->arch.apf.host_apf_reason = 0; | |
4087 | local_irq_disable(); | |
a2b7861b | 4088 | kvm_async_pf_task_wait(fault_address, 0); |
1261bfa3 WL |
4089 | local_irq_enable(); |
4090 | break; | |
4091 | case KVM_PV_REASON_PAGE_READY: | |
4092 | vcpu->arch.apf.host_apf_reason = 0; | |
4093 | local_irq_disable(); | |
4094 | kvm_async_pf_task_wake(fault_address); | |
4095 | local_irq_enable(); | |
4096 | break; | |
4097 | } | |
4098 | return r; | |
4099 | } | |
4100 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
4101 | ||
6a39bbc5 XG |
4102 | static bool |
4103 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
4104 | { | |
4105 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
4106 | ||
4107 | gfn &= ~(page_num - 1); | |
4108 | ||
4109 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
4110 | } | |
4111 | ||
56028d08 | 4112 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 4113 | bool prefault) |
fb72d167 | 4114 | { |
ba049e93 | 4115 | kvm_pfn_t pfn; |
fb72d167 | 4116 | int r; |
852e3c19 | 4117 | int level; |
cd1872f0 | 4118 | bool force_pt_level; |
05da4558 | 4119 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 4120 | unsigned long mmu_seq; |
612819c3 MT |
4121 | int write = error_code & PFERR_WRITE_MASK; |
4122 | bool map_writable; | |
fb72d167 | 4123 | |
44dd3ffa | 4124 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)); |
fb72d167 | 4125 | |
3d0c27ad | 4126 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 4127 | return RET_PF_EMULATE; |
ce88decf | 4128 | |
fb72d167 JR |
4129 | r = mmu_topup_memory_caches(vcpu); |
4130 | if (r) | |
4131 | return r; | |
4132 | ||
fd136902 TY |
4133 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
4134 | PT_DIRECTORY_LEVEL); | |
4135 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 4136 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
4137 | if (level > PT_DIRECTORY_LEVEL && |
4138 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
4139 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 4140 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 4141 | } |
852e3c19 | 4142 | |
c7ba5b48 | 4143 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
9b8ebbdb | 4144 | return RET_PF_RETRY; |
c7ba5b48 | 4145 | |
e930bffe | 4146 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 4147 | smp_rmb(); |
af585b92 | 4148 | |
78b2c54a | 4149 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
9b8ebbdb | 4150 | return RET_PF_RETRY; |
af585b92 | 4151 | |
d7c55201 XG |
4152 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
4153 | return r; | |
4154 | ||
43fdcda9 | 4155 | r = RET_PF_RETRY; |
fb72d167 | 4156 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 4157 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 4158 | goto out_unlock; |
26eeb53c WL |
4159 | if (make_mmu_pages_available(vcpu) < 0) |
4160 | goto out_unlock; | |
936a5fe6 | 4161 | if (likely(!force_pt_level)) |
d679b326 | 4162 | transparent_hugepage_adjust(vcpu, gfn, &pfn, &level); |
3fcf2d1b | 4163 | r = __direct_map(vcpu, gpa, write, map_writable, level, pfn, prefault); |
e930bffe AA |
4164 | out_unlock: |
4165 | spin_unlock(&vcpu->kvm->mmu_lock); | |
4166 | kvm_release_pfn_clean(pfn); | |
43fdcda9 | 4167 | return r; |
fb72d167 JR |
4168 | } |
4169 | ||
8a3c1a33 PB |
4170 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
4171 | struct kvm_mmu *context) | |
6aa8b732 | 4172 | { |
6aa8b732 | 4173 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 4174 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 4175 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4176 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4177 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 4178 | context->root_level = 0; |
6aa8b732 | 4179 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4180 | context->direct_map = true; |
2d48a985 | 4181 | context->nx = false; |
6aa8b732 AK |
4182 | } |
4183 | ||
b94742c9 JS |
4184 | /* |
4185 | * Find out if a previously cached root matching the new CR3/role is available. | |
4186 | * The current root is also inserted into the cache. | |
4187 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
4188 | * returned. | |
4189 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
4190 | * false is returned. This root should now be freed by the caller. | |
4191 | */ | |
4192 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3, | |
4193 | union kvm_mmu_page_role new_role) | |
4194 | { | |
4195 | uint i; | |
4196 | struct kvm_mmu_root_info root; | |
44dd3ffa | 4197 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 4198 | |
ad7dc69a | 4199 | root.cr3 = mmu->root_cr3; |
b94742c9 JS |
4200 | root.hpa = mmu->root_hpa; |
4201 | ||
4202 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { | |
4203 | swap(root, mmu->prev_roots[i]); | |
4204 | ||
4205 | if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) && | |
4206 | page_header(root.hpa) != NULL && | |
4207 | new_role.word == page_header(root.hpa)->role.word) | |
4208 | break; | |
4209 | } | |
4210 | ||
4211 | mmu->root_hpa = root.hpa; | |
ad7dc69a | 4212 | mmu->root_cr3 = root.cr3; |
b94742c9 JS |
4213 | |
4214 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
4215 | } | |
4216 | ||
0aab33e4 | 4217 | static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
ade61e28 JS |
4218 | union kvm_mmu_page_role new_role, |
4219 | bool skip_tlb_flush) | |
6aa8b732 | 4220 | { |
44dd3ffa | 4221 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
4222 | |
4223 | /* | |
4224 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
4225 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
4226 | * later if necessary. | |
4227 | */ | |
4228 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
4229 | mmu->root_level >= PT64_ROOT_4LEVEL) { | |
7c390d35 JS |
4230 | if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT)) |
4231 | return false; | |
4232 | ||
b94742c9 | 4233 | if (cached_root_available(vcpu, new_cr3, new_role)) { |
0aab33e4 | 4234 | kvm_make_request(KVM_REQ_LOAD_CR3, vcpu); |
956bf353 JS |
4235 | if (!skip_tlb_flush) { |
4236 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); | |
ade61e28 | 4237 | kvm_x86_ops->tlb_flush(vcpu, true); |
956bf353 JS |
4238 | } |
4239 | ||
4240 | /* | |
4241 | * The last MMIO access's GVA and GPA are cached in the | |
4242 | * VCPU. When switching to a new CR3, that GVA->GPA | |
4243 | * mapping may no longer be valid. So clear any cached | |
4244 | * MMIO info even when we don't need to sync the shadow | |
4245 | * page tables. | |
4246 | */ | |
4247 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
ade61e28 | 4248 | |
7c390d35 JS |
4249 | __clear_sp_write_flooding_count( |
4250 | page_header(mmu->root_hpa)); | |
4251 | ||
7c390d35 JS |
4252 | return true; |
4253 | } | |
4254 | } | |
4255 | ||
4256 | return false; | |
6aa8b732 AK |
4257 | } |
4258 | ||
0aab33e4 | 4259 | static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
ade61e28 JS |
4260 | union kvm_mmu_page_role new_role, |
4261 | bool skip_tlb_flush) | |
6aa8b732 | 4262 | { |
ade61e28 | 4263 | if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush)) |
6a82cd1c VK |
4264 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, |
4265 | KVM_MMU_ROOT_CURRENT); | |
6aa8b732 AK |
4266 | } |
4267 | ||
ade61e28 | 4268 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush) |
0aab33e4 | 4269 | { |
ade61e28 JS |
4270 | __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu), |
4271 | skip_tlb_flush); | |
0aab33e4 | 4272 | } |
50c28f21 | 4273 | EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3); |
0aab33e4 | 4274 | |
5777ed34 JR |
4275 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
4276 | { | |
9f8fe504 | 4277 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
4278 | } |
4279 | ||
6389ee94 AK |
4280 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
4281 | struct x86_exception *fault) | |
6aa8b732 | 4282 | { |
44dd3ffa | 4283 | vcpu->arch.mmu->inject_page_fault(vcpu, fault); |
6aa8b732 AK |
4284 | } |
4285 | ||
54bf36aa | 4286 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 4287 | unsigned access, int *nr_present) |
ce88decf XG |
4288 | { |
4289 | if (unlikely(is_mmio_spte(*sptep))) { | |
4290 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4291 | mmu_spte_clear_no_track(sptep); | |
4292 | return true; | |
4293 | } | |
4294 | ||
4295 | (*nr_present)++; | |
54bf36aa | 4296 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4297 | return true; |
4298 | } | |
4299 | ||
4300 | return false; | |
4301 | } | |
4302 | ||
6bb69c9b PB |
4303 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
4304 | unsigned level, unsigned gpte) | |
6fd01b71 | 4305 | { |
6bb69c9b PB |
4306 | /* |
4307 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
4308 | * If it is clear, there are no large pages at this level, so clear | |
4309 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
4310 | */ | |
4311 | gpte &= level - mmu->last_nonleaf_level; | |
4312 | ||
829ee279 LP |
4313 | /* |
4314 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
4315 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
4316 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
4317 | */ | |
4318 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
4319 | ||
6bb69c9b | 4320 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
4321 | } |
4322 | ||
37406aaa NHE |
4323 | #define PTTYPE_EPT 18 /* arbitrary */ |
4324 | #define PTTYPE PTTYPE_EPT | |
4325 | #include "paging_tmpl.h" | |
4326 | #undef PTTYPE | |
4327 | ||
6aa8b732 AK |
4328 | #define PTTYPE 64 |
4329 | #include "paging_tmpl.h" | |
4330 | #undef PTTYPE | |
4331 | ||
4332 | #define PTTYPE 32 | |
4333 | #include "paging_tmpl.h" | |
4334 | #undef PTTYPE | |
4335 | ||
6dc98b86 XG |
4336 | static void |
4337 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4338 | struct rsvd_bits_validate *rsvd_check, | |
4339 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 4340 | bool pse, bool amd) |
82725b20 | 4341 | { |
82725b20 | 4342 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 4343 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4344 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 4345 | |
a0a64f50 | 4346 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4347 | |
6dc98b86 | 4348 | if (!nx) |
82725b20 | 4349 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 4350 | if (!gbpages) |
5f7dde7b | 4351 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
4352 | |
4353 | /* | |
4354 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4355 | * leaf entries) on AMD CPUs only. | |
4356 | */ | |
6fec2144 | 4357 | if (amd) |
a0c0feb5 PB |
4358 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4359 | ||
6dc98b86 | 4360 | switch (level) { |
82725b20 DE |
4361 | case PT32_ROOT_LEVEL: |
4362 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4363 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4364 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4365 | rsvd_check->rsvd_bits_mask[1][0] = | |
4366 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4367 | |
6dc98b86 | 4368 | if (!pse) { |
a0a64f50 | 4369 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4370 | break; |
4371 | } | |
4372 | ||
82725b20 DE |
4373 | if (is_cpuid_PSE36()) |
4374 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4375 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4376 | else |
4377 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4378 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4379 | break; |
4380 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 4381 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 4382 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 4383 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 4384 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 4385 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 4386 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 4387 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 4388 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
4389 | rsvd_bits(maxphyaddr, 62) | |
4390 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4391 | rsvd_check->rsvd_bits_mask[1][0] = |
4392 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4393 | break; |
855feb67 YZ |
4394 | case PT64_ROOT_5LEVEL: |
4395 | rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd | | |
4396 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4397 | rsvd_bits(maxphyaddr, 51); | |
4398 | rsvd_check->rsvd_bits_mask[1][4] = | |
4399 | rsvd_check->rsvd_bits_mask[0][4]; | |
b2869f28 | 4400 | /* fall through */ |
2a7266a8 | 4401 | case PT64_ROOT_4LEVEL: |
a0a64f50 XG |
4402 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
4403 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 4404 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4405 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
4406 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 4407 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4408 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4409 | rsvd_bits(maxphyaddr, 51); | |
4410 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4411 | rsvd_bits(maxphyaddr, 51); | |
4412 | rsvd_check->rsvd_bits_mask[1][3] = | |
4413 | rsvd_check->rsvd_bits_mask[0][3]; | |
4414 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4415 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4416 | rsvd_bits(13, 29); |
a0a64f50 | 4417 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4418 | rsvd_bits(maxphyaddr, 51) | |
4419 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4420 | rsvd_check->rsvd_bits_mask[1][0] = |
4421 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4422 | break; |
4423 | } | |
4424 | } | |
4425 | ||
6dc98b86 XG |
4426 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4427 | struct kvm_mmu *context) | |
4428 | { | |
4429 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4430 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4431 | context->nx, |
4432 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
6fec2144 | 4433 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
4434 | } |
4435 | ||
81b8eebb XG |
4436 | static void |
4437 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4438 | int maxphyaddr, bool execonly) | |
25d92081 | 4439 | { |
951f9fd7 | 4440 | u64 bad_mt_xwr; |
25d92081 | 4441 | |
855feb67 YZ |
4442 | rsvd_check->rsvd_bits_mask[0][4] = |
4443 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
a0a64f50 | 4444 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4445 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4446 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4447 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4448 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4449 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4450 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4451 | |
4452 | /* large page */ | |
855feb67 | 4453 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 XG |
4454 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4455 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4456 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4457 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4458 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4459 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4460 | |
951f9fd7 PB |
4461 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4462 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4463 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4464 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4465 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4466 | if (!execonly) { | |
4467 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4468 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4469 | } |
951f9fd7 | 4470 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4471 | } |
4472 | ||
81b8eebb XG |
4473 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4474 | struct kvm_mmu *context, bool execonly) | |
4475 | { | |
4476 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4477 | cpuid_maxphyaddr(vcpu), execonly); | |
4478 | } | |
4479 | ||
c258b62b XG |
4480 | /* |
4481 | * the page table on host is the shadow page table for the page | |
4482 | * table in guest or amd nested guest, its mmu features completely | |
4483 | * follow the features in guest. | |
4484 | */ | |
4485 | void | |
4486 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4487 | { | |
36d9594d VK |
4488 | bool uses_nx = context->nx || |
4489 | context->mmu_role.base.smep_andnot_wp; | |
ea2800dd BS |
4490 | struct rsvd_bits_validate *shadow_zero_check; |
4491 | int i; | |
5f0b8199 | 4492 | |
6fec2144 PB |
4493 | /* |
4494 | * Passing "true" to the last argument is okay; it adds a check | |
4495 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4496 | */ | |
ea2800dd BS |
4497 | shadow_zero_check = &context->shadow_zero_check; |
4498 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
f3ecb59d | 4499 | shadow_phys_bits, |
5f0b8199 | 4500 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4501 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4502 | is_pse(vcpu), true); | |
ea2800dd BS |
4503 | |
4504 | if (!shadow_me_mask) | |
4505 | return; | |
4506 | ||
4507 | for (i = context->shadow_root_level; --i >= 0;) { | |
4508 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4509 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4510 | } | |
4511 | ||
c258b62b XG |
4512 | } |
4513 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4514 | ||
6fec2144 PB |
4515 | static inline bool boot_cpu_is_amd(void) |
4516 | { | |
4517 | WARN_ON_ONCE(!tdp_enabled); | |
4518 | return shadow_x_mask == 0; | |
4519 | } | |
4520 | ||
c258b62b XG |
4521 | /* |
4522 | * the direct page table on host, use as much mmu features as | |
4523 | * possible, however, kvm currently does not do execution-protection. | |
4524 | */ | |
4525 | static void | |
4526 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4527 | struct kvm_mmu *context) | |
4528 | { | |
ea2800dd BS |
4529 | struct rsvd_bits_validate *shadow_zero_check; |
4530 | int i; | |
4531 | ||
4532 | shadow_zero_check = &context->shadow_zero_check; | |
4533 | ||
6fec2144 | 4534 | if (boot_cpu_is_amd()) |
ea2800dd | 4535 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
f3ecb59d | 4536 | shadow_phys_bits, |
c258b62b | 4537 | context->shadow_root_level, false, |
b8291adc BP |
4538 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4539 | true, true); | |
c258b62b | 4540 | else |
ea2800dd | 4541 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
f3ecb59d | 4542 | shadow_phys_bits, |
c258b62b XG |
4543 | false); |
4544 | ||
ea2800dd BS |
4545 | if (!shadow_me_mask) |
4546 | return; | |
4547 | ||
4548 | for (i = context->shadow_root_level; --i >= 0;) { | |
4549 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4550 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4551 | } | |
c258b62b XG |
4552 | } |
4553 | ||
4554 | /* | |
4555 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4556 | * is the shadow page table for intel nested guest. | |
4557 | */ | |
4558 | static void | |
4559 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4560 | struct kvm_mmu *context, bool execonly) | |
4561 | { | |
4562 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
f3ecb59d | 4563 | shadow_phys_bits, execonly); |
c258b62b XG |
4564 | } |
4565 | ||
09f037aa PB |
4566 | #define BYTE_MASK(access) \ |
4567 | ((1 & (access) ? 2 : 0) | \ | |
4568 | (2 & (access) ? 4 : 0) | \ | |
4569 | (3 & (access) ? 8 : 0) | \ | |
4570 | (4 & (access) ? 16 : 0) | \ | |
4571 | (5 & (access) ? 32 : 0) | \ | |
4572 | (6 & (access) ? 64 : 0) | \ | |
4573 | (7 & (access) ? 128 : 0)) | |
4574 | ||
4575 | ||
edc90b7d XG |
4576 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4577 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4578 | { |
09f037aa PB |
4579 | unsigned byte; |
4580 | ||
4581 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4582 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4583 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4584 | ||
4585 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4586 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4587 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4588 | |
97d64b78 | 4589 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4590 | unsigned pfec = byte << 1; |
4591 | ||
97ec8c06 | 4592 | /* |
09f037aa PB |
4593 | * Each "*f" variable has a 1 bit for each UWX value |
4594 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4595 | */ |
97d64b78 | 4596 | |
09f037aa PB |
4597 | /* Faults from writes to non-writable pages */ |
4598 | u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0; | |
4599 | /* Faults from user mode accesses to supervisor pages */ | |
4600 | u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0; | |
4601 | /* Faults from fetches of non-executable pages*/ | |
4602 | u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0; | |
4603 | /* Faults from kernel mode fetches of user pages */ | |
4604 | u8 smepf = 0; | |
4605 | /* Faults from kernel mode accesses of user pages */ | |
4606 | u8 smapf = 0; | |
4607 | ||
4608 | if (!ept) { | |
4609 | /* Faults from kernel mode accesses to user pages */ | |
4610 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4611 | ||
4612 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4613 | if (!mmu->nx) | |
4614 | ff = 0; | |
4615 | ||
4616 | /* Allow supervisor writes if !cr0.wp */ | |
4617 | if (!cr0_wp) | |
4618 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4619 | ||
4620 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4621 | if (cr4_smep) | |
4622 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4623 | ||
4624 | /* | |
4625 | * SMAP:kernel-mode data accesses from user-mode | |
4626 | * mappings should fault. A fault is considered | |
4627 | * as a SMAP violation if all of the following | |
39337ad1 | 4628 | * conditions are true: |
09f037aa PB |
4629 | * - X86_CR4_SMAP is set in CR4 |
4630 | * - A user page is accessed | |
4631 | * - The access is not a fetch | |
4632 | * - Page fault in kernel mode | |
4633 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4634 | * | |
4635 | * Here, we cover the first three conditions. | |
4636 | * The fourth is computed dynamically in permission_fault(); | |
4637 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4638 | * *not* subject to SMAP restrictions. | |
4639 | */ | |
4640 | if (cr4_smap) | |
4641 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4642 | } |
09f037aa PB |
4643 | |
4644 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4645 | } |
4646 | } | |
4647 | ||
2d344105 HH |
4648 | /* |
4649 | * PKU is an additional mechanism by which the paging controls access to | |
4650 | * user-mode addresses based on the value in the PKRU register. Protection | |
4651 | * key violations are reported through a bit in the page fault error code. | |
4652 | * Unlike other bits of the error code, the PK bit is not known at the | |
4653 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4654 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4655 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4656 | * | |
4657 | * In particular the following conditions come from the error code, the | |
4658 | * page tables and the machine state: | |
4659 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4660 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4661 | * - PK is always zero if U=0 in the page tables | |
4662 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4663 | * | |
4664 | * The PKRU bitmask caches the result of these four conditions. The error | |
4665 | * code (minus the P bit) and the page table's U bit form an index into the | |
4666 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4667 | * with the two bits of the PKRU register corresponding to the protection key. | |
4668 | * For the first three conditions above the bits will be 00, thus masking | |
4669 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4670 | * only will be masked away. | |
4671 | */ | |
4672 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4673 | bool ept) | |
4674 | { | |
4675 | unsigned bit; | |
4676 | bool wp; | |
4677 | ||
4678 | if (ept) { | |
4679 | mmu->pkru_mask = 0; | |
4680 | return; | |
4681 | } | |
4682 | ||
4683 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4684 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4685 | mmu->pkru_mask = 0; | |
4686 | return; | |
4687 | } | |
4688 | ||
4689 | wp = is_write_protection(vcpu); | |
4690 | ||
4691 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4692 | unsigned pfec, pkey_bits; | |
4693 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4694 | ||
4695 | pfec = bit << 1; | |
4696 | ff = pfec & PFERR_FETCH_MASK; | |
4697 | uf = pfec & PFERR_USER_MASK; | |
4698 | wf = pfec & PFERR_WRITE_MASK; | |
4699 | ||
4700 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4701 | pte_user = pfec & PFERR_RSVD_MASK; | |
4702 | ||
4703 | /* | |
4704 | * Only need to check the access which is not an | |
4705 | * instruction fetch and is to a user page. | |
4706 | */ | |
4707 | check_pkey = (!ff && pte_user); | |
4708 | /* | |
4709 | * write access is controlled by PKRU if it is a | |
4710 | * user access or CR0.WP = 1. | |
4711 | */ | |
4712 | check_write = check_pkey && wf && (uf || wp); | |
4713 | ||
4714 | /* PKRU.AD stops both read and write access. */ | |
4715 | pkey_bits = !!check_pkey; | |
4716 | /* PKRU.WD stops write access. */ | |
4717 | pkey_bits |= (!!check_write) << 1; | |
4718 | ||
4719 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4720 | } | |
4721 | } | |
4722 | ||
6bb69c9b | 4723 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4724 | { |
6bb69c9b PB |
4725 | unsigned root_level = mmu->root_level; |
4726 | ||
4727 | mmu->last_nonleaf_level = root_level; | |
4728 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4729 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4730 | } |
4731 | ||
8a3c1a33 PB |
4732 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4733 | struct kvm_mmu *context, | |
4734 | int level) | |
6aa8b732 | 4735 | { |
2d48a985 | 4736 | context->nx = is_nx(vcpu); |
4d6931c3 | 4737 | context->root_level = level; |
2d48a985 | 4738 | |
4d6931c3 | 4739 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4740 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4741 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4742 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4743 | |
fa4a2c08 | 4744 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4745 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4746 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4747 | context->sync_page = paging64_sync_page; |
a7052897 | 4748 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4749 | context->update_pte = paging64_update_pte; |
17ac10ad | 4750 | context->shadow_root_level = level; |
c5a78f2b | 4751 | context->direct_map = false; |
6aa8b732 AK |
4752 | } |
4753 | ||
8a3c1a33 PB |
4754 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4755 | struct kvm_mmu *context) | |
17ac10ad | 4756 | { |
855feb67 YZ |
4757 | int root_level = is_la57_mode(vcpu) ? |
4758 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4759 | ||
4760 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4761 | } |
4762 | ||
8a3c1a33 PB |
4763 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4764 | struct kvm_mmu *context) | |
6aa8b732 | 4765 | { |
2d48a985 | 4766 | context->nx = false; |
4d6931c3 | 4767 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4768 | |
4d6931c3 | 4769 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4770 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4771 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4772 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4773 | |
6aa8b732 | 4774 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4775 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4776 | context->sync_page = paging32_sync_page; |
a7052897 | 4777 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4778 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4779 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4780 | context->direct_map = false; |
6aa8b732 AK |
4781 | } |
4782 | ||
8a3c1a33 PB |
4783 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4784 | struct kvm_mmu *context) | |
6aa8b732 | 4785 | { |
8a3c1a33 | 4786 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4787 | } |
4788 | ||
a336282d VK |
4789 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu) |
4790 | { | |
4791 | union kvm_mmu_extended_role ext = {0}; | |
4792 | ||
7dcd5755 | 4793 | ext.cr0_pg = !!is_paging(vcpu); |
0699c64a | 4794 | ext.cr4_pae = !!is_pae(vcpu); |
a336282d VK |
4795 | ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
4796 | ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); | |
4797 | ext.cr4_pse = !!is_pse(vcpu); | |
4798 | ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE); | |
7dcd5755 | 4799 | ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57); |
de3ccd26 | 4800 | ext.maxphyaddr = cpuid_maxphyaddr(vcpu); |
a336282d VK |
4801 | |
4802 | ext.valid = 1; | |
4803 | ||
4804 | return ext; | |
4805 | } | |
4806 | ||
7dcd5755 VK |
4807 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
4808 | bool base_only) | |
4809 | { | |
4810 | union kvm_mmu_role role = {0}; | |
4811 | ||
4812 | role.base.access = ACC_ALL; | |
4813 | role.base.nxe = !!is_nx(vcpu); | |
7dcd5755 VK |
4814 | role.base.cr0_wp = is_write_protection(vcpu); |
4815 | role.base.smm = is_smm(vcpu); | |
4816 | role.base.guest_mode = is_guest_mode(vcpu); | |
4817 | ||
4818 | if (base_only) | |
4819 | return role; | |
4820 | ||
4821 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
4822 | ||
4823 | return role; | |
4824 | } | |
4825 | ||
4826 | static union kvm_mmu_role | |
4827 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
9fa72119 | 4828 | { |
7dcd5755 | 4829 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); |
9fa72119 | 4830 | |
7dcd5755 VK |
4831 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
4832 | role.base.level = kvm_x86_ops->get_tdp_level(vcpu); | |
4833 | role.base.direct = true; | |
47c42e6b | 4834 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4835 | |
4836 | return role; | |
4837 | } | |
4838 | ||
8a3c1a33 | 4839 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4840 | { |
44dd3ffa | 4841 | struct kvm_mmu *context = vcpu->arch.mmu; |
7dcd5755 VK |
4842 | union kvm_mmu_role new_role = |
4843 | kvm_calc_tdp_mmu_root_page_role(vcpu, false); | |
fb72d167 | 4844 | |
7dcd5755 VK |
4845 | new_role.base.word &= mmu_base_role_mask.word; |
4846 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4847 | return; | |
4848 | ||
4849 | context->mmu_role.as_u64 = new_role.as_u64; | |
fb72d167 | 4850 | context->page_fault = tdp_page_fault; |
e8bc217a | 4851 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4852 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4853 | context->update_pte = nonpaging_update_pte; |
855feb67 | 4854 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu); |
c5a78f2b | 4855 | context->direct_map = true; |
1c97f0a0 | 4856 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4857 | context->get_cr3 = get_cr3; |
e4e517b4 | 4858 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4859 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4860 | |
4861 | if (!is_paging(vcpu)) { | |
2d48a985 | 4862 | context->nx = false; |
fb72d167 JR |
4863 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4864 | context->root_level = 0; | |
4865 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4866 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4867 | context->root_level = is_la57_mode(vcpu) ? |
4868 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4869 | reset_rsvds_bits_mask(vcpu, context); |
4870 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4871 | } else if (is_pae(vcpu)) { |
2d48a985 | 4872 | context->nx = is_nx(vcpu); |
fb72d167 | 4873 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4874 | reset_rsvds_bits_mask(vcpu, context); |
4875 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4876 | } else { |
2d48a985 | 4877 | context->nx = false; |
fb72d167 | 4878 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4879 | reset_rsvds_bits_mask(vcpu, context); |
4880 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4881 | } |
4882 | ||
25d92081 | 4883 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4884 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4885 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4886 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4887 | } |
4888 | ||
7dcd5755 VK |
4889 | static union kvm_mmu_role |
4890 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
4891 | { | |
4892 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); | |
4893 | ||
4894 | role.base.smep_andnot_wp = role.ext.cr4_smep && | |
4895 | !is_write_protection(vcpu); | |
4896 | role.base.smap_andnot_wp = role.ext.cr4_smap && | |
4897 | !is_write_protection(vcpu); | |
4898 | role.base.direct = !is_paging(vcpu); | |
47c42e6b | 4899 | role.base.gpte_is_8_bytes = !!is_pae(vcpu); |
9fa72119 JS |
4900 | |
4901 | if (!is_long_mode(vcpu)) | |
7dcd5755 | 4902 | role.base.level = PT32E_ROOT_LEVEL; |
9fa72119 | 4903 | else if (is_la57_mode(vcpu)) |
7dcd5755 | 4904 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4905 | else |
7dcd5755 | 4906 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4907 | |
4908 | return role; | |
4909 | } | |
4910 | ||
4911 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) | |
4912 | { | |
44dd3ffa | 4913 | struct kvm_mmu *context = vcpu->arch.mmu; |
7dcd5755 VK |
4914 | union kvm_mmu_role new_role = |
4915 | kvm_calc_shadow_mmu_root_page_role(vcpu, false); | |
4916 | ||
4917 | new_role.base.word &= mmu_base_role_mask.word; | |
4918 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4919 | return; | |
6aa8b732 AK |
4920 | |
4921 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4922 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4923 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4924 | paging64_init_context(vcpu, context); |
6aa8b732 | 4925 | else if (is_pae(vcpu)) |
8a3c1a33 | 4926 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4927 | else |
8a3c1a33 | 4928 | paging32_init_context(vcpu, context); |
a770f6f2 | 4929 | |
7dcd5755 | 4930 | context->mmu_role.as_u64 = new_role.as_u64; |
c258b62b | 4931 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4932 | } |
4933 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4934 | ||
a336282d VK |
4935 | static union kvm_mmu_role |
4936 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
4937 | bool execonly) | |
9fa72119 | 4938 | { |
552c69b1 | 4939 | union kvm_mmu_role role = {0}; |
14c07ad8 | 4940 | |
47c42e6b SC |
4941 | /* SMM flag is inherited from root_mmu */ |
4942 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 4943 | |
a336282d | 4944 | role.base.level = PT64_ROOT_4LEVEL; |
47c42e6b | 4945 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
4946 | role.base.direct = false; |
4947 | role.base.ad_disabled = !accessed_dirty; | |
4948 | role.base.guest_mode = true; | |
4949 | role.base.access = ACC_ALL; | |
9fa72119 | 4950 | |
47c42e6b SC |
4951 | /* |
4952 | * WP=1 and NOT_WP=1 is an impossible combination, use WP and the | |
4953 | * SMAP variation to denote shadow EPT entries. | |
4954 | */ | |
4955 | role.base.cr0_wp = true; | |
4956 | role.base.smap_andnot_wp = true; | |
4957 | ||
552c69b1 | 4958 | role.ext = kvm_calc_mmu_role_ext(vcpu); |
a336282d | 4959 | role.ext.execonly = execonly; |
9fa72119 JS |
4960 | |
4961 | return role; | |
4962 | } | |
4963 | ||
ae1e2d10 | 4964 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4965 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4966 | { |
44dd3ffa | 4967 | struct kvm_mmu *context = vcpu->arch.mmu; |
a336282d VK |
4968 | union kvm_mmu_role new_role = |
4969 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
4970 | execonly); | |
4971 | ||
4972 | __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false); | |
4973 | ||
4974 | new_role.base.word &= mmu_base_role_mask.word; | |
4975 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4976 | return; | |
ad896af0 | 4977 | |
855feb67 | 4978 | context->shadow_root_level = PT64_ROOT_4LEVEL; |
155a97a3 NHE |
4979 | |
4980 | context->nx = true; | |
ae1e2d10 | 4981 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4982 | context->page_fault = ept_page_fault; |
4983 | context->gva_to_gpa = ept_gva_to_gpa; | |
4984 | context->sync_page = ept_sync_page; | |
4985 | context->invlpg = ept_invlpg; | |
4986 | context->update_pte = ept_update_pte; | |
855feb67 | 4987 | context->root_level = PT64_ROOT_4LEVEL; |
155a97a3 | 4988 | context->direct_map = false; |
a336282d | 4989 | context->mmu_role.as_u64 = new_role.as_u64; |
3dc773e7 | 4990 | |
155a97a3 | 4991 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 4992 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4993 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4994 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4995 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4996 | } |
4997 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4998 | ||
8a3c1a33 | 4999 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 5000 | { |
44dd3ffa | 5001 | struct kvm_mmu *context = vcpu->arch.mmu; |
ad896af0 PB |
5002 | |
5003 | kvm_init_shadow_mmu(vcpu); | |
5004 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
5005 | context->get_cr3 = get_cr3; | |
5006 | context->get_pdptr = kvm_pdptr_read; | |
5007 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
5008 | } |
5009 | ||
8a3c1a33 | 5010 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 5011 | { |
bf627a92 | 5012 | union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false); |
02f59dc9 JR |
5013 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
5014 | ||
bf627a92 VK |
5015 | new_role.base.word &= mmu_base_role_mask.word; |
5016 | if (new_role.as_u64 == g_context->mmu_role.as_u64) | |
5017 | return; | |
5018 | ||
5019 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
02f59dc9 | 5020 | g_context->get_cr3 = get_cr3; |
e4e517b4 | 5021 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
5022 | g_context->inject_page_fault = kvm_inject_page_fault; |
5023 | ||
5024 | /* | |
44dd3ffa | 5025 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
5026 | * L1's nested page tables (e.g. EPT12). The nested translation |
5027 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
5028 | * L2's page tables as the first level of translation and L1's | |
5029 | * nested page tables as the second level of translation. Basically | |
5030 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
5031 | */ |
5032 | if (!is_paging(vcpu)) { | |
2d48a985 | 5033 | g_context->nx = false; |
02f59dc9 JR |
5034 | g_context->root_level = 0; |
5035 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
5036 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 5037 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
5038 | g_context->root_level = is_la57_mode(vcpu) ? |
5039 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 5040 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5041 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
5042 | } else if (is_pae(vcpu)) { | |
2d48a985 | 5043 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 5044 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 5045 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5046 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
5047 | } else { | |
2d48a985 | 5048 | g_context->nx = false; |
02f59dc9 | 5049 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 5050 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5051 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
5052 | } | |
5053 | ||
25d92081 | 5054 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 5055 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 5056 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
5057 | } |
5058 | ||
1c53da3f | 5059 | void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots) |
fb72d167 | 5060 | { |
1c53da3f | 5061 | if (reset_roots) { |
b94742c9 JS |
5062 | uint i; |
5063 | ||
44dd3ffa | 5064 | vcpu->arch.mmu->root_hpa = INVALID_PAGE; |
b94742c9 JS |
5065 | |
5066 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
44dd3ffa | 5067 | vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
1c53da3f JS |
5068 | } |
5069 | ||
02f59dc9 | 5070 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 5071 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 5072 | else if (tdp_enabled) |
e0c6db3e | 5073 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 5074 | else |
e0c6db3e | 5075 | init_kvm_softmmu(vcpu); |
fb72d167 | 5076 | } |
1c53da3f | 5077 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 5078 | |
9fa72119 JS |
5079 | static union kvm_mmu_page_role |
5080 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
5081 | { | |
7dcd5755 VK |
5082 | union kvm_mmu_role role; |
5083 | ||
9fa72119 | 5084 | if (tdp_enabled) |
7dcd5755 | 5085 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, true); |
9fa72119 | 5086 | else |
7dcd5755 VK |
5087 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, true); |
5088 | ||
5089 | return role.base; | |
9fa72119 | 5090 | } |
fb72d167 | 5091 | |
8a3c1a33 | 5092 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 5093 | { |
95f93af4 | 5094 | kvm_mmu_unload(vcpu); |
1c53da3f | 5095 | kvm_init_mmu(vcpu, true); |
17c3ba9d | 5096 | } |
8668a3c4 | 5097 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
5098 | |
5099 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 5100 | { |
714b93da AK |
5101 | int r; |
5102 | ||
e2dec939 | 5103 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
5104 | if (r) |
5105 | goto out; | |
8986ecc0 | 5106 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 5107 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
5108 | if (r) |
5109 | goto out; | |
6e42782f | 5110 | kvm_mmu_load_cr3(vcpu); |
afe828d1 | 5111 | kvm_x86_ops->tlb_flush(vcpu, true); |
714b93da AK |
5112 | out: |
5113 | return r; | |
6aa8b732 | 5114 | } |
17c3ba9d AK |
5115 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
5116 | ||
5117 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
5118 | { | |
14c07ad8 VK |
5119 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
5120 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
5121 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
5122 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 5123 | } |
4b16184c | 5124 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 5125 | |
0028425f | 5126 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
5127 | struct kvm_mmu_page *sp, u64 *spte, |
5128 | const void *new) | |
0028425f | 5129 | { |
30945387 | 5130 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
5131 | ++vcpu->kvm->stat.mmu_pde_zapped; |
5132 | return; | |
30945387 | 5133 | } |
0028425f | 5134 | |
4cee5764 | 5135 | ++vcpu->kvm->stat.mmu_pte_updated; |
44dd3ffa | 5136 | vcpu->arch.mmu->update_pte(vcpu, sp, spte, new); |
0028425f AK |
5137 | } |
5138 | ||
79539cec AK |
5139 | static bool need_remote_flush(u64 old, u64 new) |
5140 | { | |
5141 | if (!is_shadow_present_pte(old)) | |
5142 | return false; | |
5143 | if (!is_shadow_present_pte(new)) | |
5144 | return true; | |
5145 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
5146 | return true; | |
53166229 GN |
5147 | old ^= shadow_nx_mask; |
5148 | new ^= shadow_nx_mask; | |
79539cec AK |
5149 | return (old & ~new & PT64_PERM_MASK) != 0; |
5150 | } | |
5151 | ||
889e5cbc | 5152 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 5153 | int *bytes) |
da4a00f0 | 5154 | { |
0e0fee5c | 5155 | u64 gentry = 0; |
889e5cbc | 5156 | int r; |
72016f3a | 5157 | |
72016f3a AK |
5158 | /* |
5159 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
5160 | * as the current vcpu paging mode since we update the sptes only |
5161 | * when they have the same mode. | |
72016f3a | 5162 | */ |
889e5cbc | 5163 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 5164 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
5165 | *gpa &= ~(gpa_t)7; |
5166 | *bytes = 8; | |
08e850c6 AK |
5167 | } |
5168 | ||
0e0fee5c JS |
5169 | if (*bytes == 4 || *bytes == 8) { |
5170 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
5171 | if (r) | |
5172 | gentry = 0; | |
72016f3a AK |
5173 | } |
5174 | ||
889e5cbc XG |
5175 | return gentry; |
5176 | } | |
5177 | ||
5178 | /* | |
5179 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
5180 | * or we may be forking, in which case it is better to unmap the page. | |
5181 | */ | |
a138fe75 | 5182 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 5183 | { |
a30f47cb XG |
5184 | /* |
5185 | * Skip write-flooding detected for the sp whose level is 1, because | |
5186 | * it can become unsync, then the guest page is not write-protected. | |
5187 | */ | |
f71fa31f | 5188 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 5189 | return false; |
3246af0e | 5190 | |
e5691a81 XG |
5191 | atomic_inc(&sp->write_flooding_count); |
5192 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
5193 | } |
5194 | ||
5195 | /* | |
5196 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
5197 | * indicate a page is not used as a page table. | |
5198 | */ | |
5199 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
5200 | int bytes) | |
5201 | { | |
5202 | unsigned offset, pte_size, misaligned; | |
5203 | ||
5204 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
5205 | gpa, bytes, sp->role.word); | |
5206 | ||
5207 | offset = offset_in_page(gpa); | |
47c42e6b | 5208 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
5209 | |
5210 | /* | |
5211 | * Sometimes, the OS only writes the last one bytes to update status | |
5212 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
5213 | */ | |
5214 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
5215 | return false; | |
5216 | ||
889e5cbc XG |
5217 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
5218 | misaligned |= bytes < 4; | |
5219 | ||
5220 | return misaligned; | |
5221 | } | |
5222 | ||
5223 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
5224 | { | |
5225 | unsigned page_offset, quadrant; | |
5226 | u64 *spte; | |
5227 | int level; | |
5228 | ||
5229 | page_offset = offset_in_page(gpa); | |
5230 | level = sp->role.level; | |
5231 | *nspte = 1; | |
47c42e6b | 5232 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
5233 | page_offset <<= 1; /* 32->64 */ |
5234 | /* | |
5235 | * A 32-bit pde maps 4MB while the shadow pdes map | |
5236 | * only 2MB. So we need to double the offset again | |
5237 | * and zap two pdes instead of one. | |
5238 | */ | |
5239 | if (level == PT32_ROOT_LEVEL) { | |
5240 | page_offset &= ~7; /* kill rounding error */ | |
5241 | page_offset <<= 1; | |
5242 | *nspte = 2; | |
5243 | } | |
5244 | quadrant = page_offset >> PAGE_SHIFT; | |
5245 | page_offset &= ~PAGE_MASK; | |
5246 | if (quadrant != sp->role.quadrant) | |
5247 | return NULL; | |
5248 | } | |
5249 | ||
5250 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
5251 | return spte; | |
5252 | } | |
5253 | ||
13d268ca | 5254 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5255 | const u8 *new, int bytes, |
5256 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5257 | { |
5258 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5259 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5260 | LIST_HEAD(invalid_list); |
5261 | u64 entry, gentry, *spte; | |
5262 | int npte; | |
b8c67b7a | 5263 | bool remote_flush, local_flush; |
889e5cbc XG |
5264 | |
5265 | /* | |
5266 | * If we don't have indirect shadow pages, it means no page is | |
5267 | * write-protected, so we can exit simply. | |
5268 | */ | |
6aa7de05 | 5269 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5270 | return; |
5271 | ||
b8c67b7a | 5272 | remote_flush = local_flush = false; |
889e5cbc XG |
5273 | |
5274 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5275 | ||
889e5cbc XG |
5276 | /* |
5277 | * No need to care whether allocation memory is successful | |
5278 | * or not since pte prefetch is skiped if it does not have | |
5279 | * enough objects in the cache. | |
5280 | */ | |
5281 | mmu_topup_memory_caches(vcpu); | |
5282 | ||
5283 | spin_lock(&vcpu->kvm->mmu_lock); | |
0e0fee5c JS |
5284 | |
5285 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5286 | ||
889e5cbc | 5287 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5288 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5289 | |
b67bfe0d | 5290 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5291 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5292 | detect_write_flooding(sp)) { |
b8c67b7a | 5293 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5294 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5295 | continue; |
5296 | } | |
889e5cbc XG |
5297 | |
5298 | spte = get_written_sptes(sp, gpa, &npte); | |
5299 | if (!spte) | |
5300 | continue; | |
5301 | ||
0671a8e7 | 5302 | local_flush = true; |
ac1b714e | 5303 | while (npte--) { |
36d9594d VK |
5304 | u32 base_role = vcpu->arch.mmu->mmu_role.base.word; |
5305 | ||
79539cec | 5306 | entry = *spte; |
38e3b2b2 | 5307 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf | 5308 | if (gentry && |
36d9594d | 5309 | !((sp->role.word ^ base_role) |
9fa72119 | 5310 | & mmu_base_role_mask.word) && rmap_can_add(vcpu)) |
7c562522 | 5311 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 5312 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5313 | remote_flush = true; |
ac1b714e | 5314 | ++spte; |
9b7a0325 | 5315 | } |
9b7a0325 | 5316 | } |
b8c67b7a | 5317 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5318 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 5319 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5320 | } |
5321 | ||
a436036b AK |
5322 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
5323 | { | |
10589a46 MT |
5324 | gpa_t gpa; |
5325 | int r; | |
a436036b | 5326 | |
44dd3ffa | 5327 | if (vcpu->arch.mmu->direct_map) |
60f24784 AK |
5328 | return 0; |
5329 | ||
1871c602 | 5330 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 5331 | |
10589a46 | 5332 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 5333 | |
10589a46 | 5334 | return r; |
a436036b | 5335 | } |
577bdc49 | 5336 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 5337 | |
26eeb53c | 5338 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 5339 | { |
d98ba053 | 5340 | LIST_HEAD(invalid_list); |
103ad25a | 5341 | |
81f4f76b | 5342 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
26eeb53c | 5343 | return 0; |
81f4f76b | 5344 | |
5da59607 TY |
5345 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
5346 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
5347 | break; | |
ebeace86 | 5348 | |
4cee5764 | 5349 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 5350 | } |
aa6bd187 | 5351 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
26eeb53c WL |
5352 | |
5353 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
5354 | return -ENOSPC; | |
5355 | return 0; | |
ebeace86 | 5356 | } |
ebeace86 | 5357 | |
14727754 | 5358 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code, |
dc25e89e | 5359 | void *insn, int insn_len) |
3067714c | 5360 | { |
472faffa | 5361 | int r, emulation_type = 0; |
3067714c | 5362 | enum emulation_result er; |
44dd3ffa | 5363 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5364 | |
618232e2 | 5365 | /* With shadow page tables, fault_address contains a GVA or nGPA. */ |
44dd3ffa | 5366 | if (vcpu->arch.mmu->direct_map) { |
618232e2 BS |
5367 | vcpu->arch.gpa_available = true; |
5368 | vcpu->arch.gpa_val = cr2; | |
5369 | } | |
3067714c | 5370 | |
9b8ebbdb | 5371 | r = RET_PF_INVALID; |
e9ee956e TY |
5372 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
5373 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
472faffa | 5374 | if (r == RET_PF_EMULATE) |
e9ee956e | 5375 | goto emulate; |
e9ee956e | 5376 | } |
3067714c | 5377 | |
9b8ebbdb | 5378 | if (r == RET_PF_INVALID) { |
44dd3ffa VK |
5379 | r = vcpu->arch.mmu->page_fault(vcpu, cr2, |
5380 | lower_32_bits(error_code), | |
5381 | false); | |
9b8ebbdb PB |
5382 | WARN_ON(r == RET_PF_INVALID); |
5383 | } | |
5384 | ||
5385 | if (r == RET_PF_RETRY) | |
5386 | return 1; | |
3067714c | 5387 | if (r < 0) |
e9ee956e | 5388 | return r; |
3067714c | 5389 | |
14727754 TL |
5390 | /* |
5391 | * Before emulating the instruction, check if the error code | |
5392 | * was due to a RO violation while translating the guest page. | |
5393 | * This can occur when using nested virtualization with nested | |
5394 | * paging in both guests. If true, we simply unprotect the page | |
5395 | * and resume the guest. | |
14727754 | 5396 | */ |
44dd3ffa | 5397 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5398 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
14727754 TL |
5399 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2)); |
5400 | return 1; | |
5401 | } | |
5402 | ||
472faffa SC |
5403 | /* |
5404 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5405 | * optimistically try to just unprotect the page and let the processor | |
5406 | * re-execute the instruction that caused the page fault. Do not allow | |
5407 | * retrying MMIO emulation, as it's not only pointless but could also | |
5408 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5409 | * faulting on the non-existent MMIO address. Retrying an instruction |
5410 | * from a nested guest is also pointless and dangerous as we are only | |
5411 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5412 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5413 | */ |
6c3dfeb6 | 5414 | if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu)) |
472faffa | 5415 | emulation_type = EMULTYPE_ALLOW_RETRY; |
e9ee956e | 5416 | emulate: |
00b10fe1 BS |
5417 | /* |
5418 | * On AMD platforms, under certain conditions insn_len may be zero on #NPF. | |
5419 | * This can happen if a guest gets a page-fault on data access but the HW | |
5420 | * table walker is not able to read the instruction page (e.g instruction | |
5421 | * page is not present in memory). In those cases we simply restart the | |
05d5a486 | 5422 | * guest, with the exception of AMD Erratum 1096 which is unrecoverable. |
00b10fe1 | 5423 | */ |
05d5a486 SB |
5424 | if (unlikely(insn && !insn_len)) { |
5425 | if (!kvm_x86_ops->need_emulation_on_page_fault(vcpu)) | |
5426 | return 1; | |
5427 | } | |
00b10fe1 | 5428 | |
1cb3f3ae | 5429 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
5430 | |
5431 | switch (er) { | |
5432 | case EMULATE_DONE: | |
5433 | return 1; | |
ac0a48c3 | 5434 | case EMULATE_USER_EXIT: |
3067714c | 5435 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 5436 | /* fall through */ |
3067714c | 5437 | case EMULATE_FAIL: |
3f5d18a9 | 5438 | return 0; |
3067714c AK |
5439 | default: |
5440 | BUG(); | |
5441 | } | |
3067714c AK |
5442 | } |
5443 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5444 | ||
a7052897 MT |
5445 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5446 | { | |
44dd3ffa | 5447 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 5448 | int i; |
7eb77e9f | 5449 | |
faff8758 JS |
5450 | /* INVLPG on a * non-canonical address is a NOP according to the SDM. */ |
5451 | if (is_noncanonical_address(gva, vcpu)) | |
5452 | return; | |
5453 | ||
7eb77e9f | 5454 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
956bf353 JS |
5455 | |
5456 | /* | |
5457 | * INVLPG is required to invalidate any global mappings for the VA, | |
5458 | * irrespective of PCID. Since it would take us roughly similar amount | |
b94742c9 JS |
5459 | * of work to determine whether any of the prev_root mappings of the VA |
5460 | * is marked global, or to just sync it blindly, so we might as well | |
5461 | * just always sync it. | |
956bf353 | 5462 | * |
b94742c9 JS |
5463 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5464 | * synced when switching to that cr3, so nothing needs to be done here | |
5465 | * for them. | |
956bf353 | 5466 | */ |
b94742c9 JS |
5467 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
5468 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5469 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
956bf353 | 5470 | |
faff8758 | 5471 | kvm_x86_ops->tlb_flush_gva(vcpu, gva); |
a7052897 MT |
5472 | ++vcpu->stat.invlpg; |
5473 | } | |
5474 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5475 | ||
eb4b248e JS |
5476 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5477 | { | |
44dd3ffa | 5478 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5479 | bool tlb_flush = false; |
b94742c9 | 5480 | uint i; |
eb4b248e JS |
5481 | |
5482 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5483 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5484 | tlb_flush = true; |
eb4b248e JS |
5485 | } |
5486 | ||
b94742c9 JS |
5487 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5488 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
5489 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) { | |
5490 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5491 | tlb_flush = true; | |
5492 | } | |
956bf353 | 5493 | } |
ade61e28 | 5494 | |
faff8758 JS |
5495 | if (tlb_flush) |
5496 | kvm_x86_ops->tlb_flush_gva(vcpu, gva); | |
5497 | ||
eb4b248e JS |
5498 | ++vcpu->stat.invlpg; |
5499 | ||
5500 | /* | |
b94742c9 JS |
5501 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5502 | * synced when switching to that cr3, so nothing needs to be done here | |
5503 | * for them. | |
eb4b248e JS |
5504 | */ |
5505 | } | |
5506 | EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva); | |
5507 | ||
18552672 JR |
5508 | void kvm_enable_tdp(void) |
5509 | { | |
5510 | tdp_enabled = true; | |
5511 | } | |
5512 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
5513 | ||
5f4cb662 JR |
5514 | void kvm_disable_tdp(void) |
5515 | { | |
5516 | tdp_enabled = false; | |
5517 | } | |
5518 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
5519 | ||
85875a13 SC |
5520 | |
5521 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
5522 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); | |
5523 | ||
5524 | /* The caller should hold mmu-lock before calling this function. */ | |
5525 | static __always_inline bool | |
5526 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5527 | slot_level_handler fn, int start_level, int end_level, | |
5528 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5529 | { | |
5530 | struct slot_rmap_walk_iterator iterator; | |
5531 | bool flush = false; | |
5532 | ||
5533 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5534 | end_gfn, &iterator) { | |
5535 | if (iterator.rmap) | |
5536 | flush |= fn(kvm, iterator.rmap); | |
5537 | ||
5538 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5539 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5540 | kvm_flush_remote_tlbs_with_address(kvm, |
5541 | start_gfn, | |
5542 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5543 | flush = false; |
5544 | } | |
5545 | cond_resched_lock(&kvm->mmu_lock); | |
5546 | } | |
5547 | } | |
5548 | ||
5549 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5550 | kvm_flush_remote_tlbs_with_address(kvm, start_gfn, |
5551 | end_gfn - start_gfn + 1); | |
85875a13 SC |
5552 | flush = false; |
5553 | } | |
5554 | ||
5555 | return flush; | |
5556 | } | |
5557 | ||
5558 | static __always_inline bool | |
5559 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5560 | slot_level_handler fn, int start_level, int end_level, | |
5561 | bool lock_flush_tlb) | |
5562 | { | |
5563 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5564 | end_level, memslot->base_gfn, | |
5565 | memslot->base_gfn + memslot->npages - 1, | |
5566 | lock_flush_tlb); | |
5567 | } | |
5568 | ||
5569 | static __always_inline bool | |
5570 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5571 | slot_level_handler fn, bool lock_flush_tlb) | |
5572 | { | |
5573 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5574 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5575 | } | |
5576 | ||
5577 | static __always_inline bool | |
5578 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5579 | slot_level_handler fn, bool lock_flush_tlb) | |
5580 | { | |
5581 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
5582 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5583 | } | |
5584 | ||
5585 | static __always_inline bool | |
5586 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5587 | slot_level_handler fn, bool lock_flush_tlb) | |
5588 | { | |
5589 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5590 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
5591 | } | |
5592 | ||
6aa8b732 AK |
5593 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
5594 | { | |
44dd3ffa VK |
5595 | free_page((unsigned long)vcpu->arch.mmu->pae_root); |
5596 | free_page((unsigned long)vcpu->arch.mmu->lm_root); | |
6aa8b732 AK |
5597 | } |
5598 | ||
5599 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
5600 | { | |
17ac10ad | 5601 | struct page *page; |
6aa8b732 AK |
5602 | int i; |
5603 | ||
ee6268ba LC |
5604 | if (tdp_enabled) |
5605 | return 0; | |
5606 | ||
17ac10ad AK |
5607 | /* |
5608 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
5609 | * Therefore we need to allocate shadow page tables in the first | |
5610 | * 4GB of memory, which happens to fit the DMA32 zone. | |
5611 | */ | |
254272ce | 5612 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5613 | if (!page) |
d7fa6ab2 WY |
5614 | return -ENOMEM; |
5615 | ||
44dd3ffa | 5616 | vcpu->arch.mmu->pae_root = page_address(page); |
17ac10ad | 5617 | for (i = 0; i < 4; ++i) |
44dd3ffa | 5618 | vcpu->arch.mmu->pae_root[i] = INVALID_PAGE; |
17ac10ad | 5619 | |
6aa8b732 | 5620 | return 0; |
6aa8b732 AK |
5621 | } |
5622 | ||
8018c27b | 5623 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5624 | { |
b94742c9 JS |
5625 | uint i; |
5626 | ||
44dd3ffa VK |
5627 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5628 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5629 | |
44dd3ffa | 5630 | vcpu->arch.root_mmu.root_hpa = INVALID_PAGE; |
ad7dc69a | 5631 | vcpu->arch.root_mmu.root_cr3 = 0; |
44dd3ffa | 5632 | vcpu->arch.root_mmu.translate_gpa = translate_gpa; |
b94742c9 | 5633 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
44dd3ffa | 5634 | vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
6aa8b732 | 5635 | |
14c07ad8 | 5636 | vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE; |
ad7dc69a | 5637 | vcpu->arch.guest_mmu.root_cr3 = 0; |
14c07ad8 VK |
5638 | vcpu->arch.guest_mmu.translate_gpa = translate_gpa; |
5639 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5640 | vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
2c264957 | 5641 | |
14c07ad8 | 5642 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
8018c27b | 5643 | return alloc_mmu_pages(vcpu); |
6aa8b732 AK |
5644 | } |
5645 | ||
b5f5fdca | 5646 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5647 | struct kvm_memory_slot *slot, |
5648 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5649 | { |
4e103134 SC |
5650 | struct kvm_mmu_page *sp; |
5651 | LIST_HEAD(invalid_list); | |
5652 | unsigned long i; | |
5653 | bool flush; | |
5654 | gfn_t gfn; | |
13d268ca | 5655 | |
4e103134 | 5656 | spin_lock(&kvm->mmu_lock); |
13d268ca | 5657 | |
4e103134 SC |
5658 | if (list_empty(&kvm->arch.active_mmu_pages)) |
5659 | goto out_unlock; | |
13d268ca | 5660 | |
4e103134 | 5661 | flush = slot_handle_all_level(kvm, slot, kvm_zap_rmapp, false); |
1bad2b2a | 5662 | |
4e103134 SC |
5663 | for (i = 0; i < slot->npages; i++) { |
5664 | gfn = slot->base_gfn + i; | |
1bad2b2a | 5665 | |
4e103134 SC |
5666 | for_each_valid_sp(kvm, sp, gfn) { |
5667 | if (sp->gfn != gfn) | |
5668 | continue; | |
1bad2b2a | 5669 | |
4e103134 SC |
5670 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
5671 | } | |
1bad2b2a | 5672 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { |
4e103134 SC |
5673 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
5674 | flush = false; | |
1bad2b2a XG |
5675 | cond_resched_lock(&kvm->mmu_lock); |
5676 | } | |
5677 | } | |
4e103134 | 5678 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
1bad2b2a | 5679 | |
4e103134 SC |
5680 | out_unlock: |
5681 | spin_unlock(&kvm->mmu_lock); | |
1bad2b2a XG |
5682 | } |
5683 | ||
13d268ca | 5684 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5685 | { |
13d268ca | 5686 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5687 | |
13d268ca | 5688 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5689 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5690 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5691 | } |
5692 | ||
13d268ca | 5693 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5694 | { |
13d268ca | 5695 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5696 | |
13d268ca | 5697 | kvm_page_track_unregister_notifier(kvm, node); |
1bad2b2a XG |
5698 | } |
5699 | ||
efdfe536 XG |
5700 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5701 | { | |
5702 | struct kvm_memslots *slots; | |
5703 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5704 | int i; |
efdfe536 XG |
5705 | |
5706 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
5707 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5708 | slots = __kvm_memslots(kvm, i); | |
5709 | kvm_for_each_memslot(memslot, slots) { | |
5710 | gfn_t start, end; | |
5711 | ||
5712 | start = max(gfn_start, memslot->base_gfn); | |
5713 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5714 | if (start >= end) | |
5715 | continue; | |
efdfe536 | 5716 | |
92da008f BG |
5717 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
5718 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
5719 | start, end - 1, true); | |
9da0e4d5 | 5720 | } |
efdfe536 XG |
5721 | } |
5722 | ||
5723 | spin_unlock(&kvm->mmu_lock); | |
5724 | } | |
5725 | ||
018aabb5 TY |
5726 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5727 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5728 | { |
018aabb5 | 5729 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5730 | } |
5731 | ||
1c91cad4 KH |
5732 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
5733 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 5734 | { |
d77aa73c | 5735 | bool flush; |
6aa8b732 | 5736 | |
9d1beefb | 5737 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
5738 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
5739 | false); | |
9d1beefb | 5740 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
5741 | |
5742 | /* | |
5743 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
5744 | * which do tlb flush out of mmu-lock should be serialized by | |
5745 | * kvm->slots_lock otherwise tlb flush would be missed. | |
5746 | */ | |
5747 | lockdep_assert_held(&kvm->slots_lock); | |
5748 | ||
5749 | /* | |
5750 | * We can flush all the TLBs out of the mmu lock without TLB | |
5751 | * corruption since we just change the spte from writable to | |
5752 | * readonly so that we only need to care the case of changing | |
5753 | * spte from present to present (changing the spte from present | |
5754 | * to nonpresent will flush all the TLBs immediately), in other | |
5755 | * words, the only case we care is mmu_spte_update() where we | |
bdd303cb | 5756 | * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE |
198c74f4 XG |
5757 | * instead of PT_WRITABLE_MASK, that means it does not depend |
5758 | * on PT_WRITABLE_MASK anymore. | |
5759 | */ | |
d91ffee9 | 5760 | if (flush) |
c3134ce2 LT |
5761 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5762 | memslot->npages); | |
6aa8b732 | 5763 | } |
37a7d8b0 | 5764 | |
3ea3b7fa | 5765 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5766 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5767 | { |
5768 | u64 *sptep; | |
5769 | struct rmap_iterator iter; | |
5770 | int need_tlb_flush = 0; | |
ba049e93 | 5771 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5772 | struct kvm_mmu_page *sp; |
5773 | ||
0d536790 | 5774 | restart: |
018aabb5 | 5775 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
5776 | sp = page_header(__pa(sptep)); |
5777 | pfn = spte_to_pfn(*sptep); | |
5778 | ||
5779 | /* | |
decf6333 XG |
5780 | * We cannot do huge page mapping for indirect shadow pages, |
5781 | * which are found on the last rmap (level = 1) when not using | |
5782 | * tdp; such shadow pages are synced with the page table in | |
5783 | * the guest, and the guest page table is using 4K page size | |
5784 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
5785 | */ |
5786 | if (sp->role.direct && | |
5787 | !kvm_is_reserved_pfn(pfn) && | |
127393fb | 5788 | PageTransCompoundMap(pfn_to_page(pfn))) { |
e7912386 | 5789 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5790 | |
5791 | if (kvm_available_flush_tlb_with_range()) | |
5792 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5793 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5794 | else | |
5795 | need_tlb_flush = 1; | |
5796 | ||
0d536790 XG |
5797 | goto restart; |
5798 | } | |
3ea3b7fa WL |
5799 | } |
5800 | ||
5801 | return need_tlb_flush; | |
5802 | } | |
5803 | ||
5804 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5805 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5806 | { |
f36f3f28 | 5807 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5808 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5809 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5810 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5811 | spin_unlock(&kvm->mmu_lock); |
5812 | } | |
5813 | ||
f4b4b180 KH |
5814 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5815 | struct kvm_memory_slot *memslot) | |
5816 | { | |
d77aa73c | 5817 | bool flush; |
f4b4b180 KH |
5818 | |
5819 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5820 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5821 | spin_unlock(&kvm->mmu_lock); |
5822 | ||
5823 | lockdep_assert_held(&kvm->slots_lock); | |
5824 | ||
5825 | /* | |
5826 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5827 | * function is only used for dirty logging, in which case flushing TLB | |
5828 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5829 | * dirty_bitmap. | |
5830 | */ | |
5831 | if (flush) | |
c3134ce2 LT |
5832 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5833 | memslot->npages); | |
f4b4b180 KH |
5834 | } |
5835 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5836 | ||
5837 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5838 | struct kvm_memory_slot *memslot) | |
5839 | { | |
d77aa73c | 5840 | bool flush; |
f4b4b180 KH |
5841 | |
5842 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5843 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5844 | false); | |
f4b4b180 KH |
5845 | spin_unlock(&kvm->mmu_lock); |
5846 | ||
5847 | /* see kvm_mmu_slot_remove_write_access */ | |
5848 | lockdep_assert_held(&kvm->slots_lock); | |
5849 | ||
5850 | if (flush) | |
c3134ce2 LT |
5851 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5852 | memslot->npages); | |
f4b4b180 KH |
5853 | } |
5854 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5855 | ||
5856 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5857 | struct kvm_memory_slot *memslot) | |
5858 | { | |
d77aa73c | 5859 | bool flush; |
f4b4b180 KH |
5860 | |
5861 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5862 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5863 | spin_unlock(&kvm->mmu_lock); |
5864 | ||
5865 | lockdep_assert_held(&kvm->slots_lock); | |
5866 | ||
5867 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
5868 | if (flush) | |
c3134ce2 LT |
5869 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5870 | memslot->npages); | |
f4b4b180 KH |
5871 | } |
5872 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5873 | ||
8ab3c471 | 5874 | static void __kvm_mmu_zap_all(struct kvm *kvm, bool mmio_only) |
5304b8d3 XG |
5875 | { |
5876 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 5877 | LIST_HEAD(invalid_list); |
83cdb568 | 5878 | int ign; |
5304b8d3 | 5879 | |
7390de1e | 5880 | spin_lock(&kvm->mmu_lock); |
5304b8d3 | 5881 | restart: |
8a674adc | 5882 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
8ab3c471 | 5883 | if (mmio_only && !sp->mmio_cached) |
5304b8d3 | 5884 | continue; |
8ab3c471 | 5885 | if (sp->role.invalid && sp->root_count) |
4771450c | 5886 | continue; |
24efe61f | 5887 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) { |
8ab3c471 | 5888 | WARN_ON_ONCE(mmio_only); |
5304b8d3 XG |
5889 | goto restart; |
5890 | } | |
24efe61f | 5891 | if (cond_resched_lock(&kvm->mmu_lock)) |
5304b8d3 XG |
5892 | goto restart; |
5893 | } | |
5894 | ||
4771450c | 5895 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
5304b8d3 XG |
5896 | spin_unlock(&kvm->mmu_lock); |
5897 | } | |
5898 | ||
8ab3c471 | 5899 | void kvm_mmu_zap_all(struct kvm *kvm) |
365c8868 | 5900 | { |
8ab3c471 | 5901 | return __kvm_mmu_zap_all(kvm, false); |
365c8868 XG |
5902 | } |
5903 | ||
15248258 | 5904 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5905 | { |
164bf7e5 | 5906 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5907 | |
164bf7e5 | 5908 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 5909 | |
f8f55942 | 5910 | /* |
e1359e2b SC |
5911 | * Generation numbers are incremented in multiples of the number of |
5912 | * address spaces in order to provide unique generations across all | |
5913 | * address spaces. Strip what is effectively the address space | |
5914 | * modifier prior to checking for a wrap of the MMIO generation so | |
5915 | * that a wrap in any address space is detected. | |
5916 | */ | |
5917 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5918 | ||
f8f55942 | 5919 | /* |
e1359e2b | 5920 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5921 | * zap all shadow pages. |
f8f55942 | 5922 | */ |
e1359e2b | 5923 | if (unlikely(gen == 0)) { |
ae0f5499 | 5924 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
8ab3c471 | 5925 | __kvm_mmu_zap_all(kvm, true); |
7a2e8aaf | 5926 | } |
f8f55942 XG |
5927 | } |
5928 | ||
70534a73 DC |
5929 | static unsigned long |
5930 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5931 | { |
5932 | struct kvm *kvm; | |
1495f230 | 5933 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5934 | unsigned long freed = 0; |
3ee16c81 | 5935 | |
0d9ce162 | 5936 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
5937 | |
5938 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5939 | int idx; |
d98ba053 | 5940 | LIST_HEAD(invalid_list); |
3ee16c81 | 5941 | |
35f2d16b TY |
5942 | /* |
5943 | * Never scan more than sc->nr_to_scan VM instances. | |
5944 | * Will not hit this condition practically since we do not try | |
5945 | * to shrink more than one VM and it is very unlikely to see | |
5946 | * !n_used_mmu_pages so many times. | |
5947 | */ | |
5948 | if (!nr_to_scan--) | |
5949 | break; | |
19526396 GN |
5950 | /* |
5951 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5952 | * here. We may skip a VM instance errorneosly, but we do not | |
5953 | * want to shrink a VM that only started to populate its MMU | |
5954 | * anyway. | |
5955 | */ | |
52d5dedc | 5956 | if (!kvm->arch.n_used_mmu_pages) |
19526396 | 5957 | continue; |
19526396 | 5958 | |
f656ce01 | 5959 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5960 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5961 | |
70534a73 DC |
5962 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5963 | freed++; | |
d98ba053 | 5964 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5965 | |
3ee16c81 | 5966 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5967 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5968 | |
70534a73 DC |
5969 | /* |
5970 | * unfair on small ones | |
5971 | * per-vm shrinkers cry out | |
5972 | * sadness comes quickly | |
5973 | */ | |
19526396 GN |
5974 | list_move_tail(&kvm->vm_list, &vm_list); |
5975 | break; | |
3ee16c81 | 5976 | } |
3ee16c81 | 5977 | |
0d9ce162 | 5978 | mutex_unlock(&kvm_lock); |
70534a73 | 5979 | return freed; |
70534a73 DC |
5980 | } |
5981 | ||
5982 | static unsigned long | |
5983 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5984 | { | |
45221ab6 | 5985 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5986 | } |
5987 | ||
5988 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5989 | .count_objects = mmu_shrink_count, |
5990 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5991 | .seeks = DEFAULT_SEEKS * 10, |
5992 | }; | |
5993 | ||
2ddfd20e | 5994 | static void mmu_destroy_caches(void) |
b5a33a75 | 5995 | { |
c1bd743e TH |
5996 | kmem_cache_destroy(pte_list_desc_cache); |
5997 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5998 | } |
5999 | ||
7b6f8a06 KH |
6000 | static void kvm_set_mmio_spte_mask(void) |
6001 | { | |
6002 | u64 mask; | |
7b6f8a06 KH |
6003 | |
6004 | /* | |
6005 | * Set the reserved bits and the present bit of an paging-structure | |
6006 | * entry to generate page fault with PFER.RSV = 1. | |
6007 | */ | |
6008 | ||
6009 | /* | |
6010 | * Mask the uppermost physical address bit, which would be reserved as | |
6011 | * long as the supported physical address width is less than 52. | |
6012 | */ | |
6013 | mask = 1ull << 51; | |
6014 | ||
6015 | /* Set the present bit. */ | |
6016 | mask |= 1ull; | |
6017 | ||
6018 | /* | |
6019 | * If reserved bit is not supported, clear the present bit to disable | |
6020 | * mmio page fault. | |
6021 | */ | |
f3ecb59d | 6022 | if (IS_ENABLED(CONFIG_X86_64) && shadow_phys_bits == 52) |
7b6f8a06 KH |
6023 | mask &= ~1ull; |
6024 | ||
6025 | kvm_mmu_set_mmio_spte_mask(mask, mask); | |
6026 | } | |
6027 | ||
b5a33a75 AK |
6028 | int kvm_mmu_module_init(void) |
6029 | { | |
ab271bd4 AB |
6030 | int ret = -ENOMEM; |
6031 | ||
36d9594d VK |
6032 | /* |
6033 | * MMU roles use union aliasing which is, generally speaking, an | |
6034 | * undefined behavior. However, we supposedly know how compilers behave | |
6035 | * and the current status quo is unlikely to change. Guardians below are | |
6036 | * supposed to let us know if the assumption becomes false. | |
6037 | */ | |
6038 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
6039 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
6040 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
6041 | ||
28a1f3ac | 6042 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 6043 | |
7b6f8a06 KH |
6044 | kvm_set_mmio_spte_mask(); |
6045 | ||
53c07b18 XG |
6046 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
6047 | sizeof(struct pte_list_desc), | |
46bea48a | 6048 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 6049 | if (!pte_list_desc_cache) |
ab271bd4 | 6050 | goto out; |
b5a33a75 | 6051 | |
d3d25b04 AK |
6052 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
6053 | sizeof(struct kvm_mmu_page), | |
46bea48a | 6054 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 6055 | if (!mmu_page_header_cache) |
ab271bd4 | 6056 | goto out; |
d3d25b04 | 6057 | |
908c7f19 | 6058 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 6059 | goto out; |
45bf21a8 | 6060 | |
ab271bd4 AB |
6061 | ret = register_shrinker(&mmu_shrinker); |
6062 | if (ret) | |
6063 | goto out; | |
3ee16c81 | 6064 | |
b5a33a75 AK |
6065 | return 0; |
6066 | ||
ab271bd4 | 6067 | out: |
3ee16c81 | 6068 | mmu_destroy_caches(); |
ab271bd4 | 6069 | return ret; |
b5a33a75 AK |
6070 | } |
6071 | ||
3ad82a7e | 6072 | /* |
39337ad1 | 6073 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 6074 | */ |
bc8a3d89 | 6075 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 6076 | { |
bc8a3d89 BG |
6077 | unsigned long nr_mmu_pages; |
6078 | unsigned long nr_pages = 0; | |
bc6678a3 | 6079 | struct kvm_memslots *slots; |
be6ba0f0 | 6080 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 6081 | int i; |
3ad82a7e | 6082 | |
9da0e4d5 PB |
6083 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
6084 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 6085 | |
9da0e4d5 PB |
6086 | kvm_for_each_memslot(memslot, slots) |
6087 | nr_pages += memslot->npages; | |
6088 | } | |
3ad82a7e ZX |
6089 | |
6090 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 6091 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
6092 | |
6093 | return nr_mmu_pages; | |
6094 | } | |
6095 | ||
c42fffe3 XG |
6096 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
6097 | { | |
95f93af4 | 6098 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
6099 | free_mmu_pages(vcpu); |
6100 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
6101 | } |
6102 | ||
b034cf01 XG |
6103 | void kvm_mmu_module_exit(void) |
6104 | { | |
6105 | mmu_destroy_caches(); | |
6106 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
6107 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
6108 | mmu_audit_disable(); |
6109 | } |