]>
Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
1767e931 PG |
32 | #include <linux/moduleparam.h> |
33 | #include <linux/export.h> | |
448353ca | 34 | #include <linux/swap.h> |
05da4558 | 35 | #include <linux/hugetlb.h> |
2f333bcb | 36 | #include <linux/compiler.h> |
bc6678a3 | 37 | #include <linux/srcu.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
3f07c014 | 39 | #include <linux/sched/signal.h> |
bf998156 | 40 | #include <linux/uaccess.h> |
114df303 | 41 | #include <linux/hash.h> |
f160c7b7 | 42 | #include <linux/kern_levels.h> |
6aa8b732 | 43 | |
e495606d AK |
44 | #include <asm/page.h> |
45 | #include <asm/cmpxchg.h> | |
4e542370 | 46 | #include <asm/io.h> |
13673a90 | 47 | #include <asm/vmx.h> |
3d0c27ad | 48 | #include <asm/kvm_page_track.h> |
6aa8b732 | 49 | |
18552672 JR |
50 | /* |
51 | * When setting this variable to true it enables Two-Dimensional-Paging | |
52 | * where the hardware walks 2 page tables: | |
53 | * 1. the guest-virtual to guest-physical | |
54 | * 2. while doing 1. it walks guest-physical to host-physical | |
55 | * If the hardware supports that we don't need to do shadow paging. | |
56 | */ | |
2f333bcb | 57 | bool tdp_enabled = false; |
18552672 | 58 | |
8b1fe17c XG |
59 | enum { |
60 | AUDIT_PRE_PAGE_FAULT, | |
61 | AUDIT_POST_PAGE_FAULT, | |
62 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
63 | AUDIT_POST_PTE_WRITE, |
64 | AUDIT_PRE_SYNC, | |
65 | AUDIT_POST_SYNC | |
8b1fe17c | 66 | }; |
37a7d8b0 | 67 | |
8b1fe17c | 68 | #undef MMU_DEBUG |
37a7d8b0 AK |
69 | |
70 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
71 | static bool dbg = 0; |
72 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
73 | |
74 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
75 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 76 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 77 | #else |
37a7d8b0 AK |
78 | #define pgprintk(x...) do { } while (0) |
79 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 80 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 81 | #endif |
6aa8b732 | 82 | |
957ed9ef XG |
83 | #define PTE_PREFETCH_NUM 8 |
84 | ||
00763e41 | 85 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
86 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
87 | ||
6aa8b732 AK |
88 | #define PT64_LEVEL_BITS 9 |
89 | ||
90 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 91 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 92 | |
6aa8b732 AK |
93 | #define PT64_INDEX(address, level)\ |
94 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
95 | ||
96 | ||
97 | #define PT32_LEVEL_BITS 10 | |
98 | ||
99 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 100 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 101 | |
e04da980 JR |
102 | #define PT32_LVL_OFFSET_MASK(level) \ |
103 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
104 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
105 | |
106 | #define PT32_INDEX(address, level)\ | |
107 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
108 | ||
109 | ||
27aba766 | 110 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
111 | #define PT64_DIR_BASE_ADDR_MASK \ |
112 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
113 | #define PT64_LVL_ADDR_MASK(level) \ |
114 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
115 | * PT64_LEVEL_BITS))) - 1)) | |
116 | #define PT64_LVL_OFFSET_MASK(level) \ | |
117 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
118 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
119 | |
120 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
121 | #define PT32_DIR_BASE_ADDR_MASK \ | |
122 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
123 | #define PT32_LVL_ADDR_MASK(level) \ |
124 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 126 | |
53166229 GN |
127 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
128 | | shadow_x_mask | shadow_nx_mask) | |
6aa8b732 | 129 | |
fe135d2c AK |
130 | #define ACC_EXEC_MASK 1 |
131 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
132 | #define ACC_USER_MASK PT_USER_MASK | |
133 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
134 | ||
f160c7b7 JS |
135 | /* The mask for the R/X bits in EPT PTEs */ |
136 | #define PT64_EPT_READABLE_MASK 0x1ull | |
137 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
138 | ||
90bb6fc5 AK |
139 | #include <trace/events/kvm.h> |
140 | ||
07420171 AK |
141 | #define CREATE_TRACE_POINTS |
142 | #include "mmutrace.h" | |
143 | ||
49fde340 XG |
144 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
145 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 146 | |
135f8c2b AK |
147 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
148 | ||
220f773a TY |
149 | /* make pte_list_desc fit well in cache line */ |
150 | #define PTE_LIST_EXT 3 | |
151 | ||
53c07b18 XG |
152 | struct pte_list_desc { |
153 | u64 *sptes[PTE_LIST_EXT]; | |
154 | struct pte_list_desc *more; | |
cd4a4e53 AK |
155 | }; |
156 | ||
2d11123a AK |
157 | struct kvm_shadow_walk_iterator { |
158 | u64 addr; | |
159 | hpa_t shadow_addr; | |
2d11123a | 160 | u64 *sptep; |
dd3bfd59 | 161 | int level; |
2d11123a AK |
162 | unsigned index; |
163 | }; | |
164 | ||
165 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
166 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
167 | shadow_walk_okay(&(_walker)); \ | |
168 | shadow_walk_next(&(_walker))) | |
169 | ||
c2a2ac2b XG |
170 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
171 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
172 | shadow_walk_okay(&(_walker)) && \ | |
173 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
174 | __shadow_walk_next(&(_walker), spte)) | |
175 | ||
53c07b18 | 176 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 177 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 178 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 179 | |
7b52345e SY |
180 | static u64 __read_mostly shadow_nx_mask; |
181 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
182 | static u64 __read_mostly shadow_user_mask; | |
183 | static u64 __read_mostly shadow_accessed_mask; | |
184 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 185 | static u64 __read_mostly shadow_mmio_mask; |
dcdca5fe | 186 | static u64 __read_mostly shadow_mmio_value; |
ffb128c8 | 187 | static u64 __read_mostly shadow_present_mask; |
ce88decf | 188 | |
f160c7b7 | 189 | /* |
ac8d57e5 PF |
190 | * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value. |
191 | * Non-present SPTEs with shadow_acc_track_value set are in place for access | |
192 | * tracking. | |
f160c7b7 JS |
193 | */ |
194 | static u64 __read_mostly shadow_acc_track_mask; | |
195 | static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK; | |
196 | ||
197 | /* | |
198 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
199 | * as not-present for access tracking purposes. We do not save the W bit as the | |
200 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
201 | * restored only when a write is attempted to the page. | |
202 | */ | |
203 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
204 | PT64_EPT_EXECUTABLE_MASK; | |
205 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
206 | ||
ce88decf | 207 | static void mmu_spte_set(u64 *sptep, u64 spte); |
e676505a | 208 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf | 209 | |
dcdca5fe | 210 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value) |
ce88decf | 211 | { |
dcdca5fe PF |
212 | BUG_ON((mmio_mask & mmio_value) != mmio_value); |
213 | shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK; | |
312b616b | 214 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
ce88decf XG |
215 | } |
216 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
217 | ||
ac8d57e5 PF |
218 | static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) |
219 | { | |
220 | return sp->role.ad_disabled; | |
221 | } | |
222 | ||
223 | static inline bool spte_ad_enabled(u64 spte) | |
224 | { | |
225 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
226 | return !(spte & shadow_acc_track_value); | |
227 | } | |
228 | ||
229 | static inline u64 spte_shadow_accessed_mask(u64 spte) | |
230 | { | |
231 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
232 | return spte_ad_enabled(spte) ? shadow_accessed_mask : 0; | |
233 | } | |
234 | ||
235 | static inline u64 spte_shadow_dirty_mask(u64 spte) | |
236 | { | |
237 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
238 | return spte_ad_enabled(spte) ? shadow_dirty_mask : 0; | |
239 | } | |
240 | ||
f160c7b7 JS |
241 | static inline bool is_access_track_spte(u64 spte) |
242 | { | |
ac8d57e5 | 243 | return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0; |
f160c7b7 JS |
244 | } |
245 | ||
f2fd125d | 246 | /* |
ee3d1570 DM |
247 | * the low bit of the generation number is always presumed to be zero. |
248 | * This disables mmio caching during memslot updates. The concept is | |
249 | * similar to a seqcount but instead of retrying the access we just punt | |
250 | * and ignore the cache. | |
251 | * | |
252 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
253 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 254 | */ |
ee3d1570 | 255 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
256 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
257 | ||
ee3d1570 DM |
258 | #define MMIO_GEN_SHIFT 20 |
259 | #define MMIO_GEN_LOW_SHIFT 10 | |
260 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 261 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
262 | |
263 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
264 | { | |
265 | u64 mask; | |
266 | ||
842bb26a | 267 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
268 | |
269 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
270 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
271 | return mask; | |
272 | } | |
273 | ||
274 | static unsigned int get_mmio_spte_generation(u64 spte) | |
275 | { | |
276 | unsigned int gen; | |
277 | ||
278 | spte &= ~shadow_mmio_mask; | |
279 | ||
280 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
281 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
282 | return gen; | |
283 | } | |
284 | ||
54bf36aa | 285 | static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu) |
f8f55942 | 286 | { |
54bf36aa | 287 | return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
288 | } |
289 | ||
54bf36aa | 290 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 291 | unsigned access) |
ce88decf | 292 | { |
54bf36aa | 293 | unsigned int gen = kvm_current_mmio_generation(vcpu); |
f8f55942 | 294 | u64 mask = generation_mmio_spte_mask(gen); |
95b0430d | 295 | |
ce88decf | 296 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
dcdca5fe | 297 | mask |= shadow_mmio_value | access | gfn << PAGE_SHIFT; |
f2fd125d | 298 | |
f8f55942 | 299 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 300 | mmu_spte_set(sptep, mask); |
ce88decf XG |
301 | } |
302 | ||
303 | static bool is_mmio_spte(u64 spte) | |
304 | { | |
dcdca5fe | 305 | return (spte & shadow_mmio_mask) == shadow_mmio_value; |
ce88decf XG |
306 | } |
307 | ||
308 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
309 | { | |
842bb26a | 310 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 311 | return (spte & ~mask) >> PAGE_SHIFT; |
ce88decf XG |
312 | } |
313 | ||
314 | static unsigned get_mmio_spte_access(u64 spte) | |
315 | { | |
842bb26a | 316 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 317 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
318 | } |
319 | ||
54bf36aa | 320 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 321 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
322 | { |
323 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 324 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
325 | return true; |
326 | } | |
327 | ||
328 | return false; | |
329 | } | |
c7addb90 | 330 | |
54bf36aa | 331 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 332 | { |
089504c0 XG |
333 | unsigned int kvm_gen, spte_gen; |
334 | ||
54bf36aa | 335 | kvm_gen = kvm_current_mmio_generation(vcpu); |
089504c0 XG |
336 | spte_gen = get_mmio_spte_generation(spte); |
337 | ||
338 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
339 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
340 | } |
341 | ||
ce00053b PF |
342 | /* |
343 | * Sets the shadow PTE masks used by the MMU. | |
344 | * | |
345 | * Assumptions: | |
346 | * - Setting either @accessed_mask or @dirty_mask requires setting both | |
347 | * - At least one of @accessed_mask or @acc_track_mask must be set | |
348 | */ | |
7b52345e | 349 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 JS |
350 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
351 | u64 acc_track_mask) | |
7b52345e | 352 | { |
ce00053b PF |
353 | BUG_ON(!dirty_mask != !accessed_mask); |
354 | BUG_ON(!accessed_mask && !acc_track_mask); | |
ac8d57e5 | 355 | BUG_ON(acc_track_mask & shadow_acc_track_value); |
312b616b | 356 | |
7b52345e SY |
357 | shadow_user_mask = user_mask; |
358 | shadow_accessed_mask = accessed_mask; | |
359 | shadow_dirty_mask = dirty_mask; | |
360 | shadow_nx_mask = nx_mask; | |
361 | shadow_x_mask = x_mask; | |
ffb128c8 | 362 | shadow_present_mask = p_mask; |
f160c7b7 | 363 | shadow_acc_track_mask = acc_track_mask; |
7b52345e SY |
364 | } |
365 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
366 | ||
f160c7b7 JS |
367 | void kvm_mmu_clear_all_pte_masks(void) |
368 | { | |
369 | shadow_user_mask = 0; | |
370 | shadow_accessed_mask = 0; | |
371 | shadow_dirty_mask = 0; | |
372 | shadow_nx_mask = 0; | |
373 | shadow_x_mask = 0; | |
374 | shadow_mmio_mask = 0; | |
375 | shadow_present_mask = 0; | |
376 | shadow_acc_track_mask = 0; | |
377 | } | |
378 | ||
6aa8b732 AK |
379 | static int is_cpuid_PSE36(void) |
380 | { | |
381 | return 1; | |
382 | } | |
383 | ||
73b1087e AK |
384 | static int is_nx(struct kvm_vcpu *vcpu) |
385 | { | |
f6801dff | 386 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
387 | } |
388 | ||
c7addb90 AK |
389 | static int is_shadow_present_pte(u64 pte) |
390 | { | |
f160c7b7 | 391 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
392 | } |
393 | ||
05da4558 MT |
394 | static int is_large_pte(u64 pte) |
395 | { | |
396 | return pte & PT_PAGE_SIZE_MASK; | |
397 | } | |
398 | ||
776e6633 MT |
399 | static int is_last_spte(u64 pte, int level) |
400 | { | |
401 | if (level == PT_PAGE_TABLE_LEVEL) | |
402 | return 1; | |
852e3c19 | 403 | if (is_large_pte(pte)) |
776e6633 MT |
404 | return 1; |
405 | return 0; | |
406 | } | |
407 | ||
d3e328f2 JS |
408 | static bool is_executable_pte(u64 spte) |
409 | { | |
410 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
411 | } | |
412 | ||
ba049e93 | 413 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 414 | { |
35149e21 | 415 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
416 | } |
417 | ||
da928521 AK |
418 | static gfn_t pse36_gfn_delta(u32 gpte) |
419 | { | |
420 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
421 | ||
422 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
423 | } | |
424 | ||
603e0651 | 425 | #ifdef CONFIG_X86_64 |
d555c333 | 426 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 427 | { |
b19ee2ff | 428 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
429 | } |
430 | ||
603e0651 | 431 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 432 | { |
b19ee2ff | 433 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
434 | } |
435 | ||
436 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
437 | { | |
438 | return xchg(sptep, spte); | |
439 | } | |
c2a2ac2b XG |
440 | |
441 | static u64 __get_spte_lockless(u64 *sptep) | |
442 | { | |
443 | return ACCESS_ONCE(*sptep); | |
444 | } | |
a9221dd5 | 445 | #else |
603e0651 XG |
446 | union split_spte { |
447 | struct { | |
448 | u32 spte_low; | |
449 | u32 spte_high; | |
450 | }; | |
451 | u64 spte; | |
452 | }; | |
a9221dd5 | 453 | |
c2a2ac2b XG |
454 | static void count_spte_clear(u64 *sptep, u64 spte) |
455 | { | |
456 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
457 | ||
458 | if (is_shadow_present_pte(spte)) | |
459 | return; | |
460 | ||
461 | /* Ensure the spte is completely set before we increase the count */ | |
462 | smp_wmb(); | |
463 | sp->clear_spte_count++; | |
464 | } | |
465 | ||
603e0651 XG |
466 | static void __set_spte(u64 *sptep, u64 spte) |
467 | { | |
468 | union split_spte *ssptep, sspte; | |
a9221dd5 | 469 | |
603e0651 XG |
470 | ssptep = (union split_spte *)sptep; |
471 | sspte = (union split_spte)spte; | |
472 | ||
473 | ssptep->spte_high = sspte.spte_high; | |
474 | ||
475 | /* | |
476 | * If we map the spte from nonpresent to present, We should store | |
477 | * the high bits firstly, then set present bit, so cpu can not | |
478 | * fetch this spte while we are setting the spte. | |
479 | */ | |
480 | smp_wmb(); | |
481 | ||
b19ee2ff | 482 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
483 | } |
484 | ||
603e0651 XG |
485 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
486 | { | |
487 | union split_spte *ssptep, sspte; | |
488 | ||
489 | ssptep = (union split_spte *)sptep; | |
490 | sspte = (union split_spte)spte; | |
491 | ||
b19ee2ff | 492 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
493 | |
494 | /* | |
495 | * If we map the spte from present to nonpresent, we should clear | |
496 | * present bit firstly to avoid vcpu fetch the old high bits. | |
497 | */ | |
498 | smp_wmb(); | |
499 | ||
500 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 501 | count_spte_clear(sptep, spte); |
603e0651 XG |
502 | } |
503 | ||
504 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
505 | { | |
506 | union split_spte *ssptep, sspte, orig; | |
507 | ||
508 | ssptep = (union split_spte *)sptep; | |
509 | sspte = (union split_spte)spte; | |
510 | ||
511 | /* xchg acts as a barrier before the setting of the high bits */ | |
512 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
513 | orig.spte_high = ssptep->spte_high; |
514 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 515 | count_spte_clear(sptep, spte); |
603e0651 XG |
516 | |
517 | return orig.spte; | |
518 | } | |
c2a2ac2b XG |
519 | |
520 | /* | |
521 | * The idea using the light way get the spte on x86_32 guest is from | |
522 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
523 | * |
524 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
525 | * coalesces them and we are running out of the MMU lock. Therefore | |
526 | * we need to protect against in-progress updates of the spte. | |
527 | * | |
528 | * Reading the spte while an update is in progress may get the old value | |
529 | * for the high part of the spte. The race is fine for a present->non-present | |
530 | * change (because the high part of the spte is ignored for non-present spte), | |
531 | * but for a present->present change we must reread the spte. | |
532 | * | |
533 | * All such changes are done in two steps (present->non-present and | |
534 | * non-present->present), hence it is enough to count the number of | |
535 | * present->non-present updates: if it changed while reading the spte, | |
536 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
537 | */ |
538 | static u64 __get_spte_lockless(u64 *sptep) | |
539 | { | |
540 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
541 | union split_spte spte, *orig = (union split_spte *)sptep; | |
542 | int count; | |
543 | ||
544 | retry: | |
545 | count = sp->clear_spte_count; | |
546 | smp_rmb(); | |
547 | ||
548 | spte.spte_low = orig->spte_low; | |
549 | smp_rmb(); | |
550 | ||
551 | spte.spte_high = orig->spte_high; | |
552 | smp_rmb(); | |
553 | ||
554 | if (unlikely(spte.spte_low != orig->spte_low || | |
555 | count != sp->clear_spte_count)) | |
556 | goto retry; | |
557 | ||
558 | return spte.spte; | |
559 | } | |
603e0651 XG |
560 | #endif |
561 | ||
ea4114bc | 562 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 563 | { |
feb3eb70 GN |
564 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
565 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
566 | } |
567 | ||
8672b721 XG |
568 | static bool spte_has_volatile_bits(u64 spte) |
569 | { | |
f160c7b7 JS |
570 | if (!is_shadow_present_pte(spte)) |
571 | return false; | |
572 | ||
c7ba5b48 | 573 | /* |
6a6256f9 | 574 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
575 | * out of mmu-lock, it can ensure dirty bit is not lost, |
576 | * also, it can help us to get a stable is_writable_pte() | |
577 | * to ensure tlb flush is not missed. | |
578 | */ | |
f160c7b7 JS |
579 | if (spte_can_locklessly_be_made_writable(spte) || |
580 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
581 | return true; |
582 | ||
ac8d57e5 | 583 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
584 | if ((spte & shadow_accessed_mask) == 0 || |
585 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
586 | return true; | |
587 | } | |
8672b721 | 588 | |
f160c7b7 | 589 | return false; |
8672b721 XG |
590 | } |
591 | ||
83ef6c81 | 592 | static bool is_accessed_spte(u64 spte) |
4132779b | 593 | { |
ac8d57e5 PF |
594 | u64 accessed_mask = spte_shadow_accessed_mask(spte); |
595 | ||
596 | return accessed_mask ? spte & accessed_mask | |
597 | : !is_access_track_spte(spte); | |
4132779b XG |
598 | } |
599 | ||
83ef6c81 | 600 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 601 | { |
ac8d57e5 PF |
602 | u64 dirty_mask = spte_shadow_dirty_mask(spte); |
603 | ||
604 | return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
605 | } |
606 | ||
1df9f2dc XG |
607 | /* Rules for using mmu_spte_set: |
608 | * Set the sptep from nonpresent to present. | |
609 | * Note: the sptep being assigned *must* be either not present | |
610 | * or in a state where the hardware will not attempt to update | |
611 | * the spte. | |
612 | */ | |
613 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
614 | { | |
615 | WARN_ON(is_shadow_present_pte(*sptep)); | |
616 | __set_spte(sptep, new_spte); | |
617 | } | |
618 | ||
f39a058d JS |
619 | /* |
620 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
621 | * accessed/dirty status. | |
1df9f2dc | 622 | */ |
f39a058d | 623 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 624 | { |
c7ba5b48 | 625 | u64 old_spte = *sptep; |
4132779b | 626 | |
afd28fe1 | 627 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 628 | |
6e7d0354 XG |
629 | if (!is_shadow_present_pte(old_spte)) { |
630 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 631 | return old_spte; |
6e7d0354 | 632 | } |
4132779b | 633 | |
c7ba5b48 | 634 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 635 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 636 | else |
603e0651 | 637 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 638 | |
83ef6c81 JS |
639 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
640 | ||
f39a058d JS |
641 | return old_spte; |
642 | } | |
643 | ||
644 | /* Rules for using mmu_spte_update: | |
645 | * Update the state bits, it means the mapped pfn is not changed. | |
646 | * | |
647 | * Whenever we overwrite a writable spte with a read-only one we | |
648 | * should flush remote TLBs. Otherwise rmap_write_protect | |
649 | * will find a read-only spte, even though the writable spte | |
650 | * might be cached on a CPU's TLB, the return value indicates this | |
651 | * case. | |
652 | * | |
653 | * Returns true if the TLB needs to be flushed | |
654 | */ | |
655 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
656 | { | |
657 | bool flush = false; | |
658 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
659 | ||
660 | if (!is_shadow_present_pte(old_spte)) | |
661 | return false; | |
662 | ||
c7ba5b48 XG |
663 | /* |
664 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 665 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
666 | * spte_has_volatile_bits(). |
667 | */ | |
ea4114bc | 668 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 669 | !is_writable_pte(new_spte)) |
83ef6c81 | 670 | flush = true; |
4132779b | 671 | |
7e71a59b | 672 | /* |
83ef6c81 | 673 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
674 | * to guarantee consistency between TLB and page tables. |
675 | */ | |
7e71a59b | 676 | |
83ef6c81 JS |
677 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
678 | flush = true; | |
4132779b | 679 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
680 | } |
681 | ||
682 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
683 | flush = true; | |
4132779b | 684 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 685 | } |
6e7d0354 | 686 | |
83ef6c81 | 687 | return flush; |
b79b93f9 AK |
688 | } |
689 | ||
1df9f2dc XG |
690 | /* |
691 | * Rules for using mmu_spte_clear_track_bits: | |
692 | * It sets the sptep from present to nonpresent, and track the | |
693 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 694 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
695 | */ |
696 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
697 | { | |
ba049e93 | 698 | kvm_pfn_t pfn; |
1df9f2dc XG |
699 | u64 old_spte = *sptep; |
700 | ||
701 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 702 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 703 | else |
603e0651 | 704 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 705 | |
afd28fe1 | 706 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
707 | return 0; |
708 | ||
709 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
710 | |
711 | /* | |
712 | * KVM does not hold the refcount of the page used by | |
713 | * kvm mmu, before reclaiming the page, we should | |
714 | * unmap it from mmu first. | |
715 | */ | |
bf4bea8e | 716 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 717 | |
83ef6c81 | 718 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 719 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
720 | |
721 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 722 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 723 | |
1df9f2dc XG |
724 | return 1; |
725 | } | |
726 | ||
727 | /* | |
728 | * Rules for using mmu_spte_clear_no_track: | |
729 | * Directly clear spte without caring the state bits of sptep, | |
730 | * it is used to set the upper level spte. | |
731 | */ | |
732 | static void mmu_spte_clear_no_track(u64 *sptep) | |
733 | { | |
603e0651 | 734 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
735 | } |
736 | ||
c2a2ac2b XG |
737 | static u64 mmu_spte_get_lockless(u64 *sptep) |
738 | { | |
739 | return __get_spte_lockless(sptep); | |
740 | } | |
741 | ||
f160c7b7 JS |
742 | static u64 mark_spte_for_access_track(u64 spte) |
743 | { | |
ac8d57e5 | 744 | if (spte_ad_enabled(spte)) |
f160c7b7 JS |
745 | return spte & ~shadow_accessed_mask; |
746 | ||
ac8d57e5 | 747 | if (is_access_track_spte(spte)) |
f160c7b7 JS |
748 | return spte; |
749 | ||
750 | /* | |
20d65236 JS |
751 | * Making an Access Tracking PTE will result in removal of write access |
752 | * from the PTE. So, verify that we will be able to restore the write | |
753 | * access in the fast page fault path later on. | |
f160c7b7 JS |
754 | */ |
755 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
756 | !spte_can_locklessly_be_made_writable(spte), | |
757 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
758 | ||
759 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
760 | shadow_acc_track_saved_bits_shift), | |
761 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
762 | ||
763 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
764 | shadow_acc_track_saved_bits_shift; | |
765 | spte &= ~shadow_acc_track_mask; | |
f160c7b7 JS |
766 | |
767 | return spte; | |
768 | } | |
769 | ||
d3e328f2 JS |
770 | /* Restore an acc-track PTE back to a regular PTE */ |
771 | static u64 restore_acc_track_spte(u64 spte) | |
772 | { | |
773 | u64 new_spte = spte; | |
774 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
775 | & shadow_acc_track_saved_bits_mask; | |
776 | ||
ac8d57e5 | 777 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
778 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
779 | ||
780 | new_spte &= ~shadow_acc_track_mask; | |
781 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
782 | shadow_acc_track_saved_bits_shift); | |
783 | new_spte |= saved_bits; | |
784 | ||
785 | return new_spte; | |
786 | } | |
787 | ||
f160c7b7 JS |
788 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
789 | static bool mmu_spte_age(u64 *sptep) | |
790 | { | |
791 | u64 spte = mmu_spte_get_lockless(sptep); | |
792 | ||
793 | if (!is_accessed_spte(spte)) | |
794 | return false; | |
795 | ||
ac8d57e5 | 796 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
797 | clear_bit((ffs(shadow_accessed_mask) - 1), |
798 | (unsigned long *)sptep); | |
799 | } else { | |
800 | /* | |
801 | * Capture the dirty status of the page, so that it doesn't get | |
802 | * lost when the SPTE is marked for access tracking. | |
803 | */ | |
804 | if (is_writable_pte(spte)) | |
805 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
806 | ||
807 | spte = mark_spte_for_access_track(spte); | |
808 | mmu_spte_update_no_track(sptep, spte); | |
809 | } | |
810 | ||
811 | return true; | |
812 | } | |
813 | ||
c2a2ac2b XG |
814 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
815 | { | |
c142786c AK |
816 | /* |
817 | * Prevent page table teardown by making any free-er wait during | |
818 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
819 | */ | |
820 | local_irq_disable(); | |
36ca7e0a | 821 | |
c142786c AK |
822 | /* |
823 | * Make sure a following spte read is not reordered ahead of the write | |
824 | * to vcpu->mode. | |
825 | */ | |
36ca7e0a | 826 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
827 | } |
828 | ||
829 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
830 | { | |
c142786c AK |
831 | /* |
832 | * Make sure the write to vcpu->mode is not reordered in front of | |
833 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
834 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
835 | */ | |
36ca7e0a | 836 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 837 | local_irq_enable(); |
c2a2ac2b XG |
838 | } |
839 | ||
e2dec939 | 840 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 841 | struct kmem_cache *base_cache, int min) |
714b93da AK |
842 | { |
843 | void *obj; | |
844 | ||
845 | if (cache->nobjs >= min) | |
e2dec939 | 846 | return 0; |
714b93da | 847 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 848 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 849 | if (!obj) |
e2dec939 | 850 | return -ENOMEM; |
714b93da AK |
851 | cache->objects[cache->nobjs++] = obj; |
852 | } | |
e2dec939 | 853 | return 0; |
714b93da AK |
854 | } |
855 | ||
f759e2b4 XG |
856 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
857 | { | |
858 | return cache->nobjs; | |
859 | } | |
860 | ||
e8ad9a70 XG |
861 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
862 | struct kmem_cache *cache) | |
714b93da AK |
863 | { |
864 | while (mc->nobjs) | |
e8ad9a70 | 865 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
866 | } |
867 | ||
c1158e63 | 868 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 869 | int min) |
c1158e63 | 870 | { |
842f22ed | 871 | void *page; |
c1158e63 AK |
872 | |
873 | if (cache->nobjs >= min) | |
874 | return 0; | |
875 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 876 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
877 | if (!page) |
878 | return -ENOMEM; | |
842f22ed | 879 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
880 | } |
881 | return 0; | |
882 | } | |
883 | ||
884 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
885 | { | |
886 | while (mc->nobjs) | |
c4d198d5 | 887 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
888 | } |
889 | ||
2e3e5882 | 890 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 891 | { |
e2dec939 AK |
892 | int r; |
893 | ||
53c07b18 | 894 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 895 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
896 | if (r) |
897 | goto out; | |
ad312c7c | 898 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
899 | if (r) |
900 | goto out; | |
ad312c7c | 901 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 902 | mmu_page_header_cache, 4); |
e2dec939 AK |
903 | out: |
904 | return r; | |
714b93da AK |
905 | } |
906 | ||
907 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
908 | { | |
53c07b18 XG |
909 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
910 | pte_list_desc_cache); | |
ad312c7c | 911 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
912 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
913 | mmu_page_header_cache); | |
714b93da AK |
914 | } |
915 | ||
80feb89a | 916 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
917 | { |
918 | void *p; | |
919 | ||
920 | BUG_ON(!mc->nobjs); | |
921 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
922 | return p; |
923 | } | |
924 | ||
53c07b18 | 925 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 926 | { |
80feb89a | 927 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
928 | } |
929 | ||
53c07b18 | 930 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 931 | { |
53c07b18 | 932 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
933 | } |
934 | ||
2032a93d LJ |
935 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
936 | { | |
937 | if (!sp->role.direct) | |
938 | return sp->gfns[index]; | |
939 | ||
940 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
941 | } | |
942 | ||
943 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
944 | { | |
945 | if (sp->role.direct) | |
946 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
947 | else | |
948 | sp->gfns[index] = gfn; | |
949 | } | |
950 | ||
05da4558 | 951 | /* |
d4dbf470 TY |
952 | * Return the pointer to the large page information for a given gfn, |
953 | * handling slots that are not large page aligned. | |
05da4558 | 954 | */ |
d4dbf470 TY |
955 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
956 | struct kvm_memory_slot *slot, | |
957 | int level) | |
05da4558 MT |
958 | { |
959 | unsigned long idx; | |
960 | ||
fb03cb6f | 961 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 962 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
963 | } |
964 | ||
547ffaed XG |
965 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
966 | gfn_t gfn, int count) | |
967 | { | |
968 | struct kvm_lpage_info *linfo; | |
969 | int i; | |
970 | ||
971 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
972 | linfo = lpage_info_slot(gfn, slot, i); | |
973 | linfo->disallow_lpage += count; | |
974 | WARN_ON(linfo->disallow_lpage < 0); | |
975 | } | |
976 | } | |
977 | ||
978 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
979 | { | |
980 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
981 | } | |
982 | ||
983 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
984 | { | |
985 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
986 | } | |
987 | ||
3ed1a478 | 988 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 989 | { |
699023e2 | 990 | struct kvm_memslots *slots; |
d25797b2 | 991 | struct kvm_memory_slot *slot; |
3ed1a478 | 992 | gfn_t gfn; |
05da4558 | 993 | |
56ca57f9 | 994 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 995 | gfn = sp->gfn; |
699023e2 PB |
996 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
997 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
998 | |
999 | /* the non-leaf shadow pages are keeping readonly. */ | |
1000 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
1001 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
1002 | KVM_PAGE_TRACK_WRITE); | |
1003 | ||
547ffaed | 1004 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
1005 | } |
1006 | ||
3ed1a478 | 1007 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1008 | { |
699023e2 | 1009 | struct kvm_memslots *slots; |
d25797b2 | 1010 | struct kvm_memory_slot *slot; |
3ed1a478 | 1011 | gfn_t gfn; |
05da4558 | 1012 | |
56ca57f9 | 1013 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 1014 | gfn = sp->gfn; |
699023e2 PB |
1015 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1016 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1017 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
1018 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1019 | KVM_PAGE_TRACK_WRITE); | |
1020 | ||
547ffaed | 1021 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
1022 | } |
1023 | ||
92f94f1e XG |
1024 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
1025 | struct kvm_memory_slot *slot) | |
05da4558 | 1026 | { |
d4dbf470 | 1027 | struct kvm_lpage_info *linfo; |
05da4558 MT |
1028 | |
1029 | if (slot) { | |
d4dbf470 | 1030 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 1031 | return !!linfo->disallow_lpage; |
05da4558 MT |
1032 | } |
1033 | ||
92f94f1e | 1034 | return true; |
05da4558 MT |
1035 | } |
1036 | ||
92f94f1e XG |
1037 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
1038 | int level) | |
5225fdf8 TY |
1039 | { |
1040 | struct kvm_memory_slot *slot; | |
1041 | ||
1042 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 1043 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
1044 | } |
1045 | ||
d25797b2 | 1046 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 1047 | { |
8f0b1ab6 | 1048 | unsigned long page_size; |
d25797b2 | 1049 | int i, ret = 0; |
05da4558 | 1050 | |
8f0b1ab6 | 1051 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 1052 | |
8a3d08f1 | 1053 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
1054 | if (page_size >= KVM_HPAGE_SIZE(i)) |
1055 | ret = i; | |
1056 | else | |
1057 | break; | |
1058 | } | |
1059 | ||
4c2155ce | 1060 | return ret; |
05da4558 MT |
1061 | } |
1062 | ||
d8aacf5d TY |
1063 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
1064 | bool no_dirty_log) | |
1065 | { | |
1066 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
1067 | return false; | |
1068 | if (no_dirty_log && slot->dirty_bitmap) | |
1069 | return false; | |
1070 | ||
1071 | return true; | |
1072 | } | |
1073 | ||
5d163b1c XG |
1074 | static struct kvm_memory_slot * |
1075 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1076 | bool no_dirty_log) | |
05da4558 MT |
1077 | { |
1078 | struct kvm_memory_slot *slot; | |
5d163b1c | 1079 | |
54bf36aa | 1080 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 1081 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
1082 | slot = NULL; |
1083 | ||
1084 | return slot; | |
1085 | } | |
1086 | ||
fd136902 TY |
1087 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
1088 | bool *force_pt_level) | |
936a5fe6 AA |
1089 | { |
1090 | int host_level, level, max_level; | |
d8aacf5d TY |
1091 | struct kvm_memory_slot *slot; |
1092 | ||
8c85ac1c TY |
1093 | if (unlikely(*force_pt_level)) |
1094 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 1095 | |
8c85ac1c TY |
1096 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
1097 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
1098 | if (unlikely(*force_pt_level)) |
1099 | return PT_PAGE_TABLE_LEVEL; | |
1100 | ||
d25797b2 JR |
1101 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
1102 | ||
1103 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
1104 | return host_level; | |
1105 | ||
55dd98c3 | 1106 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
1107 | |
1108 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 1109 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 1110 | break; |
d25797b2 JR |
1111 | |
1112 | return level - 1; | |
05da4558 MT |
1113 | } |
1114 | ||
290fc38d | 1115 | /* |
018aabb5 | 1116 | * About rmap_head encoding: |
cd4a4e53 | 1117 | * |
018aabb5 TY |
1118 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1119 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1120 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1121 | */ |
1122 | ||
1123 | /* | |
1124 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1125 | */ |
53c07b18 | 1126 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1127 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1128 | { |
53c07b18 | 1129 | struct pte_list_desc *desc; |
53a27b39 | 1130 | int i, count = 0; |
cd4a4e53 | 1131 | |
018aabb5 | 1132 | if (!rmap_head->val) { |
53c07b18 | 1133 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1134 | rmap_head->val = (unsigned long)spte; |
1135 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1136 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1137 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1138 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1139 | desc->sptes[1] = spte; |
018aabb5 | 1140 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1141 | ++count; |
cd4a4e53 | 1142 | } else { |
53c07b18 | 1143 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1144 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1145 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1146 | desc = desc->more; |
53c07b18 | 1147 | count += PTE_LIST_EXT; |
53a27b39 | 1148 | } |
53c07b18 XG |
1149 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1150 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1151 | desc = desc->more; |
1152 | } | |
d555c333 | 1153 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1154 | ++count; |
d555c333 | 1155 | desc->sptes[i] = spte; |
cd4a4e53 | 1156 | } |
53a27b39 | 1157 | return count; |
cd4a4e53 AK |
1158 | } |
1159 | ||
53c07b18 | 1160 | static void |
018aabb5 TY |
1161 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1162 | struct pte_list_desc *desc, int i, | |
1163 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1164 | { |
1165 | int j; | |
1166 | ||
53c07b18 | 1167 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1168 | ; |
d555c333 AK |
1169 | desc->sptes[i] = desc->sptes[j]; |
1170 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1171 | if (j != 0) |
1172 | return; | |
1173 | if (!prev_desc && !desc->more) | |
018aabb5 | 1174 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
1175 | else |
1176 | if (prev_desc) | |
1177 | prev_desc->more = desc->more; | |
1178 | else | |
018aabb5 | 1179 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1180 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1181 | } |
1182 | ||
018aabb5 | 1183 | static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1184 | { |
53c07b18 XG |
1185 | struct pte_list_desc *desc; |
1186 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1187 | int i; |
1188 | ||
018aabb5 | 1189 | if (!rmap_head->val) { |
53c07b18 | 1190 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 1191 | BUG(); |
018aabb5 | 1192 | } else if (!(rmap_head->val & 1)) { |
53c07b18 | 1193 | rmap_printk("pte_list_remove: %p 1->0\n", spte); |
018aabb5 | 1194 | if ((u64 *)rmap_head->val != spte) { |
53c07b18 | 1195 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
1196 | BUG(); |
1197 | } | |
018aabb5 | 1198 | rmap_head->val = 0; |
cd4a4e53 | 1199 | } else { |
53c07b18 | 1200 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
018aabb5 | 1201 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1202 | prev_desc = NULL; |
1203 | while (desc) { | |
018aabb5 | 1204 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1205 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1206 | pte_list_desc_remove_entry(rmap_head, |
1207 | desc, i, prev_desc); | |
cd4a4e53 AK |
1208 | return; |
1209 | } | |
018aabb5 | 1210 | } |
cd4a4e53 AK |
1211 | prev_desc = desc; |
1212 | desc = desc->more; | |
1213 | } | |
53c07b18 | 1214 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1215 | BUG(); |
1216 | } | |
1217 | } | |
1218 | ||
018aabb5 TY |
1219 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1220 | struct kvm_memory_slot *slot) | |
53c07b18 | 1221 | { |
77d11309 | 1222 | unsigned long idx; |
53c07b18 | 1223 | |
77d11309 | 1224 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1225 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1226 | } |
1227 | ||
018aabb5 TY |
1228 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1229 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1230 | { |
699023e2 | 1231 | struct kvm_memslots *slots; |
9b9b1492 TY |
1232 | struct kvm_memory_slot *slot; |
1233 | ||
699023e2 PB |
1234 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1235 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1236 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1237 | } |
1238 | ||
f759e2b4 XG |
1239 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1240 | { | |
1241 | struct kvm_mmu_memory_cache *cache; | |
1242 | ||
1243 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1244 | return mmu_memory_cache_free_objects(cache); | |
1245 | } | |
1246 | ||
53c07b18 XG |
1247 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1248 | { | |
1249 | struct kvm_mmu_page *sp; | |
018aabb5 | 1250 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1251 | |
53c07b18 XG |
1252 | sp = page_header(__pa(spte)); |
1253 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1254 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1255 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1256 | } |
1257 | ||
53c07b18 XG |
1258 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1259 | { | |
1260 | struct kvm_mmu_page *sp; | |
1261 | gfn_t gfn; | |
018aabb5 | 1262 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1263 | |
1264 | sp = page_header(__pa(spte)); | |
1265 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 TY |
1266 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
1267 | pte_list_remove(spte, rmap_head); | |
53c07b18 XG |
1268 | } |
1269 | ||
1e3f42f0 TY |
1270 | /* |
1271 | * Used by the following functions to iterate through the sptes linked by a | |
1272 | * rmap. All fields are private and not assumed to be used outside. | |
1273 | */ | |
1274 | struct rmap_iterator { | |
1275 | /* private fields */ | |
1276 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1277 | int pos; /* index of the sptep */ | |
1278 | }; | |
1279 | ||
1280 | /* | |
1281 | * Iteration must be started by this function. This should also be used after | |
1282 | * removing/dropping sptes from the rmap link because in such cases the | |
1283 | * information in the itererator may not be valid. | |
1284 | * | |
1285 | * Returns sptep if found, NULL otherwise. | |
1286 | */ | |
018aabb5 TY |
1287 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1288 | struct rmap_iterator *iter) | |
1e3f42f0 | 1289 | { |
77fbbbd2 TY |
1290 | u64 *sptep; |
1291 | ||
018aabb5 | 1292 | if (!rmap_head->val) |
1e3f42f0 TY |
1293 | return NULL; |
1294 | ||
018aabb5 | 1295 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1296 | iter->desc = NULL; |
77fbbbd2 TY |
1297 | sptep = (u64 *)rmap_head->val; |
1298 | goto out; | |
1e3f42f0 TY |
1299 | } |
1300 | ||
018aabb5 | 1301 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1302 | iter->pos = 0; |
77fbbbd2 TY |
1303 | sptep = iter->desc->sptes[iter->pos]; |
1304 | out: | |
1305 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1306 | return sptep; | |
1e3f42f0 TY |
1307 | } |
1308 | ||
1309 | /* | |
1310 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1311 | * | |
1312 | * Returns sptep if found, NULL otherwise. | |
1313 | */ | |
1314 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1315 | { | |
77fbbbd2 TY |
1316 | u64 *sptep; |
1317 | ||
1e3f42f0 TY |
1318 | if (iter->desc) { |
1319 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1320 | ++iter->pos; |
1321 | sptep = iter->desc->sptes[iter->pos]; | |
1322 | if (sptep) | |
77fbbbd2 | 1323 | goto out; |
1e3f42f0 TY |
1324 | } |
1325 | ||
1326 | iter->desc = iter->desc->more; | |
1327 | ||
1328 | if (iter->desc) { | |
1329 | iter->pos = 0; | |
1330 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1331 | sptep = iter->desc->sptes[iter->pos]; |
1332 | goto out; | |
1e3f42f0 TY |
1333 | } |
1334 | } | |
1335 | ||
1336 | return NULL; | |
77fbbbd2 TY |
1337 | out: |
1338 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1339 | return sptep; | |
1e3f42f0 TY |
1340 | } |
1341 | ||
018aabb5 TY |
1342 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1343 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1344 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1345 | |
c3707958 | 1346 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1347 | { |
1df9f2dc | 1348 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1349 | rmap_remove(kvm, sptep); |
be38d276 AK |
1350 | } |
1351 | ||
8e22f955 XG |
1352 | |
1353 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1354 | { | |
1355 | if (is_large_pte(*sptep)) { | |
1356 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1357 | PT_PAGE_TABLE_LEVEL); | |
1358 | drop_spte(kvm, sptep); | |
1359 | --kvm->stat.lpages; | |
1360 | return true; | |
1361 | } | |
1362 | ||
1363 | return false; | |
1364 | } | |
1365 | ||
1366 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1367 | { | |
1368 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1369 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1370 | } | |
1371 | ||
1372 | /* | |
49fde340 | 1373 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1374 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1375 | * |
b4619660 | 1376 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1377 | * protection: |
1378 | * - for dirty logging, the spte can be set to writable at anytime if | |
1379 | * its dirty bitmap is properly set. | |
1380 | * - for spte protection, the spte can be writable only after unsync-ing | |
1381 | * shadow page. | |
8e22f955 | 1382 | * |
c126d94f | 1383 | * Return true if tlb need be flushed. |
8e22f955 | 1384 | */ |
c4f138b4 | 1385 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1386 | { |
1387 | u64 spte = *sptep; | |
1388 | ||
49fde340 | 1389 | if (!is_writable_pte(spte) && |
ea4114bc | 1390 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1391 | return false; |
1392 | ||
1393 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1394 | ||
49fde340 XG |
1395 | if (pt_protect) |
1396 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1397 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1398 | |
c126d94f | 1399 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1400 | } |
1401 | ||
018aabb5 TY |
1402 | static bool __rmap_write_protect(struct kvm *kvm, |
1403 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1404 | bool pt_protect) |
98348e95 | 1405 | { |
1e3f42f0 TY |
1406 | u64 *sptep; |
1407 | struct rmap_iterator iter; | |
d13bc5b5 | 1408 | bool flush = false; |
374cbac0 | 1409 | |
018aabb5 | 1410 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1411 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1412 | |
d13bc5b5 | 1413 | return flush; |
a0ed4607 TY |
1414 | } |
1415 | ||
c4f138b4 | 1416 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1417 | { |
1418 | u64 spte = *sptep; | |
1419 | ||
1420 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1421 | ||
1422 | spte &= ~shadow_dirty_mask; | |
1423 | ||
1424 | return mmu_spte_update(sptep, spte); | |
1425 | } | |
1426 | ||
ac8d57e5 PF |
1427 | static bool wrprot_ad_disabled_spte(u64 *sptep) |
1428 | { | |
1429 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1430 | (unsigned long *)sptep); | |
1431 | if (was_writable) | |
1432 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); | |
1433 | ||
1434 | return was_writable; | |
1435 | } | |
1436 | ||
1437 | /* | |
1438 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1439 | * - D bit on ad-enabled SPTEs, and | |
1440 | * - W bit on ad-disabled SPTEs. | |
1441 | * Returns true iff any D or W bits were cleared. | |
1442 | */ | |
018aabb5 | 1443 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1444 | { |
1445 | u64 *sptep; | |
1446 | struct rmap_iterator iter; | |
1447 | bool flush = false; | |
1448 | ||
018aabb5 | 1449 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1450 | if (spte_ad_enabled(*sptep)) |
1451 | flush |= spte_clear_dirty(sptep); | |
1452 | else | |
1453 | flush |= wrprot_ad_disabled_spte(sptep); | |
f4b4b180 KH |
1454 | |
1455 | return flush; | |
1456 | } | |
1457 | ||
c4f138b4 | 1458 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1459 | { |
1460 | u64 spte = *sptep; | |
1461 | ||
1462 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1463 | ||
1464 | spte |= shadow_dirty_mask; | |
1465 | ||
1466 | return mmu_spte_update(sptep, spte); | |
1467 | } | |
1468 | ||
018aabb5 | 1469 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1470 | { |
1471 | u64 *sptep; | |
1472 | struct rmap_iterator iter; | |
1473 | bool flush = false; | |
1474 | ||
018aabb5 | 1475 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1476 | if (spte_ad_enabled(*sptep)) |
1477 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1478 | |
1479 | return flush; | |
1480 | } | |
1481 | ||
5dc99b23 | 1482 | /** |
3b0f1d01 | 1483 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1484 | * @kvm: kvm instance |
1485 | * @slot: slot to protect | |
1486 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1487 | * @mask: indicates which pages we should protect | |
1488 | * | |
1489 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1490 | * logging we do not have any such mappings. | |
1491 | */ | |
3b0f1d01 | 1492 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1493 | struct kvm_memory_slot *slot, |
1494 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1495 | { |
018aabb5 | 1496 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1497 | |
5dc99b23 | 1498 | while (mask) { |
018aabb5 TY |
1499 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1500 | PT_PAGE_TABLE_LEVEL, slot); | |
1501 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1502 | |
5dc99b23 TY |
1503 | /* clear the first set bit */ |
1504 | mask &= mask - 1; | |
1505 | } | |
374cbac0 AK |
1506 | } |
1507 | ||
f4b4b180 | 1508 | /** |
ac8d57e5 PF |
1509 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1510 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1511 | * @kvm: kvm instance |
1512 | * @slot: slot to clear D-bit | |
1513 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1514 | * @mask: indicates which pages we should clear D-bit | |
1515 | * | |
1516 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1517 | */ | |
1518 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1519 | struct kvm_memory_slot *slot, | |
1520 | gfn_t gfn_offset, unsigned long mask) | |
1521 | { | |
018aabb5 | 1522 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1523 | |
1524 | while (mask) { | |
018aabb5 TY |
1525 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1526 | PT_PAGE_TABLE_LEVEL, slot); | |
1527 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1528 | |
1529 | /* clear the first set bit */ | |
1530 | mask &= mask - 1; | |
1531 | } | |
1532 | } | |
1533 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1534 | ||
3b0f1d01 KH |
1535 | /** |
1536 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1537 | * PT level pages. | |
1538 | * | |
1539 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1540 | * enable dirty logging for them. | |
1541 | * | |
1542 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1543 | * logging we do not have any such mappings. | |
1544 | */ | |
1545 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1546 | struct kvm_memory_slot *slot, | |
1547 | gfn_t gfn_offset, unsigned long mask) | |
1548 | { | |
88178fd4 KH |
1549 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1550 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1551 | mask); | |
1552 | else | |
1553 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1554 | } |
1555 | ||
bab4165e BD |
1556 | /** |
1557 | * kvm_arch_write_log_dirty - emulate dirty page logging | |
1558 | * @vcpu: Guest mode vcpu | |
1559 | * | |
1560 | * Emulate arch specific page modification logging for the | |
1561 | * nested hypervisor | |
1562 | */ | |
1563 | int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu) | |
1564 | { | |
1565 | if (kvm_x86_ops->write_log_dirty) | |
1566 | return kvm_x86_ops->write_log_dirty(vcpu); | |
1567 | ||
1568 | return 0; | |
1569 | } | |
1570 | ||
aeecee2e XG |
1571 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1572 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1573 | { |
018aabb5 | 1574 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1575 | int i; |
2f84569f | 1576 | bool write_protected = false; |
95d4c16c | 1577 | |
8a3d08f1 | 1578 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1579 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1580 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1581 | } |
1582 | ||
1583 | return write_protected; | |
95d4c16c TY |
1584 | } |
1585 | ||
aeecee2e XG |
1586 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1587 | { | |
1588 | struct kvm_memory_slot *slot; | |
1589 | ||
1590 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1591 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1592 | } | |
1593 | ||
018aabb5 | 1594 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1595 | { |
1e3f42f0 TY |
1596 | u64 *sptep; |
1597 | struct rmap_iterator iter; | |
6a49f85c | 1598 | bool flush = false; |
e930bffe | 1599 | |
018aabb5 | 1600 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1601 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 TY |
1602 | |
1603 | drop_spte(kvm, sptep); | |
6a49f85c | 1604 | flush = true; |
e930bffe | 1605 | } |
1e3f42f0 | 1606 | |
6a49f85c XG |
1607 | return flush; |
1608 | } | |
1609 | ||
018aabb5 | 1610 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1611 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1612 | unsigned long data) | |
1613 | { | |
018aabb5 | 1614 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1615 | } |
1616 | ||
018aabb5 | 1617 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1618 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1619 | unsigned long data) | |
3da0dd43 | 1620 | { |
1e3f42f0 TY |
1621 | u64 *sptep; |
1622 | struct rmap_iterator iter; | |
3da0dd43 | 1623 | int need_flush = 0; |
1e3f42f0 | 1624 | u64 new_spte; |
3da0dd43 | 1625 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1626 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1627 | |
1628 | WARN_ON(pte_huge(*ptep)); | |
1629 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1630 | |
0d536790 | 1631 | restart: |
018aabb5 | 1632 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1633 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1634 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1635 | |
3da0dd43 | 1636 | need_flush = 1; |
1e3f42f0 | 1637 | |
3da0dd43 | 1638 | if (pte_write(*ptep)) { |
1e3f42f0 | 1639 | drop_spte(kvm, sptep); |
0d536790 | 1640 | goto restart; |
3da0dd43 | 1641 | } else { |
1e3f42f0 | 1642 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1643 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1644 | ||
1645 | new_spte &= ~PT_WRITABLE_MASK; | |
1646 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1647 | |
1648 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1649 | |
1650 | mmu_spte_clear_track_bits(sptep); | |
1651 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1652 | } |
1653 | } | |
1e3f42f0 | 1654 | |
3da0dd43 IE |
1655 | if (need_flush) |
1656 | kvm_flush_remote_tlbs(kvm); | |
1657 | ||
1658 | return 0; | |
1659 | } | |
1660 | ||
6ce1f4e2 XG |
1661 | struct slot_rmap_walk_iterator { |
1662 | /* input fields. */ | |
1663 | struct kvm_memory_slot *slot; | |
1664 | gfn_t start_gfn; | |
1665 | gfn_t end_gfn; | |
1666 | int start_level; | |
1667 | int end_level; | |
1668 | ||
1669 | /* output fields. */ | |
1670 | gfn_t gfn; | |
018aabb5 | 1671 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1672 | int level; |
1673 | ||
1674 | /* private field. */ | |
018aabb5 | 1675 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1676 | }; |
1677 | ||
1678 | static void | |
1679 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1680 | { | |
1681 | iterator->level = level; | |
1682 | iterator->gfn = iterator->start_gfn; | |
1683 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1684 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1685 | iterator->slot); | |
1686 | } | |
1687 | ||
1688 | static void | |
1689 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1690 | struct kvm_memory_slot *slot, int start_level, | |
1691 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1692 | { | |
1693 | iterator->slot = slot; | |
1694 | iterator->start_level = start_level; | |
1695 | iterator->end_level = end_level; | |
1696 | iterator->start_gfn = start_gfn; | |
1697 | iterator->end_gfn = end_gfn; | |
1698 | ||
1699 | rmap_walk_init_level(iterator, iterator->start_level); | |
1700 | } | |
1701 | ||
1702 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1703 | { | |
1704 | return !!iterator->rmap; | |
1705 | } | |
1706 | ||
1707 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1708 | { | |
1709 | if (++iterator->rmap <= iterator->end_rmap) { | |
1710 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1711 | return; | |
1712 | } | |
1713 | ||
1714 | if (++iterator->level > iterator->end_level) { | |
1715 | iterator->rmap = NULL; | |
1716 | return; | |
1717 | } | |
1718 | ||
1719 | rmap_walk_init_level(iterator, iterator->level); | |
1720 | } | |
1721 | ||
1722 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1723 | _start_gfn, _end_gfn, _iter_) \ | |
1724 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1725 | _end_level_, _start_gfn, _end_gfn); \ | |
1726 | slot_rmap_walk_okay(_iter_); \ | |
1727 | slot_rmap_walk_next(_iter_)) | |
1728 | ||
84504ef3 TY |
1729 | static int kvm_handle_hva_range(struct kvm *kvm, |
1730 | unsigned long start, | |
1731 | unsigned long end, | |
1732 | unsigned long data, | |
1733 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1734 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1735 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1736 | gfn_t gfn, |
1737 | int level, | |
84504ef3 | 1738 | unsigned long data)) |
e930bffe | 1739 | { |
bc6678a3 | 1740 | struct kvm_memslots *slots; |
be6ba0f0 | 1741 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1742 | struct slot_rmap_walk_iterator iterator; |
1743 | int ret = 0; | |
9da0e4d5 | 1744 | int i; |
bc6678a3 | 1745 | |
9da0e4d5 PB |
1746 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1747 | slots = __kvm_memslots(kvm, i); | |
1748 | kvm_for_each_memslot(memslot, slots) { | |
1749 | unsigned long hva_start, hva_end; | |
1750 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1751 | |
9da0e4d5 PB |
1752 | hva_start = max(start, memslot->userspace_addr); |
1753 | hva_end = min(end, memslot->userspace_addr + | |
1754 | (memslot->npages << PAGE_SHIFT)); | |
1755 | if (hva_start >= hva_end) | |
1756 | continue; | |
1757 | /* | |
1758 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1759 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1760 | */ | |
1761 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1762 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1763 | ||
1764 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1765 | PT_MAX_HUGEPAGE_LEVEL, | |
1766 | gfn_start, gfn_end - 1, | |
1767 | &iterator) | |
1768 | ret |= handler(kvm, iterator.rmap, memslot, | |
1769 | iterator.gfn, iterator.level, data); | |
1770 | } | |
e930bffe AA |
1771 | } |
1772 | ||
f395302e | 1773 | return ret; |
e930bffe AA |
1774 | } |
1775 | ||
84504ef3 TY |
1776 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1777 | unsigned long data, | |
018aabb5 TY |
1778 | int (*handler)(struct kvm *kvm, |
1779 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1780 | struct kvm_memory_slot *slot, |
8a9522d2 | 1781 | gfn_t gfn, int level, |
84504ef3 TY |
1782 | unsigned long data)) |
1783 | { | |
1784 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1785 | } |
1786 | ||
1787 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1788 | { | |
3da0dd43 IE |
1789 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1790 | } | |
1791 | ||
b3ae2096 TY |
1792 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1793 | { | |
1794 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1795 | } | |
1796 | ||
3da0dd43 IE |
1797 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1798 | { | |
8a8365c5 | 1799 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1800 | } |
1801 | ||
018aabb5 | 1802 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1803 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1804 | unsigned long data) | |
e930bffe | 1805 | { |
1e3f42f0 | 1806 | u64 *sptep; |
79f702a6 | 1807 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1808 | int young = 0; |
1809 | ||
f160c7b7 JS |
1810 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1811 | young |= mmu_spte_age(sptep); | |
0d536790 | 1812 | |
8a9522d2 | 1813 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1814 | return young; |
1815 | } | |
1816 | ||
018aabb5 | 1817 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1818 | struct kvm_memory_slot *slot, gfn_t gfn, |
1819 | int level, unsigned long data) | |
8ee53820 | 1820 | { |
1e3f42f0 TY |
1821 | u64 *sptep; |
1822 | struct rmap_iterator iter; | |
8ee53820 | 1823 | |
83ef6c81 JS |
1824 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1825 | if (is_accessed_spte(*sptep)) | |
1826 | return 1; | |
83ef6c81 | 1827 | return 0; |
8ee53820 AA |
1828 | } |
1829 | ||
53a27b39 MT |
1830 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1831 | ||
852e3c19 | 1832 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1833 | { |
018aabb5 | 1834 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1835 | struct kvm_mmu_page *sp; |
1836 | ||
1837 | sp = page_header(__pa(spte)); | |
53a27b39 | 1838 | |
018aabb5 | 1839 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1840 | |
018aabb5 | 1841 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
53a27b39 MT |
1842 | kvm_flush_remote_tlbs(vcpu->kvm); |
1843 | } | |
1844 | ||
57128468 | 1845 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1846 | { |
57128468 | 1847 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
1848 | } |
1849 | ||
8ee53820 AA |
1850 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1851 | { | |
1852 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1853 | } | |
1854 | ||
d6c69ee9 | 1855 | #ifdef MMU_DEBUG |
47ad8e68 | 1856 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1857 | { |
139bdb2d AK |
1858 | u64 *pos; |
1859 | u64 *end; | |
1860 | ||
47ad8e68 | 1861 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1862 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1863 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1864 | pos, *pos); |
6aa8b732 | 1865 | return 0; |
139bdb2d | 1866 | } |
6aa8b732 AK |
1867 | return 1; |
1868 | } | |
d6c69ee9 | 1869 | #endif |
6aa8b732 | 1870 | |
45221ab6 DH |
1871 | /* |
1872 | * This value is the sum of all of the kvm instances's | |
1873 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1874 | * aggregate version in order to make the slab shrinker | |
1875 | * faster | |
1876 | */ | |
1877 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1878 | { | |
1879 | kvm->arch.n_used_mmu_pages += nr; | |
1880 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1881 | } | |
1882 | ||
834be0d8 | 1883 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1884 | { |
fa4a2c08 | 1885 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1886 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1887 | list_del(&sp->link); |
1888 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1889 | if (!sp->role.direct) |
1890 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1891 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1892 | } |
1893 | ||
cea0f0e7 AK |
1894 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1895 | { | |
114df303 | 1896 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1897 | } |
1898 | ||
714b93da | 1899 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1900 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1901 | { |
cea0f0e7 AK |
1902 | if (!parent_pte) |
1903 | return; | |
cea0f0e7 | 1904 | |
67052b35 | 1905 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1906 | } |
1907 | ||
4db35314 | 1908 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1909 | u64 *parent_pte) |
1910 | { | |
67052b35 | 1911 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1912 | } |
1913 | ||
bcdd9a93 XG |
1914 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1915 | u64 *parent_pte) | |
1916 | { | |
1917 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1918 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1919 | } |
1920 | ||
47005792 | 1921 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1922 | { |
67052b35 | 1923 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1924 | |
80feb89a TY |
1925 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1926 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1927 | if (!direct) |
80feb89a | 1928 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1929 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1930 | |
1931 | /* | |
1932 | * The active_mmu_pages list is the FIFO list, do not move the | |
1933 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1934 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1935 | */ | |
67052b35 | 1936 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1937 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1938 | return sp; | |
ad8cfbe3 MT |
1939 | } |
1940 | ||
67052b35 | 1941 | static void mark_unsync(u64 *spte); |
1047df1f | 1942 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1943 | { |
74c4e63a TY |
1944 | u64 *sptep; |
1945 | struct rmap_iterator iter; | |
1946 | ||
1947 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1948 | mark_unsync(sptep); | |
1949 | } | |
0074ff63 MT |
1950 | } |
1951 | ||
67052b35 | 1952 | static void mark_unsync(u64 *spte) |
0074ff63 | 1953 | { |
67052b35 | 1954 | struct kvm_mmu_page *sp; |
1047df1f | 1955 | unsigned int index; |
0074ff63 | 1956 | |
67052b35 | 1957 | sp = page_header(__pa(spte)); |
1047df1f XG |
1958 | index = spte - sp->spt; |
1959 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1960 | return; |
1047df1f | 1961 | if (sp->unsync_children++) |
0074ff63 | 1962 | return; |
1047df1f | 1963 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1964 | } |
1965 | ||
e8bc217a | 1966 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1967 | struct kvm_mmu_page *sp) |
e8bc217a | 1968 | { |
1f50f1b3 | 1969 | return 0; |
e8bc217a MT |
1970 | } |
1971 | ||
a7052897 MT |
1972 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1973 | { | |
1974 | } | |
1975 | ||
0f53b5b1 XG |
1976 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1977 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1978 | const void *pte) |
0f53b5b1 XG |
1979 | { |
1980 | WARN_ON(1); | |
1981 | } | |
1982 | ||
60c8aec6 MT |
1983 | #define KVM_PAGE_ARRAY_NR 16 |
1984 | ||
1985 | struct kvm_mmu_pages { | |
1986 | struct mmu_page_and_offset { | |
1987 | struct kvm_mmu_page *sp; | |
1988 | unsigned int idx; | |
1989 | } page[KVM_PAGE_ARRAY_NR]; | |
1990 | unsigned int nr; | |
1991 | }; | |
1992 | ||
cded19f3 HE |
1993 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1994 | int idx) | |
4731d4c7 | 1995 | { |
60c8aec6 | 1996 | int i; |
4731d4c7 | 1997 | |
60c8aec6 MT |
1998 | if (sp->unsync) |
1999 | for (i=0; i < pvec->nr; i++) | |
2000 | if (pvec->page[i].sp == sp) | |
2001 | return 0; | |
2002 | ||
2003 | pvec->page[pvec->nr].sp = sp; | |
2004 | pvec->page[pvec->nr].idx = idx; | |
2005 | pvec->nr++; | |
2006 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
2007 | } | |
2008 | ||
fd951457 TY |
2009 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
2010 | { | |
2011 | --sp->unsync_children; | |
2012 | WARN_ON((int)sp->unsync_children < 0); | |
2013 | __clear_bit(idx, sp->unsync_child_bitmap); | |
2014 | } | |
2015 | ||
60c8aec6 MT |
2016 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
2017 | struct kvm_mmu_pages *pvec) | |
2018 | { | |
2019 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 2020 | |
37178b8b | 2021 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 2022 | struct kvm_mmu_page *child; |
4731d4c7 MT |
2023 | u64 ent = sp->spt[i]; |
2024 | ||
fd951457 TY |
2025 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
2026 | clear_unsync_child_bit(sp, i); | |
2027 | continue; | |
2028 | } | |
7a8f1a74 XG |
2029 | |
2030 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
2031 | ||
2032 | if (child->unsync_children) { | |
2033 | if (mmu_pages_add(pvec, child, i)) | |
2034 | return -ENOSPC; | |
2035 | ||
2036 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
2037 | if (!ret) { |
2038 | clear_unsync_child_bit(sp, i); | |
2039 | continue; | |
2040 | } else if (ret > 0) { | |
7a8f1a74 | 2041 | nr_unsync_leaf += ret; |
fd951457 | 2042 | } else |
7a8f1a74 XG |
2043 | return ret; |
2044 | } else if (child->unsync) { | |
2045 | nr_unsync_leaf++; | |
2046 | if (mmu_pages_add(pvec, child, i)) | |
2047 | return -ENOSPC; | |
2048 | } else | |
fd951457 | 2049 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2050 | } |
2051 | ||
60c8aec6 MT |
2052 | return nr_unsync_leaf; |
2053 | } | |
2054 | ||
e23d3fef XG |
2055 | #define INVALID_INDEX (-1) |
2056 | ||
60c8aec6 MT |
2057 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2058 | struct kvm_mmu_pages *pvec) | |
2059 | { | |
0a47cd85 | 2060 | pvec->nr = 0; |
60c8aec6 MT |
2061 | if (!sp->unsync_children) |
2062 | return 0; | |
2063 | ||
e23d3fef | 2064 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2065 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2066 | } |
2067 | ||
4731d4c7 MT |
2068 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2069 | { | |
2070 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2071 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2072 | sp->unsync = 0; |
2073 | --kvm->stat.mmu_unsync; | |
2074 | } | |
2075 | ||
7775834a XG |
2076 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2077 | struct list_head *invalid_list); | |
2078 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
2079 | struct list_head *invalid_list); | |
4731d4c7 | 2080 | |
f34d251d XG |
2081 | /* |
2082 | * NOTE: we should pay more attention on the zapped-obsolete page | |
2083 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
2084 | * since it has been deleted from active_mmu_pages but still can be found | |
2085 | * at hast list. | |
2086 | * | |
f3414bc7 | 2087 | * for_each_valid_sp() has skipped that kind of pages. |
f34d251d | 2088 | */ |
f3414bc7 | 2089 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2090 | hlist_for_each_entry(_sp, \ |
2091 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
f3414bc7 DM |
2092 | if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \ |
2093 | } else | |
1044b030 TY |
2094 | |
2095 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2096 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2097 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2098 | |
f918b443 | 2099 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2100 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2101 | struct list_head *invalid_list) | |
4731d4c7 | 2102 | { |
5b7e0102 | 2103 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 2104 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2105 | return false; |
4731d4c7 MT |
2106 | } |
2107 | ||
1f50f1b3 | 2108 | if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) { |
d98ba053 | 2109 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2110 | return false; |
4731d4c7 MT |
2111 | } |
2112 | ||
1f50f1b3 | 2113 | return true; |
4731d4c7 MT |
2114 | } |
2115 | ||
35a70510 PB |
2116 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2117 | struct list_head *invalid_list, | |
2118 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2119 | { |
35a70510 PB |
2120 | if (!list_empty(invalid_list)) { |
2121 | kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list); | |
2122 | return; | |
2123 | } | |
d98ba053 | 2124 | |
35a70510 PB |
2125 | if (remote_flush) |
2126 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2127 | else if (local_flush) | |
2128 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
1d9dc7e0 XG |
2129 | } |
2130 | ||
e37fa785 XG |
2131 | #ifdef CONFIG_KVM_MMU_AUDIT |
2132 | #include "mmu_audit.c" | |
2133 | #else | |
2134 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2135 | static void mmu_audit_disable(void) { } | |
2136 | #endif | |
2137 | ||
46971a2f XG |
2138 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2139 | { | |
2140 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2141 | } | |
2142 | ||
1f50f1b3 | 2143 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2144 | struct list_head *invalid_list) |
1d9dc7e0 | 2145 | { |
9a43c5d9 PB |
2146 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2147 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2148 | } |
2149 | ||
9f1a122f | 2150 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2151 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2152 | struct list_head *invalid_list) | |
9f1a122f | 2153 | { |
9f1a122f | 2154 | struct kvm_mmu_page *s; |
2a74003a | 2155 | bool ret = false; |
9f1a122f | 2156 | |
b67bfe0d | 2157 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2158 | if (!s->unsync) |
9f1a122f XG |
2159 | continue; |
2160 | ||
2161 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2162 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2163 | } |
2164 | ||
2a74003a | 2165 | return ret; |
9f1a122f XG |
2166 | } |
2167 | ||
60c8aec6 | 2168 | struct mmu_page_path { |
0a47cd85 PB |
2169 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL]; |
2170 | unsigned int idx[PT64_ROOT_LEVEL]; | |
4731d4c7 MT |
2171 | }; |
2172 | ||
60c8aec6 | 2173 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2174 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2175 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2176 | i = mmu_pages_next(&pvec, &parents, i)) | |
2177 | ||
cded19f3 HE |
2178 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2179 | struct mmu_page_path *parents, | |
2180 | int i) | |
60c8aec6 MT |
2181 | { |
2182 | int n; | |
2183 | ||
2184 | for (n = i+1; n < pvec->nr; n++) { | |
2185 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2186 | unsigned idx = pvec->page[n].idx; |
2187 | int level = sp->role.level; | |
60c8aec6 | 2188 | |
0a47cd85 PB |
2189 | parents->idx[level-1] = idx; |
2190 | if (level == PT_PAGE_TABLE_LEVEL) | |
2191 | break; | |
60c8aec6 | 2192 | |
0a47cd85 | 2193 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2194 | } |
2195 | ||
2196 | return n; | |
2197 | } | |
2198 | ||
0a47cd85 PB |
2199 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2200 | struct mmu_page_path *parents) | |
2201 | { | |
2202 | struct kvm_mmu_page *sp; | |
2203 | int level; | |
2204 | ||
2205 | if (pvec->nr == 0) | |
2206 | return 0; | |
2207 | ||
e23d3fef XG |
2208 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2209 | ||
0a47cd85 PB |
2210 | sp = pvec->page[0].sp; |
2211 | level = sp->role.level; | |
2212 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2213 | ||
2214 | parents->parent[level-2] = sp; | |
2215 | ||
2216 | /* Also set up a sentinel. Further entries in pvec are all | |
2217 | * children of sp, so this element is never overwritten. | |
2218 | */ | |
2219 | parents->parent[level-1] = NULL; | |
2220 | return mmu_pages_next(pvec, parents, 0); | |
2221 | } | |
2222 | ||
cded19f3 | 2223 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2224 | { |
60c8aec6 MT |
2225 | struct kvm_mmu_page *sp; |
2226 | unsigned int level = 0; | |
2227 | ||
2228 | do { | |
2229 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2230 | sp = parents->parent[level]; |
2231 | if (!sp) | |
2232 | return; | |
2233 | ||
e23d3fef | 2234 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2235 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2236 | level++; |
0a47cd85 | 2237 | } while (!sp->unsync_children); |
60c8aec6 | 2238 | } |
4731d4c7 | 2239 | |
60c8aec6 MT |
2240 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2241 | struct kvm_mmu_page *parent) | |
2242 | { | |
2243 | int i; | |
2244 | struct kvm_mmu_page *sp; | |
2245 | struct mmu_page_path parents; | |
2246 | struct kvm_mmu_pages pages; | |
d98ba053 | 2247 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2248 | bool flush = false; |
60c8aec6 | 2249 | |
60c8aec6 | 2250 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2251 | bool protected = false; |
b1a36821 MT |
2252 | |
2253 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2254 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2255 | |
50c9e6f3 | 2256 | if (protected) { |
b1a36821 | 2257 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2258 | flush = false; |
2259 | } | |
b1a36821 | 2260 | |
60c8aec6 | 2261 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2262 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2263 | mmu_pages_clear_parents(&parents); |
2264 | } | |
50c9e6f3 PB |
2265 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2266 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2267 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2268 | flush = false; | |
2269 | } | |
60c8aec6 | 2270 | } |
50c9e6f3 PB |
2271 | |
2272 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2273 | } |
2274 | ||
a30f47cb XG |
2275 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2276 | { | |
e5691a81 | 2277 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2278 | } |
2279 | ||
2280 | static void clear_sp_write_flooding_count(u64 *spte) | |
2281 | { | |
2282 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2283 | ||
2284 | __clear_sp_write_flooding_count(sp); | |
2285 | } | |
2286 | ||
cea0f0e7 AK |
2287 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2288 | gfn_t gfn, | |
2289 | gva_t gaddr, | |
2290 | unsigned level, | |
f6e2c02b | 2291 | int direct, |
bb11c6c9 | 2292 | unsigned access) |
cea0f0e7 AK |
2293 | { |
2294 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2295 | unsigned quadrant; |
9f1a122f | 2296 | struct kvm_mmu_page *sp; |
9f1a122f | 2297 | bool need_sync = false; |
2a74003a | 2298 | bool flush = false; |
f3414bc7 | 2299 | int collisions = 0; |
2a74003a | 2300 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2301 | |
a770f6f2 | 2302 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 2303 | role.level = level; |
f6e2c02b | 2304 | role.direct = direct; |
84b0c8c6 | 2305 | if (role.direct) |
5b7e0102 | 2306 | role.cr4_pae = 0; |
41074d07 | 2307 | role.access = access; |
c5a78f2b JR |
2308 | if (!vcpu->arch.mmu.direct_map |
2309 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2310 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2311 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2312 | role.quadrant = quadrant; | |
2313 | } | |
f3414bc7 DM |
2314 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2315 | if (sp->gfn != gfn) { | |
2316 | collisions++; | |
2317 | continue; | |
2318 | } | |
2319 | ||
7ae680eb XG |
2320 | if (!need_sync && sp->unsync) |
2321 | need_sync = true; | |
4731d4c7 | 2322 | |
7ae680eb XG |
2323 | if (sp->role.word != role.word) |
2324 | continue; | |
4731d4c7 | 2325 | |
2a74003a PB |
2326 | if (sp->unsync) { |
2327 | /* The page is good, but __kvm_sync_page might still end | |
2328 | * up zapping it. If so, break in order to rebuild it. | |
2329 | */ | |
2330 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2331 | break; | |
2332 | ||
2333 | WARN_ON(!list_empty(&invalid_list)); | |
2334 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2335 | } | |
e02aa901 | 2336 | |
98bba238 | 2337 | if (sp->unsync_children) |
a8eeb04a | 2338 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2339 | |
a30f47cb | 2340 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2341 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2342 | goto out; |
7ae680eb | 2343 | } |
47005792 | 2344 | |
dfc5aa00 | 2345 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2346 | |
2347 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2348 | ||
4db35314 AK |
2349 | sp->gfn = gfn; |
2350 | sp->role = role; | |
7ae680eb XG |
2351 | hlist_add_head(&sp->hash_link, |
2352 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2353 | if (!direct) { |
56ca57f9 XG |
2354 | /* |
2355 | * we should do write protection before syncing pages | |
2356 | * otherwise the content of the synced shadow page may | |
2357 | * be inconsistent with guest page table. | |
2358 | */ | |
2359 | account_shadowed(vcpu->kvm, sp); | |
2360 | if (level == PT_PAGE_TABLE_LEVEL && | |
2361 | rmap_write_protect(vcpu, gfn)) | |
b1a36821 | 2362 | kvm_flush_remote_tlbs(vcpu->kvm); |
9f1a122f | 2363 | |
9f1a122f | 2364 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2365 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2366 | } |
5304b8d3 | 2367 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2368 | clear_page(sp->spt); |
f691fe1d | 2369 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2370 | |
2371 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2372 | out: |
2373 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2374 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2375 | return sp; |
cea0f0e7 AK |
2376 | } |
2377 | ||
2d11123a AK |
2378 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2379 | struct kvm_vcpu *vcpu, u64 addr) | |
2380 | { | |
2381 | iterator->addr = addr; | |
2382 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
2383 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
2384 | |
2385 | if (iterator->level == PT64_ROOT_LEVEL && | |
2386 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
2387 | !vcpu->arch.mmu.direct_map) | |
2388 | --iterator->level; | |
2389 | ||
2d11123a AK |
2390 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2391 | iterator->shadow_addr | |
2392 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2393 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2394 | --iterator->level; | |
2395 | if (!iterator->shadow_addr) | |
2396 | iterator->level = 0; | |
2397 | } | |
2398 | } | |
2399 | ||
2400 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2401 | { | |
2402 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2403 | return false; | |
4d88954d | 2404 | |
2d11123a AK |
2405 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2406 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2407 | return true; | |
2408 | } | |
2409 | ||
c2a2ac2b XG |
2410 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2411 | u64 spte) | |
2d11123a | 2412 | { |
c2a2ac2b | 2413 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2414 | iterator->level = 0; |
2415 | return; | |
2416 | } | |
2417 | ||
c2a2ac2b | 2418 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2419 | --iterator->level; |
2420 | } | |
2421 | ||
c2a2ac2b XG |
2422 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2423 | { | |
2424 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2425 | } | |
2426 | ||
98bba238 TY |
2427 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2428 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2429 | { |
2430 | u64 spte; | |
2431 | ||
ffb128c8 | 2432 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2433 | |
ffb128c8 | 2434 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
ac8d57e5 PF |
2435 | shadow_user_mask | shadow_x_mask; |
2436 | ||
2437 | if (sp_ad_disabled(sp)) | |
2438 | spte |= shadow_acc_track_value; | |
2439 | else | |
2440 | spte |= shadow_accessed_mask; | |
24db2734 | 2441 | |
1df9f2dc | 2442 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2443 | |
2444 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2445 | ||
2446 | if (sp->unsync_children || sp->unsync) | |
2447 | mark_unsync(sptep); | |
32ef26a3 AK |
2448 | } |
2449 | ||
a357bd22 AK |
2450 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2451 | unsigned direct_access) | |
2452 | { | |
2453 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2454 | struct kvm_mmu_page *child; | |
2455 | ||
2456 | /* | |
2457 | * For the direct sp, if the guest pte's dirty bit | |
2458 | * changed form clean to dirty, it will corrupt the | |
2459 | * sp's access: allow writable in the read-only sp, | |
2460 | * so we should update the spte at this point to get | |
2461 | * a new sp with the correct access. | |
2462 | */ | |
2463 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2464 | if (child->role.access == direct_access) | |
2465 | return; | |
2466 | ||
bcdd9a93 | 2467 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2468 | kvm_flush_remote_tlbs(vcpu->kvm); |
2469 | } | |
2470 | } | |
2471 | ||
505aef8f | 2472 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2473 | u64 *spte) |
2474 | { | |
2475 | u64 pte; | |
2476 | struct kvm_mmu_page *child; | |
2477 | ||
2478 | pte = *spte; | |
2479 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2480 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2481 | drop_spte(kvm, spte); |
505aef8f XG |
2482 | if (is_large_pte(pte)) |
2483 | --kvm->stat.lpages; | |
2484 | } else { | |
38e3b2b2 | 2485 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2486 | drop_parent_pte(child, spte); |
38e3b2b2 | 2487 | } |
505aef8f XG |
2488 | return true; |
2489 | } | |
2490 | ||
2491 | if (is_mmio_spte(pte)) | |
ce88decf | 2492 | mmu_spte_clear_no_track(spte); |
c3707958 | 2493 | |
505aef8f | 2494 | return false; |
38e3b2b2 XG |
2495 | } |
2496 | ||
90cb0529 | 2497 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2498 | struct kvm_mmu_page *sp) |
a436036b | 2499 | { |
697fe2e2 | 2500 | unsigned i; |
697fe2e2 | 2501 | |
38e3b2b2 XG |
2502 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2503 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2504 | } |
2505 | ||
31aa2b44 | 2506 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2507 | { |
1e3f42f0 TY |
2508 | u64 *sptep; |
2509 | struct rmap_iterator iter; | |
a436036b | 2510 | |
018aabb5 | 2511 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2512 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2513 | } |
2514 | ||
60c8aec6 | 2515 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2516 | struct kvm_mmu_page *parent, |
2517 | struct list_head *invalid_list) | |
4731d4c7 | 2518 | { |
60c8aec6 MT |
2519 | int i, zapped = 0; |
2520 | struct mmu_page_path parents; | |
2521 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2522 | |
60c8aec6 | 2523 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2524 | return 0; |
60c8aec6 | 2525 | |
60c8aec6 MT |
2526 | while (mmu_unsync_walk(parent, &pages)) { |
2527 | struct kvm_mmu_page *sp; | |
2528 | ||
2529 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2530 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2531 | mmu_pages_clear_parents(&parents); |
77662e00 | 2532 | zapped++; |
60c8aec6 | 2533 | } |
60c8aec6 MT |
2534 | } |
2535 | ||
2536 | return zapped; | |
4731d4c7 MT |
2537 | } |
2538 | ||
7775834a XG |
2539 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2540 | struct list_head *invalid_list) | |
31aa2b44 | 2541 | { |
4731d4c7 | 2542 | int ret; |
f691fe1d | 2543 | |
7775834a | 2544 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2545 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2546 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2547 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2548 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2549 | |
f6e2c02b | 2550 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2551 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2552 | |
4731d4c7 MT |
2553 | if (sp->unsync) |
2554 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2555 | if (!sp->root_count) { |
54a4f023 GJ |
2556 | /* Count self */ |
2557 | ret++; | |
7775834a | 2558 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2559 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2560 | } else { |
5b5c6a5a | 2561 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2562 | |
2563 | /* | |
2564 | * The obsolete pages can not be used on any vcpus. | |
2565 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2566 | */ | |
2567 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2568 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2569 | } |
7775834a XG |
2570 | |
2571 | sp->role.invalid = 1; | |
4731d4c7 | 2572 | return ret; |
a436036b AK |
2573 | } |
2574 | ||
7775834a XG |
2575 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2576 | struct list_head *invalid_list) | |
2577 | { | |
945315b9 | 2578 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2579 | |
2580 | if (list_empty(invalid_list)) | |
2581 | return; | |
2582 | ||
c142786c | 2583 | /* |
9753f529 LT |
2584 | * We need to make sure everyone sees our modifications to |
2585 | * the page tables and see changes to vcpu->mode here. The barrier | |
2586 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2587 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2588 | * | |
2589 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2590 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2591 | */ |
2592 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2593 | |
945315b9 | 2594 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2595 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2596 | kvm_mmu_free_page(sp); |
945315b9 | 2597 | } |
7775834a XG |
2598 | } |
2599 | ||
5da59607 TY |
2600 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2601 | struct list_head *invalid_list) | |
2602 | { | |
2603 | struct kvm_mmu_page *sp; | |
2604 | ||
2605 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2606 | return false; | |
2607 | ||
d74c0e6b GT |
2608 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2609 | struct kvm_mmu_page, link); | |
5da59607 TY |
2610 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
2611 | ||
2612 | return true; | |
2613 | } | |
2614 | ||
82ce2c96 IE |
2615 | /* |
2616 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2617 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2618 | */ |
49d5ca26 | 2619 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2620 | { |
d98ba053 | 2621 | LIST_HEAD(invalid_list); |
82ce2c96 | 2622 | |
b34cb590 TY |
2623 | spin_lock(&kvm->mmu_lock); |
2624 | ||
49d5ca26 | 2625 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2626 | /* Need to free some mmu pages to achieve the goal. */ |
2627 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2628 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2629 | break; | |
82ce2c96 | 2630 | |
aa6bd187 | 2631 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2632 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2633 | } |
82ce2c96 | 2634 | |
49d5ca26 | 2635 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2636 | |
2637 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2638 | } |
2639 | ||
1cb3f3ae | 2640 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2641 | { |
4db35314 | 2642 | struct kvm_mmu_page *sp; |
d98ba053 | 2643 | LIST_HEAD(invalid_list); |
a436036b AK |
2644 | int r; |
2645 | ||
9ad17b10 | 2646 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2647 | r = 0; |
1cb3f3ae | 2648 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2649 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2650 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2651 | sp->role.word); |
2652 | r = 1; | |
f41d335a | 2653 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2654 | } |
d98ba053 | 2655 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2656 | spin_unlock(&kvm->mmu_lock); |
2657 | ||
a436036b | 2658 | return r; |
cea0f0e7 | 2659 | } |
1cb3f3ae | 2660 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2661 | |
5c520e90 | 2662 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2663 | { |
2664 | trace_kvm_mmu_unsync_page(sp); | |
2665 | ++vcpu->kvm->stat.mmu_unsync; | |
2666 | sp->unsync = 1; | |
2667 | ||
2668 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2669 | } |
2670 | ||
3d0c27ad XG |
2671 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2672 | bool can_unsync) | |
4731d4c7 | 2673 | { |
5c520e90 | 2674 | struct kvm_mmu_page *sp; |
4731d4c7 | 2675 | |
3d0c27ad XG |
2676 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2677 | return true; | |
9cf5cf5a | 2678 | |
5c520e90 | 2679 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2680 | if (!can_unsync) |
3d0c27ad | 2681 | return true; |
36a2e677 | 2682 | |
5c520e90 XG |
2683 | if (sp->unsync) |
2684 | continue; | |
9cf5cf5a | 2685 | |
5c520e90 XG |
2686 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2687 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2688 | } |
3d0c27ad XG |
2689 | |
2690 | return false; | |
4731d4c7 MT |
2691 | } |
2692 | ||
ba049e93 | 2693 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2694 | { |
2695 | if (pfn_valid(pfn)) | |
2696 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)); | |
2697 | ||
2698 | return true; | |
2699 | } | |
2700 | ||
d555c333 | 2701 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2702 | unsigned pte_access, int level, |
ba049e93 | 2703 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2704 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2705 | { |
ffb128c8 | 2706 | u64 spte = 0; |
1e73f9dd | 2707 | int ret = 0; |
ac8d57e5 | 2708 | struct kvm_mmu_page *sp; |
64d4d521 | 2709 | |
54bf36aa | 2710 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2711 | return 0; |
2712 | ||
ac8d57e5 PF |
2713 | sp = page_header(__pa(sptep)); |
2714 | if (sp_ad_disabled(sp)) | |
2715 | spte |= shadow_acc_track_value; | |
2716 | ||
d95c5568 BD |
2717 | /* |
2718 | * For the EPT case, shadow_present_mask is 0 if hardware | |
2719 | * supports exec-only page table entries. In that case, | |
2720 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
2721 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
2722 | */ | |
ffb128c8 | 2723 | spte |= shadow_present_mask; |
947da538 | 2724 | if (!speculative) |
ac8d57e5 | 2725 | spte |= spte_shadow_accessed_mask(spte); |
640d9b0d | 2726 | |
7b52345e SY |
2727 | if (pte_access & ACC_EXEC_MASK) |
2728 | spte |= shadow_x_mask; | |
2729 | else | |
2730 | spte |= shadow_nx_mask; | |
49fde340 | 2731 | |
1c4f1fd6 | 2732 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2733 | spte |= shadow_user_mask; |
49fde340 | 2734 | |
852e3c19 | 2735 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2736 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2737 | if (tdp_enabled) |
4b12f0de | 2738 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2739 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2740 | |
9bdbba13 | 2741 | if (host_writable) |
1403283a | 2742 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2743 | else |
2744 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2745 | |
35149e21 | 2746 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2747 | |
c2288505 | 2748 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2749 | |
c2193463 | 2750 | /* |
7751babd XG |
2751 | * Other vcpu creates new sp in the window between |
2752 | * mapping_level() and acquiring mmu-lock. We can | |
2753 | * allow guest to retry the access, the mapping can | |
2754 | * be fixed if guest refault. | |
c2193463 | 2755 | */ |
852e3c19 | 2756 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2757 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2758 | goto done; |
38187c83 | 2759 | |
49fde340 | 2760 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2761 | |
ecc5589f MT |
2762 | /* |
2763 | * Optimization: for pte sync, if spte was writable the hash | |
2764 | * lookup is unnecessary (and expensive). Write protection | |
2765 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2766 | * Same reasoning can be applied to dirty page accounting. | |
2767 | */ | |
8dae4445 | 2768 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2769 | goto set_pte; |
2770 | ||
4731d4c7 | 2771 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2772 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2773 | __func__, gfn); |
1e73f9dd | 2774 | ret = 1; |
1c4f1fd6 | 2775 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2776 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2777 | } |
2778 | } | |
2779 | ||
9b51a630 | 2780 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2781 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
ac8d57e5 | 2782 | spte |= spte_shadow_dirty_mask(spte); |
9b51a630 | 2783 | } |
1c4f1fd6 | 2784 | |
f160c7b7 JS |
2785 | if (speculative) |
2786 | spte = mark_spte_for_access_track(spte); | |
2787 | ||
38187c83 | 2788 | set_pte: |
6e7d0354 | 2789 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2790 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2791 | done: |
1e73f9dd MT |
2792 | return ret; |
2793 | } | |
2794 | ||
029499b4 | 2795 | static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
ba049e93 | 2796 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, |
029499b4 | 2797 | bool speculative, bool host_writable) |
1e73f9dd MT |
2798 | { |
2799 | int was_rmapped = 0; | |
53a27b39 | 2800 | int rmap_count; |
029499b4 | 2801 | bool emulate = false; |
1e73f9dd | 2802 | |
f7616203 XG |
2803 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2804 | *sptep, write_fault, gfn); | |
1e73f9dd | 2805 | |
afd28fe1 | 2806 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2807 | /* |
2808 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2809 | * the parent of the now unreachable PTE. | |
2810 | */ | |
852e3c19 JR |
2811 | if (level > PT_PAGE_TABLE_LEVEL && |
2812 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2813 | struct kvm_mmu_page *child; |
d555c333 | 2814 | u64 pte = *sptep; |
1e73f9dd MT |
2815 | |
2816 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2817 | drop_parent_pte(child, sptep); |
3be2264b | 2818 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2819 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2820 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2821 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2822 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2823 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2824 | } else |
2825 | was_rmapped = 1; | |
1e73f9dd | 2826 | } |
852e3c19 | 2827 | |
c2288505 XG |
2828 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2829 | true, host_writable)) { | |
1e73f9dd | 2830 | if (write_fault) |
029499b4 | 2831 | emulate = true; |
77c3913b | 2832 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 2833 | } |
1e73f9dd | 2834 | |
029499b4 TY |
2835 | if (unlikely(is_mmio_spte(*sptep))) |
2836 | emulate = true; | |
ce88decf | 2837 | |
d555c333 | 2838 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2839 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2840 | is_large_pte(*sptep)? "2MB" : "4kB", |
f160c7b7 | 2841 | *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn, |
a205bc19 | 2842 | *sptep, sptep); |
d555c333 | 2843 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2844 | ++vcpu->kvm->stat.lpages; |
2845 | ||
ffb61bb3 | 2846 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2847 | if (!was_rmapped) { |
2848 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2849 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2850 | rmap_recycle(vcpu, sptep, gfn); | |
2851 | } | |
1c4f1fd6 | 2852 | } |
cb9aaa30 | 2853 | |
f3ac1a4b | 2854 | kvm_release_pfn_clean(pfn); |
029499b4 TY |
2855 | |
2856 | return emulate; | |
1c4f1fd6 AK |
2857 | } |
2858 | ||
ba049e93 | 2859 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2860 | bool no_dirty_log) |
2861 | { | |
2862 | struct kvm_memory_slot *slot; | |
957ed9ef | 2863 | |
5d163b1c | 2864 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2865 | if (!slot) |
6c8ee57b | 2866 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2867 | |
037d92dc | 2868 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2869 | } |
2870 | ||
2871 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2872 | struct kvm_mmu_page *sp, | |
2873 | u64 *start, u64 *end) | |
2874 | { | |
2875 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2876 | struct kvm_memory_slot *slot; |
957ed9ef XG |
2877 | unsigned access = sp->role.access; |
2878 | int i, ret; | |
2879 | gfn_t gfn; | |
2880 | ||
2881 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2882 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2883 | if (!slot) | |
957ed9ef XG |
2884 | return -1; |
2885 | ||
d9ef13c2 | 2886 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2887 | if (ret <= 0) |
2888 | return -1; | |
2889 | ||
2890 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
2891 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
2892 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
2893 | |
2894 | return 0; | |
2895 | } | |
2896 | ||
2897 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2898 | struct kvm_mmu_page *sp, u64 *sptep) | |
2899 | { | |
2900 | u64 *spte, *start = NULL; | |
2901 | int i; | |
2902 | ||
2903 | WARN_ON(!sp->role.direct); | |
2904 | ||
2905 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2906 | spte = sp->spt + i; | |
2907 | ||
2908 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2909 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2910 | if (!start) |
2911 | continue; | |
2912 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2913 | break; | |
2914 | start = NULL; | |
2915 | } else if (!start) | |
2916 | start = spte; | |
2917 | } | |
2918 | } | |
2919 | ||
2920 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2921 | { | |
2922 | struct kvm_mmu_page *sp; | |
2923 | ||
ac8d57e5 PF |
2924 | sp = page_header(__pa(sptep)); |
2925 | ||
957ed9ef | 2926 | /* |
ac8d57e5 PF |
2927 | * Without accessed bits, there's no way to distinguish between |
2928 | * actually accessed translations and prefetched, so disable pte | |
2929 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2930 | */ |
ac8d57e5 | 2931 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2932 | return; |
2933 | ||
957ed9ef XG |
2934 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
2935 | return; | |
2936 | ||
2937 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2938 | } | |
2939 | ||
7ee0e5b2 | 2940 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 2941 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 2942 | { |
9f652d21 | 2943 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2944 | struct kvm_mmu_page *sp; |
b90a0e6c | 2945 | int emulate = 0; |
140754bc | 2946 | gfn_t pseudo_gfn; |
6aa8b732 | 2947 | |
989c6b34 MT |
2948 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2949 | return 0; | |
2950 | ||
9f652d21 | 2951 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2952 | if (iterator.level == level) { |
029499b4 TY |
2953 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
2954 | write, level, gfn, pfn, prefault, | |
2955 | map_writable); | |
957ed9ef | 2956 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2957 | ++vcpu->stat.pf_fixed; |
2958 | break; | |
6aa8b732 AK |
2959 | } |
2960 | ||
404381c5 | 2961 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 2962 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2963 | u64 base_addr = iterator.addr; |
2964 | ||
2965 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2966 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 2967 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 2968 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 2969 | |
98bba238 | 2970 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
2971 | } |
2972 | } | |
b90a0e6c | 2973 | return emulate; |
6aa8b732 AK |
2974 | } |
2975 | ||
77db5cbd | 2976 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2977 | { |
77db5cbd HY |
2978 | siginfo_t info; |
2979 | ||
2980 | info.si_signo = SIGBUS; | |
2981 | info.si_errno = 0; | |
2982 | info.si_code = BUS_MCEERR_AR; | |
2983 | info.si_addr = (void __user *)address; | |
2984 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2985 | |
77db5cbd | 2986 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2987 | } |
2988 | ||
ba049e93 | 2989 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2990 | { |
4d8b81ab XG |
2991 | /* |
2992 | * Do not cache the mmio info caused by writing the readonly gfn | |
2993 | * into the spte otherwise read access on readonly gfn also can | |
2994 | * caused mmio page fault and treat it as mmio access. | |
2995 | * Return 1 to tell kvm to emulate it. | |
2996 | */ | |
2997 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2998 | return 1; | |
2999 | ||
e6c1502b | 3000 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3001 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
bf998156 | 3002 | return 0; |
d7c55201 | 3003 | } |
edba23e5 | 3004 | |
d7c55201 | 3005 | return -EFAULT; |
bf998156 HY |
3006 | } |
3007 | ||
936a5fe6 | 3008 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
3009 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
3010 | int *levelp) | |
936a5fe6 | 3011 | { |
ba049e93 | 3012 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
3013 | gfn_t gfn = *gfnp; |
3014 | int level = *levelp; | |
3015 | ||
3016 | /* | |
3017 | * Check if it's a transparent hugepage. If this would be an | |
3018 | * hugetlbfs page, level wouldn't be set to | |
3019 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
3020 | * here. | |
3021 | */ | |
bf4bea8e | 3022 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 | 3023 | level == PT_PAGE_TABLE_LEVEL && |
127393fb | 3024 | PageTransCompoundMap(pfn_to_page(pfn)) && |
92f94f1e | 3025 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
3026 | unsigned long mask; |
3027 | /* | |
3028 | * mmu_notifier_retry was successful and we hold the | |
3029 | * mmu_lock here, so the pmd can't become splitting | |
3030 | * from under us, and in turn | |
3031 | * __split_huge_page_refcount() can't run from under | |
3032 | * us and we can safely transfer the refcount from | |
3033 | * PG_tail to PG_head as we switch the pfn to tail to | |
3034 | * head. | |
3035 | */ | |
3036 | *levelp = level = PT_DIRECTORY_LEVEL; | |
3037 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
3038 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
3039 | if (pfn & mask) { | |
3040 | gfn &= ~mask; | |
3041 | *gfnp = gfn; | |
3042 | kvm_release_pfn_clean(pfn); | |
3043 | pfn &= ~mask; | |
c3586667 | 3044 | kvm_get_pfn(pfn); |
936a5fe6 AA |
3045 | *pfnp = pfn; |
3046 | } | |
3047 | } | |
3048 | } | |
3049 | ||
d7c55201 | 3050 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 3051 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 3052 | { |
d7c55201 | 3053 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3054 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3055 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3056 | return true; |
d7c55201 XG |
3057 | } |
3058 | ||
ce88decf | 3059 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 3060 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 3061 | |
798e88b3 | 3062 | return false; |
d7c55201 XG |
3063 | } |
3064 | ||
e5552fd2 | 3065 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3066 | { |
1c118b82 XG |
3067 | /* |
3068 | * Do not fix the mmio spte with invalid generation number which | |
3069 | * need to be updated by slow page fault path. | |
3070 | */ | |
3071 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3072 | return false; | |
3073 | ||
f160c7b7 JS |
3074 | /* See if the page fault is due to an NX violation */ |
3075 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3076 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3077 | return false; | |
3078 | ||
c7ba5b48 | 3079 | /* |
f160c7b7 JS |
3080 | * #PF can be fast if: |
3081 | * 1. The shadow page table entry is not present, which could mean that | |
3082 | * the fault is potentially caused by access tracking (if enabled). | |
3083 | * 2. The shadow page table entry is present and the fault | |
3084 | * is caused by write-protect, that means we just need change the W | |
3085 | * bit of the spte which can be done out of mmu-lock. | |
3086 | * | |
3087 | * However, if access tracking is disabled we know that a non-present | |
3088 | * page must be a genuine page fault where we have to create a new SPTE. | |
3089 | * So, if access tracking is disabled, we return true only for write | |
3090 | * accesses to a present page. | |
c7ba5b48 | 3091 | */ |
c7ba5b48 | 3092 | |
f160c7b7 JS |
3093 | return shadow_acc_track_mask != 0 || |
3094 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3095 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3096 | } |
3097 | ||
97dceba2 JS |
3098 | /* |
3099 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3100 | * someone else modified the SPTE from its original value. | |
3101 | */ | |
c7ba5b48 | 3102 | static bool |
92a476cb | 3103 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3104 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3105 | { |
c7ba5b48 XG |
3106 | gfn_t gfn; |
3107 | ||
3108 | WARN_ON(!sp->role.direct); | |
3109 | ||
9b51a630 KH |
3110 | /* |
3111 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3112 | * order to eliminate unnecessary PML logging. See comments in | |
3113 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3114 | * enabled, so we do not do this. This might result in the same GPA | |
3115 | * to be logged in PML buffer again when the write really happens, and | |
3116 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3117 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3118 | * so non-PML cases won't be impacted. | |
3119 | * | |
3120 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3121 | */ | |
f160c7b7 | 3122 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3123 | return false; |
3124 | ||
d3e328f2 | 3125 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3126 | /* |
3127 | * The gfn of direct spte is stable since it is | |
3128 | * calculated by sp->gfn. | |
3129 | */ | |
3130 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3131 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3132 | } | |
c7ba5b48 XG |
3133 | |
3134 | return true; | |
3135 | } | |
3136 | ||
d3e328f2 JS |
3137 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3138 | { | |
3139 | if (fault_err_code & PFERR_FETCH_MASK) | |
3140 | return is_executable_pte(spte); | |
3141 | ||
3142 | if (fault_err_code & PFERR_WRITE_MASK) | |
3143 | return is_writable_pte(spte); | |
3144 | ||
3145 | /* Fault was on Read access */ | |
3146 | return spte & PT_PRESENT_MASK; | |
3147 | } | |
3148 | ||
c7ba5b48 XG |
3149 | /* |
3150 | * Return value: | |
3151 | * - true: let the vcpu to access on the same address again. | |
3152 | * - false: let the real page fault path to fix it. | |
3153 | */ | |
3154 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
3155 | u32 error_code) | |
3156 | { | |
3157 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3158 | struct kvm_mmu_page *sp; |
97dceba2 | 3159 | bool fault_handled = false; |
c7ba5b48 | 3160 | u64 spte = 0ull; |
97dceba2 | 3161 | uint retry_count = 0; |
c7ba5b48 | 3162 | |
37f6a4e2 MT |
3163 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3164 | return false; | |
3165 | ||
e5552fd2 | 3166 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3167 | return false; |
3168 | ||
3169 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3170 | |
97dceba2 | 3171 | do { |
d3e328f2 | 3172 | u64 new_spte; |
c7ba5b48 | 3173 | |
d162f30a JS |
3174 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) |
3175 | if (!is_shadow_present_pte(spte) || | |
3176 | iterator.level < level) | |
3177 | break; | |
3178 | ||
97dceba2 JS |
3179 | sp = page_header(__pa(iterator.sptep)); |
3180 | if (!is_last_spte(spte, sp->role.level)) | |
3181 | break; | |
c7ba5b48 | 3182 | |
97dceba2 | 3183 | /* |
f160c7b7 JS |
3184 | * Check whether the memory access that caused the fault would |
3185 | * still cause it if it were to be performed right now. If not, | |
3186 | * then this is a spurious fault caused by TLB lazily flushed, | |
3187 | * or some other CPU has already fixed the PTE after the | |
3188 | * current CPU took the fault. | |
97dceba2 JS |
3189 | * |
3190 | * Need not check the access of upper level table entries since | |
3191 | * they are always ACC_ALL. | |
3192 | */ | |
d3e328f2 JS |
3193 | if (is_access_allowed(error_code, spte)) { |
3194 | fault_handled = true; | |
3195 | break; | |
3196 | } | |
f160c7b7 | 3197 | |
d3e328f2 JS |
3198 | new_spte = spte; |
3199 | ||
3200 | if (is_access_track_spte(spte)) | |
3201 | new_spte = restore_acc_track_spte(new_spte); | |
3202 | ||
3203 | /* | |
3204 | * Currently, to simplify the code, write-protection can | |
3205 | * be removed in the fast path only if the SPTE was | |
3206 | * write-protected for dirty-logging or access tracking. | |
3207 | */ | |
3208 | if ((error_code & PFERR_WRITE_MASK) && | |
3209 | spte_can_locklessly_be_made_writable(spte)) | |
3210 | { | |
3211 | new_spte |= PT_WRITABLE_MASK; | |
f160c7b7 JS |
3212 | |
3213 | /* | |
d3e328f2 JS |
3214 | * Do not fix write-permission on the large spte. Since |
3215 | * we only dirty the first page into the dirty-bitmap in | |
3216 | * fast_pf_fix_direct_spte(), other pages are missed | |
3217 | * if its slot has dirty logging enabled. | |
3218 | * | |
3219 | * Instead, we let the slow page fault path create a | |
3220 | * normal spte to fix the access. | |
3221 | * | |
3222 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3223 | */ |
d3e328f2 | 3224 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3225 | break; |
97dceba2 | 3226 | } |
c7ba5b48 | 3227 | |
f160c7b7 | 3228 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3229 | if (new_spte == spte || |
3230 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3231 | break; |
3232 | ||
3233 | /* | |
3234 | * Currently, fast page fault only works for direct mapping | |
3235 | * since the gfn is not stable for indirect shadow page. See | |
3236 | * Documentation/virtual/kvm/locking.txt to get more detail. | |
3237 | */ | |
3238 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3239 | iterator.sptep, spte, |
d3e328f2 | 3240 | new_spte); |
97dceba2 JS |
3241 | if (fault_handled) |
3242 | break; | |
3243 | ||
3244 | if (++retry_count > 4) { | |
3245 | printk_once(KERN_WARNING | |
3246 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3247 | break; | |
3248 | } | |
3249 | ||
97dceba2 | 3250 | } while (true); |
c126d94f | 3251 | |
a72faf25 | 3252 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
97dceba2 | 3253 | spte, fault_handled); |
c7ba5b48 XG |
3254 | walk_shadow_page_lockless_end(vcpu); |
3255 | ||
97dceba2 | 3256 | return fault_handled; |
c7ba5b48 XG |
3257 | } |
3258 | ||
78b2c54a | 3259 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3260 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 3261 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3262 | |
c7ba5b48 XG |
3263 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3264 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3265 | { |
3266 | int r; | |
852e3c19 | 3267 | int level; |
fd136902 | 3268 | bool force_pt_level = false; |
ba049e93 | 3269 | kvm_pfn_t pfn; |
e930bffe | 3270 | unsigned long mmu_seq; |
c7ba5b48 | 3271 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3272 | |
fd136902 | 3273 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3274 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3275 | /* |
3276 | * This path builds a PAE pagetable - so we can map | |
3277 | * 2mb pages at maximum. Therefore check if the level | |
3278 | * is larger than that. | |
3279 | */ | |
3280 | if (level > PT_DIRECTORY_LEVEL) | |
3281 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3282 | |
936a5fe6 | 3283 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3284 | } |
05da4558 | 3285 | |
c7ba5b48 XG |
3286 | if (fast_page_fault(vcpu, v, level, error_code)) |
3287 | return 0; | |
3288 | ||
e930bffe | 3289 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3290 | smp_rmb(); |
060c2abe | 3291 | |
78b2c54a | 3292 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 3293 | return 0; |
aaee2c94 | 3294 | |
d7c55201 XG |
3295 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3296 | return r; | |
d196e343 | 3297 | |
aaee2c94 | 3298 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3299 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3300 | goto out_unlock; |
450e0b41 | 3301 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3302 | if (likely(!force_pt_level)) |
3303 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3304 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3305 | spin_unlock(&vcpu->kvm->mmu_lock); |
3306 | ||
10589a46 | 3307 | return r; |
e930bffe AA |
3308 | |
3309 | out_unlock: | |
3310 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3311 | kvm_release_pfn_clean(pfn); | |
3312 | return 0; | |
10589a46 MT |
3313 | } |
3314 | ||
3315 | ||
17ac10ad AK |
3316 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
3317 | { | |
3318 | int i; | |
4db35314 | 3319 | struct kvm_mmu_page *sp; |
d98ba053 | 3320 | LIST_HEAD(invalid_list); |
17ac10ad | 3321 | |
ad312c7c | 3322 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 3323 | return; |
35af577a | 3324 | |
81407ca5 JR |
3325 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
3326 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
3327 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 3328 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3329 | |
35af577a | 3330 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
3331 | sp = page_header(root); |
3332 | --sp->root_count; | |
d98ba053 XG |
3333 | if (!sp->root_count && sp->role.invalid) { |
3334 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
3335 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
3336 | } | |
aaee2c94 | 3337 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 3338 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3339 | return; |
3340 | } | |
35af577a GN |
3341 | |
3342 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3343 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3344 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3345 | |
417726a3 | 3346 | if (root) { |
417726a3 | 3347 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
3348 | sp = page_header(root); |
3349 | --sp->root_count; | |
2e53d63a | 3350 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
3351 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
3352 | &invalid_list); | |
417726a3 | 3353 | } |
ad312c7c | 3354 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3355 | } |
d98ba053 | 3356 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3357 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3358 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3359 | } |
3360 | ||
8986ecc0 MT |
3361 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3362 | { | |
3363 | int ret = 0; | |
3364 | ||
3365 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3366 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3367 | ret = 1; |
3368 | } | |
3369 | ||
3370 | return ret; | |
3371 | } | |
3372 | ||
651dd37a JR |
3373 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3374 | { | |
3375 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3376 | unsigned i; |
651dd37a JR |
3377 | |
3378 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3379 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3380 | make_mmu_pages_available(vcpu); |
bb11c6c9 | 3381 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3382 | ++sp->root_count; |
3383 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3384 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3385 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3386 | for (i = 0; i < 4; ++i) { | |
3387 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3388 | ||
fa4a2c08 | 3389 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3390 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3391 | make_mmu_pages_available(vcpu); |
649497d1 | 3392 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3393 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3394 | root = __pa(sp->spt); |
3395 | ++sp->root_count; | |
3396 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3397 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3398 | } |
6292757f | 3399 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3400 | } else |
3401 | BUG(); | |
3402 | ||
3403 | return 0; | |
3404 | } | |
3405 | ||
3406 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3407 | { |
4db35314 | 3408 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3409 | u64 pdptr, pm_mask; |
3410 | gfn_t root_gfn; | |
3411 | int i; | |
3bb65a22 | 3412 | |
5777ed34 | 3413 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3414 | |
651dd37a JR |
3415 | if (mmu_check_root(vcpu, root_gfn)) |
3416 | return 1; | |
3417 | ||
3418 | /* | |
3419 | * Do we shadow a long mode page table? If so we need to | |
3420 | * write-protect the guests page table root. | |
3421 | */ | |
3422 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3423 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3424 | |
fa4a2c08 | 3425 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3426 | |
8facbbff | 3427 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3428 | make_mmu_pages_available(vcpu); |
651dd37a | 3429 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
bb11c6c9 | 3430 | 0, ACC_ALL); |
4db35314 AK |
3431 | root = __pa(sp->spt); |
3432 | ++sp->root_count; | |
8facbbff | 3433 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3434 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3435 | return 0; |
17ac10ad | 3436 | } |
f87f9288 | 3437 | |
651dd37a JR |
3438 | /* |
3439 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3440 | * or a PAE 3-level page table. In either case we need to be aware that |
3441 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3442 | */ |
81407ca5 JR |
3443 | pm_mask = PT_PRESENT_MASK; |
3444 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3445 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3446 | ||
17ac10ad | 3447 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3448 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3449 | |
fa4a2c08 | 3450 | MMU_WARN_ON(VALID_PAGE(root)); |
ad312c7c | 3451 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3452 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
812f30b2 | 3453 | if (!(pdptr & PT_PRESENT_MASK)) { |
ad312c7c | 3454 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3455 | continue; |
3456 | } | |
6de4f3ad | 3457 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3458 | if (mmu_check_root(vcpu, root_gfn)) |
3459 | return 1; | |
5a7388c2 | 3460 | } |
8facbbff | 3461 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3462 | make_mmu_pages_available(vcpu); |
bb11c6c9 TY |
3463 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3464 | 0, ACC_ALL); | |
4db35314 AK |
3465 | root = __pa(sp->spt); |
3466 | ++sp->root_count; | |
8facbbff AK |
3467 | spin_unlock(&vcpu->kvm->mmu_lock); |
3468 | ||
81407ca5 | 3469 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3470 | } |
6292757f | 3471 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3472 | |
3473 | /* | |
3474 | * If we shadow a 32 bit page table with a long mode page | |
3475 | * table we enter this path. | |
3476 | */ | |
3477 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3478 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3479 | /* | |
3480 | * The additional page necessary for this is only | |
3481 | * allocated on demand. | |
3482 | */ | |
3483 | ||
3484 | u64 *lm_root; | |
3485 | ||
3486 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3487 | if (lm_root == NULL) | |
3488 | return 1; | |
3489 | ||
3490 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3491 | ||
3492 | vcpu->arch.mmu.lm_root = lm_root; | |
3493 | } | |
3494 | ||
3495 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3496 | } | |
3497 | ||
8986ecc0 | 3498 | return 0; |
17ac10ad AK |
3499 | } |
3500 | ||
651dd37a JR |
3501 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3502 | { | |
3503 | if (vcpu->arch.mmu.direct_map) | |
3504 | return mmu_alloc_direct_roots(vcpu); | |
3505 | else | |
3506 | return mmu_alloc_shadow_roots(vcpu); | |
3507 | } | |
3508 | ||
0ba73cda MT |
3509 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3510 | { | |
3511 | int i; | |
3512 | struct kvm_mmu_page *sp; | |
3513 | ||
81407ca5 JR |
3514 | if (vcpu->arch.mmu.direct_map) |
3515 | return; | |
3516 | ||
0ba73cda MT |
3517 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3518 | return; | |
6903074c | 3519 | |
56f17dd3 | 3520 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
0375f7fa | 3521 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3522 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3523 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3524 | sp = page_header(root); | |
3525 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3526 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3527 | return; |
3528 | } | |
3529 | for (i = 0; i < 4; ++i) { | |
3530 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3531 | ||
8986ecc0 | 3532 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3533 | root &= PT64_BASE_ADDR_MASK; |
3534 | sp = page_header(root); | |
3535 | mmu_sync_children(vcpu, sp); | |
3536 | } | |
3537 | } | |
0375f7fa | 3538 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3539 | } |
3540 | ||
3541 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3542 | { | |
3543 | spin_lock(&vcpu->kvm->mmu_lock); | |
3544 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3545 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3546 | } |
bfd0a56b | 3547 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3548 | |
1871c602 | 3549 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3550 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3551 | { |
ab9ae313 AK |
3552 | if (exception) |
3553 | exception->error_code = 0; | |
6aa8b732 AK |
3554 | return vaddr; |
3555 | } | |
3556 | ||
6539e738 | 3557 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3558 | u32 access, |
3559 | struct x86_exception *exception) | |
6539e738 | 3560 | { |
ab9ae313 AK |
3561 | if (exception) |
3562 | exception->error_code = 0; | |
54987b7a | 3563 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3564 | } |
3565 | ||
d625b155 XG |
3566 | static bool |
3567 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3568 | { | |
3569 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3570 | ||
3571 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3572 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3573 | } | |
3574 | ||
3575 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3576 | { | |
3577 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3578 | } | |
3579 | ||
3580 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3581 | { | |
3582 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3583 | } | |
3584 | ||
ded58749 | 3585 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3586 | { |
3587 | if (direct) | |
3588 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3589 | ||
3590 | return vcpu_match_mmio_gva(vcpu, addr); | |
3591 | } | |
3592 | ||
47ab8751 XG |
3593 | /* return true if reserved bit is detected on spte. */ |
3594 | static bool | |
3595 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3596 | { |
3597 | struct kvm_shadow_walk_iterator iterator; | |
47ab8751 XG |
3598 | u64 sptes[PT64_ROOT_LEVEL], spte = 0ull; |
3599 | int root, leaf; | |
3600 | bool reserved = false; | |
ce88decf | 3601 | |
37f6a4e2 | 3602 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
47ab8751 | 3603 | goto exit; |
37f6a4e2 | 3604 | |
ce88decf | 3605 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3606 | |
29ecd660 PB |
3607 | for (shadow_walk_init(&iterator, vcpu, addr), |
3608 | leaf = root = iterator.level; | |
47ab8751 XG |
3609 | shadow_walk_okay(&iterator); |
3610 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3611 | spte = mmu_spte_get_lockless(iterator.sptep); |
3612 | ||
3613 | sptes[leaf - 1] = spte; | |
29ecd660 | 3614 | leaf--; |
47ab8751 | 3615 | |
ce88decf XG |
3616 | if (!is_shadow_present_pte(spte)) |
3617 | break; | |
47ab8751 XG |
3618 | |
3619 | reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, | |
58c95070 | 3620 | iterator.level); |
47ab8751 XG |
3621 | } |
3622 | ||
ce88decf XG |
3623 | walk_shadow_page_lockless_end(vcpu); |
3624 | ||
47ab8751 XG |
3625 | if (reserved) { |
3626 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3627 | __func__, addr); | |
29ecd660 | 3628 | while (root > leaf) { |
47ab8751 XG |
3629 | pr_err("------ spte 0x%llx level %d.\n", |
3630 | sptes[root - 1], root); | |
3631 | root--; | |
3632 | } | |
3633 | } | |
3634 | exit: | |
3635 | *sptep = spte; | |
3636 | return reserved; | |
ce88decf XG |
3637 | } |
3638 | ||
450869d6 | 3639 | int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3640 | { |
3641 | u64 spte; | |
47ab8751 | 3642 | bool reserved; |
ce88decf | 3643 | |
ded58749 | 3644 | if (mmio_info_in_cache(vcpu, addr, direct)) |
b37fbea6 | 3645 | return RET_MMIO_PF_EMULATE; |
ce88decf | 3646 | |
47ab8751 | 3647 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3648 | if (WARN_ON(reserved)) |
47ab8751 | 3649 | return RET_MMIO_PF_BUG; |
ce88decf XG |
3650 | |
3651 | if (is_mmio_spte(spte)) { | |
3652 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3653 | unsigned access = get_mmio_spte_access(spte); | |
3654 | ||
54bf36aa | 3655 | if (!check_mmio_spte(vcpu, spte)) |
f8f55942 XG |
3656 | return RET_MMIO_PF_INVALID; |
3657 | ||
ce88decf XG |
3658 | if (direct) |
3659 | addr = 0; | |
4f022648 XG |
3660 | |
3661 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3662 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
b37fbea6 | 3663 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3664 | } |
3665 | ||
ce88decf XG |
3666 | /* |
3667 | * If the page table is zapped by other cpus, let CPU fault again on | |
3668 | * the address. | |
3669 | */ | |
b37fbea6 | 3670 | return RET_MMIO_PF_RETRY; |
ce88decf | 3671 | } |
450869d6 | 3672 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault); |
ce88decf | 3673 | |
3d0c27ad XG |
3674 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3675 | u32 error_code, gfn_t gfn) | |
3676 | { | |
3677 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3678 | return false; | |
3679 | ||
3680 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3681 | !(error_code & PFERR_WRITE_MASK)) | |
3682 | return false; | |
3683 | ||
3684 | /* | |
3685 | * guest is writing the page which is write tracked which can | |
3686 | * not be fixed by page fault handler. | |
3687 | */ | |
3688 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3689 | return true; | |
3690 | ||
3691 | return false; | |
3692 | } | |
3693 | ||
e5691a81 XG |
3694 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3695 | { | |
3696 | struct kvm_shadow_walk_iterator iterator; | |
3697 | u64 spte; | |
3698 | ||
3699 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3700 | return; | |
3701 | ||
3702 | walk_shadow_page_lockless_begin(vcpu); | |
3703 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3704 | clear_sp_write_flooding_count(iterator.sptep); | |
3705 | if (!is_shadow_present_pte(spte)) | |
3706 | break; | |
3707 | } | |
3708 | walk_shadow_page_lockless_end(vcpu); | |
3709 | } | |
3710 | ||
6aa8b732 | 3711 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3712 | u32 error_code, bool prefault) |
6aa8b732 | 3713 | { |
3d0c27ad | 3714 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3715 | int r; |
6aa8b732 | 3716 | |
b8688d51 | 3717 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3718 | |
3d0c27ad XG |
3719 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3720 | return 1; | |
ce88decf | 3721 | |
e2dec939 AK |
3722 | r = mmu_topup_memory_caches(vcpu); |
3723 | if (r) | |
3724 | return r; | |
714b93da | 3725 | |
fa4a2c08 | 3726 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3727 | |
6aa8b732 | 3728 | |
e833240f | 3729 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3730 | error_code, gfn, prefault); |
6aa8b732 AK |
3731 | } |
3732 | ||
7e1fbeac | 3733 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3734 | { |
3735 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3736 | |
7c90705b | 3737 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3738 | arch.gfn = gfn; |
c4806acd | 3739 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3740 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3741 | |
54bf36aa | 3742 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3743 | } |
3744 | ||
9bc1f09f | 3745 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) |
af585b92 | 3746 | { |
35754c98 | 3747 | if (unlikely(!lapic_in_kernel(vcpu) || |
af585b92 GN |
3748 | kvm_event_needs_reinjection(vcpu))) |
3749 | return false; | |
3750 | ||
9bc1f09f WL |
3751 | if (is_guest_mode(vcpu)) |
3752 | return false; | |
3753 | ||
af585b92 GN |
3754 | return kvm_x86_ops->interrupt_allowed(vcpu); |
3755 | } | |
3756 | ||
78b2c54a | 3757 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3758 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 3759 | { |
3520469d | 3760 | struct kvm_memory_slot *slot; |
af585b92 GN |
3761 | bool async; |
3762 | ||
54bf36aa | 3763 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
3764 | async = false; |
3765 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3766 | if (!async) |
3767 | return false; /* *pfn has correct page already */ | |
3768 | ||
9bc1f09f | 3769 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
c9b263d2 | 3770 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3771 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3772 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3773 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3774 | return true; | |
3775 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3776 | return true; | |
3777 | } | |
3778 | ||
3520469d | 3779 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3780 | return false; |
3781 | } | |
3782 | ||
6a39bbc5 XG |
3783 | static bool |
3784 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
3785 | { | |
3786 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
3787 | ||
3788 | gfn &= ~(page_num - 1); | |
3789 | ||
3790 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
3791 | } | |
3792 | ||
56028d08 | 3793 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3794 | bool prefault) |
fb72d167 | 3795 | { |
ba049e93 | 3796 | kvm_pfn_t pfn; |
fb72d167 | 3797 | int r; |
852e3c19 | 3798 | int level; |
cd1872f0 | 3799 | bool force_pt_level; |
05da4558 | 3800 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3801 | unsigned long mmu_seq; |
612819c3 MT |
3802 | int write = error_code & PFERR_WRITE_MASK; |
3803 | bool map_writable; | |
fb72d167 | 3804 | |
fa4a2c08 | 3805 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
fb72d167 | 3806 | |
3d0c27ad XG |
3807 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3808 | return 1; | |
ce88decf | 3809 | |
fb72d167 JR |
3810 | r = mmu_topup_memory_caches(vcpu); |
3811 | if (r) | |
3812 | return r; | |
3813 | ||
fd136902 TY |
3814 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
3815 | PT_DIRECTORY_LEVEL); | |
3816 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 3817 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
3818 | if (level > PT_DIRECTORY_LEVEL && |
3819 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
3820 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 3821 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3822 | } |
852e3c19 | 3823 | |
c7ba5b48 XG |
3824 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3825 | return 0; | |
3826 | ||
e930bffe | 3827 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3828 | smp_rmb(); |
af585b92 | 3829 | |
78b2c54a | 3830 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3831 | return 0; |
3832 | ||
d7c55201 XG |
3833 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3834 | return r; | |
3835 | ||
fb72d167 | 3836 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3837 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3838 | goto out_unlock; |
450e0b41 | 3839 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3840 | if (likely(!force_pt_level)) |
3841 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3842 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 3843 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3844 | |
3845 | return r; | |
e930bffe AA |
3846 | |
3847 | out_unlock: | |
3848 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3849 | kvm_release_pfn_clean(pfn); | |
3850 | return 0; | |
fb72d167 JR |
3851 | } |
3852 | ||
8a3c1a33 PB |
3853 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3854 | struct kvm_mmu *context) | |
6aa8b732 | 3855 | { |
6aa8b732 | 3856 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3857 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3858 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3859 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3860 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3861 | context->root_level = 0; |
6aa8b732 | 3862 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3863 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3864 | context->direct_map = true; |
2d48a985 | 3865 | context->nx = false; |
6aa8b732 AK |
3866 | } |
3867 | ||
d8d173da | 3868 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu) |
6aa8b732 | 3869 | { |
cea0f0e7 | 3870 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3871 | } |
3872 | ||
5777ed34 JR |
3873 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3874 | { | |
9f8fe504 | 3875 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3876 | } |
3877 | ||
6389ee94 AK |
3878 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3879 | struct x86_exception *fault) | |
6aa8b732 | 3880 | { |
6389ee94 | 3881 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3882 | } |
3883 | ||
54bf36aa | 3884 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 3885 | unsigned access, int *nr_present) |
ce88decf XG |
3886 | { |
3887 | if (unlikely(is_mmio_spte(*sptep))) { | |
3888 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3889 | mmu_spte_clear_no_track(sptep); | |
3890 | return true; | |
3891 | } | |
3892 | ||
3893 | (*nr_present)++; | |
54bf36aa | 3894 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3895 | return true; |
3896 | } | |
3897 | ||
3898 | return false; | |
3899 | } | |
3900 | ||
6bb69c9b PB |
3901 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
3902 | unsigned level, unsigned gpte) | |
6fd01b71 | 3903 | { |
6bb69c9b PB |
3904 | /* |
3905 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
3906 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
3907 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
3908 | */ | |
3909 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
6fd01b71 | 3910 | |
6bb69c9b PB |
3911 | /* |
3912 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
3913 | * If it is clear, there are no large pages at this level, so clear | |
3914 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
3915 | */ | |
3916 | gpte &= level - mmu->last_nonleaf_level; | |
3917 | ||
3918 | return gpte & PT_PAGE_SIZE_MASK; | |
6fd01b71 AK |
3919 | } |
3920 | ||
37406aaa NHE |
3921 | #define PTTYPE_EPT 18 /* arbitrary */ |
3922 | #define PTTYPE PTTYPE_EPT | |
3923 | #include "paging_tmpl.h" | |
3924 | #undef PTTYPE | |
3925 | ||
6aa8b732 AK |
3926 | #define PTTYPE 64 |
3927 | #include "paging_tmpl.h" | |
3928 | #undef PTTYPE | |
3929 | ||
3930 | #define PTTYPE 32 | |
3931 | #include "paging_tmpl.h" | |
3932 | #undef PTTYPE | |
3933 | ||
6dc98b86 XG |
3934 | static void |
3935 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
3936 | struct rsvd_bits_validate *rsvd_check, | |
3937 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 3938 | bool pse, bool amd) |
82725b20 | 3939 | { |
82725b20 | 3940 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 3941 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 3942 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 3943 | |
a0a64f50 | 3944 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 3945 | |
6dc98b86 | 3946 | if (!nx) |
82725b20 | 3947 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 3948 | if (!gbpages) |
5f7dde7b | 3949 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
3950 | |
3951 | /* | |
3952 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
3953 | * leaf entries) on AMD CPUs only. | |
3954 | */ | |
6fec2144 | 3955 | if (amd) |
a0c0feb5 PB |
3956 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
3957 | ||
6dc98b86 | 3958 | switch (level) { |
82725b20 DE |
3959 | case PT32_ROOT_LEVEL: |
3960 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
3961 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
3962 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
3963 | rsvd_check->rsvd_bits_mask[1][0] = | |
3964 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 3965 | |
6dc98b86 | 3966 | if (!pse) { |
a0a64f50 | 3967 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
3968 | break; |
3969 | } | |
3970 | ||
82725b20 DE |
3971 | if (is_cpuid_PSE36()) |
3972 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 3973 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
3974 | else |
3975 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 3976 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
3977 | break; |
3978 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 3979 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 3980 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 3981 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 3982 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3983 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 3984 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 3985 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 3986 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
3987 | rsvd_bits(maxphyaddr, 62) | |
3988 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3989 | rsvd_check->rsvd_bits_mask[1][0] = |
3990 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
3991 | break; |
3992 | case PT64_ROOT_LEVEL: | |
a0a64f50 XG |
3993 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
3994 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 3995 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3996 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
3997 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 3998 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3999 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4000 | rsvd_bits(maxphyaddr, 51); | |
4001 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4002 | rsvd_bits(maxphyaddr, 51); | |
4003 | rsvd_check->rsvd_bits_mask[1][3] = | |
4004 | rsvd_check->rsvd_bits_mask[0][3]; | |
4005 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4006 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4007 | rsvd_bits(13, 29); |
a0a64f50 | 4008 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4009 | rsvd_bits(maxphyaddr, 51) | |
4010 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4011 | rsvd_check->rsvd_bits_mask[1][0] = |
4012 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4013 | break; |
4014 | } | |
4015 | } | |
4016 | ||
6dc98b86 XG |
4017 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4018 | struct kvm_mmu *context) | |
4019 | { | |
4020 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4021 | cpuid_maxphyaddr(vcpu), context->root_level, | |
4022 | context->nx, guest_cpuid_has_gbpages(vcpu), | |
6fec2144 | 4023 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
4024 | } |
4025 | ||
81b8eebb XG |
4026 | static void |
4027 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4028 | int maxphyaddr, bool execonly) | |
25d92081 | 4029 | { |
951f9fd7 | 4030 | u64 bad_mt_xwr; |
25d92081 | 4031 | |
a0a64f50 | 4032 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4033 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4034 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4035 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4036 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4037 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4038 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4039 | |
4040 | /* large page */ | |
a0a64f50 XG |
4041 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4042 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4043 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4044 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4045 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4046 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4047 | |
951f9fd7 PB |
4048 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4049 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4050 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4051 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4052 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4053 | if (!execonly) { | |
4054 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4055 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4056 | } |
951f9fd7 | 4057 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4058 | } |
4059 | ||
81b8eebb XG |
4060 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4061 | struct kvm_mmu *context, bool execonly) | |
4062 | { | |
4063 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4064 | cpuid_maxphyaddr(vcpu), execonly); | |
4065 | } | |
4066 | ||
c258b62b XG |
4067 | /* |
4068 | * the page table on host is the shadow page table for the page | |
4069 | * table in guest or amd nested guest, its mmu features completely | |
4070 | * follow the features in guest. | |
4071 | */ | |
4072 | void | |
4073 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4074 | { | |
5f0b8199 PB |
4075 | bool uses_nx = context->nx || context->base_role.smep_andnot_wp; |
4076 | ||
6fec2144 PB |
4077 | /* |
4078 | * Passing "true" to the last argument is okay; it adds a check | |
4079 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4080 | */ | |
c258b62b XG |
4081 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
4082 | boot_cpu_data.x86_phys_bits, | |
5f0b8199 | 4083 | context->shadow_root_level, uses_nx, |
6fec2144 PB |
4084 | guest_cpuid_has_gbpages(vcpu), is_pse(vcpu), |
4085 | true); | |
c258b62b XG |
4086 | } |
4087 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4088 | ||
6fec2144 PB |
4089 | static inline bool boot_cpu_is_amd(void) |
4090 | { | |
4091 | WARN_ON_ONCE(!tdp_enabled); | |
4092 | return shadow_x_mask == 0; | |
4093 | } | |
4094 | ||
c258b62b XG |
4095 | /* |
4096 | * the direct page table on host, use as much mmu features as | |
4097 | * possible, however, kvm currently does not do execution-protection. | |
4098 | */ | |
4099 | static void | |
4100 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4101 | struct kvm_mmu *context) | |
4102 | { | |
6fec2144 | 4103 | if (boot_cpu_is_amd()) |
c258b62b XG |
4104 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
4105 | boot_cpu_data.x86_phys_bits, | |
4106 | context->shadow_root_level, false, | |
b8291adc BP |
4107 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4108 | true, true); | |
c258b62b XG |
4109 | else |
4110 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4111 | boot_cpu_data.x86_phys_bits, | |
4112 | false); | |
4113 | ||
4114 | } | |
4115 | ||
4116 | /* | |
4117 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4118 | * is the shadow page table for intel nested guest. | |
4119 | */ | |
4120 | static void | |
4121 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4122 | struct kvm_mmu *context, bool execonly) | |
4123 | { | |
4124 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4125 | boot_cpu_data.x86_phys_bits, execonly); | |
4126 | } | |
4127 | ||
edc90b7d XG |
4128 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4129 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 AK |
4130 | { |
4131 | unsigned bit, byte, pfec; | |
4132 | u8 map; | |
66386ade | 4133 | bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0; |
97d64b78 | 4134 | |
66386ade | 4135 | cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
97ec8c06 | 4136 | cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
97d64b78 AK |
4137 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
4138 | pfec = byte << 1; | |
4139 | map = 0; | |
4140 | wf = pfec & PFERR_WRITE_MASK; | |
4141 | uf = pfec & PFERR_USER_MASK; | |
4142 | ff = pfec & PFERR_FETCH_MASK; | |
97ec8c06 FW |
4143 | /* |
4144 | * PFERR_RSVD_MASK bit is set in PFEC if the access is not | |
4145 | * subject to SMAP restrictions, and cleared otherwise. The | |
4146 | * bit is only meaningful if the SMAP bit is set in CR4. | |
4147 | */ | |
4148 | smapf = !(pfec & PFERR_RSVD_MASK); | |
97d64b78 AK |
4149 | for (bit = 0; bit < 8; ++bit) { |
4150 | x = bit & ACC_EXEC_MASK; | |
4151 | w = bit & ACC_WRITE_MASK; | |
4152 | u = bit & ACC_USER_MASK; | |
4153 | ||
25d92081 YZ |
4154 | if (!ept) { |
4155 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4156 | x |= !mmu->nx; | |
4157 | /* Allow supervisor writes if !cr0.wp */ | |
4158 | w |= !is_write_protection(vcpu) && !uf; | |
4159 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
66386ade | 4160 | x &= !(cr4_smep && u && !uf); |
97ec8c06 FW |
4161 | |
4162 | /* | |
4163 | * SMAP:kernel-mode data accesses from user-mode | |
4164 | * mappings should fault. A fault is considered | |
4165 | * as a SMAP violation if all of the following | |
4166 | * conditions are ture: | |
4167 | * - X86_CR4_SMAP is set in CR4 | |
9332ef9d | 4168 | * - A user page is accessed |
97ec8c06 FW |
4169 | * - Page fault in kernel mode |
4170 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4171 | * | |
4172 | * Here, we cover the first three conditions. | |
4173 | * The fourth is computed dynamically in | |
4174 | * permission_fault() and is in smapf. | |
4175 | * | |
4176 | * Also, SMAP does not affect instruction | |
4177 | * fetches, add the !ff check here to make it | |
4178 | * clearer. | |
4179 | */ | |
4180 | smap = cr4_smap && u && !uf && !ff; | |
d95c5568 | 4181 | } |
97d64b78 | 4182 | |
97ec8c06 FW |
4183 | fault = (ff && !x) || (uf && !u) || (wf && !w) || |
4184 | (smapf && smap); | |
97d64b78 AK |
4185 | map |= fault << bit; |
4186 | } | |
4187 | mmu->permissions[byte] = map; | |
4188 | } | |
4189 | } | |
4190 | ||
2d344105 HH |
4191 | /* |
4192 | * PKU is an additional mechanism by which the paging controls access to | |
4193 | * user-mode addresses based on the value in the PKRU register. Protection | |
4194 | * key violations are reported through a bit in the page fault error code. | |
4195 | * Unlike other bits of the error code, the PK bit is not known at the | |
4196 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4197 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4198 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4199 | * | |
4200 | * In particular the following conditions come from the error code, the | |
4201 | * page tables and the machine state: | |
4202 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4203 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4204 | * - PK is always zero if U=0 in the page tables | |
4205 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4206 | * | |
4207 | * The PKRU bitmask caches the result of these four conditions. The error | |
4208 | * code (minus the P bit) and the page table's U bit form an index into the | |
4209 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4210 | * with the two bits of the PKRU register corresponding to the protection key. | |
4211 | * For the first three conditions above the bits will be 00, thus masking | |
4212 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4213 | * only will be masked away. | |
4214 | */ | |
4215 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4216 | bool ept) | |
4217 | { | |
4218 | unsigned bit; | |
4219 | bool wp; | |
4220 | ||
4221 | if (ept) { | |
4222 | mmu->pkru_mask = 0; | |
4223 | return; | |
4224 | } | |
4225 | ||
4226 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4227 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4228 | mmu->pkru_mask = 0; | |
4229 | return; | |
4230 | } | |
4231 | ||
4232 | wp = is_write_protection(vcpu); | |
4233 | ||
4234 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4235 | unsigned pfec, pkey_bits; | |
4236 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4237 | ||
4238 | pfec = bit << 1; | |
4239 | ff = pfec & PFERR_FETCH_MASK; | |
4240 | uf = pfec & PFERR_USER_MASK; | |
4241 | wf = pfec & PFERR_WRITE_MASK; | |
4242 | ||
4243 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4244 | pte_user = pfec & PFERR_RSVD_MASK; | |
4245 | ||
4246 | /* | |
4247 | * Only need to check the access which is not an | |
4248 | * instruction fetch and is to a user page. | |
4249 | */ | |
4250 | check_pkey = (!ff && pte_user); | |
4251 | /* | |
4252 | * write access is controlled by PKRU if it is a | |
4253 | * user access or CR0.WP = 1. | |
4254 | */ | |
4255 | check_write = check_pkey && wf && (uf || wp); | |
4256 | ||
4257 | /* PKRU.AD stops both read and write access. */ | |
4258 | pkey_bits = !!check_pkey; | |
4259 | /* PKRU.WD stops write access. */ | |
4260 | pkey_bits |= (!!check_write) << 1; | |
4261 | ||
4262 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4263 | } | |
4264 | } | |
4265 | ||
6bb69c9b | 4266 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4267 | { |
6bb69c9b PB |
4268 | unsigned root_level = mmu->root_level; |
4269 | ||
4270 | mmu->last_nonleaf_level = root_level; | |
4271 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4272 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4273 | } |
4274 | ||
8a3c1a33 PB |
4275 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4276 | struct kvm_mmu *context, | |
4277 | int level) | |
6aa8b732 | 4278 | { |
2d48a985 | 4279 | context->nx = is_nx(vcpu); |
4d6931c3 | 4280 | context->root_level = level; |
2d48a985 | 4281 | |
4d6931c3 | 4282 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4283 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4284 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4285 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4286 | |
fa4a2c08 | 4287 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4288 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4289 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4290 | context->sync_page = paging64_sync_page; |
a7052897 | 4291 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4292 | context->update_pte = paging64_update_pte; |
17ac10ad | 4293 | context->shadow_root_level = level; |
17c3ba9d | 4294 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4295 | context->direct_map = false; |
6aa8b732 AK |
4296 | } |
4297 | ||
8a3c1a33 PB |
4298 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4299 | struct kvm_mmu *context) | |
17ac10ad | 4300 | { |
8a3c1a33 | 4301 | paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
4302 | } |
4303 | ||
8a3c1a33 PB |
4304 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4305 | struct kvm_mmu *context) | |
6aa8b732 | 4306 | { |
2d48a985 | 4307 | context->nx = false; |
4d6931c3 | 4308 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4309 | |
4d6931c3 | 4310 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4311 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4312 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4313 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4314 | |
6aa8b732 | 4315 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4316 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4317 | context->sync_page = paging32_sync_page; |
a7052897 | 4318 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4319 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4320 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 4321 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4322 | context->direct_map = false; |
6aa8b732 AK |
4323 | } |
4324 | ||
8a3c1a33 PB |
4325 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4326 | struct kvm_mmu *context) | |
6aa8b732 | 4327 | { |
8a3c1a33 | 4328 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4329 | } |
4330 | ||
8a3c1a33 | 4331 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4332 | { |
ad896af0 | 4333 | struct kvm_mmu *context = &vcpu->arch.mmu; |
fb72d167 | 4334 | |
c445f8ef | 4335 | context->base_role.word = 0; |
699023e2 | 4336 | context->base_role.smm = is_smm(vcpu); |
ac8d57e5 | 4337 | context->base_role.ad_disabled = (shadow_accessed_mask == 0); |
fb72d167 | 4338 | context->page_fault = tdp_page_fault; |
e8bc217a | 4339 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4340 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4341 | context->update_pte = nonpaging_update_pte; |
67253af5 | 4342 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 4343 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4344 | context->direct_map = true; |
1c97f0a0 | 4345 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4346 | context->get_cr3 = get_cr3; |
e4e517b4 | 4347 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4348 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4349 | |
4350 | if (!is_paging(vcpu)) { | |
2d48a985 | 4351 | context->nx = false; |
fb72d167 JR |
4352 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4353 | context->root_level = 0; | |
4354 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4355 | context->nx = is_nx(vcpu); |
fb72d167 | 4356 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
4357 | reset_rsvds_bits_mask(vcpu, context); |
4358 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4359 | } else if (is_pae(vcpu)) { |
2d48a985 | 4360 | context->nx = is_nx(vcpu); |
fb72d167 | 4361 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4362 | reset_rsvds_bits_mask(vcpu, context); |
4363 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4364 | } else { |
2d48a985 | 4365 | context->nx = false; |
fb72d167 | 4366 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4367 | reset_rsvds_bits_mask(vcpu, context); |
4368 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4369 | } |
4370 | ||
25d92081 | 4371 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4372 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4373 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4374 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4375 | } |
4376 | ||
ad896af0 | 4377 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) |
6aa8b732 | 4378 | { |
411c588d | 4379 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
edc90b7d | 4380 | bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
ad896af0 PB |
4381 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4382 | ||
fa4a2c08 | 4383 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
6aa8b732 AK |
4384 | |
4385 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4386 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4387 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4388 | paging64_init_context(vcpu, context); |
6aa8b732 | 4389 | else if (is_pae(vcpu)) |
8a3c1a33 | 4390 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4391 | else |
8a3c1a33 | 4392 | paging32_init_context(vcpu, context); |
a770f6f2 | 4393 | |
ad896af0 PB |
4394 | context->base_role.nxe = is_nx(vcpu); |
4395 | context->base_role.cr4_pae = !!is_pae(vcpu); | |
4396 | context->base_role.cr0_wp = is_write_protection(vcpu); | |
4397 | context->base_role.smep_andnot_wp | |
411c588d | 4398 | = smep && !is_write_protection(vcpu); |
edc90b7d XG |
4399 | context->base_role.smap_andnot_wp |
4400 | = smap && !is_write_protection(vcpu); | |
699023e2 | 4401 | context->base_role.smm = is_smm(vcpu); |
c258b62b | 4402 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4403 | } |
4404 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4405 | ||
ae1e2d10 PB |
4406 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
4407 | bool accessed_dirty) | |
155a97a3 | 4408 | { |
ad896af0 PB |
4409 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4410 | ||
fa4a2c08 | 4411 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
155a97a3 NHE |
4412 | |
4413 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); | |
4414 | ||
4415 | context->nx = true; | |
ae1e2d10 | 4416 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4417 | context->page_fault = ept_page_fault; |
4418 | context->gva_to_gpa = ept_gva_to_gpa; | |
4419 | context->sync_page = ept_sync_page; | |
4420 | context->invlpg = ept_invlpg; | |
4421 | context->update_pte = ept_update_pte; | |
155a97a3 NHE |
4422 | context->root_level = context->shadow_root_level; |
4423 | context->root_hpa = INVALID_PAGE; | |
4424 | context->direct_map = false; | |
995f00a6 | 4425 | context->base_role.ad_disabled = !accessed_dirty; |
155a97a3 NHE |
4426 | |
4427 | update_permission_bitmask(vcpu, context, true); | |
2d344105 | 4428 | update_pkru_bitmask(vcpu, context, true); |
155a97a3 | 4429 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4430 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4431 | } |
4432 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4433 | ||
8a3c1a33 | 4434 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4435 | { |
ad896af0 PB |
4436 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4437 | ||
4438 | kvm_init_shadow_mmu(vcpu); | |
4439 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4440 | context->get_cr3 = get_cr3; | |
4441 | context->get_pdptr = kvm_pdptr_read; | |
4442 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4443 | } |
4444 | ||
8a3c1a33 | 4445 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
4446 | { |
4447 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
4448 | ||
4449 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 4450 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4451 | g_context->inject_page_fault = kvm_inject_page_fault; |
4452 | ||
4453 | /* | |
0af2593b DM |
4454 | * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using |
4455 | * L1's nested page tables (e.g. EPT12). The nested translation | |
4456 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4457 | * L2's page tables as the first level of translation and L1's | |
4458 | * nested page tables as the second level of translation. Basically | |
4459 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4460 | */ |
4461 | if (!is_paging(vcpu)) { | |
2d48a985 | 4462 | g_context->nx = false; |
02f59dc9 JR |
4463 | g_context->root_level = 0; |
4464 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4465 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4466 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4467 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 4468 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4469 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4470 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4471 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4472 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4473 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4474 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4475 | } else { | |
2d48a985 | 4476 | g_context->nx = false; |
02f59dc9 | 4477 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4478 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4479 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4480 | } | |
4481 | ||
25d92081 | 4482 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4483 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4484 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4485 | } |
4486 | ||
8a3c1a33 | 4487 | static void init_kvm_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4488 | { |
02f59dc9 | 4489 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4490 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4491 | else if (tdp_enabled) |
e0c6db3e | 4492 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4493 | else |
e0c6db3e | 4494 | init_kvm_softmmu(vcpu); |
fb72d167 JR |
4495 | } |
4496 | ||
8a3c1a33 | 4497 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4498 | { |
95f93af4 | 4499 | kvm_mmu_unload(vcpu); |
8a3c1a33 | 4500 | init_kvm_mmu(vcpu); |
17c3ba9d | 4501 | } |
8668a3c4 | 4502 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4503 | |
4504 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4505 | { |
714b93da AK |
4506 | int r; |
4507 | ||
e2dec939 | 4508 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
4509 | if (r) |
4510 | goto out; | |
8986ecc0 | 4511 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4512 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4513 | if (r) |
4514 | goto out; | |
3662cb1c | 4515 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 4516 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
4517 | out: |
4518 | return r; | |
6aa8b732 | 4519 | } |
17c3ba9d AK |
4520 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4521 | ||
4522 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4523 | { | |
4524 | mmu_free_roots(vcpu); | |
95f93af4 | 4525 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 4526 | } |
4b16184c | 4527 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4528 | |
0028425f | 4529 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4530 | struct kvm_mmu_page *sp, u64 *spte, |
4531 | const void *new) | |
0028425f | 4532 | { |
30945387 | 4533 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
4534 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4535 | return; | |
30945387 | 4536 | } |
0028425f | 4537 | |
4cee5764 | 4538 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 4539 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
4540 | } |
4541 | ||
79539cec AK |
4542 | static bool need_remote_flush(u64 old, u64 new) |
4543 | { | |
4544 | if (!is_shadow_present_pte(old)) | |
4545 | return false; | |
4546 | if (!is_shadow_present_pte(new)) | |
4547 | return true; | |
4548 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4549 | return true; | |
53166229 GN |
4550 | old ^= shadow_nx_mask; |
4551 | new ^= shadow_nx_mask; | |
79539cec AK |
4552 | return (old & ~new & PT64_PERM_MASK) != 0; |
4553 | } | |
4554 | ||
889e5cbc XG |
4555 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
4556 | const u8 *new, int *bytes) | |
da4a00f0 | 4557 | { |
889e5cbc XG |
4558 | u64 gentry; |
4559 | int r; | |
72016f3a | 4560 | |
72016f3a AK |
4561 | /* |
4562 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4563 | * as the current vcpu paging mode since we update the sptes only |
4564 | * when they have the same mode. | |
72016f3a | 4565 | */ |
889e5cbc | 4566 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4567 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4568 | *gpa &= ~(gpa_t)7; |
4569 | *bytes = 8; | |
54bf36aa | 4570 | r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8); |
72016f3a AK |
4571 | if (r) |
4572 | gentry = 0; | |
08e850c6 AK |
4573 | new = (const u8 *)&gentry; |
4574 | } | |
4575 | ||
889e5cbc | 4576 | switch (*bytes) { |
08e850c6 AK |
4577 | case 4: |
4578 | gentry = *(const u32 *)new; | |
4579 | break; | |
4580 | case 8: | |
4581 | gentry = *(const u64 *)new; | |
4582 | break; | |
4583 | default: | |
4584 | gentry = 0; | |
4585 | break; | |
72016f3a AK |
4586 | } |
4587 | ||
889e5cbc XG |
4588 | return gentry; |
4589 | } | |
4590 | ||
4591 | /* | |
4592 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4593 | * or we may be forking, in which case it is better to unmap the page. | |
4594 | */ | |
a138fe75 | 4595 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4596 | { |
a30f47cb XG |
4597 | /* |
4598 | * Skip write-flooding detected for the sp whose level is 1, because | |
4599 | * it can become unsync, then the guest page is not write-protected. | |
4600 | */ | |
f71fa31f | 4601 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4602 | return false; |
3246af0e | 4603 | |
e5691a81 XG |
4604 | atomic_inc(&sp->write_flooding_count); |
4605 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4606 | } |
4607 | ||
4608 | /* | |
4609 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4610 | * indicate a page is not used as a page table. | |
4611 | */ | |
4612 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4613 | int bytes) | |
4614 | { | |
4615 | unsigned offset, pte_size, misaligned; | |
4616 | ||
4617 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4618 | gpa, bytes, sp->role.word); | |
4619 | ||
4620 | offset = offset_in_page(gpa); | |
4621 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4622 | |
4623 | /* | |
4624 | * Sometimes, the OS only writes the last one bytes to update status | |
4625 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4626 | */ | |
4627 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4628 | return false; | |
4629 | ||
889e5cbc XG |
4630 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4631 | misaligned |= bytes < 4; | |
4632 | ||
4633 | return misaligned; | |
4634 | } | |
4635 | ||
4636 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4637 | { | |
4638 | unsigned page_offset, quadrant; | |
4639 | u64 *spte; | |
4640 | int level; | |
4641 | ||
4642 | page_offset = offset_in_page(gpa); | |
4643 | level = sp->role.level; | |
4644 | *nspte = 1; | |
4645 | if (!sp->role.cr4_pae) { | |
4646 | page_offset <<= 1; /* 32->64 */ | |
4647 | /* | |
4648 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4649 | * only 2MB. So we need to double the offset again | |
4650 | * and zap two pdes instead of one. | |
4651 | */ | |
4652 | if (level == PT32_ROOT_LEVEL) { | |
4653 | page_offset &= ~7; /* kill rounding error */ | |
4654 | page_offset <<= 1; | |
4655 | *nspte = 2; | |
4656 | } | |
4657 | quadrant = page_offset >> PAGE_SHIFT; | |
4658 | page_offset &= ~PAGE_MASK; | |
4659 | if (quadrant != sp->role.quadrant) | |
4660 | return NULL; | |
4661 | } | |
4662 | ||
4663 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4664 | return spte; | |
4665 | } | |
4666 | ||
13d268ca | 4667 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
4668 | const u8 *new, int bytes, |
4669 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
4670 | { |
4671 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4672 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4673 | LIST_HEAD(invalid_list); |
4674 | u64 entry, gentry, *spte; | |
4675 | int npte; | |
b8c67b7a | 4676 | bool remote_flush, local_flush; |
4141259b AM |
4677 | union kvm_mmu_page_role mask = { }; |
4678 | ||
4679 | mask.cr0_wp = 1; | |
4680 | mask.cr4_pae = 1; | |
4681 | mask.nxe = 1; | |
4682 | mask.smep_andnot_wp = 1; | |
4683 | mask.smap_andnot_wp = 1; | |
699023e2 | 4684 | mask.smm = 1; |
ac8d57e5 | 4685 | mask.ad_disabled = 1; |
889e5cbc XG |
4686 | |
4687 | /* | |
4688 | * If we don't have indirect shadow pages, it means no page is | |
4689 | * write-protected, so we can exit simply. | |
4690 | */ | |
4691 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4692 | return; | |
4693 | ||
b8c67b7a | 4694 | remote_flush = local_flush = false; |
889e5cbc XG |
4695 | |
4696 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4697 | ||
4698 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4699 | ||
4700 | /* | |
4701 | * No need to care whether allocation memory is successful | |
4702 | * or not since pte prefetch is skiped if it does not have | |
4703 | * enough objects in the cache. | |
4704 | */ | |
4705 | mmu_topup_memory_caches(vcpu); | |
4706 | ||
4707 | spin_lock(&vcpu->kvm->mmu_lock); | |
4708 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4709 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4710 | |
b67bfe0d | 4711 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4712 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4713 | detect_write_flooding(sp)) { |
b8c67b7a | 4714 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4715 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4716 | continue; |
4717 | } | |
889e5cbc XG |
4718 | |
4719 | spte = get_written_sptes(sp, gpa, &npte); | |
4720 | if (!spte) | |
4721 | continue; | |
4722 | ||
0671a8e7 | 4723 | local_flush = true; |
ac1b714e | 4724 | while (npte--) { |
79539cec | 4725 | entry = *spte; |
38e3b2b2 | 4726 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4727 | if (gentry && |
4728 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4729 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4730 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4731 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4732 | remote_flush = true; |
ac1b714e | 4733 | ++spte; |
9b7a0325 | 4734 | } |
9b7a0325 | 4735 | } |
b8c67b7a | 4736 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 4737 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4738 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4739 | } |
4740 | ||
a436036b AK |
4741 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4742 | { | |
10589a46 MT |
4743 | gpa_t gpa; |
4744 | int r; | |
a436036b | 4745 | |
c5a78f2b | 4746 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4747 | return 0; |
4748 | ||
1871c602 | 4749 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4750 | |
10589a46 | 4751 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4752 | |
10589a46 | 4753 | return r; |
a436036b | 4754 | } |
577bdc49 | 4755 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4756 | |
81f4f76b | 4757 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4758 | { |
d98ba053 | 4759 | LIST_HEAD(invalid_list); |
103ad25a | 4760 | |
81f4f76b TY |
4761 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4762 | return; | |
4763 | ||
5da59607 TY |
4764 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4765 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4766 | break; | |
ebeace86 | 4767 | |
4cee5764 | 4768 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4769 | } |
aa6bd187 | 4770 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4771 | } |
ebeace86 | 4772 | |
14727754 | 4773 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code, |
dc25e89e | 4774 | void *insn, int insn_len) |
3067714c | 4775 | { |
1cb3f3ae | 4776 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c | 4777 | enum emulation_result er; |
ded58749 | 4778 | bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu); |
3067714c | 4779 | |
e9ee956e TY |
4780 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
4781 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
4782 | if (r == RET_MMIO_PF_EMULATE) { | |
4783 | emulation_type = 0; | |
4784 | goto emulate; | |
4785 | } | |
4786 | if (r == RET_MMIO_PF_RETRY) | |
4787 | return 1; | |
4788 | if (r < 0) | |
4789 | return r; | |
4790 | } | |
3067714c | 4791 | |
14727754 TL |
4792 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code), |
4793 | false); | |
3067714c | 4794 | if (r < 0) |
e9ee956e TY |
4795 | return r; |
4796 | if (!r) | |
4797 | return 1; | |
3067714c | 4798 | |
14727754 TL |
4799 | /* |
4800 | * Before emulating the instruction, check if the error code | |
4801 | * was due to a RO violation while translating the guest page. | |
4802 | * This can occur when using nested virtualization with nested | |
4803 | * paging in both guests. If true, we simply unprotect the page | |
4804 | * and resume the guest. | |
4805 | * | |
4806 | * Note: AMD only (since it supports the PFERR_GUEST_PAGE_MASK used | |
4807 | * in PFERR_NEXT_GUEST_PAGE) | |
4808 | */ | |
4809 | if (error_code == PFERR_NESTED_GUEST_PAGE) { | |
4810 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2)); | |
4811 | return 1; | |
4812 | } | |
4813 | ||
ded58749 | 4814 | if (mmio_info_in_cache(vcpu, cr2, direct)) |
1cb3f3ae | 4815 | emulation_type = 0; |
e9ee956e | 4816 | emulate: |
1cb3f3ae | 4817 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
4818 | |
4819 | switch (er) { | |
4820 | case EMULATE_DONE: | |
4821 | return 1; | |
ac0a48c3 | 4822 | case EMULATE_USER_EXIT: |
3067714c | 4823 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 4824 | /* fall through */ |
3067714c | 4825 | case EMULATE_FAIL: |
3f5d18a9 | 4826 | return 0; |
3067714c AK |
4827 | default: |
4828 | BUG(); | |
4829 | } | |
3067714c AK |
4830 | } |
4831 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4832 | ||
a7052897 MT |
4833 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4834 | { | |
a7052897 | 4835 | vcpu->arch.mmu.invlpg(vcpu, gva); |
77c3913b | 4836 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a7052897 MT |
4837 | ++vcpu->stat.invlpg; |
4838 | } | |
4839 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4840 | ||
18552672 JR |
4841 | void kvm_enable_tdp(void) |
4842 | { | |
4843 | tdp_enabled = true; | |
4844 | } | |
4845 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4846 | ||
5f4cb662 JR |
4847 | void kvm_disable_tdp(void) |
4848 | { | |
4849 | tdp_enabled = false; | |
4850 | } | |
4851 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4852 | ||
6aa8b732 AK |
4853 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4854 | { | |
ad312c7c | 4855 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4856 | if (vcpu->arch.mmu.lm_root != NULL) |
4857 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4858 | } |
4859 | ||
4860 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4861 | { | |
17ac10ad | 4862 | struct page *page; |
6aa8b732 AK |
4863 | int i; |
4864 | ||
17ac10ad AK |
4865 | /* |
4866 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4867 | * Therefore we need to allocate shadow page tables in the first | |
4868 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4869 | */ | |
4870 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4871 | if (!page) | |
d7fa6ab2 WY |
4872 | return -ENOMEM; |
4873 | ||
ad312c7c | 4874 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4875 | for (i = 0; i < 4; ++i) |
ad312c7c | 4876 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4877 | |
6aa8b732 | 4878 | return 0; |
6aa8b732 AK |
4879 | } |
4880 | ||
8018c27b | 4881 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4882 | { |
e459e322 XG |
4883 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
4884 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4885 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4886 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4887 | |
8018c27b IM |
4888 | return alloc_mmu_pages(vcpu); |
4889 | } | |
6aa8b732 | 4890 | |
8a3c1a33 | 4891 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b | 4892 | { |
fa4a2c08 | 4893 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4894 | |
8a3c1a33 | 4895 | init_kvm_mmu(vcpu); |
6aa8b732 AK |
4896 | } |
4897 | ||
b5f5fdca | 4898 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
4899 | struct kvm_memory_slot *slot, |
4900 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca XC |
4901 | { |
4902 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
4903 | } | |
4904 | ||
13d268ca XG |
4905 | void kvm_mmu_init_vm(struct kvm *kvm) |
4906 | { | |
4907 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
4908 | ||
4909 | node->track_write = kvm_mmu_pte_write; | |
b5f5fdca | 4910 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca XG |
4911 | kvm_page_track_register_notifier(kvm, node); |
4912 | } | |
4913 | ||
4914 | void kvm_mmu_uninit_vm(struct kvm *kvm) | |
4915 | { | |
4916 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
4917 | ||
4918 | kvm_page_track_unregister_notifier(kvm, node); | |
4919 | } | |
4920 | ||
1bad2b2a | 4921 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 4922 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
4923 | |
4924 | /* The caller should hold mmu-lock before calling this function. */ | |
4925 | static bool | |
4926 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4927 | slot_level_handler fn, int start_level, int end_level, | |
4928 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
4929 | { | |
4930 | struct slot_rmap_walk_iterator iterator; | |
4931 | bool flush = false; | |
4932 | ||
4933 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
4934 | end_gfn, &iterator) { | |
4935 | if (iterator.rmap) | |
4936 | flush |= fn(kvm, iterator.rmap); | |
4937 | ||
4938 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4939 | if (flush && lock_flush_tlb) { | |
4940 | kvm_flush_remote_tlbs(kvm); | |
4941 | flush = false; | |
4942 | } | |
4943 | cond_resched_lock(&kvm->mmu_lock); | |
4944 | } | |
4945 | } | |
4946 | ||
4947 | if (flush && lock_flush_tlb) { | |
4948 | kvm_flush_remote_tlbs(kvm); | |
4949 | flush = false; | |
4950 | } | |
4951 | ||
4952 | return flush; | |
4953 | } | |
4954 | ||
4955 | static bool | |
4956 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4957 | slot_level_handler fn, int start_level, int end_level, | |
4958 | bool lock_flush_tlb) | |
4959 | { | |
4960 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
4961 | end_level, memslot->base_gfn, | |
4962 | memslot->base_gfn + memslot->npages - 1, | |
4963 | lock_flush_tlb); | |
4964 | } | |
4965 | ||
4966 | static bool | |
4967 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4968 | slot_level_handler fn, bool lock_flush_tlb) | |
4969 | { | |
4970 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
4971 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
4972 | } | |
4973 | ||
4974 | static bool | |
4975 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4976 | slot_level_handler fn, bool lock_flush_tlb) | |
4977 | { | |
4978 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
4979 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
4980 | } | |
4981 | ||
4982 | static bool | |
4983 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4984 | slot_level_handler fn, bool lock_flush_tlb) | |
4985 | { | |
4986 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
4987 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
4988 | } | |
4989 | ||
efdfe536 XG |
4990 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
4991 | { | |
4992 | struct kvm_memslots *slots; | |
4993 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 4994 | int i; |
efdfe536 XG |
4995 | |
4996 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
4997 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
4998 | slots = __kvm_memslots(kvm, i); | |
4999 | kvm_for_each_memslot(memslot, slots) { | |
5000 | gfn_t start, end; | |
5001 | ||
5002 | start = max(gfn_start, memslot->base_gfn); | |
5003 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5004 | if (start >= end) | |
5005 | continue; | |
efdfe536 | 5006 | |
9da0e4d5 PB |
5007 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
5008 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
5009 | start, end - 1, true); | |
5010 | } | |
efdfe536 XG |
5011 | } |
5012 | ||
5013 | spin_unlock(&kvm->mmu_lock); | |
5014 | } | |
5015 | ||
018aabb5 TY |
5016 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5017 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5018 | { |
018aabb5 | 5019 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5020 | } |
5021 | ||
1c91cad4 KH |
5022 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
5023 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 5024 | { |
d77aa73c | 5025 | bool flush; |
6aa8b732 | 5026 | |
9d1beefb | 5027 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
5028 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
5029 | false); | |
9d1beefb | 5030 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
5031 | |
5032 | /* | |
5033 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
5034 | * which do tlb flush out of mmu-lock should be serialized by | |
5035 | * kvm->slots_lock otherwise tlb flush would be missed. | |
5036 | */ | |
5037 | lockdep_assert_held(&kvm->slots_lock); | |
5038 | ||
5039 | /* | |
5040 | * We can flush all the TLBs out of the mmu lock without TLB | |
5041 | * corruption since we just change the spte from writable to | |
5042 | * readonly so that we only need to care the case of changing | |
5043 | * spte from present to present (changing the spte from present | |
5044 | * to nonpresent will flush all the TLBs immediately), in other | |
5045 | * words, the only case we care is mmu_spte_update() where we | |
5046 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
5047 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
5048 | * on PT_WRITABLE_MASK anymore. | |
5049 | */ | |
d91ffee9 KH |
5050 | if (flush) |
5051 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 5052 | } |
37a7d8b0 | 5053 | |
3ea3b7fa | 5054 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5055 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5056 | { |
5057 | u64 *sptep; | |
5058 | struct rmap_iterator iter; | |
5059 | int need_tlb_flush = 0; | |
ba049e93 | 5060 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5061 | struct kvm_mmu_page *sp; |
5062 | ||
0d536790 | 5063 | restart: |
018aabb5 | 5064 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
5065 | sp = page_header(__pa(sptep)); |
5066 | pfn = spte_to_pfn(*sptep); | |
5067 | ||
5068 | /* | |
decf6333 XG |
5069 | * We cannot do huge page mapping for indirect shadow pages, |
5070 | * which are found on the last rmap (level = 1) when not using | |
5071 | * tdp; such shadow pages are synced with the page table in | |
5072 | * the guest, and the guest page table is using 4K page size | |
5073 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
5074 | */ |
5075 | if (sp->role.direct && | |
5076 | !kvm_is_reserved_pfn(pfn) && | |
127393fb | 5077 | PageTransCompoundMap(pfn_to_page(pfn))) { |
3ea3b7fa | 5078 | drop_spte(kvm, sptep); |
3ea3b7fa | 5079 | need_tlb_flush = 1; |
0d536790 XG |
5080 | goto restart; |
5081 | } | |
3ea3b7fa WL |
5082 | } |
5083 | ||
5084 | return need_tlb_flush; | |
5085 | } | |
5086 | ||
5087 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5088 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5089 | { |
f36f3f28 | 5090 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5091 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5092 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5093 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5094 | spin_unlock(&kvm->mmu_lock); |
5095 | } | |
5096 | ||
f4b4b180 KH |
5097 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5098 | struct kvm_memory_slot *memslot) | |
5099 | { | |
d77aa73c | 5100 | bool flush; |
f4b4b180 KH |
5101 | |
5102 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5103 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5104 | spin_unlock(&kvm->mmu_lock); |
5105 | ||
5106 | lockdep_assert_held(&kvm->slots_lock); | |
5107 | ||
5108 | /* | |
5109 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5110 | * function is only used for dirty logging, in which case flushing TLB | |
5111 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5112 | * dirty_bitmap. | |
5113 | */ | |
5114 | if (flush) | |
5115 | kvm_flush_remote_tlbs(kvm); | |
5116 | } | |
5117 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5118 | ||
5119 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5120 | struct kvm_memory_slot *memslot) | |
5121 | { | |
d77aa73c | 5122 | bool flush; |
f4b4b180 KH |
5123 | |
5124 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5125 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5126 | false); | |
f4b4b180 KH |
5127 | spin_unlock(&kvm->mmu_lock); |
5128 | ||
5129 | /* see kvm_mmu_slot_remove_write_access */ | |
5130 | lockdep_assert_held(&kvm->slots_lock); | |
5131 | ||
5132 | if (flush) | |
5133 | kvm_flush_remote_tlbs(kvm); | |
5134 | } | |
5135 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5136 | ||
5137 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5138 | struct kvm_memory_slot *memslot) | |
5139 | { | |
d77aa73c | 5140 | bool flush; |
f4b4b180 KH |
5141 | |
5142 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5143 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5144 | spin_unlock(&kvm->mmu_lock); |
5145 | ||
5146 | lockdep_assert_held(&kvm->slots_lock); | |
5147 | ||
5148 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
5149 | if (flush) | |
5150 | kvm_flush_remote_tlbs(kvm); | |
5151 | } | |
5152 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5153 | ||
e7d11c7a | 5154 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
5155 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5156 | { | |
5157 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 5158 | int batch = 0; |
5304b8d3 XG |
5159 | |
5160 | restart: | |
5161 | list_for_each_entry_safe_reverse(sp, node, | |
5162 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
5163 | int ret; |
5164 | ||
5304b8d3 XG |
5165 | /* |
5166 | * No obsolete page exists before new created page since | |
5167 | * active_mmu_pages is the FIFO list. | |
5168 | */ | |
5169 | if (!is_obsolete_sp(kvm, sp)) | |
5170 | break; | |
5171 | ||
5172 | /* | |
5304b8d3 XG |
5173 | * Since we are reversely walking the list and the invalid |
5174 | * list will be moved to the head, skip the invalid page | |
5175 | * can help us to avoid the infinity list walking. | |
5176 | */ | |
5177 | if (sp->role.invalid) | |
5178 | continue; | |
5179 | ||
f34d251d XG |
5180 | /* |
5181 | * Need not flush tlb since we only zap the sp with invalid | |
5182 | * generation number. | |
5183 | */ | |
e7d11c7a | 5184 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 5185 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 5186 | batch = 0; |
5304b8d3 XG |
5187 | goto restart; |
5188 | } | |
5189 | ||
365c8868 XG |
5190 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
5191 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
5192 | batch += ret; |
5193 | ||
5194 | if (ret) | |
5304b8d3 XG |
5195 | goto restart; |
5196 | } | |
5197 | ||
f34d251d XG |
5198 | /* |
5199 | * Should flush tlb before free page tables since lockless-walking | |
5200 | * may use the pages. | |
5201 | */ | |
365c8868 | 5202 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
5203 | } |
5204 | ||
5205 | /* | |
5206 | * Fast invalidate all shadow pages and use lock-break technique | |
5207 | * to zap obsolete pages. | |
5208 | * | |
5209 | * It's required when memslot is being deleted or VM is being | |
5210 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5211 | * not use any resource of the being-deleted slot or all slots | |
5212 | * after calling the function. | |
5213 | */ | |
5214 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
5215 | { | |
5216 | spin_lock(&kvm->mmu_lock); | |
35006126 | 5217 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
5218 | kvm->arch.mmu_valid_gen++; |
5219 | ||
f34d251d XG |
5220 | /* |
5221 | * Notify all vcpus to reload its shadow page table | |
5222 | * and flush TLB. Then all vcpus will switch to new | |
5223 | * shadow page table with the new mmu_valid_gen. | |
5224 | * | |
5225 | * Note: we should do this under the protection of | |
5226 | * mmu-lock, otherwise, vcpu would purge shadow page | |
5227 | * but miss tlb flush. | |
5228 | */ | |
5229 | kvm_reload_remote_mmus(kvm); | |
5230 | ||
5304b8d3 XG |
5231 | kvm_zap_obsolete_pages(kvm); |
5232 | spin_unlock(&kvm->mmu_lock); | |
5233 | } | |
5234 | ||
365c8868 XG |
5235 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5236 | { | |
5237 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5238 | } | |
5239 | ||
54bf36aa | 5240 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots) |
f8f55942 XG |
5241 | { |
5242 | /* | |
5243 | * The very rare case: if the generation-number is round, | |
5244 | * zap all shadow pages. | |
f8f55942 | 5245 | */ |
54bf36aa | 5246 | if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) { |
ae0f5499 | 5247 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 5248 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 5249 | } |
f8f55942 XG |
5250 | } |
5251 | ||
70534a73 DC |
5252 | static unsigned long |
5253 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5254 | { |
5255 | struct kvm *kvm; | |
1495f230 | 5256 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5257 | unsigned long freed = 0; |
3ee16c81 | 5258 | |
2f303b74 | 5259 | spin_lock(&kvm_lock); |
3ee16c81 IE |
5260 | |
5261 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5262 | int idx; |
d98ba053 | 5263 | LIST_HEAD(invalid_list); |
3ee16c81 | 5264 | |
35f2d16b TY |
5265 | /* |
5266 | * Never scan more than sc->nr_to_scan VM instances. | |
5267 | * Will not hit this condition practically since we do not try | |
5268 | * to shrink more than one VM and it is very unlikely to see | |
5269 | * !n_used_mmu_pages so many times. | |
5270 | */ | |
5271 | if (!nr_to_scan--) | |
5272 | break; | |
19526396 GN |
5273 | /* |
5274 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5275 | * here. We may skip a VM instance errorneosly, but we do not | |
5276 | * want to shrink a VM that only started to populate its MMU | |
5277 | * anyway. | |
5278 | */ | |
365c8868 XG |
5279 | if (!kvm->arch.n_used_mmu_pages && |
5280 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5281 | continue; |
19526396 | 5282 | |
f656ce01 | 5283 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5284 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5285 | |
365c8868 XG |
5286 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5287 | kvm_mmu_commit_zap_page(kvm, | |
5288 | &kvm->arch.zapped_obsolete_pages); | |
5289 | goto unlock; | |
5290 | } | |
5291 | ||
70534a73 DC |
5292 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5293 | freed++; | |
d98ba053 | 5294 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5295 | |
365c8868 | 5296 | unlock: |
3ee16c81 | 5297 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5298 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5299 | |
70534a73 DC |
5300 | /* |
5301 | * unfair on small ones | |
5302 | * per-vm shrinkers cry out | |
5303 | * sadness comes quickly | |
5304 | */ | |
19526396 GN |
5305 | list_move_tail(&kvm->vm_list, &vm_list); |
5306 | break; | |
3ee16c81 | 5307 | } |
3ee16c81 | 5308 | |
2f303b74 | 5309 | spin_unlock(&kvm_lock); |
70534a73 | 5310 | return freed; |
70534a73 DC |
5311 | } |
5312 | ||
5313 | static unsigned long | |
5314 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5315 | { | |
45221ab6 | 5316 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5317 | } |
5318 | ||
5319 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5320 | .count_objects = mmu_shrink_count, |
5321 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5322 | .seeks = DEFAULT_SEEKS * 10, |
5323 | }; | |
5324 | ||
2ddfd20e | 5325 | static void mmu_destroy_caches(void) |
b5a33a75 | 5326 | { |
53c07b18 XG |
5327 | if (pte_list_desc_cache) |
5328 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
5329 | if (mmu_page_header_cache) |
5330 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5331 | } |
5332 | ||
5333 | int kvm_mmu_module_init(void) | |
5334 | { | |
f160c7b7 JS |
5335 | kvm_mmu_clear_all_pte_masks(); |
5336 | ||
53c07b18 XG |
5337 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5338 | sizeof(struct pte_list_desc), | |
20c2df83 | 5339 | 0, 0, NULL); |
53c07b18 | 5340 | if (!pte_list_desc_cache) |
b5a33a75 AK |
5341 | goto nomem; |
5342 | ||
d3d25b04 AK |
5343 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5344 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 5345 | 0, 0, NULL); |
d3d25b04 AK |
5346 | if (!mmu_page_header_cache) |
5347 | goto nomem; | |
5348 | ||
908c7f19 | 5349 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
45bf21a8 WY |
5350 | goto nomem; |
5351 | ||
3ee16c81 IE |
5352 | register_shrinker(&mmu_shrinker); |
5353 | ||
b5a33a75 AK |
5354 | return 0; |
5355 | ||
5356 | nomem: | |
3ee16c81 | 5357 | mmu_destroy_caches(); |
b5a33a75 AK |
5358 | return -ENOMEM; |
5359 | } | |
5360 | ||
3ad82a7e ZX |
5361 | /* |
5362 | * Caculate mmu pages needed for kvm. | |
5363 | */ | |
5364 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
5365 | { | |
3ad82a7e ZX |
5366 | unsigned int nr_mmu_pages; |
5367 | unsigned int nr_pages = 0; | |
bc6678a3 | 5368 | struct kvm_memslots *slots; |
be6ba0f0 | 5369 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5370 | int i; |
3ad82a7e | 5371 | |
9da0e4d5 PB |
5372 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5373 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5374 | |
9da0e4d5 PB |
5375 | kvm_for_each_memslot(memslot, slots) |
5376 | nr_pages += memslot->npages; | |
5377 | } | |
3ad82a7e ZX |
5378 | |
5379 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
5380 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 5381 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5382 | |
5383 | return nr_mmu_pages; | |
5384 | } | |
5385 | ||
c42fffe3 XG |
5386 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5387 | { | |
95f93af4 | 5388 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
5389 | free_mmu_pages(vcpu); |
5390 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
5391 | } |
5392 | ||
b034cf01 XG |
5393 | void kvm_mmu_module_exit(void) |
5394 | { | |
5395 | mmu_destroy_caches(); | |
5396 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5397 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5398 | mmu_audit_disable(); |
5399 | } |