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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
e495606d | 19 | |
1d737c8a | 20 | #include "mmu.h" |
6de4f3ad | 21 | #include "kvm_cache_regs.h" |
e495606d | 22 | |
edf88417 | 23 | #include <linux/kvm_host.h> |
6aa8b732 AK |
24 | #include <linux/types.h> |
25 | #include <linux/string.h> | |
6aa8b732 AK |
26 | #include <linux/mm.h> |
27 | #include <linux/highmem.h> | |
28 | #include <linux/module.h> | |
448353ca | 29 | #include <linux/swap.h> |
05da4558 | 30 | #include <linux/hugetlb.h> |
2f333bcb | 31 | #include <linux/compiler.h> |
6aa8b732 | 32 | |
e495606d AK |
33 | #include <asm/page.h> |
34 | #include <asm/cmpxchg.h> | |
4e542370 | 35 | #include <asm/io.h> |
13673a90 | 36 | #include <asm/vmx.h> |
6aa8b732 | 37 | |
18552672 JR |
38 | /* |
39 | * When setting this variable to true it enables Two-Dimensional-Paging | |
40 | * where the hardware walks 2 page tables: | |
41 | * 1. the guest-virtual to guest-physical | |
42 | * 2. while doing 1. it walks guest-physical to host-physical | |
43 | * If the hardware supports that we don't need to do shadow paging. | |
44 | */ | |
2f333bcb | 45 | bool tdp_enabled = false; |
18552672 | 46 | |
37a7d8b0 AK |
47 | #undef MMU_DEBUG |
48 | ||
49 | #undef AUDIT | |
50 | ||
51 | #ifdef AUDIT | |
52 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg); | |
53 | #else | |
54 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {} | |
55 | #endif | |
56 | ||
57 | #ifdef MMU_DEBUG | |
58 | ||
59 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
60 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
61 | ||
62 | #else | |
63 | ||
64 | #define pgprintk(x...) do { } while (0) | |
65 | #define rmap_printk(x...) do { } while (0) | |
66 | ||
67 | #endif | |
68 | ||
69 | #if defined(MMU_DEBUG) || defined(AUDIT) | |
6ada8cca AK |
70 | static int dbg = 0; |
71 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 72 | #endif |
6aa8b732 | 73 | |
582801a9 MT |
74 | static int oos_shadow = 1; |
75 | module_param(oos_shadow, bool, 0644); | |
76 | ||
d6c69ee9 YD |
77 | #ifndef MMU_DEBUG |
78 | #define ASSERT(x) do { } while (0) | |
79 | #else | |
6aa8b732 AK |
80 | #define ASSERT(x) \ |
81 | if (!(x)) { \ | |
82 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
83 | __FILE__, __LINE__, #x); \ | |
84 | } | |
d6c69ee9 | 85 | #endif |
6aa8b732 | 86 | |
6aa8b732 AK |
87 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
88 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
89 | ||
6aa8b732 AK |
90 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
91 | ||
92 | #define PT64_LEVEL_BITS 9 | |
93 | ||
94 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 95 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
96 | |
97 | #define PT64_LEVEL_MASK(level) \ | |
98 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
99 | ||
100 | #define PT64_INDEX(address, level)\ | |
101 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
102 | ||
103 | ||
104 | #define PT32_LEVEL_BITS 10 | |
105 | ||
106 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 107 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
108 | |
109 | #define PT32_LEVEL_MASK(level) \ | |
110 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
111 | #define PT32_LVL_OFFSET_MASK(level) \ |
112 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
113 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
114 | |
115 | #define PT32_INDEX(address, level)\ | |
116 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
117 | ||
118 | ||
27aba766 | 119 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
120 | #define PT64_DIR_BASE_ADDR_MASK \ |
121 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
122 | #define PT64_LVL_ADDR_MASK(level) \ |
123 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
124 | * PT64_LEVEL_BITS))) - 1)) | |
125 | #define PT64_LVL_OFFSET_MASK(level) \ | |
126 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
127 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
128 | |
129 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
130 | #define PT32_DIR_BASE_ADDR_MASK \ | |
131 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
132 | #define PT32_LVL_ADDR_MASK(level) \ |
133 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
134 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 135 | |
79539cec AK |
136 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
137 | | PT64_NX_MASK) | |
6aa8b732 AK |
138 | |
139 | #define PFERR_PRESENT_MASK (1U << 0) | |
140 | #define PFERR_WRITE_MASK (1U << 1) | |
141 | #define PFERR_USER_MASK (1U << 2) | |
82725b20 | 142 | #define PFERR_RSVD_MASK (1U << 3) |
73b1087e | 143 | #define PFERR_FETCH_MASK (1U << 4) |
6aa8b732 | 144 | |
e04da980 | 145 | #define PT_PDPE_LEVEL 3 |
6aa8b732 AK |
146 | #define PT_DIRECTORY_LEVEL 2 |
147 | #define PT_PAGE_TABLE_LEVEL 1 | |
148 | ||
cd4a4e53 AK |
149 | #define RMAP_EXT 4 |
150 | ||
fe135d2c AK |
151 | #define ACC_EXEC_MASK 1 |
152 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
153 | #define ACC_USER_MASK PT_USER_MASK | |
154 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
155 | ||
07420171 AK |
156 | #define CREATE_TRACE_POINTS |
157 | #include "mmutrace.h" | |
158 | ||
135f8c2b AK |
159 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
160 | ||
cd4a4e53 | 161 | struct kvm_rmap_desc { |
d555c333 | 162 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
163 | struct kvm_rmap_desc *more; |
164 | }; | |
165 | ||
2d11123a AK |
166 | struct kvm_shadow_walk_iterator { |
167 | u64 addr; | |
168 | hpa_t shadow_addr; | |
169 | int level; | |
170 | u64 *sptep; | |
171 | unsigned index; | |
172 | }; | |
173 | ||
174 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
175 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
176 | shadow_walk_okay(&(_walker)); \ | |
177 | shadow_walk_next(&(_walker))) | |
178 | ||
179 | ||
4731d4c7 MT |
180 | struct kvm_unsync_walk { |
181 | int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk); | |
182 | }; | |
183 | ||
ad8cfbe3 MT |
184 | typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp); |
185 | ||
b5a33a75 AK |
186 | static struct kmem_cache *pte_chain_cache; |
187 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 188 | static struct kmem_cache *mmu_page_header_cache; |
b5a33a75 | 189 | |
c7addb90 AK |
190 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
191 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
192 | static u64 __read_mostly shadow_base_present_pte; |
193 | static u64 __read_mostly shadow_nx_mask; | |
194 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
195 | static u64 __read_mostly shadow_user_mask; | |
196 | static u64 __read_mostly shadow_accessed_mask; | |
197 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 198 | |
82725b20 DE |
199 | static inline u64 rsvd_bits(int s, int e) |
200 | { | |
201 | return ((1ULL << (e - s + 1)) - 1) << s; | |
202 | } | |
203 | ||
c7addb90 AK |
204 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
205 | { | |
206 | shadow_trap_nonpresent_pte = trap_pte; | |
207 | shadow_notrap_nonpresent_pte = notrap_pte; | |
208 | } | |
209 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
210 | ||
7b52345e SY |
211 | void kvm_mmu_set_base_ptes(u64 base_pte) |
212 | { | |
213 | shadow_base_present_pte = base_pte; | |
214 | } | |
215 | EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes); | |
216 | ||
217 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
4b12f0de | 218 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
219 | { |
220 | shadow_user_mask = user_mask; | |
221 | shadow_accessed_mask = accessed_mask; | |
222 | shadow_dirty_mask = dirty_mask; | |
223 | shadow_nx_mask = nx_mask; | |
224 | shadow_x_mask = x_mask; | |
225 | } | |
226 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
227 | ||
6aa8b732 AK |
228 | static int is_write_protection(struct kvm_vcpu *vcpu) |
229 | { | |
ad312c7c | 230 | return vcpu->arch.cr0 & X86_CR0_WP; |
6aa8b732 AK |
231 | } |
232 | ||
233 | static int is_cpuid_PSE36(void) | |
234 | { | |
235 | return 1; | |
236 | } | |
237 | ||
73b1087e AK |
238 | static int is_nx(struct kvm_vcpu *vcpu) |
239 | { | |
ad312c7c | 240 | return vcpu->arch.shadow_efer & EFER_NX; |
73b1087e AK |
241 | } |
242 | ||
c7addb90 AK |
243 | static int is_shadow_present_pte(u64 pte) |
244 | { | |
c7addb90 AK |
245 | return pte != shadow_trap_nonpresent_pte |
246 | && pte != shadow_notrap_nonpresent_pte; | |
247 | } | |
248 | ||
05da4558 MT |
249 | static int is_large_pte(u64 pte) |
250 | { | |
251 | return pte & PT_PAGE_SIZE_MASK; | |
252 | } | |
253 | ||
6aa8b732 AK |
254 | static int is_writeble_pte(unsigned long pte) |
255 | { | |
256 | return pte & PT_WRITABLE_MASK; | |
257 | } | |
258 | ||
43a3795a | 259 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 260 | { |
439e218a | 261 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
262 | } |
263 | ||
43a3795a | 264 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 265 | { |
4b1a80fa | 266 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
267 | } |
268 | ||
776e6633 MT |
269 | static int is_last_spte(u64 pte, int level) |
270 | { | |
271 | if (level == PT_PAGE_TABLE_LEVEL) | |
272 | return 1; | |
852e3c19 | 273 | if (is_large_pte(pte)) |
776e6633 MT |
274 | return 1; |
275 | return 0; | |
276 | } | |
277 | ||
35149e21 | 278 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 279 | { |
35149e21 | 280 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
281 | } |
282 | ||
da928521 AK |
283 | static gfn_t pse36_gfn_delta(u32 gpte) |
284 | { | |
285 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
286 | ||
287 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
288 | } | |
289 | ||
d555c333 | 290 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 AK |
291 | { |
292 | #ifdef CONFIG_X86_64 | |
293 | set_64bit((unsigned long *)sptep, spte); | |
294 | #else | |
295 | set_64bit((unsigned long long *)sptep, spte); | |
296 | #endif | |
297 | } | |
298 | ||
e2dec939 | 299 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 300 | struct kmem_cache *base_cache, int min) |
714b93da AK |
301 | { |
302 | void *obj; | |
303 | ||
304 | if (cache->nobjs >= min) | |
e2dec939 | 305 | return 0; |
714b93da | 306 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 307 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 308 | if (!obj) |
e2dec939 | 309 | return -ENOMEM; |
714b93da AK |
310 | cache->objects[cache->nobjs++] = obj; |
311 | } | |
e2dec939 | 312 | return 0; |
714b93da AK |
313 | } |
314 | ||
315 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc) | |
316 | { | |
317 | while (mc->nobjs) | |
318 | kfree(mc->objects[--mc->nobjs]); | |
319 | } | |
320 | ||
c1158e63 | 321 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 322 | int min) |
c1158e63 AK |
323 | { |
324 | struct page *page; | |
325 | ||
326 | if (cache->nobjs >= min) | |
327 | return 0; | |
328 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 329 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
330 | if (!page) |
331 | return -ENOMEM; | |
332 | set_page_private(page, 0); | |
333 | cache->objects[cache->nobjs++] = page_address(page); | |
334 | } | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
339 | { | |
340 | while (mc->nobjs) | |
c4d198d5 | 341 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
342 | } |
343 | ||
2e3e5882 | 344 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 345 | { |
e2dec939 AK |
346 | int r; |
347 | ||
ad312c7c | 348 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 349 | pte_chain_cache, 4); |
e2dec939 AK |
350 | if (r) |
351 | goto out; | |
ad312c7c | 352 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
c41ef344 | 353 | rmap_desc_cache, 4); |
d3d25b04 AK |
354 | if (r) |
355 | goto out; | |
ad312c7c | 356 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
357 | if (r) |
358 | goto out; | |
ad312c7c | 359 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 360 | mmu_page_header_cache, 4); |
e2dec939 AK |
361 | out: |
362 | return r; | |
714b93da AK |
363 | } |
364 | ||
365 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
366 | { | |
ad312c7c ZX |
367 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache); |
368 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache); | |
369 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); | |
370 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
371 | } |
372 | ||
373 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
374 | size_t size) | |
375 | { | |
376 | void *p; | |
377 | ||
378 | BUG_ON(!mc->nobjs); | |
379 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
380 | return p; |
381 | } | |
382 | ||
714b93da AK |
383 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
384 | { | |
ad312c7c | 385 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
386 | sizeof(struct kvm_pte_chain)); |
387 | } | |
388 | ||
90cb0529 | 389 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 390 | { |
90cb0529 | 391 | kfree(pc); |
714b93da AK |
392 | } |
393 | ||
394 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
395 | { | |
ad312c7c | 396 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
397 | sizeof(struct kvm_rmap_desc)); |
398 | } | |
399 | ||
90cb0529 | 400 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 401 | { |
90cb0529 | 402 | kfree(rd); |
714b93da AK |
403 | } |
404 | ||
05da4558 MT |
405 | /* |
406 | * Return the pointer to the largepage write count for a given | |
407 | * gfn, handling slots that are not large page aligned. | |
408 | */ | |
d25797b2 JR |
409 | static int *slot_largepage_idx(gfn_t gfn, |
410 | struct kvm_memory_slot *slot, | |
411 | int level) | |
05da4558 MT |
412 | { |
413 | unsigned long idx; | |
414 | ||
d25797b2 JR |
415 | idx = (gfn / KVM_PAGES_PER_HPAGE(level)) - |
416 | (slot->base_gfn / KVM_PAGES_PER_HPAGE(level)); | |
417 | return &slot->lpage_info[level - 2][idx].write_count; | |
05da4558 MT |
418 | } |
419 | ||
420 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
421 | { | |
d25797b2 | 422 | struct kvm_memory_slot *slot; |
05da4558 | 423 | int *write_count; |
d25797b2 | 424 | int i; |
05da4558 | 425 | |
2843099f | 426 | gfn = unalias_gfn(kvm, gfn); |
d25797b2 JR |
427 | |
428 | slot = gfn_to_memslot_unaliased(kvm, gfn); | |
429 | for (i = PT_DIRECTORY_LEVEL; | |
430 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
431 | write_count = slot_largepage_idx(gfn, slot, i); | |
432 | *write_count += 1; | |
433 | } | |
05da4558 MT |
434 | } |
435 | ||
436 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
437 | { | |
d25797b2 | 438 | struct kvm_memory_slot *slot; |
05da4558 | 439 | int *write_count; |
d25797b2 | 440 | int i; |
05da4558 | 441 | |
2843099f | 442 | gfn = unalias_gfn(kvm, gfn); |
d25797b2 JR |
443 | for (i = PT_DIRECTORY_LEVEL; |
444 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
445 | slot = gfn_to_memslot_unaliased(kvm, gfn); | |
446 | write_count = slot_largepage_idx(gfn, slot, i); | |
447 | *write_count -= 1; | |
448 | WARN_ON(*write_count < 0); | |
449 | } | |
05da4558 MT |
450 | } |
451 | ||
d25797b2 JR |
452 | static int has_wrprotected_page(struct kvm *kvm, |
453 | gfn_t gfn, | |
454 | int level) | |
05da4558 | 455 | { |
2843099f | 456 | struct kvm_memory_slot *slot; |
05da4558 MT |
457 | int *largepage_idx; |
458 | ||
2843099f IE |
459 | gfn = unalias_gfn(kvm, gfn); |
460 | slot = gfn_to_memslot_unaliased(kvm, gfn); | |
05da4558 | 461 | if (slot) { |
d25797b2 | 462 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
463 | return *largepage_idx; |
464 | } | |
465 | ||
466 | return 1; | |
467 | } | |
468 | ||
d25797b2 | 469 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 470 | { |
d25797b2 | 471 | unsigned long page_size = PAGE_SIZE; |
05da4558 MT |
472 | struct vm_area_struct *vma; |
473 | unsigned long addr; | |
d25797b2 | 474 | int i, ret = 0; |
05da4558 MT |
475 | |
476 | addr = gfn_to_hva(kvm, gfn); | |
477 | if (kvm_is_error_hva(addr)) | |
d25797b2 | 478 | return page_size; |
05da4558 | 479 | |
4c2155ce | 480 | down_read(¤t->mm->mmap_sem); |
05da4558 | 481 | vma = find_vma(current->mm, addr); |
d25797b2 JR |
482 | if (!vma) |
483 | goto out; | |
484 | ||
485 | page_size = vma_kernel_pagesize(vma); | |
486 | ||
487 | out: | |
4c2155ce | 488 | up_read(¤t->mm->mmap_sem); |
05da4558 | 489 | |
d25797b2 JR |
490 | for (i = PT_PAGE_TABLE_LEVEL; |
491 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
492 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
493 | ret = i; | |
494 | else | |
495 | break; | |
496 | } | |
497 | ||
4c2155ce | 498 | return ret; |
05da4558 MT |
499 | } |
500 | ||
d25797b2 | 501 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
502 | { |
503 | struct kvm_memory_slot *slot; | |
d25797b2 JR |
504 | int host_level; |
505 | int level = PT_PAGE_TABLE_LEVEL; | |
05da4558 MT |
506 | |
507 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
508 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 509 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 510 | |
d25797b2 JR |
511 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
512 | ||
513 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
514 | return host_level; | |
515 | ||
516 | for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level) { | |
517 | ||
518 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) | |
519 | break; | |
520 | } | |
521 | ||
522 | return level - 1; | |
05da4558 MT |
523 | } |
524 | ||
290fc38d IE |
525 | /* |
526 | * Take gfn and return the reverse mapping to it. | |
527 | * Note: gfn must be unaliased before this function get called | |
528 | */ | |
529 | ||
44ad9944 | 530 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
531 | { |
532 | struct kvm_memory_slot *slot; | |
05da4558 | 533 | unsigned long idx; |
290fc38d IE |
534 | |
535 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 536 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
537 | return &slot->rmap[gfn - slot->base_gfn]; |
538 | ||
44ad9944 JR |
539 | idx = (gfn / KVM_PAGES_PER_HPAGE(level)) - |
540 | (slot->base_gfn / KVM_PAGES_PER_HPAGE(level)); | |
05da4558 | 541 | |
44ad9944 | 542 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
543 | } |
544 | ||
cd4a4e53 AK |
545 | /* |
546 | * Reverse mapping data structures: | |
547 | * | |
290fc38d IE |
548 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
549 | * that points to page_address(page). | |
cd4a4e53 | 550 | * |
290fc38d IE |
551 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
552 | * containing more mappings. | |
53a27b39 MT |
553 | * |
554 | * Returns the number of rmap entries before the spte was added or zero if | |
555 | * the spte was not added. | |
556 | * | |
cd4a4e53 | 557 | */ |
44ad9944 | 558 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 559 | { |
4db35314 | 560 | struct kvm_mmu_page *sp; |
cd4a4e53 | 561 | struct kvm_rmap_desc *desc; |
290fc38d | 562 | unsigned long *rmapp; |
53a27b39 | 563 | int i, count = 0; |
cd4a4e53 | 564 | |
43a3795a | 565 | if (!is_rmap_spte(*spte)) |
53a27b39 | 566 | return count; |
290fc38d | 567 | gfn = unalias_gfn(vcpu->kvm, gfn); |
4db35314 AK |
568 | sp = page_header(__pa(spte)); |
569 | sp->gfns[spte - sp->spt] = gfn; | |
44ad9944 | 570 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 571 | if (!*rmapp) { |
cd4a4e53 | 572 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
573 | *rmapp = (unsigned long)spte; |
574 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 575 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 576 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
577 | desc->sptes[0] = (u64 *)*rmapp; |
578 | desc->sptes[1] = spte; | |
290fc38d | 579 | *rmapp = (unsigned long)desc | 1; |
cd4a4e53 AK |
580 | } else { |
581 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 582 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 583 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 584 | desc = desc->more; |
53a27b39 MT |
585 | count += RMAP_EXT; |
586 | } | |
d555c333 | 587 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 588 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
589 | desc = desc->more; |
590 | } | |
d555c333 | 591 | for (i = 0; desc->sptes[i]; ++i) |
cd4a4e53 | 592 | ; |
d555c333 | 593 | desc->sptes[i] = spte; |
cd4a4e53 | 594 | } |
53a27b39 | 595 | return count; |
cd4a4e53 AK |
596 | } |
597 | ||
290fc38d | 598 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
599 | struct kvm_rmap_desc *desc, |
600 | int i, | |
601 | struct kvm_rmap_desc *prev_desc) | |
602 | { | |
603 | int j; | |
604 | ||
d555c333 | 605 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 606 | ; |
d555c333 AK |
607 | desc->sptes[i] = desc->sptes[j]; |
608 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
609 | if (j != 0) |
610 | return; | |
611 | if (!prev_desc && !desc->more) | |
d555c333 | 612 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
613 | else |
614 | if (prev_desc) | |
615 | prev_desc->more = desc->more; | |
616 | else | |
290fc38d | 617 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 618 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
619 | } |
620 | ||
290fc38d | 621 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 622 | { |
cd4a4e53 AK |
623 | struct kvm_rmap_desc *desc; |
624 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 625 | struct kvm_mmu_page *sp; |
35149e21 | 626 | pfn_t pfn; |
290fc38d | 627 | unsigned long *rmapp; |
cd4a4e53 AK |
628 | int i; |
629 | ||
43a3795a | 630 | if (!is_rmap_spte(*spte)) |
cd4a4e53 | 631 | return; |
4db35314 | 632 | sp = page_header(__pa(spte)); |
35149e21 | 633 | pfn = spte_to_pfn(*spte); |
7b52345e | 634 | if (*spte & shadow_accessed_mask) |
35149e21 | 635 | kvm_set_pfn_accessed(pfn); |
b4231d61 | 636 | if (is_writeble_pte(*spte)) |
35149e21 | 637 | kvm_release_pfn_dirty(pfn); |
b4231d61 | 638 | else |
35149e21 | 639 | kvm_release_pfn_clean(pfn); |
44ad9944 | 640 | rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level); |
290fc38d | 641 | if (!*rmapp) { |
cd4a4e53 AK |
642 | printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte); |
643 | BUG(); | |
290fc38d | 644 | } else if (!(*rmapp & 1)) { |
cd4a4e53 | 645 | rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte); |
290fc38d | 646 | if ((u64 *)*rmapp != spte) { |
cd4a4e53 AK |
647 | printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n", |
648 | spte, *spte); | |
649 | BUG(); | |
650 | } | |
290fc38d | 651 | *rmapp = 0; |
cd4a4e53 AK |
652 | } else { |
653 | rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte); | |
290fc38d | 654 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
655 | prev_desc = NULL; |
656 | while (desc) { | |
d555c333 AK |
657 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
658 | if (desc->sptes[i] == spte) { | |
290fc38d | 659 | rmap_desc_remove_entry(rmapp, |
714b93da | 660 | desc, i, |
cd4a4e53 AK |
661 | prev_desc); |
662 | return; | |
663 | } | |
664 | prev_desc = desc; | |
665 | desc = desc->more; | |
666 | } | |
667 | BUG(); | |
668 | } | |
669 | } | |
670 | ||
98348e95 | 671 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 672 | { |
374cbac0 | 673 | struct kvm_rmap_desc *desc; |
98348e95 IE |
674 | struct kvm_rmap_desc *prev_desc; |
675 | u64 *prev_spte; | |
676 | int i; | |
677 | ||
678 | if (!*rmapp) | |
679 | return NULL; | |
680 | else if (!(*rmapp & 1)) { | |
681 | if (!spte) | |
682 | return (u64 *)*rmapp; | |
683 | return NULL; | |
684 | } | |
685 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
686 | prev_desc = NULL; | |
687 | prev_spte = NULL; | |
688 | while (desc) { | |
d555c333 | 689 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 690 | if (prev_spte == spte) |
d555c333 AK |
691 | return desc->sptes[i]; |
692 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
693 | } |
694 | desc = desc->more; | |
695 | } | |
696 | return NULL; | |
697 | } | |
698 | ||
b1a36821 | 699 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 700 | { |
290fc38d | 701 | unsigned long *rmapp; |
374cbac0 | 702 | u64 *spte; |
44ad9944 | 703 | int i, write_protected = 0; |
374cbac0 | 704 | |
4a4c9924 | 705 | gfn = unalias_gfn(kvm, gfn); |
44ad9944 | 706 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 707 | |
98348e95 IE |
708 | spte = rmap_next(kvm, rmapp, NULL); |
709 | while (spte) { | |
374cbac0 | 710 | BUG_ON(!spte); |
374cbac0 | 711 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 712 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
caa5b8a5 | 713 | if (is_writeble_pte(*spte)) { |
d555c333 | 714 | __set_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
715 | write_protected = 1; |
716 | } | |
9647c14c | 717 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 718 | } |
855149aa | 719 | if (write_protected) { |
35149e21 | 720 | pfn_t pfn; |
855149aa IE |
721 | |
722 | spte = rmap_next(kvm, rmapp, NULL); | |
35149e21 AL |
723 | pfn = spte_to_pfn(*spte); |
724 | kvm_set_pfn_dirty(pfn); | |
855149aa IE |
725 | } |
726 | ||
05da4558 | 727 | /* check for huge page mappings */ |
44ad9944 JR |
728 | for (i = PT_DIRECTORY_LEVEL; |
729 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
730 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
731 | spte = rmap_next(kvm, rmapp, NULL); | |
732 | while (spte) { | |
733 | BUG_ON(!spte); | |
734 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
735 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
736 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
737 | if (is_writeble_pte(*spte)) { | |
738 | rmap_remove(kvm, spte); | |
739 | --kvm->stat.lpages; | |
740 | __set_spte(spte, shadow_trap_nonpresent_pte); | |
741 | spte = NULL; | |
742 | write_protected = 1; | |
743 | } | |
744 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 745 | } |
05da4558 MT |
746 | } |
747 | ||
b1a36821 | 748 | return write_protected; |
374cbac0 AK |
749 | } |
750 | ||
e930bffe AA |
751 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp) |
752 | { | |
753 | u64 *spte; | |
754 | int need_tlb_flush = 0; | |
755 | ||
756 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
757 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
758 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
759 | rmap_remove(kvm, spte); | |
d555c333 | 760 | __set_spte(spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
761 | need_tlb_flush = 1; |
762 | } | |
763 | return need_tlb_flush; | |
764 | } | |
765 | ||
766 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, | |
767 | int (*handler)(struct kvm *kvm, unsigned long *rmapp)) | |
768 | { | |
852e3c19 | 769 | int i, j; |
e930bffe AA |
770 | int retval = 0; |
771 | ||
772 | /* | |
773 | * If mmap_sem isn't taken, we can look the memslots with only | |
774 | * the mmu_lock by skipping over the slots with userspace_addr == 0. | |
775 | */ | |
776 | for (i = 0; i < kvm->nmemslots; i++) { | |
777 | struct kvm_memory_slot *memslot = &kvm->memslots[i]; | |
778 | unsigned long start = memslot->userspace_addr; | |
779 | unsigned long end; | |
780 | ||
781 | /* mmu_lock protects userspace_addr */ | |
782 | if (!start) | |
783 | continue; | |
784 | ||
785 | end = start + (memslot->npages << PAGE_SHIFT); | |
786 | if (hva >= start && hva < end) { | |
787 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 788 | |
e930bffe | 789 | retval |= handler(kvm, &memslot->rmap[gfn_offset]); |
852e3c19 JR |
790 | |
791 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
792 | int idx = gfn_offset; | |
793 | idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j); | |
794 | retval |= handler(kvm, | |
795 | &memslot->lpage_info[j][idx].rmap_pde); | |
796 | } | |
e930bffe AA |
797 | } |
798 | } | |
799 | ||
800 | return retval; | |
801 | } | |
802 | ||
803 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
804 | { | |
805 | return kvm_handle_hva(kvm, hva, kvm_unmap_rmapp); | |
806 | } | |
807 | ||
808 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp) | |
809 | { | |
810 | u64 *spte; | |
811 | int young = 0; | |
812 | ||
534e38b4 SY |
813 | /* always return old for EPT */ |
814 | if (!shadow_accessed_mask) | |
815 | return 0; | |
816 | ||
e930bffe AA |
817 | spte = rmap_next(kvm, rmapp, NULL); |
818 | while (spte) { | |
819 | int _young; | |
820 | u64 _spte = *spte; | |
821 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
822 | _young = _spte & PT_ACCESSED_MASK; | |
823 | if (_young) { | |
824 | young = 1; | |
825 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
826 | } | |
827 | spte = rmap_next(kvm, rmapp, spte); | |
828 | } | |
829 | return young; | |
830 | } | |
831 | ||
53a27b39 MT |
832 | #define RMAP_RECYCLE_THRESHOLD 1000 |
833 | ||
852e3c19 | 834 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
835 | { |
836 | unsigned long *rmapp; | |
852e3c19 JR |
837 | struct kvm_mmu_page *sp; |
838 | ||
839 | sp = page_header(__pa(spte)); | |
53a27b39 MT |
840 | |
841 | gfn = unalias_gfn(vcpu->kvm, gfn); | |
852e3c19 | 842 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 MT |
843 | |
844 | kvm_unmap_rmapp(vcpu->kvm, rmapp); | |
845 | kvm_flush_remote_tlbs(vcpu->kvm); | |
846 | } | |
847 | ||
e930bffe AA |
848 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
849 | { | |
850 | return kvm_handle_hva(kvm, hva, kvm_age_rmapp); | |
851 | } | |
852 | ||
d6c69ee9 | 853 | #ifdef MMU_DEBUG |
47ad8e68 | 854 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 855 | { |
139bdb2d AK |
856 | u64 *pos; |
857 | u64 *end; | |
858 | ||
47ad8e68 | 859 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 860 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 861 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 862 | pos, *pos); |
6aa8b732 | 863 | return 0; |
139bdb2d | 864 | } |
6aa8b732 AK |
865 | return 1; |
866 | } | |
d6c69ee9 | 867 | #endif |
6aa8b732 | 868 | |
4db35314 | 869 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 870 | { |
4db35314 AK |
871 | ASSERT(is_empty_shadow_page(sp->spt)); |
872 | list_del(&sp->link); | |
873 | __free_page(virt_to_page(sp->spt)); | |
874 | __free_page(virt_to_page(sp->gfns)); | |
875 | kfree(sp); | |
f05e70ac | 876 | ++kvm->arch.n_free_mmu_pages; |
260746c0 AK |
877 | } |
878 | ||
cea0f0e7 AK |
879 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
880 | { | |
1ae0a13d | 881 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
882 | } |
883 | ||
25c0de2c AK |
884 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
885 | u64 *parent_pte) | |
6aa8b732 | 886 | { |
4db35314 | 887 | struct kvm_mmu_page *sp; |
6aa8b732 | 888 | |
ad312c7c ZX |
889 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
890 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
891 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
4db35314 | 892 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 893 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
6cffe8ca | 894 | INIT_LIST_HEAD(&sp->oos_link); |
291f26bc | 895 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
896 | sp->multimapped = 0; |
897 | sp->parent_pte = parent_pte; | |
f05e70ac | 898 | --vcpu->kvm->arch.n_free_mmu_pages; |
4db35314 | 899 | return sp; |
6aa8b732 AK |
900 | } |
901 | ||
714b93da | 902 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 903 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
904 | { |
905 | struct kvm_pte_chain *pte_chain; | |
906 | struct hlist_node *node; | |
907 | int i; | |
908 | ||
909 | if (!parent_pte) | |
910 | return; | |
4db35314 AK |
911 | if (!sp->multimapped) { |
912 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
913 | |
914 | if (!old) { | |
4db35314 | 915 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
916 | return; |
917 | } | |
4db35314 | 918 | sp->multimapped = 1; |
714b93da | 919 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
920 | INIT_HLIST_HEAD(&sp->parent_ptes); |
921 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
922 | pte_chain->parent_ptes[0] = old; |
923 | } | |
4db35314 | 924 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
925 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
926 | continue; | |
927 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
928 | if (!pte_chain->parent_ptes[i]) { | |
929 | pte_chain->parent_ptes[i] = parent_pte; | |
930 | return; | |
931 | } | |
932 | } | |
714b93da | 933 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 934 | BUG_ON(!pte_chain); |
4db35314 | 935 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
936 | pte_chain->parent_ptes[0] = parent_pte; |
937 | } | |
938 | ||
4db35314 | 939 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
940 | u64 *parent_pte) |
941 | { | |
942 | struct kvm_pte_chain *pte_chain; | |
943 | struct hlist_node *node; | |
944 | int i; | |
945 | ||
4db35314 AK |
946 | if (!sp->multimapped) { |
947 | BUG_ON(sp->parent_pte != parent_pte); | |
948 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
949 | return; |
950 | } | |
4db35314 | 951 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
952 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
953 | if (!pte_chain->parent_ptes[i]) | |
954 | break; | |
955 | if (pte_chain->parent_ptes[i] != parent_pte) | |
956 | continue; | |
697fe2e2 AK |
957 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
958 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
959 | pte_chain->parent_ptes[i] |
960 | = pte_chain->parent_ptes[i + 1]; | |
961 | ++i; | |
962 | } | |
963 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
964 | if (i == 0) { |
965 | hlist_del(&pte_chain->link); | |
90cb0529 | 966 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
967 | if (hlist_empty(&sp->parent_ptes)) { |
968 | sp->multimapped = 0; | |
969 | sp->parent_pte = NULL; | |
697fe2e2 AK |
970 | } |
971 | } | |
cea0f0e7 AK |
972 | return; |
973 | } | |
974 | BUG(); | |
975 | } | |
976 | ||
ad8cfbe3 MT |
977 | |
978 | static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
979 | mmu_parent_walk_fn fn) | |
980 | { | |
981 | struct kvm_pte_chain *pte_chain; | |
982 | struct hlist_node *node; | |
983 | struct kvm_mmu_page *parent_sp; | |
984 | int i; | |
985 | ||
986 | if (!sp->multimapped && sp->parent_pte) { | |
987 | parent_sp = page_header(__pa(sp->parent_pte)); | |
988 | fn(vcpu, parent_sp); | |
989 | mmu_parent_walk(vcpu, parent_sp, fn); | |
990 | return; | |
991 | } | |
992 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) | |
993 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
994 | if (!pte_chain->parent_ptes[i]) | |
995 | break; | |
996 | parent_sp = page_header(__pa(pte_chain->parent_ptes[i])); | |
997 | fn(vcpu, parent_sp); | |
998 | mmu_parent_walk(vcpu, parent_sp, fn); | |
999 | } | |
1000 | } | |
1001 | ||
0074ff63 MT |
1002 | static void kvm_mmu_update_unsync_bitmap(u64 *spte) |
1003 | { | |
1004 | unsigned int index; | |
1005 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1006 | ||
1007 | index = spte - sp->spt; | |
60c8aec6 MT |
1008 | if (!__test_and_set_bit(index, sp->unsync_child_bitmap)) |
1009 | sp->unsync_children++; | |
1010 | WARN_ON(!sp->unsync_children); | |
0074ff63 MT |
1011 | } |
1012 | ||
1013 | static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp) | |
1014 | { | |
1015 | struct kvm_pte_chain *pte_chain; | |
1016 | struct hlist_node *node; | |
1017 | int i; | |
1018 | ||
1019 | if (!sp->parent_pte) | |
1020 | return; | |
1021 | ||
1022 | if (!sp->multimapped) { | |
1023 | kvm_mmu_update_unsync_bitmap(sp->parent_pte); | |
1024 | return; | |
1025 | } | |
1026 | ||
1027 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) | |
1028 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1029 | if (!pte_chain->parent_ptes[i]) | |
1030 | break; | |
1031 | kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]); | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) | |
1036 | { | |
0074ff63 MT |
1037 | kvm_mmu_update_parents_unsync(sp); |
1038 | return 1; | |
1039 | } | |
1040 | ||
1041 | static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu, | |
1042 | struct kvm_mmu_page *sp) | |
1043 | { | |
1044 | mmu_parent_walk(vcpu, sp, unsync_walk_fn); | |
1045 | kvm_mmu_update_parents_unsync(sp); | |
1046 | } | |
1047 | ||
d761a501 AK |
1048 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1049 | struct kvm_mmu_page *sp) | |
1050 | { | |
1051 | int i; | |
1052 | ||
1053 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1054 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1055 | } | |
1056 | ||
e8bc217a MT |
1057 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
1058 | struct kvm_mmu_page *sp) | |
1059 | { | |
1060 | return 1; | |
1061 | } | |
1062 | ||
a7052897 MT |
1063 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1064 | { | |
1065 | } | |
1066 | ||
60c8aec6 MT |
1067 | #define KVM_PAGE_ARRAY_NR 16 |
1068 | ||
1069 | struct kvm_mmu_pages { | |
1070 | struct mmu_page_and_offset { | |
1071 | struct kvm_mmu_page *sp; | |
1072 | unsigned int idx; | |
1073 | } page[KVM_PAGE_ARRAY_NR]; | |
1074 | unsigned int nr; | |
1075 | }; | |
1076 | ||
0074ff63 MT |
1077 | #define for_each_unsync_children(bitmap, idx) \ |
1078 | for (idx = find_first_bit(bitmap, 512); \ | |
1079 | idx < 512; \ | |
1080 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1081 | ||
cded19f3 HE |
1082 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1083 | int idx) | |
4731d4c7 | 1084 | { |
60c8aec6 | 1085 | int i; |
4731d4c7 | 1086 | |
60c8aec6 MT |
1087 | if (sp->unsync) |
1088 | for (i=0; i < pvec->nr; i++) | |
1089 | if (pvec->page[i].sp == sp) | |
1090 | return 0; | |
1091 | ||
1092 | pvec->page[pvec->nr].sp = sp; | |
1093 | pvec->page[pvec->nr].idx = idx; | |
1094 | pvec->nr++; | |
1095 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1096 | } | |
1097 | ||
1098 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1099 | struct kvm_mmu_pages *pvec) | |
1100 | { | |
1101 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1102 | |
0074ff63 | 1103 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
4731d4c7 MT |
1104 | u64 ent = sp->spt[i]; |
1105 | ||
87917239 | 1106 | if (is_shadow_present_pte(ent) && !is_large_pte(ent)) { |
4731d4c7 MT |
1107 | struct kvm_mmu_page *child; |
1108 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1109 | ||
1110 | if (child->unsync_children) { | |
60c8aec6 MT |
1111 | if (mmu_pages_add(pvec, child, i)) |
1112 | return -ENOSPC; | |
1113 | ||
1114 | ret = __mmu_unsync_walk(child, pvec); | |
1115 | if (!ret) | |
1116 | __clear_bit(i, sp->unsync_child_bitmap); | |
1117 | else if (ret > 0) | |
1118 | nr_unsync_leaf += ret; | |
1119 | else | |
4731d4c7 MT |
1120 | return ret; |
1121 | } | |
1122 | ||
1123 | if (child->unsync) { | |
60c8aec6 MT |
1124 | nr_unsync_leaf++; |
1125 | if (mmu_pages_add(pvec, child, i)) | |
1126 | return -ENOSPC; | |
4731d4c7 MT |
1127 | } |
1128 | } | |
1129 | } | |
1130 | ||
0074ff63 | 1131 | if (find_first_bit(sp->unsync_child_bitmap, 512) == 512) |
4731d4c7 MT |
1132 | sp->unsync_children = 0; |
1133 | ||
60c8aec6 MT |
1134 | return nr_unsync_leaf; |
1135 | } | |
1136 | ||
1137 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1138 | struct kvm_mmu_pages *pvec) | |
1139 | { | |
1140 | if (!sp->unsync_children) | |
1141 | return 0; | |
1142 | ||
1143 | mmu_pages_add(pvec, sp, 0); | |
1144 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1145 | } |
1146 | ||
4db35314 | 1147 | static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn) |
cea0f0e7 AK |
1148 | { |
1149 | unsigned index; | |
1150 | struct hlist_head *bucket; | |
4db35314 | 1151 | struct kvm_mmu_page *sp; |
cea0f0e7 AK |
1152 | struct hlist_node *node; |
1153 | ||
b8688d51 | 1154 | pgprintk("%s: looking for gfn %lx\n", __func__, gfn); |
1ae0a13d | 1155 | index = kvm_page_table_hashfn(gfn); |
f05e70ac | 1156 | bucket = &kvm->arch.mmu_page_hash[index]; |
4db35314 | 1157 | hlist_for_each_entry(sp, node, bucket, hash_link) |
f6e2c02b | 1158 | if (sp->gfn == gfn && !sp->role.direct |
2e53d63a | 1159 | && !sp->role.invalid) { |
cea0f0e7 | 1160 | pgprintk("%s: found role %x\n", |
b8688d51 | 1161 | __func__, sp->role.word); |
4db35314 | 1162 | return sp; |
cea0f0e7 AK |
1163 | } |
1164 | return NULL; | |
1165 | } | |
1166 | ||
4731d4c7 MT |
1167 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1168 | { | |
1169 | WARN_ON(!sp->unsync); | |
1170 | sp->unsync = 0; | |
1171 | --kvm->stat.mmu_unsync; | |
1172 | } | |
1173 | ||
1174 | static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp); | |
1175 | ||
1176 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) | |
1177 | { | |
1178 | if (sp->role.glevels != vcpu->arch.mmu.root_level) { | |
1179 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
1180 | return 1; | |
1181 | } | |
1182 | ||
f691fe1d | 1183 | trace_kvm_mmu_sync_page(sp); |
b1a36821 MT |
1184 | if (rmap_write_protect(vcpu->kvm, sp->gfn)) |
1185 | kvm_flush_remote_tlbs(vcpu->kvm); | |
0c0f40bd | 1186 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
4731d4c7 MT |
1187 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
1188 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
1189 | return 1; | |
1190 | } | |
1191 | ||
1192 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1193 | return 0; |
1194 | } | |
1195 | ||
60c8aec6 MT |
1196 | struct mmu_page_path { |
1197 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1198 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1199 | }; |
1200 | ||
60c8aec6 MT |
1201 | #define for_each_sp(pvec, sp, parents, i) \ |
1202 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1203 | sp = pvec.page[i].sp; \ | |
1204 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1205 | i = mmu_pages_next(&pvec, &parents, i)) | |
1206 | ||
cded19f3 HE |
1207 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1208 | struct mmu_page_path *parents, | |
1209 | int i) | |
60c8aec6 MT |
1210 | { |
1211 | int n; | |
1212 | ||
1213 | for (n = i+1; n < pvec->nr; n++) { | |
1214 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1215 | ||
1216 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1217 | parents->idx[0] = pvec->page[n].idx; | |
1218 | return n; | |
1219 | } | |
1220 | ||
1221 | parents->parent[sp->role.level-2] = sp; | |
1222 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1223 | } | |
1224 | ||
1225 | return n; | |
1226 | } | |
1227 | ||
cded19f3 | 1228 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1229 | { |
60c8aec6 MT |
1230 | struct kvm_mmu_page *sp; |
1231 | unsigned int level = 0; | |
1232 | ||
1233 | do { | |
1234 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1235 | |
60c8aec6 MT |
1236 | sp = parents->parent[level]; |
1237 | if (!sp) | |
1238 | return; | |
1239 | ||
1240 | --sp->unsync_children; | |
1241 | WARN_ON((int)sp->unsync_children < 0); | |
1242 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1243 | level++; | |
1244 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1245 | } |
1246 | ||
60c8aec6 MT |
1247 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1248 | struct mmu_page_path *parents, | |
1249 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1250 | { |
60c8aec6 MT |
1251 | parents->parent[parent->role.level-1] = NULL; |
1252 | pvec->nr = 0; | |
1253 | } | |
4731d4c7 | 1254 | |
60c8aec6 MT |
1255 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1256 | struct kvm_mmu_page *parent) | |
1257 | { | |
1258 | int i; | |
1259 | struct kvm_mmu_page *sp; | |
1260 | struct mmu_page_path parents; | |
1261 | struct kvm_mmu_pages pages; | |
1262 | ||
1263 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1264 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1265 | int protected = 0; |
1266 | ||
1267 | for_each_sp(pages, sp, parents, i) | |
1268 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1269 | ||
1270 | if (protected) | |
1271 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1272 | ||
60c8aec6 MT |
1273 | for_each_sp(pages, sp, parents, i) { |
1274 | kvm_sync_page(vcpu, sp); | |
1275 | mmu_pages_clear_parents(&parents); | |
1276 | } | |
4731d4c7 | 1277 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1278 | kvm_mmu_pages_init(parent, &parents, &pages); |
1279 | } | |
4731d4c7 MT |
1280 | } |
1281 | ||
cea0f0e7 AK |
1282 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1283 | gfn_t gfn, | |
1284 | gva_t gaddr, | |
1285 | unsigned level, | |
f6e2c02b | 1286 | int direct, |
41074d07 | 1287 | unsigned access, |
f7d9c7b7 | 1288 | u64 *parent_pte) |
cea0f0e7 AK |
1289 | { |
1290 | union kvm_mmu_page_role role; | |
1291 | unsigned index; | |
1292 | unsigned quadrant; | |
1293 | struct hlist_head *bucket; | |
4db35314 | 1294 | struct kvm_mmu_page *sp; |
4731d4c7 | 1295 | struct hlist_node *node, *tmp; |
cea0f0e7 | 1296 | |
a770f6f2 | 1297 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1298 | role.level = level; |
f6e2c02b | 1299 | role.direct = direct; |
41074d07 | 1300 | role.access = access; |
ad312c7c | 1301 | if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
1302 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1303 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1304 | role.quadrant = quadrant; | |
1305 | } | |
1ae0a13d | 1306 | index = kvm_page_table_hashfn(gfn); |
f05e70ac | 1307 | bucket = &vcpu->kvm->arch.mmu_page_hash[index]; |
4731d4c7 MT |
1308 | hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link) |
1309 | if (sp->gfn == gfn) { | |
1310 | if (sp->unsync) | |
1311 | if (kvm_sync_page(vcpu, sp)) | |
1312 | continue; | |
1313 | ||
1314 | if (sp->role.word != role.word) | |
1315 | continue; | |
1316 | ||
4db35314 | 1317 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
0074ff63 MT |
1318 | if (sp->unsync_children) { |
1319 | set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests); | |
1320 | kvm_mmu_mark_parents_unsync(vcpu, sp); | |
1321 | } | |
f691fe1d | 1322 | trace_kvm_mmu_get_page(sp, false); |
4db35314 | 1323 | return sp; |
cea0f0e7 | 1324 | } |
dfc5aa00 | 1325 | ++vcpu->kvm->stat.mmu_cache_miss; |
4db35314 AK |
1326 | sp = kvm_mmu_alloc_page(vcpu, parent_pte); |
1327 | if (!sp) | |
1328 | return sp; | |
4db35314 AK |
1329 | sp->gfn = gfn; |
1330 | sp->role = role; | |
1331 | hlist_add_head(&sp->hash_link, bucket); | |
f6e2c02b | 1332 | if (!direct) { |
b1a36821 MT |
1333 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1334 | kvm_flush_remote_tlbs(vcpu->kvm); | |
4731d4c7 MT |
1335 | account_shadowed(vcpu->kvm, gfn); |
1336 | } | |
131d8279 AK |
1337 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1338 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1339 | else | |
1340 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1341 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1342 | return sp; |
cea0f0e7 AK |
1343 | } |
1344 | ||
2d11123a AK |
1345 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1346 | struct kvm_vcpu *vcpu, u64 addr) | |
1347 | { | |
1348 | iterator->addr = addr; | |
1349 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1350 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
1351 | if (iterator->level == PT32E_ROOT_LEVEL) { | |
1352 | iterator->shadow_addr | |
1353 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1354 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1355 | --iterator->level; | |
1356 | if (!iterator->shadow_addr) | |
1357 | iterator->level = 0; | |
1358 | } | |
1359 | } | |
1360 | ||
1361 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1362 | { | |
1363 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1364 | return false; | |
4d88954d MT |
1365 | |
1366 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1367 | if (is_large_pte(*iterator->sptep)) | |
1368 | return false; | |
1369 | ||
2d11123a AK |
1370 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1371 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1372 | return true; | |
1373 | } | |
1374 | ||
1375 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1376 | { | |
1377 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1378 | --iterator->level; | |
1379 | } | |
1380 | ||
90cb0529 | 1381 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1382 | struct kvm_mmu_page *sp) |
a436036b | 1383 | { |
697fe2e2 AK |
1384 | unsigned i; |
1385 | u64 *pt; | |
1386 | u64 ent; | |
1387 | ||
4db35314 | 1388 | pt = sp->spt; |
697fe2e2 | 1389 | |
697fe2e2 AK |
1390 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1391 | ent = pt[i]; | |
1392 | ||
05da4558 | 1393 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1394 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1395 | ent &= PT64_BASE_ADDR_MASK; |
1396 | mmu_page_remove_parent_pte(page_header(ent), | |
1397 | &pt[i]); | |
1398 | } else { | |
776e6633 MT |
1399 | if (is_large_pte(ent)) |
1400 | --kvm->stat.lpages; | |
05da4558 MT |
1401 | rmap_remove(kvm, &pt[i]); |
1402 | } | |
1403 | } | |
c7addb90 | 1404 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1405 | } |
a436036b AK |
1406 | } |
1407 | ||
4db35314 | 1408 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1409 | { |
4db35314 | 1410 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1411 | } |
1412 | ||
12b7d28f AK |
1413 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1414 | { | |
1415 | int i; | |
988a2cae | 1416 | struct kvm_vcpu *vcpu; |
12b7d28f | 1417 | |
988a2cae GN |
1418 | kvm_for_each_vcpu(i, vcpu, kvm) |
1419 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1420 | } |
1421 | ||
31aa2b44 | 1422 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1423 | { |
1424 | u64 *parent_pte; | |
1425 | ||
4db35314 AK |
1426 | while (sp->multimapped || sp->parent_pte) { |
1427 | if (!sp->multimapped) | |
1428 | parent_pte = sp->parent_pte; | |
a436036b AK |
1429 | else { |
1430 | struct kvm_pte_chain *chain; | |
1431 | ||
4db35314 | 1432 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1433 | struct kvm_pte_chain, link); |
1434 | parent_pte = chain->parent_ptes[0]; | |
1435 | } | |
697fe2e2 | 1436 | BUG_ON(!parent_pte); |
4db35314 | 1437 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1438 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1439 | } |
31aa2b44 AK |
1440 | } |
1441 | ||
60c8aec6 MT |
1442 | static int mmu_zap_unsync_children(struct kvm *kvm, |
1443 | struct kvm_mmu_page *parent) | |
4731d4c7 | 1444 | { |
60c8aec6 MT |
1445 | int i, zapped = 0; |
1446 | struct mmu_page_path parents; | |
1447 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1448 | |
60c8aec6 | 1449 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1450 | return 0; |
60c8aec6 MT |
1451 | |
1452 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1453 | while (mmu_unsync_walk(parent, &pages)) { | |
1454 | struct kvm_mmu_page *sp; | |
1455 | ||
1456 | for_each_sp(pages, sp, parents, i) { | |
1457 | kvm_mmu_zap_page(kvm, sp); | |
1458 | mmu_pages_clear_parents(&parents); | |
1459 | } | |
1460 | zapped += pages.nr; | |
1461 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1462 | } | |
1463 | ||
1464 | return zapped; | |
4731d4c7 MT |
1465 | } |
1466 | ||
07385413 | 1467 | static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
31aa2b44 | 1468 | { |
4731d4c7 | 1469 | int ret; |
f691fe1d AK |
1470 | |
1471 | trace_kvm_mmu_zap_page(sp); | |
31aa2b44 | 1472 | ++kvm->stat.mmu_shadow_zapped; |
4731d4c7 | 1473 | ret = mmu_zap_unsync_children(kvm, sp); |
4db35314 | 1474 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1475 | kvm_mmu_unlink_parents(kvm, sp); |
5b5c6a5a | 1476 | kvm_flush_remote_tlbs(kvm); |
f6e2c02b | 1477 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1478 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1479 | if (sp->unsync) |
1480 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 AK |
1481 | if (!sp->root_count) { |
1482 | hlist_del(&sp->hash_link); | |
1483 | kvm_mmu_free_page(kvm, sp); | |
2e53d63a | 1484 | } else { |
2e53d63a | 1485 | sp->role.invalid = 1; |
5b5c6a5a | 1486 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1487 | kvm_reload_remote_mmus(kvm); |
1488 | } | |
12b7d28f | 1489 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1490 | return ret; |
a436036b AK |
1491 | } |
1492 | ||
82ce2c96 IE |
1493 | /* |
1494 | * Changing the number of mmu pages allocated to the vm | |
1495 | * Note: if kvm_nr_mmu_pages is too small, you will get dead lock | |
1496 | */ | |
1497 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages) | |
1498 | { | |
025dbbf3 MT |
1499 | int used_pages; |
1500 | ||
1501 | used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages; | |
1502 | used_pages = max(0, used_pages); | |
1503 | ||
82ce2c96 IE |
1504 | /* |
1505 | * If we set the number of mmu pages to be smaller be than the | |
1506 | * number of actived pages , we must to free some mmu pages before we | |
1507 | * change the value | |
1508 | */ | |
1509 | ||
025dbbf3 MT |
1510 | if (used_pages > kvm_nr_mmu_pages) { |
1511 | while (used_pages > kvm_nr_mmu_pages) { | |
82ce2c96 IE |
1512 | struct kvm_mmu_page *page; |
1513 | ||
f05e70ac | 1514 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 IE |
1515 | struct kvm_mmu_page, link); |
1516 | kvm_mmu_zap_page(kvm, page); | |
025dbbf3 | 1517 | used_pages--; |
82ce2c96 | 1518 | } |
f05e70ac | 1519 | kvm->arch.n_free_mmu_pages = 0; |
82ce2c96 IE |
1520 | } |
1521 | else | |
f05e70ac ZX |
1522 | kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages |
1523 | - kvm->arch.n_alloc_mmu_pages; | |
82ce2c96 | 1524 | |
f05e70ac | 1525 | kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages; |
82ce2c96 IE |
1526 | } |
1527 | ||
f67a46f4 | 1528 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b AK |
1529 | { |
1530 | unsigned index; | |
1531 | struct hlist_head *bucket; | |
4db35314 | 1532 | struct kvm_mmu_page *sp; |
a436036b AK |
1533 | struct hlist_node *node, *n; |
1534 | int r; | |
1535 | ||
b8688d51 | 1536 | pgprintk("%s: looking for gfn %lx\n", __func__, gfn); |
a436036b | 1537 | r = 0; |
1ae0a13d | 1538 | index = kvm_page_table_hashfn(gfn); |
f05e70ac | 1539 | bucket = &kvm->arch.mmu_page_hash[index]; |
4db35314 | 1540 | hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) |
f6e2c02b | 1541 | if (sp->gfn == gfn && !sp->role.direct) { |
b8688d51 | 1542 | pgprintk("%s: gfn %lx role %x\n", __func__, gfn, |
4db35314 | 1543 | sp->role.word); |
a436036b | 1544 | r = 1; |
07385413 MT |
1545 | if (kvm_mmu_zap_page(kvm, sp)) |
1546 | n = bucket->first; | |
a436036b AK |
1547 | } |
1548 | return r; | |
cea0f0e7 AK |
1549 | } |
1550 | ||
f67a46f4 | 1551 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1552 | { |
4677a3b6 AK |
1553 | unsigned index; |
1554 | struct hlist_head *bucket; | |
4db35314 | 1555 | struct kvm_mmu_page *sp; |
4677a3b6 | 1556 | struct hlist_node *node, *nn; |
97a0a01e | 1557 | |
4677a3b6 AK |
1558 | index = kvm_page_table_hashfn(gfn); |
1559 | bucket = &kvm->arch.mmu_page_hash[index]; | |
1560 | hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) { | |
f6e2c02b | 1561 | if (sp->gfn == gfn && !sp->role.direct |
4677a3b6 AK |
1562 | && !sp->role.invalid) { |
1563 | pgprintk("%s: zap %lx %x\n", | |
1564 | __func__, gfn, sp->role.word); | |
1565 | kvm_mmu_zap_page(kvm, sp); | |
1566 | } | |
97a0a01e AK |
1567 | } |
1568 | } | |
1569 | ||
38c335f1 | 1570 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1571 | { |
38c335f1 | 1572 | int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn)); |
4db35314 | 1573 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1574 | |
291f26bc | 1575 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1576 | } |
1577 | ||
6844dec6 MT |
1578 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1579 | { | |
1580 | int i; | |
1581 | u64 *pt = sp->spt; | |
1582 | ||
1583 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1584 | return; | |
1585 | ||
1586 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1587 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1588 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1589 | } |
1590 | } | |
1591 | ||
039576c0 AK |
1592 | struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva) |
1593 | { | |
72dc67a6 IE |
1594 | struct page *page; |
1595 | ||
ad312c7c | 1596 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva); |
039576c0 AK |
1597 | |
1598 | if (gpa == UNMAPPED_GVA) | |
1599 | return NULL; | |
72dc67a6 | 1600 | |
72dc67a6 | 1601 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 IE |
1602 | |
1603 | return page; | |
039576c0 AK |
1604 | } |
1605 | ||
74be52e3 SY |
1606 | /* |
1607 | * The function is based on mtrr_type_lookup() in | |
1608 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1609 | */ | |
1610 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1611 | u64 start, u64 end) | |
1612 | { | |
1613 | int i; | |
1614 | u64 base, mask; | |
1615 | u8 prev_match, curr_match; | |
1616 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1617 | ||
1618 | if (!mtrr_state->enabled) | |
1619 | return 0xFF; | |
1620 | ||
1621 | /* Make end inclusive end, instead of exclusive */ | |
1622 | end--; | |
1623 | ||
1624 | /* Look in fixed ranges. Just return the type as per start */ | |
1625 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1626 | int idx; | |
1627 | ||
1628 | if (start < 0x80000) { | |
1629 | idx = 0; | |
1630 | idx += (start >> 16); | |
1631 | return mtrr_state->fixed_ranges[idx]; | |
1632 | } else if (start < 0xC0000) { | |
1633 | idx = 1 * 8; | |
1634 | idx += ((start - 0x80000) >> 14); | |
1635 | return mtrr_state->fixed_ranges[idx]; | |
1636 | } else if (start < 0x1000000) { | |
1637 | idx = 3 * 8; | |
1638 | idx += ((start - 0xC0000) >> 12); | |
1639 | return mtrr_state->fixed_ranges[idx]; | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | /* | |
1644 | * Look in variable ranges | |
1645 | * Look of multiple ranges matching this address and pick type | |
1646 | * as per MTRR precedence | |
1647 | */ | |
1648 | if (!(mtrr_state->enabled & 2)) | |
1649 | return mtrr_state->def_type; | |
1650 | ||
1651 | prev_match = 0xFF; | |
1652 | for (i = 0; i < num_var_ranges; ++i) { | |
1653 | unsigned short start_state, end_state; | |
1654 | ||
1655 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1656 | continue; | |
1657 | ||
1658 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1659 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1660 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1661 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1662 | ||
1663 | start_state = ((start & mask) == (base & mask)); | |
1664 | end_state = ((end & mask) == (base & mask)); | |
1665 | if (start_state != end_state) | |
1666 | return 0xFE; | |
1667 | ||
1668 | if ((start & mask) != (base & mask)) | |
1669 | continue; | |
1670 | ||
1671 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1672 | if (prev_match == 0xFF) { | |
1673 | prev_match = curr_match; | |
1674 | continue; | |
1675 | } | |
1676 | ||
1677 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1678 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1679 | return MTRR_TYPE_UNCACHABLE; | |
1680 | ||
1681 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1682 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1683 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1684 | curr_match == MTRR_TYPE_WRBACK)) { | |
1685 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1686 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1687 | } | |
1688 | ||
1689 | if (prev_match != curr_match) | |
1690 | return MTRR_TYPE_UNCACHABLE; | |
1691 | } | |
1692 | ||
1693 | if (prev_match != 0xFF) | |
1694 | return prev_match; | |
1695 | ||
1696 | return mtrr_state->def_type; | |
1697 | } | |
1698 | ||
4b12f0de | 1699 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1700 | { |
1701 | u8 mtrr; | |
1702 | ||
1703 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1704 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1705 | if (mtrr == 0xfe || mtrr == 0xff) | |
1706 | mtrr = MTRR_TYPE_WRBACK; | |
1707 | return mtrr; | |
1708 | } | |
4b12f0de | 1709 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1710 | |
4731d4c7 MT |
1711 | static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1712 | { | |
1713 | unsigned index; | |
1714 | struct hlist_head *bucket; | |
1715 | struct kvm_mmu_page *s; | |
1716 | struct hlist_node *node, *n; | |
1717 | ||
f691fe1d | 1718 | trace_kvm_mmu_unsync_page(sp); |
4731d4c7 MT |
1719 | index = kvm_page_table_hashfn(sp->gfn); |
1720 | bucket = &vcpu->kvm->arch.mmu_page_hash[index]; | |
1721 | /* don't unsync if pagetable is shadowed with multiple roles */ | |
1722 | hlist_for_each_entry_safe(s, node, n, bucket, hash_link) { | |
f6e2c02b | 1723 | if (s->gfn != sp->gfn || s->role.direct) |
4731d4c7 MT |
1724 | continue; |
1725 | if (s->role.word != sp->role.word) | |
1726 | return 1; | |
1727 | } | |
4731d4c7 MT |
1728 | ++vcpu->kvm->stat.mmu_unsync; |
1729 | sp->unsync = 1; | |
6cffe8ca | 1730 | |
c2d0ee46 | 1731 | kvm_mmu_mark_parents_unsync(vcpu, sp); |
6cffe8ca | 1732 | |
4731d4c7 MT |
1733 | mmu_convert_notrap(sp); |
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1738 | bool can_unsync) | |
1739 | { | |
1740 | struct kvm_mmu_page *shadow; | |
1741 | ||
1742 | shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn); | |
1743 | if (shadow) { | |
1744 | if (shadow->role.level != PT_PAGE_TABLE_LEVEL) | |
1745 | return 1; | |
1746 | if (shadow->unsync) | |
1747 | return 0; | |
582801a9 | 1748 | if (can_unsync && oos_shadow) |
4731d4c7 MT |
1749 | return kvm_unsync_page(vcpu, shadow); |
1750 | return 1; | |
1751 | } | |
1752 | return 0; | |
1753 | } | |
1754 | ||
d555c333 | 1755 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1756 | unsigned pte_access, int user_fault, |
852e3c19 | 1757 | int write_fault, int dirty, int level, |
c2d0ee46 | 1758 | gfn_t gfn, pfn_t pfn, bool speculative, |
4731d4c7 | 1759 | bool can_unsync) |
1c4f1fd6 AK |
1760 | { |
1761 | u64 spte; | |
1e73f9dd | 1762 | int ret = 0; |
64d4d521 | 1763 | |
1c4f1fd6 AK |
1764 | /* |
1765 | * We don't set the accessed bit, since we sometimes want to see | |
1766 | * whether the guest actually used the pte (in order to detect | |
1767 | * demand paging). | |
1768 | */ | |
7b52345e | 1769 | spte = shadow_base_present_pte | shadow_dirty_mask; |
947da538 | 1770 | if (!speculative) |
3201b5d9 | 1771 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1772 | if (!dirty) |
1773 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1774 | if (pte_access & ACC_EXEC_MASK) |
1775 | spte |= shadow_x_mask; | |
1776 | else | |
1777 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1778 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1779 | spte |= shadow_user_mask; |
852e3c19 | 1780 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1781 | spte |= PT_PAGE_SIZE_MASK; |
4b12f0de SY |
1782 | if (tdp_enabled) |
1783 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, | |
1784 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1785 | |
35149e21 | 1786 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1787 | |
1788 | if ((pte_access & ACC_WRITE_MASK) | |
1789 | || (write_fault && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 1790 | |
852e3c19 JR |
1791 | if (level > PT_PAGE_TABLE_LEVEL && |
1792 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 MT |
1793 | ret = 1; |
1794 | spte = shadow_trap_nonpresent_pte; | |
1795 | goto set_pte; | |
1796 | } | |
1797 | ||
1c4f1fd6 | 1798 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1799 | |
ecc5589f MT |
1800 | /* |
1801 | * Optimization: for pte sync, if spte was writable the hash | |
1802 | * lookup is unnecessary (and expensive). Write protection | |
1803 | * is responsibility of mmu_get_page / kvm_sync_page. | |
1804 | * Same reasoning can be applied to dirty page accounting. | |
1805 | */ | |
d555c333 | 1806 | if (!can_unsync && is_writeble_pte(*sptep)) |
ecc5589f MT |
1807 | goto set_pte; |
1808 | ||
4731d4c7 | 1809 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
1c4f1fd6 | 1810 | pgprintk("%s: found shadow page for %lx, marking ro\n", |
b8688d51 | 1811 | __func__, gfn); |
1e73f9dd | 1812 | ret = 1; |
1c4f1fd6 | 1813 | pte_access &= ~ACC_WRITE_MASK; |
a378b4e6 | 1814 | if (is_writeble_pte(spte)) |
1c4f1fd6 | 1815 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
1816 | } |
1817 | } | |
1818 | ||
1c4f1fd6 AK |
1819 | if (pte_access & ACC_WRITE_MASK) |
1820 | mark_page_dirty(vcpu->kvm, gfn); | |
1821 | ||
38187c83 | 1822 | set_pte: |
d555c333 | 1823 | __set_spte(sptep, spte); |
1e73f9dd MT |
1824 | return ret; |
1825 | } | |
1826 | ||
d555c333 | 1827 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
1828 | unsigned pt_access, unsigned pte_access, |
1829 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 1830 | int *ptwrite, int level, gfn_t gfn, |
c2d0ee46 | 1831 | pfn_t pfn, bool speculative) |
1e73f9dd MT |
1832 | { |
1833 | int was_rmapped = 0; | |
d555c333 | 1834 | int was_writeble = is_writeble_pte(*sptep); |
53a27b39 | 1835 | int rmap_count; |
1e73f9dd MT |
1836 | |
1837 | pgprintk("%s: spte %llx access %x write_fault %d" | |
1838 | " user_fault %d gfn %lx\n", | |
d555c333 | 1839 | __func__, *sptep, pt_access, |
1e73f9dd MT |
1840 | write_fault, user_fault, gfn); |
1841 | ||
d555c333 | 1842 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
1843 | /* |
1844 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
1845 | * the parent of the now unreachable PTE. | |
1846 | */ | |
852e3c19 JR |
1847 | if (level > PT_PAGE_TABLE_LEVEL && |
1848 | !is_large_pte(*sptep)) { | |
1e73f9dd | 1849 | struct kvm_mmu_page *child; |
d555c333 | 1850 | u64 pte = *sptep; |
1e73f9dd MT |
1851 | |
1852 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 AK |
1853 | mmu_page_remove_parent_pte(child, sptep); |
1854 | } else if (pfn != spte_to_pfn(*sptep)) { | |
1e73f9dd | 1855 | pgprintk("hfn old %lx new %lx\n", |
d555c333 AK |
1856 | spte_to_pfn(*sptep), pfn); |
1857 | rmap_remove(vcpu->kvm, sptep); | |
6bed6b9e JR |
1858 | } else |
1859 | was_rmapped = 1; | |
1e73f9dd | 1860 | } |
852e3c19 | 1861 | |
d555c333 | 1862 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
852e3c19 | 1863 | dirty, level, gfn, pfn, speculative, true)) { |
1e73f9dd MT |
1864 | if (write_fault) |
1865 | *ptwrite = 1; | |
a378b4e6 MT |
1866 | kvm_x86_ops->tlb_flush(vcpu); |
1867 | } | |
1e73f9dd | 1868 | |
d555c333 | 1869 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
1e73f9dd | 1870 | pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n", |
d555c333 | 1871 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
1872 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
1873 | *sptep, sptep); | |
d555c333 | 1874 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
1875 | ++vcpu->kvm->stat.lpages; |
1876 | ||
d555c333 | 1877 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 1878 | if (!was_rmapped) { |
44ad9944 | 1879 | rmap_count = rmap_add(vcpu, sptep, gfn); |
d555c333 | 1880 | if (!is_rmap_spte(*sptep)) |
35149e21 | 1881 | kvm_release_pfn_clean(pfn); |
53a27b39 | 1882 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 1883 | rmap_recycle(vcpu, sptep, gfn); |
75e68e60 IE |
1884 | } else { |
1885 | if (was_writeble) | |
35149e21 | 1886 | kvm_release_pfn_dirty(pfn); |
75e68e60 | 1887 | else |
35149e21 | 1888 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 | 1889 | } |
1b7fcd32 | 1890 | if (speculative) { |
d555c333 | 1891 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
1892 | vcpu->arch.last_pte_gfn = gfn; |
1893 | } | |
1c4f1fd6 AK |
1894 | } |
1895 | ||
6aa8b732 AK |
1896 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
1897 | { | |
1898 | } | |
1899 | ||
9f652d21 | 1900 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
852e3c19 | 1901 | int level, gfn_t gfn, pfn_t pfn) |
140754bc | 1902 | { |
9f652d21 | 1903 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 1904 | struct kvm_mmu_page *sp; |
9f652d21 | 1905 | int pt_write = 0; |
140754bc | 1906 | gfn_t pseudo_gfn; |
6aa8b732 | 1907 | |
9f652d21 | 1908 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 1909 | if (iterator.level == level) { |
9f652d21 AK |
1910 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL, |
1911 | 0, write, 1, &pt_write, | |
852e3c19 | 1912 | level, gfn, pfn, false); |
9f652d21 AK |
1913 | ++vcpu->stat.pf_fixed; |
1914 | break; | |
6aa8b732 AK |
1915 | } |
1916 | ||
9f652d21 AK |
1917 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
1918 | pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
1919 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, | |
1920 | iterator.level - 1, | |
1921 | 1, ACC_ALL, iterator.sptep); | |
1922 | if (!sp) { | |
1923 | pgprintk("nonpaging_map: ENOMEM\n"); | |
1924 | kvm_release_pfn_clean(pfn); | |
1925 | return -ENOMEM; | |
1926 | } | |
140754bc | 1927 | |
d555c333 AK |
1928 | __set_spte(iterator.sptep, |
1929 | __pa(sp->spt) | |
1930 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
1931 | | shadow_user_mask | shadow_x_mask); | |
9f652d21 AK |
1932 | } |
1933 | } | |
1934 | return pt_write; | |
6aa8b732 AK |
1935 | } |
1936 | ||
10589a46 MT |
1937 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
1938 | { | |
1939 | int r; | |
852e3c19 | 1940 | int level; |
35149e21 | 1941 | pfn_t pfn; |
e930bffe | 1942 | unsigned long mmu_seq; |
aaee2c94 | 1943 | |
852e3c19 JR |
1944 | level = mapping_level(vcpu, gfn); |
1945 | ||
1946 | /* | |
1947 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
1948 | * maximum. Therefore check if the level is larger than that. | |
1949 | */ | |
1950 | if (level > PT_DIRECTORY_LEVEL) | |
1951 | level = PT_DIRECTORY_LEVEL; | |
1952 | ||
1953 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 1954 | |
e930bffe | 1955 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 1956 | smp_rmb(); |
35149e21 | 1957 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
aaee2c94 | 1958 | |
d196e343 | 1959 | /* mmio */ |
35149e21 AL |
1960 | if (is_error_pfn(pfn)) { |
1961 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
1962 | return 1; |
1963 | } | |
1964 | ||
aaee2c94 | 1965 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
1966 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
1967 | goto out_unlock; | |
eb787d10 | 1968 | kvm_mmu_free_some_pages(vcpu); |
852e3c19 | 1969 | r = __direct_map(vcpu, v, write, level, gfn, pfn); |
aaee2c94 MT |
1970 | spin_unlock(&vcpu->kvm->mmu_lock); |
1971 | ||
aaee2c94 | 1972 | |
10589a46 | 1973 | return r; |
e930bffe AA |
1974 | |
1975 | out_unlock: | |
1976 | spin_unlock(&vcpu->kvm->mmu_lock); | |
1977 | kvm_release_pfn_clean(pfn); | |
1978 | return 0; | |
10589a46 MT |
1979 | } |
1980 | ||
1981 | ||
17ac10ad AK |
1982 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
1983 | { | |
1984 | int i; | |
4db35314 | 1985 | struct kvm_mmu_page *sp; |
17ac10ad | 1986 | |
ad312c7c | 1987 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 1988 | return; |
aaee2c94 | 1989 | spin_lock(&vcpu->kvm->mmu_lock); |
ad312c7c ZX |
1990 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
1991 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad | 1992 | |
4db35314 AK |
1993 | sp = page_header(root); |
1994 | --sp->root_count; | |
2e53d63a MT |
1995 | if (!sp->root_count && sp->role.invalid) |
1996 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
ad312c7c | 1997 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 1998 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
1999 | return; |
2000 | } | |
17ac10ad | 2001 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2002 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2003 | |
417726a3 | 2004 | if (root) { |
417726a3 | 2005 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2006 | sp = page_header(root); |
2007 | --sp->root_count; | |
2e53d63a MT |
2008 | if (!sp->root_count && sp->role.invalid) |
2009 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
417726a3 | 2010 | } |
ad312c7c | 2011 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2012 | } |
aaee2c94 | 2013 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2014 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2015 | } |
2016 | ||
8986ecc0 MT |
2017 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2018 | { | |
2019 | int ret = 0; | |
2020 | ||
2021 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
2022 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
2023 | ret = 1; | |
2024 | } | |
2025 | ||
2026 | return ret; | |
2027 | } | |
2028 | ||
2029 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) | |
17ac10ad AK |
2030 | { |
2031 | int i; | |
cea0f0e7 | 2032 | gfn_t root_gfn; |
4db35314 | 2033 | struct kvm_mmu_page *sp; |
f6e2c02b | 2034 | int direct = 0; |
6de4f3ad | 2035 | u64 pdptr; |
3bb65a22 | 2036 | |
ad312c7c | 2037 | root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT; |
17ac10ad | 2038 | |
ad312c7c ZX |
2039 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2040 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad AK |
2041 | |
2042 | ASSERT(!VALID_PAGE(root)); | |
fb72d167 | 2043 | if (tdp_enabled) |
f6e2c02b | 2044 | direct = 1; |
8986ecc0 MT |
2045 | if (mmu_check_root(vcpu, root_gfn)) |
2046 | return 1; | |
4db35314 | 2047 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
f6e2c02b | 2048 | PT64_ROOT_LEVEL, direct, |
fb72d167 | 2049 | ACC_ALL, NULL); |
4db35314 AK |
2050 | root = __pa(sp->spt); |
2051 | ++sp->root_count; | |
ad312c7c | 2052 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2053 | return 0; |
17ac10ad | 2054 | } |
f6e2c02b | 2055 | direct = !is_paging(vcpu); |
fb72d167 | 2056 | if (tdp_enabled) |
f6e2c02b | 2057 | direct = 1; |
17ac10ad | 2058 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2059 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2060 | |
2061 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2062 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
6de4f3ad | 2063 | pdptr = kvm_pdptr_read(vcpu, i); |
43a3795a | 2064 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2065 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2066 | continue; |
2067 | } | |
6de4f3ad | 2068 | root_gfn = pdptr >> PAGE_SHIFT; |
ad312c7c | 2069 | } else if (vcpu->arch.mmu.root_level == 0) |
cea0f0e7 | 2070 | root_gfn = 0; |
8986ecc0 MT |
2071 | if (mmu_check_root(vcpu, root_gfn)) |
2072 | return 1; | |
4db35314 | 2073 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
f6e2c02b | 2074 | PT32_ROOT_LEVEL, direct, |
f7d9c7b7 | 2075 | ACC_ALL, NULL); |
4db35314 AK |
2076 | root = __pa(sp->spt); |
2077 | ++sp->root_count; | |
ad312c7c | 2078 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; |
17ac10ad | 2079 | } |
ad312c7c | 2080 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
8986ecc0 | 2081 | return 0; |
17ac10ad AK |
2082 | } |
2083 | ||
0ba73cda MT |
2084 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2085 | { | |
2086 | int i; | |
2087 | struct kvm_mmu_page *sp; | |
2088 | ||
2089 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2090 | return; | |
2091 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2092 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
2093 | sp = page_header(root); | |
2094 | mmu_sync_children(vcpu, sp); | |
2095 | return; | |
2096 | } | |
2097 | for (i = 0; i < 4; ++i) { | |
2098 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2099 | ||
8986ecc0 | 2100 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2101 | root &= PT64_BASE_ADDR_MASK; |
2102 | sp = page_header(root); | |
2103 | mmu_sync_children(vcpu, sp); | |
2104 | } | |
2105 | } | |
2106 | } | |
2107 | ||
2108 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2109 | { | |
2110 | spin_lock(&vcpu->kvm->mmu_lock); | |
2111 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2112 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2113 | } |
2114 | ||
6aa8b732 AK |
2115 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr) |
2116 | { | |
2117 | return vaddr; | |
2118 | } | |
2119 | ||
2120 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, | |
3f3e7124 | 2121 | u32 error_code) |
6aa8b732 | 2122 | { |
e833240f | 2123 | gfn_t gfn; |
e2dec939 | 2124 | int r; |
6aa8b732 | 2125 | |
b8688d51 | 2126 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2127 | r = mmu_topup_memory_caches(vcpu); |
2128 | if (r) | |
2129 | return r; | |
714b93da | 2130 | |
6aa8b732 | 2131 | ASSERT(vcpu); |
ad312c7c | 2132 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2133 | |
e833240f | 2134 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2135 | |
e833240f AK |
2136 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
2137 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
2138 | } |
2139 | ||
fb72d167 JR |
2140 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, |
2141 | u32 error_code) | |
2142 | { | |
35149e21 | 2143 | pfn_t pfn; |
fb72d167 | 2144 | int r; |
852e3c19 | 2145 | int level; |
05da4558 | 2146 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2147 | unsigned long mmu_seq; |
fb72d167 JR |
2148 | |
2149 | ASSERT(vcpu); | |
2150 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2151 | ||
2152 | r = mmu_topup_memory_caches(vcpu); | |
2153 | if (r) | |
2154 | return r; | |
2155 | ||
852e3c19 JR |
2156 | level = mapping_level(vcpu, gfn); |
2157 | ||
2158 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2159 | ||
e930bffe | 2160 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2161 | smp_rmb(); |
35149e21 | 2162 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
35149e21 AL |
2163 | if (is_error_pfn(pfn)) { |
2164 | kvm_release_pfn_clean(pfn); | |
fb72d167 JR |
2165 | return 1; |
2166 | } | |
2167 | spin_lock(&vcpu->kvm->mmu_lock); | |
e930bffe AA |
2168 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2169 | goto out_unlock; | |
fb72d167 JR |
2170 | kvm_mmu_free_some_pages(vcpu); |
2171 | r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK, | |
852e3c19 | 2172 | level, gfn, pfn); |
fb72d167 | 2173 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2174 | |
2175 | return r; | |
e930bffe AA |
2176 | |
2177 | out_unlock: | |
2178 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2179 | kvm_release_pfn_clean(pfn); | |
2180 | return 0; | |
fb72d167 JR |
2181 | } |
2182 | ||
6aa8b732 AK |
2183 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2184 | { | |
17ac10ad | 2185 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2186 | } |
2187 | ||
2188 | static int nonpaging_init_context(struct kvm_vcpu *vcpu) | |
2189 | { | |
ad312c7c | 2190 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2191 | |
2192 | context->new_cr3 = nonpaging_new_cr3; | |
2193 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2194 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2195 | context->free = nonpaging_free; | |
c7addb90 | 2196 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2197 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2198 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2199 | context->root_level = 0; |
6aa8b732 | 2200 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2201 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2202 | return 0; |
2203 | } | |
2204 | ||
d835dfec | 2205 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2206 | { |
1165f5fe | 2207 | ++vcpu->stat.tlb_flush; |
cbdd1bea | 2208 | kvm_x86_ops->tlb_flush(vcpu); |
6aa8b732 AK |
2209 | } |
2210 | ||
2211 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2212 | { | |
b8688d51 | 2213 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2214 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2215 | } |
2216 | ||
6aa8b732 AK |
2217 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2218 | u64 addr, | |
2219 | u32 err_code) | |
2220 | { | |
c3c91fee | 2221 | kvm_inject_page_fault(vcpu, addr, err_code); |
6aa8b732 AK |
2222 | } |
2223 | ||
6aa8b732 AK |
2224 | static void paging_free(struct kvm_vcpu *vcpu) |
2225 | { | |
2226 | nonpaging_free(vcpu); | |
2227 | } | |
2228 | ||
82725b20 DE |
2229 | static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) |
2230 | { | |
2231 | int bit7; | |
2232 | ||
2233 | bit7 = (gpte >> 7) & 1; | |
2234 | return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; | |
2235 | } | |
2236 | ||
6aa8b732 AK |
2237 | #define PTTYPE 64 |
2238 | #include "paging_tmpl.h" | |
2239 | #undef PTTYPE | |
2240 | ||
2241 | #define PTTYPE 32 | |
2242 | #include "paging_tmpl.h" | |
2243 | #undef PTTYPE | |
2244 | ||
82725b20 DE |
2245 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) |
2246 | { | |
2247 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2248 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
2249 | u64 exb_bit_rsvd = 0; | |
2250 | ||
2251 | if (!is_nx(vcpu)) | |
2252 | exb_bit_rsvd = rsvd_bits(63, 63); | |
2253 | switch (level) { | |
2254 | case PT32_ROOT_LEVEL: | |
2255 | /* no rsvd bits for 2 level 4K page table entries */ | |
2256 | context->rsvd_bits_mask[0][1] = 0; | |
2257 | context->rsvd_bits_mask[0][0] = 0; | |
2258 | if (is_cpuid_PSE36()) | |
2259 | /* 36bits PSE 4MB page */ | |
2260 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2261 | else | |
2262 | /* 32 bits PSE 4MB page */ | |
2263 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
29a4b933 | 2264 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; |
82725b20 DE |
2265 | break; |
2266 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2267 | context->rsvd_bits_mask[0][2] = |
2268 | rsvd_bits(maxphyaddr, 63) | | |
2269 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2270 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2271 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2272 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2273 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2274 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2275 | rsvd_bits(maxphyaddr, 62) | | |
2276 | rsvd_bits(13, 20); /* large page */ | |
29a4b933 | 2277 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; |
82725b20 DE |
2278 | break; |
2279 | case PT64_ROOT_LEVEL: | |
2280 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2281 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2282 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2283 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2284 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2285 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2286 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2287 | rsvd_bits(maxphyaddr, 51); | |
2288 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2289 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2290 | rsvd_bits(maxphyaddr, 51) | | |
2291 | rsvd_bits(13, 29); | |
82725b20 | 2292 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2293 | rsvd_bits(maxphyaddr, 51) | |
2294 | rsvd_bits(13, 20); /* large page */ | |
29a4b933 | 2295 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; |
82725b20 DE |
2296 | break; |
2297 | } | |
2298 | } | |
2299 | ||
17ac10ad | 2300 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level) |
6aa8b732 | 2301 | { |
ad312c7c | 2302 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2303 | |
2304 | ASSERT(is_pae(vcpu)); | |
2305 | context->new_cr3 = paging_new_cr3; | |
2306 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2307 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2308 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2309 | context->sync_page = paging64_sync_page; |
a7052897 | 2310 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2311 | context->free = paging_free; |
17ac10ad AK |
2312 | context->root_level = level; |
2313 | context->shadow_root_level = level; | |
17c3ba9d | 2314 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2315 | return 0; |
2316 | } | |
2317 | ||
17ac10ad AK |
2318 | static int paging64_init_context(struct kvm_vcpu *vcpu) |
2319 | { | |
82725b20 | 2320 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
17ac10ad AK |
2321 | return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL); |
2322 | } | |
2323 | ||
6aa8b732 AK |
2324 | static int paging32_init_context(struct kvm_vcpu *vcpu) |
2325 | { | |
ad312c7c | 2326 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 | 2327 | |
82725b20 | 2328 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2329 | context->new_cr3 = paging_new_cr3; |
2330 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2331 | context->gva_to_gpa = paging32_gva_to_gpa; |
2332 | context->free = paging_free; | |
c7addb90 | 2333 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2334 | context->sync_page = paging32_sync_page; |
a7052897 | 2335 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2336 | context->root_level = PT32_ROOT_LEVEL; |
2337 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2338 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2339 | return 0; |
2340 | } | |
2341 | ||
2342 | static int paging32E_init_context(struct kvm_vcpu *vcpu) | |
2343 | { | |
82725b20 | 2344 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
17ac10ad | 2345 | return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2346 | } |
2347 | ||
fb72d167 JR |
2348 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2349 | { | |
2350 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2351 | ||
2352 | context->new_cr3 = nonpaging_new_cr3; | |
2353 | context->page_fault = tdp_page_fault; | |
2354 | context->free = nonpaging_free; | |
2355 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2356 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2357 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2358 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 JR |
2359 | context->root_hpa = INVALID_PAGE; |
2360 | ||
2361 | if (!is_paging(vcpu)) { | |
2362 | context->gva_to_gpa = nonpaging_gva_to_gpa; | |
2363 | context->root_level = 0; | |
2364 | } else if (is_long_mode(vcpu)) { | |
82725b20 | 2365 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
fb72d167 JR |
2366 | context->gva_to_gpa = paging64_gva_to_gpa; |
2367 | context->root_level = PT64_ROOT_LEVEL; | |
2368 | } else if (is_pae(vcpu)) { | |
82725b20 | 2369 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2370 | context->gva_to_gpa = paging64_gva_to_gpa; |
2371 | context->root_level = PT32E_ROOT_LEVEL; | |
2372 | } else { | |
82725b20 | 2373 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
fb72d167 JR |
2374 | context->gva_to_gpa = paging32_gva_to_gpa; |
2375 | context->root_level = PT32_ROOT_LEVEL; | |
2376 | } | |
2377 | ||
2378 | return 0; | |
2379 | } | |
2380 | ||
2381 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2382 | { |
a770f6f2 AK |
2383 | int r; |
2384 | ||
6aa8b732 | 2385 | ASSERT(vcpu); |
ad312c7c | 2386 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2387 | |
2388 | if (!is_paging(vcpu)) | |
a770f6f2 | 2389 | r = nonpaging_init_context(vcpu); |
a9058ecd | 2390 | else if (is_long_mode(vcpu)) |
a770f6f2 | 2391 | r = paging64_init_context(vcpu); |
6aa8b732 | 2392 | else if (is_pae(vcpu)) |
a770f6f2 | 2393 | r = paging32E_init_context(vcpu); |
6aa8b732 | 2394 | else |
a770f6f2 AK |
2395 | r = paging32_init_context(vcpu); |
2396 | ||
2397 | vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level; | |
2398 | ||
2399 | return r; | |
6aa8b732 AK |
2400 | } |
2401 | ||
fb72d167 JR |
2402 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
2403 | { | |
35149e21 AL |
2404 | vcpu->arch.update_pte.pfn = bad_pfn; |
2405 | ||
fb72d167 JR |
2406 | if (tdp_enabled) |
2407 | return init_kvm_tdp_mmu(vcpu); | |
2408 | else | |
2409 | return init_kvm_softmmu(vcpu); | |
2410 | } | |
2411 | ||
6aa8b732 AK |
2412 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
2413 | { | |
2414 | ASSERT(vcpu); | |
ad312c7c ZX |
2415 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) { |
2416 | vcpu->arch.mmu.free(vcpu); | |
2417 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
6aa8b732 AK |
2418 | } |
2419 | } | |
2420 | ||
2421 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
2422 | { |
2423 | destroy_kvm_mmu(vcpu); | |
2424 | return init_kvm_mmu(vcpu); | |
2425 | } | |
8668a3c4 | 2426 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
2427 | |
2428 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2429 | { |
714b93da AK |
2430 | int r; |
2431 | ||
e2dec939 | 2432 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
2433 | if (r) |
2434 | goto out; | |
aaee2c94 | 2435 | spin_lock(&vcpu->kvm->mmu_lock); |
eb787d10 | 2436 | kvm_mmu_free_some_pages(vcpu); |
8986ecc0 | 2437 | r = mmu_alloc_roots(vcpu); |
0ba73cda | 2438 | mmu_sync_roots(vcpu); |
aaee2c94 | 2439 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
2440 | if (r) |
2441 | goto out; | |
3662cb1c | 2442 | /* set_cr3() should ensure TLB has been flushed */ |
ad312c7c | 2443 | kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
2444 | out: |
2445 | return r; | |
6aa8b732 | 2446 | } |
17c3ba9d AK |
2447 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
2448 | ||
2449 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
2450 | { | |
2451 | mmu_free_roots(vcpu); | |
2452 | } | |
6aa8b732 | 2453 | |
09072daf | 2454 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2455 | struct kvm_mmu_page *sp, |
ac1b714e AK |
2456 | u64 *spte) |
2457 | { | |
2458 | u64 pte; | |
2459 | struct kvm_mmu_page *child; | |
2460 | ||
2461 | pte = *spte; | |
c7addb90 | 2462 | if (is_shadow_present_pte(pte)) { |
776e6633 | 2463 | if (is_last_spte(pte, sp->role.level)) |
290fc38d | 2464 | rmap_remove(vcpu->kvm, spte); |
ac1b714e AK |
2465 | else { |
2466 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 2467 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
2468 | } |
2469 | } | |
d555c333 | 2470 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
2471 | if (is_large_pte(pte)) |
2472 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
2473 | } |
2474 | ||
0028425f | 2475 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2476 | struct kvm_mmu_page *sp, |
0028425f | 2477 | u64 *spte, |
489f1d65 | 2478 | const void *new) |
0028425f | 2479 | { |
30945387 | 2480 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
852e3c19 | 2481 | if (vcpu->arch.update_pte.level == PT_PAGE_TABLE_LEVEL || |
30945387 MT |
2482 | sp->role.glevels == PT32_ROOT_LEVEL) { |
2483 | ++vcpu->kvm->stat.mmu_pde_zapped; | |
2484 | return; | |
2485 | } | |
2486 | } | |
0028425f | 2487 | |
4cee5764 | 2488 | ++vcpu->kvm->stat.mmu_pte_updated; |
4db35314 | 2489 | if (sp->role.glevels == PT32_ROOT_LEVEL) |
489f1d65 | 2490 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 2491 | else |
489f1d65 | 2492 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
2493 | } |
2494 | ||
79539cec AK |
2495 | static bool need_remote_flush(u64 old, u64 new) |
2496 | { | |
2497 | if (!is_shadow_present_pte(old)) | |
2498 | return false; | |
2499 | if (!is_shadow_present_pte(new)) | |
2500 | return true; | |
2501 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
2502 | return true; | |
2503 | old ^= PT64_NX_MASK; | |
2504 | new ^= PT64_NX_MASK; | |
2505 | return (old & ~new & PT64_PERM_MASK) != 0; | |
2506 | } | |
2507 | ||
2508 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new) | |
2509 | { | |
2510 | if (need_remote_flush(old, new)) | |
2511 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2512 | else | |
2513 | kvm_mmu_flush_tlb(vcpu); | |
2514 | } | |
2515 | ||
12b7d28f AK |
2516 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
2517 | { | |
ad312c7c | 2518 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 2519 | |
7b52345e | 2520 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
2521 | } |
2522 | ||
d7824fff AK |
2523 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
2524 | const u8 *new, int bytes) | |
2525 | { | |
2526 | gfn_t gfn; | |
2527 | int r; | |
2528 | u64 gpte = 0; | |
35149e21 | 2529 | pfn_t pfn; |
d7824fff | 2530 | |
852e3c19 | 2531 | vcpu->arch.update_pte.level = PT_PAGE_TABLE_LEVEL; |
05da4558 | 2532 | |
d7824fff AK |
2533 | if (bytes != 4 && bytes != 8) |
2534 | return; | |
2535 | ||
2536 | /* | |
2537 | * Assume that the pte write on a page table of the same type | |
2538 | * as the current vcpu paging mode. This is nearly always true | |
2539 | * (might be false while changing modes). Note it is verified later | |
2540 | * by update_pte(). | |
2541 | */ | |
2542 | if (is_pae(vcpu)) { | |
2543 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ | |
2544 | if ((bytes == 4) && (gpa % 4 == 0)) { | |
2545 | r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8); | |
2546 | if (r) | |
2547 | return; | |
2548 | memcpy((void *)&gpte + (gpa % 8), new, 4); | |
2549 | } else if ((bytes == 8) && (gpa % 8 == 0)) { | |
2550 | memcpy((void *)&gpte, new, 8); | |
2551 | } | |
2552 | } else { | |
2553 | if ((bytes == 4) && (gpa % 4 == 0)) | |
2554 | memcpy((void *)&gpte, new, 4); | |
2555 | } | |
43a3795a | 2556 | if (!is_present_gpte(gpte)) |
d7824fff AK |
2557 | return; |
2558 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 2559 | |
d25797b2 JR |
2560 | if (is_large_pte(gpte) && |
2561 | (mapping_level(vcpu, gfn) == PT_DIRECTORY_LEVEL)) { | |
ec04b260 | 2562 | gfn &= ~(KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL) - 1); |
852e3c19 | 2563 | vcpu->arch.update_pte.level = PT_DIRECTORY_LEVEL; |
05da4558 | 2564 | } |
e930bffe | 2565 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2566 | smp_rmb(); |
35149e21 | 2567 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 2568 | |
35149e21 AL |
2569 | if (is_error_pfn(pfn)) { |
2570 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
2571 | return; |
2572 | } | |
d7824fff | 2573 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 2574 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
2575 | } |
2576 | ||
1b7fcd32 AK |
2577 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
2578 | { | |
2579 | u64 *spte = vcpu->arch.last_pte_updated; | |
2580 | ||
2581 | if (spte | |
2582 | && vcpu->arch.last_pte_gfn == gfn | |
2583 | && shadow_accessed_mask | |
2584 | && !(*spte & shadow_accessed_mask) | |
2585 | && is_shadow_present_pte(*spte)) | |
2586 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
2587 | } | |
2588 | ||
09072daf | 2589 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
2590 | const u8 *new, int bytes, |
2591 | bool guest_initiated) | |
da4a00f0 | 2592 | { |
9b7a0325 | 2593 | gfn_t gfn = gpa >> PAGE_SHIFT; |
4db35314 | 2594 | struct kvm_mmu_page *sp; |
0e7bc4b9 | 2595 | struct hlist_node *node, *n; |
9b7a0325 AK |
2596 | struct hlist_head *bucket; |
2597 | unsigned index; | |
489f1d65 | 2598 | u64 entry, gentry; |
9b7a0325 | 2599 | u64 *spte; |
9b7a0325 | 2600 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 2601 | unsigned pte_size; |
9b7a0325 | 2602 | unsigned page_offset; |
0e7bc4b9 | 2603 | unsigned misaligned; |
fce0657f | 2604 | unsigned quadrant; |
9b7a0325 | 2605 | int level; |
86a5ba02 | 2606 | int flooded = 0; |
ac1b714e | 2607 | int npte; |
489f1d65 | 2608 | int r; |
9b7a0325 | 2609 | |
b8688d51 | 2610 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
d7824fff | 2611 | mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes); |
aaee2c94 | 2612 | spin_lock(&vcpu->kvm->mmu_lock); |
1b7fcd32 | 2613 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 2614 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 2615 | ++vcpu->kvm->stat.mmu_pte_write; |
c7addb90 | 2616 | kvm_mmu_audit(vcpu, "pre pte write"); |
ad218f85 MT |
2617 | if (guest_initiated) { |
2618 | if (gfn == vcpu->arch.last_pt_write_gfn | |
2619 | && !last_updated_pte_accessed(vcpu)) { | |
2620 | ++vcpu->arch.last_pt_write_count; | |
2621 | if (vcpu->arch.last_pt_write_count >= 3) | |
2622 | flooded = 1; | |
2623 | } else { | |
2624 | vcpu->arch.last_pt_write_gfn = gfn; | |
2625 | vcpu->arch.last_pt_write_count = 1; | |
2626 | vcpu->arch.last_pte_updated = NULL; | |
2627 | } | |
86a5ba02 | 2628 | } |
1ae0a13d | 2629 | index = kvm_page_table_hashfn(gfn); |
f05e70ac | 2630 | bucket = &vcpu->kvm->arch.mmu_page_hash[index]; |
4db35314 | 2631 | hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) { |
f6e2c02b | 2632 | if (sp->gfn != gfn || sp->role.direct || sp->role.invalid) |
9b7a0325 | 2633 | continue; |
4db35314 | 2634 | pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8; |
0e7bc4b9 | 2635 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 2636 | misaligned |= bytes < 4; |
86a5ba02 | 2637 | if (misaligned || flooded) { |
0e7bc4b9 AK |
2638 | /* |
2639 | * Misaligned accesses are too much trouble to fix | |
2640 | * up; also, they usually indicate a page is not used | |
2641 | * as a page table. | |
86a5ba02 AK |
2642 | * |
2643 | * If we're seeing too many writes to a page, | |
2644 | * it may no longer be a page table, or we may be | |
2645 | * forking, in which case it is better to unmap the | |
2646 | * page. | |
0e7bc4b9 AK |
2647 | */ |
2648 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 2649 | gpa, bytes, sp->role.word); |
07385413 MT |
2650 | if (kvm_mmu_zap_page(vcpu->kvm, sp)) |
2651 | n = bucket->first; | |
4cee5764 | 2652 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
2653 | continue; |
2654 | } | |
9b7a0325 | 2655 | page_offset = offset; |
4db35314 | 2656 | level = sp->role.level; |
ac1b714e | 2657 | npte = 1; |
4db35314 | 2658 | if (sp->role.glevels == PT32_ROOT_LEVEL) { |
ac1b714e AK |
2659 | page_offset <<= 1; /* 32->64 */ |
2660 | /* | |
2661 | * A 32-bit pde maps 4MB while the shadow pdes map | |
2662 | * only 2MB. So we need to double the offset again | |
2663 | * and zap two pdes instead of one. | |
2664 | */ | |
2665 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 2666 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
2667 | page_offset <<= 1; |
2668 | npte = 2; | |
2669 | } | |
fce0657f | 2670 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 2671 | page_offset &= ~PAGE_MASK; |
4db35314 | 2672 | if (quadrant != sp->role.quadrant) |
fce0657f | 2673 | continue; |
9b7a0325 | 2674 | } |
4db35314 | 2675 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
489f1d65 DE |
2676 | if ((gpa & (pte_size - 1)) || (bytes < pte_size)) { |
2677 | gentry = 0; | |
2678 | r = kvm_read_guest_atomic(vcpu->kvm, | |
2679 | gpa & ~(u64)(pte_size - 1), | |
2680 | &gentry, pte_size); | |
2681 | new = (const void *)&gentry; | |
2682 | if (r < 0) | |
2683 | new = NULL; | |
2684 | } | |
ac1b714e | 2685 | while (npte--) { |
79539cec | 2686 | entry = *spte; |
4db35314 | 2687 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
489f1d65 DE |
2688 | if (new) |
2689 | mmu_pte_write_new_pte(vcpu, sp, spte, new); | |
79539cec | 2690 | mmu_pte_write_flush_tlb(vcpu, entry, *spte); |
ac1b714e | 2691 | ++spte; |
9b7a0325 | 2692 | } |
9b7a0325 | 2693 | } |
c7addb90 | 2694 | kvm_mmu_audit(vcpu, "post pte write"); |
aaee2c94 | 2695 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
2696 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
2697 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
2698 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 2699 | } |
da4a00f0 AK |
2700 | } |
2701 | ||
a436036b AK |
2702 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
2703 | { | |
10589a46 MT |
2704 | gpa_t gpa; |
2705 | int r; | |
a436036b | 2706 | |
10589a46 | 2707 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva); |
10589a46 | 2708 | |
aaee2c94 | 2709 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 2710 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 2711 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 2712 | return r; |
a436036b | 2713 | } |
577bdc49 | 2714 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 2715 | |
22d95b12 | 2716 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 2717 | { |
f05e70ac | 2718 | while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES) { |
4db35314 | 2719 | struct kvm_mmu_page *sp; |
ebeace86 | 2720 | |
f05e70ac | 2721 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 AK |
2722 | struct kvm_mmu_page, link); |
2723 | kvm_mmu_zap_page(vcpu->kvm, sp); | |
4cee5764 | 2724 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
2725 | } |
2726 | } | |
ebeace86 | 2727 | |
3067714c AK |
2728 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
2729 | { | |
2730 | int r; | |
2731 | enum emulation_result er; | |
2732 | ||
ad312c7c | 2733 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
2734 | if (r < 0) |
2735 | goto out; | |
2736 | ||
2737 | if (!r) { | |
2738 | r = 1; | |
2739 | goto out; | |
2740 | } | |
2741 | ||
b733bfb5 AK |
2742 | r = mmu_topup_memory_caches(vcpu); |
2743 | if (r) | |
2744 | goto out; | |
2745 | ||
3067714c | 2746 | er = emulate_instruction(vcpu, vcpu->run, cr2, error_code, 0); |
3067714c AK |
2747 | |
2748 | switch (er) { | |
2749 | case EMULATE_DONE: | |
2750 | return 1; | |
2751 | case EMULATE_DO_MMIO: | |
2752 | ++vcpu->stat.mmio_exits; | |
2753 | return 0; | |
2754 | case EMULATE_FAIL: | |
3f5d18a9 AK |
2755 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
2756 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2757 | return 0; | |
3067714c AK |
2758 | default: |
2759 | BUG(); | |
2760 | } | |
2761 | out: | |
3067714c AK |
2762 | return r; |
2763 | } | |
2764 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
2765 | ||
a7052897 MT |
2766 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
2767 | { | |
a7052897 | 2768 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
2769 | kvm_mmu_flush_tlb(vcpu); |
2770 | ++vcpu->stat.invlpg; | |
2771 | } | |
2772 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
2773 | ||
18552672 JR |
2774 | void kvm_enable_tdp(void) |
2775 | { | |
2776 | tdp_enabled = true; | |
2777 | } | |
2778 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
2779 | ||
5f4cb662 JR |
2780 | void kvm_disable_tdp(void) |
2781 | { | |
2782 | tdp_enabled = false; | |
2783 | } | |
2784 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
2785 | ||
6aa8b732 AK |
2786 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
2787 | { | |
ad312c7c | 2788 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
6aa8b732 AK |
2789 | } |
2790 | ||
2791 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
2792 | { | |
17ac10ad | 2793 | struct page *page; |
6aa8b732 AK |
2794 | int i; |
2795 | ||
2796 | ASSERT(vcpu); | |
2797 | ||
6a1ac771 | 2798 | spin_lock(&vcpu->kvm->mmu_lock); |
f05e70ac ZX |
2799 | if (vcpu->kvm->arch.n_requested_mmu_pages) |
2800 | vcpu->kvm->arch.n_free_mmu_pages = | |
2801 | vcpu->kvm->arch.n_requested_mmu_pages; | |
82ce2c96 | 2802 | else |
f05e70ac ZX |
2803 | vcpu->kvm->arch.n_free_mmu_pages = |
2804 | vcpu->kvm->arch.n_alloc_mmu_pages; | |
6a1ac771 | 2805 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2806 | /* |
2807 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
2808 | * Therefore we need to allocate shadow page tables in the first | |
2809 | * 4GB of memory, which happens to fit the DMA32 zone. | |
2810 | */ | |
2811 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
2812 | if (!page) | |
2813 | goto error_1; | |
ad312c7c | 2814 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 2815 | for (i = 0; i < 4; ++i) |
ad312c7c | 2816 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2817 | |
6aa8b732 AK |
2818 | return 0; |
2819 | ||
2820 | error_1: | |
2821 | free_mmu_pages(vcpu); | |
2822 | return -ENOMEM; | |
2823 | } | |
2824 | ||
8018c27b | 2825 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 2826 | { |
6aa8b732 | 2827 | ASSERT(vcpu); |
ad312c7c | 2828 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2829 | |
8018c27b IM |
2830 | return alloc_mmu_pages(vcpu); |
2831 | } | |
6aa8b732 | 2832 | |
8018c27b IM |
2833 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
2834 | { | |
2835 | ASSERT(vcpu); | |
ad312c7c | 2836 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 2837 | |
8018c27b | 2838 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
2839 | } |
2840 | ||
2841 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
2842 | { | |
2843 | ASSERT(vcpu); | |
2844 | ||
2845 | destroy_kvm_mmu(vcpu); | |
2846 | free_mmu_pages(vcpu); | |
714b93da | 2847 | mmu_free_memory_caches(vcpu); |
6aa8b732 AK |
2848 | } |
2849 | ||
90cb0529 | 2850 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 2851 | { |
4db35314 | 2852 | struct kvm_mmu_page *sp; |
6aa8b732 | 2853 | |
f05e70ac | 2854 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
2855 | int i; |
2856 | u64 *pt; | |
2857 | ||
291f26bc | 2858 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
2859 | continue; |
2860 | ||
4db35314 | 2861 | pt = sp->spt; |
6aa8b732 AK |
2862 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2863 | /* avoid RMW */ | |
9647c14c | 2864 | if (pt[i] & PT_WRITABLE_MASK) |
6aa8b732 | 2865 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 | 2866 | } |
171d595d | 2867 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 2868 | } |
37a7d8b0 | 2869 | |
90cb0529 | 2870 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 2871 | { |
4db35314 | 2872 | struct kvm_mmu_page *sp, *node; |
e0fa826f | 2873 | |
aaee2c94 | 2874 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 2875 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
07385413 MT |
2876 | if (kvm_mmu_zap_page(kvm, sp)) |
2877 | node = container_of(kvm->arch.active_mmu_pages.next, | |
2878 | struct kvm_mmu_page, link); | |
aaee2c94 | 2879 | spin_unlock(&kvm->mmu_lock); |
e0fa826f | 2880 | |
90cb0529 | 2881 | kvm_flush_remote_tlbs(kvm); |
e0fa826f DL |
2882 | } |
2883 | ||
8b2cf73c | 2884 | static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm) |
3ee16c81 IE |
2885 | { |
2886 | struct kvm_mmu_page *page; | |
2887 | ||
2888 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
2889 | struct kvm_mmu_page, link); | |
2890 | kvm_mmu_zap_page(kvm, page); | |
2891 | } | |
2892 | ||
2893 | static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask) | |
2894 | { | |
2895 | struct kvm *kvm; | |
2896 | struct kvm *kvm_freed = NULL; | |
2897 | int cache_count = 0; | |
2898 | ||
2899 | spin_lock(&kvm_lock); | |
2900 | ||
2901 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
2902 | int npages; | |
2903 | ||
5a4c9288 MT |
2904 | if (!down_read_trylock(&kvm->slots_lock)) |
2905 | continue; | |
3ee16c81 IE |
2906 | spin_lock(&kvm->mmu_lock); |
2907 | npages = kvm->arch.n_alloc_mmu_pages - | |
2908 | kvm->arch.n_free_mmu_pages; | |
2909 | cache_count += npages; | |
2910 | if (!kvm_freed && nr_to_scan > 0 && npages > 0) { | |
2911 | kvm_mmu_remove_one_alloc_mmu_page(kvm); | |
2912 | cache_count--; | |
2913 | kvm_freed = kvm; | |
2914 | } | |
2915 | nr_to_scan--; | |
2916 | ||
2917 | spin_unlock(&kvm->mmu_lock); | |
5a4c9288 | 2918 | up_read(&kvm->slots_lock); |
3ee16c81 IE |
2919 | } |
2920 | if (kvm_freed) | |
2921 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
2922 | ||
2923 | spin_unlock(&kvm_lock); | |
2924 | ||
2925 | return cache_count; | |
2926 | } | |
2927 | ||
2928 | static struct shrinker mmu_shrinker = { | |
2929 | .shrink = mmu_shrink, | |
2930 | .seeks = DEFAULT_SEEKS * 10, | |
2931 | }; | |
2932 | ||
2ddfd20e | 2933 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
2934 | { |
2935 | if (pte_chain_cache) | |
2936 | kmem_cache_destroy(pte_chain_cache); | |
2937 | if (rmap_desc_cache) | |
2938 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
2939 | if (mmu_page_header_cache) |
2940 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
2941 | } |
2942 | ||
3ee16c81 IE |
2943 | void kvm_mmu_module_exit(void) |
2944 | { | |
2945 | mmu_destroy_caches(); | |
2946 | unregister_shrinker(&mmu_shrinker); | |
2947 | } | |
2948 | ||
b5a33a75 AK |
2949 | int kvm_mmu_module_init(void) |
2950 | { | |
2951 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
2952 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 2953 | 0, 0, NULL); |
b5a33a75 AK |
2954 | if (!pte_chain_cache) |
2955 | goto nomem; | |
2956 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
2957 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 2958 | 0, 0, NULL); |
b5a33a75 AK |
2959 | if (!rmap_desc_cache) |
2960 | goto nomem; | |
2961 | ||
d3d25b04 AK |
2962 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
2963 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 2964 | 0, 0, NULL); |
d3d25b04 AK |
2965 | if (!mmu_page_header_cache) |
2966 | goto nomem; | |
2967 | ||
3ee16c81 IE |
2968 | register_shrinker(&mmu_shrinker); |
2969 | ||
b5a33a75 AK |
2970 | return 0; |
2971 | ||
2972 | nomem: | |
3ee16c81 | 2973 | mmu_destroy_caches(); |
b5a33a75 AK |
2974 | return -ENOMEM; |
2975 | } | |
2976 | ||
3ad82a7e ZX |
2977 | /* |
2978 | * Caculate mmu pages needed for kvm. | |
2979 | */ | |
2980 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
2981 | { | |
2982 | int i; | |
2983 | unsigned int nr_mmu_pages; | |
2984 | unsigned int nr_pages = 0; | |
2985 | ||
2986 | for (i = 0; i < kvm->nmemslots; i++) | |
2987 | nr_pages += kvm->memslots[i].npages; | |
2988 | ||
2989 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
2990 | nr_mmu_pages = max(nr_mmu_pages, | |
2991 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
2992 | ||
2993 | return nr_mmu_pages; | |
2994 | } | |
2995 | ||
2f333bcb MT |
2996 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
2997 | unsigned len) | |
2998 | { | |
2999 | if (len > buffer->len) | |
3000 | return NULL; | |
3001 | return buffer->ptr; | |
3002 | } | |
3003 | ||
3004 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3005 | unsigned len) | |
3006 | { | |
3007 | void *ret; | |
3008 | ||
3009 | ret = pv_mmu_peek_buffer(buffer, len); | |
3010 | if (!ret) | |
3011 | return ret; | |
3012 | buffer->ptr += len; | |
3013 | buffer->len -= len; | |
3014 | buffer->processed += len; | |
3015 | return ret; | |
3016 | } | |
3017 | ||
3018 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3019 | gpa_t addr, gpa_t value) | |
3020 | { | |
3021 | int bytes = 8; | |
3022 | int r; | |
3023 | ||
3024 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3025 | bytes = 4; | |
3026 | ||
3027 | r = mmu_topup_memory_caches(vcpu); | |
3028 | if (r) | |
3029 | return r; | |
3030 | ||
3200f405 | 3031 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3032 | return -EFAULT; |
3033 | ||
3034 | return 1; | |
3035 | } | |
3036 | ||
3037 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3038 | { | |
a8cd0244 | 3039 | kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3040 | return 1; |
3041 | } | |
3042 | ||
3043 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3044 | { | |
3045 | spin_lock(&vcpu->kvm->mmu_lock); | |
3046 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3047 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3048 | return 1; | |
3049 | } | |
3050 | ||
3051 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3052 | struct kvm_pv_mmu_op_buffer *buffer) | |
3053 | { | |
3054 | struct kvm_mmu_op_header *header; | |
3055 | ||
3056 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3057 | if (!header) | |
3058 | return 0; | |
3059 | switch (header->op) { | |
3060 | case KVM_MMU_OP_WRITE_PTE: { | |
3061 | struct kvm_mmu_op_write_pte *wpte; | |
3062 | ||
3063 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3064 | if (!wpte) | |
3065 | return 0; | |
3066 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3067 | wpte->pte_val); | |
3068 | } | |
3069 | case KVM_MMU_OP_FLUSH_TLB: { | |
3070 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3071 | ||
3072 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3073 | if (!ftlb) | |
3074 | return 0; | |
3075 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3076 | } | |
3077 | case KVM_MMU_OP_RELEASE_PT: { | |
3078 | struct kvm_mmu_op_release_pt *rpt; | |
3079 | ||
3080 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3081 | if (!rpt) | |
3082 | return 0; | |
3083 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3084 | } | |
3085 | default: return 0; | |
3086 | } | |
3087 | } | |
3088 | ||
3089 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3090 | gpa_t addr, unsigned long *ret) | |
3091 | { | |
3092 | int r; | |
6ad18fba | 3093 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3094 | |
6ad18fba DH |
3095 | buffer->ptr = buffer->buf; |
3096 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3097 | buffer->processed = 0; | |
2f333bcb | 3098 | |
6ad18fba | 3099 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3100 | if (r) |
3101 | goto out; | |
3102 | ||
6ad18fba DH |
3103 | while (buffer->len) { |
3104 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3105 | if (r < 0) |
3106 | goto out; | |
3107 | if (r == 0) | |
3108 | break; | |
3109 | } | |
3110 | ||
3111 | r = 1; | |
3112 | out: | |
6ad18fba | 3113 | *ret = buffer->processed; |
2f333bcb MT |
3114 | return r; |
3115 | } | |
3116 | ||
94d8b056 MT |
3117 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3118 | { | |
3119 | struct kvm_shadow_walk_iterator iterator; | |
3120 | int nr_sptes = 0; | |
3121 | ||
3122 | spin_lock(&vcpu->kvm->mmu_lock); | |
3123 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3124 | sptes[iterator.level-1] = *iterator.sptep; | |
3125 | nr_sptes++; | |
3126 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3127 | break; | |
3128 | } | |
3129 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3130 | ||
3131 | return nr_sptes; | |
3132 | } | |
3133 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3134 | ||
37a7d8b0 AK |
3135 | #ifdef AUDIT |
3136 | ||
3137 | static const char *audit_msg; | |
3138 | ||
3139 | static gva_t canonicalize(gva_t gva) | |
3140 | { | |
3141 | #ifdef CONFIG_X86_64 | |
3142 | gva = (long long)(gva << 16) >> 16; | |
3143 | #endif | |
3144 | return gva; | |
3145 | } | |
3146 | ||
08a3732b MT |
3147 | |
3148 | typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp, | |
3149 | u64 *sptep); | |
3150 | ||
3151 | static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp, | |
3152 | inspect_spte_fn fn) | |
3153 | { | |
3154 | int i; | |
3155 | ||
3156 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3157 | u64 ent = sp->spt[i]; | |
3158 | ||
3159 | if (is_shadow_present_pte(ent)) { | |
2920d728 | 3160 | if (!is_last_spte(ent, sp->role.level)) { |
08a3732b MT |
3161 | struct kvm_mmu_page *child; |
3162 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
3163 | __mmu_spte_walk(kvm, child, fn); | |
2920d728 | 3164 | } else |
08a3732b MT |
3165 | fn(kvm, sp, &sp->spt[i]); |
3166 | } | |
3167 | } | |
3168 | } | |
3169 | ||
3170 | static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn) | |
3171 | { | |
3172 | int i; | |
3173 | struct kvm_mmu_page *sp; | |
3174 | ||
3175 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3176 | return; | |
3177 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3178 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
3179 | sp = page_header(root); | |
3180 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3181 | return; | |
3182 | } | |
3183 | for (i = 0; i < 4; ++i) { | |
3184 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3185 | ||
3186 | if (root && VALID_PAGE(root)) { | |
3187 | root &= PT64_BASE_ADDR_MASK; | |
3188 | sp = page_header(root); | |
3189 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3190 | } | |
3191 | } | |
3192 | return; | |
3193 | } | |
3194 | ||
37a7d8b0 AK |
3195 | static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte, |
3196 | gva_t va, int level) | |
3197 | { | |
3198 | u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK); | |
3199 | int i; | |
3200 | gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1)); | |
3201 | ||
3202 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) { | |
3203 | u64 ent = pt[i]; | |
3204 | ||
c7addb90 | 3205 | if (ent == shadow_trap_nonpresent_pte) |
37a7d8b0 AK |
3206 | continue; |
3207 | ||
3208 | va = canonicalize(va); | |
2920d728 MT |
3209 | if (is_shadow_present_pte(ent) && !is_last_spte(ent, level)) |
3210 | audit_mappings_page(vcpu, ent, va, level - 1); | |
3211 | else { | |
ad312c7c | 3212 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va); |
34382539 JK |
3213 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3214 | pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn); | |
3215 | hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT; | |
37a7d8b0 | 3216 | |
2aaf65e8 MT |
3217 | if (is_error_pfn(pfn)) { |
3218 | kvm_release_pfn_clean(pfn); | |
3219 | continue; | |
3220 | } | |
3221 | ||
c7addb90 | 3222 | if (is_shadow_present_pte(ent) |
37a7d8b0 | 3223 | && (ent & PT64_BASE_ADDR_MASK) != hpa) |
c7addb90 AK |
3224 | printk(KERN_ERR "xx audit error: (%s) levels %d" |
3225 | " gva %lx gpa %llx hpa %llx ent %llx %d\n", | |
ad312c7c | 3226 | audit_msg, vcpu->arch.mmu.root_level, |
d77c26fc MD |
3227 | va, gpa, hpa, ent, |
3228 | is_shadow_present_pte(ent)); | |
c7addb90 AK |
3229 | else if (ent == shadow_notrap_nonpresent_pte |
3230 | && !is_error_hpa(hpa)) | |
3231 | printk(KERN_ERR "audit: (%s) notrap shadow," | |
3232 | " valid guest gva %lx\n", audit_msg, va); | |
35149e21 | 3233 | kvm_release_pfn_clean(pfn); |
c7addb90 | 3234 | |
37a7d8b0 AK |
3235 | } |
3236 | } | |
3237 | } | |
3238 | ||
3239 | static void audit_mappings(struct kvm_vcpu *vcpu) | |
3240 | { | |
1ea252af | 3241 | unsigned i; |
37a7d8b0 | 3242 | |
ad312c7c ZX |
3243 | if (vcpu->arch.mmu.root_level == 4) |
3244 | audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4); | |
37a7d8b0 AK |
3245 | else |
3246 | for (i = 0; i < 4; ++i) | |
ad312c7c | 3247 | if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK) |
37a7d8b0 | 3248 | audit_mappings_page(vcpu, |
ad312c7c | 3249 | vcpu->arch.mmu.pae_root[i], |
37a7d8b0 AK |
3250 | i << 30, |
3251 | 2); | |
3252 | } | |
3253 | ||
3254 | static int count_rmaps(struct kvm_vcpu *vcpu) | |
3255 | { | |
3256 | int nmaps = 0; | |
3257 | int i, j, k; | |
3258 | ||
3259 | for (i = 0; i < KVM_MEMORY_SLOTS; ++i) { | |
3260 | struct kvm_memory_slot *m = &vcpu->kvm->memslots[i]; | |
3261 | struct kvm_rmap_desc *d; | |
3262 | ||
3263 | for (j = 0; j < m->npages; ++j) { | |
290fc38d | 3264 | unsigned long *rmapp = &m->rmap[j]; |
37a7d8b0 | 3265 | |
290fc38d | 3266 | if (!*rmapp) |
37a7d8b0 | 3267 | continue; |
290fc38d | 3268 | if (!(*rmapp & 1)) { |
37a7d8b0 AK |
3269 | ++nmaps; |
3270 | continue; | |
3271 | } | |
290fc38d | 3272 | d = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
37a7d8b0 AK |
3273 | while (d) { |
3274 | for (k = 0; k < RMAP_EXT; ++k) | |
d555c333 | 3275 | if (d->sptes[k]) |
37a7d8b0 AK |
3276 | ++nmaps; |
3277 | else | |
3278 | break; | |
3279 | d = d->more; | |
3280 | } | |
3281 | } | |
3282 | } | |
3283 | return nmaps; | |
3284 | } | |
3285 | ||
08a3732b MT |
3286 | void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep) |
3287 | { | |
3288 | unsigned long *rmapp; | |
3289 | struct kvm_mmu_page *rev_sp; | |
3290 | gfn_t gfn; | |
3291 | ||
3292 | if (*sptep & PT_WRITABLE_MASK) { | |
3293 | rev_sp = page_header(__pa(sptep)); | |
3294 | gfn = rev_sp->gfns[sptep - rev_sp->spt]; | |
3295 | ||
3296 | if (!gfn_to_memslot(kvm, gfn)) { | |
3297 | if (!printk_ratelimit()) | |
3298 | return; | |
3299 | printk(KERN_ERR "%s: no memslot for gfn %ld\n", | |
3300 | audit_msg, gfn); | |
3301 | printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n", | |
3302 | audit_msg, sptep - rev_sp->spt, | |
3303 | rev_sp->gfn); | |
3304 | dump_stack(); | |
3305 | return; | |
3306 | } | |
3307 | ||
2920d728 MT |
3308 | rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt], |
3309 | is_large_pte(*sptep)); | |
08a3732b MT |
3310 | if (!*rmapp) { |
3311 | if (!printk_ratelimit()) | |
3312 | return; | |
3313 | printk(KERN_ERR "%s: no rmap for writable spte %llx\n", | |
3314 | audit_msg, *sptep); | |
3315 | dump_stack(); | |
3316 | } | |
3317 | } | |
3318 | ||
3319 | } | |
3320 | ||
3321 | void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu) | |
3322 | { | |
3323 | mmu_spte_walk(vcpu, inspect_spte_has_rmap); | |
3324 | } | |
3325 | ||
3326 | static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu) | |
37a7d8b0 | 3327 | { |
4db35314 | 3328 | struct kvm_mmu_page *sp; |
37a7d8b0 AK |
3329 | int i; |
3330 | ||
f05e70ac | 3331 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
4db35314 | 3332 | u64 *pt = sp->spt; |
37a7d8b0 | 3333 | |
4db35314 | 3334 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) |
37a7d8b0 AK |
3335 | continue; |
3336 | ||
3337 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3338 | u64 ent = pt[i]; | |
3339 | ||
3340 | if (!(ent & PT_PRESENT_MASK)) | |
3341 | continue; | |
3342 | if (!(ent & PT_WRITABLE_MASK)) | |
3343 | continue; | |
08a3732b | 3344 | inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]); |
37a7d8b0 AK |
3345 | } |
3346 | } | |
08a3732b | 3347 | return; |
37a7d8b0 AK |
3348 | } |
3349 | ||
3350 | static void audit_rmap(struct kvm_vcpu *vcpu) | |
3351 | { | |
08a3732b MT |
3352 | check_writable_mappings_rmap(vcpu); |
3353 | count_rmaps(vcpu); | |
37a7d8b0 AK |
3354 | } |
3355 | ||
3356 | static void audit_write_protection(struct kvm_vcpu *vcpu) | |
3357 | { | |
4db35314 | 3358 | struct kvm_mmu_page *sp; |
290fc38d IE |
3359 | struct kvm_memory_slot *slot; |
3360 | unsigned long *rmapp; | |
e58b0f9e | 3361 | u64 *spte; |
290fc38d | 3362 | gfn_t gfn; |
37a7d8b0 | 3363 | |
f05e70ac | 3364 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
f6e2c02b | 3365 | if (sp->role.direct) |
37a7d8b0 | 3366 | continue; |
e58b0f9e MT |
3367 | if (sp->unsync) |
3368 | continue; | |
37a7d8b0 | 3369 | |
4db35314 | 3370 | gfn = unalias_gfn(vcpu->kvm, sp->gfn); |
2843099f | 3371 | slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn); |
290fc38d | 3372 | rmapp = &slot->rmap[gfn - slot->base_gfn]; |
e58b0f9e MT |
3373 | |
3374 | spte = rmap_next(vcpu->kvm, rmapp, NULL); | |
3375 | while (spte) { | |
3376 | if (*spte & PT_WRITABLE_MASK) | |
3377 | printk(KERN_ERR "%s: (%s) shadow page has " | |
3378 | "writable mappings: gfn %lx role %x\n", | |
b8688d51 | 3379 | __func__, audit_msg, sp->gfn, |
4db35314 | 3380 | sp->role.word); |
e58b0f9e MT |
3381 | spte = rmap_next(vcpu->kvm, rmapp, spte); |
3382 | } | |
37a7d8b0 AK |
3383 | } |
3384 | } | |
3385 | ||
3386 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) | |
3387 | { | |
3388 | int olddbg = dbg; | |
3389 | ||
3390 | dbg = 0; | |
3391 | audit_msg = msg; | |
3392 | audit_rmap(vcpu); | |
3393 | audit_write_protection(vcpu); | |
2aaf65e8 MT |
3394 | if (strcmp("pre pte write", audit_msg) != 0) |
3395 | audit_mappings(vcpu); | |
08a3732b | 3396 | audit_writable_sptes_have_rmaps(vcpu); |
37a7d8b0 AK |
3397 | dbg = olddbg; |
3398 | } | |
3399 | ||
3400 | #endif |