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CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
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23#include <linux/types.h>
24#include <linux/string.h>
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25#include <linux/mm.h>
26#include <linux/highmem.h>
27#include <linux/module.h>
448353ca 28#include <linux/swap.h>
05da4558 29#include <linux/hugetlb.h>
2f333bcb 30#include <linux/compiler.h>
6aa8b732 31
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32#include <asm/page.h>
33#include <asm/cmpxchg.h>
4e542370 34#include <asm/io.h>
13673a90 35#include <asm/vmx.h>
6aa8b732 36
18552672
JR
37/*
38 * When setting this variable to true it enables Two-Dimensional-Paging
39 * where the hardware walks 2 page tables:
40 * 1. the guest-virtual to guest-physical
41 * 2. while doing 1. it walks guest-physical to host-physical
42 * If the hardware supports that we don't need to do shadow paging.
43 */
2f333bcb 44bool tdp_enabled = false;
18552672 45
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46#undef MMU_DEBUG
47
48#undef AUDIT
49
50#ifdef AUDIT
51static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
52#else
53static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
54#endif
55
56#ifdef MMU_DEBUG
57
58#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
59#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
60
61#else
62
63#define pgprintk(x...) do { } while (0)
64#define rmap_printk(x...) do { } while (0)
65
66#endif
67
68#if defined(MMU_DEBUG) || defined(AUDIT)
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69static int dbg = 0;
70module_param(dbg, bool, 0644);
37a7d8b0 71#endif
6aa8b732 72
582801a9
MT
73static int oos_shadow = 1;
74module_param(oos_shadow, bool, 0644);
75
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76#ifndef MMU_DEBUG
77#define ASSERT(x) do { } while (0)
78#else
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79#define ASSERT(x) \
80 if (!(x)) { \
81 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
82 __FILE__, __LINE__, #x); \
83 }
d6c69ee9 84#endif
6aa8b732 85
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86#define PT_FIRST_AVAIL_BITS_SHIFT 9
87#define PT64_SECOND_AVAIL_BITS_SHIFT 52
88
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89#define VALID_PAGE(x) ((x) != INVALID_PAGE)
90
91#define PT64_LEVEL_BITS 9
92
93#define PT64_LEVEL_SHIFT(level) \
d77c26fc 94 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
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95
96#define PT64_LEVEL_MASK(level) \
97 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
98
99#define PT64_INDEX(address, level)\
100 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
101
102
103#define PT32_LEVEL_BITS 10
104
105#define PT32_LEVEL_SHIFT(level) \
d77c26fc 106 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
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107
108#define PT32_LEVEL_MASK(level) \
109 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
110
111#define PT32_INDEX(address, level)\
112 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
113
114
27aba766 115#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
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116#define PT64_DIR_BASE_ADDR_MASK \
117 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
118
119#define PT32_BASE_ADDR_MASK PAGE_MASK
120#define PT32_DIR_BASE_ADDR_MASK \
121 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
122
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123#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
124 | PT64_NX_MASK)
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125
126#define PFERR_PRESENT_MASK (1U << 0)
127#define PFERR_WRITE_MASK (1U << 1)
128#define PFERR_USER_MASK (1U << 2)
82725b20 129#define PFERR_RSVD_MASK (1U << 3)
73b1087e 130#define PFERR_FETCH_MASK (1U << 4)
6aa8b732 131
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132#define PT_DIRECTORY_LEVEL 2
133#define PT_PAGE_TABLE_LEVEL 1
134
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135#define RMAP_EXT 4
136
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137#define ACC_EXEC_MASK 1
138#define ACC_WRITE_MASK PT_WRITABLE_MASK
139#define ACC_USER_MASK PT_USER_MASK
140#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
141
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142#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
143
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144struct kvm_rmap_desc {
145 u64 *shadow_ptes[RMAP_EXT];
146 struct kvm_rmap_desc *more;
147};
148
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149struct kvm_shadow_walk_iterator {
150 u64 addr;
151 hpa_t shadow_addr;
152 int level;
153 u64 *sptep;
154 unsigned index;
155};
156
157#define for_each_shadow_entry(_vcpu, _addr, _walker) \
158 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
159 shadow_walk_okay(&(_walker)); \
160 shadow_walk_next(&(_walker)))
161
162
4731d4c7
MT
163struct kvm_unsync_walk {
164 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
165};
166
ad8cfbe3
MT
167typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
168
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169static struct kmem_cache *pte_chain_cache;
170static struct kmem_cache *rmap_desc_cache;
d3d25b04 171static struct kmem_cache *mmu_page_header_cache;
b5a33a75 172
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173static u64 __read_mostly shadow_trap_nonpresent_pte;
174static u64 __read_mostly shadow_notrap_nonpresent_pte;
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SY
175static u64 __read_mostly shadow_base_present_pte;
176static u64 __read_mostly shadow_nx_mask;
177static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
178static u64 __read_mostly shadow_user_mask;
179static u64 __read_mostly shadow_accessed_mask;
180static u64 __read_mostly shadow_dirty_mask;
c7addb90 181
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182static inline u64 rsvd_bits(int s, int e)
183{
184 return ((1ULL << (e - s + 1)) - 1) << s;
185}
186
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187void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
188{
189 shadow_trap_nonpresent_pte = trap_pte;
190 shadow_notrap_nonpresent_pte = notrap_pte;
191}
192EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
193
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SY
194void kvm_mmu_set_base_ptes(u64 base_pte)
195{
196 shadow_base_present_pte = base_pte;
197}
198EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
199
200void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 201 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY
202{
203 shadow_user_mask = user_mask;
204 shadow_accessed_mask = accessed_mask;
205 shadow_dirty_mask = dirty_mask;
206 shadow_nx_mask = nx_mask;
207 shadow_x_mask = x_mask;
208}
209EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
210
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211static int is_write_protection(struct kvm_vcpu *vcpu)
212{
ad312c7c 213 return vcpu->arch.cr0 & X86_CR0_WP;
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214}
215
216static int is_cpuid_PSE36(void)
217{
218 return 1;
219}
220
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221static int is_nx(struct kvm_vcpu *vcpu)
222{
ad312c7c 223 return vcpu->arch.shadow_efer & EFER_NX;
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224}
225
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226static int is_shadow_present_pte(u64 pte)
227{
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228 return pte != shadow_trap_nonpresent_pte
229 && pte != shadow_notrap_nonpresent_pte;
230}
231
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232static int is_large_pte(u64 pte)
233{
234 return pte & PT_PAGE_SIZE_MASK;
235}
236
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237static int is_writeble_pte(unsigned long pte)
238{
239 return pte & PT_WRITABLE_MASK;
240}
241
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242static int is_dirty_pte(unsigned long pte)
243{
7b52345e 244 return pte & shadow_dirty_mask;
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245}
246
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247static int is_rmap_pte(u64 pte)
248{
4b1a80fa 249 return is_shadow_present_pte(pte);
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250}
251
35149e21 252static pfn_t spte_to_pfn(u64 pte)
0b49ea86 253{
35149e21 254 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
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255}
256
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257static gfn_t pse36_gfn_delta(u32 gpte)
258{
259 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
260
261 return (gpte & PT32_DIR_PSE36_MASK) << shift;
262}
263
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264static void set_shadow_pte(u64 *sptep, u64 spte)
265{
266#ifdef CONFIG_X86_64
267 set_64bit((unsigned long *)sptep, spte);
268#else
269 set_64bit((unsigned long long *)sptep, spte);
270#endif
271}
272
e2dec939 273static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 274 struct kmem_cache *base_cache, int min)
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275{
276 void *obj;
277
278 if (cache->nobjs >= min)
e2dec939 279 return 0;
714b93da 280 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 281 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 282 if (!obj)
e2dec939 283 return -ENOMEM;
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284 cache->objects[cache->nobjs++] = obj;
285 }
e2dec939 286 return 0;
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287}
288
289static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
290{
291 while (mc->nobjs)
292 kfree(mc->objects[--mc->nobjs]);
293}
294
c1158e63 295static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 296 int min)
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297{
298 struct page *page;
299
300 if (cache->nobjs >= min)
301 return 0;
302 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 303 page = alloc_page(GFP_KERNEL);
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304 if (!page)
305 return -ENOMEM;
306 set_page_private(page, 0);
307 cache->objects[cache->nobjs++] = page_address(page);
308 }
309 return 0;
310}
311
312static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
313{
314 while (mc->nobjs)
c4d198d5 315 free_page((unsigned long)mc->objects[--mc->nobjs]);
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316}
317
2e3e5882 318static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 319{
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320 int r;
321
ad312c7c 322 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 323 pte_chain_cache, 4);
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324 if (r)
325 goto out;
ad312c7c 326 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 327 rmap_desc_cache, 4);
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328 if (r)
329 goto out;
ad312c7c 330 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
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331 if (r)
332 goto out;
ad312c7c 333 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 334 mmu_page_header_cache, 4);
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335out:
336 return r;
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337}
338
339static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
340{
ad312c7c
ZX
341 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
342 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
343 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
344 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
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345}
346
347static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
348 size_t size)
349{
350 void *p;
351
352 BUG_ON(!mc->nobjs);
353 p = mc->objects[--mc->nobjs];
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354 return p;
355}
356
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357static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
358{
ad312c7c 359 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
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360 sizeof(struct kvm_pte_chain));
361}
362
90cb0529 363static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 364{
90cb0529 365 kfree(pc);
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366}
367
368static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
369{
ad312c7c 370 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
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371 sizeof(struct kvm_rmap_desc));
372}
373
90cb0529 374static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 375{
90cb0529 376 kfree(rd);
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377}
378
05da4558
MT
379/*
380 * Return the pointer to the largepage write count for a given
381 * gfn, handling slots that are not large page aligned.
382 */
383static int *slot_largepage_idx(gfn_t gfn, struct kvm_memory_slot *slot)
384{
385 unsigned long idx;
386
387 idx = (gfn / KVM_PAGES_PER_HPAGE) -
388 (slot->base_gfn / KVM_PAGES_PER_HPAGE);
389 return &slot->lpage_info[idx].write_count;
390}
391
392static void account_shadowed(struct kvm *kvm, gfn_t gfn)
393{
394 int *write_count;
395
2843099f
IE
396 gfn = unalias_gfn(kvm, gfn);
397 write_count = slot_largepage_idx(gfn,
398 gfn_to_memslot_unaliased(kvm, gfn));
05da4558 399 *write_count += 1;
05da4558
MT
400}
401
402static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
403{
404 int *write_count;
405
2843099f
IE
406 gfn = unalias_gfn(kvm, gfn);
407 write_count = slot_largepage_idx(gfn,
408 gfn_to_memslot_unaliased(kvm, gfn));
05da4558
MT
409 *write_count -= 1;
410 WARN_ON(*write_count < 0);
411}
412
413static int has_wrprotected_page(struct kvm *kvm, gfn_t gfn)
414{
2843099f 415 struct kvm_memory_slot *slot;
05da4558
MT
416 int *largepage_idx;
417
2843099f
IE
418 gfn = unalias_gfn(kvm, gfn);
419 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558
MT
420 if (slot) {
421 largepage_idx = slot_largepage_idx(gfn, slot);
422 return *largepage_idx;
423 }
424
425 return 1;
426}
427
428static int host_largepage_backed(struct kvm *kvm, gfn_t gfn)
429{
430 struct vm_area_struct *vma;
431 unsigned long addr;
4c2155ce 432 int ret = 0;
05da4558
MT
433
434 addr = gfn_to_hva(kvm, gfn);
435 if (kvm_is_error_hva(addr))
4c2155ce 436 return ret;
05da4558 437
4c2155ce 438 down_read(&current->mm->mmap_sem);
05da4558
MT
439 vma = find_vma(current->mm, addr);
440 if (vma && is_vm_hugetlb_page(vma))
4c2155ce
MT
441 ret = 1;
442 up_read(&current->mm->mmap_sem);
05da4558 443
4c2155ce 444 return ret;
05da4558
MT
445}
446
447static int is_largepage_backed(struct kvm_vcpu *vcpu, gfn_t large_gfn)
448{
449 struct kvm_memory_slot *slot;
450
451 if (has_wrprotected_page(vcpu->kvm, large_gfn))
452 return 0;
453
454 if (!host_largepage_backed(vcpu->kvm, large_gfn))
455 return 0;
456
457 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
458 if (slot && slot->dirty_bitmap)
459 return 0;
460
461 return 1;
462}
463
290fc38d
IE
464/*
465 * Take gfn and return the reverse mapping to it.
466 * Note: gfn must be unaliased before this function get called
467 */
468
05da4558 469static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int lpage)
290fc38d
IE
470{
471 struct kvm_memory_slot *slot;
05da4558 472 unsigned long idx;
290fc38d
IE
473
474 slot = gfn_to_memslot(kvm, gfn);
05da4558
MT
475 if (!lpage)
476 return &slot->rmap[gfn - slot->base_gfn];
477
478 idx = (gfn / KVM_PAGES_PER_HPAGE) -
479 (slot->base_gfn / KVM_PAGES_PER_HPAGE);
480
481 return &slot->lpage_info[idx].rmap_pde;
290fc38d
IE
482}
483
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484/*
485 * Reverse mapping data structures:
486 *
290fc38d
IE
487 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
488 * that points to page_address(page).
cd4a4e53 489 *
290fc38d
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490 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
491 * containing more mappings.
cd4a4e53 492 */
05da4558 493static void rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn, int lpage)
cd4a4e53 494{
4db35314 495 struct kvm_mmu_page *sp;
cd4a4e53 496 struct kvm_rmap_desc *desc;
290fc38d 497 unsigned long *rmapp;
cd4a4e53
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498 int i;
499
500 if (!is_rmap_pte(*spte))
501 return;
290fc38d 502 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK
503 sp = page_header(__pa(spte));
504 sp->gfns[spte - sp->spt] = gfn;
05da4558 505 rmapp = gfn_to_rmap(vcpu->kvm, gfn, lpage);
290fc38d 506 if (!*rmapp) {
cd4a4e53 507 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE
508 *rmapp = (unsigned long)spte;
509 } else if (!(*rmapp & 1)) {
cd4a4e53 510 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 511 desc = mmu_alloc_rmap_desc(vcpu);
290fc38d 512 desc->shadow_ptes[0] = (u64 *)*rmapp;
cd4a4e53 513 desc->shadow_ptes[1] = spte;
290fc38d 514 *rmapp = (unsigned long)desc | 1;
cd4a4e53
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515 } else {
516 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 517 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
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518 while (desc->shadow_ptes[RMAP_EXT-1] && desc->more)
519 desc = desc->more;
520 if (desc->shadow_ptes[RMAP_EXT-1]) {
714b93da 521 desc->more = mmu_alloc_rmap_desc(vcpu);
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522 desc = desc->more;
523 }
524 for (i = 0; desc->shadow_ptes[i]; ++i)
525 ;
526 desc->shadow_ptes[i] = spte;
527 }
528}
529
290fc38d 530static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
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531 struct kvm_rmap_desc *desc,
532 int i,
533 struct kvm_rmap_desc *prev_desc)
534{
535 int j;
536
537 for (j = RMAP_EXT - 1; !desc->shadow_ptes[j] && j > i; --j)
538 ;
539 desc->shadow_ptes[i] = desc->shadow_ptes[j];
11718b4d 540 desc->shadow_ptes[j] = NULL;
cd4a4e53
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541 if (j != 0)
542 return;
543 if (!prev_desc && !desc->more)
290fc38d 544 *rmapp = (unsigned long)desc->shadow_ptes[0];
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545 else
546 if (prev_desc)
547 prev_desc->more = desc->more;
548 else
290fc38d 549 *rmapp = (unsigned long)desc->more | 1;
90cb0529 550 mmu_free_rmap_desc(desc);
cd4a4e53
AK
551}
552
290fc38d 553static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 554{
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555 struct kvm_rmap_desc *desc;
556 struct kvm_rmap_desc *prev_desc;
4db35314 557 struct kvm_mmu_page *sp;
35149e21 558 pfn_t pfn;
290fc38d 559 unsigned long *rmapp;
cd4a4e53
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560 int i;
561
562 if (!is_rmap_pte(*spte))
563 return;
4db35314 564 sp = page_header(__pa(spte));
35149e21 565 pfn = spte_to_pfn(*spte);
7b52345e 566 if (*spte & shadow_accessed_mask)
35149e21 567 kvm_set_pfn_accessed(pfn);
b4231d61 568 if (is_writeble_pte(*spte))
35149e21 569 kvm_release_pfn_dirty(pfn);
b4231d61 570 else
35149e21 571 kvm_release_pfn_clean(pfn);
05da4558 572 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], is_large_pte(*spte));
290fc38d 573 if (!*rmapp) {
cd4a4e53
AK
574 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
575 BUG();
290fc38d 576 } else if (!(*rmapp & 1)) {
cd4a4e53 577 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 578 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK
579 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
580 spte, *spte);
581 BUG();
582 }
290fc38d 583 *rmapp = 0;
cd4a4e53
AK
584 } else {
585 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 586 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK
587 prev_desc = NULL;
588 while (desc) {
589 for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i)
590 if (desc->shadow_ptes[i] == spte) {
290fc38d 591 rmap_desc_remove_entry(rmapp,
714b93da 592 desc, i,
cd4a4e53
AK
593 prev_desc);
594 return;
595 }
596 prev_desc = desc;
597 desc = desc->more;
598 }
599 BUG();
600 }
601}
602
98348e95 603static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 604{
374cbac0 605 struct kvm_rmap_desc *desc;
98348e95
IE
606 struct kvm_rmap_desc *prev_desc;
607 u64 *prev_spte;
608 int i;
609
610 if (!*rmapp)
611 return NULL;
612 else if (!(*rmapp & 1)) {
613 if (!spte)
614 return (u64 *)*rmapp;
615 return NULL;
616 }
617 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
618 prev_desc = NULL;
619 prev_spte = NULL;
620 while (desc) {
621 for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i) {
622 if (prev_spte == spte)
623 return desc->shadow_ptes[i];
624 prev_spte = desc->shadow_ptes[i];
625 }
626 desc = desc->more;
627 }
628 return NULL;
629}
630
b1a36821 631static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 632{
290fc38d 633 unsigned long *rmapp;
374cbac0 634 u64 *spte;
caa5b8a5 635 int write_protected = 0;
374cbac0 636
4a4c9924 637 gfn = unalias_gfn(kvm, gfn);
05da4558 638 rmapp = gfn_to_rmap(kvm, gfn, 0);
374cbac0 639
98348e95
IE
640 spte = rmap_next(kvm, rmapp, NULL);
641 while (spte) {
374cbac0 642 BUG_ON(!spte);
374cbac0 643 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 644 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
caa5b8a5 645 if (is_writeble_pte(*spte)) {
9647c14c 646 set_shadow_pte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED
647 write_protected = 1;
648 }
9647c14c 649 spte = rmap_next(kvm, rmapp, spte);
374cbac0 650 }
855149aa 651 if (write_protected) {
35149e21 652 pfn_t pfn;
855149aa
IE
653
654 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL
655 pfn = spte_to_pfn(*spte);
656 kvm_set_pfn_dirty(pfn);
855149aa
IE
657 }
658
05da4558
MT
659 /* check for huge page mappings */
660 rmapp = gfn_to_rmap(kvm, gfn, 1);
661 spte = rmap_next(kvm, rmapp, NULL);
662 while (spte) {
663 BUG_ON(!spte);
664 BUG_ON(!(*spte & PT_PRESENT_MASK));
665 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
666 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
667 if (is_writeble_pte(*spte)) {
668 rmap_remove(kvm, spte);
669 --kvm->stat.lpages;
670 set_shadow_pte(spte, shadow_trap_nonpresent_pte);
6597ca09 671 spte = NULL;
05da4558
MT
672 write_protected = 1;
673 }
674 spte = rmap_next(kvm, rmapp, spte);
675 }
676
b1a36821 677 return write_protected;
374cbac0
AK
678}
679
e930bffe
AA
680static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp)
681{
682 u64 *spte;
683 int need_tlb_flush = 0;
684
685 while ((spte = rmap_next(kvm, rmapp, NULL))) {
686 BUG_ON(!(*spte & PT_PRESENT_MASK));
687 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
688 rmap_remove(kvm, spte);
689 set_shadow_pte(spte, shadow_trap_nonpresent_pte);
690 need_tlb_flush = 1;
691 }
692 return need_tlb_flush;
693}
694
695static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
696 int (*handler)(struct kvm *kvm, unsigned long *rmapp))
697{
698 int i;
699 int retval = 0;
700
701 /*
702 * If mmap_sem isn't taken, we can look the memslots with only
703 * the mmu_lock by skipping over the slots with userspace_addr == 0.
704 */
705 for (i = 0; i < kvm->nmemslots; i++) {
706 struct kvm_memory_slot *memslot = &kvm->memslots[i];
707 unsigned long start = memslot->userspace_addr;
708 unsigned long end;
709
710 /* mmu_lock protects userspace_addr */
711 if (!start)
712 continue;
713
714 end = start + (memslot->npages << PAGE_SHIFT);
715 if (hva >= start && hva < end) {
716 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
717 retval |= handler(kvm, &memslot->rmap[gfn_offset]);
718 retval |= handler(kvm,
719 &memslot->lpage_info[
720 gfn_offset /
721 KVM_PAGES_PER_HPAGE].rmap_pde);
722 }
723 }
724
725 return retval;
726}
727
728int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
729{
730 return kvm_handle_hva(kvm, hva, kvm_unmap_rmapp);
731}
732
733static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp)
734{
735 u64 *spte;
736 int young = 0;
737
534e38b4
SY
738 /* always return old for EPT */
739 if (!shadow_accessed_mask)
740 return 0;
741
e930bffe
AA
742 spte = rmap_next(kvm, rmapp, NULL);
743 while (spte) {
744 int _young;
745 u64 _spte = *spte;
746 BUG_ON(!(_spte & PT_PRESENT_MASK));
747 _young = _spte & PT_ACCESSED_MASK;
748 if (_young) {
749 young = 1;
750 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
751 }
752 spte = rmap_next(kvm, rmapp, spte);
753 }
754 return young;
755}
756
757int kvm_age_hva(struct kvm *kvm, unsigned long hva)
758{
759 return kvm_handle_hva(kvm, hva, kvm_age_rmapp);
760}
761
d6c69ee9 762#ifdef MMU_DEBUG
47ad8e68 763static int is_empty_shadow_page(u64 *spt)
6aa8b732 764{
139bdb2d
AK
765 u64 *pos;
766 u64 *end;
767
47ad8e68 768 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 769 if (is_shadow_present_pte(*pos)) {
b8688d51 770 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 771 pos, *pos);
6aa8b732 772 return 0;
139bdb2d 773 }
6aa8b732
AK
774 return 1;
775}
d6c69ee9 776#endif
6aa8b732 777
4db35314 778static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 779{
4db35314
AK
780 ASSERT(is_empty_shadow_page(sp->spt));
781 list_del(&sp->link);
782 __free_page(virt_to_page(sp->spt));
783 __free_page(virt_to_page(sp->gfns));
784 kfree(sp);
f05e70ac 785 ++kvm->arch.n_free_mmu_pages;
260746c0
AK
786}
787
cea0f0e7
AK
788static unsigned kvm_page_table_hashfn(gfn_t gfn)
789{
1ae0a13d 790 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK
791}
792
25c0de2c
AK
793static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
794 u64 *parent_pte)
6aa8b732 795{
4db35314 796 struct kvm_mmu_page *sp;
6aa8b732 797
ad312c7c
ZX
798 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
799 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
800 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 801 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 802 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 803 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 804 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK
805 sp->multimapped = 0;
806 sp->parent_pte = parent_pte;
f05e70ac 807 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 808 return sp;
6aa8b732
AK
809}
810
714b93da 811static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 812 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK
813{
814 struct kvm_pte_chain *pte_chain;
815 struct hlist_node *node;
816 int i;
817
818 if (!parent_pte)
819 return;
4db35314
AK
820 if (!sp->multimapped) {
821 u64 *old = sp->parent_pte;
cea0f0e7
AK
822
823 if (!old) {
4db35314 824 sp->parent_pte = parent_pte;
cea0f0e7
AK
825 return;
826 }
4db35314 827 sp->multimapped = 1;
714b93da 828 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK
829 INIT_HLIST_HEAD(&sp->parent_ptes);
830 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK
831 pte_chain->parent_ptes[0] = old;
832 }
4db35314 833 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK
834 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
835 continue;
836 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
837 if (!pte_chain->parent_ptes[i]) {
838 pte_chain->parent_ptes[i] = parent_pte;
839 return;
840 }
841 }
714b93da 842 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 843 BUG_ON(!pte_chain);
4db35314 844 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK
845 pte_chain->parent_ptes[0] = parent_pte;
846}
847
4db35314 848static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK
849 u64 *parent_pte)
850{
851 struct kvm_pte_chain *pte_chain;
852 struct hlist_node *node;
853 int i;
854
4db35314
AK
855 if (!sp->multimapped) {
856 BUG_ON(sp->parent_pte != parent_pte);
857 sp->parent_pte = NULL;
cea0f0e7
AK
858 return;
859 }
4db35314 860 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK
861 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
862 if (!pte_chain->parent_ptes[i])
863 break;
864 if (pte_chain->parent_ptes[i] != parent_pte)
865 continue;
697fe2e2
AK
866 while (i + 1 < NR_PTE_CHAIN_ENTRIES
867 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK
868 pte_chain->parent_ptes[i]
869 = pte_chain->parent_ptes[i + 1];
870 ++i;
871 }
872 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK
873 if (i == 0) {
874 hlist_del(&pte_chain->link);
90cb0529 875 mmu_free_pte_chain(pte_chain);
4db35314
AK
876 if (hlist_empty(&sp->parent_ptes)) {
877 sp->multimapped = 0;
878 sp->parent_pte = NULL;
697fe2e2
AK
879 }
880 }
cea0f0e7
AK
881 return;
882 }
883 BUG();
884}
885
ad8cfbe3
MT
886
887static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
888 mmu_parent_walk_fn fn)
889{
890 struct kvm_pte_chain *pte_chain;
891 struct hlist_node *node;
892 struct kvm_mmu_page *parent_sp;
893 int i;
894
895 if (!sp->multimapped && sp->parent_pte) {
896 parent_sp = page_header(__pa(sp->parent_pte));
897 fn(vcpu, parent_sp);
898 mmu_parent_walk(vcpu, parent_sp, fn);
899 return;
900 }
901 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
902 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
903 if (!pte_chain->parent_ptes[i])
904 break;
905 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
906 fn(vcpu, parent_sp);
907 mmu_parent_walk(vcpu, parent_sp, fn);
908 }
909}
910
0074ff63
MT
911static void kvm_mmu_update_unsync_bitmap(u64 *spte)
912{
913 unsigned int index;
914 struct kvm_mmu_page *sp = page_header(__pa(spte));
915
916 index = spte - sp->spt;
60c8aec6
MT
917 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
918 sp->unsync_children++;
919 WARN_ON(!sp->unsync_children);
0074ff63
MT
920}
921
922static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
923{
924 struct kvm_pte_chain *pte_chain;
925 struct hlist_node *node;
926 int i;
927
928 if (!sp->parent_pte)
929 return;
930
931 if (!sp->multimapped) {
932 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
933 return;
934 }
935
936 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
937 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
938 if (!pte_chain->parent_ptes[i])
939 break;
940 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
941 }
942}
943
944static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
945{
0074ff63
MT
946 kvm_mmu_update_parents_unsync(sp);
947 return 1;
948}
949
950static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
951 struct kvm_mmu_page *sp)
952{
953 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
954 kvm_mmu_update_parents_unsync(sp);
955}
956
d761a501
AK
957static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
958 struct kvm_mmu_page *sp)
959{
960 int i;
961
962 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
963 sp->spt[i] = shadow_trap_nonpresent_pte;
964}
965
e8bc217a
MT
966static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
967 struct kvm_mmu_page *sp)
968{
969 return 1;
970}
971
a7052897
MT
972static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
973{
974}
975
60c8aec6
MT
976#define KVM_PAGE_ARRAY_NR 16
977
978struct kvm_mmu_pages {
979 struct mmu_page_and_offset {
980 struct kvm_mmu_page *sp;
981 unsigned int idx;
982 } page[KVM_PAGE_ARRAY_NR];
983 unsigned int nr;
984};
985
0074ff63
MT
986#define for_each_unsync_children(bitmap, idx) \
987 for (idx = find_first_bit(bitmap, 512); \
988 idx < 512; \
989 idx = find_next_bit(bitmap, 512, idx+1))
990
cded19f3
HE
991static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
992 int idx)
4731d4c7 993{
60c8aec6 994 int i;
4731d4c7 995
60c8aec6
MT
996 if (sp->unsync)
997 for (i=0; i < pvec->nr; i++)
998 if (pvec->page[i].sp == sp)
999 return 0;
1000
1001 pvec->page[pvec->nr].sp = sp;
1002 pvec->page[pvec->nr].idx = idx;
1003 pvec->nr++;
1004 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1005}
1006
1007static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1008 struct kvm_mmu_pages *pvec)
1009{
1010 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1011
0074ff63 1012 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT
1013 u64 ent = sp->spt[i];
1014
87917239 1015 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT
1016 struct kvm_mmu_page *child;
1017 child = page_header(ent & PT64_BASE_ADDR_MASK);
1018
1019 if (child->unsync_children) {
60c8aec6
MT
1020 if (mmu_pages_add(pvec, child, i))
1021 return -ENOSPC;
1022
1023 ret = __mmu_unsync_walk(child, pvec);
1024 if (!ret)
1025 __clear_bit(i, sp->unsync_child_bitmap);
1026 else if (ret > 0)
1027 nr_unsync_leaf += ret;
1028 else
4731d4c7
MT
1029 return ret;
1030 }
1031
1032 if (child->unsync) {
60c8aec6
MT
1033 nr_unsync_leaf++;
1034 if (mmu_pages_add(pvec, child, i))
1035 return -ENOSPC;
4731d4c7
MT
1036 }
1037 }
1038 }
1039
0074ff63 1040 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT
1041 sp->unsync_children = 0;
1042
60c8aec6
MT
1043 return nr_unsync_leaf;
1044}
1045
1046static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1047 struct kvm_mmu_pages *pvec)
1048{
1049 if (!sp->unsync_children)
1050 return 0;
1051
1052 mmu_pages_add(pvec, sp, 0);
1053 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT
1054}
1055
4db35314 1056static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK
1057{
1058 unsigned index;
1059 struct hlist_head *bucket;
4db35314 1060 struct kvm_mmu_page *sp;
cea0f0e7
AK
1061 struct hlist_node *node;
1062
b8688d51 1063 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1064 index = kvm_page_table_hashfn(gfn);
f05e70ac 1065 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1066 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1067 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1068 && !sp->role.invalid) {
cea0f0e7 1069 pgprintk("%s: found role %x\n",
b8688d51 1070 __func__, sp->role.word);
4db35314 1071 return sp;
cea0f0e7
AK
1072 }
1073 return NULL;
1074}
1075
4731d4c7
MT
1076static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1077{
1078 WARN_ON(!sp->unsync);
1079 sp->unsync = 0;
1080 --kvm->stat.mmu_unsync;
1081}
1082
1083static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1084
1085static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1086{
1087 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1088 kvm_mmu_zap_page(vcpu->kvm, sp);
1089 return 1;
1090 }
1091
b1a36821
MT
1092 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1093 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1094 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT
1095 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1096 kvm_mmu_zap_page(vcpu->kvm, sp);
1097 return 1;
1098 }
1099
1100 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT
1101 return 0;
1102}
1103
60c8aec6
MT
1104struct mmu_page_path {
1105 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1106 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT
1107};
1108
60c8aec6
MT
1109#define for_each_sp(pvec, sp, parents, i) \
1110 for (i = mmu_pages_next(&pvec, &parents, -1), \
1111 sp = pvec.page[i].sp; \
1112 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1113 i = mmu_pages_next(&pvec, &parents, i))
1114
cded19f3
HE
1115static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1116 struct mmu_page_path *parents,
1117 int i)
60c8aec6
MT
1118{
1119 int n;
1120
1121 for (n = i+1; n < pvec->nr; n++) {
1122 struct kvm_mmu_page *sp = pvec->page[n].sp;
1123
1124 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1125 parents->idx[0] = pvec->page[n].idx;
1126 return n;
1127 }
1128
1129 parents->parent[sp->role.level-2] = sp;
1130 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1131 }
1132
1133 return n;
1134}
1135
cded19f3 1136static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1137{
60c8aec6
MT
1138 struct kvm_mmu_page *sp;
1139 unsigned int level = 0;
1140
1141 do {
1142 unsigned int idx = parents->idx[level];
4731d4c7 1143
60c8aec6
MT
1144 sp = parents->parent[level];
1145 if (!sp)
1146 return;
1147
1148 --sp->unsync_children;
1149 WARN_ON((int)sp->unsync_children < 0);
1150 __clear_bit(idx, sp->unsync_child_bitmap);
1151 level++;
1152 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT
1153}
1154
60c8aec6
MT
1155static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1156 struct mmu_page_path *parents,
1157 struct kvm_mmu_pages *pvec)
4731d4c7 1158{
60c8aec6
MT
1159 parents->parent[parent->role.level-1] = NULL;
1160 pvec->nr = 0;
1161}
4731d4c7 1162
60c8aec6
MT
1163static void mmu_sync_children(struct kvm_vcpu *vcpu,
1164 struct kvm_mmu_page *parent)
1165{
1166 int i;
1167 struct kvm_mmu_page *sp;
1168 struct mmu_page_path parents;
1169 struct kvm_mmu_pages pages;
1170
1171 kvm_mmu_pages_init(parent, &parents, &pages);
1172 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT
1173 int protected = 0;
1174
1175 for_each_sp(pages, sp, parents, i)
1176 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1177
1178 if (protected)
1179 kvm_flush_remote_tlbs(vcpu->kvm);
1180
60c8aec6
MT
1181 for_each_sp(pages, sp, parents, i) {
1182 kvm_sync_page(vcpu, sp);
1183 mmu_pages_clear_parents(&parents);
1184 }
4731d4c7 1185 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT
1186 kvm_mmu_pages_init(parent, &parents, &pages);
1187 }
4731d4c7
MT
1188}
1189
cea0f0e7
AK
1190static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1191 gfn_t gfn,
1192 gva_t gaddr,
1193 unsigned level,
f6e2c02b 1194 int direct,
41074d07 1195 unsigned access,
f7d9c7b7 1196 u64 *parent_pte)
cea0f0e7
AK
1197{
1198 union kvm_mmu_page_role role;
1199 unsigned index;
1200 unsigned quadrant;
1201 struct hlist_head *bucket;
4db35314 1202 struct kvm_mmu_page *sp;
4731d4c7 1203 struct hlist_node *node, *tmp;
cea0f0e7 1204
a770f6f2 1205 role = vcpu->arch.mmu.base_role;
cea0f0e7 1206 role.level = level;
f6e2c02b 1207 role.direct = direct;
41074d07 1208 role.access = access;
ad312c7c 1209 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK
1210 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1211 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1212 role.quadrant = quadrant;
1213 }
b8688d51 1214 pgprintk("%s: looking gfn %lx role %x\n", __func__,
cea0f0e7 1215 gfn, role.word);
1ae0a13d 1216 index = kvm_page_table_hashfn(gfn);
f05e70ac 1217 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT
1218 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1219 if (sp->gfn == gfn) {
1220 if (sp->unsync)
1221 if (kvm_sync_page(vcpu, sp))
1222 continue;
1223
1224 if (sp->role.word != role.word)
1225 continue;
1226
4db35314 1227 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT
1228 if (sp->unsync_children) {
1229 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1230 kvm_mmu_mark_parents_unsync(vcpu, sp);
1231 }
b8688d51 1232 pgprintk("%s: found\n", __func__);
4db35314 1233 return sp;
cea0f0e7 1234 }
dfc5aa00 1235 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK
1236 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1237 if (!sp)
1238 return sp;
b8688d51 1239 pgprintk("%s: adding gfn %lx role %x\n", __func__, gfn, role.word);
4db35314
AK
1240 sp->gfn = gfn;
1241 sp->role = role;
1242 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1243 if (!direct) {
b1a36821
MT
1244 if (rmap_write_protect(vcpu->kvm, gfn))
1245 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT
1246 account_shadowed(vcpu->kvm, gfn);
1247 }
131d8279
AK
1248 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1249 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1250 else
1251 nonpaging_prefetch_page(vcpu, sp);
4db35314 1252 return sp;
cea0f0e7
AK
1253}
1254
2d11123a
AK
1255static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1256 struct kvm_vcpu *vcpu, u64 addr)
1257{
1258 iterator->addr = addr;
1259 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1260 iterator->level = vcpu->arch.mmu.shadow_root_level;
1261 if (iterator->level == PT32E_ROOT_LEVEL) {
1262 iterator->shadow_addr
1263 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1264 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1265 --iterator->level;
1266 if (!iterator->shadow_addr)
1267 iterator->level = 0;
1268 }
1269}
1270
1271static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1272{
1273 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1274 return false;
1275 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1276 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1277 return true;
1278}
1279
1280static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1281{
1282 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1283 --iterator->level;
1284}
1285
90cb0529 1286static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1287 struct kvm_mmu_page *sp)
a436036b 1288{
697fe2e2
AK
1289 unsigned i;
1290 u64 *pt;
1291 u64 ent;
1292
4db35314 1293 pt = sp->spt;
697fe2e2 1294
4db35314 1295 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
697fe2e2 1296 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
c7addb90 1297 if (is_shadow_present_pte(pt[i]))
290fc38d 1298 rmap_remove(kvm, &pt[i]);
c7addb90 1299 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2
AK
1300 }
1301 return;
1302 }
1303
1304 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1305 ent = pt[i];
1306
05da4558
MT
1307 if (is_shadow_present_pte(ent)) {
1308 if (!is_large_pte(ent)) {
1309 ent &= PT64_BASE_ADDR_MASK;
1310 mmu_page_remove_parent_pte(page_header(ent),
1311 &pt[i]);
1312 } else {
1313 --kvm->stat.lpages;
1314 rmap_remove(kvm, &pt[i]);
1315 }
1316 }
c7addb90 1317 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1318 }
a436036b
AK
1319}
1320
4db35314 1321static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1322{
4db35314 1323 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK
1324}
1325
12b7d28f
AK
1326static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1327{
1328 int i;
1329
1330 for (i = 0; i < KVM_MAX_VCPUS; ++i)
1331 if (kvm->vcpus[i])
ad312c7c 1332 kvm->vcpus[i]->arch.last_pte_updated = NULL;
12b7d28f
AK
1333}
1334
31aa2b44 1335static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK
1336{
1337 u64 *parent_pte;
1338
4db35314
AK
1339 while (sp->multimapped || sp->parent_pte) {
1340 if (!sp->multimapped)
1341 parent_pte = sp->parent_pte;
a436036b
AK
1342 else {
1343 struct kvm_pte_chain *chain;
1344
4db35314 1345 chain = container_of(sp->parent_ptes.first,
a436036b
AK
1346 struct kvm_pte_chain, link);
1347 parent_pte = chain->parent_ptes[0];
1348 }
697fe2e2 1349 BUG_ON(!parent_pte);
4db35314 1350 kvm_mmu_put_page(sp, parent_pte);
c7addb90 1351 set_shadow_pte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1352 }
31aa2b44
AK
1353}
1354
60c8aec6
MT
1355static int mmu_zap_unsync_children(struct kvm *kvm,
1356 struct kvm_mmu_page *parent)
4731d4c7 1357{
60c8aec6
MT
1358 int i, zapped = 0;
1359 struct mmu_page_path parents;
1360 struct kvm_mmu_pages pages;
4731d4c7 1361
60c8aec6 1362 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1363 return 0;
60c8aec6
MT
1364
1365 kvm_mmu_pages_init(parent, &parents, &pages);
1366 while (mmu_unsync_walk(parent, &pages)) {
1367 struct kvm_mmu_page *sp;
1368
1369 for_each_sp(pages, sp, parents, i) {
1370 kvm_mmu_zap_page(kvm, sp);
1371 mmu_pages_clear_parents(&parents);
1372 }
1373 zapped += pages.nr;
1374 kvm_mmu_pages_init(parent, &parents, &pages);
1375 }
1376
1377 return zapped;
4731d4c7
MT
1378}
1379
07385413 1380static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1381{
4731d4c7 1382 int ret;
31aa2b44 1383 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1384 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1385 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1386 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1387 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1388 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1389 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT
1390 if (sp->unsync)
1391 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK
1392 if (!sp->root_count) {
1393 hlist_del(&sp->hash_link);
1394 kvm_mmu_free_page(kvm, sp);
2e53d63a 1395 } else {
2e53d63a 1396 sp->role.invalid = 1;
5b5c6a5a 1397 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT
1398 kvm_reload_remote_mmus(kvm);
1399 }
12b7d28f 1400 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1401 return ret;
a436036b
AK
1402}
1403
82ce2c96
IE
1404/*
1405 * Changing the number of mmu pages allocated to the vm
1406 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1407 */
1408void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1409{
025dbbf3
MT
1410 int used_pages;
1411
1412 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1413 used_pages = max(0, used_pages);
1414
82ce2c96
IE
1415 /*
1416 * If we set the number of mmu pages to be smaller be than the
1417 * number of actived pages , we must to free some mmu pages before we
1418 * change the value
1419 */
1420
025dbbf3
MT
1421 if (used_pages > kvm_nr_mmu_pages) {
1422 while (used_pages > kvm_nr_mmu_pages) {
82ce2c96
IE
1423 struct kvm_mmu_page *page;
1424
f05e70ac 1425 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE
1426 struct kvm_mmu_page, link);
1427 kvm_mmu_zap_page(kvm, page);
025dbbf3 1428 used_pages--;
82ce2c96 1429 }
f05e70ac 1430 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE
1431 }
1432 else
f05e70ac
ZX
1433 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1434 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1435
f05e70ac 1436 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE
1437}
1438
f67a46f4 1439static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK
1440{
1441 unsigned index;
1442 struct hlist_head *bucket;
4db35314 1443 struct kvm_mmu_page *sp;
a436036b
AK
1444 struct hlist_node *node, *n;
1445 int r;
1446
b8688d51 1447 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1448 r = 0;
1ae0a13d 1449 index = kvm_page_table_hashfn(gfn);
f05e70ac 1450 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1451 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1452 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1453 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1454 sp->role.word);
a436036b 1455 r = 1;
07385413
MT
1456 if (kvm_mmu_zap_page(kvm, sp))
1457 n = bucket->first;
a436036b
AK
1458 }
1459 return r;
cea0f0e7
AK
1460}
1461
f67a46f4 1462static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1463{
4677a3b6
AK
1464 unsigned index;
1465 struct hlist_head *bucket;
4db35314 1466 struct kvm_mmu_page *sp;
4677a3b6 1467 struct hlist_node *node, *nn;
97a0a01e 1468
4677a3b6
AK
1469 index = kvm_page_table_hashfn(gfn);
1470 bucket = &kvm->arch.mmu_page_hash[index];
1471 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1472 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK
1473 && !sp->role.invalid) {
1474 pgprintk("%s: zap %lx %x\n",
1475 __func__, gfn, sp->role.word);
1476 kvm_mmu_zap_page(kvm, sp);
1477 }
97a0a01e
AK
1478 }
1479}
1480
38c335f1 1481static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1482{
38c335f1 1483 int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn));
4db35314 1484 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1485
291f26bc 1486 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK
1487}
1488
6844dec6
MT
1489static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1490{
1491 int i;
1492 u64 *pt = sp->spt;
1493
1494 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1495 return;
1496
1497 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1498 if (pt[i] == shadow_notrap_nonpresent_pte)
1499 set_shadow_pte(&pt[i], shadow_trap_nonpresent_pte);
1500 }
1501}
1502
039576c0
AK
1503struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1504{
72dc67a6
IE
1505 struct page *page;
1506
ad312c7c 1507 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK
1508
1509 if (gpa == UNMAPPED_GVA)
1510 return NULL;
72dc67a6 1511
72dc67a6 1512 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE
1513
1514 return page;
039576c0
AK
1515}
1516
74be52e3
SY
1517/*
1518 * The function is based on mtrr_type_lookup() in
1519 * arch/x86/kernel/cpu/mtrr/generic.c
1520 */
1521static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1522 u64 start, u64 end)
1523{
1524 int i;
1525 u64 base, mask;
1526 u8 prev_match, curr_match;
1527 int num_var_ranges = KVM_NR_VAR_MTRR;
1528
1529 if (!mtrr_state->enabled)
1530 return 0xFF;
1531
1532 /* Make end inclusive end, instead of exclusive */
1533 end--;
1534
1535 /* Look in fixed ranges. Just return the type as per start */
1536 if (mtrr_state->have_fixed && (start < 0x100000)) {
1537 int idx;
1538
1539 if (start < 0x80000) {
1540 idx = 0;
1541 idx += (start >> 16);
1542 return mtrr_state->fixed_ranges[idx];
1543 } else if (start < 0xC0000) {
1544 idx = 1 * 8;
1545 idx += ((start - 0x80000) >> 14);
1546 return mtrr_state->fixed_ranges[idx];
1547 } else if (start < 0x1000000) {
1548 idx = 3 * 8;
1549 idx += ((start - 0xC0000) >> 12);
1550 return mtrr_state->fixed_ranges[idx];
1551 }
1552 }
1553
1554 /*
1555 * Look in variable ranges
1556 * Look of multiple ranges matching this address and pick type
1557 * as per MTRR precedence
1558 */
1559 if (!(mtrr_state->enabled & 2))
1560 return mtrr_state->def_type;
1561
1562 prev_match = 0xFF;
1563 for (i = 0; i < num_var_ranges; ++i) {
1564 unsigned short start_state, end_state;
1565
1566 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1567 continue;
1568
1569 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1570 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1571 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1572 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1573
1574 start_state = ((start & mask) == (base & mask));
1575 end_state = ((end & mask) == (base & mask));
1576 if (start_state != end_state)
1577 return 0xFE;
1578
1579 if ((start & mask) != (base & mask))
1580 continue;
1581
1582 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1583 if (prev_match == 0xFF) {
1584 prev_match = curr_match;
1585 continue;
1586 }
1587
1588 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1589 curr_match == MTRR_TYPE_UNCACHABLE)
1590 return MTRR_TYPE_UNCACHABLE;
1591
1592 if ((prev_match == MTRR_TYPE_WRBACK &&
1593 curr_match == MTRR_TYPE_WRTHROUGH) ||
1594 (prev_match == MTRR_TYPE_WRTHROUGH &&
1595 curr_match == MTRR_TYPE_WRBACK)) {
1596 prev_match = MTRR_TYPE_WRTHROUGH;
1597 curr_match = MTRR_TYPE_WRTHROUGH;
1598 }
1599
1600 if (prev_match != curr_match)
1601 return MTRR_TYPE_UNCACHABLE;
1602 }
1603
1604 if (prev_match != 0xFF)
1605 return prev_match;
1606
1607 return mtrr_state->def_type;
1608}
1609
4b12f0de 1610u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY
1611{
1612 u8 mtrr;
1613
1614 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1615 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1616 if (mtrr == 0xfe || mtrr == 0xff)
1617 mtrr = MTRR_TYPE_WRBACK;
1618 return mtrr;
1619}
4b12f0de 1620EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1621
4731d4c7
MT
1622static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1623{
1624 unsigned index;
1625 struct hlist_head *bucket;
1626 struct kvm_mmu_page *s;
1627 struct hlist_node *node, *n;
1628
1629 index = kvm_page_table_hashfn(sp->gfn);
1630 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1631 /* don't unsync if pagetable is shadowed with multiple roles */
1632 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1633 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT
1634 continue;
1635 if (s->role.word != sp->role.word)
1636 return 1;
1637 }
4731d4c7
MT
1638 ++vcpu->kvm->stat.mmu_unsync;
1639 sp->unsync = 1;
6cffe8ca 1640
c2d0ee46 1641 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1642
4731d4c7
MT
1643 mmu_convert_notrap(sp);
1644 return 0;
1645}
1646
1647static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1648 bool can_unsync)
1649{
1650 struct kvm_mmu_page *shadow;
1651
1652 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1653 if (shadow) {
1654 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1655 return 1;
1656 if (shadow->unsync)
1657 return 0;
582801a9 1658 if (can_unsync && oos_shadow)
4731d4c7
MT
1659 return kvm_unsync_page(vcpu, shadow);
1660 return 1;
1661 }
1662 return 0;
1663}
1664
1e73f9dd
MT
1665static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
1666 unsigned pte_access, int user_fault,
1667 int write_fault, int dirty, int largepage,
c2d0ee46 1668 gfn_t gfn, pfn_t pfn, bool speculative,
4731d4c7 1669 bool can_unsync)
1c4f1fd6
AK
1670{
1671 u64 spte;
1e73f9dd 1672 int ret = 0;
64d4d521 1673
1c4f1fd6
AK
1674 /*
1675 * We don't set the accessed bit, since we sometimes want to see
1676 * whether the guest actually used the pte (in order to detect
1677 * demand paging).
1678 */
7b52345e 1679 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1680 if (!speculative)
3201b5d9 1681 spte |= shadow_accessed_mask;
1c4f1fd6
AK
1682 if (!dirty)
1683 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY
1684 if (pte_access & ACC_EXEC_MASK)
1685 spte |= shadow_x_mask;
1686 else
1687 spte |= shadow_nx_mask;
1c4f1fd6 1688 if (pte_access & ACC_USER_MASK)
7b52345e 1689 spte |= shadow_user_mask;
05da4558
MT
1690 if (largepage)
1691 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY
1692 if (tdp_enabled)
1693 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1694 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1695
35149e21 1696 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK
1697
1698 if ((pte_access & ACC_WRITE_MASK)
1699 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1700
38187c83
MT
1701 if (largepage && has_wrprotected_page(vcpu->kvm, gfn)) {
1702 ret = 1;
1703 spte = shadow_trap_nonpresent_pte;
1704 goto set_pte;
1705 }
1706
1c4f1fd6 1707 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1708
ecc5589f
MT
1709 /*
1710 * Optimization: for pte sync, if spte was writable the hash
1711 * lookup is unnecessary (and expensive). Write protection
1712 * is responsibility of mmu_get_page / kvm_sync_page.
1713 * Same reasoning can be applied to dirty page accounting.
1714 */
1715 if (!can_unsync && is_writeble_pte(*shadow_pte))
1716 goto set_pte;
1717
4731d4c7 1718 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1719 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1720 __func__, gfn);
1e73f9dd 1721 ret = 1;
1c4f1fd6 1722 pte_access &= ~ACC_WRITE_MASK;
a378b4e6 1723 if (is_writeble_pte(spte))
1c4f1fd6 1724 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK
1725 }
1726 }
1727
1c4f1fd6
AK
1728 if (pte_access & ACC_WRITE_MASK)
1729 mark_page_dirty(vcpu->kvm, gfn);
1730
38187c83 1731set_pte:
1c4f1fd6 1732 set_shadow_pte(shadow_pte, spte);
1e73f9dd
MT
1733 return ret;
1734}
1735
1e73f9dd
MT
1736static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
1737 unsigned pt_access, unsigned pte_access,
1738 int user_fault, int write_fault, int dirty,
c2d0ee46
MT
1739 int *ptwrite, int largepage, gfn_t gfn,
1740 pfn_t pfn, bool speculative)
1e73f9dd
MT
1741{
1742 int was_rmapped = 0;
1743 int was_writeble = is_writeble_pte(*shadow_pte);
1744
1745 pgprintk("%s: spte %llx access %x write_fault %d"
1746 " user_fault %d gfn %lx\n",
1747 __func__, *shadow_pte, pt_access,
1748 write_fault, user_fault, gfn);
1749
1750 if (is_rmap_pte(*shadow_pte)) {
1751 /*
1752 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1753 * the parent of the now unreachable PTE.
1754 */
1755 if (largepage && !is_large_pte(*shadow_pte)) {
1756 struct kvm_mmu_page *child;
1757 u64 pte = *shadow_pte;
1758
1759 child = page_header(pte & PT64_BASE_ADDR_MASK);
1760 mmu_page_remove_parent_pte(child, shadow_pte);
1761 } else if (pfn != spte_to_pfn(*shadow_pte)) {
1762 pgprintk("hfn old %lx new %lx\n",
1763 spte_to_pfn(*shadow_pte), pfn);
1764 rmap_remove(vcpu->kvm, shadow_pte);
6bed6b9e
JR
1765 } else
1766 was_rmapped = 1;
1e73f9dd
MT
1767 }
1768 if (set_spte(vcpu, shadow_pte, pte_access, user_fault, write_fault,
c2d0ee46 1769 dirty, largepage, gfn, pfn, speculative, true)) {
1e73f9dd
MT
1770 if (write_fault)
1771 *ptwrite = 1;
a378b4e6
MT
1772 kvm_x86_ops->tlb_flush(vcpu);
1773 }
1e73f9dd
MT
1774
1775 pgprintk("%s: setting spte %llx\n", __func__, *shadow_pte);
1776 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
1777 is_large_pte(*shadow_pte)? "2MB" : "4kB",
1778 is_present_pte(*shadow_pte)?"RW":"R", gfn,
1779 *shadow_pte, shadow_pte);
1780 if (!was_rmapped && is_large_pte(*shadow_pte))
05da4558
MT
1781 ++vcpu->kvm->stat.lpages;
1782
1c4f1fd6
AK
1783 page_header_update_slot(vcpu->kvm, shadow_pte, gfn);
1784 if (!was_rmapped) {
05da4558 1785 rmap_add(vcpu, shadow_pte, gfn, largepage);
1c4f1fd6 1786 if (!is_rmap_pte(*shadow_pte))
35149e21 1787 kvm_release_pfn_clean(pfn);
75e68e60
IE
1788 } else {
1789 if (was_writeble)
35149e21 1790 kvm_release_pfn_dirty(pfn);
75e68e60 1791 else
35149e21 1792 kvm_release_pfn_clean(pfn);
1c4f1fd6 1793 }
1b7fcd32 1794 if (speculative) {
ad312c7c 1795 vcpu->arch.last_pte_updated = shadow_pte;
1b7fcd32
AK
1796 vcpu->arch.last_pte_gfn = gfn;
1797 }
1c4f1fd6
AK
1798}
1799
6aa8b732
AK
1800static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1801{
1802}
1803
9f652d21
AK
1804static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
1805 int largepage, gfn_t gfn, pfn_t pfn)
140754bc 1806{
9f652d21 1807 struct kvm_shadow_walk_iterator iterator;
140754bc 1808 struct kvm_mmu_page *sp;
9f652d21 1809 int pt_write = 0;
140754bc 1810 gfn_t pseudo_gfn;
6aa8b732 1811
9f652d21
AK
1812 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
1813 if (iterator.level == PT_PAGE_TABLE_LEVEL
1814 || (largepage && iterator.level == PT_DIRECTORY_LEVEL)) {
1815 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1816 0, write, 1, &pt_write,
c2d0ee46 1817 largepage, gfn, pfn, false);
9f652d21
AK
1818 ++vcpu->stat.pf_fixed;
1819 break;
6aa8b732
AK
1820 }
1821
9f652d21
AK
1822 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1823 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1824 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1825 iterator.level - 1,
1826 1, ACC_ALL, iterator.sptep);
1827 if (!sp) {
1828 pgprintk("nonpaging_map: ENOMEM\n");
1829 kvm_release_pfn_clean(pfn);
1830 return -ENOMEM;
1831 }
140754bc 1832
9f652d21
AK
1833 set_shadow_pte(iterator.sptep,
1834 __pa(sp->spt)
1835 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1836 | shadow_user_mask | shadow_x_mask);
1837 }
1838 }
1839 return pt_write;
6aa8b732
AK
1840}
1841
10589a46
MT
1842static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1843{
1844 int r;
05da4558 1845 int largepage = 0;
35149e21 1846 pfn_t pfn;
e930bffe 1847 unsigned long mmu_seq;
aaee2c94 1848
05da4558
MT
1849 if (is_largepage_backed(vcpu, gfn & ~(KVM_PAGES_PER_HPAGE-1))) {
1850 gfn &= ~(KVM_PAGES_PER_HPAGE-1);
1851 largepage = 1;
1852 }
1853
e930bffe 1854 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 1855 smp_rmb();
35149e21 1856 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 1857
d196e343 1858 /* mmio */
35149e21
AL
1859 if (is_error_pfn(pfn)) {
1860 kvm_release_pfn_clean(pfn);
d196e343
AK
1861 return 1;
1862 }
1863
aaee2c94 1864 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA
1865 if (mmu_notifier_retry(vcpu, mmu_seq))
1866 goto out_unlock;
eb787d10 1867 kvm_mmu_free_some_pages(vcpu);
6c41f428 1868 r = __direct_map(vcpu, v, write, largepage, gfn, pfn);
aaee2c94
MT
1869 spin_unlock(&vcpu->kvm->mmu_lock);
1870
aaee2c94 1871
10589a46 1872 return r;
e930bffe
AA
1873
1874out_unlock:
1875 spin_unlock(&vcpu->kvm->mmu_lock);
1876 kvm_release_pfn_clean(pfn);
1877 return 0;
10589a46
MT
1878}
1879
1880
17ac10ad
AK
1881static void mmu_free_roots(struct kvm_vcpu *vcpu)
1882{
1883 int i;
4db35314 1884 struct kvm_mmu_page *sp;
17ac10ad 1885
ad312c7c 1886 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 1887 return;
aaee2c94 1888 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX
1889 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
1890 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 1891
4db35314
AK
1892 sp = page_header(root);
1893 --sp->root_count;
2e53d63a
MT
1894 if (!sp->root_count && sp->role.invalid)
1895 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 1896 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 1897 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK
1898 return;
1899 }
17ac10ad 1900 for (i = 0; i < 4; ++i) {
ad312c7c 1901 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 1902
417726a3 1903 if (root) {
417726a3 1904 root &= PT64_BASE_ADDR_MASK;
4db35314
AK
1905 sp = page_header(root);
1906 --sp->root_count;
2e53d63a
MT
1907 if (!sp->root_count && sp->role.invalid)
1908 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 1909 }
ad312c7c 1910 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 1911 }
aaee2c94 1912 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 1913 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK
1914}
1915
8986ecc0
MT
1916static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
1917{
1918 int ret = 0;
1919
1920 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
1921 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1922 ret = 1;
1923 }
1924
1925 return ret;
1926}
1927
1928static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK
1929{
1930 int i;
cea0f0e7 1931 gfn_t root_gfn;
4db35314 1932 struct kvm_mmu_page *sp;
f6e2c02b 1933 int direct = 0;
3bb65a22 1934
ad312c7c 1935 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 1936
ad312c7c
ZX
1937 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
1938 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK
1939
1940 ASSERT(!VALID_PAGE(root));
fb72d167 1941 if (tdp_enabled)
f6e2c02b 1942 direct = 1;
8986ecc0
MT
1943 if (mmu_check_root(vcpu, root_gfn))
1944 return 1;
4db35314 1945 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 1946 PT64_ROOT_LEVEL, direct,
fb72d167 1947 ACC_ALL, NULL);
4db35314
AK
1948 root = __pa(sp->spt);
1949 ++sp->root_count;
ad312c7c 1950 vcpu->arch.mmu.root_hpa = root;
8986ecc0 1951 return 0;
17ac10ad 1952 }
f6e2c02b 1953 direct = !is_paging(vcpu);
fb72d167 1954 if (tdp_enabled)
f6e2c02b 1955 direct = 1;
17ac10ad 1956 for (i = 0; i < 4; ++i) {
ad312c7c 1957 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK
1958
1959 ASSERT(!VALID_PAGE(root));
ad312c7c
ZX
1960 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
1961 if (!is_present_pte(vcpu->arch.pdptrs[i])) {
1962 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK
1963 continue;
1964 }
ad312c7c
ZX
1965 root_gfn = vcpu->arch.pdptrs[i] >> PAGE_SHIFT;
1966 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 1967 root_gfn = 0;
8986ecc0
MT
1968 if (mmu_check_root(vcpu, root_gfn))
1969 return 1;
4db35314 1970 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 1971 PT32_ROOT_LEVEL, direct,
f7d9c7b7 1972 ACC_ALL, NULL);
4db35314
AK
1973 root = __pa(sp->spt);
1974 ++sp->root_count;
ad312c7c 1975 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 1976 }
ad312c7c 1977 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 1978 return 0;
17ac10ad
AK
1979}
1980
0ba73cda
MT
1981static void mmu_sync_roots(struct kvm_vcpu *vcpu)
1982{
1983 int i;
1984 struct kvm_mmu_page *sp;
1985
1986 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1987 return;
1988 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
1989 hpa_t root = vcpu->arch.mmu.root_hpa;
1990 sp = page_header(root);
1991 mmu_sync_children(vcpu, sp);
1992 return;
1993 }
1994 for (i = 0; i < 4; ++i) {
1995 hpa_t root = vcpu->arch.mmu.pae_root[i];
1996
8986ecc0 1997 if (root && VALID_PAGE(root)) {
0ba73cda
MT
1998 root &= PT64_BASE_ADDR_MASK;
1999 sp = page_header(root);
2000 mmu_sync_children(vcpu, sp);
2001 }
2002 }
2003}
2004
2005void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2006{
2007 spin_lock(&vcpu->kvm->mmu_lock);
2008 mmu_sync_roots(vcpu);
6cffe8ca 2009 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT
2010}
2011
6aa8b732
AK
2012static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
2013{
2014 return vaddr;
2015}
2016
2017static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2018 u32 error_code)
6aa8b732 2019{
e833240f 2020 gfn_t gfn;
e2dec939 2021 int r;
6aa8b732 2022
b8688d51 2023 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK
2024 r = mmu_topup_memory_caches(vcpu);
2025 if (r)
2026 return r;
714b93da 2027
6aa8b732 2028 ASSERT(vcpu);
ad312c7c 2029 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2030
e833240f 2031 gfn = gva >> PAGE_SHIFT;
6aa8b732 2032
e833240f
AK
2033 return nonpaging_map(vcpu, gva & PAGE_MASK,
2034 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK
2035}
2036
fb72d167
JR
2037static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2038 u32 error_code)
2039{
35149e21 2040 pfn_t pfn;
fb72d167 2041 int r;
05da4558
MT
2042 int largepage = 0;
2043 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2044 unsigned long mmu_seq;
fb72d167
JR
2045
2046 ASSERT(vcpu);
2047 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2048
2049 r = mmu_topup_memory_caches(vcpu);
2050 if (r)
2051 return r;
2052
05da4558
MT
2053 if (is_largepage_backed(vcpu, gfn & ~(KVM_PAGES_PER_HPAGE-1))) {
2054 gfn &= ~(KVM_PAGES_PER_HPAGE-1);
2055 largepage = 1;
2056 }
e930bffe 2057 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2058 smp_rmb();
35149e21 2059 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL
2060 if (is_error_pfn(pfn)) {
2061 kvm_release_pfn_clean(pfn);
fb72d167
JR
2062 return 1;
2063 }
2064 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA
2065 if (mmu_notifier_retry(vcpu, mmu_seq))
2066 goto out_unlock;
fb72d167
JR
2067 kvm_mmu_free_some_pages(vcpu);
2068 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
6c41f428 2069 largepage, gfn, pfn);
fb72d167 2070 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR
2071
2072 return r;
e930bffe
AA
2073
2074out_unlock:
2075 spin_unlock(&vcpu->kvm->mmu_lock);
2076 kvm_release_pfn_clean(pfn);
2077 return 0;
fb72d167
JR
2078}
2079
6aa8b732
AK
2080static void nonpaging_free(struct kvm_vcpu *vcpu)
2081{
17ac10ad 2082 mmu_free_roots(vcpu);
6aa8b732
AK
2083}
2084
2085static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2086{
ad312c7c 2087 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK
2088
2089 context->new_cr3 = nonpaging_new_cr3;
2090 context->page_fault = nonpaging_page_fault;
6aa8b732
AK
2091 context->gva_to_gpa = nonpaging_gva_to_gpa;
2092 context->free = nonpaging_free;
c7addb90 2093 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2094 context->sync_page = nonpaging_sync_page;
a7052897 2095 context->invlpg = nonpaging_invlpg;
cea0f0e7 2096 context->root_level = 0;
6aa8b732 2097 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2098 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
2099 return 0;
2100}
2101
d835dfec 2102void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2103{
1165f5fe 2104 ++vcpu->stat.tlb_flush;
cbdd1bea 2105 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK
2106}
2107
2108static void paging_new_cr3(struct kvm_vcpu *vcpu)
2109{
b8688d51 2110 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2111 mmu_free_roots(vcpu);
6aa8b732
AK
2112}
2113
6aa8b732
AK
2114static void inject_page_fault(struct kvm_vcpu *vcpu,
2115 u64 addr,
2116 u32 err_code)
2117{
c3c91fee 2118 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK
2119}
2120
6aa8b732
AK
2121static void paging_free(struct kvm_vcpu *vcpu)
2122{
2123 nonpaging_free(vcpu);
2124}
2125
82725b20
DE
2126static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2127{
2128 int bit7;
2129
2130 bit7 = (gpte >> 7) & 1;
2131 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2132}
2133
6aa8b732
AK
2134#define PTTYPE 64
2135#include "paging_tmpl.h"
2136#undef PTTYPE
2137
2138#define PTTYPE 32
2139#include "paging_tmpl.h"
2140#undef PTTYPE
2141
82725b20
DE
2142static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2143{
2144 struct kvm_mmu *context = &vcpu->arch.mmu;
2145 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2146 u64 exb_bit_rsvd = 0;
2147
2148 if (!is_nx(vcpu))
2149 exb_bit_rsvd = rsvd_bits(63, 63);
2150 switch (level) {
2151 case PT32_ROOT_LEVEL:
2152 /* no rsvd bits for 2 level 4K page table entries */
2153 context->rsvd_bits_mask[0][1] = 0;
2154 context->rsvd_bits_mask[0][0] = 0;
2155 if (is_cpuid_PSE36())
2156 /* 36bits PSE 4MB page */
2157 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2158 else
2159 /* 32 bits PSE 4MB page */
2160 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2161 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE
2162 break;
2163 case PT32E_ROOT_LEVEL:
20c466b5
DE
2164 context->rsvd_bits_mask[0][2] =
2165 rsvd_bits(maxphyaddr, 63) |
2166 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2167 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2168 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE
2169 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2170 rsvd_bits(maxphyaddr, 62); /* PTE */
2171 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2172 rsvd_bits(maxphyaddr, 62) |
2173 rsvd_bits(13, 20); /* large page */
29a4b933 2174 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE
2175 break;
2176 case PT64_ROOT_LEVEL:
2177 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2178 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2179 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2180 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2181 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2182 rsvd_bits(maxphyaddr, 51);
82725b20
DE
2183 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2184 rsvd_bits(maxphyaddr, 51);
2185 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
2186 context->rsvd_bits_mask[1][2] = context->rsvd_bits_mask[0][2];
2187 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY
2188 rsvd_bits(maxphyaddr, 51) |
2189 rsvd_bits(13, 20); /* large page */
29a4b933 2190 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE
2191 break;
2192 }
2193}
2194
17ac10ad 2195static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2196{
ad312c7c 2197 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK
2198
2199 ASSERT(is_pae(vcpu));
2200 context->new_cr3 = paging_new_cr3;
2201 context->page_fault = paging64_page_fault;
6aa8b732 2202 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2203 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2204 context->sync_page = paging64_sync_page;
a7052897 2205 context->invlpg = paging64_invlpg;
6aa8b732 2206 context->free = paging_free;
17ac10ad
AK
2207 context->root_level = level;
2208 context->shadow_root_level = level;
17c3ba9d 2209 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
2210 return 0;
2211}
2212
17ac10ad
AK
2213static int paging64_init_context(struct kvm_vcpu *vcpu)
2214{
82725b20 2215 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK
2216 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2217}
2218
6aa8b732
AK
2219static int paging32_init_context(struct kvm_vcpu *vcpu)
2220{
ad312c7c 2221 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2222
82725b20 2223 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK
2224 context->new_cr3 = paging_new_cr3;
2225 context->page_fault = paging32_page_fault;
6aa8b732
AK
2226 context->gva_to_gpa = paging32_gva_to_gpa;
2227 context->free = paging_free;
c7addb90 2228 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2229 context->sync_page = paging32_sync_page;
a7052897 2230 context->invlpg = paging32_invlpg;
6aa8b732
AK
2231 context->root_level = PT32_ROOT_LEVEL;
2232 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2233 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
2234 return 0;
2235}
2236
2237static int paging32E_init_context(struct kvm_vcpu *vcpu)
2238{
82725b20 2239 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2240 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK
2241}
2242
fb72d167
JR
2243static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2244{
2245 struct kvm_mmu *context = &vcpu->arch.mmu;
2246
2247 context->new_cr3 = nonpaging_new_cr3;
2248 context->page_fault = tdp_page_fault;
2249 context->free = nonpaging_free;
2250 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2251 context->sync_page = nonpaging_sync_page;
a7052897 2252 context->invlpg = nonpaging_invlpg;
67253af5 2253 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR
2254 context->root_hpa = INVALID_PAGE;
2255
2256 if (!is_paging(vcpu)) {
2257 context->gva_to_gpa = nonpaging_gva_to_gpa;
2258 context->root_level = 0;
2259 } else if (is_long_mode(vcpu)) {
82725b20 2260 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR
2261 context->gva_to_gpa = paging64_gva_to_gpa;
2262 context->root_level = PT64_ROOT_LEVEL;
2263 } else if (is_pae(vcpu)) {
82725b20 2264 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR
2265 context->gva_to_gpa = paging64_gva_to_gpa;
2266 context->root_level = PT32E_ROOT_LEVEL;
2267 } else {
82725b20 2268 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR
2269 context->gva_to_gpa = paging32_gva_to_gpa;
2270 context->root_level = PT32_ROOT_LEVEL;
2271 }
2272
2273 return 0;
2274}
2275
2276static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2277{
a770f6f2
AK
2278 int r;
2279
6aa8b732 2280 ASSERT(vcpu);
ad312c7c 2281 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK
2282
2283 if (!is_paging(vcpu))
a770f6f2 2284 r = nonpaging_init_context(vcpu);
a9058ecd 2285 else if (is_long_mode(vcpu))
a770f6f2 2286 r = paging64_init_context(vcpu);
6aa8b732 2287 else if (is_pae(vcpu))
a770f6f2 2288 r = paging32E_init_context(vcpu);
6aa8b732 2289 else
a770f6f2
AK
2290 r = paging32_init_context(vcpu);
2291
2292 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2293
2294 return r;
6aa8b732
AK
2295}
2296
fb72d167
JR
2297static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2298{
35149e21
AL
2299 vcpu->arch.update_pte.pfn = bad_pfn;
2300
fb72d167
JR
2301 if (tdp_enabled)
2302 return init_kvm_tdp_mmu(vcpu);
2303 else
2304 return init_kvm_softmmu(vcpu);
2305}
2306
6aa8b732
AK
2307static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2308{
2309 ASSERT(vcpu);
ad312c7c
ZX
2310 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2311 vcpu->arch.mmu.free(vcpu);
2312 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK
2313 }
2314}
2315
2316int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK
2317{
2318 destroy_kvm_mmu(vcpu);
2319 return init_kvm_mmu(vcpu);
2320}
8668a3c4 2321EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK
2322
2323int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2324{
714b93da
AK
2325 int r;
2326
e2dec939 2327 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK
2328 if (r)
2329 goto out;
aaee2c94 2330 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2331 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2332 r = mmu_alloc_roots(vcpu);
0ba73cda 2333 mmu_sync_roots(vcpu);
aaee2c94 2334 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT
2335 if (r)
2336 goto out;
ad312c7c 2337 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
17c3ba9d 2338 kvm_mmu_flush_tlb(vcpu);
714b93da
AK
2339out:
2340 return r;
6aa8b732 2341}
17c3ba9d
AK
2342EXPORT_SYMBOL_GPL(kvm_mmu_load);
2343
2344void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2345{
2346 mmu_free_roots(vcpu);
2347}
6aa8b732 2348
09072daf 2349static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2350 struct kvm_mmu_page *sp,
ac1b714e
AK
2351 u64 *spte)
2352{
2353 u64 pte;
2354 struct kvm_mmu_page *child;
2355
2356 pte = *spte;
c7addb90 2357 if (is_shadow_present_pte(pte)) {
05da4558
MT
2358 if (sp->role.level == PT_PAGE_TABLE_LEVEL ||
2359 is_large_pte(pte))
290fc38d 2360 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK
2361 else {
2362 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2363 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK
2364 }
2365 }
c7addb90 2366 set_shadow_pte(spte, shadow_trap_nonpresent_pte);
05da4558
MT
2367 if (is_large_pte(pte))
2368 --vcpu->kvm->stat.lpages;
ac1b714e
AK
2369}
2370
0028425f 2371static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2372 struct kvm_mmu_page *sp,
0028425f 2373 u64 *spte,
489f1d65 2374 const void *new)
0028425f 2375{
30945387
MT
2376 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
2377 if (!vcpu->arch.update_pte.largepage ||
2378 sp->role.glevels == PT32_ROOT_LEVEL) {
2379 ++vcpu->kvm->stat.mmu_pde_zapped;
2380 return;
2381 }
2382 }
0028425f 2383
4cee5764 2384 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2385 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2386 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2387 else
489f1d65 2388 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK
2389}
2390
79539cec
AK
2391static bool need_remote_flush(u64 old, u64 new)
2392{
2393 if (!is_shadow_present_pte(old))
2394 return false;
2395 if (!is_shadow_present_pte(new))
2396 return true;
2397 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2398 return true;
2399 old ^= PT64_NX_MASK;
2400 new ^= PT64_NX_MASK;
2401 return (old & ~new & PT64_PERM_MASK) != 0;
2402}
2403
2404static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2405{
2406 if (need_remote_flush(old, new))
2407 kvm_flush_remote_tlbs(vcpu->kvm);
2408 else
2409 kvm_mmu_flush_tlb(vcpu);
2410}
2411
12b7d28f
AK
2412static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2413{
ad312c7c 2414 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2415
7b52345e 2416 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK
2417}
2418
d7824fff
AK
2419static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2420 const u8 *new, int bytes)
2421{
2422 gfn_t gfn;
2423 int r;
2424 u64 gpte = 0;
35149e21 2425 pfn_t pfn;
d7824fff 2426
05da4558
MT
2427 vcpu->arch.update_pte.largepage = 0;
2428
d7824fff
AK
2429 if (bytes != 4 && bytes != 8)
2430 return;
2431
2432 /*
2433 * Assume that the pte write on a page table of the same type
2434 * as the current vcpu paging mode. This is nearly always true
2435 * (might be false while changing modes). Note it is verified later
2436 * by update_pte().
2437 */
2438 if (is_pae(vcpu)) {
2439 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2440 if ((bytes == 4) && (gpa % 4 == 0)) {
2441 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2442 if (r)
2443 return;
2444 memcpy((void *)&gpte + (gpa % 8), new, 4);
2445 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2446 memcpy((void *)&gpte, new, 8);
2447 }
2448 } else {
2449 if ((bytes == 4) && (gpa % 4 == 0))
2450 memcpy((void *)&gpte, new, 4);
2451 }
2452 if (!is_present_pte(gpte))
2453 return;
2454 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2455
05da4558
MT
2456 if (is_large_pte(gpte) && is_largepage_backed(vcpu, gfn)) {
2457 gfn &= ~(KVM_PAGES_PER_HPAGE-1);
2458 vcpu->arch.update_pte.largepage = 1;
2459 }
e930bffe 2460 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2461 smp_rmb();
35149e21 2462 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2463
35149e21
AL
2464 if (is_error_pfn(pfn)) {
2465 kvm_release_pfn_clean(pfn);
d196e343
AK
2466 return;
2467 }
d7824fff 2468 vcpu->arch.update_pte.gfn = gfn;
35149e21 2469 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK
2470}
2471
1b7fcd32
AK
2472static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2473{
2474 u64 *spte = vcpu->arch.last_pte_updated;
2475
2476 if (spte
2477 && vcpu->arch.last_pte_gfn == gfn
2478 && shadow_accessed_mask
2479 && !(*spte & shadow_accessed_mask)
2480 && is_shadow_present_pte(*spte))
2481 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2482}
2483
09072daf 2484void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT
2485 const u8 *new, int bytes,
2486 bool guest_initiated)
da4a00f0 2487{
9b7a0325 2488 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2489 struct kvm_mmu_page *sp;
0e7bc4b9 2490 struct hlist_node *node, *n;
9b7a0325
AK
2491 struct hlist_head *bucket;
2492 unsigned index;
489f1d65 2493 u64 entry, gentry;
9b7a0325 2494 u64 *spte;
9b7a0325 2495 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2496 unsigned pte_size;
9b7a0325 2497 unsigned page_offset;
0e7bc4b9 2498 unsigned misaligned;
fce0657f 2499 unsigned quadrant;
9b7a0325 2500 int level;
86a5ba02 2501 int flooded = 0;
ac1b714e 2502 int npte;
489f1d65 2503 int r;
9b7a0325 2504
b8688d51 2505 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
d7824fff 2506 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 2507 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2508 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2509 kvm_mmu_free_some_pages(vcpu);
4cee5764 2510 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2511 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT
2512 if (guest_initiated) {
2513 if (gfn == vcpu->arch.last_pt_write_gfn
2514 && !last_updated_pte_accessed(vcpu)) {
2515 ++vcpu->arch.last_pt_write_count;
2516 if (vcpu->arch.last_pt_write_count >= 3)
2517 flooded = 1;
2518 } else {
2519 vcpu->arch.last_pt_write_gfn = gfn;
2520 vcpu->arch.last_pt_write_count = 1;
2521 vcpu->arch.last_pte_updated = NULL;
2522 }
86a5ba02 2523 }
1ae0a13d 2524 index = kvm_page_table_hashfn(gfn);
f05e70ac 2525 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2526 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2527 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2528 continue;
4db35314 2529 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2530 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2531 misaligned |= bytes < 4;
86a5ba02 2532 if (misaligned || flooded) {
0e7bc4b9
AK
2533 /*
2534 * Misaligned accesses are too much trouble to fix
2535 * up; also, they usually indicate a page is not used
2536 * as a page table.
86a5ba02
AK
2537 *
2538 * If we're seeing too many writes to a page,
2539 * it may no longer be a page table, or we may be
2540 * forking, in which case it is better to unmap the
2541 * page.
0e7bc4b9
AK
2542 */
2543 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2544 gpa, bytes, sp->role.word);
07385413
MT
2545 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2546 n = bucket->first;
4cee5764 2547 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK
2548 continue;
2549 }
9b7a0325 2550 page_offset = offset;
4db35314 2551 level = sp->role.level;
ac1b714e 2552 npte = 1;
4db35314 2553 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK
2554 page_offset <<= 1; /* 32->64 */
2555 /*
2556 * A 32-bit pde maps 4MB while the shadow pdes map
2557 * only 2MB. So we need to double the offset again
2558 * and zap two pdes instead of one.
2559 */
2560 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2561 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK
2562 page_offset <<= 1;
2563 npte = 2;
2564 }
fce0657f 2565 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2566 page_offset &= ~PAGE_MASK;
4db35314 2567 if (quadrant != sp->role.quadrant)
fce0657f 2568 continue;
9b7a0325 2569 }
4db35314 2570 spte = &sp->spt[page_offset / sizeof(*spte)];
489f1d65
DE
2571 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2572 gentry = 0;
2573 r = kvm_read_guest_atomic(vcpu->kvm,
2574 gpa & ~(u64)(pte_size - 1),
2575 &gentry, pte_size);
2576 new = (const void *)&gentry;
2577 if (r < 0)
2578 new = NULL;
2579 }
ac1b714e 2580 while (npte--) {
79539cec 2581 entry = *spte;
4db35314 2582 mmu_pte_write_zap_pte(vcpu, sp, spte);
489f1d65
DE
2583 if (new)
2584 mmu_pte_write_new_pte(vcpu, sp, spte, new);
79539cec 2585 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2586 ++spte;
9b7a0325 2587 }
9b7a0325 2588 }
c7addb90 2589 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2590 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL
2591 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2592 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2593 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2594 }
da4a00f0
AK
2595}
2596
a436036b
AK
2597int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2598{
10589a46
MT
2599 gpa_t gpa;
2600 int r;
a436036b 2601
10589a46 2602 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
10589a46 2603
aaee2c94 2604 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2605 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2606 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2607 return r;
a436036b 2608}
577bdc49 2609EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2610
22d95b12 2611void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2612{
f05e70ac 2613 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES) {
4db35314 2614 struct kvm_mmu_page *sp;
ebeace86 2615
f05e70ac 2616 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK
2617 struct kvm_mmu_page, link);
2618 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2619 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK
2620 }
2621}
ebeace86 2622
3067714c
AK
2623int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2624{
2625 int r;
2626 enum emulation_result er;
2627
ad312c7c 2628 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK
2629 if (r < 0)
2630 goto out;
2631
2632 if (!r) {
2633 r = 1;
2634 goto out;
2635 }
2636
b733bfb5
AK
2637 r = mmu_topup_memory_caches(vcpu);
2638 if (r)
2639 goto out;
2640
3067714c 2641 er = emulate_instruction(vcpu, vcpu->run, cr2, error_code, 0);
3067714c
AK
2642
2643 switch (er) {
2644 case EMULATE_DONE:
2645 return 1;
2646 case EMULATE_DO_MMIO:
2647 ++vcpu->stat.mmio_exits;
2648 return 0;
2649 case EMULATE_FAIL:
2650 kvm_report_emulation_failure(vcpu, "pagetable");
2651 return 1;
2652 default:
2653 BUG();
2654 }
2655out:
3067714c
AK
2656 return r;
2657}
2658EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2659
a7052897
MT
2660void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2661{
a7052897 2662 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT
2663 kvm_mmu_flush_tlb(vcpu);
2664 ++vcpu->stat.invlpg;
2665}
2666EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2667
18552672
JR
2668void kvm_enable_tdp(void)
2669{
2670 tdp_enabled = true;
2671}
2672EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2673
5f4cb662
JR
2674void kvm_disable_tdp(void)
2675{
2676 tdp_enabled = false;
2677}
2678EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2679
6aa8b732
AK
2680static void free_mmu_pages(struct kvm_vcpu *vcpu)
2681{
ad312c7c 2682 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK
2683}
2684
2685static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2686{
17ac10ad 2687 struct page *page;
6aa8b732
AK
2688 int i;
2689
2690 ASSERT(vcpu);
2691
f05e70ac
ZX
2692 if (vcpu->kvm->arch.n_requested_mmu_pages)
2693 vcpu->kvm->arch.n_free_mmu_pages =
2694 vcpu->kvm->arch.n_requested_mmu_pages;
82ce2c96 2695 else
f05e70ac
ZX
2696 vcpu->kvm->arch.n_free_mmu_pages =
2697 vcpu->kvm->arch.n_alloc_mmu_pages;
17ac10ad
AK
2698 /*
2699 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2700 * Therefore we need to allocate shadow page tables in the first
2701 * 4GB of memory, which happens to fit the DMA32 zone.
2702 */
2703 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2704 if (!page)
2705 goto error_1;
ad312c7c 2706 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2707 for (i = 0; i < 4; ++i)
ad312c7c 2708 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2709
6aa8b732
AK
2710 return 0;
2711
2712error_1:
2713 free_mmu_pages(vcpu);
2714 return -ENOMEM;
2715}
2716
8018c27b 2717int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2718{
6aa8b732 2719 ASSERT(vcpu);
ad312c7c 2720 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2721
8018c27b
IM
2722 return alloc_mmu_pages(vcpu);
2723}
6aa8b732 2724
8018c27b
IM
2725int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2726{
2727 ASSERT(vcpu);
ad312c7c 2728 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2729
8018c27b 2730 return init_kvm_mmu(vcpu);
6aa8b732
AK
2731}
2732
2733void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2734{
2735 ASSERT(vcpu);
2736
2737 destroy_kvm_mmu(vcpu);
2738 free_mmu_pages(vcpu);
714b93da 2739 mmu_free_memory_caches(vcpu);
6aa8b732
AK
2740}
2741
90cb0529 2742void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2743{
4db35314 2744 struct kvm_mmu_page *sp;
6aa8b732 2745
f05e70ac 2746 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK
2747 int i;
2748 u64 *pt;
2749
291f26bc 2750 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK
2751 continue;
2752
4db35314 2753 pt = sp->spt;
6aa8b732
AK
2754 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2755 /* avoid RMW */
9647c14c 2756 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2757 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2758 }
171d595d 2759 kvm_flush_remote_tlbs(kvm);
6aa8b732 2760}
37a7d8b0 2761
90cb0529 2762void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2763{
4db35314 2764 struct kvm_mmu_page *sp, *node;
e0fa826f 2765
aaee2c94 2766 spin_lock(&kvm->mmu_lock);
f05e70ac 2767 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT
2768 if (kvm_mmu_zap_page(kvm, sp))
2769 node = container_of(kvm->arch.active_mmu_pages.next,
2770 struct kvm_mmu_page, link);
aaee2c94 2771 spin_unlock(&kvm->mmu_lock);
e0fa826f 2772
90cb0529 2773 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL
2774}
2775
8b2cf73c 2776static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE
2777{
2778 struct kvm_mmu_page *page;
2779
2780 page = container_of(kvm->arch.active_mmu_pages.prev,
2781 struct kvm_mmu_page, link);
2782 kvm_mmu_zap_page(kvm, page);
2783}
2784
2785static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2786{
2787 struct kvm *kvm;
2788 struct kvm *kvm_freed = NULL;
2789 int cache_count = 0;
2790
2791 spin_lock(&kvm_lock);
2792
2793 list_for_each_entry(kvm, &vm_list, vm_list) {
2794 int npages;
2795
5a4c9288
MT
2796 if (!down_read_trylock(&kvm->slots_lock))
2797 continue;
3ee16c81
IE
2798 spin_lock(&kvm->mmu_lock);
2799 npages = kvm->arch.n_alloc_mmu_pages -
2800 kvm->arch.n_free_mmu_pages;
2801 cache_count += npages;
2802 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2803 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2804 cache_count--;
2805 kvm_freed = kvm;
2806 }
2807 nr_to_scan--;
2808
2809 spin_unlock(&kvm->mmu_lock);
5a4c9288 2810 up_read(&kvm->slots_lock);
3ee16c81
IE
2811 }
2812 if (kvm_freed)
2813 list_move_tail(&kvm_freed->vm_list, &vm_list);
2814
2815 spin_unlock(&kvm_lock);
2816
2817 return cache_count;
2818}
2819
2820static struct shrinker mmu_shrinker = {
2821 .shrink = mmu_shrink,
2822 .seeks = DEFAULT_SEEKS * 10,
2823};
2824
2ddfd20e 2825static void mmu_destroy_caches(void)
b5a33a75
AK
2826{
2827 if (pte_chain_cache)
2828 kmem_cache_destroy(pte_chain_cache);
2829 if (rmap_desc_cache)
2830 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK
2831 if (mmu_page_header_cache)
2832 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK
2833}
2834
3ee16c81
IE
2835void kvm_mmu_module_exit(void)
2836{
2837 mmu_destroy_caches();
2838 unregister_shrinker(&mmu_shrinker);
2839}
2840
b5a33a75
AK
2841int kvm_mmu_module_init(void)
2842{
2843 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2844 sizeof(struct kvm_pte_chain),
20c2df83 2845 0, 0, NULL);
b5a33a75
AK
2846 if (!pte_chain_cache)
2847 goto nomem;
2848 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2849 sizeof(struct kvm_rmap_desc),
20c2df83 2850 0, 0, NULL);
b5a33a75
AK
2851 if (!rmap_desc_cache)
2852 goto nomem;
2853
d3d25b04
AK
2854 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2855 sizeof(struct kvm_mmu_page),
20c2df83 2856 0, 0, NULL);
d3d25b04
AK
2857 if (!mmu_page_header_cache)
2858 goto nomem;
2859
3ee16c81
IE
2860 register_shrinker(&mmu_shrinker);
2861
b5a33a75
AK
2862 return 0;
2863
2864nomem:
3ee16c81 2865 mmu_destroy_caches();
b5a33a75
AK
2866 return -ENOMEM;
2867}
2868
3ad82a7e
ZX
2869/*
2870 * Caculate mmu pages needed for kvm.
2871 */
2872unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
2873{
2874 int i;
2875 unsigned int nr_mmu_pages;
2876 unsigned int nr_pages = 0;
2877
2878 for (i = 0; i < kvm->nmemslots; i++)
2879 nr_pages += kvm->memslots[i].npages;
2880
2881 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
2882 nr_mmu_pages = max(nr_mmu_pages,
2883 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
2884
2885 return nr_mmu_pages;
2886}
2887
2f333bcb
MT
2888static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
2889 unsigned len)
2890{
2891 if (len > buffer->len)
2892 return NULL;
2893 return buffer->ptr;
2894}
2895
2896static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
2897 unsigned len)
2898{
2899 void *ret;
2900
2901 ret = pv_mmu_peek_buffer(buffer, len);
2902 if (!ret)
2903 return ret;
2904 buffer->ptr += len;
2905 buffer->len -= len;
2906 buffer->processed += len;
2907 return ret;
2908}
2909
2910static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
2911 gpa_t addr, gpa_t value)
2912{
2913 int bytes = 8;
2914 int r;
2915
2916 if (!is_long_mode(vcpu) && !is_pae(vcpu))
2917 bytes = 4;
2918
2919 r = mmu_topup_memory_caches(vcpu);
2920 if (r)
2921 return r;
2922
3200f405 2923 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT
2924 return -EFAULT;
2925
2926 return 1;
2927}
2928
2929static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
2930{
a8cd0244 2931 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT
2932 return 1;
2933}
2934
2935static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
2936{
2937 spin_lock(&vcpu->kvm->mmu_lock);
2938 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
2939 spin_unlock(&vcpu->kvm->mmu_lock);
2940 return 1;
2941}
2942
2943static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
2944 struct kvm_pv_mmu_op_buffer *buffer)
2945{
2946 struct kvm_mmu_op_header *header;
2947
2948 header = pv_mmu_peek_buffer(buffer, sizeof *header);
2949 if (!header)
2950 return 0;
2951 switch (header->op) {
2952 case KVM_MMU_OP_WRITE_PTE: {
2953 struct kvm_mmu_op_write_pte *wpte;
2954
2955 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
2956 if (!wpte)
2957 return 0;
2958 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
2959 wpte->pte_val);
2960 }
2961 case KVM_MMU_OP_FLUSH_TLB: {
2962 struct kvm_mmu_op_flush_tlb *ftlb;
2963
2964 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
2965 if (!ftlb)
2966 return 0;
2967 return kvm_pv_mmu_flush_tlb(vcpu);
2968 }
2969 case KVM_MMU_OP_RELEASE_PT: {
2970 struct kvm_mmu_op_release_pt *rpt;
2971
2972 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
2973 if (!rpt)
2974 return 0;
2975 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
2976 }
2977 default: return 0;
2978 }
2979}
2980
2981int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
2982 gpa_t addr, unsigned long *ret)
2983{
2984 int r;
6ad18fba 2985 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 2986
6ad18fba
DH
2987 buffer->ptr = buffer->buf;
2988 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
2989 buffer->processed = 0;
2f333bcb 2990
6ad18fba 2991 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT
2992 if (r)
2993 goto out;
2994
6ad18fba
DH
2995 while (buffer->len) {
2996 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT
2997 if (r < 0)
2998 goto out;
2999 if (r == 0)
3000 break;
3001 }
3002
3003 r = 1;
3004out:
6ad18fba 3005 *ret = buffer->processed;
2f333bcb
MT
3006 return r;
3007}
3008
37a7d8b0
AK
3009#ifdef AUDIT
3010
3011static const char *audit_msg;
3012
3013static gva_t canonicalize(gva_t gva)
3014{
3015#ifdef CONFIG_X86_64
3016 gva = (long long)(gva << 16) >> 16;
3017#endif
3018 return gva;
3019}
3020
3021static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3022 gva_t va, int level)
3023{
3024 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3025 int i;
3026 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3027
3028 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3029 u64 ent = pt[i];
3030
c7addb90 3031 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK
3032 continue;
3033
3034 va = canonicalize(va);
c7addb90
AK
3035 if (level > 1) {
3036 if (ent == shadow_notrap_nonpresent_pte)
3037 printk(KERN_ERR "audit: (%s) nontrapping pte"
3038 " in nonleaf level: levels %d gva %lx"
3039 " level %d pte %llx\n", audit_msg,
ad312c7c 3040 vcpu->arch.mmu.root_level, va, level, ent);
34382539
JK
3041 else
3042 audit_mappings_page(vcpu, ent, va, level - 1);
c7addb90 3043 } else {
ad312c7c 3044 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
34382539
JK
3045 gfn_t gfn = gpa >> PAGE_SHIFT;
3046 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3047 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3048
c7addb90 3049 if (is_shadow_present_pte(ent)
37a7d8b0 3050 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK
3051 printk(KERN_ERR "xx audit error: (%s) levels %d"
3052 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3053 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD
3054 va, gpa, hpa, ent,
3055 is_shadow_present_pte(ent));
c7addb90
AK
3056 else if (ent == shadow_notrap_nonpresent_pte
3057 && !is_error_hpa(hpa))
3058 printk(KERN_ERR "audit: (%s) notrap shadow,"
3059 " valid guest gva %lx\n", audit_msg, va);
35149e21 3060 kvm_release_pfn_clean(pfn);
c7addb90 3061
37a7d8b0
AK
3062 }
3063 }
3064}
3065
3066static void audit_mappings(struct kvm_vcpu *vcpu)
3067{
1ea252af 3068 unsigned i;
37a7d8b0 3069
ad312c7c
ZX
3070 if (vcpu->arch.mmu.root_level == 4)
3071 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK
3072 else
3073 for (i = 0; i < 4; ++i)
ad312c7c 3074 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3075 audit_mappings_page(vcpu,
ad312c7c 3076 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK
3077 i << 30,
3078 2);
3079}
3080
3081static int count_rmaps(struct kvm_vcpu *vcpu)
3082{
3083 int nmaps = 0;
3084 int i, j, k;
3085
3086 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
3087 struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
3088 struct kvm_rmap_desc *d;
3089
3090 for (j = 0; j < m->npages; ++j) {
290fc38d 3091 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3092
290fc38d 3093 if (!*rmapp)
37a7d8b0 3094 continue;
290fc38d 3095 if (!(*rmapp & 1)) {
37a7d8b0
AK
3096 ++nmaps;
3097 continue;
3098 }
290fc38d 3099 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK
3100 while (d) {
3101 for (k = 0; k < RMAP_EXT; ++k)
3102 if (d->shadow_ptes[k])
3103 ++nmaps;
3104 else
3105 break;
3106 d = d->more;
3107 }
3108 }
3109 }
3110 return nmaps;
3111}
3112
3113static int count_writable_mappings(struct kvm_vcpu *vcpu)
3114{
3115 int nmaps = 0;
4db35314 3116 struct kvm_mmu_page *sp;
37a7d8b0
AK
3117 int i;
3118
f05e70ac 3119 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3120 u64 *pt = sp->spt;
37a7d8b0 3121
4db35314 3122 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK
3123 continue;
3124
3125 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3126 u64 ent = pt[i];
3127
3128 if (!(ent & PT_PRESENT_MASK))
3129 continue;
3130 if (!(ent & PT_WRITABLE_MASK))
3131 continue;
3132 ++nmaps;
3133 }
3134 }
3135 return nmaps;
3136}
3137
3138static void audit_rmap(struct kvm_vcpu *vcpu)
3139{
3140 int n_rmap = count_rmaps(vcpu);
3141 int n_actual = count_writable_mappings(vcpu);
3142
3143 if (n_rmap != n_actual)
3144 printk(KERN_ERR "%s: (%s) rmap %d actual %d\n",
b8688d51 3145 __func__, audit_msg, n_rmap, n_actual);
37a7d8b0
AK
3146}
3147
3148static void audit_write_protection(struct kvm_vcpu *vcpu)
3149{
4db35314 3150 struct kvm_mmu_page *sp;
290fc38d
IE
3151 struct kvm_memory_slot *slot;
3152 unsigned long *rmapp;
3153 gfn_t gfn;
37a7d8b0 3154
f05e70ac 3155 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3156 if (sp->role.direct)
37a7d8b0
AK
3157 continue;
3158
4db35314 3159 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3160 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d
IE
3161 rmapp = &slot->rmap[gfn - slot->base_gfn];
3162 if (*rmapp)
37a7d8b0
AK
3163 printk(KERN_ERR "%s: (%s) shadow page has writable"
3164 " mappings: gfn %lx role %x\n",
b8688d51 3165 __func__, audit_msg, sp->gfn,
4db35314 3166 sp->role.word);
37a7d8b0
AK
3167 }
3168}
3169
3170static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3171{
3172 int olddbg = dbg;
3173
3174 dbg = 0;
3175 audit_msg = msg;
3176 audit_rmap(vcpu);
3177 audit_write_protection(vcpu);
3178 audit_mappings(vcpu);
3179 dbg = olddbg;
3180}
3181
3182#endif