[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / mmu.h

#ifndef __KVM_X86_MMU_H
#define __KVM_X86_MMU_H

#include <linux/kvm_host.h>
#include "kvm_cache_regs.h"

#define PT64_PT_BITS 9
#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
#define PT32_PT_BITS 10
#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)

#define PT_WRITABLE_SHIFT 1
#define PT_USER_SHIFT 2

#define PT_PRESENT_MASK (1ULL << 0)
#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
#define PT_USER_MASK (1ULL << PT_USER_SHIFT)
#define PT_PWT_MASK (1ULL << 3)
#define PT_PCD_MASK (1ULL << 4)
#define PT_ACCESSED_SHIFT 5
#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
#define PT_DIRTY_SHIFT 6
#define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
#define PT_PAGE_SIZE_SHIFT 7
#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
#define PT_PAT_MASK (1ULL << 7)
#define PT_GLOBAL_MASK (1ULL << 8)
#define PT64_NX_SHIFT 63
#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)

#define PT_PAT_SHIFT 7
#define PT_DIR_PAT_SHIFT 12
#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)

#define PT32_DIR_PSE36_SIZE 4
#define PT32_DIR_PSE36_SHIFT 13
#define PT32_DIR_PSE36_MASK \
	(((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)

#define PT64_ROOT_5LEVEL 5
#define PT64_ROOT_4LEVEL 4
#define PT32_ROOT_LEVEL 2
#define PT32E_ROOT_LEVEL 3

#define PT_PDPE_LEVEL 3
#define PT_DIRECTORY_LEVEL 2
#define PT_PAGE_TABLE_LEVEL 1
#define PT_MAX_HUGEPAGE_LEVEL (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES - 1)

static inline u64 rsvd_bits(int s, int e)
{
	if (e < s)
		return 0;

	return ((1ULL << (e - s + 1)) - 1) << s;
}

void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value);

void
reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context);

void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);
void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
			     bool accessed_dirty);
bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
				u64 fault_address, char *insn, int insn_len,
				bool need_unprotect);

static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
{
	if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
		return kvm->arch.n_max_mmu_pages -
			kvm->arch.n_used_mmu_pages;

	return 0;
}

static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
{
	if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
		return 0;

	return kvm_mmu_load(vcpu);
}

/*
 * Currently, we have two sorts of write-protection, a) the first one
 * write-protects guest page to sync the guest modification, b) another one is
 * used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences
 * between these two sorts are:
 * 1) the first case clears SPTE_MMU_WRITEABLE bit.
 * 2) the first case requires flushing tlb immediately avoiding corrupting
 *    shadow page table between all vcpus so it should be in the protection of
 *    mmu-lock. And the another case does not need to flush tlb until returning
 *    the dirty bitmap to userspace since it only write-protects the page
 *    logged in the bitmap, that means the page in the dirty bitmap is not
 *    missed, so it can flush tlb out of mmu-lock.
 *
 * So, there is the problem: the first case can meet the corrupted tlb caused
 * by another case which write-protects pages but without flush tlb
 * immediately. In order to making the first case be aware this problem we let
 * it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit
 * is set, it works since another case never touches SPTE_MMU_WRITEABLE bit.
 *
 * Anyway, whenever a spte is updated (only permission and status bits are
 * changed) we need to check whether the spte with SPTE_MMU_WRITEABLE becomes
 * readonly, if that happens, we need to flush tlb. Fortunately,
 * mmu_spte_update() has already handled it perfectly.
 *
 * The rules to use SPTE_MMU_WRITEABLE and PT_WRITABLE_MASK:
 * - if we want to see if it has writable tlb entry or if the spte can be
 *   writable on the mmu mapping, check SPTE_MMU_WRITEABLE, this is the most
 *   case, otherwise
 * - if we fix page fault on the spte or do write-protection by dirty logging,
 *   check PT_WRITABLE_MASK.
 *
 * TODO: introduce APIs to split these two cases.
 */
static inline int is_writable_pte(unsigned long pte)
{
	return pte & PT_WRITABLE_MASK;
}

static inline bool is_write_protection(struct kvm_vcpu *vcpu)
{
	return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
}

/*
 * Check if a given access (described through the I/D, W/R and U/S bits of a
 * page fault error code pfec) causes a permission fault with the given PTE
 * access rights (in ACC_* format).
 *
 * Return zero if the access does not fault; return the page fault error code
 * if the access faults.
 */
static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
				  unsigned pte_access, unsigned pte_pkey,
				  unsigned pfec)
{
	int cpl = kvm_x86_ops->get_cpl(vcpu);
	unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);

	/*
	 * If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1.
	 *
	 * If CPL = 3, SMAP applies to all supervisor-mode data accesses
	 * (these are implicit supervisor accesses) regardless of the value
	 * of EFLAGS.AC.
	 *
	 * This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving
	 * the result in X86_EFLAGS_AC. We then insert it in place of
	 * the PFERR_RSVD_MASK bit; this bit will always be zero in pfec,
	 * but it will be one in index if SMAP checks are being overridden.
	 * It is important to keep this branchless.
	 */
	unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC);
	int index = (pfec >> 1) +
		    (smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1));
	bool fault = (mmu->permissions[index] >> pte_access) & 1;
	u32 errcode = PFERR_PRESENT_MASK;

	WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
	if (unlikely(mmu->pkru_mask)) {
		u32 pkru_bits, offset;

		/*
		* PKRU defines 32 bits, there are 16 domains and 2
		* attribute bits per domain in pkru.  pte_pkey is the
		* index of the protection domain, so pte_pkey * 2 is
		* is the index of the first bit for the domain.
		*/
		pkru_bits = (kvm_read_pkru(vcpu) >> (pte_pkey * 2)) & 3;

		/* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
		offset = (pfec & ~1) +
			((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));

		pkru_bits &= mmu->pkru_mask >> offset;
		errcode |= -pkru_bits & PFERR_PK_MASK;
		fault |= (pkru_bits != 0);
	}

	return -(u32)fault & errcode;
}

void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm);
void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);

void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
				    struct kvm_memory_slot *slot, u64 gfn);
int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
#endif
Commit	Line	Data
1d737c8a ZX	1	#ifndef __KVM_X86_MMU_H
	2	#define __KVM_X86_MMU_H
	3
edf88417	4	#include <linux/kvm_host.h>
fc78f519	5	#include "kvm_cache_regs.h"
1d737c8a	6
8c6d6adc SY	7	#define PT64_PT_BITS 9
	8	#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
	9	#define PT32_PT_BITS 10
	10	#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
	11
	12	#define PT_WRITABLE_SHIFT 1
be94f6b7	13	#define PT_USER_SHIFT 2
8c6d6adc SY	14
	15	#define PT_PRESENT_MASK (1ULL << 0)
	16	#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
be94f6b7	17	#define PT_USER_MASK (1ULL << PT_USER_SHIFT)
8c6d6adc SY	18	#define PT_PWT_MASK (1ULL << 3)
8c6d6adc SY	19	#define PT_PCD_MASK (1ULL << 4)
1b7fcd32 AK	20	#define PT_ACCESSED_SHIFT 5
1b7fcd32 AK	21	#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
8ea667f2 AK	22	#define PT_DIRTY_SHIFT 6
8ea667f2 AK	23	#define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
6fd01b71 AK	24	#define PT_PAGE_SIZE_SHIFT 7
6fd01b71 AK	25	#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
8c6d6adc SY	26	#define PT_PAT_MASK (1ULL << 7)
	27	#define PT_GLOBAL_MASK (1ULL << 8)
	28	#define PT64_NX_SHIFT 63
	29	#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
	30
	31	#define PT_PAT_SHIFT 7
	32	#define PT_DIR_PAT_SHIFT 12
	33	#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
	34
	35	#define PT32_DIR_PSE36_SIZE 4
	36	#define PT32_DIR_PSE36_SHIFT 13
	37	#define PT32_DIR_PSE36_MASK \
	38	(((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
	39
855feb67	40	#define PT64_ROOT_5LEVEL 5
2a7266a8	41	#define PT64_ROOT_4LEVEL 4
8c6d6adc SY	42	#define PT32_ROOT_LEVEL 2
	43	#define PT32E_ROOT_LEVEL 3
	44
c9c54174 SY	45	#define PT_PDPE_LEVEL 3
	46	#define PT_DIRECTORY_LEVEL 2
	47	#define PT_PAGE_TABLE_LEVEL 1
8a3d08f1	48	#define PT_MAX_HUGEPAGE_LEVEL (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES - 1)
c9c54174	49
d1431483 TC	50	static inline u64 rsvd_bits(int s, int e)
d1431483 TC	51	{
d1cd3ce9 YZ	52	if (e < s)
	53	return 0;
	54
d1431483 TC	55	return ((1ULL << (e - s + 1)) - 1) << s;
	56	}
	57
dcdca5fe	58	void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value);
b37fbea6	59
c258b62b XG	60	void
	61	reset_shadow_zero_bits_mask(struct kvm_vcpu vcpu, struct kvm_mmu context);
	62
ad896af0	63	void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);
ae1e2d10 PB	64	void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
ae1e2d10 PB	65	bool accessed_dirty);
9bc1f09f	66	bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
1261bfa3 WL	67	int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
	68	u64 fault_address, char *insn, int insn_len,
	69	bool need_unprotect);
94d8b056	70
e0df7b9f DH	71	static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
e0df7b9f DH	72	{
5d218814 MT	73	if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
	74	return kvm->arch.n_max_mmu_pages -
	75	kvm->arch.n_used_mmu_pages;
	76
	77	return 0;
e0df7b9f DH	78	}
e0df7b9f DH	79
1d737c8a ZX	80	static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
	81	{
	82	if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
	83	return 0;
	84
	85	return kvm_mmu_load(vcpu);
	86	}
	87
198c74f4 XG	88	/*
	89	* Currently, we have two sorts of write-protection, a) the first one
	90	* write-protects guest page to sync the guest modification, b) another one is
	91	* used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences
	92	* between these two sorts are:
	93	* 1) the first case clears SPTE_MMU_WRITEABLE bit.
	94	* 2) the first case requires flushing tlb immediately avoiding corrupting
	95	* shadow page table between all vcpus so it should be in the protection of
	96	* mmu-lock. And the another case does not need to flush tlb until returning
	97	* the dirty bitmap to userspace since it only write-protects the page
	98	* logged in the bitmap, that means the page in the dirty bitmap is not
	99	* missed, so it can flush tlb out of mmu-lock.
	100	*
	101	* So, there is the problem: the first case can meet the corrupted tlb caused
	102	* by another case which write-protects pages but without flush tlb
	103	* immediately. In order to making the first case be aware this problem we let
	104	* it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit
	105	* is set, it works since another case never touches SPTE_MMU_WRITEABLE bit.
	106	*
	107	* Anyway, whenever a spte is updated (only permission and status bits are
	108	* changed) we need to check whether the spte with SPTE_MMU_WRITEABLE becomes
	109	* readonly, if that happens, we need to flush tlb. Fortunately,
	110	* mmu_spte_update() has already handled it perfectly.
	111	*
	112	* The rules to use SPTE_MMU_WRITEABLE and PT_WRITABLE_MASK:
	113	* - if we want to see if it has writable tlb entry or if the spte can be
	114	* writable on the mmu mapping, check SPTE_MMU_WRITEABLE, this is the most
	115	* case, otherwise
	116	* - if we fix page fault on the spte or do write-protection by dirty logging,
	117	* check PT_WRITABLE_MASK.
	118	*
	119	* TODO: introduce APIs to split these two cases.
	120	*/
bebb106a XG	121	static inline int is_writable_pte(unsigned long pte)
	122	{
	123	return pte & PT_WRITABLE_MASK;
	124	}
	125
	126	static inline bool is_write_protection(struct kvm_vcpu *vcpu)
	127	{
	128	return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
	129	}
	130
97d64b78	131	/*
f13577e8 PB	132	* Check if a given access (described through the I/D, W/R and U/S bits of a
	133	* page fault error code pfec) causes a permission fault with the given PTE
	134	* access rights (in ACC_* format).
	135	*
	136	* Return zero if the access does not fault; return the page fault error code
	137	* if the access faults.
97d64b78	138	*/
f13577e8	139	static inline u8 permission_fault(struct kvm_vcpu vcpu, struct kvm_mmu mmu,
be94f6b7 HH	140	unsigned pte_access, unsigned pte_pkey,
be94f6b7 HH	141	unsigned pfec)
bebb106a	142	{
97ec8c06 FW	143	int cpl = kvm_x86_ops->get_cpl(vcpu);
	144	unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
	145
	146	/*
	147	* If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1.
	148	*
	149	* If CPL = 3, SMAP applies to all supervisor-mode data accesses
	150	* (these are implicit supervisor accesses) regardless of the value
	151	* of EFLAGS.AC.
	152	*
	153	* This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving
	154	* the result in X86_EFLAGS_AC. We then insert it in place of
	155	* the PFERR_RSVD_MASK bit; this bit will always be zero in pfec,
	156	* but it will be one in index if SMAP checks are being overridden.
	157	* It is important to keep this branchless.
	158	*/
	159	unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC);
	160	int index = (pfec >> 1) +
	161	(smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1));
be94f6b7	162	bool fault = (mmu->permissions[index] >> pte_access) & 1;
7a98205d	163	u32 errcode = PFERR_PRESENT_MASK;
97ec8c06	164
be94f6b7	165	WARN_ON(pfec & (PFERR_PK_MASK \| PFERR_RSVD_MASK));
be94f6b7 HH	166	if (unlikely(mmu->pkru_mask)) {
	167	u32 pkru_bits, offset;
	168
	169	/*
	170	* PKRU defines 32 bits, there are 16 domains and 2
	171	* attribute bits per domain in pkru. pte_pkey is the
	172	* index of the protection domain, so pte_pkey * 2 is
	173	* is the index of the first bit for the domain.
	174	*/
	175	pkru_bits = (kvm_read_pkru(vcpu) >> (pte_pkey * 2)) & 3;
	176
	177	/* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
7a98205d	178	offset = (pfec & ~1) +
be94f6b7 HH	179	((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
	180
	181	pkru_bits &= mmu->pkru_mask >> offset;
7a98205d	182	errcode \|= -pkru_bits & PFERR_PK_MASK;
be94f6b7 HH	183	fault \|= (pkru_bits != 0);
	184	}
	185
7a98205d	186	return -(u32)fault & errcode;
bebb106a	187	}
97d64b78	188
5304b8d3	189	void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm);
efdfe536	190	void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
547ffaed XG	191
	192	void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
	193	void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
aeecee2e XG	194	bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
aeecee2e XG	195	struct kvm_memory_slot *slot, u64 gfn);
bab4165e	196	int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
1d737c8a	197	#endif