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ff53604b XG |
1 | /* |
2 | * vMTRR implementation | |
3 | * | |
4 | * Copyright (C) 2006 Qumranet, Inc. | |
5 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. | |
6 | * Copyright(C) 2015 Intel Corporation. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Marcelo Tosatti <mtosatti@redhat.com> | |
12 | * Paolo Bonzini <pbonzini@redhat.com> | |
13 | * Xiao Guangrong <guangrong.xiao@linux.intel.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | */ | |
18 | ||
19 | #include <linux/kvm_host.h> | |
20 | #include <asm/mtrr.h> | |
21 | ||
22 | #include "cpuid.h" | |
23 | #include "mmu.h" | |
24 | ||
10fac2dc XG |
25 | #define IA32_MTRR_DEF_TYPE_E (1ULL << 11) |
26 | #define IA32_MTRR_DEF_TYPE_FE (1ULL << 10) | |
27 | #define IA32_MTRR_DEF_TYPE_TYPE_MASK (0xff) | |
28 | ||
ff53604b XG |
29 | static bool msr_mtrr_valid(unsigned msr) |
30 | { | |
31 | switch (msr) { | |
32 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
33 | case MSR_MTRRfix64K_00000: | |
34 | case MSR_MTRRfix16K_80000: | |
35 | case MSR_MTRRfix16K_A0000: | |
36 | case MSR_MTRRfix4K_C0000: | |
37 | case MSR_MTRRfix4K_C8000: | |
38 | case MSR_MTRRfix4K_D0000: | |
39 | case MSR_MTRRfix4K_D8000: | |
40 | case MSR_MTRRfix4K_E0000: | |
41 | case MSR_MTRRfix4K_E8000: | |
42 | case MSR_MTRRfix4K_F0000: | |
43 | case MSR_MTRRfix4K_F8000: | |
44 | case MSR_MTRRdefType: | |
45 | case MSR_IA32_CR_PAT: | |
46 | return true; | |
ff53604b XG |
47 | } |
48 | return false; | |
49 | } | |
50 | ||
ff53604b XG |
51 | static bool valid_mtrr_type(unsigned t) |
52 | { | |
53 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
54 | } | |
55 | ||
56 | bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
57 | { | |
58 | int i; | |
59 | u64 mask; | |
60 | ||
61 | if (!msr_mtrr_valid(msr)) | |
62 | return false; | |
63 | ||
64 | if (msr == MSR_IA32_CR_PAT) { | |
30460222 | 65 | return kvm_pat_valid(data); |
ff53604b XG |
66 | } else if (msr == MSR_MTRRdefType) { |
67 | if (data & ~0xcff) | |
68 | return false; | |
69 | return valid_mtrr_type(data & 0xff); | |
70 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
71 | for (i = 0; i < 8 ; i++) | |
72 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
73 | return false; | |
74 | return true; | |
75 | } | |
76 | ||
77 | /* variable MTRRs */ | |
78 | WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); | |
79 | ||
80 | mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
81 | if ((msr & 1) == 0) { | |
82 | /* MTRR base */ | |
83 | if (!valid_mtrr_type(data & 0xff)) | |
84 | return false; | |
85 | mask |= 0xf00; | |
86 | } else | |
87 | /* MTRR mask */ | |
88 | mask |= 0x7ff; | |
89 | if (data & mask) { | |
90 | kvm_inject_gp(vcpu, 0); | |
91 | return false; | |
92 | } | |
93 | ||
94 | return true; | |
95 | } | |
96 | EXPORT_SYMBOL_GPL(kvm_mtrr_valid); | |
97 | ||
10fac2dc XG |
98 | static bool mtrr_is_enabled(struct kvm_mtrr *mtrr_state) |
99 | { | |
100 | return !!(mtrr_state->deftype & IA32_MTRR_DEF_TYPE_E); | |
101 | } | |
102 | ||
103 | static bool fixed_mtrr_is_enabled(struct kvm_mtrr *mtrr_state) | |
104 | { | |
105 | return !!(mtrr_state->deftype & IA32_MTRR_DEF_TYPE_FE); | |
106 | } | |
107 | ||
108 | static u8 mtrr_default_type(struct kvm_mtrr *mtrr_state) | |
109 | { | |
110 | return mtrr_state->deftype & IA32_MTRR_DEF_TYPE_TYPE_MASK; | |
111 | } | |
112 | ||
e24dea2a | 113 | static u8 mtrr_disabled_type(struct kvm_vcpu *vcpu) |
10dc331f XG |
114 | { |
115 | /* | |
116 | * Intel SDM 11.11.2.2: all MTRRs are disabled when | |
117 | * IA32_MTRR_DEF_TYPE.E bit is cleared, and the UC | |
118 | * memory type is applied to all of physical memory. | |
e24dea2a PB |
119 | * |
120 | * However, virtual machines can be run with CPUID such that | |
121 | * there are no MTRRs. In that case, the firmware will never | |
122 | * enable MTRRs and it is obviously undesirable to run the | |
123 | * guest entirely with UC memory and we use WB. | |
10dc331f | 124 | */ |
d6321d49 | 125 | if (guest_cpuid_has(vcpu, X86_FEATURE_MTRR)) |
e24dea2a PB |
126 | return MTRR_TYPE_UNCACHABLE; |
127 | else | |
128 | return MTRR_TYPE_WRBACK; | |
10dc331f XG |
129 | } |
130 | ||
de9aef5e XG |
131 | /* |
132 | * Three terms are used in the following code: | |
133 | * - segment, it indicates the address segments covered by fixed MTRRs. | |
134 | * - unit, it corresponds to the MSR entry in the segment. | |
135 | * - range, a range is covered in one memory cache type. | |
136 | */ | |
137 | struct fixed_mtrr_segment { | |
138 | u64 start; | |
139 | u64 end; | |
140 | ||
141 | int range_shift; | |
142 | ||
143 | /* the start position in kvm_mtrr.fixed_ranges[]. */ | |
144 | int range_start; | |
145 | }; | |
146 | ||
147 | static struct fixed_mtrr_segment fixed_seg_table[] = { | |
148 | /* MSR_MTRRfix64K_00000, 1 unit. 64K fixed mtrr. */ | |
149 | { | |
150 | .start = 0x0, | |
151 | .end = 0x80000, | |
152 | .range_shift = 16, /* 64K */ | |
153 | .range_start = 0, | |
154 | }, | |
155 | ||
156 | /* | |
157 | * MSR_MTRRfix16K_80000 ... MSR_MTRRfix16K_A0000, 2 units, | |
158 | * 16K fixed mtrr. | |
159 | */ | |
160 | { | |
161 | .start = 0x80000, | |
162 | .end = 0xc0000, | |
163 | .range_shift = 14, /* 16K */ | |
164 | .range_start = 8, | |
165 | }, | |
166 | ||
167 | /* | |
168 | * MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000, 8 units, | |
169 | * 4K fixed mtrr. | |
170 | */ | |
171 | { | |
172 | .start = 0xc0000, | |
173 | .end = 0x100000, | |
174 | .range_shift = 12, /* 12K */ | |
175 | .range_start = 24, | |
176 | } | |
177 | }; | |
178 | ||
179 | /* | |
180 | * The size of unit is covered in one MSR, one MSR entry contains | |
181 | * 8 ranges so that unit size is always 8 * 2^range_shift. | |
182 | */ | |
183 | static u64 fixed_mtrr_seg_unit_size(int seg) | |
184 | { | |
185 | return 8 << fixed_seg_table[seg].range_shift; | |
186 | } | |
187 | ||
188 | static bool fixed_msr_to_seg_unit(u32 msr, int *seg, int *unit) | |
189 | { | |
190 | switch (msr) { | |
191 | case MSR_MTRRfix64K_00000: | |
192 | *seg = 0; | |
193 | *unit = 0; | |
194 | break; | |
195 | case MSR_MTRRfix16K_80000 ... MSR_MTRRfix16K_A0000: | |
196 | *seg = 1; | |
16718c86 MP |
197 | *unit = array_index_nospec( |
198 | msr - MSR_MTRRfix16K_80000, | |
199 | MSR_MTRRfix16K_A0000 - MSR_MTRRfix16K_80000 + 1); | |
de9aef5e XG |
200 | break; |
201 | case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000: | |
202 | *seg = 2; | |
16718c86 MP |
203 | *unit = array_index_nospec( |
204 | msr - MSR_MTRRfix4K_C0000, | |
205 | MSR_MTRRfix4K_F8000 - MSR_MTRRfix4K_C0000 + 1); | |
de9aef5e XG |
206 | break; |
207 | default: | |
208 | return false; | |
209 | } | |
210 | ||
211 | return true; | |
212 | } | |
213 | ||
214 | static void fixed_mtrr_seg_unit_range(int seg, int unit, u64 *start, u64 *end) | |
215 | { | |
216 | struct fixed_mtrr_segment *mtrr_seg = &fixed_seg_table[seg]; | |
217 | u64 unit_size = fixed_mtrr_seg_unit_size(seg); | |
218 | ||
219 | *start = mtrr_seg->start + unit * unit_size; | |
220 | *end = *start + unit_size; | |
221 | WARN_ON(*end > mtrr_seg->end); | |
222 | } | |
223 | ||
224 | static int fixed_mtrr_seg_unit_range_index(int seg, int unit) | |
225 | { | |
226 | struct fixed_mtrr_segment *mtrr_seg = &fixed_seg_table[seg]; | |
227 | ||
228 | WARN_ON(mtrr_seg->start + unit * fixed_mtrr_seg_unit_size(seg) | |
229 | > mtrr_seg->end); | |
230 | ||
231 | /* each unit has 8 ranges. */ | |
232 | return mtrr_seg->range_start + 8 * unit; | |
233 | } | |
234 | ||
f571c097 XG |
235 | static int fixed_mtrr_seg_end_range_index(int seg) |
236 | { | |
237 | struct fixed_mtrr_segment *mtrr_seg = &fixed_seg_table[seg]; | |
238 | int n; | |
239 | ||
240 | n = (mtrr_seg->end - mtrr_seg->start) >> mtrr_seg->range_shift; | |
241 | return mtrr_seg->range_start + n - 1; | |
242 | } | |
243 | ||
de9aef5e XG |
244 | static bool fixed_msr_to_range(u32 msr, u64 *start, u64 *end) |
245 | { | |
246 | int seg, unit; | |
247 | ||
248 | if (!fixed_msr_to_seg_unit(msr, &seg, &unit)) | |
249 | return false; | |
250 | ||
251 | fixed_mtrr_seg_unit_range(seg, unit, start, end); | |
252 | return true; | |
253 | } | |
254 | ||
255 | static int fixed_msr_to_range_index(u32 msr) | |
256 | { | |
257 | int seg, unit; | |
258 | ||
259 | if (!fixed_msr_to_seg_unit(msr, &seg, &unit)) | |
260 | return -1; | |
261 | ||
262 | return fixed_mtrr_seg_unit_range_index(seg, unit); | |
263 | } | |
264 | ||
f7bfb57b XG |
265 | static int fixed_mtrr_addr_to_seg(u64 addr) |
266 | { | |
267 | struct fixed_mtrr_segment *mtrr_seg; | |
268 | int seg, seg_num = ARRAY_SIZE(fixed_seg_table); | |
269 | ||
270 | for (seg = 0; seg < seg_num; seg++) { | |
271 | mtrr_seg = &fixed_seg_table[seg]; | |
a7f2d786 | 272 | if (mtrr_seg->start <= addr && addr < mtrr_seg->end) |
f7bfb57b XG |
273 | return seg; |
274 | } | |
275 | ||
276 | return -1; | |
277 | } | |
278 | ||
279 | static int fixed_mtrr_addr_seg_to_range_index(u64 addr, int seg) | |
280 | { | |
281 | struct fixed_mtrr_segment *mtrr_seg; | |
282 | int index; | |
283 | ||
284 | mtrr_seg = &fixed_seg_table[seg]; | |
285 | index = mtrr_seg->range_start; | |
286 | index += (addr - mtrr_seg->start) >> mtrr_seg->range_shift; | |
287 | return index; | |
288 | } | |
289 | ||
f571c097 XG |
290 | static u64 fixed_mtrr_range_end_addr(int seg, int index) |
291 | { | |
292 | struct fixed_mtrr_segment *mtrr_seg = &fixed_seg_table[seg]; | |
293 | int pos = index - mtrr_seg->range_start; | |
294 | ||
295 | return mtrr_seg->start + ((pos + 1) << mtrr_seg->range_shift); | |
296 | } | |
297 | ||
a13842dc XG |
298 | static void var_mtrr_range(struct kvm_mtrr_range *range, u64 *start, u64 *end) |
299 | { | |
300 | u64 mask; | |
301 | ||
302 | *start = range->base & PAGE_MASK; | |
303 | ||
304 | mask = range->mask & PAGE_MASK; | |
a13842dc XG |
305 | |
306 | /* This cannot overflow because writing to the reserved bits of | |
307 | * variable MTRRs causes a #GP. | |
308 | */ | |
309 | *end = (*start | ~mask) + 1; | |
310 | } | |
311 | ||
ff53604b XG |
312 | static void update_mtrr(struct kvm_vcpu *vcpu, u32 msr) |
313 | { | |
70109e7d | 314 | struct kvm_mtrr *mtrr_state = &vcpu->arch.mtrr_state; |
a13842dc | 315 | gfn_t start, end; |
ff53604b | 316 | int index; |
ff53604b XG |
317 | |
318 | if (msr == MSR_IA32_CR_PAT || !tdp_enabled || | |
319 | !kvm_arch_has_noncoherent_dma(vcpu->kvm)) | |
320 | return; | |
321 | ||
10fac2dc | 322 | if (!mtrr_is_enabled(mtrr_state) && msr != MSR_MTRRdefType) |
ff53604b XG |
323 | return; |
324 | ||
de9aef5e XG |
325 | /* fixed MTRRs. */ |
326 | if (fixed_msr_to_range(msr, &start, &end)) { | |
327 | if (!fixed_mtrr_is_enabled(mtrr_state)) | |
328 | return; | |
329 | } else if (msr == MSR_MTRRdefType) { | |
ff53604b XG |
330 | start = 0x0; |
331 | end = ~0ULL; | |
de9aef5e | 332 | } else { |
ff53604b | 333 | /* variable range MTRRs. */ |
ff53604b | 334 | index = (msr - 0x200) / 2; |
a13842dc | 335 | var_mtrr_range(&mtrr_state->var_ranges[index], &start, &end); |
ff53604b XG |
336 | } |
337 | ||
ff53604b XG |
338 | kvm_zap_gfn_range(vcpu->kvm, gpa_to_gfn(start), gpa_to_gfn(end)); |
339 | } | |
340 | ||
19efffa2 XG |
341 | static bool var_mtrr_range_is_valid(struct kvm_mtrr_range *range) |
342 | { | |
343 | return (range->mask & (1 << 11)) != 0; | |
344 | } | |
345 | ||
346 | static void set_var_mtrr_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
347 | { | |
348 | struct kvm_mtrr *mtrr_state = &vcpu->arch.mtrr_state; | |
349 | struct kvm_mtrr_range *tmp, *cur; | |
350 | int index, is_mtrr_mask; | |
351 | ||
352 | index = (msr - 0x200) / 2; | |
353 | is_mtrr_mask = msr - 0x200 - 2 * index; | |
354 | cur = &mtrr_state->var_ranges[index]; | |
355 | ||
356 | /* remove the entry if it's in the list. */ | |
357 | if (var_mtrr_range_is_valid(cur)) | |
358 | list_del(&mtrr_state->var_ranges[index].node); | |
359 | ||
fa7c4ebd PB |
360 | /* Extend the mask with all 1 bits to the left, since those |
361 | * bits must implicitly be 0. The bits are then cleared | |
362 | * when reading them. | |
363 | */ | |
19efffa2 XG |
364 | if (!is_mtrr_mask) |
365 | cur->base = data; | |
366 | else | |
fa7c4ebd | 367 | cur->mask = data | (-1LL << cpuid_maxphyaddr(vcpu)); |
19efffa2 XG |
368 | |
369 | /* add it to the list if it's enabled. */ | |
370 | if (var_mtrr_range_is_valid(cur)) { | |
371 | list_for_each_entry(tmp, &mtrr_state->head, node) | |
372 | if (cur->base >= tmp->base) | |
373 | break; | |
374 | list_add_tail(&cur->node, &tmp->node); | |
375 | } | |
376 | } | |
377 | ||
ff53604b XG |
378 | int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
379 | { | |
de9aef5e | 380 | int index; |
ff53604b XG |
381 | |
382 | if (!kvm_mtrr_valid(vcpu, msr, data)) | |
383 | return 1; | |
384 | ||
de9aef5e XG |
385 | index = fixed_msr_to_range_index(msr); |
386 | if (index >= 0) | |
387 | *(u64 *)&vcpu->arch.mtrr_state.fixed_ranges[index] = data; | |
388 | else if (msr == MSR_MTRRdefType) | |
10fac2dc | 389 | vcpu->arch.mtrr_state.deftype = data; |
ff53604b XG |
390 | else if (msr == MSR_IA32_CR_PAT) |
391 | vcpu->arch.pat = data; | |
19efffa2 XG |
392 | else |
393 | set_var_mtrr_msr(vcpu, msr, data); | |
ff53604b XG |
394 | |
395 | update_mtrr(vcpu, msr); | |
396 | return 0; | |
397 | } | |
398 | ||
399 | int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
400 | { | |
de9aef5e | 401 | int index; |
ff53604b | 402 | |
eb839917 XG |
403 | /* MSR_MTRRcap is a readonly MSR. */ |
404 | if (msr == MSR_MTRRcap) { | |
405 | /* | |
406 | * SMRR = 0 | |
407 | * WC = 1 | |
408 | * FIX = 1 | |
409 | * VCNT = KVM_NR_VAR_MTRR | |
410 | */ | |
411 | *pdata = 0x500 | KVM_NR_VAR_MTRR; | |
412 | return 0; | |
413 | } | |
414 | ||
ff53604b XG |
415 | if (!msr_mtrr_valid(msr)) |
416 | return 1; | |
417 | ||
de9aef5e XG |
418 | index = fixed_msr_to_range_index(msr); |
419 | if (index >= 0) | |
420 | *pdata = *(u64 *)&vcpu->arch.mtrr_state.fixed_ranges[index]; | |
421 | else if (msr == MSR_MTRRdefType) | |
10fac2dc | 422 | *pdata = vcpu->arch.mtrr_state.deftype; |
ff53604b XG |
423 | else if (msr == MSR_IA32_CR_PAT) |
424 | *pdata = vcpu->arch.pat; | |
425 | else { /* Variable MTRRs */ | |
de9aef5e | 426 | int is_mtrr_mask; |
ff53604b | 427 | |
de9aef5e XG |
428 | index = (msr - 0x200) / 2; |
429 | is_mtrr_mask = msr - 0x200 - 2 * index; | |
ff53604b | 430 | if (!is_mtrr_mask) |
de9aef5e | 431 | *pdata = vcpu->arch.mtrr_state.var_ranges[index].base; |
ff53604b | 432 | else |
de9aef5e | 433 | *pdata = vcpu->arch.mtrr_state.var_ranges[index].mask; |
fa7c4ebd PB |
434 | |
435 | *pdata &= (1ULL << cpuid_maxphyaddr(vcpu)) - 1; | |
ff53604b XG |
436 | } |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
19efffa2 XG |
441 | void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu) |
442 | { | |
443 | INIT_LIST_HEAD(&vcpu->arch.mtrr_state.head); | |
444 | } | |
445 | ||
f571c097 XG |
446 | struct mtrr_iter { |
447 | /* input fields. */ | |
448 | struct kvm_mtrr *mtrr_state; | |
449 | u64 start; | |
450 | u64 end; | |
451 | ||
452 | /* output fields. */ | |
453 | int mem_type; | |
10dc331f XG |
454 | /* mtrr is completely disabled? */ |
455 | bool mtrr_disabled; | |
f571c097 XG |
456 | /* [start, end) is not fully covered in MTRRs? */ |
457 | bool partial_map; | |
458 | ||
459 | /* private fields. */ | |
460 | union { | |
461 | /* used for fixed MTRRs. */ | |
462 | struct { | |
463 | int index; | |
464 | int seg; | |
465 | }; | |
466 | ||
467 | /* used for var MTRRs. */ | |
468 | struct { | |
469 | struct kvm_mtrr_range *range; | |
470 | /* max address has been covered in var MTRRs. */ | |
471 | u64 start_max; | |
472 | }; | |
473 | }; | |
474 | ||
475 | bool fixed; | |
476 | }; | |
477 | ||
478 | static bool mtrr_lookup_fixed_start(struct mtrr_iter *iter) | |
479 | { | |
480 | int seg, index; | |
481 | ||
482 | if (!fixed_mtrr_is_enabled(iter->mtrr_state)) | |
483 | return false; | |
484 | ||
485 | seg = fixed_mtrr_addr_to_seg(iter->start); | |
486 | if (seg < 0) | |
487 | return false; | |
488 | ||
489 | iter->fixed = true; | |
490 | index = fixed_mtrr_addr_seg_to_range_index(iter->start, seg); | |
491 | iter->index = index; | |
492 | iter->seg = seg; | |
493 | return true; | |
494 | } | |
495 | ||
496 | static bool match_var_range(struct mtrr_iter *iter, | |
497 | struct kvm_mtrr_range *range) | |
498 | { | |
499 | u64 start, end; | |
500 | ||
501 | var_mtrr_range(range, &start, &end); | |
502 | if (!(start >= iter->end || end <= iter->start)) { | |
503 | iter->range = range; | |
504 | ||
505 | /* | |
506 | * the function is called when we do kvm_mtrr.head walking. | |
507 | * Range has the minimum base address which interleaves | |
508 | * [looker->start_max, looker->end). | |
509 | */ | |
510 | iter->partial_map |= iter->start_max < start; | |
511 | ||
512 | /* update the max address has been covered. */ | |
513 | iter->start_max = max(iter->start_max, end); | |
514 | return true; | |
515 | } | |
516 | ||
517 | return false; | |
518 | } | |
519 | ||
520 | static void __mtrr_lookup_var_next(struct mtrr_iter *iter) | |
521 | { | |
522 | struct kvm_mtrr *mtrr_state = iter->mtrr_state; | |
523 | ||
524 | list_for_each_entry_continue(iter->range, &mtrr_state->head, node) | |
525 | if (match_var_range(iter, iter->range)) | |
526 | return; | |
527 | ||
528 | iter->range = NULL; | |
529 | iter->partial_map |= iter->start_max < iter->end; | |
530 | } | |
531 | ||
532 | static void mtrr_lookup_var_start(struct mtrr_iter *iter) | |
533 | { | |
534 | struct kvm_mtrr *mtrr_state = iter->mtrr_state; | |
535 | ||
536 | iter->fixed = false; | |
537 | iter->start_max = iter->start; | |
30b072ce | 538 | iter->range = NULL; |
f571c097 XG |
539 | iter->range = list_prepare_entry(iter->range, &mtrr_state->head, node); |
540 | ||
541 | __mtrr_lookup_var_next(iter); | |
542 | } | |
543 | ||
544 | static void mtrr_lookup_fixed_next(struct mtrr_iter *iter) | |
545 | { | |
546 | /* terminate the lookup. */ | |
547 | if (fixed_mtrr_range_end_addr(iter->seg, iter->index) >= iter->end) { | |
548 | iter->fixed = false; | |
549 | iter->range = NULL; | |
550 | return; | |
551 | } | |
552 | ||
553 | iter->index++; | |
554 | ||
555 | /* have looked up for all fixed MTRRs. */ | |
556 | if (iter->index >= ARRAY_SIZE(iter->mtrr_state->fixed_ranges)) | |
557 | return mtrr_lookup_var_start(iter); | |
558 | ||
559 | /* switch to next segment. */ | |
560 | if (iter->index > fixed_mtrr_seg_end_range_index(iter->seg)) | |
561 | iter->seg++; | |
562 | } | |
563 | ||
564 | static void mtrr_lookup_var_next(struct mtrr_iter *iter) | |
565 | { | |
566 | __mtrr_lookup_var_next(iter); | |
567 | } | |
568 | ||
569 | static void mtrr_lookup_start(struct mtrr_iter *iter) | |
570 | { | |
571 | if (!mtrr_is_enabled(iter->mtrr_state)) { | |
10dc331f | 572 | iter->mtrr_disabled = true; |
f571c097 XG |
573 | return; |
574 | } | |
575 | ||
576 | if (!mtrr_lookup_fixed_start(iter)) | |
577 | mtrr_lookup_var_start(iter); | |
578 | } | |
579 | ||
580 | static void mtrr_lookup_init(struct mtrr_iter *iter, | |
581 | struct kvm_mtrr *mtrr_state, u64 start, u64 end) | |
582 | { | |
583 | iter->mtrr_state = mtrr_state; | |
584 | iter->start = start; | |
585 | iter->end = end; | |
10dc331f | 586 | iter->mtrr_disabled = false; |
f571c097 XG |
587 | iter->partial_map = false; |
588 | iter->fixed = false; | |
589 | iter->range = NULL; | |
590 | ||
591 | mtrr_lookup_start(iter); | |
592 | } | |
593 | ||
594 | static bool mtrr_lookup_okay(struct mtrr_iter *iter) | |
595 | { | |
596 | if (iter->fixed) { | |
597 | iter->mem_type = iter->mtrr_state->fixed_ranges[iter->index]; | |
598 | return true; | |
599 | } | |
600 | ||
601 | if (iter->range) { | |
602 | iter->mem_type = iter->range->base & 0xff; | |
603 | return true; | |
604 | } | |
605 | ||
606 | return false; | |
607 | } | |
608 | ||
609 | static void mtrr_lookup_next(struct mtrr_iter *iter) | |
610 | { | |
611 | if (iter->fixed) | |
612 | mtrr_lookup_fixed_next(iter); | |
613 | else | |
614 | mtrr_lookup_var_next(iter); | |
615 | } | |
616 | ||
617 | #define mtrr_for_each_mem_type(_iter_, _mtrr_, _gpa_start_, _gpa_end_) \ | |
618 | for (mtrr_lookup_init(_iter_, _mtrr_, _gpa_start_, _gpa_end_); \ | |
619 | mtrr_lookup_okay(_iter_); mtrr_lookup_next(_iter_)) | |
620 | ||
3f3f78b6 | 621 | u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
ff53604b | 622 | { |
3f3f78b6 | 623 | struct kvm_mtrr *mtrr_state = &vcpu->arch.mtrr_state; |
fa612137 XG |
624 | struct mtrr_iter iter; |
625 | u64 start, end; | |
626 | int type = -1; | |
3f3f78b6 XG |
627 | const int wt_wb_mask = (1 << MTRR_TYPE_WRBACK) |
628 | | (1 << MTRR_TYPE_WRTHROUGH); | |
629 | ||
630 | start = gfn_to_gpa(gfn); | |
fa612137 | 631 | end = start + PAGE_SIZE; |
ff53604b | 632 | |
fa612137 XG |
633 | mtrr_for_each_mem_type(&iter, mtrr_state, start, end) { |
634 | int curr_type = iter.mem_type; | |
ff53604b | 635 | |
3f3f78b6 XG |
636 | /* |
637 | * Please refer to Intel SDM Volume 3: 11.11.4.1 MTRR | |
638 | * Precedences. | |
639 | */ | |
640 | ||
3f3f78b6 XG |
641 | if (type == -1) { |
642 | type = curr_type; | |
ff53604b XG |
643 | continue; |
644 | } | |
645 | ||
3f3f78b6 XG |
646 | /* |
647 | * If two or more variable memory ranges match and the | |
648 | * memory types are identical, then that memory type is | |
649 | * used. | |
650 | */ | |
651 | if (type == curr_type) | |
652 | continue; | |
653 | ||
654 | /* | |
655 | * If two or more variable memory ranges match and one of | |
656 | * the memory types is UC, the UC memory type used. | |
657 | */ | |
658 | if (curr_type == MTRR_TYPE_UNCACHABLE) | |
ff53604b XG |
659 | return MTRR_TYPE_UNCACHABLE; |
660 | ||
3f3f78b6 XG |
661 | /* |
662 | * If two or more variable memory ranges match and the | |
663 | * memory types are WT and WB, the WT memory type is used. | |
664 | */ | |
665 | if (((1 << type) & wt_wb_mask) && | |
666 | ((1 << curr_type) & wt_wb_mask)) { | |
667 | type = MTRR_TYPE_WRTHROUGH; | |
668 | continue; | |
ff53604b XG |
669 | } |
670 | ||
3f3f78b6 XG |
671 | /* |
672 | * For overlaps not defined by the above rules, processor | |
673 | * behavior is undefined. | |
674 | */ | |
675 | ||
676 | /* We use WB for this undefined behavior. :( */ | |
677 | return MTRR_TYPE_WRBACK; | |
ff53604b XG |
678 | } |
679 | ||
10dc331f | 680 | if (iter.mtrr_disabled) |
e24dea2a | 681 | return mtrr_disabled_type(vcpu); |
10dc331f | 682 | |
fc1a8126 AW |
683 | /* not contained in any MTRRs. */ |
684 | if (type == -1) | |
685 | return mtrr_default_type(mtrr_state); | |
686 | ||
3e5d2fdc XG |
687 | /* |
688 | * We just check one page, partially covered by MTRRs is | |
689 | * impossible. | |
690 | */ | |
691 | WARN_ON(iter.partial_map); | |
692 | ||
fa612137 | 693 | return type; |
ff53604b | 694 | } |
ff53604b | 695 | EXPORT_SYMBOL_GPL(kvm_mtrr_get_guest_memory_type); |
6a39bbc5 XG |
696 | |
697 | bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, | |
698 | int page_num) | |
699 | { | |
700 | struct kvm_mtrr *mtrr_state = &vcpu->arch.mtrr_state; | |
701 | struct mtrr_iter iter; | |
702 | u64 start, end; | |
703 | int type = -1; | |
704 | ||
705 | start = gfn_to_gpa(gfn); | |
706 | end = gfn_to_gpa(gfn + page_num); | |
707 | mtrr_for_each_mem_type(&iter, mtrr_state, start, end) { | |
708 | if (type == -1) { | |
709 | type = iter.mem_type; | |
710 | continue; | |
711 | } | |
712 | ||
713 | if (type != iter.mem_type) | |
714 | return false; | |
715 | } | |
716 | ||
10dc331f XG |
717 | if (iter.mtrr_disabled) |
718 | return true; | |
719 | ||
6a39bbc5 XG |
720 | if (!iter.partial_map) |
721 | return true; | |
722 | ||
723 | if (type == -1) | |
724 | return true; | |
725 | ||
726 | return type == mtrr_default_type(mtrr_state); | |
727 | } |