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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
cea0f0e7 | 66 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 67 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 68 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 69 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
70 | unsigned pt_access; |
71 | unsigned pte_access; | |
815af8d4 | 72 | gfn_t gfn; |
8c28d031 | 73 | struct x86_exception fault; |
6aa8b732 AK |
74 | }; |
75 | ||
e04da980 | 76 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 77 | { |
e04da980 | 78 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
79 | } |
80 | ||
a78484c6 | 81 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
82 | pt_element_t __user *ptep_user, unsigned index, |
83 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 84 | { |
c8cfbb55 | 85 | int npages; |
b3e4e63f MT |
86 | pt_element_t ret; |
87 | pt_element_t *table; | |
88 | struct page *page; | |
89 | ||
c8cfbb55 TY |
90 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
91 | /* Check if the user is doing something meaningless. */ | |
92 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
93 | return -EFAULT; |
94 | ||
b3e4e63f | 95 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 96 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
97 | kunmap_atomic(table, KM_USER0); |
98 | ||
99 | kvm_release_page_dirty(page); | |
100 | ||
101 | return (ret != orig_pte); | |
102 | } | |
103 | ||
bedbe4ee AK |
104 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
105 | { | |
106 | unsigned access; | |
107 | ||
108 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
109 | #if PTTYPE == 64 | |
2d48a985 | 110 | if (vcpu->arch.mmu.nx) |
bedbe4ee AK |
111 | access &= ~(gpte >> PT64_NX_SHIFT); |
112 | #endif | |
113 | return access; | |
114 | } | |
115 | ||
ac79c978 AK |
116 | /* |
117 | * Fetch a guest pte for a guest virtual address | |
118 | */ | |
1e301feb JR |
119 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
120 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 121 | gva_t addr, u32 access) |
6aa8b732 | 122 | { |
42bf3f0a | 123 | pt_element_t pte; |
b7233635 | 124 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 125 | gfn_t table_gfn; |
f59c1d2d | 126 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 127 | gpa_t pte_gpa; |
134291bf TY |
128 | bool eperm; |
129 | int offset; | |
130 | const int write_fault = access & PFERR_WRITE_MASK; | |
131 | const int user_fault = access & PFERR_USER_MASK; | |
132 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
133 | u16 errcode = 0; | |
6aa8b732 | 134 | |
07420171 AK |
135 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
136 | fetch_fault); | |
b3e4e63f | 137 | walk: |
134291bf | 138 | eperm = false; |
1e301feb JR |
139 | walker->level = mmu->root_level; |
140 | pte = mmu->get_cr3(vcpu); | |
141 | ||
1b0973bd | 142 | #if PTTYPE == 64 |
1e301feb | 143 | if (walker->level == PT32E_ROOT_LEVEL) { |
d41d1895 | 144 | pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3); |
07420171 | 145 | trace_kvm_mmu_paging_element(pte, walker->level); |
134291bf | 146 | if (!is_present_gpte(pte)) |
f59c1d2d | 147 | goto error; |
1b0973bd AK |
148 | --walker->level; |
149 | } | |
150 | #endif | |
a9058ecd | 151 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 152 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 153 | |
fe135d2c | 154 | pt_access = ACC_ALL; |
ac79c978 AK |
155 | |
156 | for (;;) { | |
6e2ca7d1 TY |
157 | gfn_t real_gfn; |
158 | unsigned long host_addr; | |
159 | ||
42bf3f0a | 160 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 161 | |
5fb07ddb | 162 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
163 | offset = index * sizeof(pt_element_t); |
164 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 165 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 166 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 167 | |
6e2ca7d1 TY |
168 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
169 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
170 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
171 | goto error; | |
6e2ca7d1 TY |
172 | real_gfn = gpa_to_gfn(real_gfn); |
173 | ||
174 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
175 | if (unlikely(kvm_is_error_hva(host_addr))) |
176 | goto error; | |
6e2ca7d1 TY |
177 | |
178 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
179 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
180 | goto error; | |
a6085fba | 181 | |
07420171 | 182 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 183 | |
134291bf TY |
184 | if (unlikely(!is_present_gpte(pte))) |
185 | goto error; | |
7993ba43 | 186 | |
781e0743 AK |
187 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
188 | walker->level))) { | |
134291bf TY |
189 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
190 | goto error; | |
f59c1d2d | 191 | } |
82725b20 | 192 | |
781e0743 AK |
193 | if (unlikely(write_fault && !is_writable_pte(pte) |
194 | && (user_fault || is_write_protection(vcpu)))) | |
195 | eperm = true; | |
7993ba43 | 196 | |
781e0743 | 197 | if (unlikely(user_fault && !(pte & PT_USER_MASK))) |
f59c1d2d | 198 | eperm = true; |
7993ba43 | 199 | |
73b1087e | 200 | #if PTTYPE == 64 |
781e0743 | 201 | if (unlikely(fetch_fault && (pte & PT64_NX_MASK))) |
f59c1d2d | 202 | eperm = true; |
73b1087e AK |
203 | #endif |
204 | ||
134291bf | 205 | if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) { |
a78484c6 | 206 | int ret; |
07420171 AK |
207 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
208 | sizeof(pte)); | |
c8cfbb55 TY |
209 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, |
210 | pte, pte|PT_ACCESSED_MASK); | |
134291bf TY |
211 | if (unlikely(ret < 0)) |
212 | goto error; | |
213 | else if (ret) | |
b3e4e63f | 214 | goto walk; |
a78484c6 | 215 | |
f3b8c964 | 216 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 217 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 218 | } |
815af8d4 | 219 | |
bedbe4ee | 220 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 221 | |
7819026e MT |
222 | walker->ptes[walker->level - 1] = pte; |
223 | ||
e04da980 JR |
224 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
225 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 226 | is_large_pte(pte) && |
e04da980 JR |
227 | (PTTYPE == 64 || is_pse(vcpu))) || |
228 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 229 | is_large_pte(pte) && |
1e301feb | 230 | mmu->root_level == PT64_ROOT_LEVEL)) { |
e04da980 | 231 | int lvl = walker->level; |
2329d46d JR |
232 | gpa_t real_gpa; |
233 | gfn_t gfn; | |
33770780 | 234 | u32 ac; |
e04da980 | 235 | |
e57d4a35 YW |
236 | /* check if the kernel is fetching from user page */ |
237 | if (unlikely(pte_access & PT_USER_MASK) && | |
238 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
239 | if (fetch_fault && !user_fault) | |
240 | eperm = true; | |
241 | ||
2329d46d JR |
242 | gfn = gpte_to_gfn_lvl(pte, lvl); |
243 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
244 | |
245 | if (PTTYPE == 32 && | |
246 | walker->level == PT_DIRECTORY_LEVEL && | |
247 | is_cpuid_PSE36()) | |
2329d46d JR |
248 | gfn += pse36_gfn_delta(pte); |
249 | ||
33770780 | 250 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
251 | |
252 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 253 | ac); |
2329d46d JR |
254 | if (real_gpa == UNMAPPED_GVA) |
255 | return 0; | |
256 | ||
257 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 258 | |
ac79c978 | 259 | break; |
815af8d4 | 260 | } |
ac79c978 | 261 | |
fe135d2c | 262 | pt_access = pte_access; |
ac79c978 AK |
263 | --walker->level; |
264 | } | |
42bf3f0a | 265 | |
134291bf TY |
266 | if (unlikely(eperm)) { |
267 | errcode |= PFERR_PRESENT_MASK; | |
f59c1d2d | 268 | goto error; |
134291bf | 269 | } |
f59c1d2d | 270 | |
781e0743 | 271 | if (write_fault && unlikely(!is_dirty_gpte(pte))) { |
a78484c6 | 272 | int ret; |
b3e4e63f | 273 | |
07420171 | 274 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
c8cfbb55 TY |
275 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, |
276 | pte, pte|PT_DIRTY_MASK); | |
134291bf | 277 | if (unlikely(ret < 0)) |
a78484c6 | 278 | goto error; |
134291bf | 279 | else if (ret) |
b3e4e63f | 280 | goto walk; |
a78484c6 | 281 | |
f3b8c964 | 282 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 283 | pte |= PT_DIRTY_MASK; |
7819026e | 284 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
285 | } |
286 | ||
fe135d2c AK |
287 | walker->pt_access = pt_access; |
288 | walker->pte_access = pte_access; | |
289 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 290 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
291 | return 1; |
292 | ||
f59c1d2d | 293 | error: |
134291bf | 294 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
295 | if (fetch_fault && (mmu->nx || |
296 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 297 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 298 | |
134291bf TY |
299 | walker->fault.vector = PF_VECTOR; |
300 | walker->fault.error_code_valid = true; | |
301 | walker->fault.error_code = errcode; | |
6389ee94 AK |
302 | walker->fault.address = addr; |
303 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 304 | |
8c28d031 | 305 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 306 | return 0; |
6aa8b732 AK |
307 | } |
308 | ||
1e301feb | 309 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 310 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
311 | { |
312 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 313 | access); |
1e301feb JR |
314 | } |
315 | ||
6539e738 JR |
316 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
317 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 318 | u32 access) |
6539e738 JR |
319 | { |
320 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 321 | addr, access); |
6539e738 JR |
322 | } |
323 | ||
407c61c6 XG |
324 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
325 | struct kvm_mmu_page *sp, u64 *spte, | |
326 | pt_element_t gpte) | |
327 | { | |
328 | u64 nonpresent = shadow_trap_nonpresent_pte; | |
329 | ||
330 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
331 | goto no_present; | |
332 | ||
333 | if (!is_present_gpte(gpte)) { | |
334 | if (!sp->unsync) | |
335 | nonpresent = shadow_notrap_nonpresent_pte; | |
336 | goto no_present; | |
337 | } | |
338 | ||
339 | if (!(gpte & PT_ACCESSED_MASK)) | |
340 | goto no_present; | |
341 | ||
342 | return false; | |
343 | ||
344 | no_present: | |
345 | drop_spte(vcpu->kvm, spte, nonpresent); | |
346 | return true; | |
347 | } | |
348 | ||
ac3cd03c | 349 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 350 | u64 *spte, const void *pte) |
0028425f AK |
351 | { |
352 | pt_element_t gpte; | |
41074d07 | 353 | unsigned pte_access; |
35149e21 | 354 | pfn_t pfn; |
0028425f | 355 | |
0028425f | 356 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 357 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 358 | return; |
407c61c6 | 359 | |
b8688d51 | 360 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 361 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
0f53b5b1 XG |
362 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
363 | if (is_error_pfn(pfn)) { | |
364 | kvm_release_pfn_clean(pfn); | |
d7824fff | 365 | return; |
0f53b5b1 | 366 | } |
0f53b5b1 | 367 | |
1403283a | 368 | /* |
0d2eb44f | 369 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
370 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
371 | */ | |
ac3cd03c | 372 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 373 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 374 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
375 | } |
376 | ||
39c8c672 AK |
377 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
378 | struct guest_walker *gw, int level) | |
379 | { | |
39c8c672 | 380 | pt_element_t curr_pte; |
189be38d XG |
381 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
382 | u64 mask; | |
383 | int r, index; | |
384 | ||
385 | if (level == PT_PAGE_TABLE_LEVEL) { | |
386 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
387 | base_gpa = pte_gpa & ~mask; | |
388 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
389 | ||
390 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
391 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
392 | curr_pte = gw->prefetch_ptes[index]; | |
393 | } else | |
394 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 395 | &curr_pte, sizeof(curr_pte)); |
189be38d | 396 | |
39c8c672 AK |
397 | return r || curr_pte != gw->ptes[level - 1]; |
398 | } | |
399 | ||
189be38d XG |
400 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
401 | u64 *sptep) | |
957ed9ef XG |
402 | { |
403 | struct kvm_mmu_page *sp; | |
189be38d | 404 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 405 | u64 *spte; |
189be38d | 406 | int i; |
957ed9ef XG |
407 | |
408 | sp = page_header(__pa(sptep)); | |
409 | ||
410 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
411 | return; | |
412 | ||
413 | if (sp->role.direct) | |
414 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
415 | ||
416 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
417 | spte = sp->spt + i; |
418 | ||
419 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
420 | pt_element_t gpte; | |
421 | unsigned pte_access; | |
422 | gfn_t gfn; | |
423 | pfn_t pfn; | |
424 | bool dirty; | |
425 | ||
426 | if (spte == sptep) | |
427 | continue; | |
428 | ||
429 | if (*spte != shadow_trap_nonpresent_pte) | |
430 | continue; | |
431 | ||
432 | gpte = gptep[i]; | |
433 | ||
407c61c6 | 434 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
435 | continue; |
436 | ||
437 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
438 | gfn = gpte_to_gfn(gpte); | |
439 | dirty = is_dirty_gpte(gpte); | |
440 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
441 | (pte_access & ACC_WRITE_MASK) && dirty); | |
442 | if (is_error_pfn(pfn)) { | |
443 | kvm_release_pfn_clean(pfn); | |
444 | break; | |
445 | } | |
446 | ||
447 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
448 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
449 | pfn, true, true); | |
450 | } | |
451 | } | |
452 | ||
6aa8b732 AK |
453 | /* |
454 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
455 | */ | |
e7a04c99 AK |
456 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
457 | struct guest_walker *gw, | |
7e4e4056 | 458 | int user_fault, int write_fault, int hlevel, |
fb67e14f XG |
459 | int *ptwrite, pfn_t pfn, bool map_writable, |
460 | bool prefault) | |
6aa8b732 | 461 | { |
abb9e0b8 | 462 | unsigned access = gw->pt_access; |
5991b332 | 463 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 464 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 465 | int top_level; |
84754cd8 | 466 | unsigned direct_access; |
24157aaf | 467 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 468 | |
43a3795a | 469 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 470 | return NULL; |
6aa8b732 | 471 | |
84754cd8 XG |
472 | direct_access = gw->pt_access & gw->pte_access; |
473 | if (!dirty) | |
474 | direct_access &= ~ACC_WRITE_MASK; | |
475 | ||
5991b332 AK |
476 | top_level = vcpu->arch.mmu.root_level; |
477 | if (top_level == PT32E_ROOT_LEVEL) | |
478 | top_level = PT32_ROOT_LEVEL; | |
479 | /* | |
480 | * Verify that the top-level gpte is still there. Since the page | |
481 | * is a root page, it is either write protected (and cannot be | |
482 | * changed from now on) or it is invalid (in which case, we don't | |
483 | * really care if it changes underneath us after this point). | |
484 | */ | |
485 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
486 | goto out_gpte_changed; | |
487 | ||
24157aaf AK |
488 | for (shadow_walk_init(&it, vcpu, addr); |
489 | shadow_walk_okay(&it) && it.level > gw->level; | |
490 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
491 | gfn_t table_gfn; |
492 | ||
24157aaf | 493 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 494 | |
5991b332 | 495 | sp = NULL; |
24157aaf AK |
496 | if (!is_shadow_present_pte(*it.sptep)) { |
497 | table_gfn = gw->table_gfn[it.level - 2]; | |
498 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
499 | false, access, it.sptep); | |
5991b332 | 500 | } |
0b3c9333 AK |
501 | |
502 | /* | |
503 | * Verify that the gpte in the page we've just write | |
504 | * protected is still there. | |
505 | */ | |
24157aaf | 506 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 507 | goto out_gpte_changed; |
abb9e0b8 | 508 | |
5991b332 | 509 | if (sp) |
24157aaf | 510 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 511 | } |
050e6499 | 512 | |
0b3c9333 | 513 | for (; |
24157aaf AK |
514 | shadow_walk_okay(&it) && it.level > hlevel; |
515 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
516 | gfn_t direct_gfn; |
517 | ||
24157aaf | 518 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 519 | |
24157aaf | 520 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 521 | |
24157aaf | 522 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
523 | continue; |
524 | ||
24157aaf | 525 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 526 | |
24157aaf AK |
527 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
528 | true, direct_access, it.sptep); | |
529 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
530 | } |
531 | ||
24157aaf AK |
532 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
533 | user_fault, write_fault, dirty, ptwrite, it.level, | |
fb67e14f | 534 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 535 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 536 | |
24157aaf | 537 | return it.sptep; |
0b3c9333 AK |
538 | |
539 | out_gpte_changed: | |
5991b332 | 540 | if (sp) |
24157aaf | 541 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
542 | kvm_release_pfn_clean(pfn); |
543 | return NULL; | |
6aa8b732 AK |
544 | } |
545 | ||
6aa8b732 AK |
546 | /* |
547 | * Page fault handler. There are several causes for a page fault: | |
548 | * - there is no shadow pte for the guest pte | |
549 | * - write access through a shadow pte marked read only so that we can set | |
550 | * the dirty bit | |
551 | * - write access to a shadow pte marked read only so we can update the page | |
552 | * dirty bitmap, when userspace requests it | |
553 | * - mmio access; in this case we will never install a present shadow pte | |
554 | * - normal guest page fault due to the guest pte marked not present, not | |
555 | * writable, or not executable | |
556 | * | |
e2dec939 AK |
557 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
558 | * a negative value on error. | |
6aa8b732 | 559 | */ |
56028d08 | 560 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 561 | bool prefault) |
6aa8b732 AK |
562 | { |
563 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
564 | int user_fault = error_code & PFERR_USER_MASK; |
565 | struct guest_walker walker; | |
d555c333 | 566 | u64 *sptep; |
cea0f0e7 | 567 | int write_pt = 0; |
e2dec939 | 568 | int r; |
35149e21 | 569 | pfn_t pfn; |
7e4e4056 | 570 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 571 | int force_pt_level; |
e930bffe | 572 | unsigned long mmu_seq; |
612819c3 | 573 | bool map_writable; |
6aa8b732 | 574 | |
b8688d51 | 575 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 576 | |
e2dec939 AK |
577 | r = mmu_topup_memory_caches(vcpu); |
578 | if (r) | |
579 | return r; | |
714b93da | 580 | |
6aa8b732 | 581 | /* |
a8b876b1 | 582 | * Look up the guest pte for the faulting address. |
6aa8b732 | 583 | */ |
33770780 | 584 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
585 | |
586 | /* | |
587 | * The page is not mapped by the guest. Let the guest handle it. | |
588 | */ | |
7993ba43 | 589 | if (!r) { |
b8688d51 | 590 | pgprintk("%s: guest page fault\n", __func__); |
fb67e14f XG |
591 | if (!prefault) { |
592 | inject_page_fault(vcpu, &walker.fault); | |
593 | /* reset fork detector */ | |
594 | vcpu->arch.last_pt_write_count = 0; | |
595 | } | |
6aa8b732 AK |
596 | return 0; |
597 | } | |
598 | ||
936a5fe6 AA |
599 | if (walker.level >= PT_DIRECTORY_LEVEL) |
600 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
601 | else | |
602 | force_pt_level = 1; | |
603 | if (!force_pt_level) { | |
7e4e4056 JR |
604 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
605 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 606 | } |
7e4e4056 | 607 | |
e930bffe | 608 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 609 | smp_rmb(); |
af585b92 | 610 | |
78b2c54a | 611 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 612 | &map_writable)) |
af585b92 | 613 | return 0; |
d7824fff | 614 | |
d196e343 | 615 | /* mmio */ |
bf998156 HY |
616 | if (is_error_pfn(pfn)) |
617 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 618 | |
aaee2c94 | 619 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
620 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
621 | goto out_unlock; | |
bc32ce21 | 622 | |
8b1fe17c | 623 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 624 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
625 | if (!force_pt_level) |
626 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 627 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
fb67e14f | 628 | level, &write_pt, pfn, map_writable, prefault); |
a24e8099 | 629 | (void)sptep; |
b8688d51 | 630 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 631 | sptep, *sptep, write_pt); |
cea0f0e7 | 632 | |
a25f7e1f | 633 | if (!write_pt) |
ad312c7c | 634 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 635 | |
1165f5fe | 636 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 637 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 638 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 639 | |
cea0f0e7 | 640 | return write_pt; |
e930bffe AA |
641 | |
642 | out_unlock: | |
643 | spin_unlock(&vcpu->kvm->mmu_lock); | |
644 | kvm_release_pfn_clean(pfn); | |
645 | return 0; | |
6aa8b732 AK |
646 | } |
647 | ||
a461930b | 648 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 649 | { |
a461930b | 650 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 651 | struct kvm_mmu_page *sp; |
08e850c6 | 652 | gpa_t pte_gpa = -1; |
a461930b AK |
653 | int level; |
654 | u64 *sptep; | |
4539b358 | 655 | int need_flush = 0; |
a461930b AK |
656 | |
657 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 658 | |
a461930b AK |
659 | for_each_shadow_entry(vcpu, gva, iterator) { |
660 | level = iterator.level; | |
661 | sptep = iterator.sptep; | |
ad218f85 | 662 | |
f78978aa | 663 | sp = page_header(__pa(sptep)); |
884a0ff0 | 664 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 665 | int offset, shift; |
08e850c6 | 666 | |
f78978aa XG |
667 | if (!sp->unsync) |
668 | break; | |
669 | ||
22c9b2d1 XG |
670 | shift = PAGE_SHIFT - |
671 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
672 | offset = sp->role.quadrant << shift; | |
673 | ||
674 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 675 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
676 | |
677 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
678 | if (is_large_pte(*sptep)) |
679 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
680 | drop_spte(vcpu->kvm, sptep, |
681 | shadow_trap_nonpresent_pte); | |
4539b358 | 682 | need_flush = 1; |
be38d276 AK |
683 | } else |
684 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 685 | break; |
87917239 | 686 | } |
a7052897 | 687 | |
f78978aa | 688 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
689 | break; |
690 | } | |
a7052897 | 691 | |
4539b358 AA |
692 | if (need_flush) |
693 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
694 | |
695 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
696 | ||
ad218f85 | 697 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
698 | |
699 | if (pte_gpa == -1) | |
700 | return; | |
701 | ||
702 | if (mmu_topup_memory_caches(vcpu)) | |
703 | return; | |
704 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
705 | } |
706 | ||
1871c602 | 707 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 708 | struct x86_exception *exception) |
6aa8b732 AK |
709 | { |
710 | struct guest_walker walker; | |
e119d117 AK |
711 | gpa_t gpa = UNMAPPED_GVA; |
712 | int r; | |
6aa8b732 | 713 | |
33770780 | 714 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 715 | |
e119d117 | 716 | if (r) { |
1755fbcc | 717 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 718 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
719 | } else if (exception) |
720 | *exception = walker.fault; | |
6aa8b732 AK |
721 | |
722 | return gpa; | |
723 | } | |
724 | ||
6539e738 | 725 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
726 | u32 access, |
727 | struct x86_exception *exception) | |
6539e738 JR |
728 | { |
729 | struct guest_walker walker; | |
730 | gpa_t gpa = UNMAPPED_GVA; | |
731 | int r; | |
732 | ||
33770780 | 733 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
734 | |
735 | if (r) { | |
736 | gpa = gfn_to_gpa(walker.gfn); | |
737 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
738 | } else if (exception) |
739 | *exception = walker.fault; | |
6539e738 JR |
740 | |
741 | return gpa; | |
742 | } | |
743 | ||
c7addb90 AK |
744 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
745 | struct kvm_mmu_page *sp) | |
746 | { | |
eab9f71f AK |
747 | int i, j, offset, r; |
748 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
749 | gpa_t pte_gpa; | |
c7addb90 | 750 | |
f6e2c02b | 751 | if (sp->role.direct |
e5a4c8ca | 752 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
753 | nonpaging_prefetch_page(vcpu, sp); |
754 | return; | |
755 | } | |
756 | ||
eab9f71f AK |
757 | pte_gpa = gfn_to_gpa(sp->gfn); |
758 | if (PTTYPE == 32) { | |
e5a4c8ca | 759 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
760 | pte_gpa += offset * sizeof(pt_element_t); |
761 | } | |
7ec54588 | 762 | |
eab9f71f AK |
763 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
764 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
765 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
766 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 767 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
768 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
769 | else | |
770 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 771 | } |
c7addb90 AK |
772 | } |
773 | ||
e8bc217a MT |
774 | /* |
775 | * Using the cached information from sp->gfns is safe because: | |
776 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
777 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
778 | * |
779 | * Note: | |
780 | * We should flush all tlbs if spte is dropped even though guest is | |
781 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
782 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
783 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
784 | * freed pages. | |
785 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 786 | */ |
a4a8e6f7 | 787 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a MT |
788 | { |
789 | int i, offset, nr_present; | |
9bdbba13 | 790 | bool host_writable; |
51fb60d8 | 791 | gpa_t first_pte_gpa; |
e8bc217a MT |
792 | |
793 | offset = nr_present = 0; | |
794 | ||
2032a93d LJ |
795 | /* direct kvm_mmu_page can not be unsync. */ |
796 | BUG_ON(sp->role.direct); | |
797 | ||
e8bc217a MT |
798 | if (PTTYPE == 32) |
799 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
800 | ||
51fb60d8 GJ |
801 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
802 | ||
e8bc217a MT |
803 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
804 | unsigned pte_access; | |
805 | pt_element_t gpte; | |
806 | gpa_t pte_gpa; | |
f55c3f41 | 807 | gfn_t gfn; |
e8bc217a MT |
808 | |
809 | if (!is_shadow_present_pte(sp->spt[i])) | |
810 | continue; | |
811 | ||
51fb60d8 | 812 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
813 | |
814 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
815 | sizeof(pt_element_t))) | |
816 | return -EINVAL; | |
817 | ||
f55c3f41 | 818 | gfn = gpte_to_gfn(gpte); |
407c61c6 XG |
819 | |
820 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { | |
a4ee1ca4 | 821 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
822 | continue; |
823 | } | |
824 | ||
825 | if (gfn != sp->gfns[i]) { | |
826 | drop_spte(vcpu->kvm, &sp->spt[i], | |
827 | shadow_trap_nonpresent_pte); | |
a4ee1ca4 | 828 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
829 | continue; |
830 | } | |
831 | ||
832 | nr_present++; | |
833 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
f8e453b0 XG |
834 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
835 | ||
e8bc217a | 836 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 837 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 838 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 839 | host_writable); |
e8bc217a MT |
840 | } |
841 | ||
842 | return !nr_present; | |
843 | } | |
844 | ||
6aa8b732 AK |
845 | #undef pt_element_t |
846 | #undef guest_walker | |
847 | #undef FNAME | |
848 | #undef PT_BASE_ADDR_MASK | |
849 | #undef PT_INDEX | |
e04da980 JR |
850 | #undef PT_LVL_ADDR_MASK |
851 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 852 | #undef PT_LEVEL_BITS |
cea0f0e7 | 853 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 854 | #undef gpte_to_gfn |
e04da980 | 855 | #undef gpte_to_gfn_lvl |
b3e4e63f | 856 | #undef CMPXCHG |