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KVM: X86: Introduce pointer to mmu context used for gva_to_gpa
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / paging_tmpl.h
CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
221d059d 10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
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11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21/*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26#if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
e04da980
JR
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
6aa8b732 33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
6aa8b732 34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90 35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
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36 #ifdef CONFIG_X86_64
37 #define PT_MAX_FULL_LEVELS 4
b3e4e63f 38 #define CMPXCHG cmpxchg
cea0f0e7 39 #else
b3e4e63f 40 #define CMPXCHG cmpxchg64
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41 #define PT_MAX_FULL_LEVELS 2
42 #endif
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43#elif PTTYPE == 32
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
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48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
6aa8b732 50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
6aa8b732 51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90 52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7 53 #define PT_MAX_FULL_LEVELS 2
b3e4e63f 54 #define CMPXCHG cmpxchg
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55#else
56 #error Invalid PTTYPE value
57#endif
58
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59#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
5fb07ddb 61
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62/*
63 * The guest_walker structure emulates the behavior of the hardware page
64 * table walker.
65 */
66struct guest_walker {
67 int level;
cea0f0e7 68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
7819026e 69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
189be38d 70 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
7819026e 71 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
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72 unsigned pt_access;
73 unsigned pte_access;
815af8d4 74 gfn_t gfn;
7993ba43 75 u32 error_code;
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76};
77
e04da980 78static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
5fb07ddb 79{
e04da980 80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
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AK
81}
82
b3e4e63f
MT
83static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
84 gfn_t table_gfn, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
86{
87 pt_element_t ret;
88 pt_element_t *table;
89 struct page *page;
90
91 page = gfn_to_page(kvm, table_gfn);
72dc67a6 92
b3e4e63f 93 table = kmap_atomic(page, KM_USER0);
b3e4e63f 94 ret = CMPXCHG(&table[index], orig_pte, new_pte);
b3e4e63f
MT
95 kunmap_atomic(table, KM_USER0);
96
97 kvm_release_page_dirty(page);
98
99 return (ret != orig_pte);
100}
101
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102static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
103{
104 unsigned access;
105
106 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
107#if PTTYPE == 64
108 if (is_nx(vcpu))
109 access &= ~(gpte >> PT64_NX_SHIFT);
110#endif
111 return access;
112}
113
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114/*
115 * Fetch a guest pte for a guest virtual address
116 */
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117static int FNAME(walk_addr_generic)(struct guest_walker *walker,
118 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
119 gva_t addr, int write_fault,
120 int user_fault, int fetch_fault)
6aa8b732 121{
42bf3f0a 122 pt_element_t pte;
cea0f0e7 123 gfn_t table_gfn;
f59c1d2d 124 unsigned index, pt_access, uninitialized_var(pte_access);
42bf3f0a 125 gpa_t pte_gpa;
f59c1d2d 126 bool eperm, present, rsvd_fault;
6aa8b732 127
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128 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
129 fetch_fault);
b3e4e63f 130walk:
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131 present = true;
132 eperm = rsvd_fault = false;
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133 walker->level = mmu->root_level;
134 pte = mmu->get_cr3(vcpu);
135
1b0973bd 136#if PTTYPE == 64
1e301feb 137 if (walker->level == PT32E_ROOT_LEVEL) {
6de4f3ad 138 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
07420171 139 trace_kvm_mmu_paging_element(pte, walker->level);
f59c1d2d
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140 if (!is_present_gpte(pte)) {
141 present = false;
142 goto error;
143 }
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144 --walker->level;
145 }
146#endif
a9058ecd 147 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
1e301feb 148 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732 149
fe135d2c 150 pt_access = ACC_ALL;
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151
152 for (;;) {
42bf3f0a 153 index = PT_INDEX(addr, walker->level);
ac79c978 154
5fb07ddb 155 table_gfn = gpte_to_gfn(pte);
1755fbcc 156 pte_gpa = gfn_to_gpa(table_gfn);
ec8d4eae 157 pte_gpa += index * sizeof(pt_element_t);
42bf3f0a 158 walker->table_gfn[walker->level - 1] = table_gfn;
7819026e 159 walker->pte_gpa[walker->level - 1] = pte_gpa;
42bf3f0a 160
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161 if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte))) {
162 present = false;
163 break;
164 }
a6085fba 165
07420171 166 trace_kvm_mmu_paging_element(pte, walker->level);
42bf3f0a 167
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168 if (!is_present_gpte(pte)) {
169 present = false;
170 break;
171 }
7993ba43 172
3241f22d 173 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
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174 rsvd_fault = true;
175 break;
176 }
82725b20 177
8dae4445 178 if (write_fault && !is_writable_pte(pte))
7993ba43 179 if (user_fault || is_write_protection(vcpu))
f59c1d2d 180 eperm = true;
7993ba43 181
42bf3f0a 182 if (user_fault && !(pte & PT_USER_MASK))
f59c1d2d 183 eperm = true;
7993ba43 184
73b1087e 185#if PTTYPE == 64
24222c2f 186 if (fetch_fault && (pte & PT64_NX_MASK))
f59c1d2d 187 eperm = true;
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188#endif
189
f59c1d2d 190 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
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191 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
192 sizeof(pte));
b3e4e63f
MT
193 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
194 index, pte, pte|PT_ACCESSED_MASK))
195 goto walk;
f3b8c964 196 mark_page_dirty(vcpu->kvm, table_gfn);
42bf3f0a 197 pte |= PT_ACCESSED_MASK;
bf3f8e86 198 }
815af8d4 199
bedbe4ee 200 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
fe135d2c 201
7819026e
MT
202 walker->ptes[walker->level - 1] = pte;
203
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JR
204 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
205 ((walker->level == PT_DIRECTORY_LEVEL) &&
814a59d2 206 is_large_pte(pte) &&
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207 (PTTYPE == 64 || is_pse(vcpu))) ||
208 ((walker->level == PT_PDPE_LEVEL) &&
814a59d2 209 is_large_pte(pte) &&
1e301feb 210 mmu->root_level == PT64_ROOT_LEVEL)) {
e04da980
JR
211 int lvl = walker->level;
212
213 walker->gfn = gpte_to_gfn_lvl(pte, lvl);
214 walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
215 >> PAGE_SHIFT;
216
217 if (PTTYPE == 32 &&
218 walker->level == PT_DIRECTORY_LEVEL &&
219 is_cpuid_PSE36())
da928521 220 walker->gfn += pse36_gfn_delta(pte);
e04da980 221
ac79c978 222 break;
815af8d4 223 }
ac79c978 224
fe135d2c 225 pt_access = pte_access;
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226 --walker->level;
227 }
42bf3f0a 228
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229 if (!present || eperm || rsvd_fault)
230 goto error;
231
43a3795a 232 if (write_fault && !is_dirty_gpte(pte)) {
b3e4e63f
MT
233 bool ret;
234
07420171 235 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
b3e4e63f
MT
236 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
237 pte|PT_DIRTY_MASK);
238 if (ret)
239 goto walk;
f3b8c964 240 mark_page_dirty(vcpu->kvm, table_gfn);
42bf3f0a 241 pte |= PT_DIRTY_MASK;
7819026e 242 walker->ptes[walker->level - 1] = pte;
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243 }
244
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245 walker->pt_access = pt_access;
246 walker->pte_access = pte_access;
247 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
518c5a05 248 __func__, (u64)pte, pte_access, pt_access);
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249 return 1;
250
f59c1d2d 251error:
7993ba43 252 walker->error_code = 0;
f59c1d2d
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253 if (present)
254 walker->error_code |= PFERR_PRESENT_MASK;
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255 if (write_fault)
256 walker->error_code |= PFERR_WRITE_MASK;
257 if (user_fault)
258 walker->error_code |= PFERR_USER_MASK;
b0eeec29 259 if (fetch_fault && is_nx(vcpu))
73b1087e 260 walker->error_code |= PFERR_FETCH_MASK;
82725b20
DE
261 if (rsvd_fault)
262 walker->error_code |= PFERR_RSVD_MASK;
8df25a32
JR
263
264 vcpu->arch.fault.address = addr;
265 vcpu->arch.fault.error_code = walker->error_code;
266
07420171 267 trace_kvm_mmu_walker_error(walker->error_code);
fe551881 268 return 0;
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269}
270
1e301feb
JR
271static int FNAME(walk_addr)(struct guest_walker *walker,
272 struct kvm_vcpu *vcpu, gva_t addr,
273 int write_fault, int user_fault, int fetch_fault)
274{
275 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
276 write_fault, user_fault, fetch_fault);
277}
278
ac3cd03c 279static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
489f1d65 280 u64 *spte, const void *pte)
0028425f
AK
281{
282 pt_element_t gpte;
41074d07 283 unsigned pte_access;
35149e21 284 pfn_t pfn;
fbc5d139 285 u64 new_spte;
0028425f 286
0028425f 287 gpte = *(const pt_element_t *)pte;
c7addb90 288 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
fbc5d139 289 if (!is_present_gpte(gpte)) {
ac3cd03c 290 if (sp->unsync)
fbc5d139
AK
291 new_spte = shadow_trap_nonpresent_pte;
292 else
293 new_spte = shadow_notrap_nonpresent_pte;
294 __set_spte(spte, new_spte);
295 }
c7addb90
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296 return;
297 }
b8688d51 298 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
ac3cd03c 299 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
d7824fff
AK
300 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
301 return;
35149e21
AL
302 pfn = vcpu->arch.update_pte.pfn;
303 if (is_error_pfn(pfn))
d7824fff 304 return;
e930bffe
AA
305 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
306 return;
35149e21 307 kvm_get_pfn(pfn);
1403283a
IE
308 /*
309 * we call mmu_set_spte() with reset_host_protection = true beacuse that
310 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
311 */
ac3cd03c 312 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
cb83cad2 313 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
1403283a 314 gpte_to_gfn(gpte), pfn, true, true);
0028425f
AK
315}
316
39c8c672
AK
317static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
318 struct guest_walker *gw, int level)
319{
39c8c672 320 pt_element_t curr_pte;
189be38d
XG
321 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
322 u64 mask;
323 int r, index;
324
325 if (level == PT_PAGE_TABLE_LEVEL) {
326 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
327 base_gpa = pte_gpa & ~mask;
328 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
329
330 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
331 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
332 curr_pte = gw->prefetch_ptes[index];
333 } else
334 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
39c8c672 335 &curr_pte, sizeof(curr_pte));
189be38d 336
39c8c672
AK
337 return r || curr_pte != gw->ptes[level - 1];
338}
339
189be38d
XG
340static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
341 u64 *sptep)
957ed9ef
XG
342{
343 struct kvm_mmu_page *sp;
3241f22d 344 struct kvm_mmu *mmu = &vcpu->arch.mmu;
189be38d 345 pt_element_t *gptep = gw->prefetch_ptes;
957ed9ef 346 u64 *spte;
189be38d 347 int i;
957ed9ef
XG
348
349 sp = page_header(__pa(sptep));
350
351 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
352 return;
353
354 if (sp->role.direct)
355 return __direct_pte_prefetch(vcpu, sp, sptep);
356
357 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
957ed9ef
XG
358 spte = sp->spt + i;
359
360 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
361 pt_element_t gpte;
362 unsigned pte_access;
363 gfn_t gfn;
364 pfn_t pfn;
365 bool dirty;
366
367 if (spte == sptep)
368 continue;
369
370 if (*spte != shadow_trap_nonpresent_pte)
371 continue;
372
373 gpte = gptep[i];
374
375 if (!is_present_gpte(gpte) ||
3241f22d 376 is_rsvd_bits_set(mmu, gpte, PT_PAGE_TABLE_LEVEL)) {
957ed9ef
XG
377 if (!sp->unsync)
378 __set_spte(spte, shadow_notrap_nonpresent_pte);
379 continue;
380 }
381
382 if (!(gpte & PT_ACCESSED_MASK))
383 continue;
384
385 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
386 gfn = gpte_to_gfn(gpte);
387 dirty = is_dirty_gpte(gpte);
388 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
389 (pte_access & ACC_WRITE_MASK) && dirty);
390 if (is_error_pfn(pfn)) {
391 kvm_release_pfn_clean(pfn);
392 break;
393 }
394
395 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
396 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
397 pfn, true, true);
398 }
399}
400
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401/*
402 * Fetch a shadow pte for a specific level in the paging hierarchy.
403 */
e7a04c99
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404static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
405 struct guest_walker *gw,
7e4e4056 406 int user_fault, int write_fault, int hlevel,
e7a04c99 407 int *ptwrite, pfn_t pfn)
6aa8b732 408{
abb9e0b8 409 unsigned access = gw->pt_access;
5991b332 410 struct kvm_mmu_page *sp = NULL;
84754cd8 411 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
5991b332 412 int top_level;
84754cd8 413 unsigned direct_access;
24157aaf 414 struct kvm_shadow_walk_iterator it;
abb9e0b8 415
43a3795a 416 if (!is_present_gpte(gw->ptes[gw->level - 1]))
e7a04c99 417 return NULL;
6aa8b732 418
84754cd8
XG
419 direct_access = gw->pt_access & gw->pte_access;
420 if (!dirty)
421 direct_access &= ~ACC_WRITE_MASK;
422
5991b332
AK
423 top_level = vcpu->arch.mmu.root_level;
424 if (top_level == PT32E_ROOT_LEVEL)
425 top_level = PT32_ROOT_LEVEL;
426 /*
427 * Verify that the top-level gpte is still there. Since the page
428 * is a root page, it is either write protected (and cannot be
429 * changed from now on) or it is invalid (in which case, we don't
430 * really care if it changes underneath us after this point).
431 */
432 if (FNAME(gpte_changed)(vcpu, gw, top_level))
433 goto out_gpte_changed;
434
24157aaf
AK
435 for (shadow_walk_init(&it, vcpu, addr);
436 shadow_walk_okay(&it) && it.level > gw->level;
437 shadow_walk_next(&it)) {
0b3c9333
AK
438 gfn_t table_gfn;
439
24157aaf 440 drop_large_spte(vcpu, it.sptep);
ef0197e8 441
5991b332 442 sp = NULL;
24157aaf
AK
443 if (!is_shadow_present_pte(*it.sptep)) {
444 table_gfn = gw->table_gfn[it.level - 2];
445 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
446 false, access, it.sptep);
5991b332 447 }
0b3c9333
AK
448
449 /*
450 * Verify that the gpte in the page we've just write
451 * protected is still there.
452 */
24157aaf 453 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
0b3c9333 454 goto out_gpte_changed;
abb9e0b8 455
5991b332 456 if (sp)
24157aaf 457 link_shadow_page(it.sptep, sp);
e7a04c99 458 }
050e6499 459
0b3c9333 460 for (;
24157aaf
AK
461 shadow_walk_okay(&it) && it.level > hlevel;
462 shadow_walk_next(&it)) {
0b3c9333
AK
463 gfn_t direct_gfn;
464
24157aaf 465 validate_direct_spte(vcpu, it.sptep, direct_access);
0b3c9333 466
24157aaf 467 drop_large_spte(vcpu, it.sptep);
0b3c9333 468
24157aaf 469 if (is_shadow_present_pte(*it.sptep))
0b3c9333
AK
470 continue;
471
24157aaf 472 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
0b3c9333 473
24157aaf
AK
474 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
475 true, direct_access, it.sptep);
476 link_shadow_page(it.sptep, sp);
0b3c9333
AK
477 }
478
24157aaf
AK
479 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
480 user_fault, write_fault, dirty, ptwrite, it.level,
0b3c9333 481 gw->gfn, pfn, false, true);
189be38d 482 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
0b3c9333 483
24157aaf 484 return it.sptep;
0b3c9333
AK
485
486out_gpte_changed:
5991b332 487 if (sp)
24157aaf 488 kvm_mmu_put_page(sp, it.sptep);
0b3c9333
AK
489 kvm_release_pfn_clean(pfn);
490 return NULL;
6aa8b732
AK
491}
492
6aa8b732
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493/*
494 * Page fault handler. There are several causes for a page fault:
495 * - there is no shadow pte for the guest pte
496 * - write access through a shadow pte marked read only so that we can set
497 * the dirty bit
498 * - write access to a shadow pte marked read only so we can update the page
499 * dirty bitmap, when userspace requests it
500 * - mmio access; in this case we will never install a present shadow pte
501 * - normal guest page fault due to the guest pte marked not present, not
502 * writable, or not executable
503 *
e2dec939
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504 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
505 * a negative value on error.
6aa8b732
AK
506 */
507static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
508 u32 error_code)
509{
510 int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732 511 int user_fault = error_code & PFERR_USER_MASK;
73b1087e 512 int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 513 struct guest_walker walker;
d555c333 514 u64 *sptep;
cea0f0e7 515 int write_pt = 0;
e2dec939 516 int r;
35149e21 517 pfn_t pfn;
7e4e4056 518 int level = PT_PAGE_TABLE_LEVEL;
e930bffe 519 unsigned long mmu_seq;
6aa8b732 520
b8688d51 521 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
714b93da 522
e2dec939
AK
523 r = mmu_topup_memory_caches(vcpu);
524 if (r)
525 return r;
714b93da 526
6aa8b732 527 /*
a8b876b1 528 * Look up the guest pte for the faulting address.
6aa8b732 529 */
73b1087e
AK
530 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
531 fetch_fault);
6aa8b732
AK
532
533 /*
534 * The page is not mapped by the guest. Let the guest handle it.
535 */
7993ba43 536 if (!r) {
b8688d51 537 pgprintk("%s: guest page fault\n", __func__);
8df25a32 538 inject_page_fault(vcpu);
ad312c7c 539 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
6aa8b732
AK
540 return 0;
541 }
542
7e4e4056
JR
543 if (walker.level >= PT_DIRECTORY_LEVEL) {
544 level = min(walker.level, mapping_level(vcpu, walker.gfn));
545 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 546 }
7e4e4056 547
e930bffe 548 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 549 smp_rmb();
35149e21 550 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
d7824fff 551
d196e343 552 /* mmio */
bf998156
HY
553 if (is_error_pfn(pfn))
554 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
d196e343 555
aaee2c94 556 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA
557 if (mmu_notifier_retry(vcpu, mmu_seq))
558 goto out_unlock;
bc32ce21 559
8b1fe17c 560 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
eb787d10 561 kvm_mmu_free_some_pages(vcpu);
d555c333 562 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
7e4e4056 563 level, &write_pt, pfn);
a24e8099 564 (void)sptep;
b8688d51 565 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
d555c333 566 sptep, *sptep, write_pt);
cea0f0e7 567
a25f7e1f 568 if (!write_pt)
ad312c7c 569 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
a25f7e1f 570
1165f5fe 571 ++vcpu->stat.pf_fixed;
8b1fe17c 572 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
aaee2c94 573 spin_unlock(&vcpu->kvm->mmu_lock);
6aa8b732 574
cea0f0e7 575 return write_pt;
e930bffe
AA
576
577out_unlock:
578 spin_unlock(&vcpu->kvm->mmu_lock);
579 kvm_release_pfn_clean(pfn);
580 return 0;
6aa8b732
AK
581}
582
a461930b 583static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
a7052897 584{
a461930b 585 struct kvm_shadow_walk_iterator iterator;
f78978aa 586 struct kvm_mmu_page *sp;
08e850c6 587 gpa_t pte_gpa = -1;
a461930b
AK
588 int level;
589 u64 *sptep;
4539b358 590 int need_flush = 0;
a461930b
AK
591
592 spin_lock(&vcpu->kvm->mmu_lock);
a7052897 593
a461930b
AK
594 for_each_shadow_entry(vcpu, gva, iterator) {
595 level = iterator.level;
596 sptep = iterator.sptep;
ad218f85 597
f78978aa 598 sp = page_header(__pa(sptep));
884a0ff0 599 if (is_last_spte(*sptep, level)) {
22c9b2d1 600 int offset, shift;
08e850c6 601
f78978aa
XG
602 if (!sp->unsync)
603 break;
604
22c9b2d1
XG
605 shift = PAGE_SHIFT -
606 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
607 offset = sp->role.quadrant << shift;
608
609 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
08e850c6 610 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
a461930b
AK
611
612 if (is_shadow_present_pte(*sptep)) {
a461930b
AK
613 if (is_large_pte(*sptep))
614 --vcpu->kvm->stat.lpages;
be38d276
AK
615 drop_spte(vcpu->kvm, sptep,
616 shadow_trap_nonpresent_pte);
4539b358 617 need_flush = 1;
be38d276
AK
618 } else
619 __set_spte(sptep, shadow_trap_nonpresent_pte);
a461930b 620 break;
87917239 621 }
a7052897 622
f78978aa 623 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
a461930b
AK
624 break;
625 }
a7052897 626
4539b358
AA
627 if (need_flush)
628 kvm_flush_remote_tlbs(vcpu->kvm);
08e850c6
AK
629
630 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
631
ad218f85 632 spin_unlock(&vcpu->kvm->mmu_lock);
08e850c6
AK
633
634 if (pte_gpa == -1)
635 return;
636
637 if (mmu_topup_memory_caches(vcpu))
638 return;
639 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
a7052897
MT
640}
641
1871c602
GN
642static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
643 u32 *error)
6aa8b732
AK
644{
645 struct guest_walker walker;
e119d117
AK
646 gpa_t gpa = UNMAPPED_GVA;
647 int r;
6aa8b732 648
1871c602
GN
649 r = FNAME(walk_addr)(&walker, vcpu, vaddr,
650 !!(access & PFERR_WRITE_MASK),
651 !!(access & PFERR_USER_MASK),
652 !!(access & PFERR_FETCH_MASK));
6aa8b732 653
e119d117 654 if (r) {
1755fbcc 655 gpa = gfn_to_gpa(walker.gfn);
e119d117 656 gpa |= vaddr & ~PAGE_MASK;
1871c602
GN
657 } else if (error)
658 *error = walker.error_code;
6aa8b732
AK
659
660 return gpa;
661}
662
c7addb90
AK
663static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
664 struct kvm_mmu_page *sp)
665{
eab9f71f
AK
666 int i, j, offset, r;
667 pt_element_t pt[256 / sizeof(pt_element_t)];
668 gpa_t pte_gpa;
c7addb90 669
f6e2c02b 670 if (sp->role.direct
e5a4c8ca 671 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
c7addb90
AK
672 nonpaging_prefetch_page(vcpu, sp);
673 return;
674 }
675
eab9f71f
AK
676 pte_gpa = gfn_to_gpa(sp->gfn);
677 if (PTTYPE == 32) {
e5a4c8ca 678 offset = sp->role.quadrant << PT64_LEVEL_BITS;
eab9f71f
AK
679 pte_gpa += offset * sizeof(pt_element_t);
680 }
7ec54588 681
eab9f71f
AK
682 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
683 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
684 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
685 for (j = 0; j < ARRAY_SIZE(pt); ++j)
43a3795a 686 if (r || is_present_gpte(pt[j]))
eab9f71f
AK
687 sp->spt[i+j] = shadow_trap_nonpresent_pte;
688 else
689 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
7ec54588 690 }
c7addb90
AK
691}
692
e8bc217a
MT
693/*
694 * Using the cached information from sp->gfns is safe because:
695 * - The spte has a reference to the struct page, so the pfn for a given gfn
696 * can't change unless all sptes pointing to it are nuked first.
e8bc217a 697 */
be71e061
XG
698static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
699 bool clear_unsync)
e8bc217a
MT
700{
701 int i, offset, nr_present;
1403283a 702 bool reset_host_protection;
51fb60d8 703 gpa_t first_pte_gpa;
e8bc217a
MT
704
705 offset = nr_present = 0;
706
2032a93d
LJ
707 /* direct kvm_mmu_page can not be unsync. */
708 BUG_ON(sp->role.direct);
709
e8bc217a
MT
710 if (PTTYPE == 32)
711 offset = sp->role.quadrant << PT64_LEVEL_BITS;
712
51fb60d8
GJ
713 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
714
e8bc217a
MT
715 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
716 unsigned pte_access;
717 pt_element_t gpte;
718 gpa_t pte_gpa;
f55c3f41 719 gfn_t gfn;
e8bc217a
MT
720
721 if (!is_shadow_present_pte(sp->spt[i]))
722 continue;
723
51fb60d8 724 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
e8bc217a
MT
725
726 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
727 sizeof(pt_element_t)))
728 return -EINVAL;
729
f55c3f41 730 gfn = gpte_to_gfn(gpte);
3241f22d 731 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)
fa1de2bf
XG
732 || gfn != sp->gfns[i] || !is_present_gpte(gpte)
733 || !(gpte & PT_ACCESSED_MASK)) {
e8bc217a
MT
734 u64 nonpresent;
735
be71e061 736 if (is_present_gpte(gpte) || !clear_unsync)
e8bc217a
MT
737 nonpresent = shadow_trap_nonpresent_pte;
738 else
739 nonpresent = shadow_notrap_nonpresent_pte;
be38d276 740 drop_spte(vcpu->kvm, &sp->spt[i], nonpresent);
e8bc217a
MT
741 continue;
742 }
743
744 nr_present++;
745 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
1403283a
IE
746 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
747 pte_access &= ~ACC_WRITE_MASK;
748 reset_host_protection = 0;
749 } else {
750 reset_host_protection = 1;
751 }
e8bc217a 752 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
7e4e4056 753 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
1403283a
IE
754 spte_to_pfn(sp->spt[i]), true, false,
755 reset_host_protection);
e8bc217a
MT
756 }
757
758 return !nr_present;
759}
760
6aa8b732
AK
761#undef pt_element_t
762#undef guest_walker
763#undef FNAME
764#undef PT_BASE_ADDR_MASK
765#undef PT_INDEX
6aa8b732 766#undef PT_LEVEL_MASK
e04da980
JR
767#undef PT_LVL_ADDR_MASK
768#undef PT_LVL_OFFSET_MASK
c7addb90 769#undef PT_LEVEL_BITS
cea0f0e7 770#undef PT_MAX_FULL_LEVELS
5fb07ddb 771#undef gpte_to_gfn
e04da980 772#undef gpte_to_gfn_lvl
b3e4e63f 773#undef CMPXCHG