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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
37406aaa NHE |
26 | /* |
27 | * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro | |
28 | * uses for EPT without A/D paging type. | |
29 | */ | |
30 | extern u64 __pure __using_nonexistent_pte_bit(void) | |
31 | __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT"); | |
32 | ||
6aa8b732 AK |
33 | #if PTTYPE == 64 |
34 | #define pt_element_t u64 | |
35 | #define guest_walker guest_walker64 | |
36 | #define FNAME(name) paging##64_##name | |
37 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
38 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
39 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 40 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 41 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
42 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
43 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
44 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
45 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
cea0f0e7 AK |
46 | #ifdef CONFIG_X86_64 |
47 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 48 | #define CMPXCHG cmpxchg |
cea0f0e7 | 49 | #else |
b3e4e63f | 50 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
51 | #define PT_MAX_FULL_LEVELS 2 |
52 | #endif | |
6aa8b732 AK |
53 | #elif PTTYPE == 32 |
54 | #define pt_element_t u32 | |
55 | #define guest_walker guest_walker32 | |
56 | #define FNAME(name) paging##32_##name | |
57 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
58 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
59 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 60 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 61 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 62 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
63 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
64 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
65 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
66 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
b3e4e63f | 67 | #define CMPXCHG cmpxchg |
37406aaa NHE |
68 | #elif PTTYPE == PTTYPE_EPT |
69 | #define pt_element_t u64 | |
70 | #define guest_walker guest_walkerEPT | |
71 | #define FNAME(name) ept_##name | |
72 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
73 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
74 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
75 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
76 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
77 | #define PT_GUEST_ACCESSED_MASK 0 | |
78 | #define PT_GUEST_DIRTY_MASK 0 | |
79 | #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit() | |
80 | #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit() | |
81 | #define CMPXCHG cmpxchg64 | |
82 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
83 | #else |
84 | #error Invalid PTTYPE value | |
85 | #endif | |
86 | ||
e04da980 JR |
87 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
88 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 89 | |
6aa8b732 AK |
90 | /* |
91 | * The guest_walker structure emulates the behavior of the hardware page | |
92 | * table walker. | |
93 | */ | |
94 | struct guest_walker { | |
95 | int level; | |
8cbc7069 | 96 | unsigned max_level; |
cea0f0e7 | 97 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 98 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 99 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 100 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 101 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
102 | unsigned pt_access; |
103 | unsigned pte_access; | |
815af8d4 | 104 | gfn_t gfn; |
8c28d031 | 105 | struct x86_exception fault; |
6aa8b732 AK |
106 | }; |
107 | ||
e04da980 | 108 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 109 | { |
e04da980 | 110 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
111 | } |
112 | ||
0ad805a0 NHE |
113 | static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte) |
114 | { | |
115 | unsigned mask; | |
116 | ||
61719a8f GN |
117 | /* dirty bit is not supported, so no need to track it */ |
118 | if (!PT_GUEST_DIRTY_MASK) | |
119 | return; | |
120 | ||
0ad805a0 NHE |
121 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
122 | ||
123 | mask = (unsigned)~ACC_WRITE_MASK; | |
124 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
125 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
126 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
127 | *access &= mask; |
128 | } | |
129 | ||
130 | static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level) | |
131 | { | |
25d92081 | 132 | int bit7 = (gpte >> 7) & 1, low6 = gpte & 0x3f; |
0ad805a0 | 133 | |
25d92081 YZ |
134 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) | |
135 | ((mmu->bad_mt_xwr & (1ull << low6)) != 0); | |
0ad805a0 NHE |
136 | } |
137 | ||
138 | static inline int FNAME(is_present_gpte)(unsigned long pte) | |
139 | { | |
37406aaa | 140 | #if PTTYPE != PTTYPE_EPT |
0ad805a0 | 141 | return is_present_gpte(pte); |
37406aaa NHE |
142 | #else |
143 | return pte & 7; | |
144 | #endif | |
0ad805a0 NHE |
145 | } |
146 | ||
a78484c6 | 147 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
148 | pt_element_t __user *ptep_user, unsigned index, |
149 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 150 | { |
c8cfbb55 | 151 | int npages; |
b3e4e63f MT |
152 | pt_element_t ret; |
153 | pt_element_t *table; | |
154 | struct page *page; | |
155 | ||
c8cfbb55 TY |
156 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
157 | /* Check if the user is doing something meaningless. */ | |
158 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
159 | return -EFAULT; |
160 | ||
8fd75e12 | 161 | table = kmap_atomic(page); |
b3e4e63f | 162 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 163 | kunmap_atomic(table); |
b3e4e63f MT |
164 | |
165 | kvm_release_page_dirty(page); | |
166 | ||
167 | return (ret != orig_pte); | |
168 | } | |
169 | ||
0ad805a0 NHE |
170 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
171 | struct kvm_mmu_page *sp, u64 *spte, | |
172 | u64 gpte) | |
173 | { | |
174 | if (FNAME(is_rsvd_bits_set)(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
175 | goto no_present; | |
176 | ||
177 | if (!FNAME(is_present_gpte)(gpte)) | |
178 | goto no_present; | |
179 | ||
61719a8f GN |
180 | /* if accessed bit is not supported prefetch non accessed gpte */ |
181 | if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
182 | goto no_present; |
183 | ||
184 | return false; | |
185 | ||
186 | no_present: | |
187 | drop_spte(vcpu->kvm, spte); | |
188 | return true; | |
189 | } | |
190 | ||
191 | static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte) | |
192 | { | |
193 | unsigned access; | |
37406aaa NHE |
194 | #if PTTYPE == PTTYPE_EPT |
195 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
196 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
197 | ACC_USER_MASK; | |
198 | #else | |
0ad805a0 NHE |
199 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; |
200 | access &= ~(gpte >> PT64_NX_SHIFT); | |
37406aaa | 201 | #endif |
0ad805a0 NHE |
202 | |
203 | return access; | |
204 | } | |
205 | ||
8cbc7069 AK |
206 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
207 | struct kvm_mmu *mmu, | |
208 | struct guest_walker *walker, | |
209 | int write_fault) | |
210 | { | |
211 | unsigned level, index; | |
212 | pt_element_t pte, orig_pte; | |
213 | pt_element_t __user *ptep_user; | |
214 | gfn_t table_gfn; | |
215 | int ret; | |
216 | ||
61719a8f GN |
217 | /* dirty/accessed bits are not supported, so no need to update them */ |
218 | if (!PT_GUEST_DIRTY_MASK) | |
219 | return 0; | |
220 | ||
8cbc7069 AK |
221 | for (level = walker->max_level; level >= walker->level; --level) { |
222 | pte = orig_pte = walker->ptes[level - 1]; | |
223 | table_gfn = walker->table_gfn[level - 1]; | |
224 | ptep_user = walker->ptep_user[level - 1]; | |
225 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 226 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 227 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 228 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 229 | } |
0ad805a0 | 230 | if (level == walker->level && write_fault && |
d8089bac | 231 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 232 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 233 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
234 | } |
235 | if (pte == orig_pte) | |
236 | continue; | |
237 | ||
238 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); | |
239 | if (ret) | |
240 | return ret; | |
241 | ||
242 | mark_page_dirty(vcpu->kvm, table_gfn); | |
243 | walker->ptes[level] = pte; | |
244 | } | |
245 | return 0; | |
246 | } | |
247 | ||
ac79c978 AK |
248 | /* |
249 | * Fetch a guest pte for a guest virtual address | |
250 | */ | |
1e301feb JR |
251 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
252 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 253 | gva_t addr, u32 access) |
6aa8b732 | 254 | { |
8cbc7069 | 255 | int ret; |
42bf3f0a | 256 | pt_element_t pte; |
b7233635 | 257 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 258 | gfn_t table_gfn; |
b0cfeb5d | 259 | unsigned index, pt_access, pte_access, accessed_dirty; |
42bf3f0a | 260 | gpa_t pte_gpa; |
134291bf TY |
261 | int offset; |
262 | const int write_fault = access & PFERR_WRITE_MASK; | |
263 | const int user_fault = access & PFERR_USER_MASK; | |
264 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
265 | u16 errcode = 0; | |
13d22b6a AK |
266 | gpa_t real_gpa; |
267 | gfn_t gfn; | |
6aa8b732 | 268 | |
6fbc2770 | 269 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 270 | retry_walk: |
1e301feb JR |
271 | walker->level = mmu->root_level; |
272 | pte = mmu->get_cr3(vcpu); | |
273 | ||
1b0973bd | 274 | #if PTTYPE == 64 |
1e301feb | 275 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 276 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 277 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 278 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 279 | goto error; |
1b0973bd AK |
280 | --walker->level; |
281 | } | |
282 | #endif | |
8cbc7069 | 283 | walker->max_level = walker->level; |
a9058ecd | 284 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 285 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 286 | |
d8089bac | 287 | accessed_dirty = PT_GUEST_ACCESSED_MASK; |
13d22b6a AK |
288 | pt_access = pte_access = ACC_ALL; |
289 | ++walker->level; | |
ac79c978 | 290 | |
13d22b6a | 291 | do { |
6e2ca7d1 TY |
292 | gfn_t real_gfn; |
293 | unsigned long host_addr; | |
294 | ||
13d22b6a AK |
295 | pt_access &= pte_access; |
296 | --walker->level; | |
297 | ||
42bf3f0a | 298 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 299 | |
5fb07ddb | 300 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
301 | offset = index * sizeof(pt_element_t); |
302 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 303 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 304 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 305 | |
6e2ca7d1 TY |
306 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
307 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
308 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
309 | goto error; | |
6e2ca7d1 TY |
310 | real_gfn = gpa_to_gfn(real_gfn); |
311 | ||
312 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
313 | if (unlikely(kvm_is_error_hva(host_addr))) |
314 | goto error; | |
6e2ca7d1 TY |
315 | |
316 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
317 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
318 | goto error; | |
8cbc7069 | 319 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 320 | |
07420171 | 321 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 322 | |
0ad805a0 | 323 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 324 | goto error; |
7993ba43 | 325 | |
0ad805a0 NHE |
326 | if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, |
327 | walker->level))) { | |
134291bf TY |
328 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
329 | goto error; | |
f59c1d2d | 330 | } |
82725b20 | 331 | |
b514c30f | 332 | accessed_dirty &= pte; |
0ad805a0 | 333 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
73b1087e | 334 | |
7819026e | 335 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 336 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 337 | |
71331a1d | 338 | if (unlikely(permission_fault(mmu, pte_access, access))) { |
134291bf | 339 | errcode |= PFERR_PRESENT_MASK; |
f59c1d2d | 340 | goto error; |
134291bf | 341 | } |
f59c1d2d | 342 | |
13d22b6a AK |
343 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
344 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
345 | ||
346 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
347 | gfn += pse36_gfn_delta(pte); | |
348 | ||
c5421519 | 349 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access); |
13d22b6a AK |
350 | if (real_gpa == UNMAPPED_GVA) |
351 | return 0; | |
352 | ||
353 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
354 | ||
8ea667f2 | 355 | if (!write_fault) |
0ad805a0 | 356 | FNAME(protect_clean_gpte)(&pte_access, pte); |
908e7d79 GN |
357 | else |
358 | /* | |
61719a8f GN |
359 | * On a write fault, fold the dirty bit into accessed_dirty. |
360 | * For modes without A/D bits support accessed_dirty will be | |
361 | * always clear. | |
908e7d79 | 362 | */ |
d8089bac GN |
363 | accessed_dirty &= pte >> |
364 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
365 | |
366 | if (unlikely(!accessed_dirty)) { | |
367 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
368 | if (unlikely(ret < 0)) | |
369 | goto error; | |
370 | else if (ret) | |
371 | goto retry_walk; | |
372 | } | |
42bf3f0a | 373 | |
fe135d2c AK |
374 | walker->pt_access = pt_access; |
375 | walker->pte_access = pte_access; | |
376 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 377 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
378 | return 1; |
379 | ||
f59c1d2d | 380 | error: |
134291bf | 381 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
382 | if (fetch_fault && (mmu->nx || |
383 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 384 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 385 | |
134291bf TY |
386 | walker->fault.vector = PF_VECTOR; |
387 | walker->fault.error_code_valid = true; | |
388 | walker->fault.error_code = errcode; | |
25d92081 YZ |
389 | |
390 | #if PTTYPE == PTTYPE_EPT | |
391 | /* | |
392 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
393 | * misconfiguration requires to be injected. The detection is | |
394 | * done by is_rsvd_bits_set() above. | |
395 | * | |
396 | * We set up the value of exit_qualification to inject: | |
397 | * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation | |
398 | * [5:3] - Calculated by the page walk of the guest EPT page tables | |
399 | * [7:8] - Derived from [7:8] of real exit_qualification | |
400 | * | |
401 | * The other bits are set to 0. | |
402 | */ | |
403 | if (!(errcode & PFERR_RSVD_MASK)) { | |
404 | vcpu->arch.exit_qualification &= 0x187; | |
405 | vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3; | |
406 | } | |
407 | #endif | |
6389ee94 AK |
408 | walker->fault.address = addr; |
409 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 410 | |
8c28d031 | 411 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 412 | return 0; |
6aa8b732 AK |
413 | } |
414 | ||
1e301feb | 415 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 416 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
417 | { |
418 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 419 | access); |
1e301feb JR |
420 | } |
421 | ||
37406aaa | 422 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
423 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
424 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 425 | u32 access) |
6539e738 JR |
426 | { |
427 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 428 | addr, access); |
6539e738 | 429 | } |
37406aaa | 430 | #endif |
6539e738 | 431 | |
bd6360cc XG |
432 | static bool |
433 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
434 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 435 | { |
41074d07 | 436 | unsigned pte_access; |
bd6360cc | 437 | gfn_t gfn; |
35149e21 | 438 | pfn_t pfn; |
0028425f | 439 | |
0ad805a0 | 440 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 441 | return false; |
407c61c6 | 442 | |
b8688d51 | 443 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
444 | |
445 | gfn = gpte_to_gfn(gpte); | |
0ad805a0 NHE |
446 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
447 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
bd6360cc XG |
448 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
449 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 450 | if (is_error_pfn(pfn)) |
bd6360cc | 451 | return false; |
0f53b5b1 | 452 | |
1403283a | 453 | /* |
bd6360cc XG |
454 | * we call mmu_set_spte() with host_writable = true because |
455 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 456 | */ |
f7616203 XG |
457 | mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL, |
458 | gfn, pfn, true, true); | |
bd6360cc XG |
459 | |
460 | return true; | |
461 | } | |
462 | ||
463 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
464 | u64 *spte, const void *pte) | |
465 | { | |
466 | pt_element_t gpte = *(const pt_element_t *)pte; | |
467 | ||
468 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
469 | } |
470 | ||
39c8c672 AK |
471 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
472 | struct guest_walker *gw, int level) | |
473 | { | |
39c8c672 | 474 | pt_element_t curr_pte; |
189be38d XG |
475 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
476 | u64 mask; | |
477 | int r, index; | |
478 | ||
479 | if (level == PT_PAGE_TABLE_LEVEL) { | |
480 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
481 | base_gpa = pte_gpa & ~mask; | |
482 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
483 | ||
484 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
485 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
486 | curr_pte = gw->prefetch_ptes[index]; | |
487 | } else | |
488 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 489 | &curr_pte, sizeof(curr_pte)); |
189be38d | 490 | |
39c8c672 AK |
491 | return r || curr_pte != gw->ptes[level - 1]; |
492 | } | |
493 | ||
189be38d XG |
494 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
495 | u64 *sptep) | |
957ed9ef XG |
496 | { |
497 | struct kvm_mmu_page *sp; | |
189be38d | 498 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 499 | u64 *spte; |
189be38d | 500 | int i; |
957ed9ef XG |
501 | |
502 | sp = page_header(__pa(sptep)); | |
503 | ||
504 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
505 | return; | |
506 | ||
507 | if (sp->role.direct) | |
508 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
509 | ||
510 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
511 | spte = sp->spt + i; |
512 | ||
513 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
514 | if (spte == sptep) |
515 | continue; | |
516 | ||
c3707958 | 517 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
518 | continue; |
519 | ||
bd6360cc | 520 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 521 | break; |
957ed9ef XG |
522 | } |
523 | } | |
524 | ||
6aa8b732 AK |
525 | /* |
526 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
527 | * If the guest tries to write a write-protected page, we need to |
528 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 529 | */ |
d4878f24 | 530 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 531 | struct guest_walker *gw, |
c2288505 | 532 | int write_fault, int hlevel, |
d4878f24 | 533 | pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 534 | { |
5991b332 | 535 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 536 | struct kvm_shadow_walk_iterator it; |
d4878f24 XG |
537 | unsigned direct_access, access = gw->pt_access; |
538 | int top_level, emulate = 0; | |
abb9e0b8 | 539 | |
b36c7a7c | 540 | direct_access = gw->pte_access; |
84754cd8 | 541 | |
5991b332 AK |
542 | top_level = vcpu->arch.mmu.root_level; |
543 | if (top_level == PT32E_ROOT_LEVEL) | |
544 | top_level = PT32_ROOT_LEVEL; | |
545 | /* | |
546 | * Verify that the top-level gpte is still there. Since the page | |
547 | * is a root page, it is either write protected (and cannot be | |
548 | * changed from now on) or it is invalid (in which case, we don't | |
549 | * really care if it changes underneath us after this point). | |
550 | */ | |
551 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
552 | goto out_gpte_changed; | |
553 | ||
24157aaf AK |
554 | for (shadow_walk_init(&it, vcpu, addr); |
555 | shadow_walk_okay(&it) && it.level > gw->level; | |
556 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
557 | gfn_t table_gfn; |
558 | ||
a30f47cb | 559 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 560 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 561 | |
5991b332 | 562 | sp = NULL; |
24157aaf AK |
563 | if (!is_shadow_present_pte(*it.sptep)) { |
564 | table_gfn = gw->table_gfn[it.level - 2]; | |
565 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
566 | false, access, it.sptep); | |
5991b332 | 567 | } |
0b3c9333 AK |
568 | |
569 | /* | |
570 | * Verify that the gpte in the page we've just write | |
571 | * protected is still there. | |
572 | */ | |
24157aaf | 573 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 574 | goto out_gpte_changed; |
abb9e0b8 | 575 | |
5991b332 | 576 | if (sp) |
7a1638ce | 577 | link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK); |
e7a04c99 | 578 | } |
050e6499 | 579 | |
0b3c9333 | 580 | for (; |
24157aaf AK |
581 | shadow_walk_okay(&it) && it.level > hlevel; |
582 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
583 | gfn_t direct_gfn; |
584 | ||
a30f47cb | 585 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 586 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 587 | |
24157aaf | 588 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 589 | |
24157aaf | 590 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
591 | continue; |
592 | ||
24157aaf | 593 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 594 | |
24157aaf AK |
595 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
596 | true, direct_access, it.sptep); | |
7a1638ce | 597 | link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK); |
0b3c9333 AK |
598 | } |
599 | ||
a30f47cb | 600 | clear_sp_write_flooding_count(it.sptep); |
f7616203 XG |
601 | mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate, |
602 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 603 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 604 | |
d4878f24 | 605 | return emulate; |
0b3c9333 AK |
606 | |
607 | out_gpte_changed: | |
5991b332 | 608 | if (sp) |
24157aaf | 609 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 | 610 | kvm_release_pfn_clean(pfn); |
d4878f24 | 611 | return 0; |
6aa8b732 AK |
612 | } |
613 | ||
7751babd XG |
614 | /* |
615 | * To see whether the mapped gfn can write its page table in the current | |
616 | * mapping. | |
617 | * | |
618 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
619 | * size to map the writable gfn which is used as current page table, we should | |
620 | * force kvm to use small page size to map it because new shadow page will be | |
621 | * created when kvm establishes shadow page table that stop kvm using large | |
622 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
623 | * | |
93c05d3e XG |
624 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
625 | * currently used as its page table. | |
626 | * | |
7751babd XG |
627 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
628 | * since the PDPT is always shadowed, that means, we can not use large page | |
629 | * size to map the gfn which is used as PDPT. | |
630 | */ | |
631 | static bool | |
632 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
633 | struct guest_walker *walker, int user_fault, |
634 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
635 | { |
636 | int level; | |
637 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 638 | bool self_changed = false; |
7751babd XG |
639 | |
640 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
641 | (!is_write_protection(vcpu) && !user_fault))) | |
642 | return false; | |
643 | ||
93c05d3e XG |
644 | for (level = walker->level; level <= walker->max_level; level++) { |
645 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
646 | ||
647 | self_changed |= !(gfn & mask); | |
648 | *write_fault_to_shadow_pgtable |= !gfn; | |
649 | } | |
7751babd | 650 | |
93c05d3e | 651 | return self_changed; |
7751babd XG |
652 | } |
653 | ||
6aa8b732 AK |
654 | /* |
655 | * Page fault handler. There are several causes for a page fault: | |
656 | * - there is no shadow pte for the guest pte | |
657 | * - write access through a shadow pte marked read only so that we can set | |
658 | * the dirty bit | |
659 | * - write access to a shadow pte marked read only so we can update the page | |
660 | * dirty bitmap, when userspace requests it | |
661 | * - mmio access; in this case we will never install a present shadow pte | |
662 | * - normal guest page fault due to the guest pte marked not present, not | |
663 | * writable, or not executable | |
664 | * | |
e2dec939 AK |
665 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
666 | * a negative value on error. | |
6aa8b732 | 667 | */ |
56028d08 | 668 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 669 | bool prefault) |
6aa8b732 AK |
670 | { |
671 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
672 | int user_fault = error_code & PFERR_USER_MASK; |
673 | struct guest_walker walker; | |
e2dec939 | 674 | int r; |
35149e21 | 675 | pfn_t pfn; |
7e4e4056 | 676 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 677 | int force_pt_level; |
e930bffe | 678 | unsigned long mmu_seq; |
93c05d3e | 679 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 680 | |
b8688d51 | 681 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 682 | |
f8f55942 XG |
683 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
684 | r = handle_mmio_page_fault(vcpu, addr, error_code, | |
ce88decf | 685 | mmu_is_nested(vcpu)); |
f8f55942 XG |
686 | if (likely(r != RET_MMIO_PF_INVALID)) |
687 | return r; | |
688 | }; | |
ce88decf | 689 | |
e2dec939 AK |
690 | r = mmu_topup_memory_caches(vcpu); |
691 | if (r) | |
692 | return r; | |
714b93da | 693 | |
6aa8b732 | 694 | /* |
a8b876b1 | 695 | * Look up the guest pte for the faulting address. |
6aa8b732 | 696 | */ |
33770780 | 697 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
698 | |
699 | /* | |
700 | * The page is not mapped by the guest. Let the guest handle it. | |
701 | */ | |
7993ba43 | 702 | if (!r) { |
b8688d51 | 703 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 704 | if (!prefault) |
fb67e14f | 705 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 706 | |
6aa8b732 AK |
707 | return 0; |
708 | } | |
709 | ||
93c05d3e XG |
710 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
711 | ||
712 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
713 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
714 | ||
936a5fe6 | 715 | if (walker.level >= PT_DIRECTORY_LEVEL) |
7751babd | 716 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn) |
93c05d3e | 717 | || is_self_change_mapping; |
936a5fe6 AA |
718 | else |
719 | force_pt_level = 1; | |
720 | if (!force_pt_level) { | |
7e4e4056 JR |
721 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
722 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 723 | } |
7e4e4056 | 724 | |
e930bffe | 725 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 726 | smp_rmb(); |
af585b92 | 727 | |
78b2c54a | 728 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 729 | &map_writable)) |
af585b92 | 730 | return 0; |
d7824fff | 731 | |
d7c55201 XG |
732 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
733 | walker.gfn, pfn, walker.pte_access, &r)) | |
734 | return r; | |
735 | ||
c2288505 XG |
736 | /* |
737 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
738 | * we will cache the incorrect access into mmio spte. | |
739 | */ | |
740 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
741 | !is_write_protection(vcpu) && !user_fault && | |
742 | !is_noslot_pfn(pfn)) { | |
743 | walker.pte_access |= ACC_WRITE_MASK; | |
744 | walker.pte_access &= ~ACC_USER_MASK; | |
745 | ||
746 | /* | |
747 | * If we converted a user page to a kernel page, | |
748 | * so that the kernel can write to it when cr0.wp=0, | |
749 | * then we should prevent the kernel from executing it | |
750 | * if SMEP is enabled. | |
751 | */ | |
752 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
753 | walker.pte_access &= ~ACC_EXEC_MASK; | |
754 | } | |
755 | ||
aaee2c94 | 756 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 757 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 758 | goto out_unlock; |
bc32ce21 | 759 | |
0375f7fa | 760 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
450e0b41 | 761 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
762 | if (!force_pt_level) |
763 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 764 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 765 | level, pfn, map_writable, prefault); |
1165f5fe | 766 | ++vcpu->stat.pf_fixed; |
0375f7fa | 767 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 768 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 769 | |
d4878f24 | 770 | return r; |
e930bffe AA |
771 | |
772 | out_unlock: | |
773 | spin_unlock(&vcpu->kvm->mmu_lock); | |
774 | kvm_release_pfn_clean(pfn); | |
775 | return 0; | |
6aa8b732 AK |
776 | } |
777 | ||
505aef8f XG |
778 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
779 | { | |
780 | int offset = 0; | |
781 | ||
f71fa31f | 782 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
783 | |
784 | if (PTTYPE == 32) | |
785 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
786 | ||
787 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
788 | } | |
789 | ||
a461930b | 790 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 791 | { |
a461930b | 792 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 793 | struct kvm_mmu_page *sp; |
a461930b AK |
794 | int level; |
795 | u64 *sptep; | |
796 | ||
bebb106a XG |
797 | vcpu_clear_mmio_info(vcpu, gva); |
798 | ||
f57f2ef5 XG |
799 | /* |
800 | * No need to check return value here, rmap_can_add() can | |
801 | * help us to skip pte prefetch later. | |
802 | */ | |
803 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 804 | |
f57f2ef5 | 805 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
806 | for_each_shadow_entry(vcpu, gva, iterator) { |
807 | level = iterator.level; | |
808 | sptep = iterator.sptep; | |
ad218f85 | 809 | |
f78978aa | 810 | sp = page_header(__pa(sptep)); |
884a0ff0 | 811 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
812 | pt_element_t gpte; |
813 | gpa_t pte_gpa; | |
814 | ||
f78978aa XG |
815 | if (!sp->unsync) |
816 | break; | |
817 | ||
505aef8f | 818 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 819 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 820 | |
505aef8f XG |
821 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
822 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
823 | |
824 | if (!rmap_can_add(vcpu)) | |
825 | break; | |
826 | ||
827 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
828 | sizeof(pt_element_t))) | |
829 | break; | |
830 | ||
831 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 832 | } |
a7052897 | 833 | |
f78978aa | 834 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
835 | break; |
836 | } | |
ad218f85 | 837 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
838 | } |
839 | ||
1871c602 | 840 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 841 | struct x86_exception *exception) |
6aa8b732 AK |
842 | { |
843 | struct guest_walker walker; | |
e119d117 AK |
844 | gpa_t gpa = UNMAPPED_GVA; |
845 | int r; | |
6aa8b732 | 846 | |
33770780 | 847 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 848 | |
e119d117 | 849 | if (r) { |
1755fbcc | 850 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 851 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
852 | } else if (exception) |
853 | *exception = walker.fault; | |
6aa8b732 AK |
854 | |
855 | return gpa; | |
856 | } | |
857 | ||
37406aaa | 858 | #if PTTYPE != PTTYPE_EPT |
6539e738 | 859 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
860 | u32 access, |
861 | struct x86_exception *exception) | |
6539e738 JR |
862 | { |
863 | struct guest_walker walker; | |
864 | gpa_t gpa = UNMAPPED_GVA; | |
865 | int r; | |
866 | ||
33770780 | 867 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
868 | |
869 | if (r) { | |
870 | gpa = gfn_to_gpa(walker.gfn); | |
871 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
872 | } else if (exception) |
873 | *exception = walker.fault; | |
6539e738 JR |
874 | |
875 | return gpa; | |
876 | } | |
37406aaa | 877 | #endif |
6539e738 | 878 | |
e8bc217a MT |
879 | /* |
880 | * Using the cached information from sp->gfns is safe because: | |
881 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
882 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
883 | * |
884 | * Note: | |
885 | * We should flush all tlbs if spte is dropped even though guest is | |
886 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
887 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
888 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
889 | * freed pages. | |
890 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 891 | */ |
a4a8e6f7 | 892 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 893 | { |
505aef8f | 894 | int i, nr_present = 0; |
9bdbba13 | 895 | bool host_writable; |
51fb60d8 | 896 | gpa_t first_pte_gpa; |
e8bc217a | 897 | |
2032a93d LJ |
898 | /* direct kvm_mmu_page can not be unsync. */ |
899 | BUG_ON(sp->role.direct); | |
900 | ||
505aef8f | 901 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 902 | |
e8bc217a MT |
903 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
904 | unsigned pte_access; | |
905 | pt_element_t gpte; | |
906 | gpa_t pte_gpa; | |
f55c3f41 | 907 | gfn_t gfn; |
e8bc217a | 908 | |
ce88decf | 909 | if (!sp->spt[i]) |
e8bc217a MT |
910 | continue; |
911 | ||
51fb60d8 | 912 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
913 | |
914 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
915 | sizeof(pt_element_t))) | |
916 | return -EINVAL; | |
917 | ||
0ad805a0 | 918 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
a4ee1ca4 | 919 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
920 | continue; |
921 | } | |
922 | ||
ce88decf XG |
923 | gfn = gpte_to_gfn(gpte); |
924 | pte_access = sp->role.access; | |
0ad805a0 NHE |
925 | pte_access &= FNAME(gpte_access)(vcpu, gpte); |
926 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
ce88decf | 927 | |
f2fd125d XG |
928 | if (sync_mmio_spte(vcpu->kvm, &sp->spt[i], gfn, pte_access, |
929 | &nr_present)) | |
ce88decf XG |
930 | continue; |
931 | ||
407c61c6 | 932 | if (gfn != sp->gfns[i]) { |
c3707958 | 933 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a4ee1ca4 | 934 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
935 | continue; |
936 | } | |
937 | ||
938 | nr_present++; | |
ce88decf | 939 | |
f8e453b0 XG |
940 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
941 | ||
c2288505 | 942 | set_spte(vcpu, &sp->spt[i], pte_access, |
640d9b0d | 943 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 944 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 945 | host_writable); |
e8bc217a MT |
946 | } |
947 | ||
948 | return !nr_present; | |
949 | } | |
950 | ||
6aa8b732 AK |
951 | #undef pt_element_t |
952 | #undef guest_walker | |
953 | #undef FNAME | |
954 | #undef PT_BASE_ADDR_MASK | |
955 | #undef PT_INDEX | |
e04da980 JR |
956 | #undef PT_LVL_ADDR_MASK |
957 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 958 | #undef PT_LEVEL_BITS |
cea0f0e7 | 959 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 960 | #undef gpte_to_gfn |
e04da980 | 961 | #undef gpte_to_gfn_lvl |
b3e4e63f | 962 | #undef CMPXCHG |
d8089bac GN |
963 | #undef PT_GUEST_ACCESSED_MASK |
964 | #undef PT_GUEST_DIRTY_MASK | |
965 | #undef PT_GUEST_DIRTY_SHIFT | |
966 | #undef PT_GUEST_ACCESSED_SHIFT |