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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
35 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
36 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 37 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
cea0f0e7 AK |
38 | #ifdef CONFIG_X86_64 |
39 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 40 | #define CMPXCHG cmpxchg |
cea0f0e7 | 41 | #else |
b3e4e63f | 42 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
43 | #define PT_MAX_FULL_LEVELS 2 |
44 | #endif | |
6aa8b732 AK |
45 | #elif PTTYPE == 32 |
46 | #define pt_element_t u32 | |
47 | #define guest_walker guest_walker32 | |
48 | #define FNAME(name) paging##32_##name | |
49 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
50 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
51 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 52 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 53 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 54 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
55 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
56 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 57 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
b3e4e63f | 58 | #define CMPXCHG cmpxchg |
37406aaa NHE |
59 | #elif PTTYPE == PTTYPE_EPT |
60 | #define pt_element_t u64 | |
61 | #define guest_walker guest_walkerEPT | |
62 | #define FNAME(name) ept_##name | |
63 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
64 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
65 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
66 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
67 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
ae1e2d10 PB |
68 | #define PT_GUEST_DIRTY_SHIFT 9 |
69 | #define PT_GUEST_ACCESSED_SHIFT 8 | |
70 | #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) | |
37406aaa NHE |
71 | #define CMPXCHG cmpxchg64 |
72 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
73 | #else |
74 | #error Invalid PTTYPE value | |
75 | #endif | |
76 | ||
ae1e2d10 PB |
77 | #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT) |
78 | #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT) | |
79 | ||
e04da980 JR |
80 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
81 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 82 | |
6aa8b732 AK |
83 | /* |
84 | * The guest_walker structure emulates the behavior of the hardware page | |
85 | * table walker. | |
86 | */ | |
87 | struct guest_walker { | |
88 | int level; | |
8cbc7069 | 89 | unsigned max_level; |
cea0f0e7 | 90 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 91 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 92 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 93 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 94 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 95 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
96 | unsigned pt_access; |
97 | unsigned pte_access; | |
815af8d4 | 98 | gfn_t gfn; |
8c28d031 | 99 | struct x86_exception fault; |
6aa8b732 AK |
100 | }; |
101 | ||
e04da980 | 102 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 103 | { |
e04da980 | 104 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
105 | } |
106 | ||
86407bcb PB |
107 | static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access, |
108 | unsigned gpte) | |
0ad805a0 NHE |
109 | { |
110 | unsigned mask; | |
111 | ||
61719a8f | 112 | /* dirty bit is not supported, so no need to track it */ |
86407bcb | 113 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
114 | return; |
115 | ||
0ad805a0 NHE |
116 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
117 | ||
118 | mask = (unsigned)~ACC_WRITE_MASK; | |
119 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
120 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
121 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
122 | *access &= mask; |
123 | } | |
124 | ||
0ad805a0 NHE |
125 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
126 | { | |
37406aaa | 127 | #if PTTYPE != PTTYPE_EPT |
812f30b2 | 128 | return pte & PT_PRESENT_MASK; |
37406aaa NHE |
129 | #else |
130 | return pte & 7; | |
131 | #endif | |
0ad805a0 NHE |
132 | } |
133 | ||
a78484c6 | 134 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
135 | pt_element_t __user *ptep_user, unsigned index, |
136 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 137 | { |
c8cfbb55 | 138 | int npages; |
b3e4e63f MT |
139 | pt_element_t ret; |
140 | pt_element_t *table; | |
141 | struct page *page; | |
142 | ||
73b0140b | 143 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page); |
bd53cb35 FS |
144 | if (likely(npages == 1)) { |
145 | table = kmap_atomic(page); | |
146 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
147 | kunmap_atomic(table); | |
148 | ||
149 | kvm_release_page_dirty(page); | |
150 | } else { | |
151 | struct vm_area_struct *vma; | |
152 | unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK; | |
153 | unsigned long pfn; | |
154 | unsigned long paddr; | |
155 | ||
156 | down_read(¤t->mm->mmap_sem); | |
157 | vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE); | |
158 | if (!vma || !(vma->vm_flags & VM_PFNMAP)) { | |
159 | up_read(¤t->mm->mmap_sem); | |
160 | return -EFAULT; | |
161 | } | |
162 | pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff; | |
163 | paddr = pfn << PAGE_SHIFT; | |
164 | table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB); | |
165 | if (!table) { | |
166 | up_read(¤t->mm->mmap_sem); | |
167 | return -EFAULT; | |
168 | } | |
169 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
170 | memunmap(table); | |
171 | up_read(¤t->mm->mmap_sem); | |
172 | } | |
b3e4e63f MT |
173 | |
174 | return (ret != orig_pte); | |
175 | } | |
176 | ||
0ad805a0 NHE |
177 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
178 | struct kvm_mmu_page *sp, u64 *spte, | |
179 | u64 gpte) | |
180 | { | |
44dd3ffa | 181 | if (is_rsvd_bits_set(vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
0ad805a0 NHE |
182 | goto no_present; |
183 | ||
184 | if (!FNAME(is_present_gpte)(gpte)) | |
185 | goto no_present; | |
186 | ||
61719a8f | 187 | /* if accessed bit is not supported prefetch non accessed gpte */ |
44dd3ffa VK |
188 | if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) && |
189 | !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
190 | goto no_present; |
191 | ||
192 | return false; | |
193 | ||
194 | no_present: | |
195 | drop_spte(vcpu->kvm, spte); | |
196 | return true; | |
197 | } | |
198 | ||
d95c5568 BD |
199 | /* |
200 | * For PTTYPE_EPT, a page table can be executable but not readable | |
201 | * on supported processors. Therefore, set_spte does not automatically | |
202 | * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK | |
203 | * to signify readability since it isn't used in the EPT case | |
204 | */ | |
42522d08 | 205 | static inline unsigned FNAME(gpte_access)(u64 gpte) |
0ad805a0 NHE |
206 | { |
207 | unsigned access; | |
37406aaa NHE |
208 | #if PTTYPE == PTTYPE_EPT |
209 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
210 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
d95c5568 | 211 | ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0); |
37406aaa | 212 | #else |
bb9eadf0 PB |
213 | BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK); |
214 | BUILD_BUG_ON(ACC_EXEC_MASK != 1); | |
215 | access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK); | |
216 | /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */ | |
217 | access ^= (gpte >> PT64_NX_SHIFT); | |
37406aaa | 218 | #endif |
0ad805a0 NHE |
219 | |
220 | return access; | |
221 | } | |
222 | ||
8cbc7069 AK |
223 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
224 | struct kvm_mmu *mmu, | |
225 | struct guest_walker *walker, | |
226 | int write_fault) | |
227 | { | |
228 | unsigned level, index; | |
229 | pt_element_t pte, orig_pte; | |
230 | pt_element_t __user *ptep_user; | |
231 | gfn_t table_gfn; | |
232 | int ret; | |
233 | ||
61719a8f | 234 | /* dirty/accessed bits are not supported, so no need to update them */ |
86407bcb | 235 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
236 | return 0; |
237 | ||
8cbc7069 AK |
238 | for (level = walker->max_level; level >= walker->level; --level) { |
239 | pte = orig_pte = walker->ptes[level - 1]; | |
240 | table_gfn = walker->table_gfn[level - 1]; | |
241 | ptep_user = walker->ptep_user[level - 1]; | |
242 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 243 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 244 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 245 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 246 | } |
0ad805a0 | 247 | if (level == walker->level && write_fault && |
d8089bac | 248 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 249 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
bab4165e BD |
250 | #if PTTYPE == PTTYPE_EPT |
251 | if (kvm_arch_write_log_dirty(vcpu)) | |
252 | return -EINVAL; | |
253 | #endif | |
d8089bac | 254 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
255 | } |
256 | if (pte == orig_pte) | |
257 | continue; | |
258 | ||
ba6a3541 PB |
259 | /* |
260 | * If the slot is read-only, simply do not process the accessed | |
261 | * and dirty bits. This is the correct thing to do if the slot | |
262 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
263 | * are only supported if the accessed and dirty bits are already | |
264 | * set in the ROM (so that MMIO writes are never needed). | |
265 | * | |
266 | * Note that NPT does not allow this at all and faults, since | |
267 | * it always wants nested page table entries for the guest | |
268 | * page tables to be writable. And EPT works but will simply | |
269 | * overwrite the read-only memory to set the accessed and dirty | |
270 | * bits. | |
271 | */ | |
272 | if (unlikely(!walker->pte_writable[level - 1])) | |
273 | continue; | |
274 | ||
8cbc7069 AK |
275 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
276 | if (ret) | |
277 | return ret; | |
278 | ||
54bf36aa | 279 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
17e4bce0 | 280 | walker->ptes[level - 1] = pte; |
8cbc7069 AK |
281 | } |
282 | return 0; | |
283 | } | |
284 | ||
be94f6b7 HH |
285 | static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte) |
286 | { | |
287 | unsigned pkeys = 0; | |
288 | #if PTTYPE == 64 | |
289 | pte_t pte = {.pte = gpte}; | |
290 | ||
291 | pkeys = pte_flags_pkey(pte_flags(pte)); | |
292 | #endif | |
293 | return pkeys; | |
294 | } | |
295 | ||
ac79c978 AK |
296 | /* |
297 | * Fetch a guest pte for a guest virtual address | |
298 | */ | |
1e301feb JR |
299 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
300 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 301 | gva_t addr, u32 access) |
6aa8b732 | 302 | { |
8cbc7069 | 303 | int ret; |
42bf3f0a | 304 | pt_element_t pte; |
b7233635 | 305 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 306 | gfn_t table_gfn; |
0780516a PB |
307 | u64 pt_access, pte_access; |
308 | unsigned index, accessed_dirty, pte_pkey; | |
ae1e2d10 | 309 | unsigned nested_access; |
42bf3f0a | 310 | gpa_t pte_gpa; |
86407bcb | 311 | bool have_ad; |
134291bf | 312 | int offset; |
0780516a | 313 | u64 walk_nx_mask = 0; |
134291bf TY |
314 | const int write_fault = access & PFERR_WRITE_MASK; |
315 | const int user_fault = access & PFERR_USER_MASK; | |
316 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
317 | u16 errcode = 0; | |
13d22b6a AK |
318 | gpa_t real_gpa; |
319 | gfn_t gfn; | |
6aa8b732 | 320 | |
6fbc2770 | 321 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 322 | retry_walk: |
1e301feb JR |
323 | walker->level = mmu->root_level; |
324 | pte = mmu->get_cr3(vcpu); | |
86407bcb | 325 | have_ad = PT_HAVE_ACCESSED_DIRTY(mmu); |
1e301feb | 326 | |
1b0973bd | 327 | #if PTTYPE == 64 |
0780516a | 328 | walk_nx_mask = 1ULL << PT64_NX_SHIFT; |
1e301feb | 329 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 330 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 331 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 332 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 333 | goto error; |
1b0973bd AK |
334 | --walker->level; |
335 | } | |
336 | #endif | |
8cbc7069 | 337 | walker->max_level = walker->level; |
1715d0dc | 338 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 339 | |
ae1e2d10 PB |
340 | /* |
341 | * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging | |
342 | * by the MOV to CR instruction are treated as reads and do not cause the | |
343 | * processor to set the dirty flag in any EPT paging-structure entry. | |
344 | */ | |
345 | nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK; | |
346 | ||
0780516a | 347 | pte_access = ~0; |
13d22b6a | 348 | ++walker->level; |
ac79c978 | 349 | |
13d22b6a | 350 | do { |
6e2ca7d1 TY |
351 | gfn_t real_gfn; |
352 | unsigned long host_addr; | |
353 | ||
0780516a | 354 | pt_access = pte_access; |
13d22b6a AK |
355 | --walker->level; |
356 | ||
42bf3f0a | 357 | index = PT_INDEX(addr, walker->level); |
5fb07ddb | 358 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
359 | offset = index * sizeof(pt_element_t); |
360 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
829ee279 LP |
361 | |
362 | BUG_ON(walker->level < 1); | |
42bf3f0a | 363 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 364 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 365 | |
6e2ca7d1 | 366 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
ae1e2d10 | 367 | nested_access, |
54987b7a | 368 | &walker->fault); |
5e352519 PB |
369 | |
370 | /* | |
371 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
372 | * instruction) triggers a nested page fault. The exit | |
373 | * qualification / exit info field will incorrectly have | |
374 | * "guest page access" as the nested page fault's cause, | |
375 | * instead of "guest page structure access". To fix this, | |
376 | * the x86_exception struct should be augmented with enough | |
377 | * information to fix the exit_qualification or exit_info_1 | |
378 | * fields. | |
379 | */ | |
134291bf | 380 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
54987b7a | 381 | return 0; |
5e352519 | 382 | |
6e2ca7d1 TY |
383 | real_gfn = gpa_to_gfn(real_gfn); |
384 | ||
54bf36aa | 385 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn, |
ba6a3541 | 386 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
387 | if (unlikely(kvm_is_error_hva(host_addr))) |
388 | goto error; | |
6e2ca7d1 TY |
389 | |
390 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
391 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
392 | goto error; | |
8cbc7069 | 393 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 394 | |
07420171 | 395 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 396 | |
0780516a PB |
397 | /* |
398 | * Inverting the NX it lets us AND it like other | |
399 | * permission bits. | |
400 | */ | |
401 | pte_access = pt_access & (pte ^ walk_nx_mask); | |
402 | ||
0ad805a0 | 403 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 404 | goto error; |
7993ba43 | 405 | |
d2b0f981 | 406 | if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) { |
7a98205d | 407 | errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
134291bf | 408 | goto error; |
f59c1d2d | 409 | } |
82725b20 | 410 | |
7819026e | 411 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 412 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 413 | |
be94f6b7 | 414 | pte_pkey = FNAME(gpte_pkeys)(vcpu, pte); |
0780516a PB |
415 | accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0; |
416 | ||
417 | /* Convert to ACC_*_MASK flags for struct guest_walker. */ | |
42522d08 PX |
418 | walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask); |
419 | walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask); | |
0780516a | 420 | errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access); |
f13577e8 | 421 | if (unlikely(errcode)) |
f59c1d2d AK |
422 | goto error; |
423 | ||
13d22b6a AK |
424 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
425 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
426 | ||
427 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
428 | gfn += pse36_gfn_delta(pte); | |
429 | ||
54987b7a | 430 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
431 | if (real_gpa == UNMAPPED_GVA) |
432 | return 0; | |
433 | ||
434 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
435 | ||
8ea667f2 | 436 | if (!write_fault) |
0780516a | 437 | FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte); |
908e7d79 GN |
438 | else |
439 | /* | |
61719a8f GN |
440 | * On a write fault, fold the dirty bit into accessed_dirty. |
441 | * For modes without A/D bits support accessed_dirty will be | |
442 | * always clear. | |
908e7d79 | 443 | */ |
d8089bac GN |
444 | accessed_dirty &= pte >> |
445 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
446 | |
447 | if (unlikely(!accessed_dirty)) { | |
448 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
449 | if (unlikely(ret < 0)) | |
450 | goto error; | |
451 | else if (ret) | |
452 | goto retry_walk; | |
453 | } | |
42bf3f0a | 454 | |
fe135d2c | 455 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", |
0780516a | 456 | __func__, (u64)pte, walker->pte_access, walker->pt_access); |
7993ba43 AK |
457 | return 1; |
458 | ||
f59c1d2d | 459 | error: |
134291bf | 460 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
461 | if (fetch_fault && (mmu->nx || |
462 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 463 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 464 | |
134291bf TY |
465 | walker->fault.vector = PF_VECTOR; |
466 | walker->fault.error_code_valid = true; | |
467 | walker->fault.error_code = errcode; | |
25d92081 YZ |
468 | |
469 | #if PTTYPE == PTTYPE_EPT | |
470 | /* | |
471 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
472 | * misconfiguration requires to be injected. The detection is | |
473 | * done by is_rsvd_bits_set() above. | |
474 | * | |
475 | * We set up the value of exit_qualification to inject: | |
ddd6f0e9 KA |
476 | * [2:0] - Derive from the access bits. The exit_qualification might be |
477 | * out of date if it is serving an EPT misconfiguration. | |
25d92081 YZ |
478 | * [5:3] - Calculated by the page walk of the guest EPT page tables |
479 | * [7:8] - Derived from [7:8] of real exit_qualification | |
480 | * | |
481 | * The other bits are set to 0. | |
482 | */ | |
483 | if (!(errcode & PFERR_RSVD_MASK)) { | |
ddd6f0e9 KA |
484 | vcpu->arch.exit_qualification &= 0x180; |
485 | if (write_fault) | |
486 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE; | |
487 | if (user_fault) | |
488 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ; | |
489 | if (fetch_fault) | |
490 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR; | |
0780516a | 491 | vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3; |
25d92081 YZ |
492 | } |
493 | #endif | |
6389ee94 AK |
494 | walker->fault.address = addr; |
495 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 496 | |
8c28d031 | 497 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 498 | return 0; |
6aa8b732 AK |
499 | } |
500 | ||
1e301feb | 501 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 502 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb | 503 | { |
44dd3ffa | 504 | return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr, |
33770780 | 505 | access); |
1e301feb JR |
506 | } |
507 | ||
37406aaa | 508 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
509 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
510 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 511 | u32 access) |
6539e738 JR |
512 | { |
513 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 514 | addr, access); |
6539e738 | 515 | } |
37406aaa | 516 | #endif |
6539e738 | 517 | |
bd6360cc XG |
518 | static bool |
519 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
520 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 521 | { |
41074d07 | 522 | unsigned pte_access; |
bd6360cc | 523 | gfn_t gfn; |
ba049e93 | 524 | kvm_pfn_t pfn; |
0028425f | 525 | |
0ad805a0 | 526 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 527 | return false; |
407c61c6 | 528 | |
b8688d51 | 529 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
530 | |
531 | gfn = gpte_to_gfn(gpte); | |
42522d08 | 532 | pte_access = sp->role.access & FNAME(gpte_access)(gpte); |
44dd3ffa | 533 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
bd6360cc XG |
534 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
535 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 536 | if (is_error_pfn(pfn)) |
bd6360cc | 537 | return false; |
0f53b5b1 | 538 | |
1403283a | 539 | /* |
bd6360cc XG |
540 | * we call mmu_set_spte() with host_writable = true because |
541 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 542 | */ |
029499b4 TY |
543 | mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn, |
544 | true, true); | |
bd6360cc | 545 | |
43fdcda9 | 546 | kvm_release_pfn_clean(pfn); |
bd6360cc XG |
547 | return true; |
548 | } | |
549 | ||
550 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
551 | u64 *spte, const void *pte) | |
552 | { | |
553 | pt_element_t gpte = *(const pt_element_t *)pte; | |
554 | ||
555 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
556 | } |
557 | ||
39c8c672 AK |
558 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
559 | struct guest_walker *gw, int level) | |
560 | { | |
39c8c672 | 561 | pt_element_t curr_pte; |
189be38d XG |
562 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
563 | u64 mask; | |
564 | int r, index; | |
565 | ||
566 | if (level == PT_PAGE_TABLE_LEVEL) { | |
567 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
568 | base_gpa = pte_gpa & ~mask; | |
569 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
570 | ||
54bf36aa | 571 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
572 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
573 | curr_pte = gw->prefetch_ptes[index]; | |
574 | } else | |
54bf36aa | 575 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 576 | &curr_pte, sizeof(curr_pte)); |
189be38d | 577 | |
39c8c672 AK |
578 | return r || curr_pte != gw->ptes[level - 1]; |
579 | } | |
580 | ||
189be38d XG |
581 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
582 | u64 *sptep) | |
957ed9ef XG |
583 | { |
584 | struct kvm_mmu_page *sp; | |
189be38d | 585 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 586 | u64 *spte; |
189be38d | 587 | int i; |
957ed9ef XG |
588 | |
589 | sp = page_header(__pa(sptep)); | |
590 | ||
591 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
592 | return; | |
593 | ||
594 | if (sp->role.direct) | |
595 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
596 | ||
597 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
598 | spte = sp->spt + i; |
599 | ||
600 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
601 | if (spte == sptep) |
602 | continue; | |
603 | ||
c3707958 | 604 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
605 | continue; |
606 | ||
bd6360cc | 607 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 608 | break; |
957ed9ef XG |
609 | } |
610 | } | |
611 | ||
6aa8b732 AK |
612 | /* |
613 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
614 | * If the guest tries to write a write-protected page, we need to |
615 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 616 | */ |
d4878f24 | 617 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 618 | struct guest_walker *gw, |
c2288505 | 619 | int write_fault, int hlevel, |
ba049e93 | 620 | kvm_pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 621 | { |
5991b332 | 622 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 623 | struct kvm_shadow_walk_iterator it; |
d4878f24 | 624 | unsigned direct_access, access = gw->pt_access; |
9b8ebbdb | 625 | int top_level, ret; |
abb9e0b8 | 626 | |
b36c7a7c | 627 | direct_access = gw->pte_access; |
84754cd8 | 628 | |
44dd3ffa | 629 | top_level = vcpu->arch.mmu->root_level; |
5991b332 AK |
630 | if (top_level == PT32E_ROOT_LEVEL) |
631 | top_level = PT32_ROOT_LEVEL; | |
632 | /* | |
633 | * Verify that the top-level gpte is still there. Since the page | |
634 | * is a root page, it is either write protected (and cannot be | |
635 | * changed from now on) or it is invalid (in which case, we don't | |
636 | * really care if it changes underneath us after this point). | |
637 | */ | |
638 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
639 | goto out_gpte_changed; | |
640 | ||
44dd3ffa | 641 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
37f6a4e2 MT |
642 | goto out_gpte_changed; |
643 | ||
24157aaf AK |
644 | for (shadow_walk_init(&it, vcpu, addr); |
645 | shadow_walk_okay(&it) && it.level > gw->level; | |
646 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
647 | gfn_t table_gfn; |
648 | ||
a30f47cb | 649 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 650 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 651 | |
5991b332 | 652 | sp = NULL; |
24157aaf AK |
653 | if (!is_shadow_present_pte(*it.sptep)) { |
654 | table_gfn = gw->table_gfn[it.level - 2]; | |
655 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
bb11c6c9 | 656 | false, access); |
5991b332 | 657 | } |
0b3c9333 AK |
658 | |
659 | /* | |
660 | * Verify that the gpte in the page we've just write | |
661 | * protected is still there. | |
662 | */ | |
24157aaf | 663 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 664 | goto out_gpte_changed; |
abb9e0b8 | 665 | |
5991b332 | 666 | if (sp) |
98bba238 | 667 | link_shadow_page(vcpu, it.sptep, sp); |
e7a04c99 | 668 | } |
050e6499 | 669 | |
0b3c9333 | 670 | for (; |
24157aaf AK |
671 | shadow_walk_okay(&it) && it.level > hlevel; |
672 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
673 | gfn_t direct_gfn; |
674 | ||
a30f47cb | 675 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 676 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 677 | |
24157aaf | 678 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 679 | |
24157aaf | 680 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
681 | continue; |
682 | ||
24157aaf | 683 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 684 | |
24157aaf | 685 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
bb11c6c9 | 686 | true, direct_access); |
98bba238 | 687 | link_shadow_page(vcpu, it.sptep, sp); |
0b3c9333 AK |
688 | } |
689 | ||
a30f47cb | 690 | clear_sp_write_flooding_count(it.sptep); |
9b8ebbdb PB |
691 | ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, |
692 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 693 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 694 | |
9b8ebbdb | 695 | return ret; |
0b3c9333 AK |
696 | |
697 | out_gpte_changed: | |
9b8ebbdb | 698 | return RET_PF_RETRY; |
6aa8b732 AK |
699 | } |
700 | ||
7751babd XG |
701 | /* |
702 | * To see whether the mapped gfn can write its page table in the current | |
703 | * mapping. | |
704 | * | |
705 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
706 | * size to map the writable gfn which is used as current page table, we should | |
707 | * force kvm to use small page size to map it because new shadow page will be | |
708 | * created when kvm establishes shadow page table that stop kvm using large | |
709 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
710 | * | |
93c05d3e XG |
711 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
712 | * currently used as its page table. | |
713 | * | |
7751babd XG |
714 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
715 | * since the PDPT is always shadowed, that means, we can not use large page | |
716 | * size to map the gfn which is used as PDPT. | |
717 | */ | |
718 | static bool | |
719 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
720 | struct guest_walker *walker, int user_fault, |
721 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
722 | { |
723 | int level; | |
724 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 725 | bool self_changed = false; |
7751babd XG |
726 | |
727 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
728 | (!is_write_protection(vcpu) && !user_fault))) | |
729 | return false; | |
730 | ||
93c05d3e XG |
731 | for (level = walker->level; level <= walker->max_level; level++) { |
732 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
733 | ||
734 | self_changed |= !(gfn & mask); | |
735 | *write_fault_to_shadow_pgtable |= !gfn; | |
736 | } | |
7751babd | 737 | |
93c05d3e | 738 | return self_changed; |
7751babd XG |
739 | } |
740 | ||
6aa8b732 AK |
741 | /* |
742 | * Page fault handler. There are several causes for a page fault: | |
743 | * - there is no shadow pte for the guest pte | |
744 | * - write access through a shadow pte marked read only so that we can set | |
745 | * the dirty bit | |
746 | * - write access to a shadow pte marked read only so we can update the page | |
747 | * dirty bitmap, when userspace requests it | |
748 | * - mmio access; in this case we will never install a present shadow pte | |
749 | * - normal guest page fault due to the guest pte marked not present, not | |
750 | * writable, or not executable | |
751 | * | |
e2dec939 AK |
752 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
753 | * a negative value on error. | |
6aa8b732 | 754 | */ |
56028d08 | 755 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 756 | bool prefault) |
6aa8b732 AK |
757 | { |
758 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
759 | int user_fault = error_code & PFERR_USER_MASK; |
760 | struct guest_walker walker; | |
e2dec939 | 761 | int r; |
ba049e93 | 762 | kvm_pfn_t pfn; |
7e4e4056 | 763 | int level = PT_PAGE_TABLE_LEVEL; |
8c85ac1c | 764 | bool force_pt_level = false; |
e930bffe | 765 | unsigned long mmu_seq; |
93c05d3e | 766 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 767 | |
b8688d51 | 768 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 769 | |
e2dec939 AK |
770 | r = mmu_topup_memory_caches(vcpu); |
771 | if (r) | |
772 | return r; | |
714b93da | 773 | |
e9ee956e TY |
774 | /* |
775 | * If PFEC.RSVD is set, this is a shadow page fault. | |
776 | * The bit needs to be cleared before walking guest page tables. | |
777 | */ | |
778 | error_code &= ~PFERR_RSVD_MASK; | |
779 | ||
6aa8b732 | 780 | /* |
a8b876b1 | 781 | * Look up the guest pte for the faulting address. |
6aa8b732 | 782 | */ |
33770780 | 783 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
784 | |
785 | /* | |
786 | * The page is not mapped by the guest. Let the guest handle it. | |
787 | */ | |
7993ba43 | 788 | if (!r) { |
b8688d51 | 789 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 790 | if (!prefault) |
fb67e14f | 791 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 792 | |
9b8ebbdb | 793 | return RET_PF_RETRY; |
6aa8b732 AK |
794 | } |
795 | ||
e5691a81 XG |
796 | if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) { |
797 | shadow_page_table_clear_flood(vcpu, addr); | |
9b8ebbdb | 798 | return RET_PF_EMULATE; |
e5691a81 | 799 | } |
3d0c27ad | 800 | |
93c05d3e XG |
801 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
802 | ||
803 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
804 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
805 | ||
5ed5c5c8 | 806 | if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) { |
fd136902 TY |
807 | level = mapping_level(vcpu, walker.gfn, &force_pt_level); |
808 | if (likely(!force_pt_level)) { | |
809 | level = min(walker.level, level); | |
5ed5c5c8 TY |
810 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); |
811 | } | |
812 | } else | |
cd1872f0 | 813 | force_pt_level = true; |
7e4e4056 | 814 | |
e930bffe | 815 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 816 | smp_rmb(); |
af585b92 | 817 | |
78b2c54a | 818 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 819 | &map_writable)) |
9b8ebbdb | 820 | return RET_PF_RETRY; |
d7824fff | 821 | |
9034e6e8 | 822 | if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r)) |
d7c55201 XG |
823 | return r; |
824 | ||
c2288505 XG |
825 | /* |
826 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
827 | * we will cache the incorrect access into mmio spte. | |
828 | */ | |
829 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
830 | !is_write_protection(vcpu) && !user_fault && | |
831 | !is_noslot_pfn(pfn)) { | |
832 | walker.pte_access |= ACC_WRITE_MASK; | |
833 | walker.pte_access &= ~ACC_USER_MASK; | |
834 | ||
835 | /* | |
836 | * If we converted a user page to a kernel page, | |
837 | * so that the kernel can write to it when cr0.wp=0, | |
838 | * then we should prevent the kernel from executing it | |
839 | * if SMEP is enabled. | |
840 | */ | |
841 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
842 | walker.pte_access &= ~ACC_EXEC_MASK; | |
843 | } | |
844 | ||
43fdcda9 | 845 | r = RET_PF_RETRY; |
aaee2c94 | 846 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 847 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 848 | goto out_unlock; |
bc32ce21 | 849 | |
0375f7fa | 850 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
26eeb53c WL |
851 | if (make_mmu_pages_available(vcpu) < 0) |
852 | goto out_unlock; | |
936a5fe6 AA |
853 | if (!force_pt_level) |
854 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 855 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 856 | level, pfn, map_writable, prefault); |
1165f5fe | 857 | ++vcpu->stat.pf_fixed; |
0375f7fa | 858 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
e930bffe AA |
859 | |
860 | out_unlock: | |
861 | spin_unlock(&vcpu->kvm->mmu_lock); | |
862 | kvm_release_pfn_clean(pfn); | |
43fdcda9 | 863 | return r; |
6aa8b732 AK |
864 | } |
865 | ||
505aef8f XG |
866 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
867 | { | |
868 | int offset = 0; | |
869 | ||
f71fa31f | 870 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
871 | |
872 | if (PTTYPE == 32) | |
873 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
874 | ||
875 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
876 | } | |
877 | ||
7eb77e9f | 878 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa) |
a7052897 | 879 | { |
a461930b | 880 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 881 | struct kvm_mmu_page *sp; |
a461930b AK |
882 | int level; |
883 | u64 *sptep; | |
884 | ||
bebb106a XG |
885 | vcpu_clear_mmio_info(vcpu, gva); |
886 | ||
f57f2ef5 XG |
887 | /* |
888 | * No need to check return value here, rmap_can_add() can | |
889 | * help us to skip pte prefetch later. | |
890 | */ | |
891 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 892 | |
7eb77e9f | 893 | if (!VALID_PAGE(root_hpa)) { |
37f6a4e2 MT |
894 | WARN_ON(1); |
895 | return; | |
896 | } | |
897 | ||
f57f2ef5 | 898 | spin_lock(&vcpu->kvm->mmu_lock); |
7eb77e9f | 899 | for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) { |
a461930b AK |
900 | level = iterator.level; |
901 | sptep = iterator.sptep; | |
ad218f85 | 902 | |
f78978aa | 903 | sp = page_header(__pa(sptep)); |
884a0ff0 | 904 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
905 | pt_element_t gpte; |
906 | gpa_t pte_gpa; | |
907 | ||
f78978aa XG |
908 | if (!sp->unsync) |
909 | break; | |
910 | ||
505aef8f | 911 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 912 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 913 | |
505aef8f | 914 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
c3134ce2 LT |
915 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, |
916 | sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level)); | |
f57f2ef5 XG |
917 | |
918 | if (!rmap_can_add(vcpu)) | |
919 | break; | |
920 | ||
54bf36aa PB |
921 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
922 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
923 | break; |
924 | ||
925 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 926 | } |
a7052897 | 927 | |
f78978aa | 928 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
929 | break; |
930 | } | |
ad218f85 | 931 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
932 | } |
933 | ||
1871c602 | 934 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 935 | struct x86_exception *exception) |
6aa8b732 AK |
936 | { |
937 | struct guest_walker walker; | |
e119d117 AK |
938 | gpa_t gpa = UNMAPPED_GVA; |
939 | int r; | |
6aa8b732 | 940 | |
33770780 | 941 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 942 | |
e119d117 | 943 | if (r) { |
1755fbcc | 944 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 945 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
946 | } else if (exception) |
947 | *exception = walker.fault; | |
6aa8b732 AK |
948 | |
949 | return gpa; | |
950 | } | |
951 | ||
37406aaa | 952 | #if PTTYPE != PTTYPE_EPT |
6539e738 | 953 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
954 | u32 access, |
955 | struct x86_exception *exception) | |
6539e738 JR |
956 | { |
957 | struct guest_walker walker; | |
958 | gpa_t gpa = UNMAPPED_GVA; | |
959 | int r; | |
960 | ||
33770780 | 961 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
962 | |
963 | if (r) { | |
964 | gpa = gfn_to_gpa(walker.gfn); | |
965 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
966 | } else if (exception) |
967 | *exception = walker.fault; | |
6539e738 JR |
968 | |
969 | return gpa; | |
970 | } | |
37406aaa | 971 | #endif |
6539e738 | 972 | |
e8bc217a MT |
973 | /* |
974 | * Using the cached information from sp->gfns is safe because: | |
975 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
976 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
977 | * |
978 | * Note: | |
979 | * We should flush all tlbs if spte is dropped even though guest is | |
980 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
981 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
982 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
983 | * freed pages. | |
a086f6a1 | 984 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 985 | */ |
a4a8e6f7 | 986 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 987 | { |
505aef8f | 988 | int i, nr_present = 0; |
9bdbba13 | 989 | bool host_writable; |
51fb60d8 | 990 | gpa_t first_pte_gpa; |
5ce4786f | 991 | int set_spte_ret = 0; |
e8bc217a | 992 | |
2032a93d LJ |
993 | /* direct kvm_mmu_page can not be unsync. */ |
994 | BUG_ON(sp->role.direct); | |
995 | ||
505aef8f | 996 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 997 | |
e8bc217a MT |
998 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
999 | unsigned pte_access; | |
1000 | pt_element_t gpte; | |
1001 | gpa_t pte_gpa; | |
f55c3f41 | 1002 | gfn_t gfn; |
e8bc217a | 1003 | |
ce88decf | 1004 | if (!sp->spt[i]) |
e8bc217a MT |
1005 | continue; |
1006 | ||
51fb60d8 | 1007 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 1008 | |
54bf36aa PB |
1009 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
1010 | sizeof(pt_element_t))) | |
1f50f1b3 | 1011 | return 0; |
e8bc217a | 1012 | |
0ad805a0 | 1013 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
7bfdf217 LT |
1014 | /* |
1015 | * Update spte before increasing tlbs_dirty to make | |
1016 | * sure no tlb flush is lost after spte is zapped; see | |
1017 | * the comments in kvm_flush_remote_tlbs(). | |
1018 | */ | |
1019 | smp_wmb(); | |
a086f6a1 | 1020 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
1021 | continue; |
1022 | } | |
1023 | ||
ce88decf XG |
1024 | gfn = gpte_to_gfn(gpte); |
1025 | pte_access = sp->role.access; | |
42522d08 | 1026 | pte_access &= FNAME(gpte_access)(gpte); |
44dd3ffa | 1027 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
ce88decf | 1028 | |
54bf36aa | 1029 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 1030 | &nr_present)) |
ce88decf XG |
1031 | continue; |
1032 | ||
407c61c6 | 1033 | if (gfn != sp->gfns[i]) { |
c3707958 | 1034 | drop_spte(vcpu->kvm, &sp->spt[i]); |
7bfdf217 LT |
1035 | /* |
1036 | * The same as above where we are doing | |
1037 | * prefetch_invalid_gpte(). | |
1038 | */ | |
1039 | smp_wmb(); | |
a086f6a1 | 1040 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
1041 | continue; |
1042 | } | |
1043 | ||
1044 | nr_present++; | |
ce88decf | 1045 | |
f8e453b0 XG |
1046 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
1047 | ||
5ce4786f JS |
1048 | set_spte_ret |= set_spte(vcpu, &sp->spt[i], |
1049 | pte_access, PT_PAGE_TABLE_LEVEL, | |
1050 | gfn, spte_to_pfn(sp->spt[i]), | |
1051 | true, false, host_writable); | |
e8bc217a MT |
1052 | } |
1053 | ||
5ce4786f JS |
1054 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH) |
1055 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1056 | ||
1f50f1b3 | 1057 | return nr_present; |
e8bc217a MT |
1058 | } |
1059 | ||
6aa8b732 AK |
1060 | #undef pt_element_t |
1061 | #undef guest_walker | |
1062 | #undef FNAME | |
1063 | #undef PT_BASE_ADDR_MASK | |
1064 | #undef PT_INDEX | |
e04da980 JR |
1065 | #undef PT_LVL_ADDR_MASK |
1066 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 1067 | #undef PT_LEVEL_BITS |
cea0f0e7 | 1068 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 1069 | #undef gpte_to_gfn |
e04da980 | 1070 | #undef gpte_to_gfn_lvl |
b3e4e63f | 1071 | #undef CMPXCHG |
d8089bac GN |
1072 | #undef PT_GUEST_ACCESSED_MASK |
1073 | #undef PT_GUEST_DIRTY_MASK | |
1074 | #undef PT_GUEST_DIRTY_SHIFT | |
1075 | #undef PT_GUEST_ACCESSED_SHIFT | |
86407bcb | 1076 | #undef PT_HAVE_ACCESSED_DIRTY |