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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
37406aaa NHE |
26 | /* |
27 | * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro | |
28 | * uses for EPT without A/D paging type. | |
29 | */ | |
30 | extern u64 __pure __using_nonexistent_pte_bit(void) | |
31 | __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT"); | |
32 | ||
6aa8b732 AK |
33 | #if PTTYPE == 64 |
34 | #define pt_element_t u64 | |
35 | #define guest_walker guest_walker64 | |
36 | #define FNAME(name) paging##64_##name | |
37 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
38 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
39 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 40 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 41 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
42 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
43 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
44 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
45 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
cea0f0e7 AK |
46 | #ifdef CONFIG_X86_64 |
47 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 48 | #define CMPXCHG cmpxchg |
cea0f0e7 | 49 | #else |
b3e4e63f | 50 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
51 | #define PT_MAX_FULL_LEVELS 2 |
52 | #endif | |
6aa8b732 AK |
53 | #elif PTTYPE == 32 |
54 | #define pt_element_t u32 | |
55 | #define guest_walker guest_walker32 | |
56 | #define FNAME(name) paging##32_##name | |
57 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
58 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
59 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 60 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 61 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 62 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
63 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
64 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
65 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
66 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
b3e4e63f | 67 | #define CMPXCHG cmpxchg |
37406aaa NHE |
68 | #elif PTTYPE == PTTYPE_EPT |
69 | #define pt_element_t u64 | |
70 | #define guest_walker guest_walkerEPT | |
71 | #define FNAME(name) ept_##name | |
72 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
73 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
74 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
75 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
76 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
77 | #define PT_GUEST_ACCESSED_MASK 0 | |
78 | #define PT_GUEST_DIRTY_MASK 0 | |
79 | #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit() | |
80 | #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit() | |
81 | #define CMPXCHG cmpxchg64 | |
82 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
83 | #else |
84 | #error Invalid PTTYPE value | |
85 | #endif | |
86 | ||
e04da980 JR |
87 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
88 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 89 | |
6aa8b732 AK |
90 | /* |
91 | * The guest_walker structure emulates the behavior of the hardware page | |
92 | * table walker. | |
93 | */ | |
94 | struct guest_walker { | |
95 | int level; | |
8cbc7069 | 96 | unsigned max_level; |
cea0f0e7 | 97 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 98 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 99 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 100 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 101 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 102 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
103 | unsigned pt_access; |
104 | unsigned pte_access; | |
815af8d4 | 105 | gfn_t gfn; |
8c28d031 | 106 | struct x86_exception fault; |
6aa8b732 AK |
107 | }; |
108 | ||
e04da980 | 109 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 110 | { |
e04da980 | 111 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
112 | } |
113 | ||
0ad805a0 NHE |
114 | static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte) |
115 | { | |
116 | unsigned mask; | |
117 | ||
61719a8f GN |
118 | /* dirty bit is not supported, so no need to track it */ |
119 | if (!PT_GUEST_DIRTY_MASK) | |
120 | return; | |
121 | ||
0ad805a0 NHE |
122 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
123 | ||
124 | mask = (unsigned)~ACC_WRITE_MASK; | |
125 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
126 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
127 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
128 | *access &= mask; |
129 | } | |
130 | ||
0ad805a0 NHE |
131 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
132 | { | |
37406aaa | 133 | #if PTTYPE != PTTYPE_EPT |
0ad805a0 | 134 | return is_present_gpte(pte); |
37406aaa NHE |
135 | #else |
136 | return pte & 7; | |
137 | #endif | |
0ad805a0 NHE |
138 | } |
139 | ||
a78484c6 | 140 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
141 | pt_element_t __user *ptep_user, unsigned index, |
142 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 143 | { |
c8cfbb55 | 144 | int npages; |
b3e4e63f MT |
145 | pt_element_t ret; |
146 | pt_element_t *table; | |
147 | struct page *page; | |
148 | ||
c8cfbb55 TY |
149 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
150 | /* Check if the user is doing something meaningless. */ | |
151 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
152 | return -EFAULT; |
153 | ||
8fd75e12 | 154 | table = kmap_atomic(page); |
b3e4e63f | 155 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 156 | kunmap_atomic(table); |
b3e4e63f MT |
157 | |
158 | kvm_release_page_dirty(page); | |
159 | ||
160 | return (ret != orig_pte); | |
161 | } | |
162 | ||
0ad805a0 NHE |
163 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
164 | struct kvm_mmu_page *sp, u64 *spte, | |
165 | u64 gpte) | |
166 | { | |
d2b0f981 | 167 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
0ad805a0 NHE |
168 | goto no_present; |
169 | ||
170 | if (!FNAME(is_present_gpte)(gpte)) | |
171 | goto no_present; | |
172 | ||
61719a8f GN |
173 | /* if accessed bit is not supported prefetch non accessed gpte */ |
174 | if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
175 | goto no_present; |
176 | ||
177 | return false; | |
178 | ||
179 | no_present: | |
180 | drop_spte(vcpu->kvm, spte); | |
181 | return true; | |
182 | } | |
183 | ||
184 | static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte) | |
185 | { | |
186 | unsigned access; | |
37406aaa NHE |
187 | #if PTTYPE == PTTYPE_EPT |
188 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
189 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
190 | ACC_USER_MASK; | |
191 | #else | |
0ad805a0 NHE |
192 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; |
193 | access &= ~(gpte >> PT64_NX_SHIFT); | |
37406aaa | 194 | #endif |
0ad805a0 NHE |
195 | |
196 | return access; | |
197 | } | |
198 | ||
8cbc7069 AK |
199 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
200 | struct kvm_mmu *mmu, | |
201 | struct guest_walker *walker, | |
202 | int write_fault) | |
203 | { | |
204 | unsigned level, index; | |
205 | pt_element_t pte, orig_pte; | |
206 | pt_element_t __user *ptep_user; | |
207 | gfn_t table_gfn; | |
208 | int ret; | |
209 | ||
61719a8f GN |
210 | /* dirty/accessed bits are not supported, so no need to update them */ |
211 | if (!PT_GUEST_DIRTY_MASK) | |
212 | return 0; | |
213 | ||
8cbc7069 AK |
214 | for (level = walker->max_level; level >= walker->level; --level) { |
215 | pte = orig_pte = walker->ptes[level - 1]; | |
216 | table_gfn = walker->table_gfn[level - 1]; | |
217 | ptep_user = walker->ptep_user[level - 1]; | |
218 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 219 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 220 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 221 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 222 | } |
0ad805a0 | 223 | if (level == walker->level && write_fault && |
d8089bac | 224 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 225 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 226 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
227 | } |
228 | if (pte == orig_pte) | |
229 | continue; | |
230 | ||
ba6a3541 PB |
231 | /* |
232 | * If the slot is read-only, simply do not process the accessed | |
233 | * and dirty bits. This is the correct thing to do if the slot | |
234 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
235 | * are only supported if the accessed and dirty bits are already | |
236 | * set in the ROM (so that MMIO writes are never needed). | |
237 | * | |
238 | * Note that NPT does not allow this at all and faults, since | |
239 | * it always wants nested page table entries for the guest | |
240 | * page tables to be writable. And EPT works but will simply | |
241 | * overwrite the read-only memory to set the accessed and dirty | |
242 | * bits. | |
243 | */ | |
244 | if (unlikely(!walker->pte_writable[level - 1])) | |
245 | continue; | |
246 | ||
8cbc7069 AK |
247 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
248 | if (ret) | |
249 | return ret; | |
250 | ||
54bf36aa | 251 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
8cbc7069 AK |
252 | walker->ptes[level] = pte; |
253 | } | |
254 | return 0; | |
255 | } | |
256 | ||
ac79c978 AK |
257 | /* |
258 | * Fetch a guest pte for a guest virtual address | |
259 | */ | |
1e301feb JR |
260 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
261 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 262 | gva_t addr, u32 access) |
6aa8b732 | 263 | { |
8cbc7069 | 264 | int ret; |
42bf3f0a | 265 | pt_element_t pte; |
b7233635 | 266 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 267 | gfn_t table_gfn; |
b0cfeb5d | 268 | unsigned index, pt_access, pte_access, accessed_dirty; |
42bf3f0a | 269 | gpa_t pte_gpa; |
134291bf TY |
270 | int offset; |
271 | const int write_fault = access & PFERR_WRITE_MASK; | |
272 | const int user_fault = access & PFERR_USER_MASK; | |
273 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
274 | u16 errcode = 0; | |
13d22b6a AK |
275 | gpa_t real_gpa; |
276 | gfn_t gfn; | |
6aa8b732 | 277 | |
6fbc2770 | 278 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 279 | retry_walk: |
1e301feb JR |
280 | walker->level = mmu->root_level; |
281 | pte = mmu->get_cr3(vcpu); | |
282 | ||
1b0973bd | 283 | #if PTTYPE == 64 |
1e301feb | 284 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 285 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 286 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 287 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 288 | goto error; |
1b0973bd AK |
289 | --walker->level; |
290 | } | |
291 | #endif | |
8cbc7069 | 292 | walker->max_level = walker->level; |
1715d0dc | 293 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 294 | |
d8089bac | 295 | accessed_dirty = PT_GUEST_ACCESSED_MASK; |
13d22b6a AK |
296 | pt_access = pte_access = ACC_ALL; |
297 | ++walker->level; | |
ac79c978 | 298 | |
13d22b6a | 299 | do { |
6e2ca7d1 TY |
300 | gfn_t real_gfn; |
301 | unsigned long host_addr; | |
302 | ||
13d22b6a AK |
303 | pt_access &= pte_access; |
304 | --walker->level; | |
305 | ||
42bf3f0a | 306 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 307 | |
5fb07ddb | 308 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
309 | offset = index * sizeof(pt_element_t); |
310 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 311 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 312 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 313 | |
6e2ca7d1 | 314 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
54987b7a PB |
315 | PFERR_USER_MASK|PFERR_WRITE_MASK, |
316 | &walker->fault); | |
5e352519 PB |
317 | |
318 | /* | |
319 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
320 | * instruction) triggers a nested page fault. The exit | |
321 | * qualification / exit info field will incorrectly have | |
322 | * "guest page access" as the nested page fault's cause, | |
323 | * instead of "guest page structure access". To fix this, | |
324 | * the x86_exception struct should be augmented with enough | |
325 | * information to fix the exit_qualification or exit_info_1 | |
326 | * fields. | |
327 | */ | |
134291bf | 328 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
54987b7a | 329 | return 0; |
5e352519 | 330 | |
6e2ca7d1 TY |
331 | real_gfn = gpa_to_gfn(real_gfn); |
332 | ||
54bf36aa | 333 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn, |
ba6a3541 | 334 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
335 | if (unlikely(kvm_is_error_hva(host_addr))) |
336 | goto error; | |
6e2ca7d1 TY |
337 | |
338 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
339 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
340 | goto error; | |
8cbc7069 | 341 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 342 | |
07420171 | 343 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 344 | |
0ad805a0 | 345 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 346 | goto error; |
7993ba43 | 347 | |
d2b0f981 | 348 | if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) { |
134291bf TY |
349 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
350 | goto error; | |
f59c1d2d | 351 | } |
82725b20 | 352 | |
b514c30f | 353 | accessed_dirty &= pte; |
0ad805a0 | 354 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
73b1087e | 355 | |
7819026e | 356 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 357 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 358 | |
97ec8c06 | 359 | if (unlikely(permission_fault(vcpu, mmu, pte_access, access))) { |
134291bf | 360 | errcode |= PFERR_PRESENT_MASK; |
f59c1d2d | 361 | goto error; |
134291bf | 362 | } |
f59c1d2d | 363 | |
13d22b6a AK |
364 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
365 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
366 | ||
367 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
368 | gfn += pse36_gfn_delta(pte); | |
369 | ||
54987b7a | 370 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
371 | if (real_gpa == UNMAPPED_GVA) |
372 | return 0; | |
373 | ||
374 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
375 | ||
8ea667f2 | 376 | if (!write_fault) |
0ad805a0 | 377 | FNAME(protect_clean_gpte)(&pte_access, pte); |
908e7d79 GN |
378 | else |
379 | /* | |
61719a8f GN |
380 | * On a write fault, fold the dirty bit into accessed_dirty. |
381 | * For modes without A/D bits support accessed_dirty will be | |
382 | * always clear. | |
908e7d79 | 383 | */ |
d8089bac GN |
384 | accessed_dirty &= pte >> |
385 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
386 | |
387 | if (unlikely(!accessed_dirty)) { | |
388 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
389 | if (unlikely(ret < 0)) | |
390 | goto error; | |
391 | else if (ret) | |
392 | goto retry_walk; | |
393 | } | |
42bf3f0a | 394 | |
fe135d2c AK |
395 | walker->pt_access = pt_access; |
396 | walker->pte_access = pte_access; | |
397 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 398 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
399 | return 1; |
400 | ||
f59c1d2d | 401 | error: |
134291bf | 402 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
403 | if (fetch_fault && (mmu->nx || |
404 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 405 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 406 | |
134291bf TY |
407 | walker->fault.vector = PF_VECTOR; |
408 | walker->fault.error_code_valid = true; | |
409 | walker->fault.error_code = errcode; | |
25d92081 YZ |
410 | |
411 | #if PTTYPE == PTTYPE_EPT | |
412 | /* | |
413 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
414 | * misconfiguration requires to be injected. The detection is | |
415 | * done by is_rsvd_bits_set() above. | |
416 | * | |
417 | * We set up the value of exit_qualification to inject: | |
418 | * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation | |
419 | * [5:3] - Calculated by the page walk of the guest EPT page tables | |
420 | * [7:8] - Derived from [7:8] of real exit_qualification | |
421 | * | |
422 | * The other bits are set to 0. | |
423 | */ | |
424 | if (!(errcode & PFERR_RSVD_MASK)) { | |
425 | vcpu->arch.exit_qualification &= 0x187; | |
426 | vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3; | |
427 | } | |
428 | #endif | |
6389ee94 AK |
429 | walker->fault.address = addr; |
430 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 431 | |
8c28d031 | 432 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 433 | return 0; |
6aa8b732 AK |
434 | } |
435 | ||
1e301feb | 436 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 437 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
438 | { |
439 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 440 | access); |
1e301feb JR |
441 | } |
442 | ||
37406aaa | 443 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
444 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
445 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 446 | u32 access) |
6539e738 JR |
447 | { |
448 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 449 | addr, access); |
6539e738 | 450 | } |
37406aaa | 451 | #endif |
6539e738 | 452 | |
bd6360cc XG |
453 | static bool |
454 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
455 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 456 | { |
41074d07 | 457 | unsigned pte_access; |
bd6360cc | 458 | gfn_t gfn; |
35149e21 | 459 | pfn_t pfn; |
0028425f | 460 | |
0ad805a0 | 461 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 462 | return false; |
407c61c6 | 463 | |
b8688d51 | 464 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
465 | |
466 | gfn = gpte_to_gfn(gpte); | |
0ad805a0 NHE |
467 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
468 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
bd6360cc XG |
469 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
470 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 471 | if (is_error_pfn(pfn)) |
bd6360cc | 472 | return false; |
0f53b5b1 | 473 | |
1403283a | 474 | /* |
bd6360cc XG |
475 | * we call mmu_set_spte() with host_writable = true because |
476 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 477 | */ |
f7616203 XG |
478 | mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL, |
479 | gfn, pfn, true, true); | |
bd6360cc XG |
480 | |
481 | return true; | |
482 | } | |
483 | ||
484 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
485 | u64 *spte, const void *pte) | |
486 | { | |
487 | pt_element_t gpte = *(const pt_element_t *)pte; | |
488 | ||
489 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
490 | } |
491 | ||
39c8c672 AK |
492 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
493 | struct guest_walker *gw, int level) | |
494 | { | |
39c8c672 | 495 | pt_element_t curr_pte; |
189be38d XG |
496 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
497 | u64 mask; | |
498 | int r, index; | |
499 | ||
500 | if (level == PT_PAGE_TABLE_LEVEL) { | |
501 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
502 | base_gpa = pte_gpa & ~mask; | |
503 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
504 | ||
54bf36aa | 505 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
506 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
507 | curr_pte = gw->prefetch_ptes[index]; | |
508 | } else | |
54bf36aa | 509 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 510 | &curr_pte, sizeof(curr_pte)); |
189be38d | 511 | |
39c8c672 AK |
512 | return r || curr_pte != gw->ptes[level - 1]; |
513 | } | |
514 | ||
189be38d XG |
515 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
516 | u64 *sptep) | |
957ed9ef XG |
517 | { |
518 | struct kvm_mmu_page *sp; | |
189be38d | 519 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 520 | u64 *spte; |
189be38d | 521 | int i; |
957ed9ef XG |
522 | |
523 | sp = page_header(__pa(sptep)); | |
524 | ||
525 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
526 | return; | |
527 | ||
528 | if (sp->role.direct) | |
529 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
530 | ||
531 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
532 | spte = sp->spt + i; |
533 | ||
534 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
535 | if (spte == sptep) |
536 | continue; | |
537 | ||
c3707958 | 538 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
539 | continue; |
540 | ||
bd6360cc | 541 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 542 | break; |
957ed9ef XG |
543 | } |
544 | } | |
545 | ||
6aa8b732 AK |
546 | /* |
547 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
548 | * If the guest tries to write a write-protected page, we need to |
549 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 550 | */ |
d4878f24 | 551 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 552 | struct guest_walker *gw, |
c2288505 | 553 | int write_fault, int hlevel, |
d4878f24 | 554 | pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 555 | { |
5991b332 | 556 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 557 | struct kvm_shadow_walk_iterator it; |
d4878f24 XG |
558 | unsigned direct_access, access = gw->pt_access; |
559 | int top_level, emulate = 0; | |
abb9e0b8 | 560 | |
b36c7a7c | 561 | direct_access = gw->pte_access; |
84754cd8 | 562 | |
5991b332 AK |
563 | top_level = vcpu->arch.mmu.root_level; |
564 | if (top_level == PT32E_ROOT_LEVEL) | |
565 | top_level = PT32_ROOT_LEVEL; | |
566 | /* | |
567 | * Verify that the top-level gpte is still there. Since the page | |
568 | * is a root page, it is either write protected (and cannot be | |
569 | * changed from now on) or it is invalid (in which case, we don't | |
570 | * really care if it changes underneath us after this point). | |
571 | */ | |
572 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
573 | goto out_gpte_changed; | |
574 | ||
37f6a4e2 MT |
575 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
576 | goto out_gpte_changed; | |
577 | ||
24157aaf AK |
578 | for (shadow_walk_init(&it, vcpu, addr); |
579 | shadow_walk_okay(&it) && it.level > gw->level; | |
580 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
581 | gfn_t table_gfn; |
582 | ||
a30f47cb | 583 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 584 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 585 | |
5991b332 | 586 | sp = NULL; |
24157aaf AK |
587 | if (!is_shadow_present_pte(*it.sptep)) { |
588 | table_gfn = gw->table_gfn[it.level - 2]; | |
589 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
590 | false, access, it.sptep); | |
5991b332 | 591 | } |
0b3c9333 AK |
592 | |
593 | /* | |
594 | * Verify that the gpte in the page we've just write | |
595 | * protected is still there. | |
596 | */ | |
24157aaf | 597 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 598 | goto out_gpte_changed; |
abb9e0b8 | 599 | |
5991b332 | 600 | if (sp) |
7a1638ce | 601 | link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK); |
e7a04c99 | 602 | } |
050e6499 | 603 | |
0b3c9333 | 604 | for (; |
24157aaf AK |
605 | shadow_walk_okay(&it) && it.level > hlevel; |
606 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
607 | gfn_t direct_gfn; |
608 | ||
a30f47cb | 609 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 610 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 611 | |
24157aaf | 612 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 613 | |
24157aaf | 614 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
615 | continue; |
616 | ||
24157aaf | 617 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 618 | |
24157aaf AK |
619 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
620 | true, direct_access, it.sptep); | |
7a1638ce | 621 | link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK); |
0b3c9333 AK |
622 | } |
623 | ||
a30f47cb | 624 | clear_sp_write_flooding_count(it.sptep); |
f7616203 XG |
625 | mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate, |
626 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 627 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 628 | |
d4878f24 | 629 | return emulate; |
0b3c9333 AK |
630 | |
631 | out_gpte_changed: | |
5991b332 | 632 | if (sp) |
24157aaf | 633 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 | 634 | kvm_release_pfn_clean(pfn); |
d4878f24 | 635 | return 0; |
6aa8b732 AK |
636 | } |
637 | ||
7751babd XG |
638 | /* |
639 | * To see whether the mapped gfn can write its page table in the current | |
640 | * mapping. | |
641 | * | |
642 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
643 | * size to map the writable gfn which is used as current page table, we should | |
644 | * force kvm to use small page size to map it because new shadow page will be | |
645 | * created when kvm establishes shadow page table that stop kvm using large | |
646 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
647 | * | |
93c05d3e XG |
648 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
649 | * currently used as its page table. | |
650 | * | |
7751babd XG |
651 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
652 | * since the PDPT is always shadowed, that means, we can not use large page | |
653 | * size to map the gfn which is used as PDPT. | |
654 | */ | |
655 | static bool | |
656 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
657 | struct guest_walker *walker, int user_fault, |
658 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
659 | { |
660 | int level; | |
661 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 662 | bool self_changed = false; |
7751babd XG |
663 | |
664 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
665 | (!is_write_protection(vcpu) && !user_fault))) | |
666 | return false; | |
667 | ||
93c05d3e XG |
668 | for (level = walker->level; level <= walker->max_level; level++) { |
669 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
670 | ||
671 | self_changed |= !(gfn & mask); | |
672 | *write_fault_to_shadow_pgtable |= !gfn; | |
673 | } | |
7751babd | 674 | |
93c05d3e | 675 | return self_changed; |
7751babd XG |
676 | } |
677 | ||
6aa8b732 AK |
678 | /* |
679 | * Page fault handler. There are several causes for a page fault: | |
680 | * - there is no shadow pte for the guest pte | |
681 | * - write access through a shadow pte marked read only so that we can set | |
682 | * the dirty bit | |
683 | * - write access to a shadow pte marked read only so we can update the page | |
684 | * dirty bitmap, when userspace requests it | |
685 | * - mmio access; in this case we will never install a present shadow pte | |
686 | * - normal guest page fault due to the guest pte marked not present, not | |
687 | * writable, or not executable | |
688 | * | |
e2dec939 AK |
689 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
690 | * a negative value on error. | |
6aa8b732 | 691 | */ |
56028d08 | 692 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 693 | bool prefault) |
6aa8b732 AK |
694 | { |
695 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
696 | int user_fault = error_code & PFERR_USER_MASK; |
697 | struct guest_walker walker; | |
e2dec939 | 698 | int r; |
35149e21 | 699 | pfn_t pfn; |
7e4e4056 | 700 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 701 | int force_pt_level; |
e930bffe | 702 | unsigned long mmu_seq; |
93c05d3e | 703 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 704 | |
b8688d51 | 705 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 706 | |
f8f55942 XG |
707 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
708 | r = handle_mmio_page_fault(vcpu, addr, error_code, | |
ce88decf | 709 | mmu_is_nested(vcpu)); |
f8f55942 XG |
710 | if (likely(r != RET_MMIO_PF_INVALID)) |
711 | return r; | |
ceee7df7 XG |
712 | |
713 | /* | |
714 | * page fault with PFEC.RSVD = 1 is caused by shadow | |
715 | * page fault, should not be used to walk guest page | |
716 | * table. | |
717 | */ | |
718 | error_code &= ~PFERR_RSVD_MASK; | |
f8f55942 | 719 | }; |
ce88decf | 720 | |
e2dec939 AK |
721 | r = mmu_topup_memory_caches(vcpu); |
722 | if (r) | |
723 | return r; | |
714b93da | 724 | |
6aa8b732 | 725 | /* |
a8b876b1 | 726 | * Look up the guest pte for the faulting address. |
6aa8b732 | 727 | */ |
33770780 | 728 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
729 | |
730 | /* | |
731 | * The page is not mapped by the guest. Let the guest handle it. | |
732 | */ | |
7993ba43 | 733 | if (!r) { |
b8688d51 | 734 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 735 | if (!prefault) |
fb67e14f | 736 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 737 | |
6aa8b732 AK |
738 | return 0; |
739 | } | |
740 | ||
93c05d3e XG |
741 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
742 | ||
743 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
744 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
745 | ||
936a5fe6 | 746 | if (walker.level >= PT_DIRECTORY_LEVEL) |
7751babd | 747 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn) |
93c05d3e | 748 | || is_self_change_mapping; |
936a5fe6 AA |
749 | else |
750 | force_pt_level = 1; | |
751 | if (!force_pt_level) { | |
7e4e4056 JR |
752 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
753 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 754 | } |
7e4e4056 | 755 | |
e930bffe | 756 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 757 | smp_rmb(); |
af585b92 | 758 | |
78b2c54a | 759 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 760 | &map_writable)) |
af585b92 | 761 | return 0; |
d7824fff | 762 | |
d7c55201 XG |
763 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
764 | walker.gfn, pfn, walker.pte_access, &r)) | |
765 | return r; | |
766 | ||
c2288505 XG |
767 | /* |
768 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
769 | * we will cache the incorrect access into mmio spte. | |
770 | */ | |
771 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
772 | !is_write_protection(vcpu) && !user_fault && | |
773 | !is_noslot_pfn(pfn)) { | |
774 | walker.pte_access |= ACC_WRITE_MASK; | |
775 | walker.pte_access &= ~ACC_USER_MASK; | |
776 | ||
777 | /* | |
778 | * If we converted a user page to a kernel page, | |
779 | * so that the kernel can write to it when cr0.wp=0, | |
780 | * then we should prevent the kernel from executing it | |
781 | * if SMEP is enabled. | |
782 | */ | |
783 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
784 | walker.pte_access &= ~ACC_EXEC_MASK; | |
785 | } | |
786 | ||
aaee2c94 | 787 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 788 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 789 | goto out_unlock; |
bc32ce21 | 790 | |
0375f7fa | 791 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
450e0b41 | 792 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
793 | if (!force_pt_level) |
794 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 795 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 796 | level, pfn, map_writable, prefault); |
1165f5fe | 797 | ++vcpu->stat.pf_fixed; |
0375f7fa | 798 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 799 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 800 | |
d4878f24 | 801 | return r; |
e930bffe AA |
802 | |
803 | out_unlock: | |
804 | spin_unlock(&vcpu->kvm->mmu_lock); | |
805 | kvm_release_pfn_clean(pfn); | |
806 | return 0; | |
6aa8b732 AK |
807 | } |
808 | ||
505aef8f XG |
809 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
810 | { | |
811 | int offset = 0; | |
812 | ||
f71fa31f | 813 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
814 | |
815 | if (PTTYPE == 32) | |
816 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
817 | ||
818 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
819 | } | |
820 | ||
a461930b | 821 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 822 | { |
a461930b | 823 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 824 | struct kvm_mmu_page *sp; |
a461930b AK |
825 | int level; |
826 | u64 *sptep; | |
827 | ||
bebb106a XG |
828 | vcpu_clear_mmio_info(vcpu, gva); |
829 | ||
f57f2ef5 XG |
830 | /* |
831 | * No need to check return value here, rmap_can_add() can | |
832 | * help us to skip pte prefetch later. | |
833 | */ | |
834 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 835 | |
37f6a4e2 MT |
836 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) { |
837 | WARN_ON(1); | |
838 | return; | |
839 | } | |
840 | ||
f57f2ef5 | 841 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
842 | for_each_shadow_entry(vcpu, gva, iterator) { |
843 | level = iterator.level; | |
844 | sptep = iterator.sptep; | |
ad218f85 | 845 | |
f78978aa | 846 | sp = page_header(__pa(sptep)); |
884a0ff0 | 847 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
848 | pt_element_t gpte; |
849 | gpa_t pte_gpa; | |
850 | ||
f78978aa XG |
851 | if (!sp->unsync) |
852 | break; | |
853 | ||
505aef8f | 854 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 855 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 856 | |
505aef8f XG |
857 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
858 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
859 | |
860 | if (!rmap_can_add(vcpu)) | |
861 | break; | |
862 | ||
54bf36aa PB |
863 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
864 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
865 | break; |
866 | ||
867 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 868 | } |
a7052897 | 869 | |
f78978aa | 870 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
871 | break; |
872 | } | |
ad218f85 | 873 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
874 | } |
875 | ||
1871c602 | 876 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 877 | struct x86_exception *exception) |
6aa8b732 AK |
878 | { |
879 | struct guest_walker walker; | |
e119d117 AK |
880 | gpa_t gpa = UNMAPPED_GVA; |
881 | int r; | |
6aa8b732 | 882 | |
33770780 | 883 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 884 | |
e119d117 | 885 | if (r) { |
1755fbcc | 886 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 887 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
888 | } else if (exception) |
889 | *exception = walker.fault; | |
6aa8b732 AK |
890 | |
891 | return gpa; | |
892 | } | |
893 | ||
37406aaa | 894 | #if PTTYPE != PTTYPE_EPT |
6539e738 | 895 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
896 | u32 access, |
897 | struct x86_exception *exception) | |
6539e738 JR |
898 | { |
899 | struct guest_walker walker; | |
900 | gpa_t gpa = UNMAPPED_GVA; | |
901 | int r; | |
902 | ||
33770780 | 903 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
904 | |
905 | if (r) { | |
906 | gpa = gfn_to_gpa(walker.gfn); | |
907 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
908 | } else if (exception) |
909 | *exception = walker.fault; | |
6539e738 JR |
910 | |
911 | return gpa; | |
912 | } | |
37406aaa | 913 | #endif |
6539e738 | 914 | |
e8bc217a MT |
915 | /* |
916 | * Using the cached information from sp->gfns is safe because: | |
917 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
918 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
919 | * |
920 | * Note: | |
921 | * We should flush all tlbs if spte is dropped even though guest is | |
922 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
923 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
924 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
925 | * freed pages. | |
a086f6a1 | 926 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 927 | */ |
a4a8e6f7 | 928 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 929 | { |
505aef8f | 930 | int i, nr_present = 0; |
9bdbba13 | 931 | bool host_writable; |
51fb60d8 | 932 | gpa_t first_pte_gpa; |
e8bc217a | 933 | |
2032a93d LJ |
934 | /* direct kvm_mmu_page can not be unsync. */ |
935 | BUG_ON(sp->role.direct); | |
936 | ||
505aef8f | 937 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 938 | |
e8bc217a MT |
939 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
940 | unsigned pte_access; | |
941 | pt_element_t gpte; | |
942 | gpa_t pte_gpa; | |
f55c3f41 | 943 | gfn_t gfn; |
e8bc217a | 944 | |
ce88decf | 945 | if (!sp->spt[i]) |
e8bc217a MT |
946 | continue; |
947 | ||
51fb60d8 | 948 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 949 | |
54bf36aa PB |
950 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
951 | sizeof(pt_element_t))) | |
e8bc217a MT |
952 | return -EINVAL; |
953 | ||
0ad805a0 | 954 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
a086f6a1 | 955 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
956 | continue; |
957 | } | |
958 | ||
ce88decf XG |
959 | gfn = gpte_to_gfn(gpte); |
960 | pte_access = sp->role.access; | |
0ad805a0 NHE |
961 | pte_access &= FNAME(gpte_access)(vcpu, gpte); |
962 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
ce88decf | 963 | |
54bf36aa | 964 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 965 | &nr_present)) |
ce88decf XG |
966 | continue; |
967 | ||
407c61c6 | 968 | if (gfn != sp->gfns[i]) { |
c3707958 | 969 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a086f6a1 | 970 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
971 | continue; |
972 | } | |
973 | ||
974 | nr_present++; | |
ce88decf | 975 | |
f8e453b0 XG |
976 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
977 | ||
c2288505 | 978 | set_spte(vcpu, &sp->spt[i], pte_access, |
640d9b0d | 979 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 980 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 981 | host_writable); |
e8bc217a MT |
982 | } |
983 | ||
984 | return !nr_present; | |
985 | } | |
986 | ||
6aa8b732 AK |
987 | #undef pt_element_t |
988 | #undef guest_walker | |
989 | #undef FNAME | |
990 | #undef PT_BASE_ADDR_MASK | |
991 | #undef PT_INDEX | |
e04da980 JR |
992 | #undef PT_LVL_ADDR_MASK |
993 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 994 | #undef PT_LEVEL_BITS |
cea0f0e7 | 995 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 996 | #undef gpte_to_gfn |
e04da980 | 997 | #undef gpte_to_gfn_lvl |
b3e4e63f | 998 | #undef CMPXCHG |
d8089bac GN |
999 | #undef PT_GUEST_ACCESSED_MASK |
1000 | #undef PT_GUEST_DIRTY_MASK | |
1001 | #undef PT_GUEST_DIRTY_SHIFT | |
1002 | #undef PT_GUEST_ACCESSED_SHIFT |