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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
35 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
36 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
37 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
38 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
cea0f0e7 AK |
39 | #ifdef CONFIG_X86_64 |
40 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 41 | #define CMPXCHG cmpxchg |
cea0f0e7 | 42 | #else |
b3e4e63f | 43 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
44 | #define PT_MAX_FULL_LEVELS 2 |
45 | #endif | |
6aa8b732 AK |
46 | #elif PTTYPE == 32 |
47 | #define pt_element_t u32 | |
48 | #define guest_walker guest_walker32 | |
49 | #define FNAME(name) paging##32_##name | |
50 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
51 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
52 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 53 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 54 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 55 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
56 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
57 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
58 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
59 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
b3e4e63f | 60 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
61 | #else |
62 | #error Invalid PTTYPE value | |
63 | #endif | |
64 | ||
e04da980 JR |
65 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
66 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 67 | |
6aa8b732 AK |
68 | /* |
69 | * The guest_walker structure emulates the behavior of the hardware page | |
70 | * table walker. | |
71 | */ | |
72 | struct guest_walker { | |
73 | int level; | |
8cbc7069 | 74 | unsigned max_level; |
cea0f0e7 | 75 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 76 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 77 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 78 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 79 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
80 | unsigned pt_access; |
81 | unsigned pte_access; | |
815af8d4 | 82 | gfn_t gfn; |
8c28d031 | 83 | struct x86_exception fault; |
6aa8b732 AK |
84 | }; |
85 | ||
e04da980 | 86 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 87 | { |
e04da980 | 88 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
89 | } |
90 | ||
0ad805a0 NHE |
91 | static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte) |
92 | { | |
93 | unsigned mask; | |
94 | ||
61719a8f GN |
95 | /* dirty bit is not supported, so no need to track it */ |
96 | if (!PT_GUEST_DIRTY_MASK) | |
97 | return; | |
98 | ||
0ad805a0 NHE |
99 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
100 | ||
101 | mask = (unsigned)~ACC_WRITE_MASK; | |
102 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
103 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
104 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
105 | *access &= mask; |
106 | } | |
107 | ||
108 | static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level) | |
109 | { | |
110 | int bit7; | |
111 | ||
112 | bit7 = (gpte >> 7) & 1; | |
113 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; | |
114 | } | |
115 | ||
116 | static inline int FNAME(is_present_gpte)(unsigned long pte) | |
117 | { | |
118 | return is_present_gpte(pte); | |
119 | } | |
120 | ||
a78484c6 | 121 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
122 | pt_element_t __user *ptep_user, unsigned index, |
123 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 124 | { |
c8cfbb55 | 125 | int npages; |
b3e4e63f MT |
126 | pt_element_t ret; |
127 | pt_element_t *table; | |
128 | struct page *page; | |
129 | ||
c8cfbb55 TY |
130 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
131 | /* Check if the user is doing something meaningless. */ | |
132 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
133 | return -EFAULT; |
134 | ||
8fd75e12 | 135 | table = kmap_atomic(page); |
b3e4e63f | 136 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 137 | kunmap_atomic(table); |
b3e4e63f MT |
138 | |
139 | kvm_release_page_dirty(page); | |
140 | ||
141 | return (ret != orig_pte); | |
142 | } | |
143 | ||
0ad805a0 NHE |
144 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
145 | struct kvm_mmu_page *sp, u64 *spte, | |
146 | u64 gpte) | |
147 | { | |
148 | if (FNAME(is_rsvd_bits_set)(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
149 | goto no_present; | |
150 | ||
151 | if (!FNAME(is_present_gpte)(gpte)) | |
152 | goto no_present; | |
153 | ||
61719a8f GN |
154 | /* if accessed bit is not supported prefetch non accessed gpte */ |
155 | if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
156 | goto no_present; |
157 | ||
158 | return false; | |
159 | ||
160 | no_present: | |
161 | drop_spte(vcpu->kvm, spte); | |
162 | return true; | |
163 | } | |
164 | ||
165 | static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte) | |
166 | { | |
167 | unsigned access; | |
168 | ||
169 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
170 | access &= ~(gpte >> PT64_NX_SHIFT); | |
171 | ||
172 | return access; | |
173 | } | |
174 | ||
8cbc7069 AK |
175 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
176 | struct kvm_mmu *mmu, | |
177 | struct guest_walker *walker, | |
178 | int write_fault) | |
179 | { | |
180 | unsigned level, index; | |
181 | pt_element_t pte, orig_pte; | |
182 | pt_element_t __user *ptep_user; | |
183 | gfn_t table_gfn; | |
184 | int ret; | |
185 | ||
61719a8f GN |
186 | /* dirty/accessed bits are not supported, so no need to update them */ |
187 | if (!PT_GUEST_DIRTY_MASK) | |
188 | return 0; | |
189 | ||
8cbc7069 AK |
190 | for (level = walker->max_level; level >= walker->level; --level) { |
191 | pte = orig_pte = walker->ptes[level - 1]; | |
192 | table_gfn = walker->table_gfn[level - 1]; | |
193 | ptep_user = walker->ptep_user[level - 1]; | |
194 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 195 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 196 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 197 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 198 | } |
0ad805a0 | 199 | if (level == walker->level && write_fault && |
d8089bac | 200 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 201 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 202 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
203 | } |
204 | if (pte == orig_pte) | |
205 | continue; | |
206 | ||
207 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); | |
208 | if (ret) | |
209 | return ret; | |
210 | ||
211 | mark_page_dirty(vcpu->kvm, table_gfn); | |
212 | walker->ptes[level] = pte; | |
213 | } | |
214 | return 0; | |
215 | } | |
216 | ||
ac79c978 AK |
217 | /* |
218 | * Fetch a guest pte for a guest virtual address | |
219 | */ | |
1e301feb JR |
220 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
221 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 222 | gva_t addr, u32 access) |
6aa8b732 | 223 | { |
8cbc7069 | 224 | int ret; |
42bf3f0a | 225 | pt_element_t pte; |
b7233635 | 226 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 227 | gfn_t table_gfn; |
b0cfeb5d | 228 | unsigned index, pt_access, pte_access, accessed_dirty; |
42bf3f0a | 229 | gpa_t pte_gpa; |
134291bf TY |
230 | int offset; |
231 | const int write_fault = access & PFERR_WRITE_MASK; | |
232 | const int user_fault = access & PFERR_USER_MASK; | |
233 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
234 | u16 errcode = 0; | |
13d22b6a AK |
235 | gpa_t real_gpa; |
236 | gfn_t gfn; | |
6aa8b732 | 237 | |
6fbc2770 | 238 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 239 | retry_walk: |
1e301feb JR |
240 | walker->level = mmu->root_level; |
241 | pte = mmu->get_cr3(vcpu); | |
242 | ||
1b0973bd | 243 | #if PTTYPE == 64 |
1e301feb | 244 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 245 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 246 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 247 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 248 | goto error; |
1b0973bd AK |
249 | --walker->level; |
250 | } | |
251 | #endif | |
8cbc7069 | 252 | walker->max_level = walker->level; |
a9058ecd | 253 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 254 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 255 | |
d8089bac | 256 | accessed_dirty = PT_GUEST_ACCESSED_MASK; |
13d22b6a AK |
257 | pt_access = pte_access = ACC_ALL; |
258 | ++walker->level; | |
ac79c978 | 259 | |
13d22b6a | 260 | do { |
6e2ca7d1 TY |
261 | gfn_t real_gfn; |
262 | unsigned long host_addr; | |
263 | ||
13d22b6a AK |
264 | pt_access &= pte_access; |
265 | --walker->level; | |
266 | ||
42bf3f0a | 267 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 268 | |
5fb07ddb | 269 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
270 | offset = index * sizeof(pt_element_t); |
271 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 272 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 273 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 274 | |
6e2ca7d1 TY |
275 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
276 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
277 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
278 | goto error; | |
6e2ca7d1 TY |
279 | real_gfn = gpa_to_gfn(real_gfn); |
280 | ||
281 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
282 | if (unlikely(kvm_is_error_hva(host_addr))) |
283 | goto error; | |
6e2ca7d1 TY |
284 | |
285 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
286 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
287 | goto error; | |
8cbc7069 | 288 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 289 | |
07420171 | 290 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 291 | |
0ad805a0 | 292 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 293 | goto error; |
7993ba43 | 294 | |
0ad805a0 NHE |
295 | if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, |
296 | walker->level))) { | |
134291bf TY |
297 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
298 | goto error; | |
f59c1d2d | 299 | } |
82725b20 | 300 | |
b514c30f | 301 | accessed_dirty &= pte; |
0ad805a0 | 302 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
73b1087e | 303 | |
7819026e | 304 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 305 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 306 | |
71331a1d | 307 | if (unlikely(permission_fault(mmu, pte_access, access))) { |
134291bf | 308 | errcode |= PFERR_PRESENT_MASK; |
f59c1d2d | 309 | goto error; |
134291bf | 310 | } |
f59c1d2d | 311 | |
13d22b6a AK |
312 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
313 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
314 | ||
315 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
316 | gfn += pse36_gfn_delta(pte); | |
317 | ||
c5421519 | 318 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access); |
13d22b6a AK |
319 | if (real_gpa == UNMAPPED_GVA) |
320 | return 0; | |
321 | ||
322 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
323 | ||
8ea667f2 | 324 | if (!write_fault) |
0ad805a0 | 325 | FNAME(protect_clean_gpte)(&pte_access, pte); |
908e7d79 GN |
326 | else |
327 | /* | |
61719a8f GN |
328 | * On a write fault, fold the dirty bit into accessed_dirty. |
329 | * For modes without A/D bits support accessed_dirty will be | |
330 | * always clear. | |
908e7d79 | 331 | */ |
d8089bac GN |
332 | accessed_dirty &= pte >> |
333 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
334 | |
335 | if (unlikely(!accessed_dirty)) { | |
336 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
337 | if (unlikely(ret < 0)) | |
338 | goto error; | |
339 | else if (ret) | |
340 | goto retry_walk; | |
341 | } | |
42bf3f0a | 342 | |
fe135d2c AK |
343 | walker->pt_access = pt_access; |
344 | walker->pte_access = pte_access; | |
345 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 346 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
347 | return 1; |
348 | ||
f59c1d2d | 349 | error: |
134291bf | 350 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
351 | if (fetch_fault && (mmu->nx || |
352 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 353 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 354 | |
134291bf TY |
355 | walker->fault.vector = PF_VECTOR; |
356 | walker->fault.error_code_valid = true; | |
357 | walker->fault.error_code = errcode; | |
6389ee94 AK |
358 | walker->fault.address = addr; |
359 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 360 | |
8c28d031 | 361 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 362 | return 0; |
6aa8b732 AK |
363 | } |
364 | ||
1e301feb | 365 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 366 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
367 | { |
368 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 369 | access); |
1e301feb JR |
370 | } |
371 | ||
6539e738 JR |
372 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
373 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 374 | u32 access) |
6539e738 JR |
375 | { |
376 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 377 | addr, access); |
6539e738 JR |
378 | } |
379 | ||
bd6360cc XG |
380 | static bool |
381 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
382 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 383 | { |
41074d07 | 384 | unsigned pte_access; |
bd6360cc | 385 | gfn_t gfn; |
35149e21 | 386 | pfn_t pfn; |
0028425f | 387 | |
0ad805a0 | 388 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 389 | return false; |
407c61c6 | 390 | |
b8688d51 | 391 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
392 | |
393 | gfn = gpte_to_gfn(gpte); | |
0ad805a0 NHE |
394 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
395 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
bd6360cc XG |
396 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
397 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 398 | if (is_error_pfn(pfn)) |
bd6360cc | 399 | return false; |
0f53b5b1 | 400 | |
1403283a | 401 | /* |
bd6360cc XG |
402 | * we call mmu_set_spte() with host_writable = true because |
403 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 404 | */ |
f7616203 XG |
405 | mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL, |
406 | gfn, pfn, true, true); | |
bd6360cc XG |
407 | |
408 | return true; | |
409 | } | |
410 | ||
411 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
412 | u64 *spte, const void *pte) | |
413 | { | |
414 | pt_element_t gpte = *(const pt_element_t *)pte; | |
415 | ||
416 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
417 | } |
418 | ||
39c8c672 AK |
419 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
420 | struct guest_walker *gw, int level) | |
421 | { | |
39c8c672 | 422 | pt_element_t curr_pte; |
189be38d XG |
423 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
424 | u64 mask; | |
425 | int r, index; | |
426 | ||
427 | if (level == PT_PAGE_TABLE_LEVEL) { | |
428 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
429 | base_gpa = pte_gpa & ~mask; | |
430 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
431 | ||
432 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
433 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
434 | curr_pte = gw->prefetch_ptes[index]; | |
435 | } else | |
436 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 437 | &curr_pte, sizeof(curr_pte)); |
189be38d | 438 | |
39c8c672 AK |
439 | return r || curr_pte != gw->ptes[level - 1]; |
440 | } | |
441 | ||
189be38d XG |
442 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
443 | u64 *sptep) | |
957ed9ef XG |
444 | { |
445 | struct kvm_mmu_page *sp; | |
189be38d | 446 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 447 | u64 *spte; |
189be38d | 448 | int i; |
957ed9ef XG |
449 | |
450 | sp = page_header(__pa(sptep)); | |
451 | ||
452 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
453 | return; | |
454 | ||
455 | if (sp->role.direct) | |
456 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
457 | ||
458 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
459 | spte = sp->spt + i; |
460 | ||
461 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
462 | if (spte == sptep) |
463 | continue; | |
464 | ||
c3707958 | 465 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
466 | continue; |
467 | ||
bd6360cc | 468 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 469 | break; |
957ed9ef XG |
470 | } |
471 | } | |
472 | ||
6aa8b732 AK |
473 | /* |
474 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
475 | * If the guest tries to write a write-protected page, we need to |
476 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 477 | */ |
d4878f24 | 478 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 479 | struct guest_walker *gw, |
c2288505 | 480 | int write_fault, int hlevel, |
d4878f24 | 481 | pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 482 | { |
5991b332 | 483 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 484 | struct kvm_shadow_walk_iterator it; |
d4878f24 XG |
485 | unsigned direct_access, access = gw->pt_access; |
486 | int top_level, emulate = 0; | |
abb9e0b8 | 487 | |
b36c7a7c | 488 | direct_access = gw->pte_access; |
84754cd8 | 489 | |
5991b332 AK |
490 | top_level = vcpu->arch.mmu.root_level; |
491 | if (top_level == PT32E_ROOT_LEVEL) | |
492 | top_level = PT32_ROOT_LEVEL; | |
493 | /* | |
494 | * Verify that the top-level gpte is still there. Since the page | |
495 | * is a root page, it is either write protected (and cannot be | |
496 | * changed from now on) or it is invalid (in which case, we don't | |
497 | * really care if it changes underneath us after this point). | |
498 | */ | |
499 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
500 | goto out_gpte_changed; | |
501 | ||
24157aaf AK |
502 | for (shadow_walk_init(&it, vcpu, addr); |
503 | shadow_walk_okay(&it) && it.level > gw->level; | |
504 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
505 | gfn_t table_gfn; |
506 | ||
a30f47cb | 507 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 508 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 509 | |
5991b332 | 510 | sp = NULL; |
24157aaf AK |
511 | if (!is_shadow_present_pte(*it.sptep)) { |
512 | table_gfn = gw->table_gfn[it.level - 2]; | |
513 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
514 | false, access, it.sptep); | |
5991b332 | 515 | } |
0b3c9333 AK |
516 | |
517 | /* | |
518 | * Verify that the gpte in the page we've just write | |
519 | * protected is still there. | |
520 | */ | |
24157aaf | 521 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 522 | goto out_gpte_changed; |
abb9e0b8 | 523 | |
5991b332 | 524 | if (sp) |
24157aaf | 525 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 526 | } |
050e6499 | 527 | |
0b3c9333 | 528 | for (; |
24157aaf AK |
529 | shadow_walk_okay(&it) && it.level > hlevel; |
530 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
531 | gfn_t direct_gfn; |
532 | ||
a30f47cb | 533 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 534 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 535 | |
24157aaf | 536 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 537 | |
24157aaf | 538 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
539 | continue; |
540 | ||
24157aaf | 541 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 542 | |
24157aaf AK |
543 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
544 | true, direct_access, it.sptep); | |
545 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
546 | } |
547 | ||
a30f47cb | 548 | clear_sp_write_flooding_count(it.sptep); |
f7616203 XG |
549 | mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate, |
550 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 551 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 552 | |
d4878f24 | 553 | return emulate; |
0b3c9333 AK |
554 | |
555 | out_gpte_changed: | |
5991b332 | 556 | if (sp) |
24157aaf | 557 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 | 558 | kvm_release_pfn_clean(pfn); |
d4878f24 | 559 | return 0; |
6aa8b732 AK |
560 | } |
561 | ||
7751babd XG |
562 | /* |
563 | * To see whether the mapped gfn can write its page table in the current | |
564 | * mapping. | |
565 | * | |
566 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
567 | * size to map the writable gfn which is used as current page table, we should | |
568 | * force kvm to use small page size to map it because new shadow page will be | |
569 | * created when kvm establishes shadow page table that stop kvm using large | |
570 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
571 | * | |
93c05d3e XG |
572 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
573 | * currently used as its page table. | |
574 | * | |
7751babd XG |
575 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
576 | * since the PDPT is always shadowed, that means, we can not use large page | |
577 | * size to map the gfn which is used as PDPT. | |
578 | */ | |
579 | static bool | |
580 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
581 | struct guest_walker *walker, int user_fault, |
582 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
583 | { |
584 | int level; | |
585 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 586 | bool self_changed = false; |
7751babd XG |
587 | |
588 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
589 | (!is_write_protection(vcpu) && !user_fault))) | |
590 | return false; | |
591 | ||
93c05d3e XG |
592 | for (level = walker->level; level <= walker->max_level; level++) { |
593 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
594 | ||
595 | self_changed |= !(gfn & mask); | |
596 | *write_fault_to_shadow_pgtable |= !gfn; | |
597 | } | |
7751babd | 598 | |
93c05d3e | 599 | return self_changed; |
7751babd XG |
600 | } |
601 | ||
6aa8b732 AK |
602 | /* |
603 | * Page fault handler. There are several causes for a page fault: | |
604 | * - there is no shadow pte for the guest pte | |
605 | * - write access through a shadow pte marked read only so that we can set | |
606 | * the dirty bit | |
607 | * - write access to a shadow pte marked read only so we can update the page | |
608 | * dirty bitmap, when userspace requests it | |
609 | * - mmio access; in this case we will never install a present shadow pte | |
610 | * - normal guest page fault due to the guest pte marked not present, not | |
611 | * writable, or not executable | |
612 | * | |
e2dec939 AK |
613 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
614 | * a negative value on error. | |
6aa8b732 | 615 | */ |
56028d08 | 616 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 617 | bool prefault) |
6aa8b732 AK |
618 | { |
619 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
620 | int user_fault = error_code & PFERR_USER_MASK; |
621 | struct guest_walker walker; | |
e2dec939 | 622 | int r; |
35149e21 | 623 | pfn_t pfn; |
7e4e4056 | 624 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 625 | int force_pt_level; |
e930bffe | 626 | unsigned long mmu_seq; |
93c05d3e | 627 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 628 | |
b8688d51 | 629 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 630 | |
f8f55942 XG |
631 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
632 | r = handle_mmio_page_fault(vcpu, addr, error_code, | |
ce88decf | 633 | mmu_is_nested(vcpu)); |
f8f55942 XG |
634 | if (likely(r != RET_MMIO_PF_INVALID)) |
635 | return r; | |
636 | }; | |
ce88decf | 637 | |
e2dec939 AK |
638 | r = mmu_topup_memory_caches(vcpu); |
639 | if (r) | |
640 | return r; | |
714b93da | 641 | |
6aa8b732 | 642 | /* |
a8b876b1 | 643 | * Look up the guest pte for the faulting address. |
6aa8b732 | 644 | */ |
33770780 | 645 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
646 | |
647 | /* | |
648 | * The page is not mapped by the guest. Let the guest handle it. | |
649 | */ | |
7993ba43 | 650 | if (!r) { |
b8688d51 | 651 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 652 | if (!prefault) |
fb67e14f | 653 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 654 | |
6aa8b732 AK |
655 | return 0; |
656 | } | |
657 | ||
93c05d3e XG |
658 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
659 | ||
660 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
661 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
662 | ||
936a5fe6 | 663 | if (walker.level >= PT_DIRECTORY_LEVEL) |
7751babd | 664 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn) |
93c05d3e | 665 | || is_self_change_mapping; |
936a5fe6 AA |
666 | else |
667 | force_pt_level = 1; | |
668 | if (!force_pt_level) { | |
7e4e4056 JR |
669 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
670 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 671 | } |
7e4e4056 | 672 | |
e930bffe | 673 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 674 | smp_rmb(); |
af585b92 | 675 | |
78b2c54a | 676 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 677 | &map_writable)) |
af585b92 | 678 | return 0; |
d7824fff | 679 | |
d7c55201 XG |
680 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
681 | walker.gfn, pfn, walker.pte_access, &r)) | |
682 | return r; | |
683 | ||
c2288505 XG |
684 | /* |
685 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
686 | * we will cache the incorrect access into mmio spte. | |
687 | */ | |
688 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
689 | !is_write_protection(vcpu) && !user_fault && | |
690 | !is_noslot_pfn(pfn)) { | |
691 | walker.pte_access |= ACC_WRITE_MASK; | |
692 | walker.pte_access &= ~ACC_USER_MASK; | |
693 | ||
694 | /* | |
695 | * If we converted a user page to a kernel page, | |
696 | * so that the kernel can write to it when cr0.wp=0, | |
697 | * then we should prevent the kernel from executing it | |
698 | * if SMEP is enabled. | |
699 | */ | |
700 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
701 | walker.pte_access &= ~ACC_EXEC_MASK; | |
702 | } | |
703 | ||
aaee2c94 | 704 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 705 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 706 | goto out_unlock; |
bc32ce21 | 707 | |
0375f7fa | 708 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
450e0b41 | 709 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
710 | if (!force_pt_level) |
711 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 712 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 713 | level, pfn, map_writable, prefault); |
1165f5fe | 714 | ++vcpu->stat.pf_fixed; |
0375f7fa | 715 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 716 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 717 | |
d4878f24 | 718 | return r; |
e930bffe AA |
719 | |
720 | out_unlock: | |
721 | spin_unlock(&vcpu->kvm->mmu_lock); | |
722 | kvm_release_pfn_clean(pfn); | |
723 | return 0; | |
6aa8b732 AK |
724 | } |
725 | ||
505aef8f XG |
726 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
727 | { | |
728 | int offset = 0; | |
729 | ||
f71fa31f | 730 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
731 | |
732 | if (PTTYPE == 32) | |
733 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
734 | ||
735 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
736 | } | |
737 | ||
a461930b | 738 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 739 | { |
a461930b | 740 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 741 | struct kvm_mmu_page *sp; |
a461930b AK |
742 | int level; |
743 | u64 *sptep; | |
744 | ||
bebb106a XG |
745 | vcpu_clear_mmio_info(vcpu, gva); |
746 | ||
f57f2ef5 XG |
747 | /* |
748 | * No need to check return value here, rmap_can_add() can | |
749 | * help us to skip pte prefetch later. | |
750 | */ | |
751 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 752 | |
f57f2ef5 | 753 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
754 | for_each_shadow_entry(vcpu, gva, iterator) { |
755 | level = iterator.level; | |
756 | sptep = iterator.sptep; | |
ad218f85 | 757 | |
f78978aa | 758 | sp = page_header(__pa(sptep)); |
884a0ff0 | 759 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
760 | pt_element_t gpte; |
761 | gpa_t pte_gpa; | |
762 | ||
f78978aa XG |
763 | if (!sp->unsync) |
764 | break; | |
765 | ||
505aef8f | 766 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 767 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 768 | |
505aef8f XG |
769 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
770 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
771 | |
772 | if (!rmap_can_add(vcpu)) | |
773 | break; | |
774 | ||
775 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
776 | sizeof(pt_element_t))) | |
777 | break; | |
778 | ||
779 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 780 | } |
a7052897 | 781 | |
f78978aa | 782 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
783 | break; |
784 | } | |
ad218f85 | 785 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
786 | } |
787 | ||
1871c602 | 788 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 789 | struct x86_exception *exception) |
6aa8b732 AK |
790 | { |
791 | struct guest_walker walker; | |
e119d117 AK |
792 | gpa_t gpa = UNMAPPED_GVA; |
793 | int r; | |
6aa8b732 | 794 | |
33770780 | 795 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 796 | |
e119d117 | 797 | if (r) { |
1755fbcc | 798 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 799 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
800 | } else if (exception) |
801 | *exception = walker.fault; | |
6aa8b732 AK |
802 | |
803 | return gpa; | |
804 | } | |
805 | ||
6539e738 | 806 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
807 | u32 access, |
808 | struct x86_exception *exception) | |
6539e738 JR |
809 | { |
810 | struct guest_walker walker; | |
811 | gpa_t gpa = UNMAPPED_GVA; | |
812 | int r; | |
813 | ||
33770780 | 814 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
815 | |
816 | if (r) { | |
817 | gpa = gfn_to_gpa(walker.gfn); | |
818 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
819 | } else if (exception) |
820 | *exception = walker.fault; | |
6539e738 JR |
821 | |
822 | return gpa; | |
823 | } | |
824 | ||
e8bc217a MT |
825 | /* |
826 | * Using the cached information from sp->gfns is safe because: | |
827 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
828 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
829 | * |
830 | * Note: | |
831 | * We should flush all tlbs if spte is dropped even though guest is | |
832 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
833 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
834 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
835 | * freed pages. | |
836 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 837 | */ |
a4a8e6f7 | 838 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 839 | { |
505aef8f | 840 | int i, nr_present = 0; |
9bdbba13 | 841 | bool host_writable; |
51fb60d8 | 842 | gpa_t first_pte_gpa; |
e8bc217a | 843 | |
2032a93d LJ |
844 | /* direct kvm_mmu_page can not be unsync. */ |
845 | BUG_ON(sp->role.direct); | |
846 | ||
505aef8f | 847 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 848 | |
e8bc217a MT |
849 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
850 | unsigned pte_access; | |
851 | pt_element_t gpte; | |
852 | gpa_t pte_gpa; | |
f55c3f41 | 853 | gfn_t gfn; |
e8bc217a | 854 | |
ce88decf | 855 | if (!sp->spt[i]) |
e8bc217a MT |
856 | continue; |
857 | ||
51fb60d8 | 858 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
859 | |
860 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
861 | sizeof(pt_element_t))) | |
862 | return -EINVAL; | |
863 | ||
0ad805a0 | 864 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
a4ee1ca4 | 865 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
866 | continue; |
867 | } | |
868 | ||
ce88decf XG |
869 | gfn = gpte_to_gfn(gpte); |
870 | pte_access = sp->role.access; | |
0ad805a0 NHE |
871 | pte_access &= FNAME(gpte_access)(vcpu, gpte); |
872 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
ce88decf | 873 | |
f2fd125d XG |
874 | if (sync_mmio_spte(vcpu->kvm, &sp->spt[i], gfn, pte_access, |
875 | &nr_present)) | |
ce88decf XG |
876 | continue; |
877 | ||
407c61c6 | 878 | if (gfn != sp->gfns[i]) { |
c3707958 | 879 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a4ee1ca4 | 880 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
881 | continue; |
882 | } | |
883 | ||
884 | nr_present++; | |
ce88decf | 885 | |
f8e453b0 XG |
886 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
887 | ||
c2288505 | 888 | set_spte(vcpu, &sp->spt[i], pte_access, |
640d9b0d | 889 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 890 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 891 | host_writable); |
e8bc217a MT |
892 | } |
893 | ||
894 | return !nr_present; | |
895 | } | |
896 | ||
6aa8b732 AK |
897 | #undef pt_element_t |
898 | #undef guest_walker | |
899 | #undef FNAME | |
900 | #undef PT_BASE_ADDR_MASK | |
901 | #undef PT_INDEX | |
e04da980 JR |
902 | #undef PT_LVL_ADDR_MASK |
903 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 904 | #undef PT_LEVEL_BITS |
cea0f0e7 | 905 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 906 | #undef gpte_to_gfn |
e04da980 | 907 | #undef gpte_to_gfn_lvl |
b3e4e63f | 908 | #undef CMPXCHG |
d8089bac GN |
909 | #undef PT_GUEST_ACCESSED_MASK |
910 | #undef PT_GUEST_DIRTY_MASK | |
911 | #undef PT_GUEST_DIRTY_SHIFT | |
912 | #undef PT_GUEST_ACCESSED_SHIFT |