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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
35 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
36 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 37 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
cea0f0e7 AK |
38 | #ifdef CONFIG_X86_64 |
39 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 40 | #define CMPXCHG cmpxchg |
cea0f0e7 | 41 | #else |
b3e4e63f | 42 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
43 | #define PT_MAX_FULL_LEVELS 2 |
44 | #endif | |
6aa8b732 AK |
45 | #elif PTTYPE == 32 |
46 | #define pt_element_t u32 | |
47 | #define guest_walker guest_walker32 | |
48 | #define FNAME(name) paging##32_##name | |
49 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
50 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
51 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 52 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 53 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 54 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
55 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
56 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 57 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
b3e4e63f | 58 | #define CMPXCHG cmpxchg |
37406aaa NHE |
59 | #elif PTTYPE == PTTYPE_EPT |
60 | #define pt_element_t u64 | |
61 | #define guest_walker guest_walkerEPT | |
62 | #define FNAME(name) ept_##name | |
63 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
64 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
65 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
66 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
67 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
ae1e2d10 PB |
68 | #define PT_GUEST_DIRTY_SHIFT 9 |
69 | #define PT_GUEST_ACCESSED_SHIFT 8 | |
70 | #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) | |
37406aaa NHE |
71 | #define CMPXCHG cmpxchg64 |
72 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
73 | #else |
74 | #error Invalid PTTYPE value | |
75 | #endif | |
76 | ||
ae1e2d10 PB |
77 | #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT) |
78 | #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT) | |
79 | ||
e04da980 JR |
80 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
81 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 82 | |
6aa8b732 AK |
83 | /* |
84 | * The guest_walker structure emulates the behavior of the hardware page | |
85 | * table walker. | |
86 | */ | |
87 | struct guest_walker { | |
88 | int level; | |
8cbc7069 | 89 | unsigned max_level; |
cea0f0e7 | 90 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 91 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 92 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 93 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 94 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 95 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
96 | unsigned pt_access; |
97 | unsigned pte_access; | |
815af8d4 | 98 | gfn_t gfn; |
8c28d031 | 99 | struct x86_exception fault; |
6aa8b732 AK |
100 | }; |
101 | ||
e04da980 | 102 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 103 | { |
e04da980 | 104 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
105 | } |
106 | ||
86407bcb PB |
107 | static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access, |
108 | unsigned gpte) | |
0ad805a0 NHE |
109 | { |
110 | unsigned mask; | |
111 | ||
61719a8f | 112 | /* dirty bit is not supported, so no need to track it */ |
86407bcb | 113 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
114 | return; |
115 | ||
0ad805a0 NHE |
116 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
117 | ||
118 | mask = (unsigned)~ACC_WRITE_MASK; | |
119 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
120 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
121 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
122 | *access &= mask; |
123 | } | |
124 | ||
0ad805a0 NHE |
125 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
126 | { | |
37406aaa | 127 | #if PTTYPE != PTTYPE_EPT |
812f30b2 | 128 | return pte & PT_PRESENT_MASK; |
37406aaa NHE |
129 | #else |
130 | return pte & 7; | |
131 | #endif | |
0ad805a0 NHE |
132 | } |
133 | ||
a78484c6 | 134 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
135 | pt_element_t __user *ptep_user, unsigned index, |
136 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 137 | { |
c8cfbb55 | 138 | int npages; |
b3e4e63f MT |
139 | pt_element_t ret; |
140 | pt_element_t *table; | |
141 | struct page *page; | |
142 | ||
c8cfbb55 TY |
143 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
144 | /* Check if the user is doing something meaningless. */ | |
145 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
146 | return -EFAULT; |
147 | ||
8fd75e12 | 148 | table = kmap_atomic(page); |
b3e4e63f | 149 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 150 | kunmap_atomic(table); |
b3e4e63f MT |
151 | |
152 | kvm_release_page_dirty(page); | |
153 | ||
154 | return (ret != orig_pte); | |
155 | } | |
156 | ||
0ad805a0 NHE |
157 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
158 | struct kvm_mmu_page *sp, u64 *spte, | |
159 | u64 gpte) | |
160 | { | |
d2b0f981 | 161 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
0ad805a0 NHE |
162 | goto no_present; |
163 | ||
164 | if (!FNAME(is_present_gpte)(gpte)) | |
165 | goto no_present; | |
166 | ||
61719a8f | 167 | /* if accessed bit is not supported prefetch non accessed gpte */ |
86407bcb | 168 | if (PT_HAVE_ACCESSED_DIRTY(&vcpu->arch.mmu) && !(gpte & PT_GUEST_ACCESSED_MASK)) |
0ad805a0 NHE |
169 | goto no_present; |
170 | ||
171 | return false; | |
172 | ||
173 | no_present: | |
174 | drop_spte(vcpu->kvm, spte); | |
175 | return true; | |
176 | } | |
177 | ||
d95c5568 BD |
178 | /* |
179 | * For PTTYPE_EPT, a page table can be executable but not readable | |
180 | * on supported processors. Therefore, set_spte does not automatically | |
181 | * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK | |
182 | * to signify readability since it isn't used in the EPT case | |
183 | */ | |
0ad805a0 NHE |
184 | static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte) |
185 | { | |
186 | unsigned access; | |
37406aaa NHE |
187 | #if PTTYPE == PTTYPE_EPT |
188 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
189 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
d95c5568 | 190 | ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0); |
37406aaa | 191 | #else |
bb9eadf0 PB |
192 | BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK); |
193 | BUILD_BUG_ON(ACC_EXEC_MASK != 1); | |
194 | access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK); | |
195 | /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */ | |
196 | access ^= (gpte >> PT64_NX_SHIFT); | |
37406aaa | 197 | #endif |
0ad805a0 NHE |
198 | |
199 | return access; | |
200 | } | |
201 | ||
8cbc7069 AK |
202 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
203 | struct kvm_mmu *mmu, | |
204 | struct guest_walker *walker, | |
205 | int write_fault) | |
206 | { | |
207 | unsigned level, index; | |
208 | pt_element_t pte, orig_pte; | |
209 | pt_element_t __user *ptep_user; | |
210 | gfn_t table_gfn; | |
211 | int ret; | |
212 | ||
61719a8f | 213 | /* dirty/accessed bits are not supported, so no need to update them */ |
86407bcb | 214 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
215 | return 0; |
216 | ||
8cbc7069 AK |
217 | for (level = walker->max_level; level >= walker->level; --level) { |
218 | pte = orig_pte = walker->ptes[level - 1]; | |
219 | table_gfn = walker->table_gfn[level - 1]; | |
220 | ptep_user = walker->ptep_user[level - 1]; | |
221 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 222 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 223 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 224 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 225 | } |
0ad805a0 | 226 | if (level == walker->level && write_fault && |
d8089bac | 227 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 228 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
bab4165e BD |
229 | #if PTTYPE == PTTYPE_EPT |
230 | if (kvm_arch_write_log_dirty(vcpu)) | |
231 | return -EINVAL; | |
232 | #endif | |
d8089bac | 233 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
234 | } |
235 | if (pte == orig_pte) | |
236 | continue; | |
237 | ||
ba6a3541 PB |
238 | /* |
239 | * If the slot is read-only, simply do not process the accessed | |
240 | * and dirty bits. This is the correct thing to do if the slot | |
241 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
242 | * are only supported if the accessed and dirty bits are already | |
243 | * set in the ROM (so that MMIO writes are never needed). | |
244 | * | |
245 | * Note that NPT does not allow this at all and faults, since | |
246 | * it always wants nested page table entries for the guest | |
247 | * page tables to be writable. And EPT works but will simply | |
248 | * overwrite the read-only memory to set the accessed and dirty | |
249 | * bits. | |
250 | */ | |
251 | if (unlikely(!walker->pte_writable[level - 1])) | |
252 | continue; | |
253 | ||
8cbc7069 AK |
254 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
255 | if (ret) | |
256 | return ret; | |
257 | ||
54bf36aa | 258 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
17e4bce0 | 259 | walker->ptes[level - 1] = pte; |
8cbc7069 AK |
260 | } |
261 | return 0; | |
262 | } | |
263 | ||
be94f6b7 HH |
264 | static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte) |
265 | { | |
266 | unsigned pkeys = 0; | |
267 | #if PTTYPE == 64 | |
268 | pte_t pte = {.pte = gpte}; | |
269 | ||
270 | pkeys = pte_flags_pkey(pte_flags(pte)); | |
271 | #endif | |
272 | return pkeys; | |
273 | } | |
274 | ||
ac79c978 AK |
275 | /* |
276 | * Fetch a guest pte for a guest virtual address | |
277 | */ | |
1e301feb JR |
278 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
279 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 280 | gva_t addr, u32 access) |
6aa8b732 | 281 | { |
8cbc7069 | 282 | int ret; |
42bf3f0a | 283 | pt_element_t pte; |
b7233635 | 284 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 285 | gfn_t table_gfn; |
0780516a PB |
286 | u64 pt_access, pte_access; |
287 | unsigned index, accessed_dirty, pte_pkey; | |
ae1e2d10 | 288 | unsigned nested_access; |
42bf3f0a | 289 | gpa_t pte_gpa; |
86407bcb | 290 | bool have_ad; |
134291bf | 291 | int offset; |
0780516a | 292 | u64 walk_nx_mask = 0; |
134291bf TY |
293 | const int write_fault = access & PFERR_WRITE_MASK; |
294 | const int user_fault = access & PFERR_USER_MASK; | |
295 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
296 | u16 errcode = 0; | |
13d22b6a AK |
297 | gpa_t real_gpa; |
298 | gfn_t gfn; | |
6aa8b732 | 299 | |
6fbc2770 | 300 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 301 | retry_walk: |
1e301feb JR |
302 | walker->level = mmu->root_level; |
303 | pte = mmu->get_cr3(vcpu); | |
86407bcb | 304 | have_ad = PT_HAVE_ACCESSED_DIRTY(mmu); |
1e301feb | 305 | |
1b0973bd | 306 | #if PTTYPE == 64 |
0780516a | 307 | walk_nx_mask = 1ULL << PT64_NX_SHIFT; |
1e301feb | 308 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 309 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 310 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 311 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 312 | goto error; |
1b0973bd AK |
313 | --walker->level; |
314 | } | |
315 | #endif | |
8cbc7069 | 316 | walker->max_level = walker->level; |
1715d0dc | 317 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 318 | |
ae1e2d10 PB |
319 | /* |
320 | * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging | |
321 | * by the MOV to CR instruction are treated as reads and do not cause the | |
322 | * processor to set the dirty flag in any EPT paging-structure entry. | |
323 | */ | |
324 | nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK; | |
325 | ||
0780516a | 326 | pte_access = ~0; |
13d22b6a | 327 | ++walker->level; |
ac79c978 | 328 | |
13d22b6a | 329 | do { |
6e2ca7d1 TY |
330 | gfn_t real_gfn; |
331 | unsigned long host_addr; | |
332 | ||
0780516a | 333 | pt_access = pte_access; |
13d22b6a AK |
334 | --walker->level; |
335 | ||
42bf3f0a | 336 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 337 | |
5fb07ddb | 338 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
339 | offset = index * sizeof(pt_element_t); |
340 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 341 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 342 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 343 | |
6e2ca7d1 | 344 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
ae1e2d10 | 345 | nested_access, |
54987b7a | 346 | &walker->fault); |
5e352519 PB |
347 | |
348 | /* | |
349 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
350 | * instruction) triggers a nested page fault. The exit | |
351 | * qualification / exit info field will incorrectly have | |
352 | * "guest page access" as the nested page fault's cause, | |
353 | * instead of "guest page structure access". To fix this, | |
354 | * the x86_exception struct should be augmented with enough | |
355 | * information to fix the exit_qualification or exit_info_1 | |
356 | * fields. | |
357 | */ | |
134291bf | 358 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
54987b7a | 359 | return 0; |
5e352519 | 360 | |
6e2ca7d1 TY |
361 | real_gfn = gpa_to_gfn(real_gfn); |
362 | ||
54bf36aa | 363 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn, |
ba6a3541 | 364 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
365 | if (unlikely(kvm_is_error_hva(host_addr))) |
366 | goto error; | |
6e2ca7d1 TY |
367 | |
368 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
369 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
370 | goto error; | |
8cbc7069 | 371 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 372 | |
07420171 | 373 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 374 | |
0780516a PB |
375 | /* |
376 | * Inverting the NX it lets us AND it like other | |
377 | * permission bits. | |
378 | */ | |
379 | pte_access = pt_access & (pte ^ walk_nx_mask); | |
380 | ||
0ad805a0 | 381 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 382 | goto error; |
7993ba43 | 383 | |
d2b0f981 | 384 | if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) { |
7a98205d | 385 | errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
134291bf | 386 | goto error; |
f59c1d2d | 387 | } |
82725b20 | 388 | |
7819026e | 389 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 390 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 391 | |
be94f6b7 | 392 | pte_pkey = FNAME(gpte_pkeys)(vcpu, pte); |
0780516a PB |
393 | accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0; |
394 | ||
395 | /* Convert to ACC_*_MASK flags for struct guest_walker. */ | |
396 | walker->pt_access = FNAME(gpte_access)(vcpu, pt_access ^ walk_nx_mask); | |
397 | walker->pte_access = FNAME(gpte_access)(vcpu, pte_access ^ walk_nx_mask); | |
398 | errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access); | |
f13577e8 | 399 | if (unlikely(errcode)) |
f59c1d2d AK |
400 | goto error; |
401 | ||
13d22b6a AK |
402 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
403 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
404 | ||
405 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
406 | gfn += pse36_gfn_delta(pte); | |
407 | ||
54987b7a | 408 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
409 | if (real_gpa == UNMAPPED_GVA) |
410 | return 0; | |
411 | ||
412 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
413 | ||
8ea667f2 | 414 | if (!write_fault) |
0780516a | 415 | FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte); |
908e7d79 GN |
416 | else |
417 | /* | |
61719a8f GN |
418 | * On a write fault, fold the dirty bit into accessed_dirty. |
419 | * For modes without A/D bits support accessed_dirty will be | |
420 | * always clear. | |
908e7d79 | 421 | */ |
d8089bac GN |
422 | accessed_dirty &= pte >> |
423 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
424 | |
425 | if (unlikely(!accessed_dirty)) { | |
426 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
427 | if (unlikely(ret < 0)) | |
428 | goto error; | |
429 | else if (ret) | |
430 | goto retry_walk; | |
431 | } | |
42bf3f0a | 432 | |
fe135d2c | 433 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", |
0780516a | 434 | __func__, (u64)pte, walker->pte_access, walker->pt_access); |
7993ba43 AK |
435 | return 1; |
436 | ||
f59c1d2d | 437 | error: |
134291bf | 438 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
439 | if (fetch_fault && (mmu->nx || |
440 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 441 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 442 | |
134291bf TY |
443 | walker->fault.vector = PF_VECTOR; |
444 | walker->fault.error_code_valid = true; | |
445 | walker->fault.error_code = errcode; | |
25d92081 YZ |
446 | |
447 | #if PTTYPE == PTTYPE_EPT | |
448 | /* | |
449 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
450 | * misconfiguration requires to be injected. The detection is | |
451 | * done by is_rsvd_bits_set() above. | |
452 | * | |
453 | * We set up the value of exit_qualification to inject: | |
454 | * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation | |
455 | * [5:3] - Calculated by the page walk of the guest EPT page tables | |
456 | * [7:8] - Derived from [7:8] of real exit_qualification | |
457 | * | |
458 | * The other bits are set to 0. | |
459 | */ | |
460 | if (!(errcode & PFERR_RSVD_MASK)) { | |
461 | vcpu->arch.exit_qualification &= 0x187; | |
0780516a | 462 | vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3; |
25d92081 YZ |
463 | } |
464 | #endif | |
6389ee94 AK |
465 | walker->fault.address = addr; |
466 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 467 | |
8c28d031 | 468 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 469 | return 0; |
6aa8b732 AK |
470 | } |
471 | ||
1e301feb | 472 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 473 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
474 | { |
475 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 476 | access); |
1e301feb JR |
477 | } |
478 | ||
37406aaa | 479 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
480 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
481 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 482 | u32 access) |
6539e738 JR |
483 | { |
484 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 485 | addr, access); |
6539e738 | 486 | } |
37406aaa | 487 | #endif |
6539e738 | 488 | |
bd6360cc XG |
489 | static bool |
490 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
491 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 492 | { |
41074d07 | 493 | unsigned pte_access; |
bd6360cc | 494 | gfn_t gfn; |
ba049e93 | 495 | kvm_pfn_t pfn; |
0028425f | 496 | |
0ad805a0 | 497 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 498 | return false; |
407c61c6 | 499 | |
b8688d51 | 500 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
501 | |
502 | gfn = gpte_to_gfn(gpte); | |
0ad805a0 | 503 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
86407bcb | 504 | FNAME(protect_clean_gpte)(&vcpu->arch.mmu, &pte_access, gpte); |
bd6360cc XG |
505 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
506 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 507 | if (is_error_pfn(pfn)) |
bd6360cc | 508 | return false; |
0f53b5b1 | 509 | |
1403283a | 510 | /* |
bd6360cc XG |
511 | * we call mmu_set_spte() with host_writable = true because |
512 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 513 | */ |
029499b4 TY |
514 | mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn, |
515 | true, true); | |
bd6360cc XG |
516 | |
517 | return true; | |
518 | } | |
519 | ||
520 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
521 | u64 *spte, const void *pte) | |
522 | { | |
523 | pt_element_t gpte = *(const pt_element_t *)pte; | |
524 | ||
525 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
526 | } |
527 | ||
39c8c672 AK |
528 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
529 | struct guest_walker *gw, int level) | |
530 | { | |
39c8c672 | 531 | pt_element_t curr_pte; |
189be38d XG |
532 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
533 | u64 mask; | |
534 | int r, index; | |
535 | ||
536 | if (level == PT_PAGE_TABLE_LEVEL) { | |
537 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
538 | base_gpa = pte_gpa & ~mask; | |
539 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
540 | ||
54bf36aa | 541 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
542 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
543 | curr_pte = gw->prefetch_ptes[index]; | |
544 | } else | |
54bf36aa | 545 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 546 | &curr_pte, sizeof(curr_pte)); |
189be38d | 547 | |
39c8c672 AK |
548 | return r || curr_pte != gw->ptes[level - 1]; |
549 | } | |
550 | ||
189be38d XG |
551 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
552 | u64 *sptep) | |
957ed9ef XG |
553 | { |
554 | struct kvm_mmu_page *sp; | |
189be38d | 555 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 556 | u64 *spte; |
189be38d | 557 | int i; |
957ed9ef XG |
558 | |
559 | sp = page_header(__pa(sptep)); | |
560 | ||
561 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
562 | return; | |
563 | ||
564 | if (sp->role.direct) | |
565 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
566 | ||
567 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
568 | spte = sp->spt + i; |
569 | ||
570 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
571 | if (spte == sptep) |
572 | continue; | |
573 | ||
c3707958 | 574 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
575 | continue; |
576 | ||
bd6360cc | 577 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 578 | break; |
957ed9ef XG |
579 | } |
580 | } | |
581 | ||
6aa8b732 AK |
582 | /* |
583 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
584 | * If the guest tries to write a write-protected page, we need to |
585 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 586 | */ |
d4878f24 | 587 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 588 | struct guest_walker *gw, |
c2288505 | 589 | int write_fault, int hlevel, |
ba049e93 | 590 | kvm_pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 591 | { |
5991b332 | 592 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 593 | struct kvm_shadow_walk_iterator it; |
d4878f24 | 594 | unsigned direct_access, access = gw->pt_access; |
029499b4 | 595 | int top_level, emulate; |
abb9e0b8 | 596 | |
b36c7a7c | 597 | direct_access = gw->pte_access; |
84754cd8 | 598 | |
5991b332 AK |
599 | top_level = vcpu->arch.mmu.root_level; |
600 | if (top_level == PT32E_ROOT_LEVEL) | |
601 | top_level = PT32_ROOT_LEVEL; | |
602 | /* | |
603 | * Verify that the top-level gpte is still there. Since the page | |
604 | * is a root page, it is either write protected (and cannot be | |
605 | * changed from now on) or it is invalid (in which case, we don't | |
606 | * really care if it changes underneath us after this point). | |
607 | */ | |
608 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
609 | goto out_gpte_changed; | |
610 | ||
37f6a4e2 MT |
611 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
612 | goto out_gpte_changed; | |
613 | ||
24157aaf AK |
614 | for (shadow_walk_init(&it, vcpu, addr); |
615 | shadow_walk_okay(&it) && it.level > gw->level; | |
616 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
617 | gfn_t table_gfn; |
618 | ||
a30f47cb | 619 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 620 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 621 | |
5991b332 | 622 | sp = NULL; |
24157aaf AK |
623 | if (!is_shadow_present_pte(*it.sptep)) { |
624 | table_gfn = gw->table_gfn[it.level - 2]; | |
625 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
bb11c6c9 | 626 | false, access); |
5991b332 | 627 | } |
0b3c9333 AK |
628 | |
629 | /* | |
630 | * Verify that the gpte in the page we've just write | |
631 | * protected is still there. | |
632 | */ | |
24157aaf | 633 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 634 | goto out_gpte_changed; |
abb9e0b8 | 635 | |
5991b332 | 636 | if (sp) |
98bba238 | 637 | link_shadow_page(vcpu, it.sptep, sp); |
e7a04c99 | 638 | } |
050e6499 | 639 | |
0b3c9333 | 640 | for (; |
24157aaf AK |
641 | shadow_walk_okay(&it) && it.level > hlevel; |
642 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
643 | gfn_t direct_gfn; |
644 | ||
a30f47cb | 645 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 646 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 647 | |
24157aaf | 648 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 649 | |
24157aaf | 650 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
651 | continue; |
652 | ||
24157aaf | 653 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 654 | |
24157aaf | 655 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
bb11c6c9 | 656 | true, direct_access); |
98bba238 | 657 | link_shadow_page(vcpu, it.sptep, sp); |
0b3c9333 AK |
658 | } |
659 | ||
a30f47cb | 660 | clear_sp_write_flooding_count(it.sptep); |
029499b4 TY |
661 | emulate = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, |
662 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 663 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 664 | |
d4878f24 | 665 | return emulate; |
0b3c9333 AK |
666 | |
667 | out_gpte_changed: | |
0b3c9333 | 668 | kvm_release_pfn_clean(pfn); |
d4878f24 | 669 | return 0; |
6aa8b732 AK |
670 | } |
671 | ||
7751babd XG |
672 | /* |
673 | * To see whether the mapped gfn can write its page table in the current | |
674 | * mapping. | |
675 | * | |
676 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
677 | * size to map the writable gfn which is used as current page table, we should | |
678 | * force kvm to use small page size to map it because new shadow page will be | |
679 | * created when kvm establishes shadow page table that stop kvm using large | |
680 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
681 | * | |
93c05d3e XG |
682 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
683 | * currently used as its page table. | |
684 | * | |
7751babd XG |
685 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
686 | * since the PDPT is always shadowed, that means, we can not use large page | |
687 | * size to map the gfn which is used as PDPT. | |
688 | */ | |
689 | static bool | |
690 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
691 | struct guest_walker *walker, int user_fault, |
692 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
693 | { |
694 | int level; | |
695 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 696 | bool self_changed = false; |
7751babd XG |
697 | |
698 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
699 | (!is_write_protection(vcpu) && !user_fault))) | |
700 | return false; | |
701 | ||
93c05d3e XG |
702 | for (level = walker->level; level <= walker->max_level; level++) { |
703 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
704 | ||
705 | self_changed |= !(gfn & mask); | |
706 | *write_fault_to_shadow_pgtable |= !gfn; | |
707 | } | |
7751babd | 708 | |
93c05d3e | 709 | return self_changed; |
7751babd XG |
710 | } |
711 | ||
6aa8b732 AK |
712 | /* |
713 | * Page fault handler. There are several causes for a page fault: | |
714 | * - there is no shadow pte for the guest pte | |
715 | * - write access through a shadow pte marked read only so that we can set | |
716 | * the dirty bit | |
717 | * - write access to a shadow pte marked read only so we can update the page | |
718 | * dirty bitmap, when userspace requests it | |
719 | * - mmio access; in this case we will never install a present shadow pte | |
720 | * - normal guest page fault due to the guest pte marked not present, not | |
721 | * writable, or not executable | |
722 | * | |
e2dec939 AK |
723 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
724 | * a negative value on error. | |
6aa8b732 | 725 | */ |
56028d08 | 726 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 727 | bool prefault) |
6aa8b732 AK |
728 | { |
729 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
730 | int user_fault = error_code & PFERR_USER_MASK; |
731 | struct guest_walker walker; | |
e2dec939 | 732 | int r; |
ba049e93 | 733 | kvm_pfn_t pfn; |
7e4e4056 | 734 | int level = PT_PAGE_TABLE_LEVEL; |
8c85ac1c | 735 | bool force_pt_level = false; |
e930bffe | 736 | unsigned long mmu_seq; |
93c05d3e | 737 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 738 | |
b8688d51 | 739 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 740 | |
e2dec939 AK |
741 | r = mmu_topup_memory_caches(vcpu); |
742 | if (r) | |
743 | return r; | |
714b93da | 744 | |
e9ee956e TY |
745 | /* |
746 | * If PFEC.RSVD is set, this is a shadow page fault. | |
747 | * The bit needs to be cleared before walking guest page tables. | |
748 | */ | |
749 | error_code &= ~PFERR_RSVD_MASK; | |
750 | ||
6aa8b732 | 751 | /* |
a8b876b1 | 752 | * Look up the guest pte for the faulting address. |
6aa8b732 | 753 | */ |
33770780 | 754 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
755 | |
756 | /* | |
757 | * The page is not mapped by the guest. Let the guest handle it. | |
758 | */ | |
7993ba43 | 759 | if (!r) { |
b8688d51 | 760 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 761 | if (!prefault) |
fb67e14f | 762 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 763 | |
6aa8b732 AK |
764 | return 0; |
765 | } | |
766 | ||
e5691a81 XG |
767 | if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) { |
768 | shadow_page_table_clear_flood(vcpu, addr); | |
3d0c27ad | 769 | return 1; |
e5691a81 | 770 | } |
3d0c27ad | 771 | |
93c05d3e XG |
772 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
773 | ||
774 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
775 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
776 | ||
5ed5c5c8 | 777 | if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) { |
fd136902 TY |
778 | level = mapping_level(vcpu, walker.gfn, &force_pt_level); |
779 | if (likely(!force_pt_level)) { | |
780 | level = min(walker.level, level); | |
5ed5c5c8 TY |
781 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); |
782 | } | |
783 | } else | |
cd1872f0 | 784 | force_pt_level = true; |
7e4e4056 | 785 | |
e930bffe | 786 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 787 | smp_rmb(); |
af585b92 | 788 | |
78b2c54a | 789 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 790 | &map_writable)) |
af585b92 | 791 | return 0; |
d7824fff | 792 | |
d7c55201 XG |
793 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
794 | walker.gfn, pfn, walker.pte_access, &r)) | |
795 | return r; | |
796 | ||
c2288505 XG |
797 | /* |
798 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
799 | * we will cache the incorrect access into mmio spte. | |
800 | */ | |
801 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
802 | !is_write_protection(vcpu) && !user_fault && | |
803 | !is_noslot_pfn(pfn)) { | |
804 | walker.pte_access |= ACC_WRITE_MASK; | |
805 | walker.pte_access &= ~ACC_USER_MASK; | |
806 | ||
807 | /* | |
808 | * If we converted a user page to a kernel page, | |
809 | * so that the kernel can write to it when cr0.wp=0, | |
810 | * then we should prevent the kernel from executing it | |
811 | * if SMEP is enabled. | |
812 | */ | |
813 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
814 | walker.pte_access &= ~ACC_EXEC_MASK; | |
815 | } | |
816 | ||
aaee2c94 | 817 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 818 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 819 | goto out_unlock; |
bc32ce21 | 820 | |
0375f7fa | 821 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
26eeb53c WL |
822 | if (make_mmu_pages_available(vcpu) < 0) |
823 | goto out_unlock; | |
936a5fe6 AA |
824 | if (!force_pt_level) |
825 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 826 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 827 | level, pfn, map_writable, prefault); |
1165f5fe | 828 | ++vcpu->stat.pf_fixed; |
0375f7fa | 829 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 830 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 831 | |
d4878f24 | 832 | return r; |
e930bffe AA |
833 | |
834 | out_unlock: | |
835 | spin_unlock(&vcpu->kvm->mmu_lock); | |
836 | kvm_release_pfn_clean(pfn); | |
837 | return 0; | |
6aa8b732 AK |
838 | } |
839 | ||
505aef8f XG |
840 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
841 | { | |
842 | int offset = 0; | |
843 | ||
f71fa31f | 844 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
845 | |
846 | if (PTTYPE == 32) | |
847 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
848 | ||
849 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
850 | } | |
851 | ||
a461930b | 852 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 853 | { |
a461930b | 854 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 855 | struct kvm_mmu_page *sp; |
a461930b AK |
856 | int level; |
857 | u64 *sptep; | |
858 | ||
bebb106a XG |
859 | vcpu_clear_mmio_info(vcpu, gva); |
860 | ||
f57f2ef5 XG |
861 | /* |
862 | * No need to check return value here, rmap_can_add() can | |
863 | * help us to skip pte prefetch later. | |
864 | */ | |
865 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 866 | |
37f6a4e2 MT |
867 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) { |
868 | WARN_ON(1); | |
869 | return; | |
870 | } | |
871 | ||
f57f2ef5 | 872 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
873 | for_each_shadow_entry(vcpu, gva, iterator) { |
874 | level = iterator.level; | |
875 | sptep = iterator.sptep; | |
ad218f85 | 876 | |
f78978aa | 877 | sp = page_header(__pa(sptep)); |
884a0ff0 | 878 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
879 | pt_element_t gpte; |
880 | gpa_t pte_gpa; | |
881 | ||
f78978aa XG |
882 | if (!sp->unsync) |
883 | break; | |
884 | ||
505aef8f | 885 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 886 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 887 | |
505aef8f XG |
888 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
889 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
890 | |
891 | if (!rmap_can_add(vcpu)) | |
892 | break; | |
893 | ||
54bf36aa PB |
894 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
895 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
896 | break; |
897 | ||
898 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 899 | } |
a7052897 | 900 | |
f78978aa | 901 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
902 | break; |
903 | } | |
ad218f85 | 904 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
905 | } |
906 | ||
1871c602 | 907 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 908 | struct x86_exception *exception) |
6aa8b732 AK |
909 | { |
910 | struct guest_walker walker; | |
e119d117 AK |
911 | gpa_t gpa = UNMAPPED_GVA; |
912 | int r; | |
6aa8b732 | 913 | |
33770780 | 914 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 915 | |
e119d117 | 916 | if (r) { |
1755fbcc | 917 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 918 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
919 | } else if (exception) |
920 | *exception = walker.fault; | |
6aa8b732 AK |
921 | |
922 | return gpa; | |
923 | } | |
924 | ||
37406aaa | 925 | #if PTTYPE != PTTYPE_EPT |
6539e738 | 926 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
927 | u32 access, |
928 | struct x86_exception *exception) | |
6539e738 JR |
929 | { |
930 | struct guest_walker walker; | |
931 | gpa_t gpa = UNMAPPED_GVA; | |
932 | int r; | |
933 | ||
33770780 | 934 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
935 | |
936 | if (r) { | |
937 | gpa = gfn_to_gpa(walker.gfn); | |
938 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
939 | } else if (exception) |
940 | *exception = walker.fault; | |
6539e738 JR |
941 | |
942 | return gpa; | |
943 | } | |
37406aaa | 944 | #endif |
6539e738 | 945 | |
e8bc217a MT |
946 | /* |
947 | * Using the cached information from sp->gfns is safe because: | |
948 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
949 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
950 | * |
951 | * Note: | |
952 | * We should flush all tlbs if spte is dropped even though guest is | |
953 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
954 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
955 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
956 | * freed pages. | |
a086f6a1 | 957 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 958 | */ |
a4a8e6f7 | 959 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 960 | { |
505aef8f | 961 | int i, nr_present = 0; |
9bdbba13 | 962 | bool host_writable; |
51fb60d8 | 963 | gpa_t first_pte_gpa; |
e8bc217a | 964 | |
2032a93d LJ |
965 | /* direct kvm_mmu_page can not be unsync. */ |
966 | BUG_ON(sp->role.direct); | |
967 | ||
505aef8f | 968 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 969 | |
e8bc217a MT |
970 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
971 | unsigned pte_access; | |
972 | pt_element_t gpte; | |
973 | gpa_t pte_gpa; | |
f55c3f41 | 974 | gfn_t gfn; |
e8bc217a | 975 | |
ce88decf | 976 | if (!sp->spt[i]) |
e8bc217a MT |
977 | continue; |
978 | ||
51fb60d8 | 979 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 980 | |
54bf36aa PB |
981 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
982 | sizeof(pt_element_t))) | |
1f50f1b3 | 983 | return 0; |
e8bc217a | 984 | |
0ad805a0 | 985 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
7bfdf217 LT |
986 | /* |
987 | * Update spte before increasing tlbs_dirty to make | |
988 | * sure no tlb flush is lost after spte is zapped; see | |
989 | * the comments in kvm_flush_remote_tlbs(). | |
990 | */ | |
991 | smp_wmb(); | |
a086f6a1 | 992 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
993 | continue; |
994 | } | |
995 | ||
ce88decf XG |
996 | gfn = gpte_to_gfn(gpte); |
997 | pte_access = sp->role.access; | |
0ad805a0 | 998 | pte_access &= FNAME(gpte_access)(vcpu, gpte); |
86407bcb | 999 | FNAME(protect_clean_gpte)(&vcpu->arch.mmu, &pte_access, gpte); |
ce88decf | 1000 | |
54bf36aa | 1001 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 1002 | &nr_present)) |
ce88decf XG |
1003 | continue; |
1004 | ||
407c61c6 | 1005 | if (gfn != sp->gfns[i]) { |
c3707958 | 1006 | drop_spte(vcpu->kvm, &sp->spt[i]); |
7bfdf217 LT |
1007 | /* |
1008 | * The same as above where we are doing | |
1009 | * prefetch_invalid_gpte(). | |
1010 | */ | |
1011 | smp_wmb(); | |
a086f6a1 | 1012 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
1013 | continue; |
1014 | } | |
1015 | ||
1016 | nr_present++; | |
ce88decf | 1017 | |
f8e453b0 XG |
1018 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
1019 | ||
c2288505 | 1020 | set_spte(vcpu, &sp->spt[i], pte_access, |
640d9b0d | 1021 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 1022 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 1023 | host_writable); |
e8bc217a MT |
1024 | } |
1025 | ||
1f50f1b3 | 1026 | return nr_present; |
e8bc217a MT |
1027 | } |
1028 | ||
6aa8b732 AK |
1029 | #undef pt_element_t |
1030 | #undef guest_walker | |
1031 | #undef FNAME | |
1032 | #undef PT_BASE_ADDR_MASK | |
1033 | #undef PT_INDEX | |
e04da980 JR |
1034 | #undef PT_LVL_ADDR_MASK |
1035 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 1036 | #undef PT_LEVEL_BITS |
cea0f0e7 | 1037 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 1038 | #undef gpte_to_gfn |
e04da980 | 1039 | #undef gpte_to_gfn_lvl |
b3e4e63f | 1040 | #undef CMPXCHG |
d8089bac GN |
1041 | #undef PT_GUEST_ACCESSED_MASK |
1042 | #undef PT_GUEST_DIRTY_MASK | |
1043 | #undef PT_GUEST_DIRTY_SHIFT | |
1044 | #undef PT_GUEST_ACCESSED_SHIFT | |
86407bcb | 1045 | #undef PT_HAVE_ACCESSED_DIRTY |