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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
6aa8b732 | 34 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) |
c7addb90 | 35 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
36 | #ifdef CONFIG_X86_64 |
37 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 38 | #define CMPXCHG cmpxchg |
cea0f0e7 | 39 | #else |
b3e4e63f | 40 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
41 | #define PT_MAX_FULL_LEVELS 2 |
42 | #endif | |
6aa8b732 AK |
43 | #elif PTTYPE == 32 |
44 | #define pt_element_t u32 | |
45 | #define guest_walker guest_walker32 | |
46 | #define FNAME(name) paging##32_##name | |
47 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
48 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
49 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 50 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
6aa8b732 | 51 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) |
c7addb90 | 52 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 53 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 54 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
55 | #else |
56 | #error Invalid PTTYPE value | |
57 | #endif | |
58 | ||
e04da980 JR |
59 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
60 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 61 | |
6aa8b732 AK |
62 | /* |
63 | * The guest_walker structure emulates the behavior of the hardware page | |
64 | * table walker. | |
65 | */ | |
66 | struct guest_walker { | |
67 | int level; | |
cea0f0e7 | 68 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 69 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 70 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 71 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
72 | unsigned pt_access; |
73 | unsigned pte_access; | |
815af8d4 | 74 | gfn_t gfn; |
7993ba43 | 75 | u32 error_code; |
6aa8b732 AK |
76 | }; |
77 | ||
e04da980 | 78 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 79 | { |
e04da980 | 80 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
81 | } |
82 | ||
b3e4e63f MT |
83 | static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, |
84 | gfn_t table_gfn, unsigned index, | |
85 | pt_element_t orig_pte, pt_element_t new_pte) | |
86 | { | |
87 | pt_element_t ret; | |
88 | pt_element_t *table; | |
89 | struct page *page; | |
90 | ||
91 | page = gfn_to_page(kvm, table_gfn); | |
72dc67a6 | 92 | |
b3e4e63f | 93 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 94 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
95 | kunmap_atomic(table, KM_USER0); |
96 | ||
97 | kvm_release_page_dirty(page); | |
98 | ||
99 | return (ret != orig_pte); | |
100 | } | |
101 | ||
bedbe4ee AK |
102 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
103 | { | |
104 | unsigned access; | |
105 | ||
106 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
107 | #if PTTYPE == 64 | |
108 | if (is_nx(vcpu)) | |
109 | access &= ~(gpte >> PT64_NX_SHIFT); | |
110 | #endif | |
111 | return access; | |
112 | } | |
113 | ||
ac79c978 AK |
114 | /* |
115 | * Fetch a guest pte for a guest virtual address | |
116 | */ | |
1e301feb JR |
117 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
118 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
119 | gva_t addr, int write_fault, | |
120 | int user_fault, int fetch_fault) | |
6aa8b732 | 121 | { |
42bf3f0a | 122 | pt_element_t pte; |
cea0f0e7 | 123 | gfn_t table_gfn; |
f59c1d2d | 124 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 125 | gpa_t pte_gpa; |
f59c1d2d | 126 | bool eperm, present, rsvd_fault; |
2329d46d JR |
127 | int offset; |
128 | u32 access = 0; | |
6aa8b732 | 129 | |
07420171 AK |
130 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
131 | fetch_fault); | |
b3e4e63f | 132 | walk: |
f59c1d2d AK |
133 | present = true; |
134 | eperm = rsvd_fault = false; | |
1e301feb JR |
135 | walker->level = mmu->root_level; |
136 | pte = mmu->get_cr3(vcpu); | |
137 | ||
1b0973bd | 138 | #if PTTYPE == 64 |
1e301feb | 139 | if (walker->level == PT32E_ROOT_LEVEL) { |
d41d1895 | 140 | pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3); |
07420171 | 141 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
142 | if (!is_present_gpte(pte)) { |
143 | present = false; | |
144 | goto error; | |
145 | } | |
1b0973bd AK |
146 | --walker->level; |
147 | } | |
148 | #endif | |
a9058ecd | 149 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 150 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 151 | |
fe135d2c | 152 | pt_access = ACC_ALL; |
ac79c978 AK |
153 | |
154 | for (;;) { | |
42bf3f0a | 155 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 156 | |
5fb07ddb | 157 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
158 | offset = index * sizeof(pt_element_t); |
159 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 160 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 161 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 162 | |
2329d46d JR |
163 | if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte, |
164 | offset, sizeof(pte), | |
165 | PFERR_USER_MASK|PFERR_WRITE_MASK)) { | |
f59c1d2d AK |
166 | present = false; |
167 | break; | |
168 | } | |
a6085fba | 169 | |
07420171 | 170 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 171 | |
f59c1d2d AK |
172 | if (!is_present_gpte(pte)) { |
173 | present = false; | |
174 | break; | |
175 | } | |
7993ba43 | 176 | |
3241f22d | 177 | if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) { |
f59c1d2d AK |
178 | rsvd_fault = true; |
179 | break; | |
180 | } | |
82725b20 | 181 | |
8dae4445 | 182 | if (write_fault && !is_writable_pte(pte)) |
7993ba43 | 183 | if (user_fault || is_write_protection(vcpu)) |
f59c1d2d | 184 | eperm = true; |
7993ba43 | 185 | |
42bf3f0a | 186 | if (user_fault && !(pte & PT_USER_MASK)) |
f59c1d2d | 187 | eperm = true; |
7993ba43 | 188 | |
73b1087e | 189 | #if PTTYPE == 64 |
24222c2f | 190 | if (fetch_fault && (pte & PT64_NX_MASK)) |
f59c1d2d | 191 | eperm = true; |
73b1087e AK |
192 | #endif |
193 | ||
f59c1d2d | 194 | if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) { |
07420171 AK |
195 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
196 | sizeof(pte)); | |
b3e4e63f MT |
197 | if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, |
198 | index, pte, pte|PT_ACCESSED_MASK)) | |
199 | goto walk; | |
f3b8c964 | 200 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 201 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 202 | } |
815af8d4 | 203 | |
bedbe4ee | 204 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 205 | |
7819026e MT |
206 | walker->ptes[walker->level - 1] = pte; |
207 | ||
e04da980 JR |
208 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
209 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 210 | is_large_pte(pte) && |
e04da980 JR |
211 | (PTTYPE == 64 || is_pse(vcpu))) || |
212 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 213 | is_large_pte(pte) && |
1e301feb | 214 | mmu->root_level == PT64_ROOT_LEVEL)) { |
e04da980 | 215 | int lvl = walker->level; |
2329d46d JR |
216 | gpa_t real_gpa; |
217 | gfn_t gfn; | |
e04da980 | 218 | |
2329d46d JR |
219 | gfn = gpte_to_gfn_lvl(pte, lvl); |
220 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
221 | |
222 | if (PTTYPE == 32 && | |
223 | walker->level == PT_DIRECTORY_LEVEL && | |
224 | is_cpuid_PSE36()) | |
2329d46d JR |
225 | gfn += pse36_gfn_delta(pte); |
226 | ||
227 | access |= write_fault ? PFERR_WRITE_MASK : 0; | |
228 | access |= fetch_fault ? PFERR_FETCH_MASK : 0; | |
229 | access |= user_fault ? PFERR_USER_MASK : 0; | |
230 | ||
231 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
232 | access); | |
233 | if (real_gpa == UNMAPPED_GVA) | |
234 | return 0; | |
235 | ||
236 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 237 | |
ac79c978 | 238 | break; |
815af8d4 | 239 | } |
ac79c978 | 240 | |
fe135d2c | 241 | pt_access = pte_access; |
ac79c978 AK |
242 | --walker->level; |
243 | } | |
42bf3f0a | 244 | |
f59c1d2d AK |
245 | if (!present || eperm || rsvd_fault) |
246 | goto error; | |
247 | ||
43a3795a | 248 | if (write_fault && !is_dirty_gpte(pte)) { |
b3e4e63f MT |
249 | bool ret; |
250 | ||
07420171 | 251 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
b3e4e63f MT |
252 | ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte, |
253 | pte|PT_DIRTY_MASK); | |
254 | if (ret) | |
255 | goto walk; | |
f3b8c964 | 256 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 257 | pte |= PT_DIRTY_MASK; |
7819026e | 258 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
259 | } |
260 | ||
fe135d2c AK |
261 | walker->pt_access = pt_access; |
262 | walker->pte_access = pte_access; | |
263 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 264 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
265 | return 1; |
266 | ||
f59c1d2d | 267 | error: |
7993ba43 | 268 | walker->error_code = 0; |
f59c1d2d AK |
269 | if (present) |
270 | walker->error_code |= PFERR_PRESENT_MASK; | |
7993ba43 AK |
271 | if (write_fault) |
272 | walker->error_code |= PFERR_WRITE_MASK; | |
273 | if (user_fault) | |
274 | walker->error_code |= PFERR_USER_MASK; | |
b0eeec29 | 275 | if (fetch_fault && is_nx(vcpu)) |
73b1087e | 276 | walker->error_code |= PFERR_FETCH_MASK; |
82725b20 DE |
277 | if (rsvd_fault) |
278 | walker->error_code |= PFERR_RSVD_MASK; | |
8df25a32 JR |
279 | |
280 | vcpu->arch.fault.address = addr; | |
281 | vcpu->arch.fault.error_code = walker->error_code; | |
282 | ||
07420171 | 283 | trace_kvm_mmu_walker_error(walker->error_code); |
fe551881 | 284 | return 0; |
6aa8b732 AK |
285 | } |
286 | ||
1e301feb JR |
287 | static int FNAME(walk_addr)(struct guest_walker *walker, |
288 | struct kvm_vcpu *vcpu, gva_t addr, | |
289 | int write_fault, int user_fault, int fetch_fault) | |
290 | { | |
291 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
292 | write_fault, user_fault, fetch_fault); | |
293 | } | |
294 | ||
6539e738 JR |
295 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
296 | struct kvm_vcpu *vcpu, gva_t addr, | |
297 | int write_fault, int user_fault, | |
298 | int fetch_fault) | |
299 | { | |
300 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
301 | addr, write_fault, user_fault, | |
302 | fetch_fault); | |
303 | } | |
304 | ||
ac3cd03c | 305 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
489f1d65 | 306 | u64 *spte, const void *pte) |
0028425f AK |
307 | { |
308 | pt_element_t gpte; | |
41074d07 | 309 | unsigned pte_access; |
35149e21 | 310 | pfn_t pfn; |
fbc5d139 | 311 | u64 new_spte; |
0028425f | 312 | |
0028425f | 313 | gpte = *(const pt_element_t *)pte; |
c7addb90 | 314 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
fbc5d139 | 315 | if (!is_present_gpte(gpte)) { |
ac3cd03c | 316 | if (sp->unsync) |
fbc5d139 AK |
317 | new_spte = shadow_trap_nonpresent_pte; |
318 | else | |
319 | new_spte = shadow_notrap_nonpresent_pte; | |
320 | __set_spte(spte, new_spte); | |
321 | } | |
c7addb90 AK |
322 | return; |
323 | } | |
b8688d51 | 324 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 325 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
d7824fff AK |
326 | if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn) |
327 | return; | |
35149e21 AL |
328 | pfn = vcpu->arch.update_pte.pfn; |
329 | if (is_error_pfn(pfn)) | |
d7824fff | 330 | return; |
e930bffe AA |
331 | if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq)) |
332 | return; | |
35149e21 | 333 | kvm_get_pfn(pfn); |
1403283a IE |
334 | /* |
335 | * we call mmu_set_spte() with reset_host_protection = true beacuse that | |
336 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). | |
337 | */ | |
ac3cd03c | 338 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 339 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 340 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
341 | } |
342 | ||
39c8c672 AK |
343 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
344 | struct guest_walker *gw, int level) | |
345 | { | |
39c8c672 | 346 | pt_element_t curr_pte; |
189be38d XG |
347 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
348 | u64 mask; | |
349 | int r, index; | |
350 | ||
351 | if (level == PT_PAGE_TABLE_LEVEL) { | |
352 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
353 | base_gpa = pte_gpa & ~mask; | |
354 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
355 | ||
356 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
357 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
358 | curr_pte = gw->prefetch_ptes[index]; | |
359 | } else | |
360 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 361 | &curr_pte, sizeof(curr_pte)); |
189be38d | 362 | |
39c8c672 AK |
363 | return r || curr_pte != gw->ptes[level - 1]; |
364 | } | |
365 | ||
189be38d XG |
366 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
367 | u64 *sptep) | |
957ed9ef XG |
368 | { |
369 | struct kvm_mmu_page *sp; | |
3241f22d | 370 | struct kvm_mmu *mmu = &vcpu->arch.mmu; |
189be38d | 371 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 372 | u64 *spte; |
189be38d | 373 | int i; |
957ed9ef XG |
374 | |
375 | sp = page_header(__pa(sptep)); | |
376 | ||
377 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
378 | return; | |
379 | ||
380 | if (sp->role.direct) | |
381 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
382 | ||
383 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
384 | spte = sp->spt + i; |
385 | ||
386 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
387 | pt_element_t gpte; | |
388 | unsigned pte_access; | |
389 | gfn_t gfn; | |
390 | pfn_t pfn; | |
391 | bool dirty; | |
392 | ||
393 | if (spte == sptep) | |
394 | continue; | |
395 | ||
396 | if (*spte != shadow_trap_nonpresent_pte) | |
397 | continue; | |
398 | ||
399 | gpte = gptep[i]; | |
400 | ||
401 | if (!is_present_gpte(gpte) || | |
3241f22d | 402 | is_rsvd_bits_set(mmu, gpte, PT_PAGE_TABLE_LEVEL)) { |
957ed9ef XG |
403 | if (!sp->unsync) |
404 | __set_spte(spte, shadow_notrap_nonpresent_pte); | |
405 | continue; | |
406 | } | |
407 | ||
408 | if (!(gpte & PT_ACCESSED_MASK)) | |
409 | continue; | |
410 | ||
411 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
412 | gfn = gpte_to_gfn(gpte); | |
413 | dirty = is_dirty_gpte(gpte); | |
414 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
415 | (pte_access & ACC_WRITE_MASK) && dirty); | |
416 | if (is_error_pfn(pfn)) { | |
417 | kvm_release_pfn_clean(pfn); | |
418 | break; | |
419 | } | |
420 | ||
421 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
422 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
423 | pfn, true, true); | |
424 | } | |
425 | } | |
426 | ||
6aa8b732 AK |
427 | /* |
428 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
429 | */ | |
e7a04c99 AK |
430 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
431 | struct guest_walker *gw, | |
7e4e4056 | 432 | int user_fault, int write_fault, int hlevel, |
e7a04c99 | 433 | int *ptwrite, pfn_t pfn) |
6aa8b732 | 434 | { |
abb9e0b8 | 435 | unsigned access = gw->pt_access; |
5991b332 | 436 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 437 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 438 | int top_level; |
84754cd8 | 439 | unsigned direct_access; |
24157aaf | 440 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 441 | |
43a3795a | 442 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 443 | return NULL; |
6aa8b732 | 444 | |
84754cd8 XG |
445 | direct_access = gw->pt_access & gw->pte_access; |
446 | if (!dirty) | |
447 | direct_access &= ~ACC_WRITE_MASK; | |
448 | ||
5991b332 AK |
449 | top_level = vcpu->arch.mmu.root_level; |
450 | if (top_level == PT32E_ROOT_LEVEL) | |
451 | top_level = PT32_ROOT_LEVEL; | |
452 | /* | |
453 | * Verify that the top-level gpte is still there. Since the page | |
454 | * is a root page, it is either write protected (and cannot be | |
455 | * changed from now on) or it is invalid (in which case, we don't | |
456 | * really care if it changes underneath us after this point). | |
457 | */ | |
458 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
459 | goto out_gpte_changed; | |
460 | ||
24157aaf AK |
461 | for (shadow_walk_init(&it, vcpu, addr); |
462 | shadow_walk_okay(&it) && it.level > gw->level; | |
463 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
464 | gfn_t table_gfn; |
465 | ||
24157aaf | 466 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 467 | |
5991b332 | 468 | sp = NULL; |
24157aaf AK |
469 | if (!is_shadow_present_pte(*it.sptep)) { |
470 | table_gfn = gw->table_gfn[it.level - 2]; | |
471 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
472 | false, access, it.sptep); | |
5991b332 | 473 | } |
0b3c9333 AK |
474 | |
475 | /* | |
476 | * Verify that the gpte in the page we've just write | |
477 | * protected is still there. | |
478 | */ | |
24157aaf | 479 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 480 | goto out_gpte_changed; |
abb9e0b8 | 481 | |
5991b332 | 482 | if (sp) |
24157aaf | 483 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 484 | } |
050e6499 | 485 | |
0b3c9333 | 486 | for (; |
24157aaf AK |
487 | shadow_walk_okay(&it) && it.level > hlevel; |
488 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
489 | gfn_t direct_gfn; |
490 | ||
24157aaf | 491 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 492 | |
24157aaf | 493 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 494 | |
24157aaf | 495 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
496 | continue; |
497 | ||
24157aaf | 498 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 499 | |
24157aaf AK |
500 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
501 | true, direct_access, it.sptep); | |
502 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
503 | } |
504 | ||
24157aaf AK |
505 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
506 | user_fault, write_fault, dirty, ptwrite, it.level, | |
0b3c9333 | 507 | gw->gfn, pfn, false, true); |
189be38d | 508 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 509 | |
24157aaf | 510 | return it.sptep; |
0b3c9333 AK |
511 | |
512 | out_gpte_changed: | |
5991b332 | 513 | if (sp) |
24157aaf | 514 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
515 | kvm_release_pfn_clean(pfn); |
516 | return NULL; | |
6aa8b732 AK |
517 | } |
518 | ||
6aa8b732 AK |
519 | /* |
520 | * Page fault handler. There are several causes for a page fault: | |
521 | * - there is no shadow pte for the guest pte | |
522 | * - write access through a shadow pte marked read only so that we can set | |
523 | * the dirty bit | |
524 | * - write access to a shadow pte marked read only so we can update the page | |
525 | * dirty bitmap, when userspace requests it | |
526 | * - mmio access; in this case we will never install a present shadow pte | |
527 | * - normal guest page fault due to the guest pte marked not present, not | |
528 | * writable, or not executable | |
529 | * | |
e2dec939 AK |
530 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
531 | * a negative value on error. | |
6aa8b732 AK |
532 | */ |
533 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
534 | u32 error_code) | |
535 | { | |
536 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 537 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 538 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 | 539 | struct guest_walker walker; |
d555c333 | 540 | u64 *sptep; |
cea0f0e7 | 541 | int write_pt = 0; |
e2dec939 | 542 | int r; |
35149e21 | 543 | pfn_t pfn; |
7e4e4056 | 544 | int level = PT_PAGE_TABLE_LEVEL; |
e930bffe | 545 | unsigned long mmu_seq; |
6aa8b732 | 546 | |
b8688d51 | 547 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 548 | |
e2dec939 AK |
549 | r = mmu_topup_memory_caches(vcpu); |
550 | if (r) | |
551 | return r; | |
714b93da | 552 | |
6aa8b732 | 553 | /* |
a8b876b1 | 554 | * Look up the guest pte for the faulting address. |
6aa8b732 | 555 | */ |
73b1087e AK |
556 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
557 | fetch_fault); | |
6aa8b732 AK |
558 | |
559 | /* | |
560 | * The page is not mapped by the guest. Let the guest handle it. | |
561 | */ | |
7993ba43 | 562 | if (!r) { |
b8688d51 | 563 | pgprintk("%s: guest page fault\n", __func__); |
8df25a32 | 564 | inject_page_fault(vcpu); |
ad312c7c | 565 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
566 | return 0; |
567 | } | |
568 | ||
7e4e4056 JR |
569 | if (walker.level >= PT_DIRECTORY_LEVEL) { |
570 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); | |
571 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 572 | } |
7e4e4056 | 573 | |
e930bffe | 574 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 575 | smp_rmb(); |
35149e21 | 576 | pfn = gfn_to_pfn(vcpu->kvm, walker.gfn); |
d7824fff | 577 | |
d196e343 | 578 | /* mmio */ |
bf998156 HY |
579 | if (is_error_pfn(pfn)) |
580 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 581 | |
aaee2c94 | 582 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
583 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
584 | goto out_unlock; | |
bc32ce21 | 585 | |
8b1fe17c | 586 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 587 | kvm_mmu_free_some_pages(vcpu); |
d555c333 | 588 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
7e4e4056 | 589 | level, &write_pt, pfn); |
a24e8099 | 590 | (void)sptep; |
b8688d51 | 591 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 592 | sptep, *sptep, write_pt); |
cea0f0e7 | 593 | |
a25f7e1f | 594 | if (!write_pt) |
ad312c7c | 595 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 596 | |
1165f5fe | 597 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 598 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 599 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 600 | |
cea0f0e7 | 601 | return write_pt; |
e930bffe AA |
602 | |
603 | out_unlock: | |
604 | spin_unlock(&vcpu->kvm->mmu_lock); | |
605 | kvm_release_pfn_clean(pfn); | |
606 | return 0; | |
6aa8b732 AK |
607 | } |
608 | ||
a461930b | 609 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 610 | { |
a461930b | 611 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 612 | struct kvm_mmu_page *sp; |
08e850c6 | 613 | gpa_t pte_gpa = -1; |
a461930b AK |
614 | int level; |
615 | u64 *sptep; | |
4539b358 | 616 | int need_flush = 0; |
a461930b AK |
617 | |
618 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 619 | |
a461930b AK |
620 | for_each_shadow_entry(vcpu, gva, iterator) { |
621 | level = iterator.level; | |
622 | sptep = iterator.sptep; | |
ad218f85 | 623 | |
f78978aa | 624 | sp = page_header(__pa(sptep)); |
884a0ff0 | 625 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 626 | int offset, shift; |
08e850c6 | 627 | |
f78978aa XG |
628 | if (!sp->unsync) |
629 | break; | |
630 | ||
22c9b2d1 XG |
631 | shift = PAGE_SHIFT - |
632 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
633 | offset = sp->role.quadrant << shift; | |
634 | ||
635 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 636 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
637 | |
638 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
639 | if (is_large_pte(*sptep)) |
640 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
641 | drop_spte(vcpu->kvm, sptep, |
642 | shadow_trap_nonpresent_pte); | |
4539b358 | 643 | need_flush = 1; |
be38d276 AK |
644 | } else |
645 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 646 | break; |
87917239 | 647 | } |
a7052897 | 648 | |
f78978aa | 649 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
650 | break; |
651 | } | |
a7052897 | 652 | |
4539b358 AA |
653 | if (need_flush) |
654 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
655 | |
656 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
657 | ||
ad218f85 | 658 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
659 | |
660 | if (pte_gpa == -1) | |
661 | return; | |
662 | ||
663 | if (mmu_topup_memory_caches(vcpu)) | |
664 | return; | |
665 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
666 | } |
667 | ||
1871c602 GN |
668 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
669 | u32 *error) | |
6aa8b732 AK |
670 | { |
671 | struct guest_walker walker; | |
e119d117 AK |
672 | gpa_t gpa = UNMAPPED_GVA; |
673 | int r; | |
6aa8b732 | 674 | |
1871c602 GN |
675 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, |
676 | !!(access & PFERR_WRITE_MASK), | |
677 | !!(access & PFERR_USER_MASK), | |
678 | !!(access & PFERR_FETCH_MASK)); | |
6aa8b732 | 679 | |
e119d117 | 680 | if (r) { |
1755fbcc | 681 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 682 | gpa |= vaddr & ~PAGE_MASK; |
1871c602 GN |
683 | } else if (error) |
684 | *error = walker.error_code; | |
6aa8b732 AK |
685 | |
686 | return gpa; | |
687 | } | |
688 | ||
6539e738 JR |
689 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
690 | u32 access, u32 *error) | |
691 | { | |
692 | struct guest_walker walker; | |
693 | gpa_t gpa = UNMAPPED_GVA; | |
694 | int r; | |
695 | ||
696 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, | |
697 | access & PFERR_WRITE_MASK, | |
698 | access & PFERR_USER_MASK, | |
699 | access & PFERR_FETCH_MASK); | |
700 | ||
701 | if (r) { | |
702 | gpa = gfn_to_gpa(walker.gfn); | |
703 | gpa |= vaddr & ~PAGE_MASK; | |
704 | } else if (error) | |
705 | *error = walker.error_code; | |
706 | ||
707 | return gpa; | |
708 | } | |
709 | ||
c7addb90 AK |
710 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
711 | struct kvm_mmu_page *sp) | |
712 | { | |
eab9f71f AK |
713 | int i, j, offset, r; |
714 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
715 | gpa_t pte_gpa; | |
c7addb90 | 716 | |
f6e2c02b | 717 | if (sp->role.direct |
e5a4c8ca | 718 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
719 | nonpaging_prefetch_page(vcpu, sp); |
720 | return; | |
721 | } | |
722 | ||
eab9f71f AK |
723 | pte_gpa = gfn_to_gpa(sp->gfn); |
724 | if (PTTYPE == 32) { | |
e5a4c8ca | 725 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
726 | pte_gpa += offset * sizeof(pt_element_t); |
727 | } | |
7ec54588 | 728 | |
eab9f71f AK |
729 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
730 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
731 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
732 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 733 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
734 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
735 | else | |
736 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 737 | } |
c7addb90 AK |
738 | } |
739 | ||
e8bc217a MT |
740 | /* |
741 | * Using the cached information from sp->gfns is safe because: | |
742 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
743 | * can't change unless all sptes pointing to it are nuked first. | |
e8bc217a | 744 | */ |
be71e061 XG |
745 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
746 | bool clear_unsync) | |
e8bc217a MT |
747 | { |
748 | int i, offset, nr_present; | |
1403283a | 749 | bool reset_host_protection; |
51fb60d8 | 750 | gpa_t first_pte_gpa; |
e8bc217a MT |
751 | |
752 | offset = nr_present = 0; | |
753 | ||
2032a93d LJ |
754 | /* direct kvm_mmu_page can not be unsync. */ |
755 | BUG_ON(sp->role.direct); | |
756 | ||
e8bc217a MT |
757 | if (PTTYPE == 32) |
758 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
759 | ||
51fb60d8 GJ |
760 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
761 | ||
e8bc217a MT |
762 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
763 | unsigned pte_access; | |
764 | pt_element_t gpte; | |
765 | gpa_t pte_gpa; | |
f55c3f41 | 766 | gfn_t gfn; |
e8bc217a MT |
767 | |
768 | if (!is_shadow_present_pte(sp->spt[i])) | |
769 | continue; | |
770 | ||
51fb60d8 | 771 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
772 | |
773 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
774 | sizeof(pt_element_t))) | |
775 | return -EINVAL; | |
776 | ||
f55c3f41 | 777 | gfn = gpte_to_gfn(gpte); |
3241f22d | 778 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL) |
fa1de2bf XG |
779 | || gfn != sp->gfns[i] || !is_present_gpte(gpte) |
780 | || !(gpte & PT_ACCESSED_MASK)) { | |
e8bc217a MT |
781 | u64 nonpresent; |
782 | ||
be71e061 | 783 | if (is_present_gpte(gpte) || !clear_unsync) |
e8bc217a MT |
784 | nonpresent = shadow_trap_nonpresent_pte; |
785 | else | |
786 | nonpresent = shadow_notrap_nonpresent_pte; | |
be38d276 | 787 | drop_spte(vcpu->kvm, &sp->spt[i], nonpresent); |
e8bc217a MT |
788 | continue; |
789 | } | |
790 | ||
791 | nr_present++; | |
792 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
1403283a IE |
793 | if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) { |
794 | pte_access &= ~ACC_WRITE_MASK; | |
795 | reset_host_protection = 0; | |
796 | } else { | |
797 | reset_host_protection = 1; | |
798 | } | |
e8bc217a | 799 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 800 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a IE |
801 | spte_to_pfn(sp->spt[i]), true, false, |
802 | reset_host_protection); | |
e8bc217a MT |
803 | } |
804 | ||
805 | return !nr_present; | |
806 | } | |
807 | ||
6aa8b732 AK |
808 | #undef pt_element_t |
809 | #undef guest_walker | |
810 | #undef FNAME | |
811 | #undef PT_BASE_ADDR_MASK | |
812 | #undef PT_INDEX | |
6aa8b732 | 813 | #undef PT_LEVEL_MASK |
e04da980 JR |
814 | #undef PT_LVL_ADDR_MASK |
815 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 816 | #undef PT_LEVEL_BITS |
cea0f0e7 | 817 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 818 | #undef gpte_to_gfn |
e04da980 | 819 | #undef gpte_to_gfn_lvl |
b3e4e63f | 820 | #undef CMPXCHG |