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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
cea0f0e7 | 66 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 67 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 68 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 69 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
70 | unsigned pt_access; |
71 | unsigned pte_access; | |
815af8d4 | 72 | gfn_t gfn; |
8c28d031 | 73 | struct x86_exception fault; |
6aa8b732 AK |
74 | }; |
75 | ||
e04da980 | 76 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 77 | { |
e04da980 | 78 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
79 | } |
80 | ||
a78484c6 | 81 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
b3e4e63f MT |
82 | gfn_t table_gfn, unsigned index, |
83 | pt_element_t orig_pte, pt_element_t new_pte) | |
84 | { | |
85 | pt_element_t ret; | |
86 | pt_element_t *table; | |
87 | struct page *page; | |
a78484c6 | 88 | gpa_t gpa; |
b3e4e63f | 89 | |
a78484c6 RJ |
90 | gpa = mmu->translate_gpa(vcpu, table_gfn << PAGE_SHIFT, |
91 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
92 | if (gpa == UNMAPPED_GVA) | |
93 | return -EFAULT; | |
94 | ||
95 | page = gfn_to_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
72dc67a6 | 96 | |
b3e4e63f | 97 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 98 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
99 | kunmap_atomic(table, KM_USER0); |
100 | ||
101 | kvm_release_page_dirty(page); | |
102 | ||
103 | return (ret != orig_pte); | |
104 | } | |
105 | ||
bedbe4ee AK |
106 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
107 | { | |
108 | unsigned access; | |
109 | ||
110 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
111 | #if PTTYPE == 64 | |
2d48a985 | 112 | if (vcpu->arch.mmu.nx) |
bedbe4ee AK |
113 | access &= ~(gpte >> PT64_NX_SHIFT); |
114 | #endif | |
115 | return access; | |
116 | } | |
117 | ||
ac79c978 AK |
118 | /* |
119 | * Fetch a guest pte for a guest virtual address | |
120 | */ | |
1e301feb JR |
121 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
122 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 123 | gva_t addr, u32 access) |
6aa8b732 | 124 | { |
42bf3f0a | 125 | pt_element_t pte; |
6e2ca7d1 | 126 | pt_element_t __user *ptep_user; |
cea0f0e7 | 127 | gfn_t table_gfn; |
f59c1d2d | 128 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 129 | gpa_t pte_gpa; |
f59c1d2d | 130 | bool eperm, present, rsvd_fault; |
33770780 XG |
131 | int offset, write_fault, user_fault, fetch_fault; |
132 | ||
133 | write_fault = access & PFERR_WRITE_MASK; | |
134 | user_fault = access & PFERR_USER_MASK; | |
135 | fetch_fault = access & PFERR_FETCH_MASK; | |
6aa8b732 | 136 | |
07420171 AK |
137 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
138 | fetch_fault); | |
b3e4e63f | 139 | walk: |
f59c1d2d AK |
140 | present = true; |
141 | eperm = rsvd_fault = false; | |
1e301feb JR |
142 | walker->level = mmu->root_level; |
143 | pte = mmu->get_cr3(vcpu); | |
144 | ||
1b0973bd | 145 | #if PTTYPE == 64 |
1e301feb | 146 | if (walker->level == PT32E_ROOT_LEVEL) { |
d41d1895 | 147 | pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3); |
07420171 | 148 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
149 | if (!is_present_gpte(pte)) { |
150 | present = false; | |
151 | goto error; | |
152 | } | |
1b0973bd AK |
153 | --walker->level; |
154 | } | |
155 | #endif | |
a9058ecd | 156 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 157 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 158 | |
fe135d2c | 159 | pt_access = ACC_ALL; |
ac79c978 AK |
160 | |
161 | for (;;) { | |
6e2ca7d1 TY |
162 | gfn_t real_gfn; |
163 | unsigned long host_addr; | |
164 | ||
42bf3f0a | 165 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 166 | |
5fb07ddb | 167 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
168 | offset = index * sizeof(pt_element_t); |
169 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 170 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 171 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 172 | |
6e2ca7d1 TY |
173 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
174 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
781e0743 | 175 | if (unlikely(real_gfn == UNMAPPED_GVA)) { |
6e2ca7d1 TY |
176 | present = false; |
177 | break; | |
178 | } | |
179 | real_gfn = gpa_to_gfn(real_gfn); | |
180 | ||
181 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
781e0743 | 182 | if (unlikely(kvm_is_error_hva(host_addr))) { |
6e2ca7d1 TY |
183 | present = false; |
184 | break; | |
185 | } | |
186 | ||
187 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
fa3d315a | 188 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) { |
f59c1d2d AK |
189 | present = false; |
190 | break; | |
191 | } | |
a6085fba | 192 | |
07420171 | 193 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 194 | |
781e0743 | 195 | if (unlikely(!is_present_gpte(pte))) { |
f59c1d2d AK |
196 | present = false; |
197 | break; | |
198 | } | |
7993ba43 | 199 | |
781e0743 AK |
200 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
201 | walker->level))) { | |
f59c1d2d AK |
202 | rsvd_fault = true; |
203 | break; | |
204 | } | |
82725b20 | 205 | |
781e0743 AK |
206 | if (unlikely(write_fault && !is_writable_pte(pte) |
207 | && (user_fault || is_write_protection(vcpu)))) | |
208 | eperm = true; | |
7993ba43 | 209 | |
781e0743 | 210 | if (unlikely(user_fault && !(pte & PT_USER_MASK))) |
f59c1d2d | 211 | eperm = true; |
7993ba43 | 212 | |
73b1087e | 213 | #if PTTYPE == 64 |
781e0743 | 214 | if (unlikely(fetch_fault && (pte & PT64_NX_MASK))) |
f59c1d2d | 215 | eperm = true; |
73b1087e AK |
216 | #endif |
217 | ||
781e0743 AK |
218 | if (!eperm && !rsvd_fault |
219 | && unlikely(!(pte & PT_ACCESSED_MASK))) { | |
a78484c6 | 220 | int ret; |
07420171 AK |
221 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
222 | sizeof(pte)); | |
a78484c6 RJ |
223 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, table_gfn, |
224 | index, pte, pte|PT_ACCESSED_MASK); | |
225 | if (ret < 0) { | |
226 | present = false; | |
227 | break; | |
228 | } else if (ret) | |
b3e4e63f | 229 | goto walk; |
a78484c6 | 230 | |
f3b8c964 | 231 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 232 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 233 | } |
815af8d4 | 234 | |
bedbe4ee | 235 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 236 | |
7819026e MT |
237 | walker->ptes[walker->level - 1] = pte; |
238 | ||
e04da980 JR |
239 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
240 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 241 | is_large_pte(pte) && |
e04da980 JR |
242 | (PTTYPE == 64 || is_pse(vcpu))) || |
243 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 244 | is_large_pte(pte) && |
1e301feb | 245 | mmu->root_level == PT64_ROOT_LEVEL)) { |
e04da980 | 246 | int lvl = walker->level; |
2329d46d JR |
247 | gpa_t real_gpa; |
248 | gfn_t gfn; | |
33770780 | 249 | u32 ac; |
e04da980 | 250 | |
2329d46d JR |
251 | gfn = gpte_to_gfn_lvl(pte, lvl); |
252 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
253 | |
254 | if (PTTYPE == 32 && | |
255 | walker->level == PT_DIRECTORY_LEVEL && | |
256 | is_cpuid_PSE36()) | |
2329d46d JR |
257 | gfn += pse36_gfn_delta(pte); |
258 | ||
33770780 | 259 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
260 | |
261 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 262 | ac); |
2329d46d JR |
263 | if (real_gpa == UNMAPPED_GVA) |
264 | return 0; | |
265 | ||
266 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 267 | |
ac79c978 | 268 | break; |
815af8d4 | 269 | } |
ac79c978 | 270 | |
fe135d2c | 271 | pt_access = pte_access; |
ac79c978 AK |
272 | --walker->level; |
273 | } | |
42bf3f0a | 274 | |
781e0743 | 275 | if (unlikely(!present || eperm || rsvd_fault)) |
f59c1d2d AK |
276 | goto error; |
277 | ||
781e0743 | 278 | if (write_fault && unlikely(!is_dirty_gpte(pte))) { |
a78484c6 | 279 | int ret; |
b3e4e63f | 280 | |
07420171 | 281 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
a78484c6 | 282 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, table_gfn, index, pte, |
b3e4e63f | 283 | pte|PT_DIRTY_MASK); |
a78484c6 RJ |
284 | if (ret < 0) { |
285 | present = false; | |
286 | goto error; | |
287 | } else if (ret) | |
b3e4e63f | 288 | goto walk; |
a78484c6 | 289 | |
f3b8c964 | 290 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 291 | pte |= PT_DIRTY_MASK; |
7819026e | 292 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
293 | } |
294 | ||
fe135d2c AK |
295 | walker->pt_access = pt_access; |
296 | walker->pte_access = pte_access; | |
297 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 298 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
299 | return 1; |
300 | ||
f59c1d2d | 301 | error: |
8c28d031 AK |
302 | walker->fault.vector = PF_VECTOR; |
303 | walker->fault.error_code_valid = true; | |
304 | walker->fault.error_code = 0; | |
f59c1d2d | 305 | if (present) |
8c28d031 | 306 | walker->fault.error_code |= PFERR_PRESENT_MASK; |
20bd40dc | 307 | |
8c28d031 | 308 | walker->fault.error_code |= write_fault | user_fault; |
20bd40dc | 309 | |
2d48a985 | 310 | if (fetch_fault && mmu->nx) |
8c28d031 | 311 | walker->fault.error_code |= PFERR_FETCH_MASK; |
82725b20 | 312 | if (rsvd_fault) |
8c28d031 | 313 | walker->fault.error_code |= PFERR_RSVD_MASK; |
8df25a32 | 314 | |
6389ee94 AK |
315 | walker->fault.address = addr; |
316 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 317 | |
8c28d031 | 318 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 319 | return 0; |
6aa8b732 AK |
320 | } |
321 | ||
1e301feb | 322 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 323 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
324 | { |
325 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 326 | access); |
1e301feb JR |
327 | } |
328 | ||
6539e738 JR |
329 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
330 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 331 | u32 access) |
6539e738 JR |
332 | { |
333 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 334 | addr, access); |
6539e738 JR |
335 | } |
336 | ||
407c61c6 XG |
337 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
338 | struct kvm_mmu_page *sp, u64 *spte, | |
339 | pt_element_t gpte) | |
340 | { | |
341 | u64 nonpresent = shadow_trap_nonpresent_pte; | |
342 | ||
343 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
344 | goto no_present; | |
345 | ||
346 | if (!is_present_gpte(gpte)) { | |
347 | if (!sp->unsync) | |
348 | nonpresent = shadow_notrap_nonpresent_pte; | |
349 | goto no_present; | |
350 | } | |
351 | ||
352 | if (!(gpte & PT_ACCESSED_MASK)) | |
353 | goto no_present; | |
354 | ||
355 | return false; | |
356 | ||
357 | no_present: | |
358 | drop_spte(vcpu->kvm, spte, nonpresent); | |
359 | return true; | |
360 | } | |
361 | ||
ac3cd03c | 362 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 363 | u64 *spte, const void *pte) |
0028425f AK |
364 | { |
365 | pt_element_t gpte; | |
41074d07 | 366 | unsigned pte_access; |
35149e21 | 367 | pfn_t pfn; |
0028425f | 368 | |
0028425f | 369 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 370 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 371 | return; |
407c61c6 | 372 | |
b8688d51 | 373 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 374 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
0f53b5b1 XG |
375 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
376 | if (is_error_pfn(pfn)) { | |
377 | kvm_release_pfn_clean(pfn); | |
d7824fff | 378 | return; |
0f53b5b1 | 379 | } |
0f53b5b1 | 380 | |
1403283a | 381 | /* |
0d2eb44f | 382 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
383 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
384 | */ | |
ac3cd03c | 385 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 386 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 387 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
388 | } |
389 | ||
39c8c672 AK |
390 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
391 | struct guest_walker *gw, int level) | |
392 | { | |
39c8c672 | 393 | pt_element_t curr_pte; |
189be38d XG |
394 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
395 | u64 mask; | |
396 | int r, index; | |
397 | ||
398 | if (level == PT_PAGE_TABLE_LEVEL) { | |
399 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
400 | base_gpa = pte_gpa & ~mask; | |
401 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
402 | ||
403 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
404 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
405 | curr_pte = gw->prefetch_ptes[index]; | |
406 | } else | |
407 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 408 | &curr_pte, sizeof(curr_pte)); |
189be38d | 409 | |
39c8c672 AK |
410 | return r || curr_pte != gw->ptes[level - 1]; |
411 | } | |
412 | ||
189be38d XG |
413 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
414 | u64 *sptep) | |
957ed9ef XG |
415 | { |
416 | struct kvm_mmu_page *sp; | |
189be38d | 417 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 418 | u64 *spte; |
189be38d | 419 | int i; |
957ed9ef XG |
420 | |
421 | sp = page_header(__pa(sptep)); | |
422 | ||
423 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
424 | return; | |
425 | ||
426 | if (sp->role.direct) | |
427 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
428 | ||
429 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
430 | spte = sp->spt + i; |
431 | ||
432 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
433 | pt_element_t gpte; | |
434 | unsigned pte_access; | |
435 | gfn_t gfn; | |
436 | pfn_t pfn; | |
437 | bool dirty; | |
438 | ||
439 | if (spte == sptep) | |
440 | continue; | |
441 | ||
442 | if (*spte != shadow_trap_nonpresent_pte) | |
443 | continue; | |
444 | ||
445 | gpte = gptep[i]; | |
446 | ||
407c61c6 | 447 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
448 | continue; |
449 | ||
450 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
451 | gfn = gpte_to_gfn(gpte); | |
452 | dirty = is_dirty_gpte(gpte); | |
453 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
454 | (pte_access & ACC_WRITE_MASK) && dirty); | |
455 | if (is_error_pfn(pfn)) { | |
456 | kvm_release_pfn_clean(pfn); | |
457 | break; | |
458 | } | |
459 | ||
460 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
461 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
462 | pfn, true, true); | |
463 | } | |
464 | } | |
465 | ||
6aa8b732 AK |
466 | /* |
467 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
468 | */ | |
e7a04c99 AK |
469 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
470 | struct guest_walker *gw, | |
7e4e4056 | 471 | int user_fault, int write_fault, int hlevel, |
fb67e14f XG |
472 | int *ptwrite, pfn_t pfn, bool map_writable, |
473 | bool prefault) | |
6aa8b732 | 474 | { |
abb9e0b8 | 475 | unsigned access = gw->pt_access; |
5991b332 | 476 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 477 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 478 | int top_level; |
84754cd8 | 479 | unsigned direct_access; |
24157aaf | 480 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 481 | |
43a3795a | 482 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 483 | return NULL; |
6aa8b732 | 484 | |
84754cd8 XG |
485 | direct_access = gw->pt_access & gw->pte_access; |
486 | if (!dirty) | |
487 | direct_access &= ~ACC_WRITE_MASK; | |
488 | ||
5991b332 AK |
489 | top_level = vcpu->arch.mmu.root_level; |
490 | if (top_level == PT32E_ROOT_LEVEL) | |
491 | top_level = PT32_ROOT_LEVEL; | |
492 | /* | |
493 | * Verify that the top-level gpte is still there. Since the page | |
494 | * is a root page, it is either write protected (and cannot be | |
495 | * changed from now on) or it is invalid (in which case, we don't | |
496 | * really care if it changes underneath us after this point). | |
497 | */ | |
498 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
499 | goto out_gpte_changed; | |
500 | ||
24157aaf AK |
501 | for (shadow_walk_init(&it, vcpu, addr); |
502 | shadow_walk_okay(&it) && it.level > gw->level; | |
503 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
504 | gfn_t table_gfn; |
505 | ||
24157aaf | 506 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 507 | |
5991b332 | 508 | sp = NULL; |
24157aaf AK |
509 | if (!is_shadow_present_pte(*it.sptep)) { |
510 | table_gfn = gw->table_gfn[it.level - 2]; | |
511 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
512 | false, access, it.sptep); | |
5991b332 | 513 | } |
0b3c9333 AK |
514 | |
515 | /* | |
516 | * Verify that the gpte in the page we've just write | |
517 | * protected is still there. | |
518 | */ | |
24157aaf | 519 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 520 | goto out_gpte_changed; |
abb9e0b8 | 521 | |
5991b332 | 522 | if (sp) |
24157aaf | 523 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 524 | } |
050e6499 | 525 | |
0b3c9333 | 526 | for (; |
24157aaf AK |
527 | shadow_walk_okay(&it) && it.level > hlevel; |
528 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
529 | gfn_t direct_gfn; |
530 | ||
24157aaf | 531 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 532 | |
24157aaf | 533 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 534 | |
24157aaf | 535 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
536 | continue; |
537 | ||
24157aaf | 538 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 539 | |
24157aaf AK |
540 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
541 | true, direct_access, it.sptep); | |
542 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
543 | } |
544 | ||
24157aaf AK |
545 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
546 | user_fault, write_fault, dirty, ptwrite, it.level, | |
fb67e14f | 547 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 548 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 549 | |
24157aaf | 550 | return it.sptep; |
0b3c9333 AK |
551 | |
552 | out_gpte_changed: | |
5991b332 | 553 | if (sp) |
24157aaf | 554 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
555 | kvm_release_pfn_clean(pfn); |
556 | return NULL; | |
6aa8b732 AK |
557 | } |
558 | ||
6aa8b732 AK |
559 | /* |
560 | * Page fault handler. There are several causes for a page fault: | |
561 | * - there is no shadow pte for the guest pte | |
562 | * - write access through a shadow pte marked read only so that we can set | |
563 | * the dirty bit | |
564 | * - write access to a shadow pte marked read only so we can update the page | |
565 | * dirty bitmap, when userspace requests it | |
566 | * - mmio access; in this case we will never install a present shadow pte | |
567 | * - normal guest page fault due to the guest pte marked not present, not | |
568 | * writable, or not executable | |
569 | * | |
e2dec939 AK |
570 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
571 | * a negative value on error. | |
6aa8b732 | 572 | */ |
56028d08 | 573 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 574 | bool prefault) |
6aa8b732 AK |
575 | { |
576 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
577 | int user_fault = error_code & PFERR_USER_MASK; |
578 | struct guest_walker walker; | |
d555c333 | 579 | u64 *sptep; |
cea0f0e7 | 580 | int write_pt = 0; |
e2dec939 | 581 | int r; |
35149e21 | 582 | pfn_t pfn; |
7e4e4056 | 583 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 584 | int force_pt_level; |
e930bffe | 585 | unsigned long mmu_seq; |
612819c3 | 586 | bool map_writable; |
6aa8b732 | 587 | |
b8688d51 | 588 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 589 | |
e2dec939 AK |
590 | r = mmu_topup_memory_caches(vcpu); |
591 | if (r) | |
592 | return r; | |
714b93da | 593 | |
6aa8b732 | 594 | /* |
a8b876b1 | 595 | * Look up the guest pte for the faulting address. |
6aa8b732 | 596 | */ |
33770780 | 597 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
598 | |
599 | /* | |
600 | * The page is not mapped by the guest. Let the guest handle it. | |
601 | */ | |
7993ba43 | 602 | if (!r) { |
b8688d51 | 603 | pgprintk("%s: guest page fault\n", __func__); |
fb67e14f XG |
604 | if (!prefault) { |
605 | inject_page_fault(vcpu, &walker.fault); | |
606 | /* reset fork detector */ | |
607 | vcpu->arch.last_pt_write_count = 0; | |
608 | } | |
6aa8b732 AK |
609 | return 0; |
610 | } | |
611 | ||
936a5fe6 AA |
612 | if (walker.level >= PT_DIRECTORY_LEVEL) |
613 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
614 | else | |
615 | force_pt_level = 1; | |
616 | if (!force_pt_level) { | |
7e4e4056 JR |
617 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
618 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 619 | } |
7e4e4056 | 620 | |
e930bffe | 621 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 622 | smp_rmb(); |
af585b92 | 623 | |
78b2c54a | 624 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 625 | &map_writable)) |
af585b92 | 626 | return 0; |
d7824fff | 627 | |
d196e343 | 628 | /* mmio */ |
bf998156 HY |
629 | if (is_error_pfn(pfn)) |
630 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 631 | |
aaee2c94 | 632 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
633 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
634 | goto out_unlock; | |
bc32ce21 | 635 | |
8b1fe17c | 636 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 637 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
638 | if (!force_pt_level) |
639 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 640 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
fb67e14f | 641 | level, &write_pt, pfn, map_writable, prefault); |
a24e8099 | 642 | (void)sptep; |
b8688d51 | 643 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 644 | sptep, *sptep, write_pt); |
cea0f0e7 | 645 | |
a25f7e1f | 646 | if (!write_pt) |
ad312c7c | 647 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 648 | |
1165f5fe | 649 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 650 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 651 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 652 | |
cea0f0e7 | 653 | return write_pt; |
e930bffe AA |
654 | |
655 | out_unlock: | |
656 | spin_unlock(&vcpu->kvm->mmu_lock); | |
657 | kvm_release_pfn_clean(pfn); | |
658 | return 0; | |
6aa8b732 AK |
659 | } |
660 | ||
a461930b | 661 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 662 | { |
a461930b | 663 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 664 | struct kvm_mmu_page *sp; |
08e850c6 | 665 | gpa_t pte_gpa = -1; |
a461930b AK |
666 | int level; |
667 | u64 *sptep; | |
4539b358 | 668 | int need_flush = 0; |
a461930b AK |
669 | |
670 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 671 | |
a461930b AK |
672 | for_each_shadow_entry(vcpu, gva, iterator) { |
673 | level = iterator.level; | |
674 | sptep = iterator.sptep; | |
ad218f85 | 675 | |
f78978aa | 676 | sp = page_header(__pa(sptep)); |
884a0ff0 | 677 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 678 | int offset, shift; |
08e850c6 | 679 | |
f78978aa XG |
680 | if (!sp->unsync) |
681 | break; | |
682 | ||
22c9b2d1 XG |
683 | shift = PAGE_SHIFT - |
684 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
685 | offset = sp->role.quadrant << shift; | |
686 | ||
687 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 688 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
689 | |
690 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
691 | if (is_large_pte(*sptep)) |
692 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
693 | drop_spte(vcpu->kvm, sptep, |
694 | shadow_trap_nonpresent_pte); | |
4539b358 | 695 | need_flush = 1; |
be38d276 AK |
696 | } else |
697 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 698 | break; |
87917239 | 699 | } |
a7052897 | 700 | |
f78978aa | 701 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
702 | break; |
703 | } | |
a7052897 | 704 | |
4539b358 AA |
705 | if (need_flush) |
706 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
707 | |
708 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
709 | ||
ad218f85 | 710 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
711 | |
712 | if (pte_gpa == -1) | |
713 | return; | |
714 | ||
715 | if (mmu_topup_memory_caches(vcpu)) | |
716 | return; | |
717 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
718 | } |
719 | ||
1871c602 | 720 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 721 | struct x86_exception *exception) |
6aa8b732 AK |
722 | { |
723 | struct guest_walker walker; | |
e119d117 AK |
724 | gpa_t gpa = UNMAPPED_GVA; |
725 | int r; | |
6aa8b732 | 726 | |
33770780 | 727 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 728 | |
e119d117 | 729 | if (r) { |
1755fbcc | 730 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 731 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
732 | } else if (exception) |
733 | *exception = walker.fault; | |
6aa8b732 AK |
734 | |
735 | return gpa; | |
736 | } | |
737 | ||
6539e738 | 738 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
739 | u32 access, |
740 | struct x86_exception *exception) | |
6539e738 JR |
741 | { |
742 | struct guest_walker walker; | |
743 | gpa_t gpa = UNMAPPED_GVA; | |
744 | int r; | |
745 | ||
33770780 | 746 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
747 | |
748 | if (r) { | |
749 | gpa = gfn_to_gpa(walker.gfn); | |
750 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
751 | } else if (exception) |
752 | *exception = walker.fault; | |
6539e738 JR |
753 | |
754 | return gpa; | |
755 | } | |
756 | ||
c7addb90 AK |
757 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
758 | struct kvm_mmu_page *sp) | |
759 | { | |
eab9f71f AK |
760 | int i, j, offset, r; |
761 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
762 | gpa_t pte_gpa; | |
c7addb90 | 763 | |
f6e2c02b | 764 | if (sp->role.direct |
e5a4c8ca | 765 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
766 | nonpaging_prefetch_page(vcpu, sp); |
767 | return; | |
768 | } | |
769 | ||
eab9f71f AK |
770 | pte_gpa = gfn_to_gpa(sp->gfn); |
771 | if (PTTYPE == 32) { | |
e5a4c8ca | 772 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
773 | pte_gpa += offset * sizeof(pt_element_t); |
774 | } | |
7ec54588 | 775 | |
eab9f71f AK |
776 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
777 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
778 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
779 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 780 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
781 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
782 | else | |
783 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 784 | } |
c7addb90 AK |
785 | } |
786 | ||
e8bc217a MT |
787 | /* |
788 | * Using the cached information from sp->gfns is safe because: | |
789 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
790 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
791 | * |
792 | * Note: | |
793 | * We should flush all tlbs if spte is dropped even though guest is | |
794 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
795 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
796 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
797 | * freed pages. | |
798 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 799 | */ |
a4a8e6f7 | 800 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a MT |
801 | { |
802 | int i, offset, nr_present; | |
9bdbba13 | 803 | bool host_writable; |
51fb60d8 | 804 | gpa_t first_pte_gpa; |
e8bc217a MT |
805 | |
806 | offset = nr_present = 0; | |
807 | ||
2032a93d LJ |
808 | /* direct kvm_mmu_page can not be unsync. */ |
809 | BUG_ON(sp->role.direct); | |
810 | ||
e8bc217a MT |
811 | if (PTTYPE == 32) |
812 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
813 | ||
51fb60d8 GJ |
814 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
815 | ||
e8bc217a MT |
816 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
817 | unsigned pte_access; | |
818 | pt_element_t gpte; | |
819 | gpa_t pte_gpa; | |
f55c3f41 | 820 | gfn_t gfn; |
e8bc217a MT |
821 | |
822 | if (!is_shadow_present_pte(sp->spt[i])) | |
823 | continue; | |
824 | ||
51fb60d8 | 825 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
826 | |
827 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
828 | sizeof(pt_element_t))) | |
829 | return -EINVAL; | |
830 | ||
f55c3f41 | 831 | gfn = gpte_to_gfn(gpte); |
407c61c6 XG |
832 | |
833 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { | |
a4ee1ca4 | 834 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
835 | continue; |
836 | } | |
837 | ||
838 | if (gfn != sp->gfns[i]) { | |
839 | drop_spte(vcpu->kvm, &sp->spt[i], | |
840 | shadow_trap_nonpresent_pte); | |
a4ee1ca4 | 841 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
842 | continue; |
843 | } | |
844 | ||
845 | nr_present++; | |
846 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
f8e453b0 XG |
847 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
848 | ||
e8bc217a | 849 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 850 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 851 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 852 | host_writable); |
e8bc217a MT |
853 | } |
854 | ||
855 | return !nr_present; | |
856 | } | |
857 | ||
6aa8b732 AK |
858 | #undef pt_element_t |
859 | #undef guest_walker | |
860 | #undef FNAME | |
861 | #undef PT_BASE_ADDR_MASK | |
862 | #undef PT_INDEX | |
e04da980 JR |
863 | #undef PT_LVL_ADDR_MASK |
864 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 865 | #undef PT_LEVEL_BITS |
cea0f0e7 | 866 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 867 | #undef gpte_to_gfn |
e04da980 | 868 | #undef gpte_to_gfn_lvl |
b3e4e63f | 869 | #undef CMPXCHG |