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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
6aa8b732 | 34 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) |
c7addb90 | 35 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
36 | #ifdef CONFIG_X86_64 |
37 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 38 | #define CMPXCHG cmpxchg |
cea0f0e7 | 39 | #else |
b3e4e63f | 40 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
41 | #define PT_MAX_FULL_LEVELS 2 |
42 | #endif | |
6aa8b732 AK |
43 | #elif PTTYPE == 32 |
44 | #define pt_element_t u32 | |
45 | #define guest_walker guest_walker32 | |
46 | #define FNAME(name) paging##32_##name | |
47 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
48 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
49 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 50 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
6aa8b732 | 51 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) |
c7addb90 | 52 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 53 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 54 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
55 | #else |
56 | #error Invalid PTTYPE value | |
57 | #endif | |
58 | ||
e04da980 JR |
59 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
60 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 61 | |
6aa8b732 AK |
62 | /* |
63 | * The guest_walker structure emulates the behavior of the hardware page | |
64 | * table walker. | |
65 | */ | |
66 | struct guest_walker { | |
67 | int level; | |
cea0f0e7 | 68 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e MT |
69 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
70 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; | |
fe135d2c AK |
71 | unsigned pt_access; |
72 | unsigned pte_access; | |
815af8d4 | 73 | gfn_t gfn; |
7993ba43 | 74 | u32 error_code; |
6aa8b732 AK |
75 | }; |
76 | ||
e04da980 | 77 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 78 | { |
e04da980 | 79 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
80 | } |
81 | ||
b3e4e63f MT |
82 | static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, |
83 | gfn_t table_gfn, unsigned index, | |
84 | pt_element_t orig_pte, pt_element_t new_pte) | |
85 | { | |
86 | pt_element_t ret; | |
87 | pt_element_t *table; | |
88 | struct page *page; | |
89 | ||
90 | page = gfn_to_page(kvm, table_gfn); | |
72dc67a6 | 91 | |
b3e4e63f | 92 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 93 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
94 | kunmap_atomic(table, KM_USER0); |
95 | ||
96 | kvm_release_page_dirty(page); | |
97 | ||
98 | return (ret != orig_pte); | |
99 | } | |
100 | ||
bedbe4ee AK |
101 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
102 | { | |
103 | unsigned access; | |
104 | ||
105 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
106 | #if PTTYPE == 64 | |
107 | if (is_nx(vcpu)) | |
108 | access &= ~(gpte >> PT64_NX_SHIFT); | |
109 | #endif | |
110 | return access; | |
111 | } | |
112 | ||
ac79c978 AK |
113 | /* |
114 | * Fetch a guest pte for a guest virtual address | |
115 | */ | |
7993ba43 AK |
116 | static int FNAME(walk_addr)(struct guest_walker *walker, |
117 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 118 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 | 119 | { |
42bf3f0a | 120 | pt_element_t pte; |
cea0f0e7 | 121 | gfn_t table_gfn; |
f59c1d2d | 122 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 123 | gpa_t pte_gpa; |
f59c1d2d | 124 | bool eperm, present, rsvd_fault; |
6aa8b732 | 125 | |
07420171 AK |
126 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
127 | fetch_fault); | |
b3e4e63f | 128 | walk: |
f59c1d2d AK |
129 | present = true; |
130 | eperm = rsvd_fault = false; | |
ad312c7c ZX |
131 | walker->level = vcpu->arch.mmu.root_level; |
132 | pte = vcpu->arch.cr3; | |
1b0973bd AK |
133 | #if PTTYPE == 64 |
134 | if (!is_long_mode(vcpu)) { | |
6de4f3ad | 135 | pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3); |
07420171 | 136 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
137 | if (!is_present_gpte(pte)) { |
138 | present = false; | |
139 | goto error; | |
140 | } | |
1b0973bd AK |
141 | --walker->level; |
142 | } | |
143 | #endif | |
a9058ecd | 144 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
24993d53 | 145 | (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 146 | |
fe135d2c | 147 | pt_access = ACC_ALL; |
ac79c978 AK |
148 | |
149 | for (;;) { | |
42bf3f0a | 150 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 151 | |
5fb07ddb | 152 | table_gfn = gpte_to_gfn(pte); |
1755fbcc | 153 | pte_gpa = gfn_to_gpa(table_gfn); |
ec8d4eae | 154 | pte_gpa += index * sizeof(pt_element_t); |
42bf3f0a | 155 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 156 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 157 | |
f59c1d2d AK |
158 | if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte))) { |
159 | present = false; | |
160 | break; | |
161 | } | |
a6085fba | 162 | |
07420171 | 163 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 164 | |
f59c1d2d AK |
165 | if (!is_present_gpte(pte)) { |
166 | present = false; | |
167 | break; | |
168 | } | |
7993ba43 | 169 | |
f59c1d2d AK |
170 | if (is_rsvd_bits_set(vcpu, pte, walker->level)) { |
171 | rsvd_fault = true; | |
172 | break; | |
173 | } | |
82725b20 | 174 | |
8dae4445 | 175 | if (write_fault && !is_writable_pte(pte)) |
7993ba43 | 176 | if (user_fault || is_write_protection(vcpu)) |
f59c1d2d | 177 | eperm = true; |
7993ba43 | 178 | |
42bf3f0a | 179 | if (user_fault && !(pte & PT_USER_MASK)) |
f59c1d2d | 180 | eperm = true; |
7993ba43 | 181 | |
73b1087e | 182 | #if PTTYPE == 64 |
24222c2f | 183 | if (fetch_fault && (pte & PT64_NX_MASK)) |
f59c1d2d | 184 | eperm = true; |
73b1087e AK |
185 | #endif |
186 | ||
f59c1d2d | 187 | if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) { |
07420171 AK |
188 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
189 | sizeof(pte)); | |
b3e4e63f MT |
190 | if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, |
191 | index, pte, pte|PT_ACCESSED_MASK)) | |
192 | goto walk; | |
f3b8c964 | 193 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 194 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 195 | } |
815af8d4 | 196 | |
bedbe4ee | 197 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 198 | |
7819026e MT |
199 | walker->ptes[walker->level - 1] = pte; |
200 | ||
e04da980 JR |
201 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
202 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 203 | is_large_pte(pte) && |
e04da980 JR |
204 | (PTTYPE == 64 || is_pse(vcpu))) || |
205 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 206 | is_large_pte(pte) && |
e04da980 JR |
207 | is_long_mode(vcpu))) { |
208 | int lvl = walker->level; | |
209 | ||
210 | walker->gfn = gpte_to_gfn_lvl(pte, lvl); | |
211 | walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) | |
212 | >> PAGE_SHIFT; | |
213 | ||
214 | if (PTTYPE == 32 && | |
215 | walker->level == PT_DIRECTORY_LEVEL && | |
216 | is_cpuid_PSE36()) | |
da928521 | 217 | walker->gfn += pse36_gfn_delta(pte); |
e04da980 | 218 | |
ac79c978 | 219 | break; |
815af8d4 | 220 | } |
ac79c978 | 221 | |
fe135d2c | 222 | pt_access = pte_access; |
ac79c978 AK |
223 | --walker->level; |
224 | } | |
42bf3f0a | 225 | |
f59c1d2d AK |
226 | if (!present || eperm || rsvd_fault) |
227 | goto error; | |
228 | ||
43a3795a | 229 | if (write_fault && !is_dirty_gpte(pte)) { |
b3e4e63f MT |
230 | bool ret; |
231 | ||
07420171 | 232 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
b3e4e63f MT |
233 | ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte, |
234 | pte|PT_DIRTY_MASK); | |
235 | if (ret) | |
236 | goto walk; | |
f3b8c964 | 237 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 238 | pte |= PT_DIRTY_MASK; |
7819026e | 239 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
240 | } |
241 | ||
fe135d2c AK |
242 | walker->pt_access = pt_access; |
243 | walker->pte_access = pte_access; | |
244 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 245 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
246 | return 1; |
247 | ||
f59c1d2d | 248 | error: |
7993ba43 | 249 | walker->error_code = 0; |
f59c1d2d AK |
250 | if (present) |
251 | walker->error_code |= PFERR_PRESENT_MASK; | |
7993ba43 AK |
252 | if (write_fault) |
253 | walker->error_code |= PFERR_WRITE_MASK; | |
254 | if (user_fault) | |
255 | walker->error_code |= PFERR_USER_MASK; | |
b0eeec29 | 256 | if (fetch_fault && is_nx(vcpu)) |
73b1087e | 257 | walker->error_code |= PFERR_FETCH_MASK; |
82725b20 DE |
258 | if (rsvd_fault) |
259 | walker->error_code |= PFERR_RSVD_MASK; | |
07420171 | 260 | trace_kvm_mmu_walker_error(walker->error_code); |
fe551881 | 261 | return 0; |
6aa8b732 AK |
262 | } |
263 | ||
ac3cd03c | 264 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
489f1d65 | 265 | u64 *spte, const void *pte) |
0028425f AK |
266 | { |
267 | pt_element_t gpte; | |
41074d07 | 268 | unsigned pte_access; |
35149e21 | 269 | pfn_t pfn; |
fbc5d139 | 270 | u64 new_spte; |
0028425f | 271 | |
0028425f | 272 | gpte = *(const pt_element_t *)pte; |
c7addb90 | 273 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
fbc5d139 | 274 | if (!is_present_gpte(gpte)) { |
ac3cd03c | 275 | if (sp->unsync) |
fbc5d139 AK |
276 | new_spte = shadow_trap_nonpresent_pte; |
277 | else | |
278 | new_spte = shadow_notrap_nonpresent_pte; | |
279 | __set_spte(spte, new_spte); | |
280 | } | |
c7addb90 AK |
281 | return; |
282 | } | |
b8688d51 | 283 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 284 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
d7824fff AK |
285 | if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn) |
286 | return; | |
35149e21 AL |
287 | pfn = vcpu->arch.update_pte.pfn; |
288 | if (is_error_pfn(pfn)) | |
d7824fff | 289 | return; |
e930bffe AA |
290 | if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq)) |
291 | return; | |
35149e21 | 292 | kvm_get_pfn(pfn); |
1403283a IE |
293 | /* |
294 | * we call mmu_set_spte() with reset_host_protection = true beacuse that | |
295 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). | |
296 | */ | |
ac3cd03c | 297 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 298 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 299 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
300 | } |
301 | ||
6aa8b732 AK |
302 | /* |
303 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
304 | */ | |
e7a04c99 AK |
305 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
306 | struct guest_walker *gw, | |
7e4e4056 | 307 | int user_fault, int write_fault, int hlevel, |
e7a04c99 | 308 | int *ptwrite, pfn_t pfn) |
6aa8b732 | 309 | { |
abb9e0b8 | 310 | unsigned access = gw->pt_access; |
ac3cd03c | 311 | struct kvm_mmu_page *sp; |
32ef26a3 | 312 | u64 *sptep = NULL; |
f6e2c02b | 313 | int direct; |
abb9e0b8 AK |
314 | gfn_t table_gfn; |
315 | int r; | |
e7a04c99 | 316 | int level; |
84754cd8 XG |
317 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
318 | unsigned direct_access; | |
abb9e0b8 | 319 | pt_element_t curr_pte; |
e7a04c99 | 320 | struct kvm_shadow_walk_iterator iterator; |
abb9e0b8 | 321 | |
43a3795a | 322 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 323 | return NULL; |
6aa8b732 | 324 | |
84754cd8 XG |
325 | direct_access = gw->pt_access & gw->pte_access; |
326 | if (!dirty) | |
327 | direct_access &= ~ACC_WRITE_MASK; | |
328 | ||
e7a04c99 AK |
329 | for_each_shadow_entry(vcpu, addr, iterator) { |
330 | level = iterator.level; | |
331 | sptep = iterator.sptep; | |
7e4e4056 | 332 | if (iterator.level == hlevel) { |
e7a04c99 AK |
333 | mmu_set_spte(vcpu, sptep, access, |
334 | gw->pte_access & access, | |
335 | user_fault, write_fault, | |
84754cd8 | 336 | dirty, ptwrite, level, |
1403283a | 337 | gw->gfn, pfn, false, true); |
e7a04c99 AK |
338 | break; |
339 | } | |
6aa8b732 | 340 | |
a357bd22 AK |
341 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep) |
342 | && level == gw->level) | |
343 | validate_direct_spte(vcpu, sptep, direct_access); | |
abb9e0b8 | 344 | |
a3aa51cf | 345 | drop_large_spte(vcpu, sptep); |
ef0197e8 | 346 | |
a357bd22 AK |
347 | if (is_shadow_present_pte(*sptep)) |
348 | continue; | |
349 | ||
7e4e4056 | 350 | if (level <= gw->level) { |
f6e2c02b | 351 | direct = 1; |
84754cd8 | 352 | access = direct_access; |
5fd5387c | 353 | |
3af1817a LJ |
354 | /* |
355 | * It is a large guest pages backed by small host pages, | |
ac3cd03c XG |
356 | * So we set @direct(@sp->role.direct)=1, and set |
357 | * @table_gfn(@sp->gfn)=the base page frame for linear | |
358 | * translations. | |
3af1817a LJ |
359 | */ |
360 | table_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
6aa0b9de | 361 | access &= gw->pte_access; |
e7a04c99 | 362 | } else { |
f6e2c02b | 363 | direct = 0; |
e7a04c99 AK |
364 | table_gfn = gw->table_gfn[level - 2]; |
365 | } | |
ac3cd03c | 366 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1, |
f6e2c02b AK |
367 | direct, access, sptep); |
368 | if (!direct) { | |
e7a04c99 AK |
369 | r = kvm_read_guest_atomic(vcpu->kvm, |
370 | gw->pte_gpa[level - 2], | |
371 | &curr_pte, sizeof(curr_pte)); | |
372 | if (r || curr_pte != gw->ptes[level - 2]) { | |
ac3cd03c | 373 | kvm_mmu_put_page(sp, sptep); |
e7a04c99 AK |
374 | kvm_release_pfn_clean(pfn); |
375 | sptep = NULL; | |
376 | break; | |
377 | } | |
378 | } | |
abb9e0b8 | 379 | |
32ef26a3 | 380 | link_shadow_page(sptep, sp); |
e7a04c99 | 381 | } |
050e6499 | 382 | |
e7a04c99 | 383 | return sptep; |
6aa8b732 AK |
384 | } |
385 | ||
6aa8b732 AK |
386 | /* |
387 | * Page fault handler. There are several causes for a page fault: | |
388 | * - there is no shadow pte for the guest pte | |
389 | * - write access through a shadow pte marked read only so that we can set | |
390 | * the dirty bit | |
391 | * - write access to a shadow pte marked read only so we can update the page | |
392 | * dirty bitmap, when userspace requests it | |
393 | * - mmio access; in this case we will never install a present shadow pte | |
394 | * - normal guest page fault due to the guest pte marked not present, not | |
395 | * writable, or not executable | |
396 | * | |
e2dec939 AK |
397 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
398 | * a negative value on error. | |
6aa8b732 AK |
399 | */ |
400 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
401 | u32 error_code) | |
402 | { | |
403 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 404 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 405 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 | 406 | struct guest_walker walker; |
d555c333 | 407 | u64 *sptep; |
cea0f0e7 | 408 | int write_pt = 0; |
e2dec939 | 409 | int r; |
35149e21 | 410 | pfn_t pfn; |
7e4e4056 | 411 | int level = PT_PAGE_TABLE_LEVEL; |
e930bffe | 412 | unsigned long mmu_seq; |
6aa8b732 | 413 | |
b8688d51 | 414 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
37a7d8b0 | 415 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 416 | |
e2dec939 AK |
417 | r = mmu_topup_memory_caches(vcpu); |
418 | if (r) | |
419 | return r; | |
714b93da | 420 | |
6aa8b732 | 421 | /* |
a8b876b1 | 422 | * Look up the guest pte for the faulting address. |
6aa8b732 | 423 | */ |
73b1087e AK |
424 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
425 | fetch_fault); | |
6aa8b732 AK |
426 | |
427 | /* | |
428 | * The page is not mapped by the guest. Let the guest handle it. | |
429 | */ | |
7993ba43 | 430 | if (!r) { |
b8688d51 | 431 | pgprintk("%s: guest page fault\n", __func__); |
7993ba43 | 432 | inject_page_fault(vcpu, addr, walker.error_code); |
ad312c7c | 433 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
434 | return 0; |
435 | } | |
436 | ||
7e4e4056 JR |
437 | if (walker.level >= PT_DIRECTORY_LEVEL) { |
438 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); | |
439 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 440 | } |
7e4e4056 | 441 | |
e930bffe | 442 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 443 | smp_rmb(); |
35149e21 | 444 | pfn = gfn_to_pfn(vcpu->kvm, walker.gfn); |
d7824fff | 445 | |
d196e343 | 446 | /* mmio */ |
bf998156 HY |
447 | if (is_error_pfn(pfn)) |
448 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 449 | |
aaee2c94 | 450 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
451 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
452 | goto out_unlock; | |
eb787d10 | 453 | kvm_mmu_free_some_pages(vcpu); |
d555c333 | 454 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
7e4e4056 | 455 | level, &write_pt, pfn); |
a24e8099 | 456 | (void)sptep; |
b8688d51 | 457 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 458 | sptep, *sptep, write_pt); |
cea0f0e7 | 459 | |
a25f7e1f | 460 | if (!write_pt) |
ad312c7c | 461 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 462 | |
1165f5fe | 463 | ++vcpu->stat.pf_fixed; |
37a7d8b0 | 464 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
aaee2c94 | 465 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 466 | |
cea0f0e7 | 467 | return write_pt; |
e930bffe AA |
468 | |
469 | out_unlock: | |
470 | spin_unlock(&vcpu->kvm->mmu_lock); | |
471 | kvm_release_pfn_clean(pfn); | |
472 | return 0; | |
6aa8b732 AK |
473 | } |
474 | ||
a461930b | 475 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 476 | { |
a461930b | 477 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 478 | struct kvm_mmu_page *sp; |
08e850c6 | 479 | gpa_t pte_gpa = -1; |
a461930b AK |
480 | int level; |
481 | u64 *sptep; | |
4539b358 | 482 | int need_flush = 0; |
a461930b AK |
483 | |
484 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 485 | |
a461930b AK |
486 | for_each_shadow_entry(vcpu, gva, iterator) { |
487 | level = iterator.level; | |
488 | sptep = iterator.sptep; | |
ad218f85 | 489 | |
f78978aa | 490 | sp = page_header(__pa(sptep)); |
884a0ff0 | 491 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 492 | int offset, shift; |
08e850c6 | 493 | |
f78978aa XG |
494 | if (!sp->unsync) |
495 | break; | |
496 | ||
22c9b2d1 XG |
497 | shift = PAGE_SHIFT - |
498 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
499 | offset = sp->role.quadrant << shift; | |
500 | ||
501 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 502 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
503 | |
504 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
505 | if (is_large_pte(*sptep)) |
506 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
507 | drop_spte(vcpu->kvm, sptep, |
508 | shadow_trap_nonpresent_pte); | |
4539b358 | 509 | need_flush = 1; |
be38d276 AK |
510 | } else |
511 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 512 | break; |
87917239 | 513 | } |
a7052897 | 514 | |
f78978aa | 515 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
516 | break; |
517 | } | |
a7052897 | 518 | |
4539b358 AA |
519 | if (need_flush) |
520 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
521 | |
522 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
523 | ||
ad218f85 | 524 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
525 | |
526 | if (pte_gpa == -1) | |
527 | return; | |
528 | ||
529 | if (mmu_topup_memory_caches(vcpu)) | |
530 | return; | |
531 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
532 | } |
533 | ||
1871c602 GN |
534 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
535 | u32 *error) | |
6aa8b732 AK |
536 | { |
537 | struct guest_walker walker; | |
e119d117 AK |
538 | gpa_t gpa = UNMAPPED_GVA; |
539 | int r; | |
6aa8b732 | 540 | |
1871c602 GN |
541 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, |
542 | !!(access & PFERR_WRITE_MASK), | |
543 | !!(access & PFERR_USER_MASK), | |
544 | !!(access & PFERR_FETCH_MASK)); | |
6aa8b732 | 545 | |
e119d117 | 546 | if (r) { |
1755fbcc | 547 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 548 | gpa |= vaddr & ~PAGE_MASK; |
1871c602 GN |
549 | } else if (error) |
550 | *error = walker.error_code; | |
6aa8b732 AK |
551 | |
552 | return gpa; | |
553 | } | |
554 | ||
c7addb90 AK |
555 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
556 | struct kvm_mmu_page *sp) | |
557 | { | |
eab9f71f AK |
558 | int i, j, offset, r; |
559 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
560 | gpa_t pte_gpa; | |
c7addb90 | 561 | |
f6e2c02b | 562 | if (sp->role.direct |
e5a4c8ca | 563 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
564 | nonpaging_prefetch_page(vcpu, sp); |
565 | return; | |
566 | } | |
567 | ||
eab9f71f AK |
568 | pte_gpa = gfn_to_gpa(sp->gfn); |
569 | if (PTTYPE == 32) { | |
e5a4c8ca | 570 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
571 | pte_gpa += offset * sizeof(pt_element_t); |
572 | } | |
7ec54588 | 573 | |
eab9f71f AK |
574 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
575 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
576 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
577 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 578 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
579 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
580 | else | |
581 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 582 | } |
c7addb90 AK |
583 | } |
584 | ||
e8bc217a MT |
585 | /* |
586 | * Using the cached information from sp->gfns is safe because: | |
587 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
588 | * can't change unless all sptes pointing to it are nuked first. | |
e8bc217a | 589 | */ |
be71e061 XG |
590 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
591 | bool clear_unsync) | |
e8bc217a MT |
592 | { |
593 | int i, offset, nr_present; | |
1403283a | 594 | bool reset_host_protection; |
51fb60d8 | 595 | gpa_t first_pte_gpa; |
e8bc217a MT |
596 | |
597 | offset = nr_present = 0; | |
598 | ||
2032a93d LJ |
599 | /* direct kvm_mmu_page can not be unsync. */ |
600 | BUG_ON(sp->role.direct); | |
601 | ||
e8bc217a MT |
602 | if (PTTYPE == 32) |
603 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
604 | ||
51fb60d8 GJ |
605 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
606 | ||
e8bc217a MT |
607 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
608 | unsigned pte_access; | |
609 | pt_element_t gpte; | |
610 | gpa_t pte_gpa; | |
f55c3f41 | 611 | gfn_t gfn; |
e8bc217a MT |
612 | |
613 | if (!is_shadow_present_pte(sp->spt[i])) | |
614 | continue; | |
615 | ||
51fb60d8 | 616 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
617 | |
618 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
619 | sizeof(pt_element_t))) | |
620 | return -EINVAL; | |
621 | ||
f55c3f41 | 622 | gfn = gpte_to_gfn(gpte); |
a1f4d395 | 623 | if (gfn != sp->gfns[i] || |
f55c3f41 | 624 | !is_present_gpte(gpte) || !(gpte & PT_ACCESSED_MASK)) { |
e8bc217a MT |
625 | u64 nonpresent; |
626 | ||
be71e061 | 627 | if (is_present_gpte(gpte) || !clear_unsync) |
e8bc217a MT |
628 | nonpresent = shadow_trap_nonpresent_pte; |
629 | else | |
630 | nonpresent = shadow_notrap_nonpresent_pte; | |
be38d276 | 631 | drop_spte(vcpu->kvm, &sp->spt[i], nonpresent); |
e8bc217a MT |
632 | continue; |
633 | } | |
634 | ||
635 | nr_present++; | |
636 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
1403283a IE |
637 | if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) { |
638 | pte_access &= ~ACC_WRITE_MASK; | |
639 | reset_host_protection = 0; | |
640 | } else { | |
641 | reset_host_protection = 1; | |
642 | } | |
e8bc217a | 643 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 644 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a IE |
645 | spte_to_pfn(sp->spt[i]), true, false, |
646 | reset_host_protection); | |
e8bc217a MT |
647 | } |
648 | ||
649 | return !nr_present; | |
650 | } | |
651 | ||
6aa8b732 AK |
652 | #undef pt_element_t |
653 | #undef guest_walker | |
654 | #undef FNAME | |
655 | #undef PT_BASE_ADDR_MASK | |
656 | #undef PT_INDEX | |
6aa8b732 | 657 | #undef PT_LEVEL_MASK |
e04da980 JR |
658 | #undef PT_LVL_ADDR_MASK |
659 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 660 | #undef PT_LEVEL_BITS |
cea0f0e7 | 661 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 662 | #undef gpte_to_gfn |
e04da980 | 663 | #undef gpte_to_gfn_lvl |
b3e4e63f | 664 | #undef CMPXCHG |