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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
6aa8b732 | 34 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) |
c7addb90 | 35 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
36 | #ifdef CONFIG_X86_64 |
37 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 38 | #define CMPXCHG cmpxchg |
cea0f0e7 | 39 | #else |
b3e4e63f | 40 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
41 | #define PT_MAX_FULL_LEVELS 2 |
42 | #endif | |
6aa8b732 AK |
43 | #elif PTTYPE == 32 |
44 | #define pt_element_t u32 | |
45 | #define guest_walker guest_walker32 | |
46 | #define FNAME(name) paging##32_##name | |
47 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
48 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
49 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 50 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
6aa8b732 | 51 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) |
c7addb90 | 52 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 53 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 54 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
55 | #else |
56 | #error Invalid PTTYPE value | |
57 | #endif | |
58 | ||
e04da980 JR |
59 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
60 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 61 | |
6aa8b732 AK |
62 | /* |
63 | * The guest_walker structure emulates the behavior of the hardware page | |
64 | * table walker. | |
65 | */ | |
66 | struct guest_walker { | |
67 | int level; | |
cea0f0e7 | 68 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 69 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 70 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 71 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
72 | unsigned pt_access; |
73 | unsigned pte_access; | |
815af8d4 | 74 | gfn_t gfn; |
8c28d031 | 75 | struct x86_exception fault; |
6aa8b732 AK |
76 | }; |
77 | ||
e04da980 | 78 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 79 | { |
e04da980 | 80 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
81 | } |
82 | ||
b3e4e63f MT |
83 | static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, |
84 | gfn_t table_gfn, unsigned index, | |
85 | pt_element_t orig_pte, pt_element_t new_pte) | |
86 | { | |
87 | pt_element_t ret; | |
88 | pt_element_t *table; | |
89 | struct page *page; | |
90 | ||
91 | page = gfn_to_page(kvm, table_gfn); | |
72dc67a6 | 92 | |
b3e4e63f | 93 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 94 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
95 | kunmap_atomic(table, KM_USER0); |
96 | ||
97 | kvm_release_page_dirty(page); | |
98 | ||
99 | return (ret != orig_pte); | |
100 | } | |
101 | ||
bedbe4ee AK |
102 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
103 | { | |
104 | unsigned access; | |
105 | ||
106 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
107 | #if PTTYPE == 64 | |
2d48a985 | 108 | if (vcpu->arch.mmu.nx) |
bedbe4ee AK |
109 | access &= ~(gpte >> PT64_NX_SHIFT); |
110 | #endif | |
111 | return access; | |
112 | } | |
113 | ||
ac79c978 AK |
114 | /* |
115 | * Fetch a guest pte for a guest virtual address | |
116 | */ | |
1e301feb JR |
117 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
118 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 119 | gva_t addr, u32 access) |
6aa8b732 | 120 | { |
42bf3f0a | 121 | pt_element_t pte; |
cea0f0e7 | 122 | gfn_t table_gfn; |
f59c1d2d | 123 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 124 | gpa_t pte_gpa; |
f59c1d2d | 125 | bool eperm, present, rsvd_fault; |
33770780 XG |
126 | int offset, write_fault, user_fault, fetch_fault; |
127 | ||
128 | write_fault = access & PFERR_WRITE_MASK; | |
129 | user_fault = access & PFERR_USER_MASK; | |
130 | fetch_fault = access & PFERR_FETCH_MASK; | |
6aa8b732 | 131 | |
07420171 AK |
132 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
133 | fetch_fault); | |
b3e4e63f | 134 | walk: |
f59c1d2d AK |
135 | present = true; |
136 | eperm = rsvd_fault = false; | |
1e301feb JR |
137 | walker->level = mmu->root_level; |
138 | pte = mmu->get_cr3(vcpu); | |
139 | ||
1b0973bd | 140 | #if PTTYPE == 64 |
1e301feb | 141 | if (walker->level == PT32E_ROOT_LEVEL) { |
d41d1895 | 142 | pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3); |
07420171 | 143 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
144 | if (!is_present_gpte(pte)) { |
145 | present = false; | |
146 | goto error; | |
147 | } | |
1b0973bd AK |
148 | --walker->level; |
149 | } | |
150 | #endif | |
a9058ecd | 151 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 152 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 153 | |
fe135d2c | 154 | pt_access = ACC_ALL; |
ac79c978 AK |
155 | |
156 | for (;;) { | |
42bf3f0a | 157 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 158 | |
5fb07ddb | 159 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
160 | offset = index * sizeof(pt_element_t); |
161 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 162 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 163 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 164 | |
2329d46d JR |
165 | if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte, |
166 | offset, sizeof(pte), | |
167 | PFERR_USER_MASK|PFERR_WRITE_MASK)) { | |
f59c1d2d AK |
168 | present = false; |
169 | break; | |
170 | } | |
a6085fba | 171 | |
07420171 | 172 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 173 | |
f59c1d2d AK |
174 | if (!is_present_gpte(pte)) { |
175 | present = false; | |
176 | break; | |
177 | } | |
7993ba43 | 178 | |
3241f22d | 179 | if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) { |
f59c1d2d AK |
180 | rsvd_fault = true; |
181 | break; | |
182 | } | |
82725b20 | 183 | |
8dae4445 | 184 | if (write_fault && !is_writable_pte(pte)) |
7993ba43 | 185 | if (user_fault || is_write_protection(vcpu)) |
f59c1d2d | 186 | eperm = true; |
7993ba43 | 187 | |
42bf3f0a | 188 | if (user_fault && !(pte & PT_USER_MASK)) |
f59c1d2d | 189 | eperm = true; |
7993ba43 | 190 | |
73b1087e | 191 | #if PTTYPE == 64 |
24222c2f | 192 | if (fetch_fault && (pte & PT64_NX_MASK)) |
f59c1d2d | 193 | eperm = true; |
73b1087e AK |
194 | #endif |
195 | ||
f59c1d2d | 196 | if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) { |
07420171 AK |
197 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
198 | sizeof(pte)); | |
b3e4e63f MT |
199 | if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, |
200 | index, pte, pte|PT_ACCESSED_MASK)) | |
201 | goto walk; | |
f3b8c964 | 202 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 203 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 204 | } |
815af8d4 | 205 | |
bedbe4ee | 206 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 207 | |
7819026e MT |
208 | walker->ptes[walker->level - 1] = pte; |
209 | ||
e04da980 JR |
210 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
211 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 212 | is_large_pte(pte) && |
e04da980 JR |
213 | (PTTYPE == 64 || is_pse(vcpu))) || |
214 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 215 | is_large_pte(pte) && |
1e301feb | 216 | mmu->root_level == PT64_ROOT_LEVEL)) { |
e04da980 | 217 | int lvl = walker->level; |
2329d46d JR |
218 | gpa_t real_gpa; |
219 | gfn_t gfn; | |
33770780 | 220 | u32 ac; |
e04da980 | 221 | |
2329d46d JR |
222 | gfn = gpte_to_gfn_lvl(pte, lvl); |
223 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
224 | |
225 | if (PTTYPE == 32 && | |
226 | walker->level == PT_DIRECTORY_LEVEL && | |
227 | is_cpuid_PSE36()) | |
2329d46d JR |
228 | gfn += pse36_gfn_delta(pte); |
229 | ||
33770780 | 230 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
231 | |
232 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 233 | ac); |
2329d46d JR |
234 | if (real_gpa == UNMAPPED_GVA) |
235 | return 0; | |
236 | ||
237 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 238 | |
ac79c978 | 239 | break; |
815af8d4 | 240 | } |
ac79c978 | 241 | |
fe135d2c | 242 | pt_access = pte_access; |
ac79c978 AK |
243 | --walker->level; |
244 | } | |
42bf3f0a | 245 | |
f59c1d2d AK |
246 | if (!present || eperm || rsvd_fault) |
247 | goto error; | |
248 | ||
43a3795a | 249 | if (write_fault && !is_dirty_gpte(pte)) { |
b3e4e63f MT |
250 | bool ret; |
251 | ||
07420171 | 252 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
b3e4e63f MT |
253 | ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte, |
254 | pte|PT_DIRTY_MASK); | |
255 | if (ret) | |
256 | goto walk; | |
f3b8c964 | 257 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 258 | pte |= PT_DIRTY_MASK; |
7819026e | 259 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
260 | } |
261 | ||
fe135d2c AK |
262 | walker->pt_access = pt_access; |
263 | walker->pte_access = pte_access; | |
264 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 265 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
266 | return 1; |
267 | ||
f59c1d2d | 268 | error: |
8c28d031 AK |
269 | walker->fault.vector = PF_VECTOR; |
270 | walker->fault.error_code_valid = true; | |
271 | walker->fault.error_code = 0; | |
f59c1d2d | 272 | if (present) |
8c28d031 | 273 | walker->fault.error_code |= PFERR_PRESENT_MASK; |
20bd40dc | 274 | |
8c28d031 | 275 | walker->fault.error_code |= write_fault | user_fault; |
20bd40dc | 276 | |
2d48a985 | 277 | if (fetch_fault && mmu->nx) |
8c28d031 | 278 | walker->fault.error_code |= PFERR_FETCH_MASK; |
82725b20 | 279 | if (rsvd_fault) |
8c28d031 | 280 | walker->fault.error_code |= PFERR_RSVD_MASK; |
8df25a32 | 281 | |
6389ee94 AK |
282 | walker->fault.address = addr; |
283 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 284 | |
8c28d031 | 285 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 286 | return 0; |
6aa8b732 AK |
287 | } |
288 | ||
1e301feb | 289 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 290 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
291 | { |
292 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 293 | access); |
1e301feb JR |
294 | } |
295 | ||
6539e738 JR |
296 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
297 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 298 | u32 access) |
6539e738 JR |
299 | { |
300 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 301 | addr, access); |
6539e738 JR |
302 | } |
303 | ||
407c61c6 XG |
304 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
305 | struct kvm_mmu_page *sp, u64 *spte, | |
306 | pt_element_t gpte) | |
307 | { | |
308 | u64 nonpresent = shadow_trap_nonpresent_pte; | |
309 | ||
310 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
311 | goto no_present; | |
312 | ||
313 | if (!is_present_gpte(gpte)) { | |
314 | if (!sp->unsync) | |
315 | nonpresent = shadow_notrap_nonpresent_pte; | |
316 | goto no_present; | |
317 | } | |
318 | ||
319 | if (!(gpte & PT_ACCESSED_MASK)) | |
320 | goto no_present; | |
321 | ||
322 | return false; | |
323 | ||
324 | no_present: | |
325 | drop_spte(vcpu->kvm, spte, nonpresent); | |
326 | return true; | |
327 | } | |
328 | ||
ac3cd03c | 329 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
489f1d65 | 330 | u64 *spte, const void *pte) |
0028425f AK |
331 | { |
332 | pt_element_t gpte; | |
41074d07 | 333 | unsigned pte_access; |
35149e21 | 334 | pfn_t pfn; |
0028425f | 335 | |
0028425f | 336 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 337 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 338 | return; |
407c61c6 | 339 | |
b8688d51 | 340 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 341 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
d7824fff AK |
342 | if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn) |
343 | return; | |
35149e21 AL |
344 | pfn = vcpu->arch.update_pte.pfn; |
345 | if (is_error_pfn(pfn)) | |
d7824fff | 346 | return; |
e930bffe AA |
347 | if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq)) |
348 | return; | |
35149e21 | 349 | kvm_get_pfn(pfn); |
1403283a | 350 | /* |
9bdbba13 | 351 | * we call mmu_set_spte() with host_writable = true beacuse that |
1403283a IE |
352 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
353 | */ | |
ac3cd03c | 354 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 355 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 356 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
357 | } |
358 | ||
39c8c672 AK |
359 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
360 | struct guest_walker *gw, int level) | |
361 | { | |
39c8c672 | 362 | pt_element_t curr_pte; |
189be38d XG |
363 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
364 | u64 mask; | |
365 | int r, index; | |
366 | ||
367 | if (level == PT_PAGE_TABLE_LEVEL) { | |
368 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
369 | base_gpa = pte_gpa & ~mask; | |
370 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
371 | ||
372 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
373 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
374 | curr_pte = gw->prefetch_ptes[index]; | |
375 | } else | |
376 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 377 | &curr_pte, sizeof(curr_pte)); |
189be38d | 378 | |
39c8c672 AK |
379 | return r || curr_pte != gw->ptes[level - 1]; |
380 | } | |
381 | ||
189be38d XG |
382 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
383 | u64 *sptep) | |
957ed9ef XG |
384 | { |
385 | struct kvm_mmu_page *sp; | |
189be38d | 386 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 387 | u64 *spte; |
189be38d | 388 | int i; |
957ed9ef XG |
389 | |
390 | sp = page_header(__pa(sptep)); | |
391 | ||
392 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
393 | return; | |
394 | ||
395 | if (sp->role.direct) | |
396 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
397 | ||
398 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
399 | spte = sp->spt + i; |
400 | ||
401 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
402 | pt_element_t gpte; | |
403 | unsigned pte_access; | |
404 | gfn_t gfn; | |
405 | pfn_t pfn; | |
406 | bool dirty; | |
407 | ||
408 | if (spte == sptep) | |
409 | continue; | |
410 | ||
411 | if (*spte != shadow_trap_nonpresent_pte) | |
412 | continue; | |
413 | ||
414 | gpte = gptep[i]; | |
415 | ||
407c61c6 | 416 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
417 | continue; |
418 | ||
419 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
420 | gfn = gpte_to_gfn(gpte); | |
421 | dirty = is_dirty_gpte(gpte); | |
422 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
423 | (pte_access & ACC_WRITE_MASK) && dirty); | |
424 | if (is_error_pfn(pfn)) { | |
425 | kvm_release_pfn_clean(pfn); | |
426 | break; | |
427 | } | |
428 | ||
429 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
430 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
431 | pfn, true, true); | |
432 | } | |
433 | } | |
434 | ||
6aa8b732 AK |
435 | /* |
436 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
437 | */ | |
e7a04c99 AK |
438 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
439 | struct guest_walker *gw, | |
7e4e4056 | 440 | int user_fault, int write_fault, int hlevel, |
fb67e14f XG |
441 | int *ptwrite, pfn_t pfn, bool map_writable, |
442 | bool prefault) | |
6aa8b732 | 443 | { |
abb9e0b8 | 444 | unsigned access = gw->pt_access; |
5991b332 | 445 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 446 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 447 | int top_level; |
84754cd8 | 448 | unsigned direct_access; |
24157aaf | 449 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 450 | |
43a3795a | 451 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 452 | return NULL; |
6aa8b732 | 453 | |
84754cd8 XG |
454 | direct_access = gw->pt_access & gw->pte_access; |
455 | if (!dirty) | |
456 | direct_access &= ~ACC_WRITE_MASK; | |
457 | ||
5991b332 AK |
458 | top_level = vcpu->arch.mmu.root_level; |
459 | if (top_level == PT32E_ROOT_LEVEL) | |
460 | top_level = PT32_ROOT_LEVEL; | |
461 | /* | |
462 | * Verify that the top-level gpte is still there. Since the page | |
463 | * is a root page, it is either write protected (and cannot be | |
464 | * changed from now on) or it is invalid (in which case, we don't | |
465 | * really care if it changes underneath us after this point). | |
466 | */ | |
467 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
468 | goto out_gpte_changed; | |
469 | ||
24157aaf AK |
470 | for (shadow_walk_init(&it, vcpu, addr); |
471 | shadow_walk_okay(&it) && it.level > gw->level; | |
472 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
473 | gfn_t table_gfn; |
474 | ||
24157aaf | 475 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 476 | |
5991b332 | 477 | sp = NULL; |
24157aaf AK |
478 | if (!is_shadow_present_pte(*it.sptep)) { |
479 | table_gfn = gw->table_gfn[it.level - 2]; | |
480 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
481 | false, access, it.sptep); | |
5991b332 | 482 | } |
0b3c9333 AK |
483 | |
484 | /* | |
485 | * Verify that the gpte in the page we've just write | |
486 | * protected is still there. | |
487 | */ | |
24157aaf | 488 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 489 | goto out_gpte_changed; |
abb9e0b8 | 490 | |
5991b332 | 491 | if (sp) |
24157aaf | 492 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 493 | } |
050e6499 | 494 | |
0b3c9333 | 495 | for (; |
24157aaf AK |
496 | shadow_walk_okay(&it) && it.level > hlevel; |
497 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
498 | gfn_t direct_gfn; |
499 | ||
24157aaf | 500 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 501 | |
24157aaf | 502 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 503 | |
24157aaf | 504 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
505 | continue; |
506 | ||
24157aaf | 507 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 508 | |
24157aaf AK |
509 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
510 | true, direct_access, it.sptep); | |
511 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
512 | } |
513 | ||
d3c422bd AK |
514 | if (!map_writable) |
515 | access &= ~ACC_WRITE_MASK; | |
516 | ||
24157aaf AK |
517 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
518 | user_fault, write_fault, dirty, ptwrite, it.level, | |
fb67e14f | 519 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 520 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 521 | |
24157aaf | 522 | return it.sptep; |
0b3c9333 AK |
523 | |
524 | out_gpte_changed: | |
5991b332 | 525 | if (sp) |
24157aaf | 526 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
527 | kvm_release_pfn_clean(pfn); |
528 | return NULL; | |
6aa8b732 AK |
529 | } |
530 | ||
6aa8b732 AK |
531 | /* |
532 | * Page fault handler. There are several causes for a page fault: | |
533 | * - there is no shadow pte for the guest pte | |
534 | * - write access through a shadow pte marked read only so that we can set | |
535 | * the dirty bit | |
536 | * - write access to a shadow pte marked read only so we can update the page | |
537 | * dirty bitmap, when userspace requests it | |
538 | * - mmio access; in this case we will never install a present shadow pte | |
539 | * - normal guest page fault due to the guest pte marked not present, not | |
540 | * writable, or not executable | |
541 | * | |
e2dec939 AK |
542 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
543 | * a negative value on error. | |
6aa8b732 | 544 | */ |
56028d08 | 545 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 546 | bool prefault) |
6aa8b732 AK |
547 | { |
548 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
549 | int user_fault = error_code & PFERR_USER_MASK; |
550 | struct guest_walker walker; | |
d555c333 | 551 | u64 *sptep; |
cea0f0e7 | 552 | int write_pt = 0; |
e2dec939 | 553 | int r; |
35149e21 | 554 | pfn_t pfn; |
7e4e4056 | 555 | int level = PT_PAGE_TABLE_LEVEL; |
e930bffe | 556 | unsigned long mmu_seq; |
612819c3 | 557 | bool map_writable; |
6aa8b732 | 558 | |
b8688d51 | 559 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 560 | |
e2dec939 AK |
561 | r = mmu_topup_memory_caches(vcpu); |
562 | if (r) | |
563 | return r; | |
714b93da | 564 | |
6aa8b732 | 565 | /* |
a8b876b1 | 566 | * Look up the guest pte for the faulting address. |
6aa8b732 | 567 | */ |
33770780 | 568 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
569 | |
570 | /* | |
571 | * The page is not mapped by the guest. Let the guest handle it. | |
572 | */ | |
7993ba43 | 573 | if (!r) { |
b8688d51 | 574 | pgprintk("%s: guest page fault\n", __func__); |
fb67e14f XG |
575 | if (!prefault) { |
576 | inject_page_fault(vcpu, &walker.fault); | |
577 | /* reset fork detector */ | |
578 | vcpu->arch.last_pt_write_count = 0; | |
579 | } | |
6aa8b732 AK |
580 | return 0; |
581 | } | |
582 | ||
7e4e4056 JR |
583 | if (walker.level >= PT_DIRECTORY_LEVEL) { |
584 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); | |
585 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 586 | } |
7e4e4056 | 587 | |
e930bffe | 588 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 589 | smp_rmb(); |
af585b92 | 590 | |
78b2c54a | 591 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 592 | &map_writable)) |
af585b92 | 593 | return 0; |
d7824fff | 594 | |
d196e343 | 595 | /* mmio */ |
bf998156 HY |
596 | if (is_error_pfn(pfn)) |
597 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 598 | |
aaee2c94 | 599 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
600 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
601 | goto out_unlock; | |
bc32ce21 | 602 | |
8b1fe17c | 603 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 604 | kvm_mmu_free_some_pages(vcpu); |
d555c333 | 605 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
fb67e14f | 606 | level, &write_pt, pfn, map_writable, prefault); |
a24e8099 | 607 | (void)sptep; |
b8688d51 | 608 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 609 | sptep, *sptep, write_pt); |
cea0f0e7 | 610 | |
a25f7e1f | 611 | if (!write_pt) |
ad312c7c | 612 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 613 | |
1165f5fe | 614 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 615 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 616 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 617 | |
cea0f0e7 | 618 | return write_pt; |
e930bffe AA |
619 | |
620 | out_unlock: | |
621 | spin_unlock(&vcpu->kvm->mmu_lock); | |
622 | kvm_release_pfn_clean(pfn); | |
623 | return 0; | |
6aa8b732 AK |
624 | } |
625 | ||
a461930b | 626 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 627 | { |
a461930b | 628 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 629 | struct kvm_mmu_page *sp; |
08e850c6 | 630 | gpa_t pte_gpa = -1; |
a461930b AK |
631 | int level; |
632 | u64 *sptep; | |
4539b358 | 633 | int need_flush = 0; |
a461930b AK |
634 | |
635 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 636 | |
a461930b AK |
637 | for_each_shadow_entry(vcpu, gva, iterator) { |
638 | level = iterator.level; | |
639 | sptep = iterator.sptep; | |
ad218f85 | 640 | |
f78978aa | 641 | sp = page_header(__pa(sptep)); |
884a0ff0 | 642 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 643 | int offset, shift; |
08e850c6 | 644 | |
f78978aa XG |
645 | if (!sp->unsync) |
646 | break; | |
647 | ||
22c9b2d1 XG |
648 | shift = PAGE_SHIFT - |
649 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
650 | offset = sp->role.quadrant << shift; | |
651 | ||
652 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 653 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
654 | |
655 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
656 | if (is_large_pte(*sptep)) |
657 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
658 | drop_spte(vcpu->kvm, sptep, |
659 | shadow_trap_nonpresent_pte); | |
4539b358 | 660 | need_flush = 1; |
be38d276 AK |
661 | } else |
662 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 663 | break; |
87917239 | 664 | } |
a7052897 | 665 | |
f78978aa | 666 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
667 | break; |
668 | } | |
a7052897 | 669 | |
4539b358 AA |
670 | if (need_flush) |
671 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
672 | |
673 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
674 | ||
ad218f85 | 675 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
676 | |
677 | if (pte_gpa == -1) | |
678 | return; | |
679 | ||
680 | if (mmu_topup_memory_caches(vcpu)) | |
681 | return; | |
682 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
683 | } |
684 | ||
1871c602 | 685 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 686 | struct x86_exception *exception) |
6aa8b732 AK |
687 | { |
688 | struct guest_walker walker; | |
e119d117 AK |
689 | gpa_t gpa = UNMAPPED_GVA; |
690 | int r; | |
6aa8b732 | 691 | |
33770780 | 692 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 693 | |
e119d117 | 694 | if (r) { |
1755fbcc | 695 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 696 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
697 | } else if (exception) |
698 | *exception = walker.fault; | |
6aa8b732 AK |
699 | |
700 | return gpa; | |
701 | } | |
702 | ||
6539e738 | 703 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
704 | u32 access, |
705 | struct x86_exception *exception) | |
6539e738 JR |
706 | { |
707 | struct guest_walker walker; | |
708 | gpa_t gpa = UNMAPPED_GVA; | |
709 | int r; | |
710 | ||
33770780 | 711 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
712 | |
713 | if (r) { | |
714 | gpa = gfn_to_gpa(walker.gfn); | |
715 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
716 | } else if (exception) |
717 | *exception = walker.fault; | |
6539e738 JR |
718 | |
719 | return gpa; | |
720 | } | |
721 | ||
c7addb90 AK |
722 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
723 | struct kvm_mmu_page *sp) | |
724 | { | |
eab9f71f AK |
725 | int i, j, offset, r; |
726 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
727 | gpa_t pte_gpa; | |
c7addb90 | 728 | |
f6e2c02b | 729 | if (sp->role.direct |
e5a4c8ca | 730 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
731 | nonpaging_prefetch_page(vcpu, sp); |
732 | return; | |
733 | } | |
734 | ||
eab9f71f AK |
735 | pte_gpa = gfn_to_gpa(sp->gfn); |
736 | if (PTTYPE == 32) { | |
e5a4c8ca | 737 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
738 | pte_gpa += offset * sizeof(pt_element_t); |
739 | } | |
7ec54588 | 740 | |
eab9f71f AK |
741 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
742 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
743 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
744 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 745 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
746 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
747 | else | |
748 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 749 | } |
c7addb90 AK |
750 | } |
751 | ||
e8bc217a MT |
752 | /* |
753 | * Using the cached information from sp->gfns is safe because: | |
754 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
755 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
756 | * |
757 | * Note: | |
758 | * We should flush all tlbs if spte is dropped even though guest is | |
759 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
760 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
761 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
762 | * freed pages. | |
763 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 764 | */ |
a4a8e6f7 | 765 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a MT |
766 | { |
767 | int i, offset, nr_present; | |
9bdbba13 | 768 | bool host_writable; |
51fb60d8 | 769 | gpa_t first_pte_gpa; |
e8bc217a MT |
770 | |
771 | offset = nr_present = 0; | |
772 | ||
2032a93d LJ |
773 | /* direct kvm_mmu_page can not be unsync. */ |
774 | BUG_ON(sp->role.direct); | |
775 | ||
e8bc217a MT |
776 | if (PTTYPE == 32) |
777 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
778 | ||
51fb60d8 GJ |
779 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
780 | ||
e8bc217a MT |
781 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
782 | unsigned pte_access; | |
783 | pt_element_t gpte; | |
784 | gpa_t pte_gpa; | |
f55c3f41 | 785 | gfn_t gfn; |
e8bc217a MT |
786 | |
787 | if (!is_shadow_present_pte(sp->spt[i])) | |
788 | continue; | |
789 | ||
51fb60d8 | 790 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
791 | |
792 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
793 | sizeof(pt_element_t))) | |
794 | return -EINVAL; | |
795 | ||
f55c3f41 | 796 | gfn = gpte_to_gfn(gpte); |
407c61c6 XG |
797 | |
798 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { | |
a4ee1ca4 | 799 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
800 | continue; |
801 | } | |
802 | ||
803 | if (gfn != sp->gfns[i]) { | |
804 | drop_spte(vcpu->kvm, &sp->spt[i], | |
805 | shadow_trap_nonpresent_pte); | |
a4ee1ca4 | 806 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
807 | continue; |
808 | } | |
809 | ||
810 | nr_present++; | |
811 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
1403283a IE |
812 | if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) { |
813 | pte_access &= ~ACC_WRITE_MASK; | |
9bdbba13 | 814 | host_writable = 0; |
1403283a | 815 | } else { |
9bdbba13 | 816 | host_writable = 1; |
1403283a | 817 | } |
e8bc217a | 818 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 819 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 820 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 821 | host_writable); |
e8bc217a MT |
822 | } |
823 | ||
824 | return !nr_present; | |
825 | } | |
826 | ||
6aa8b732 AK |
827 | #undef pt_element_t |
828 | #undef guest_walker | |
829 | #undef FNAME | |
830 | #undef PT_BASE_ADDR_MASK | |
831 | #undef PT_INDEX | |
6aa8b732 | 832 | #undef PT_LEVEL_MASK |
e04da980 JR |
833 | #undef PT_LVL_ADDR_MASK |
834 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 835 | #undef PT_LEVEL_BITS |
cea0f0e7 | 836 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 837 | #undef gpte_to_gfn |
e04da980 | 838 | #undef gpte_to_gfn_lvl |
b3e4e63f | 839 | #undef CMPXCHG |