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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
8cbc7069 | 66 | unsigned max_level; |
cea0f0e7 | 67 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 68 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 69 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 70 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 71 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
72 | unsigned pt_access; |
73 | unsigned pte_access; | |
815af8d4 | 74 | gfn_t gfn; |
8c28d031 | 75 | struct x86_exception fault; |
6aa8b732 AK |
76 | }; |
77 | ||
e04da980 | 78 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 79 | { |
e04da980 | 80 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
81 | } |
82 | ||
a78484c6 | 83 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
84 | pt_element_t __user *ptep_user, unsigned index, |
85 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 86 | { |
c8cfbb55 | 87 | int npages; |
b3e4e63f MT |
88 | pt_element_t ret; |
89 | pt_element_t *table; | |
90 | struct page *page; | |
91 | ||
c8cfbb55 TY |
92 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
93 | /* Check if the user is doing something meaningless. */ | |
94 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
95 | return -EFAULT; |
96 | ||
8fd75e12 | 97 | table = kmap_atomic(page); |
b3e4e63f | 98 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 99 | kunmap_atomic(table); |
b3e4e63f MT |
100 | |
101 | kvm_release_page_dirty(page); | |
102 | ||
103 | return (ret != orig_pte); | |
104 | } | |
105 | ||
8cbc7069 AK |
106 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
107 | struct kvm_mmu *mmu, | |
108 | struct guest_walker *walker, | |
109 | int write_fault) | |
110 | { | |
111 | unsigned level, index; | |
112 | pt_element_t pte, orig_pte; | |
113 | pt_element_t __user *ptep_user; | |
114 | gfn_t table_gfn; | |
115 | int ret; | |
116 | ||
117 | for (level = walker->max_level; level >= walker->level; --level) { | |
118 | pte = orig_pte = walker->ptes[level - 1]; | |
119 | table_gfn = walker->table_gfn[level - 1]; | |
120 | ptep_user = walker->ptep_user[level - 1]; | |
121 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
122 | if (!(pte & PT_ACCESSED_MASK)) { | |
123 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); | |
124 | pte |= PT_ACCESSED_MASK; | |
125 | } | |
126 | if (level == walker->level && write_fault && !is_dirty_gpte(pte)) { | |
127 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); | |
128 | pte |= PT_DIRTY_MASK; | |
129 | } | |
130 | if (pte == orig_pte) | |
131 | continue; | |
132 | ||
133 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); | |
134 | if (ret) | |
135 | return ret; | |
136 | ||
137 | mark_page_dirty(vcpu->kvm, table_gfn); | |
138 | walker->ptes[level] = pte; | |
139 | } | |
140 | return 0; | |
141 | } | |
142 | ||
ac79c978 AK |
143 | /* |
144 | * Fetch a guest pte for a guest virtual address | |
145 | */ | |
1e301feb JR |
146 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
147 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 148 | gva_t addr, u32 access) |
6aa8b732 | 149 | { |
8cbc7069 | 150 | int ret; |
42bf3f0a | 151 | pt_element_t pte; |
b7233635 | 152 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 153 | gfn_t table_gfn; |
b0cfeb5d | 154 | unsigned index, pt_access, pte_access, accessed_dirty; |
42bf3f0a | 155 | gpa_t pte_gpa; |
134291bf TY |
156 | int offset; |
157 | const int write_fault = access & PFERR_WRITE_MASK; | |
158 | const int user_fault = access & PFERR_USER_MASK; | |
159 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
160 | u16 errcode = 0; | |
13d22b6a AK |
161 | gpa_t real_gpa; |
162 | gfn_t gfn; | |
6aa8b732 | 163 | |
6fbc2770 | 164 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 165 | retry_walk: |
1e301feb JR |
166 | walker->level = mmu->root_level; |
167 | pte = mmu->get_cr3(vcpu); | |
168 | ||
1b0973bd | 169 | #if PTTYPE == 64 |
1e301feb | 170 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 171 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 172 | trace_kvm_mmu_paging_element(pte, walker->level); |
134291bf | 173 | if (!is_present_gpte(pte)) |
f59c1d2d | 174 | goto error; |
1b0973bd AK |
175 | --walker->level; |
176 | } | |
177 | #endif | |
8cbc7069 | 178 | walker->max_level = walker->level; |
a9058ecd | 179 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 180 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 181 | |
b514c30f | 182 | accessed_dirty = PT_ACCESSED_MASK; |
13d22b6a AK |
183 | pt_access = pte_access = ACC_ALL; |
184 | ++walker->level; | |
ac79c978 | 185 | |
13d22b6a | 186 | do { |
6e2ca7d1 TY |
187 | gfn_t real_gfn; |
188 | unsigned long host_addr; | |
189 | ||
13d22b6a AK |
190 | pt_access &= pte_access; |
191 | --walker->level; | |
192 | ||
42bf3f0a | 193 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 194 | |
5fb07ddb | 195 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
196 | offset = index * sizeof(pt_element_t); |
197 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 198 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 199 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 200 | |
6e2ca7d1 TY |
201 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
202 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
203 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
204 | goto error; | |
6e2ca7d1 TY |
205 | real_gfn = gpa_to_gfn(real_gfn); |
206 | ||
207 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
208 | if (unlikely(kvm_is_error_hva(host_addr))) |
209 | goto error; | |
6e2ca7d1 TY |
210 | |
211 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
212 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
213 | goto error; | |
8cbc7069 | 214 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 215 | |
07420171 | 216 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 217 | |
134291bf TY |
218 | if (unlikely(!is_present_gpte(pte))) |
219 | goto error; | |
7993ba43 | 220 | |
781e0743 AK |
221 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
222 | walker->level))) { | |
134291bf TY |
223 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
224 | goto error; | |
f59c1d2d | 225 | } |
82725b20 | 226 | |
b514c30f | 227 | accessed_dirty &= pte; |
97d64b78 | 228 | pte_access = pt_access & gpte_access(vcpu, pte); |
73b1087e | 229 | |
7819026e | 230 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 231 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 232 | |
71331a1d | 233 | if (unlikely(permission_fault(mmu, pte_access, access))) { |
134291bf | 234 | errcode |= PFERR_PRESENT_MASK; |
f59c1d2d | 235 | goto error; |
134291bf | 236 | } |
f59c1d2d | 237 | |
13d22b6a AK |
238 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
239 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
240 | ||
241 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
242 | gfn += pse36_gfn_delta(pte); | |
243 | ||
c5421519 | 244 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access); |
13d22b6a AK |
245 | if (real_gpa == UNMAPPED_GVA) |
246 | return 0; | |
247 | ||
248 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
249 | ||
8ea667f2 AK |
250 | if (!write_fault) |
251 | protect_clean_gpte(&pte_access, pte); | |
908e7d79 GN |
252 | else |
253 | /* | |
254 | * On a write fault, fold the dirty bit into accessed_dirty by | |
255 | * shifting it one place right. | |
256 | */ | |
257 | accessed_dirty &= pte >> (PT_DIRTY_SHIFT - PT_ACCESSED_SHIFT); | |
b514c30f AK |
258 | |
259 | if (unlikely(!accessed_dirty)) { | |
260 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
261 | if (unlikely(ret < 0)) | |
262 | goto error; | |
263 | else if (ret) | |
264 | goto retry_walk; | |
265 | } | |
42bf3f0a | 266 | |
fe135d2c AK |
267 | walker->pt_access = pt_access; |
268 | walker->pte_access = pte_access; | |
269 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 270 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
271 | return 1; |
272 | ||
f59c1d2d | 273 | error: |
134291bf | 274 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
275 | if (fetch_fault && (mmu->nx || |
276 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 277 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 278 | |
134291bf TY |
279 | walker->fault.vector = PF_VECTOR; |
280 | walker->fault.error_code_valid = true; | |
281 | walker->fault.error_code = errcode; | |
6389ee94 AK |
282 | walker->fault.address = addr; |
283 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 284 | |
8c28d031 | 285 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 286 | return 0; |
6aa8b732 AK |
287 | } |
288 | ||
1e301feb | 289 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 290 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
291 | { |
292 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 293 | access); |
1e301feb JR |
294 | } |
295 | ||
6539e738 JR |
296 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
297 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 298 | u32 access) |
6539e738 JR |
299 | { |
300 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 301 | addr, access); |
6539e738 JR |
302 | } |
303 | ||
bd6360cc XG |
304 | static bool |
305 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
306 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 307 | { |
41074d07 | 308 | unsigned pte_access; |
bd6360cc | 309 | gfn_t gfn; |
35149e21 | 310 | pfn_t pfn; |
0028425f | 311 | |
a052b42b | 312 | if (prefetch_invalid_gpte(vcpu, sp, spte, gpte)) |
bd6360cc | 313 | return false; |
407c61c6 | 314 | |
b8688d51 | 315 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
316 | |
317 | gfn = gpte_to_gfn(gpte); | |
3d34adec | 318 | pte_access = sp->role.access & gpte_access(vcpu, gpte); |
8ea667f2 | 319 | protect_clean_gpte(&pte_access, gpte); |
bd6360cc XG |
320 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
321 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 322 | if (is_error_pfn(pfn)) |
bd6360cc | 323 | return false; |
0f53b5b1 | 324 | |
1403283a | 325 | /* |
bd6360cc XG |
326 | * we call mmu_set_spte() with host_writable = true because |
327 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 328 | */ |
ac3cd03c | 329 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
bd6360cc XG |
330 | NULL, PT_PAGE_TABLE_LEVEL, gfn, pfn, true, true); |
331 | ||
332 | return true; | |
333 | } | |
334 | ||
335 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
336 | u64 *spte, const void *pte) | |
337 | { | |
338 | pt_element_t gpte = *(const pt_element_t *)pte; | |
339 | ||
340 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
341 | } |
342 | ||
39c8c672 AK |
343 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
344 | struct guest_walker *gw, int level) | |
345 | { | |
39c8c672 | 346 | pt_element_t curr_pte; |
189be38d XG |
347 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
348 | u64 mask; | |
349 | int r, index; | |
350 | ||
351 | if (level == PT_PAGE_TABLE_LEVEL) { | |
352 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
353 | base_gpa = pte_gpa & ~mask; | |
354 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
355 | ||
356 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
357 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
358 | curr_pte = gw->prefetch_ptes[index]; | |
359 | } else | |
360 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 361 | &curr_pte, sizeof(curr_pte)); |
189be38d | 362 | |
39c8c672 AK |
363 | return r || curr_pte != gw->ptes[level - 1]; |
364 | } | |
365 | ||
189be38d XG |
366 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
367 | u64 *sptep) | |
957ed9ef XG |
368 | { |
369 | struct kvm_mmu_page *sp; | |
189be38d | 370 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 371 | u64 *spte; |
189be38d | 372 | int i; |
957ed9ef XG |
373 | |
374 | sp = page_header(__pa(sptep)); | |
375 | ||
376 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
377 | return; | |
378 | ||
379 | if (sp->role.direct) | |
380 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
381 | ||
382 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
383 | spte = sp->spt + i; |
384 | ||
385 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
386 | if (spte == sptep) |
387 | continue; | |
388 | ||
c3707958 | 389 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
390 | continue; |
391 | ||
bd6360cc | 392 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 393 | break; |
957ed9ef XG |
394 | } |
395 | } | |
396 | ||
6aa8b732 AK |
397 | /* |
398 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
399 | * If the guest tries to write a write-protected page, we need to |
400 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 401 | */ |
d4878f24 | 402 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 403 | struct guest_walker *gw, |
7e4e4056 | 404 | int user_fault, int write_fault, int hlevel, |
d4878f24 | 405 | pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 406 | { |
5991b332 | 407 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 408 | struct kvm_shadow_walk_iterator it; |
d4878f24 XG |
409 | unsigned direct_access, access = gw->pt_access; |
410 | int top_level, emulate = 0; | |
abb9e0b8 | 411 | |
43a3795a | 412 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
d4878f24 | 413 | return 0; |
6aa8b732 | 414 | |
b36c7a7c | 415 | direct_access = gw->pte_access; |
84754cd8 | 416 | |
5991b332 AK |
417 | top_level = vcpu->arch.mmu.root_level; |
418 | if (top_level == PT32E_ROOT_LEVEL) | |
419 | top_level = PT32_ROOT_LEVEL; | |
420 | /* | |
421 | * Verify that the top-level gpte is still there. Since the page | |
422 | * is a root page, it is either write protected (and cannot be | |
423 | * changed from now on) or it is invalid (in which case, we don't | |
424 | * really care if it changes underneath us after this point). | |
425 | */ | |
426 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
427 | goto out_gpte_changed; | |
428 | ||
24157aaf AK |
429 | for (shadow_walk_init(&it, vcpu, addr); |
430 | shadow_walk_okay(&it) && it.level > gw->level; | |
431 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
432 | gfn_t table_gfn; |
433 | ||
a30f47cb | 434 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 435 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 436 | |
5991b332 | 437 | sp = NULL; |
24157aaf AK |
438 | if (!is_shadow_present_pte(*it.sptep)) { |
439 | table_gfn = gw->table_gfn[it.level - 2]; | |
440 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
441 | false, access, it.sptep); | |
5991b332 | 442 | } |
0b3c9333 AK |
443 | |
444 | /* | |
445 | * Verify that the gpte in the page we've just write | |
446 | * protected is still there. | |
447 | */ | |
24157aaf | 448 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 449 | goto out_gpte_changed; |
abb9e0b8 | 450 | |
5991b332 | 451 | if (sp) |
24157aaf | 452 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 453 | } |
050e6499 | 454 | |
0b3c9333 | 455 | for (; |
24157aaf AK |
456 | shadow_walk_okay(&it) && it.level > hlevel; |
457 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
458 | gfn_t direct_gfn; |
459 | ||
a30f47cb | 460 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 461 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 462 | |
24157aaf | 463 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 464 | |
24157aaf | 465 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
466 | continue; |
467 | ||
24157aaf | 468 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 469 | |
24157aaf AK |
470 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
471 | true, direct_access, it.sptep); | |
472 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
473 | } |
474 | ||
a30f47cb | 475 | clear_sp_write_flooding_count(it.sptep); |
b36c7a7c | 476 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access, |
d4878f24 | 477 | user_fault, write_fault, &emulate, it.level, |
fb67e14f | 478 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 479 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 480 | |
d4878f24 | 481 | return emulate; |
0b3c9333 AK |
482 | |
483 | out_gpte_changed: | |
5991b332 | 484 | if (sp) |
24157aaf | 485 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 | 486 | kvm_release_pfn_clean(pfn); |
d4878f24 | 487 | return 0; |
6aa8b732 AK |
488 | } |
489 | ||
6aa8b732 AK |
490 | /* |
491 | * Page fault handler. There are several causes for a page fault: | |
492 | * - there is no shadow pte for the guest pte | |
493 | * - write access through a shadow pte marked read only so that we can set | |
494 | * the dirty bit | |
495 | * - write access to a shadow pte marked read only so we can update the page | |
496 | * dirty bitmap, when userspace requests it | |
497 | * - mmio access; in this case we will never install a present shadow pte | |
498 | * - normal guest page fault due to the guest pte marked not present, not | |
499 | * writable, or not executable | |
500 | * | |
e2dec939 AK |
501 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
502 | * a negative value on error. | |
6aa8b732 | 503 | */ |
56028d08 | 504 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 505 | bool prefault) |
6aa8b732 AK |
506 | { |
507 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
508 | int user_fault = error_code & PFERR_USER_MASK; |
509 | struct guest_walker walker; | |
e2dec939 | 510 | int r; |
35149e21 | 511 | pfn_t pfn; |
7e4e4056 | 512 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 513 | int force_pt_level; |
e930bffe | 514 | unsigned long mmu_seq; |
612819c3 | 515 | bool map_writable; |
6aa8b732 | 516 | |
b8688d51 | 517 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 518 | |
ce88decf XG |
519 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
520 | return handle_mmio_page_fault(vcpu, addr, error_code, | |
521 | mmu_is_nested(vcpu)); | |
522 | ||
e2dec939 AK |
523 | r = mmu_topup_memory_caches(vcpu); |
524 | if (r) | |
525 | return r; | |
714b93da | 526 | |
6aa8b732 | 527 | /* |
a8b876b1 | 528 | * Look up the guest pte for the faulting address. |
6aa8b732 | 529 | */ |
33770780 | 530 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
531 | |
532 | /* | |
533 | * The page is not mapped by the guest. Let the guest handle it. | |
534 | */ | |
7993ba43 | 535 | if (!r) { |
b8688d51 | 536 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 537 | if (!prefault) |
fb67e14f | 538 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 539 | |
6aa8b732 AK |
540 | return 0; |
541 | } | |
542 | ||
936a5fe6 AA |
543 | if (walker.level >= PT_DIRECTORY_LEVEL) |
544 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
545 | else | |
546 | force_pt_level = 1; | |
547 | if (!force_pt_level) { | |
7e4e4056 JR |
548 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
549 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 550 | } |
7e4e4056 | 551 | |
e930bffe | 552 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 553 | smp_rmb(); |
af585b92 | 554 | |
78b2c54a | 555 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 556 | &map_writable)) |
af585b92 | 557 | return 0; |
d7824fff | 558 | |
d7c55201 XG |
559 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
560 | walker.gfn, pfn, walker.pte_access, &r)) | |
561 | return r; | |
562 | ||
aaee2c94 | 563 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 564 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 565 | goto out_unlock; |
bc32ce21 | 566 | |
0375f7fa | 567 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 568 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
569 | if (!force_pt_level) |
570 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d4878f24 XG |
571 | r = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
572 | level, pfn, map_writable, prefault); | |
1165f5fe | 573 | ++vcpu->stat.pf_fixed; |
0375f7fa | 574 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 575 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 576 | |
d4878f24 | 577 | return r; |
e930bffe AA |
578 | |
579 | out_unlock: | |
580 | spin_unlock(&vcpu->kvm->mmu_lock); | |
581 | kvm_release_pfn_clean(pfn); | |
582 | return 0; | |
6aa8b732 AK |
583 | } |
584 | ||
505aef8f XG |
585 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
586 | { | |
587 | int offset = 0; | |
588 | ||
f71fa31f | 589 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
590 | |
591 | if (PTTYPE == 32) | |
592 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
593 | ||
594 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
595 | } | |
596 | ||
a461930b | 597 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 598 | { |
a461930b | 599 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 600 | struct kvm_mmu_page *sp; |
a461930b AK |
601 | int level; |
602 | u64 *sptep; | |
603 | ||
bebb106a XG |
604 | vcpu_clear_mmio_info(vcpu, gva); |
605 | ||
f57f2ef5 XG |
606 | /* |
607 | * No need to check return value here, rmap_can_add() can | |
608 | * help us to skip pte prefetch later. | |
609 | */ | |
610 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 611 | |
f57f2ef5 | 612 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
613 | for_each_shadow_entry(vcpu, gva, iterator) { |
614 | level = iterator.level; | |
615 | sptep = iterator.sptep; | |
ad218f85 | 616 | |
f78978aa | 617 | sp = page_header(__pa(sptep)); |
884a0ff0 | 618 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
619 | pt_element_t gpte; |
620 | gpa_t pte_gpa; | |
621 | ||
f78978aa XG |
622 | if (!sp->unsync) |
623 | break; | |
624 | ||
505aef8f | 625 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 626 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 627 | |
505aef8f XG |
628 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
629 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
630 | |
631 | if (!rmap_can_add(vcpu)) | |
632 | break; | |
633 | ||
634 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
635 | sizeof(pt_element_t))) | |
636 | break; | |
637 | ||
638 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 639 | } |
a7052897 | 640 | |
f78978aa | 641 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
642 | break; |
643 | } | |
ad218f85 | 644 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
645 | } |
646 | ||
1871c602 | 647 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 648 | struct x86_exception *exception) |
6aa8b732 AK |
649 | { |
650 | struct guest_walker walker; | |
e119d117 AK |
651 | gpa_t gpa = UNMAPPED_GVA; |
652 | int r; | |
6aa8b732 | 653 | |
33770780 | 654 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 655 | |
e119d117 | 656 | if (r) { |
1755fbcc | 657 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 658 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
659 | } else if (exception) |
660 | *exception = walker.fault; | |
6aa8b732 AK |
661 | |
662 | return gpa; | |
663 | } | |
664 | ||
6539e738 | 665 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
666 | u32 access, |
667 | struct x86_exception *exception) | |
6539e738 JR |
668 | { |
669 | struct guest_walker walker; | |
670 | gpa_t gpa = UNMAPPED_GVA; | |
671 | int r; | |
672 | ||
33770780 | 673 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
674 | |
675 | if (r) { | |
676 | gpa = gfn_to_gpa(walker.gfn); | |
677 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
678 | } else if (exception) |
679 | *exception = walker.fault; | |
6539e738 JR |
680 | |
681 | return gpa; | |
682 | } | |
683 | ||
e8bc217a MT |
684 | /* |
685 | * Using the cached information from sp->gfns is safe because: | |
686 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
687 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
688 | * |
689 | * Note: | |
690 | * We should flush all tlbs if spte is dropped even though guest is | |
691 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
692 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
693 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
694 | * freed pages. | |
695 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 696 | */ |
a4a8e6f7 | 697 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 698 | { |
505aef8f | 699 | int i, nr_present = 0; |
9bdbba13 | 700 | bool host_writable; |
51fb60d8 | 701 | gpa_t first_pte_gpa; |
e8bc217a | 702 | |
2032a93d LJ |
703 | /* direct kvm_mmu_page can not be unsync. */ |
704 | BUG_ON(sp->role.direct); | |
705 | ||
505aef8f | 706 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 707 | |
e8bc217a MT |
708 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
709 | unsigned pte_access; | |
710 | pt_element_t gpte; | |
711 | gpa_t pte_gpa; | |
f55c3f41 | 712 | gfn_t gfn; |
e8bc217a | 713 | |
ce88decf | 714 | if (!sp->spt[i]) |
e8bc217a MT |
715 | continue; |
716 | ||
51fb60d8 | 717 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
718 | |
719 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
720 | sizeof(pt_element_t))) | |
721 | return -EINVAL; | |
722 | ||
a052b42b | 723 | if (prefetch_invalid_gpte(vcpu, sp, &sp->spt[i], gpte)) { |
a4ee1ca4 | 724 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
725 | continue; |
726 | } | |
727 | ||
ce88decf XG |
728 | gfn = gpte_to_gfn(gpte); |
729 | pte_access = sp->role.access; | |
3d34adec | 730 | pte_access &= gpte_access(vcpu, gpte); |
8ea667f2 | 731 | protect_clean_gpte(&pte_access, gpte); |
ce88decf XG |
732 | |
733 | if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present)) | |
734 | continue; | |
735 | ||
407c61c6 | 736 | if (gfn != sp->gfns[i]) { |
c3707958 | 737 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a4ee1ca4 | 738 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
739 | continue; |
740 | } | |
741 | ||
742 | nr_present++; | |
ce88decf | 743 | |
f8e453b0 XG |
744 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
745 | ||
e8bc217a | 746 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
640d9b0d | 747 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 748 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 749 | host_writable); |
e8bc217a MT |
750 | } |
751 | ||
752 | return !nr_present; | |
753 | } | |
754 | ||
6aa8b732 AK |
755 | #undef pt_element_t |
756 | #undef guest_walker | |
757 | #undef FNAME | |
758 | #undef PT_BASE_ADDR_MASK | |
759 | #undef PT_INDEX | |
e04da980 JR |
760 | #undef PT_LVL_ADDR_MASK |
761 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 762 | #undef PT_LEVEL_BITS |
cea0f0e7 | 763 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 764 | #undef gpte_to_gfn |
e04da980 | 765 | #undef gpte_to_gfn_lvl |
b3e4e63f | 766 | #undef CMPXCHG |