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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
cea0f0e7 | 66 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 67 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 68 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 69 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
70 | unsigned pt_access; |
71 | unsigned pte_access; | |
815af8d4 | 72 | gfn_t gfn; |
8c28d031 | 73 | struct x86_exception fault; |
6aa8b732 AK |
74 | }; |
75 | ||
e04da980 | 76 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 77 | { |
e04da980 | 78 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
79 | } |
80 | ||
a78484c6 | 81 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
82 | pt_element_t __user *ptep_user, unsigned index, |
83 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 84 | { |
c8cfbb55 | 85 | int npages; |
b3e4e63f MT |
86 | pt_element_t ret; |
87 | pt_element_t *table; | |
88 | struct page *page; | |
89 | ||
c8cfbb55 TY |
90 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
91 | /* Check if the user is doing something meaningless. */ | |
92 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
93 | return -EFAULT; |
94 | ||
b3e4e63f | 95 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 96 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
97 | kunmap_atomic(table, KM_USER0); |
98 | ||
99 | kvm_release_page_dirty(page); | |
100 | ||
101 | return (ret != orig_pte); | |
102 | } | |
103 | ||
bedbe4ee AK |
104 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
105 | { | |
106 | unsigned access; | |
107 | ||
108 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
109 | #if PTTYPE == 64 | |
2d48a985 | 110 | if (vcpu->arch.mmu.nx) |
bedbe4ee AK |
111 | access &= ~(gpte >> PT64_NX_SHIFT); |
112 | #endif | |
113 | return access; | |
114 | } | |
115 | ||
ac79c978 AK |
116 | /* |
117 | * Fetch a guest pte for a guest virtual address | |
118 | */ | |
1e301feb JR |
119 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
120 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 121 | gva_t addr, u32 access) |
6aa8b732 | 122 | { |
42bf3f0a | 123 | pt_element_t pte; |
6e2ca7d1 | 124 | pt_element_t __user *ptep_user; |
cea0f0e7 | 125 | gfn_t table_gfn; |
f59c1d2d | 126 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 127 | gpa_t pte_gpa; |
f59c1d2d | 128 | bool eperm, present, rsvd_fault; |
33770780 XG |
129 | int offset, write_fault, user_fault, fetch_fault; |
130 | ||
131 | write_fault = access & PFERR_WRITE_MASK; | |
132 | user_fault = access & PFERR_USER_MASK; | |
133 | fetch_fault = access & PFERR_FETCH_MASK; | |
6aa8b732 | 134 | |
07420171 AK |
135 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
136 | fetch_fault); | |
b3e4e63f | 137 | walk: |
f59c1d2d AK |
138 | present = true; |
139 | eperm = rsvd_fault = false; | |
1e301feb JR |
140 | walker->level = mmu->root_level; |
141 | pte = mmu->get_cr3(vcpu); | |
142 | ||
1b0973bd | 143 | #if PTTYPE == 64 |
1e301feb | 144 | if (walker->level == PT32E_ROOT_LEVEL) { |
d41d1895 | 145 | pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3); |
07420171 | 146 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
147 | if (!is_present_gpte(pte)) { |
148 | present = false; | |
149 | goto error; | |
150 | } | |
1b0973bd AK |
151 | --walker->level; |
152 | } | |
153 | #endif | |
a9058ecd | 154 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 155 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 156 | |
fe135d2c | 157 | pt_access = ACC_ALL; |
ac79c978 AK |
158 | |
159 | for (;;) { | |
6e2ca7d1 TY |
160 | gfn_t real_gfn; |
161 | unsigned long host_addr; | |
162 | ||
42bf3f0a | 163 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 164 | |
5fb07ddb | 165 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
166 | offset = index * sizeof(pt_element_t); |
167 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 168 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 169 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 170 | |
6e2ca7d1 TY |
171 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
172 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
781e0743 | 173 | if (unlikely(real_gfn == UNMAPPED_GVA)) { |
6e2ca7d1 TY |
174 | present = false; |
175 | break; | |
176 | } | |
177 | real_gfn = gpa_to_gfn(real_gfn); | |
178 | ||
179 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
781e0743 | 180 | if (unlikely(kvm_is_error_hva(host_addr))) { |
6e2ca7d1 TY |
181 | present = false; |
182 | break; | |
183 | } | |
184 | ||
185 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
fa3d315a | 186 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) { |
f59c1d2d AK |
187 | present = false; |
188 | break; | |
189 | } | |
a6085fba | 190 | |
07420171 | 191 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 192 | |
781e0743 | 193 | if (unlikely(!is_present_gpte(pte))) { |
f59c1d2d AK |
194 | present = false; |
195 | break; | |
196 | } | |
7993ba43 | 197 | |
781e0743 AK |
198 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
199 | walker->level))) { | |
f59c1d2d AK |
200 | rsvd_fault = true; |
201 | break; | |
202 | } | |
82725b20 | 203 | |
781e0743 AK |
204 | if (unlikely(write_fault && !is_writable_pte(pte) |
205 | && (user_fault || is_write_protection(vcpu)))) | |
206 | eperm = true; | |
7993ba43 | 207 | |
781e0743 | 208 | if (unlikely(user_fault && !(pte & PT_USER_MASK))) |
f59c1d2d | 209 | eperm = true; |
7993ba43 | 210 | |
73b1087e | 211 | #if PTTYPE == 64 |
781e0743 | 212 | if (unlikely(fetch_fault && (pte & PT64_NX_MASK))) |
f59c1d2d | 213 | eperm = true; |
73b1087e AK |
214 | #endif |
215 | ||
781e0743 AK |
216 | if (!eperm && !rsvd_fault |
217 | && unlikely(!(pte & PT_ACCESSED_MASK))) { | |
a78484c6 | 218 | int ret; |
07420171 AK |
219 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
220 | sizeof(pte)); | |
c8cfbb55 TY |
221 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, |
222 | pte, pte|PT_ACCESSED_MASK); | |
223 | if (unlikely(ret < 0)) { | |
a78484c6 RJ |
224 | present = false; |
225 | break; | |
226 | } else if (ret) | |
b3e4e63f | 227 | goto walk; |
a78484c6 | 228 | |
f3b8c964 | 229 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 230 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 231 | } |
815af8d4 | 232 | |
bedbe4ee | 233 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 234 | |
7819026e MT |
235 | walker->ptes[walker->level - 1] = pte; |
236 | ||
e04da980 JR |
237 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
238 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 239 | is_large_pte(pte) && |
e04da980 JR |
240 | (PTTYPE == 64 || is_pse(vcpu))) || |
241 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 242 | is_large_pte(pte) && |
1e301feb | 243 | mmu->root_level == PT64_ROOT_LEVEL)) { |
e04da980 | 244 | int lvl = walker->level; |
2329d46d JR |
245 | gpa_t real_gpa; |
246 | gfn_t gfn; | |
33770780 | 247 | u32 ac; |
e04da980 | 248 | |
2329d46d JR |
249 | gfn = gpte_to_gfn_lvl(pte, lvl); |
250 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
251 | |
252 | if (PTTYPE == 32 && | |
253 | walker->level == PT_DIRECTORY_LEVEL && | |
254 | is_cpuid_PSE36()) | |
2329d46d JR |
255 | gfn += pse36_gfn_delta(pte); |
256 | ||
33770780 | 257 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
258 | |
259 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 260 | ac); |
2329d46d JR |
261 | if (real_gpa == UNMAPPED_GVA) |
262 | return 0; | |
263 | ||
264 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 265 | |
ac79c978 | 266 | break; |
815af8d4 | 267 | } |
ac79c978 | 268 | |
fe135d2c | 269 | pt_access = pte_access; |
ac79c978 AK |
270 | --walker->level; |
271 | } | |
42bf3f0a | 272 | |
781e0743 | 273 | if (unlikely(!present || eperm || rsvd_fault)) |
f59c1d2d AK |
274 | goto error; |
275 | ||
781e0743 | 276 | if (write_fault && unlikely(!is_dirty_gpte(pte))) { |
a78484c6 | 277 | int ret; |
b3e4e63f | 278 | |
07420171 | 279 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
c8cfbb55 TY |
280 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, |
281 | pte, pte|PT_DIRTY_MASK); | |
282 | if (unlikely(ret < 0)) { | |
a78484c6 RJ |
283 | present = false; |
284 | goto error; | |
285 | } else if (ret) | |
b3e4e63f | 286 | goto walk; |
a78484c6 | 287 | |
f3b8c964 | 288 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 289 | pte |= PT_DIRTY_MASK; |
7819026e | 290 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
291 | } |
292 | ||
fe135d2c AK |
293 | walker->pt_access = pt_access; |
294 | walker->pte_access = pte_access; | |
295 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 296 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
297 | return 1; |
298 | ||
f59c1d2d | 299 | error: |
8c28d031 AK |
300 | walker->fault.vector = PF_VECTOR; |
301 | walker->fault.error_code_valid = true; | |
302 | walker->fault.error_code = 0; | |
f59c1d2d | 303 | if (present) |
8c28d031 | 304 | walker->fault.error_code |= PFERR_PRESENT_MASK; |
20bd40dc | 305 | |
8c28d031 | 306 | walker->fault.error_code |= write_fault | user_fault; |
20bd40dc | 307 | |
2d48a985 | 308 | if (fetch_fault && mmu->nx) |
8c28d031 | 309 | walker->fault.error_code |= PFERR_FETCH_MASK; |
82725b20 | 310 | if (rsvd_fault) |
8c28d031 | 311 | walker->fault.error_code |= PFERR_RSVD_MASK; |
8df25a32 | 312 | |
6389ee94 AK |
313 | walker->fault.address = addr; |
314 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 315 | |
8c28d031 | 316 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 317 | return 0; |
6aa8b732 AK |
318 | } |
319 | ||
1e301feb | 320 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 321 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
322 | { |
323 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 324 | access); |
1e301feb JR |
325 | } |
326 | ||
6539e738 JR |
327 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
328 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 329 | u32 access) |
6539e738 JR |
330 | { |
331 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 332 | addr, access); |
6539e738 JR |
333 | } |
334 | ||
407c61c6 XG |
335 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
336 | struct kvm_mmu_page *sp, u64 *spte, | |
337 | pt_element_t gpte) | |
338 | { | |
339 | u64 nonpresent = shadow_trap_nonpresent_pte; | |
340 | ||
341 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
342 | goto no_present; | |
343 | ||
344 | if (!is_present_gpte(gpte)) { | |
345 | if (!sp->unsync) | |
346 | nonpresent = shadow_notrap_nonpresent_pte; | |
347 | goto no_present; | |
348 | } | |
349 | ||
350 | if (!(gpte & PT_ACCESSED_MASK)) | |
351 | goto no_present; | |
352 | ||
353 | return false; | |
354 | ||
355 | no_present: | |
356 | drop_spte(vcpu->kvm, spte, nonpresent); | |
357 | return true; | |
358 | } | |
359 | ||
ac3cd03c | 360 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 361 | u64 *spte, const void *pte) |
0028425f AK |
362 | { |
363 | pt_element_t gpte; | |
41074d07 | 364 | unsigned pte_access; |
35149e21 | 365 | pfn_t pfn; |
0028425f | 366 | |
0028425f | 367 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 368 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 369 | return; |
407c61c6 | 370 | |
b8688d51 | 371 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 372 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
0f53b5b1 XG |
373 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
374 | if (is_error_pfn(pfn)) { | |
375 | kvm_release_pfn_clean(pfn); | |
d7824fff | 376 | return; |
0f53b5b1 | 377 | } |
0f53b5b1 | 378 | |
1403283a | 379 | /* |
0d2eb44f | 380 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
381 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
382 | */ | |
ac3cd03c | 383 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 384 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 385 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
386 | } |
387 | ||
39c8c672 AK |
388 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
389 | struct guest_walker *gw, int level) | |
390 | { | |
39c8c672 | 391 | pt_element_t curr_pte; |
189be38d XG |
392 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
393 | u64 mask; | |
394 | int r, index; | |
395 | ||
396 | if (level == PT_PAGE_TABLE_LEVEL) { | |
397 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
398 | base_gpa = pte_gpa & ~mask; | |
399 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
400 | ||
401 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
402 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
403 | curr_pte = gw->prefetch_ptes[index]; | |
404 | } else | |
405 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 406 | &curr_pte, sizeof(curr_pte)); |
189be38d | 407 | |
39c8c672 AK |
408 | return r || curr_pte != gw->ptes[level - 1]; |
409 | } | |
410 | ||
189be38d XG |
411 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
412 | u64 *sptep) | |
957ed9ef XG |
413 | { |
414 | struct kvm_mmu_page *sp; | |
189be38d | 415 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 416 | u64 *spte; |
189be38d | 417 | int i; |
957ed9ef XG |
418 | |
419 | sp = page_header(__pa(sptep)); | |
420 | ||
421 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
422 | return; | |
423 | ||
424 | if (sp->role.direct) | |
425 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
426 | ||
427 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
428 | spte = sp->spt + i; |
429 | ||
430 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
431 | pt_element_t gpte; | |
432 | unsigned pte_access; | |
433 | gfn_t gfn; | |
434 | pfn_t pfn; | |
435 | bool dirty; | |
436 | ||
437 | if (spte == sptep) | |
438 | continue; | |
439 | ||
440 | if (*spte != shadow_trap_nonpresent_pte) | |
441 | continue; | |
442 | ||
443 | gpte = gptep[i]; | |
444 | ||
407c61c6 | 445 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
446 | continue; |
447 | ||
448 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
449 | gfn = gpte_to_gfn(gpte); | |
450 | dirty = is_dirty_gpte(gpte); | |
451 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
452 | (pte_access & ACC_WRITE_MASK) && dirty); | |
453 | if (is_error_pfn(pfn)) { | |
454 | kvm_release_pfn_clean(pfn); | |
455 | break; | |
456 | } | |
457 | ||
458 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
459 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
460 | pfn, true, true); | |
461 | } | |
462 | } | |
463 | ||
6aa8b732 AK |
464 | /* |
465 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
466 | */ | |
e7a04c99 AK |
467 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
468 | struct guest_walker *gw, | |
7e4e4056 | 469 | int user_fault, int write_fault, int hlevel, |
fb67e14f XG |
470 | int *ptwrite, pfn_t pfn, bool map_writable, |
471 | bool prefault) | |
6aa8b732 | 472 | { |
abb9e0b8 | 473 | unsigned access = gw->pt_access; |
5991b332 | 474 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 475 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 476 | int top_level; |
84754cd8 | 477 | unsigned direct_access; |
24157aaf | 478 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 479 | |
43a3795a | 480 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 481 | return NULL; |
6aa8b732 | 482 | |
84754cd8 XG |
483 | direct_access = gw->pt_access & gw->pte_access; |
484 | if (!dirty) | |
485 | direct_access &= ~ACC_WRITE_MASK; | |
486 | ||
5991b332 AK |
487 | top_level = vcpu->arch.mmu.root_level; |
488 | if (top_level == PT32E_ROOT_LEVEL) | |
489 | top_level = PT32_ROOT_LEVEL; | |
490 | /* | |
491 | * Verify that the top-level gpte is still there. Since the page | |
492 | * is a root page, it is either write protected (and cannot be | |
493 | * changed from now on) or it is invalid (in which case, we don't | |
494 | * really care if it changes underneath us after this point). | |
495 | */ | |
496 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
497 | goto out_gpte_changed; | |
498 | ||
24157aaf AK |
499 | for (shadow_walk_init(&it, vcpu, addr); |
500 | shadow_walk_okay(&it) && it.level > gw->level; | |
501 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
502 | gfn_t table_gfn; |
503 | ||
24157aaf | 504 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 505 | |
5991b332 | 506 | sp = NULL; |
24157aaf AK |
507 | if (!is_shadow_present_pte(*it.sptep)) { |
508 | table_gfn = gw->table_gfn[it.level - 2]; | |
509 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
510 | false, access, it.sptep); | |
5991b332 | 511 | } |
0b3c9333 AK |
512 | |
513 | /* | |
514 | * Verify that the gpte in the page we've just write | |
515 | * protected is still there. | |
516 | */ | |
24157aaf | 517 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 518 | goto out_gpte_changed; |
abb9e0b8 | 519 | |
5991b332 | 520 | if (sp) |
24157aaf | 521 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 522 | } |
050e6499 | 523 | |
0b3c9333 | 524 | for (; |
24157aaf AK |
525 | shadow_walk_okay(&it) && it.level > hlevel; |
526 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
527 | gfn_t direct_gfn; |
528 | ||
24157aaf | 529 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 530 | |
24157aaf | 531 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 532 | |
24157aaf | 533 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
534 | continue; |
535 | ||
24157aaf | 536 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 537 | |
24157aaf AK |
538 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
539 | true, direct_access, it.sptep); | |
540 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
541 | } |
542 | ||
24157aaf AK |
543 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
544 | user_fault, write_fault, dirty, ptwrite, it.level, | |
fb67e14f | 545 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 546 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 547 | |
24157aaf | 548 | return it.sptep; |
0b3c9333 AK |
549 | |
550 | out_gpte_changed: | |
5991b332 | 551 | if (sp) |
24157aaf | 552 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
553 | kvm_release_pfn_clean(pfn); |
554 | return NULL; | |
6aa8b732 AK |
555 | } |
556 | ||
6aa8b732 AK |
557 | /* |
558 | * Page fault handler. There are several causes for a page fault: | |
559 | * - there is no shadow pte for the guest pte | |
560 | * - write access through a shadow pte marked read only so that we can set | |
561 | * the dirty bit | |
562 | * - write access to a shadow pte marked read only so we can update the page | |
563 | * dirty bitmap, when userspace requests it | |
564 | * - mmio access; in this case we will never install a present shadow pte | |
565 | * - normal guest page fault due to the guest pte marked not present, not | |
566 | * writable, or not executable | |
567 | * | |
e2dec939 AK |
568 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
569 | * a negative value on error. | |
6aa8b732 | 570 | */ |
56028d08 | 571 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 572 | bool prefault) |
6aa8b732 AK |
573 | { |
574 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
575 | int user_fault = error_code & PFERR_USER_MASK; |
576 | struct guest_walker walker; | |
d555c333 | 577 | u64 *sptep; |
cea0f0e7 | 578 | int write_pt = 0; |
e2dec939 | 579 | int r; |
35149e21 | 580 | pfn_t pfn; |
7e4e4056 | 581 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 582 | int force_pt_level; |
e930bffe | 583 | unsigned long mmu_seq; |
612819c3 | 584 | bool map_writable; |
6aa8b732 | 585 | |
b8688d51 | 586 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 587 | |
e2dec939 AK |
588 | r = mmu_topup_memory_caches(vcpu); |
589 | if (r) | |
590 | return r; | |
714b93da | 591 | |
6aa8b732 | 592 | /* |
a8b876b1 | 593 | * Look up the guest pte for the faulting address. |
6aa8b732 | 594 | */ |
33770780 | 595 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
596 | |
597 | /* | |
598 | * The page is not mapped by the guest. Let the guest handle it. | |
599 | */ | |
7993ba43 | 600 | if (!r) { |
b8688d51 | 601 | pgprintk("%s: guest page fault\n", __func__); |
fb67e14f XG |
602 | if (!prefault) { |
603 | inject_page_fault(vcpu, &walker.fault); | |
604 | /* reset fork detector */ | |
605 | vcpu->arch.last_pt_write_count = 0; | |
606 | } | |
6aa8b732 AK |
607 | return 0; |
608 | } | |
609 | ||
936a5fe6 AA |
610 | if (walker.level >= PT_DIRECTORY_LEVEL) |
611 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
612 | else | |
613 | force_pt_level = 1; | |
614 | if (!force_pt_level) { | |
7e4e4056 JR |
615 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
616 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 617 | } |
7e4e4056 | 618 | |
e930bffe | 619 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 620 | smp_rmb(); |
af585b92 | 621 | |
78b2c54a | 622 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 623 | &map_writable)) |
af585b92 | 624 | return 0; |
d7824fff | 625 | |
d196e343 | 626 | /* mmio */ |
bf998156 HY |
627 | if (is_error_pfn(pfn)) |
628 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 629 | |
aaee2c94 | 630 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
631 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
632 | goto out_unlock; | |
bc32ce21 | 633 | |
8b1fe17c | 634 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 635 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
636 | if (!force_pt_level) |
637 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 638 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
fb67e14f | 639 | level, &write_pt, pfn, map_writable, prefault); |
a24e8099 | 640 | (void)sptep; |
b8688d51 | 641 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 642 | sptep, *sptep, write_pt); |
cea0f0e7 | 643 | |
a25f7e1f | 644 | if (!write_pt) |
ad312c7c | 645 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 646 | |
1165f5fe | 647 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 648 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 649 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 650 | |
cea0f0e7 | 651 | return write_pt; |
e930bffe AA |
652 | |
653 | out_unlock: | |
654 | spin_unlock(&vcpu->kvm->mmu_lock); | |
655 | kvm_release_pfn_clean(pfn); | |
656 | return 0; | |
6aa8b732 AK |
657 | } |
658 | ||
a461930b | 659 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 660 | { |
a461930b | 661 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 662 | struct kvm_mmu_page *sp; |
08e850c6 | 663 | gpa_t pte_gpa = -1; |
a461930b AK |
664 | int level; |
665 | u64 *sptep; | |
4539b358 | 666 | int need_flush = 0; |
a461930b AK |
667 | |
668 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 669 | |
a461930b AK |
670 | for_each_shadow_entry(vcpu, gva, iterator) { |
671 | level = iterator.level; | |
672 | sptep = iterator.sptep; | |
ad218f85 | 673 | |
f78978aa | 674 | sp = page_header(__pa(sptep)); |
884a0ff0 | 675 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 676 | int offset, shift; |
08e850c6 | 677 | |
f78978aa XG |
678 | if (!sp->unsync) |
679 | break; | |
680 | ||
22c9b2d1 XG |
681 | shift = PAGE_SHIFT - |
682 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
683 | offset = sp->role.quadrant << shift; | |
684 | ||
685 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 686 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
687 | |
688 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
689 | if (is_large_pte(*sptep)) |
690 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
691 | drop_spte(vcpu->kvm, sptep, |
692 | shadow_trap_nonpresent_pte); | |
4539b358 | 693 | need_flush = 1; |
be38d276 AK |
694 | } else |
695 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 696 | break; |
87917239 | 697 | } |
a7052897 | 698 | |
f78978aa | 699 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
700 | break; |
701 | } | |
a7052897 | 702 | |
4539b358 AA |
703 | if (need_flush) |
704 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
705 | |
706 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
707 | ||
ad218f85 | 708 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
709 | |
710 | if (pte_gpa == -1) | |
711 | return; | |
712 | ||
713 | if (mmu_topup_memory_caches(vcpu)) | |
714 | return; | |
715 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
716 | } |
717 | ||
1871c602 | 718 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 719 | struct x86_exception *exception) |
6aa8b732 AK |
720 | { |
721 | struct guest_walker walker; | |
e119d117 AK |
722 | gpa_t gpa = UNMAPPED_GVA; |
723 | int r; | |
6aa8b732 | 724 | |
33770780 | 725 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 726 | |
e119d117 | 727 | if (r) { |
1755fbcc | 728 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 729 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
730 | } else if (exception) |
731 | *exception = walker.fault; | |
6aa8b732 AK |
732 | |
733 | return gpa; | |
734 | } | |
735 | ||
6539e738 | 736 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
737 | u32 access, |
738 | struct x86_exception *exception) | |
6539e738 JR |
739 | { |
740 | struct guest_walker walker; | |
741 | gpa_t gpa = UNMAPPED_GVA; | |
742 | int r; | |
743 | ||
33770780 | 744 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
745 | |
746 | if (r) { | |
747 | gpa = gfn_to_gpa(walker.gfn); | |
748 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
749 | } else if (exception) |
750 | *exception = walker.fault; | |
6539e738 JR |
751 | |
752 | return gpa; | |
753 | } | |
754 | ||
c7addb90 AK |
755 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
756 | struct kvm_mmu_page *sp) | |
757 | { | |
eab9f71f AK |
758 | int i, j, offset, r; |
759 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
760 | gpa_t pte_gpa; | |
c7addb90 | 761 | |
f6e2c02b | 762 | if (sp->role.direct |
e5a4c8ca | 763 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
764 | nonpaging_prefetch_page(vcpu, sp); |
765 | return; | |
766 | } | |
767 | ||
eab9f71f AK |
768 | pte_gpa = gfn_to_gpa(sp->gfn); |
769 | if (PTTYPE == 32) { | |
e5a4c8ca | 770 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
771 | pte_gpa += offset * sizeof(pt_element_t); |
772 | } | |
7ec54588 | 773 | |
eab9f71f AK |
774 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
775 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
776 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
777 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 778 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
779 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
780 | else | |
781 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 782 | } |
c7addb90 AK |
783 | } |
784 | ||
e8bc217a MT |
785 | /* |
786 | * Using the cached information from sp->gfns is safe because: | |
787 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
788 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
789 | * |
790 | * Note: | |
791 | * We should flush all tlbs if spte is dropped even though guest is | |
792 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
793 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
794 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
795 | * freed pages. | |
796 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 797 | */ |
a4a8e6f7 | 798 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a MT |
799 | { |
800 | int i, offset, nr_present; | |
9bdbba13 | 801 | bool host_writable; |
51fb60d8 | 802 | gpa_t first_pte_gpa; |
e8bc217a MT |
803 | |
804 | offset = nr_present = 0; | |
805 | ||
2032a93d LJ |
806 | /* direct kvm_mmu_page can not be unsync. */ |
807 | BUG_ON(sp->role.direct); | |
808 | ||
e8bc217a MT |
809 | if (PTTYPE == 32) |
810 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
811 | ||
51fb60d8 GJ |
812 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
813 | ||
e8bc217a MT |
814 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
815 | unsigned pte_access; | |
816 | pt_element_t gpte; | |
817 | gpa_t pte_gpa; | |
f55c3f41 | 818 | gfn_t gfn; |
e8bc217a MT |
819 | |
820 | if (!is_shadow_present_pte(sp->spt[i])) | |
821 | continue; | |
822 | ||
51fb60d8 | 823 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
824 | |
825 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
826 | sizeof(pt_element_t))) | |
827 | return -EINVAL; | |
828 | ||
f55c3f41 | 829 | gfn = gpte_to_gfn(gpte); |
407c61c6 XG |
830 | |
831 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { | |
a4ee1ca4 | 832 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
833 | continue; |
834 | } | |
835 | ||
836 | if (gfn != sp->gfns[i]) { | |
837 | drop_spte(vcpu->kvm, &sp->spt[i], | |
838 | shadow_trap_nonpresent_pte); | |
a4ee1ca4 | 839 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
840 | continue; |
841 | } | |
842 | ||
843 | nr_present++; | |
844 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
f8e453b0 XG |
845 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
846 | ||
e8bc217a | 847 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 848 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 849 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 850 | host_writable); |
e8bc217a MT |
851 | } |
852 | ||
853 | return !nr_present; | |
854 | } | |
855 | ||
6aa8b732 AK |
856 | #undef pt_element_t |
857 | #undef guest_walker | |
858 | #undef FNAME | |
859 | #undef PT_BASE_ADDR_MASK | |
860 | #undef PT_INDEX | |
e04da980 JR |
861 | #undef PT_LVL_ADDR_MASK |
862 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 863 | #undef PT_LEVEL_BITS |
cea0f0e7 | 864 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 865 | #undef gpte_to_gfn |
e04da980 | 866 | #undef gpte_to_gfn_lvl |
b3e4e63f | 867 | #undef CMPXCHG |