]>
Commit | Line | Data |
---|---|---|
20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f5132b01 | 2 | /* |
c7a7062f | 3 | * Kernel-based Virtual Machine -- Performance Monitoring Unit support |
f5132b01 | 4 | * |
25462f7f | 5 | * Copyright 2015 Red Hat, Inc. and/or its affiliates. |
f5132b01 GN |
6 | * |
7 | * Authors: | |
8 | * Avi Kivity <avi@redhat.com> | |
9 | * Gleb Natapov <gleb@redhat.com> | |
25462f7f | 10 | * Wei Huang <wei@redhat.com> |
f5132b01 GN |
11 | */ |
12 | ||
13 | #include <linux/types.h> | |
14 | #include <linux/kvm_host.h> | |
15 | #include <linux/perf_event.h> | |
d27aa7f1 | 16 | #include <asm/perf_event.h> |
f5132b01 GN |
17 | #include "x86.h" |
18 | #include "cpuid.h" | |
19 | #include "lapic.h" | |
474a5bb9 | 20 | #include "pmu.h" |
f5132b01 | 21 | |
25462f7f WH |
22 | /* NOTE: |
23 | * - Each perf counter is defined as "struct kvm_pmc"; | |
24 | * - There are two types of perf counters: general purpose (gp) and fixed. | |
25 | * gp counters are stored in gp_counters[] and fixed counters are stored | |
26 | * in fixed_counters[] respectively. Both of them are part of "struct | |
27 | * kvm_pmu"; | |
28 | * - pmu.c understands the difference between gp counters and fixed counters. | |
29 | * However AMD doesn't support fixed-counters; | |
30 | * - There are three types of index to access perf counters (PMC): | |
31 | * 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD | |
32 | * has MSR_K7_PERFCTRn. | |
33 | * 2. MSR Index (named idx): This normally is used by RDPMC instruction. | |
34 | * For instance AMD RDPMC instruction uses 0000_0003h in ECX to access | |
35 | * C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except | |
36 | * that it also supports fixed counters. idx can be used to as index to | |
37 | * gp and fixed counters. | |
38 | * 3. Global PMC Index (named pmc): pmc is an index specific to PMU | |
39 | * code. Each pmc, stored in kvm_pmc.idx field, is unique across | |
40 | * all perf counters (both gp and fixed). The mapping relationship | |
41 | * between pmc and perf counters is as the following: | |
42 | * * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters | |
43 | * [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed | |
44 | * * AMD: [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters | |
45 | */ | |
f5132b01 | 46 | |
c6702c9d | 47 | static void kvm_pmi_trigger_fn(struct irq_work *irq_work) |
f5132b01 | 48 | { |
212dba12 WH |
49 | struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work); |
50 | struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu); | |
f5132b01 | 51 | |
c6702c9d | 52 | kvm_pmu_deliver_pmi(vcpu); |
f5132b01 GN |
53 | } |
54 | ||
55 | static void kvm_perf_overflow(struct perf_event *perf_event, | |
56 | struct perf_sample_data *data, | |
57 | struct pt_regs *regs) | |
58 | { | |
59 | struct kvm_pmc *pmc = perf_event->overflow_handler_context; | |
212dba12 | 60 | struct kvm_pmu *pmu = pmc_to_pmu(pmc); |
e84cfe4c WH |
61 | |
62 | if (!test_and_set_bit(pmc->idx, | |
63 | (unsigned long *)&pmu->reprogram_pmi)) { | |
671bd993 NA |
64 | __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); |
65 | kvm_make_request(KVM_REQ_PMU, pmc->vcpu); | |
66 | } | |
f5132b01 GN |
67 | } |
68 | ||
69 | static void kvm_perf_overflow_intr(struct perf_event *perf_event, | |
e84cfe4c WH |
70 | struct perf_sample_data *data, |
71 | struct pt_regs *regs) | |
f5132b01 GN |
72 | { |
73 | struct kvm_pmc *pmc = perf_event->overflow_handler_context; | |
212dba12 | 74 | struct kvm_pmu *pmu = pmc_to_pmu(pmc); |
e84cfe4c WH |
75 | |
76 | if (!test_and_set_bit(pmc->idx, | |
77 | (unsigned long *)&pmu->reprogram_pmi)) { | |
671bd993 | 78 | __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); |
f5132b01 | 79 | kvm_make_request(KVM_REQ_PMU, pmc->vcpu); |
e84cfe4c | 80 | |
f5132b01 GN |
81 | /* |
82 | * Inject PMI. If vcpu was in a guest mode during NMI PMI | |
83 | * can be ejected on a guest mode re-entry. Otherwise we can't | |
84 | * be sure that vcpu wasn't executing hlt instruction at the | |
e84cfe4c | 85 | * time of vmexit and is not going to re-enter guest mode until |
f5132b01 GN |
86 | * woken up. So we should wake it, but this is impossible from |
87 | * NMI context. Do it from irq work instead. | |
88 | */ | |
89 | if (!kvm_is_in_guest()) | |
212dba12 | 90 | irq_work_queue(&pmc_to_pmu(pmc)->irq_work); |
f5132b01 GN |
91 | else |
92 | kvm_make_request(KVM_REQ_PMI, pmc->vcpu); | |
93 | } | |
94 | } | |
95 | ||
c6702c9d | 96 | static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, |
e84cfe4c WH |
97 | unsigned config, bool exclude_user, |
98 | bool exclude_kernel, bool intr, | |
99 | bool in_tx, bool in_tx_cp) | |
f5132b01 GN |
100 | { |
101 | struct perf_event *event; | |
102 | struct perf_event_attr attr = { | |
103 | .type = type, | |
104 | .size = sizeof(attr), | |
105 | .pinned = true, | |
106 | .exclude_idle = true, | |
107 | .exclude_host = 1, | |
108 | .exclude_user = exclude_user, | |
109 | .exclude_kernel = exclude_kernel, | |
110 | .config = config, | |
111 | }; | |
e84cfe4c | 112 | |
bba82fd7 RC |
113 | attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc); |
114 | ||
103af0a9 AK |
115 | if (in_tx) |
116 | attr.config |= HSW_IN_TX; | |
bba82fd7 RC |
117 | if (in_tx_cp) { |
118 | /* | |
119 | * HSW_IN_TX_CHECKPOINTED is not supported with nonzero | |
120 | * period. Just clear the sample period so at least | |
121 | * allocating the counter doesn't fail. | |
122 | */ | |
123 | attr.sample_period = 0; | |
103af0a9 | 124 | attr.config |= HSW_IN_TX_CHECKPOINTED; |
bba82fd7 | 125 | } |
f5132b01 GN |
126 | |
127 | event = perf_event_create_kernel_counter(&attr, -1, current, | |
128 | intr ? kvm_perf_overflow_intr : | |
129 | kvm_perf_overflow, pmc); | |
130 | if (IS_ERR(event)) { | |
e84cfe4c WH |
131 | printk_once("kvm_pmu: event creation failed %ld\n", |
132 | PTR_ERR(event)); | |
f5132b01 GN |
133 | return; |
134 | } | |
135 | ||
136 | pmc->perf_event = event; | |
212dba12 | 137 | clear_bit(pmc->idx, (unsigned long*)&pmc_to_pmu(pmc)->reprogram_pmi); |
f5132b01 GN |
138 | } |
139 | ||
25462f7f | 140 | void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel) |
f5132b01 GN |
141 | { |
142 | unsigned config, type = PERF_TYPE_RAW; | |
143 | u8 event_select, unit_mask; | |
144 | ||
a7b9d2cc GN |
145 | if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) |
146 | printk_once("kvm pmu: pin control bit is ignored\n"); | |
147 | ||
f5132b01 GN |
148 | pmc->eventsel = eventsel; |
149 | ||
c6702c9d | 150 | pmc_stop_counter(pmc); |
f5132b01 | 151 | |
c6702c9d | 152 | if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc)) |
f5132b01 GN |
153 | return; |
154 | ||
155 | event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT; | |
156 | unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; | |
157 | ||
fac33683 | 158 | if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE | |
e84cfe4c WH |
159 | ARCH_PERFMON_EVENTSEL_INV | |
160 | ARCH_PERFMON_EVENTSEL_CMASK | | |
161 | HSW_IN_TX | | |
162 | HSW_IN_TX_CHECKPOINTED))) { | |
25462f7f WH |
163 | config = kvm_x86_ops->pmu_ops->find_arch_event(pmc_to_pmu(pmc), |
164 | event_select, | |
165 | unit_mask); | |
f5132b01 GN |
166 | if (config != PERF_COUNT_HW_MAX) |
167 | type = PERF_TYPE_HARDWARE; | |
168 | } | |
169 | ||
170 | if (type == PERF_TYPE_RAW) | |
171 | config = eventsel & X86_RAW_EVENT_MASK; | |
172 | ||
c6702c9d | 173 | pmc_reprogram_counter(pmc, type, config, |
e84cfe4c WH |
174 | !(eventsel & ARCH_PERFMON_EVENTSEL_USR), |
175 | !(eventsel & ARCH_PERFMON_EVENTSEL_OS), | |
176 | eventsel & ARCH_PERFMON_EVENTSEL_INT, | |
177 | (eventsel & HSW_IN_TX), | |
178 | (eventsel & HSW_IN_TX_CHECKPOINTED)); | |
f5132b01 | 179 | } |
25462f7f | 180 | EXPORT_SYMBOL_GPL(reprogram_gp_counter); |
f5132b01 | 181 | |
25462f7f | 182 | void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx) |
f5132b01 | 183 | { |
e84cfe4c WH |
184 | unsigned en_field = ctrl & 0x3; |
185 | bool pmi = ctrl & 0x8; | |
f5132b01 | 186 | |
c6702c9d | 187 | pmc_stop_counter(pmc); |
f5132b01 | 188 | |
e84cfe4c | 189 | if (!en_field || !pmc_is_enabled(pmc)) |
f5132b01 GN |
190 | return; |
191 | ||
c6702c9d | 192 | pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE, |
25462f7f | 193 | kvm_x86_ops->pmu_ops->find_fixed_event(idx), |
e84cfe4c WH |
194 | !(en_field & 0x2), /* exclude user */ |
195 | !(en_field & 0x1), /* exclude kernel */ | |
196 | pmi, false, false); | |
f5132b01 | 197 | } |
25462f7f | 198 | EXPORT_SYMBOL_GPL(reprogram_fixed_counter); |
f5132b01 | 199 | |
25462f7f | 200 | void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx) |
f5132b01 | 201 | { |
25462f7f | 202 | struct kvm_pmc *pmc = kvm_x86_ops->pmu_ops->pmc_idx_to_pmc(pmu, pmc_idx); |
f5132b01 GN |
203 | |
204 | if (!pmc) | |
205 | return; | |
206 | ||
207 | if (pmc_is_gp(pmc)) | |
208 | reprogram_gp_counter(pmc, pmc->eventsel); | |
209 | else { | |
e84cfe4c WH |
210 | int idx = pmc_idx - INTEL_PMC_IDX_FIXED; |
211 | u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx); | |
212 | ||
213 | reprogram_fixed_counter(pmc, ctrl, idx); | |
f5132b01 GN |
214 | } |
215 | } | |
25462f7f | 216 | EXPORT_SYMBOL_GPL(reprogram_counter); |
f5132b01 | 217 | |
e5af058a WH |
218 | void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) |
219 | { | |
220 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); | |
221 | u64 bitmask; | |
222 | int bit; | |
223 | ||
224 | bitmask = pmu->reprogram_pmi; | |
225 | ||
226 | for_each_set_bit(bit, (unsigned long *)&bitmask, X86_PMC_IDX_MAX) { | |
25462f7f | 227 | struct kvm_pmc *pmc = kvm_x86_ops->pmu_ops->pmc_idx_to_pmc(pmu, bit); |
e5af058a WH |
228 | |
229 | if (unlikely(!pmc || !pmc->perf_event)) { | |
230 | clear_bit(bit, (unsigned long *)&pmu->reprogram_pmi); | |
231 | continue; | |
232 | } | |
233 | ||
234 | reprogram_counter(pmu, bit); | |
235 | } | |
236 | } | |
237 | ||
238 | /* check if idx is a valid index to access PMU */ | |
239 | int kvm_pmu_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx) | |
240 | { | |
25462f7f | 241 | return kvm_x86_ops->pmu_ops->is_valid_msr_idx(vcpu, idx); |
41aac14a WH |
242 | } |
243 | ||
2d7921c4 AM |
244 | bool is_vmware_backdoor_pmc(u32 pmc_idx) |
245 | { | |
246 | switch (pmc_idx) { | |
247 | case VMWARE_BACKDOOR_PMC_HOST_TSC: | |
248 | case VMWARE_BACKDOOR_PMC_REAL_TIME: | |
249 | case VMWARE_BACKDOOR_PMC_APPARENT_TIME: | |
250 | return true; | |
251 | } | |
252 | return false; | |
253 | } | |
254 | ||
255 | static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data) | |
256 | { | |
257 | u64 ctr_val; | |
258 | ||
259 | switch (idx) { | |
260 | case VMWARE_BACKDOOR_PMC_HOST_TSC: | |
261 | ctr_val = rdtsc(); | |
262 | break; | |
263 | case VMWARE_BACKDOOR_PMC_REAL_TIME: | |
264 | ctr_val = ktime_get_boot_ns(); | |
265 | break; | |
266 | case VMWARE_BACKDOOR_PMC_APPARENT_TIME: | |
267 | ctr_val = ktime_get_boot_ns() + | |
268 | vcpu->kvm->arch.kvmclock_offset; | |
269 | break; | |
270 | default: | |
271 | return 1; | |
272 | } | |
273 | ||
274 | *data = ctr_val; | |
275 | return 0; | |
276 | } | |
277 | ||
41aac14a WH |
278 | int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data) |
279 | { | |
280 | bool fast_mode = idx & (1u << 31); | |
672ff6cf | 281 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
41aac14a | 282 | struct kvm_pmc *pmc; |
0e6f467e | 283 | u64 mask = fast_mode ? ~0u : ~0ull; |
41aac14a | 284 | |
672ff6cf LA |
285 | if (!pmu->version) |
286 | return 1; | |
287 | ||
2d7921c4 AM |
288 | if (is_vmware_backdoor_pmc(idx)) |
289 | return kvm_pmu_rdpmc_vmware(vcpu, idx, data); | |
290 | ||
0e6f467e | 291 | pmc = kvm_x86_ops->pmu_ops->msr_idx_to_pmc(vcpu, idx, &mask); |
41aac14a WH |
292 | if (!pmc) |
293 | return 1; | |
294 | ||
0e6f467e | 295 | *data = pmc_read_counter(pmc) & mask; |
e5af058a WH |
296 | return 0; |
297 | } | |
298 | ||
299 | void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu) | |
300 | { | |
bce87cce | 301 | if (lapic_in_kernel(vcpu)) |
e5af058a WH |
302 | kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC); |
303 | } | |
304 | ||
c6702c9d | 305 | bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) |
f5132b01 | 306 | { |
25462f7f | 307 | return kvm_x86_ops->pmu_ops->is_valid_msr(vcpu, msr); |
f5132b01 GN |
308 | } |
309 | ||
25462f7f | 310 | int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data) |
f5132b01 | 311 | { |
25462f7f | 312 | return kvm_x86_ops->pmu_ops->get_msr(vcpu, msr, data); |
f5132b01 GN |
313 | } |
314 | ||
afd80d85 | 315 | int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
f5132b01 | 316 | { |
25462f7f | 317 | return kvm_x86_ops->pmu_ops->set_msr(vcpu, msr_info); |
f5132b01 GN |
318 | } |
319 | ||
e84cfe4c WH |
320 | /* refresh PMU settings. This function generally is called when underlying |
321 | * settings are changed (such as changes of PMU CPUID by guest VMs), which | |
322 | * should rarely happen. | |
323 | */ | |
c6702c9d | 324 | void kvm_pmu_refresh(struct kvm_vcpu *vcpu) |
f5132b01 | 325 | { |
25462f7f | 326 | kvm_x86_ops->pmu_ops->refresh(vcpu); |
f5132b01 GN |
327 | } |
328 | ||
f5132b01 GN |
329 | void kvm_pmu_reset(struct kvm_vcpu *vcpu) |
330 | { | |
212dba12 | 331 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
f5132b01 GN |
332 | |
333 | irq_work_sync(&pmu->irq_work); | |
25462f7f | 334 | kvm_x86_ops->pmu_ops->reset(vcpu); |
f5132b01 GN |
335 | } |
336 | ||
e5af058a | 337 | void kvm_pmu_init(struct kvm_vcpu *vcpu) |
f5132b01 | 338 | { |
212dba12 | 339 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
f5132b01 | 340 | |
e5af058a | 341 | memset(pmu, 0, sizeof(*pmu)); |
25462f7f | 342 | kvm_x86_ops->pmu_ops->init(vcpu); |
e5af058a WH |
343 | init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn); |
344 | kvm_pmu_refresh(vcpu); | |
345 | } | |
346 | ||
347 | void kvm_pmu_destroy(struct kvm_vcpu *vcpu) | |
348 | { | |
349 | kvm_pmu_reset(vcpu); | |
f5132b01 | 350 | } |