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selftests: kvm: fix smm test on SVM
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / svm / svm.c
CommitLineData
44a95dae
SS		 1#define pr_fmt(fmt) "SVM: " fmt
2
edf88417
AK		 3#include <linux/kvm_host.h>
4
85f455f7 5#include "irq.h"
1d737c8a 6#include "mmu.h"
5fdbf976 7#include "kvm_cache_regs.h"
fe4c7b19 8#include "x86.h"
66f7b72e 9#include "cpuid.h"
25462f7f 10#include "pmu.h"
e495606d 11
6aa8b732 12#include <linux/module.h>
ae759544 13#include <linux/mod_devicetable.h>
9d8f549d 14#include <linux/kernel.h>
6aa8b732
AK		 15#include <linux/vmalloc.h>
16#include <linux/highmem.h>
ef0f6496 17#include <linux/amd-iommu.h>
e8edc6e0 18#include <linux/sched.h>
af658dca 19#include <linux/trace_events.h>
5a0e3ad6 20#include <linux/slab.h>
5881f737 21#include <linux/hashtable.h>
c207aee4 22#include <linux/frame.h>
e9df0942 23#include <linux/psp-sev.h>
1654efcb 24#include <linux/file.h>
89c50580
BS		 25#include <linux/pagemap.h>
26#include <linux/swap.h>
33af3a7e 27#include <linux/rwsem.h>
6aa8b732 28
8221c137 29#include <asm/apic.h>
1018faa6 30#include <asm/perf_event.h>
67ec6607 31#include <asm/tlbflush.h>
e495606d 32#include <asm/desc.h>
facb0139 33#include <asm/debugreg.h>
631bc487 34#include <asm/kvm_para.h>
411b44ba 35#include <asm/irq_remapping.h>
1c164cb3 36#include <asm/mce.h>
28a27752 37#include <asm/spec-ctrl.h>
ba5bade4 38#include <asm/cpu_device_id.h>
6aa8b732 39
63d1142f 40#include <asm/virtext.h>
229456fc 41#include "trace.h"
63d1142f 42
883b0a91
JR		 43#include "svm.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
575b255c 50#ifdef MODULE
ae759544 51static const struct x86_cpu_id svm_cpu_id[] = {
320debe5 52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
ae759544
JT		 53 {}
54};
55MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
575b255c 56#endif
ae759544 57
6aa8b732
AK		 58#define IOPM_ALLOC_ORDER 2
59#define MSRPM_ALLOC_ORDER 1
60
6aa8b732
AK		 61#define SEG_TYPE_LDT 2
62#define SEG_TYPE_BUSY_TSS16 3
63
6bc31bdc
AP		 64#define SVM_FEATURE_LBRV (1 << 1)
65#define SVM_FEATURE_SVML (1 << 2)
ddce97aa
AP		 66#define SVM_FEATURE_TSC_RATE (1 << 4)
67#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68#define SVM_FEATURE_FLUSH_ASID (1 << 6)
69#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
6bc31bdc 70#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 71
24e09cbf
JR		 72#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73
fbc0db76 74#define TSC_RATIO_RSVD 0xffffff0000000000ULL
92a1f12d
JR		 75#define TSC_RATIO_MIN 0x0000000000000001ULL
76#define TSC_RATIO_MAX 0x000000ffffffffffULL
fbc0db76 77
67ec6607
JR		 78static bool erratum_383_found __read_mostly;
79
883b0a91 80u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
323c3d80 81
2b036c6b
BO		 82/*
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
85 */
86static uint64_t osvw_len = 4, osvw_status;
87
fbc0db76
JR		 88static DEFINE_PER_CPU(u64, current_tsc_ratio);
89#define TSC_RATIO_DEFAULT 0x0100000000ULL
90
09941fbb 91static const struct svm_direct_access_msrs {
ac72a9b7
JR		 92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94} direct_access_msrs[] = {
8c06585d 95 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
97#ifdef CONFIG_X86_64
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
104#endif
b2ac58f9 105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
15d45071 106 { .index = MSR_IA32_PRED_CMD, .always = false },
ac72a9b7
JR		 107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
883b0a91 116bool npt_enabled = true;
709ddebf 117#else
883b0a91 118bool npt_enabled;
709ddebf 119#endif
6c7dac72 120
8566ac8b
BM		 121/*
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
131 *
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
148 * count only mode.
149 */
150
151static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152module_param(pause_filter_thresh, ushort, 0444);
153
154static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155module_param(pause_filter_count, ushort, 0444);
156
157/* Default doubles per-vcpu window every exit. */
158static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159module_param(pause_filter_count_grow, ushort, 0444);
160
161/* Default resets per-vcpu window every exit to pause_filter_count. */
162static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163module_param(pause_filter_count_shrink, ushort, 0444);
164
165/* Default is to compute the maximum so we can never overflow. */
166static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167module_param(pause_filter_count_max, ushort, 0444);
168
e2358851
DB		 169/* allow nested paging (virtualized MMU) for all guests */
170static int npt = true;
6c7dac72 171module_param(npt, int, S_IRUGO);
e3da3acd 172
e2358851
DB		 173/* allow nested virtualization in KVM/SVM */
174static int nested = true;
236de055
AG		 175module_param(nested, int, S_IRUGO);
176
d647eb63
PB		 177/* enable/disable Next RIP Save */
178static int nrips = true;
179module_param(nrips, int, 0444);
180
89c8a498
JN		 181/* enable/disable Virtual VMLOAD VMSAVE */
182static int vls = true;
183module_param(vls, int, 0444);
184
640bd6e5
JN		 185/* enable/disable Virtual GIF */
186static int vgif = true;
187module_param(vgif, int, 0444);
5ea11f2b 188
e9df0942
BS		 189/* enable/disable SEV support */
190static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191module_param(sev, int, 0444);
192
6f2f8453
PB		 193static bool __read_mostly dump_invalid_vmcb = 0;
194module_param(dump_invalid_vmcb, bool, 0644);
195
7607b717
BS		 196static u8 rsm_ins_bytes[] = "\x0f\xaa";
197
a5c3832d 198static void svm_complete_interrupts(struct vcpu_svm *svm);
44a95dae 199
4866d5e3 200static unsigned long iopm_base;
6aa8b732
AK		 201
202struct kvm_ldttss_desc {
203 u16 limit0;
204 u16 base0;
e0231715
JR		 205 unsigned base1:8, type:5, dpl:2, p:1;
206 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 207 u32 base3;
208 u32 zero1;
209} __attribute__((packed));
210
eaf78265 211DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
6aa8b732 212
09941fbb 213static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
6aa8b732 214
9d8f549d 215#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 216#define MSRS_RANGE_SIZE 2048
217#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
218
883b0a91 219u32 svm_msrpm_offset(u32 msr)
455716fa
JR		 220{
221 u32 offset;
222 int i;
223
224 for (i = 0; i < NUM_MSR_MAPS; i++) {
225 if (msr < msrpm_ranges[i] ||
226 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
227 continue;
228
229 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
230 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
231
232 /* Now we have the u8 offset - but need the u32 offset */
233 return offset / 4;
234 }
235
236 /* MSR not in any range */
237 return MSR_INVALID;
238}
239
6aa8b732
AK		 240#define MAX_INST_SIZE 15
241
6aa8b732
AK		 242static inline void clgi(void)
243{
ac5ffda2 244 asm volatile (__ex("clgi"));
6aa8b732
AK		 245}
246
247static inline void stgi(void)
248{
ac5ffda2 249 asm volatile (__ex("stgi"));
6aa8b732
AK		 250}
251
252static inline void invlpga(unsigned long addr, u32 asid)
253{
ac5ffda2 254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
6aa8b732
AK		 255}
256
855feb67 257static int get_npt_level(struct kvm_vcpu *vcpu)
4b16184c
JR		 258{
259#ifdef CONFIG_X86_64
2a7266a8 260 return PT64_ROOT_4LEVEL;
4b16184c
JR		 261#else
262 return PT32E_ROOT_LEVEL;
263#endif
264}
265
883b0a91 266void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
6aa8b732 267{
c513f484 268 struct vcpu_svm *svm = to_svm(vcpu);
6dc696d4 269 vcpu->arch.efer = efer;
9167ab79
PB		 270
271 if (!npt_enabled) {
272 /* Shadow paging assumes NX to be available. */
273 efer |= EFER_NX;
274
275 if (!(efer & EFER_LMA))
276 efer &= ~EFER_LME;
277 }
6aa8b732 278
c513f484
PB		 279 if (!(efer & EFER_SVME)) {
280 svm_leave_nested(svm);
281 svm_set_gif(svm, true);
282 }
283
284 svm->vmcb->save.efer = efer | EFER_SVME;
285 mark_dirty(svm->vmcb, VMCB_CR);
6aa8b732
AK		 286}
287
6aa8b732
AK		 288static int is_external_interrupt(u32 info)
289{
290 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
291 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
292}
293
37ccdcbe 294static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 295{
296 struct vcpu_svm *svm = to_svm(vcpu);
297 u32 ret = 0;
298
299 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
37ccdcbe
PB		 300 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
301 return ret;
2809f5d2
GC		 302}
303
304static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
305{
306 struct vcpu_svm *svm = to_svm(vcpu);
307
308 if (mask == 0)
309 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
310 else
311 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
312
313}
314
f8ea7c60 315static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732 316{
a2fa3e9f
GH		 317 struct vcpu_svm *svm = to_svm(vcpu);
318
d647eb63 319 if (nrips && svm->vmcb->control.next_rip != 0) {
d2922422 320 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
6bc31bdc 321 svm->next_rip = svm->vmcb->control.next_rip;
f104765b 322 }
6bc31bdc 323
1957aa63
SC		 324 if (!svm->next_rip) {
325 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
326 return 0;
327 } else {
1957aa63
SC		 328 kvm_rip_write(vcpu, svm->next_rip);
329 }
2809f5d2 330 svm_set_interrupt_shadow(vcpu, 0);
f8ea7c60 331
60fc3d02 332 return 1;
6aa8b732
AK		 333}
334
cfcd20e5 335static void svm_queue_exception(struct kvm_vcpu *vcpu)
116a4752
JK		 336{
337 struct vcpu_svm *svm = to_svm(vcpu);
cfcd20e5
WL		 338 unsigned nr = vcpu->arch.exception.nr;
339 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 340 u32 error_code = vcpu->arch.exception.error_code;
116a4752 341
da998b46
JM		 342 kvm_deliver_exception_payload(&svm->vcpu);
343
d647eb63 344 if (nr == BP_VECTOR && !nrips) {
66b7138f
JK		 345 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
346
347 /*
348 * For guest debugging where we have to reinject #BP if some
349 * INT3 is guest-owned:
350 * Emulate nRIP by moving RIP forward. Will fail if injection
351 * raises a fault that is not intercepted. Still better than
352 * failing in all cases.
353 */
f8ea7c60 354 (void)skip_emulated_instruction(&svm->vcpu);
66b7138f
JK		 355 rip = kvm_rip_read(&svm->vcpu);
356 svm->int3_rip = rip + svm->vmcb->save.cs.base;
357 svm->int3_injected = rip - old_rip;
358 }
359
116a4752
JK		 360 svm->vmcb->control.event_inj = nr
361 | SVM_EVTINJ_VALID
362 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
363 | SVM_EVTINJ_TYPE_EXEPT;
364 svm->vmcb->control.event_inj_err = error_code;
365}
366
67ec6607
JR		 367static void svm_init_erratum_383(void)
368{
369 u32 low, high;
370 int err;
371 u64 val;
372
e6ee94d5 373 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
67ec6607
JR		 374 return;
375
376 /* Use _safe variants to not break nested virtualization */
377 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
378 if (err)
379 return;
380
381 val |= (1ULL << 47);
382
383 low = lower_32_bits(val);
384 high = upper_32_bits(val);
385
386 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
387
388 erratum_383_found = true;
389}
390
2b036c6b
BO		 391static void svm_init_osvw(struct kvm_vcpu *vcpu)
392{
393 /*
394 * Guests should see errata 400 and 415 as fixed (assuming that
395 * HLT and IO instructions are intercepted).
396 */
397 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
398 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
399
400 /*
401 * By increasing VCPU's osvw.length to 3 we are telling the guest that
402 * all osvw.status bits inside that length, including bit 0 (which is
403 * reserved for erratum 298), are valid. However, if host processor's
404 * osvw_len is 0 then osvw_status[0] carries no information. We need to
405 * be conservative here and therefore we tell the guest that erratum 298
406 * is present (because we really don't know).
407 */
408 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
409 vcpu->arch.osvw.status |= 1;
410}
411
6aa8b732
AK		 412static int has_svm(void)
413{
63d1142f 414 const char *msg;
6aa8b732 415
63d1142f 416 if (!cpu_has_svm(&msg)) {
ff81ff10 417 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 418 return 0;
419 }
420
6aa8b732
AK		 421 return 1;
422}
423
13a34e06 424static void svm_hardware_disable(void)
6aa8b732 425{
fbc0db76
JR		 426 /* Make sure we clean up behind us */
427 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
428 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
429
2c8dceeb 430 cpu_svm_disable();
1018faa6
JR		 431
432 amd_pmu_disable_virt();
6aa8b732
AK		 433}
434
13a34e06 435static int svm_hardware_enable(void)
6aa8b732
AK		 436{
437
0fe1e009 438 struct svm_cpu_data *sd;
6aa8b732 439 uint64_t efer;
6aa8b732
AK		 440 struct desc_struct *gdt;
441 int me = raw_smp_processor_id();
442
10474ae8
AG		 443 rdmsrl(MSR_EFER, efer);
444 if (efer & EFER_SVME)
445 return -EBUSY;
446
6aa8b732 447 if (!has_svm()) {
1f5b77f5 448 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
10474ae8 449 return -EINVAL;
6aa8b732 450 }
0fe1e009 451 sd = per_cpu(svm_data, me);
0fe1e009 452 if (!sd) {
1f5b77f5 453 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
10474ae8 454 return -EINVAL;
6aa8b732
AK		 455 }
456
0fe1e009
TH		 457 sd->asid_generation = 1;
458 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
459 sd->next_asid = sd->max_asid + 1;
ed3cd233 460 sd->min_asid = max_sev_asid + 1;
6aa8b732 461
45fc8757 462 gdt = get_current_gdt_rw();
0fe1e009 463 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 464
9962d032 465 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 466
d0316554 467 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 468
fbc0db76
JR		 469 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
470 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
89cbc767 471 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
fbc0db76
JR		 472 }
473
2b036c6b
BO		 474
475 /*
476 * Get OSVW bits.
477 *
478 * Note that it is possible to have a system with mixed processor
479 * revisions and therefore different OSVW bits. If bits are not the same
480 * on different processors then choose the worst case (i.e. if erratum
481 * is present on one processor and not on another then assume that the
482 * erratum is present everywhere).
483 */
484 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
485 uint64_t len, status = 0;
486 int err;
487
488 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
489 if (!err)
490 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
491 &err);
492
493 if (err)
494 osvw_status = osvw_len = 0;
495 else {
496 if (len < osvw_len)
497 osvw_len = len;
498 osvw_status |= status;
499 osvw_status &= (1ULL << osvw_len) - 1;
500 }
501 } else
502 osvw_status = osvw_len = 0;
503
67ec6607
JR		 504 svm_init_erratum_383();
505
1018faa6
JR		 506 amd_pmu_enable_virt();
507
10474ae8 508 return 0;
6aa8b732
AK		 509}
510
0da1db75
JR		 511static void svm_cpu_uninit(int cpu)
512{
0fe1e009 513 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 514
0fe1e009 515 if (!sd)
0da1db75
JR		 516 return;
517
518 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
70cd94e6 519 kfree(sd->sev_vmcbs);
0fe1e009
TH		 520 __free_page(sd->save_area);
521 kfree(sd);
0da1db75
JR		 522}
523
6aa8b732
AK		 524static int svm_cpu_init(int cpu)
525{
0fe1e009 526 struct svm_cpu_data *sd;
6aa8b732 527
0fe1e009
TH		 528 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
529 if (!sd)
6aa8b732 530 return -ENOMEM;
0fe1e009 531 sd->cpu = cpu;
70cd94e6 532 sd->save_area = alloc_page(GFP_KERNEL);
0fe1e009 533 if (!sd->save_area)
d80b64ff 534 goto free_cpu_data;
6aa8b732 535
70cd94e6 536 if (svm_sev_enabled()) {
6da2ec56
KC		 537 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
538 sizeof(void *),
539 GFP_KERNEL);
70cd94e6 540 if (!sd->sev_vmcbs)
d80b64ff 541 goto free_save_area;
70cd94e6
BS		 542 }
543
0fe1e009 544 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 545
546 return 0;
547
d80b64ff
ML		 548free_save_area:
549 __free_page(sd->save_area);
550free_cpu_data:
0fe1e009 551 kfree(sd);
d80b64ff 552 return -ENOMEM;
6aa8b732
AK		 553
554}
555
ac72a9b7
JR		 556static bool valid_msr_intercept(u32 index)
557{
558 int i;
559
560 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
561 if (direct_access_msrs[i].index == index)
562 return true;
563
564 return false;
565}
566
b2ac58f9
KA		 567static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
568{
569 u8 bit_write;
570 unsigned long tmp;
571 u32 offset;
572 u32 *msrpm;
573
574 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
575 to_svm(vcpu)->msrpm;
576
577 offset = svm_msrpm_offset(msr);
578 bit_write = 2 * (msr & 0x0f) + 1;
579 tmp = msrpm[offset];
580
581 BUG_ON(offset == MSR_INVALID);
582
583 return !!test_bit(bit_write, &tmp);
584}
585
bfc733a7
RR		 586static void set_msr_interception(u32 *msrpm, unsigned msr,
587 int read, int write)
6aa8b732 588{
455716fa
JR		 589 u8 bit_read, bit_write;
590 unsigned long tmp;
591 u32 offset;
6aa8b732 592
ac72a9b7
JR		 593 /*
594 * If this warning triggers extend the direct_access_msrs list at the
595 * beginning of the file
596 */
597 WARN_ON(!valid_msr_intercept(msr));
598
455716fa
JR		 599 offset = svm_msrpm_offset(msr);
600 bit_read = 2 * (msr & 0x0f);
601 bit_write = 2 * (msr & 0x0f) + 1;
602 tmp = msrpm[offset];
603
604 BUG_ON(offset == MSR_INVALID);
605
606 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
607 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
608
609 msrpm[offset] = tmp;
6aa8b732
AK		 610}
611
f65c229c 612static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 613{
614 int i;
615
f65c229c
JR		 616 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
617
ac72a9b7
JR		 618 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
619 if (!direct_access_msrs[i].always)
620 continue;
621
622 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
623 }
f65c229c
JR		 624}
625
323c3d80
JR		 626static void add_msr_offset(u32 offset)
627{
628 int i;
629
630 for (i = 0; i < MSRPM_OFFSETS; ++i) {
631
632 /* Offset already in list? */
633 if (msrpm_offsets[i] == offset)
bfc733a7 634 return;
323c3d80
JR		 635
636 /* Slot used by another offset? */
637 if (msrpm_offsets[i] != MSR_INVALID)
638 continue;
639
640 /* Add offset to list */
641 msrpm_offsets[i] = offset;
642
643 return;
6aa8b732 644 }
323c3d80
JR		 645
646 /*
647 * If this BUG triggers the msrpm_offsets table has an overflow. Just
648 * increase MSRPM_OFFSETS in this case.
649 */
bfc733a7 650 BUG();
6aa8b732
AK		 651}
652
323c3d80 653static void init_msrpm_offsets(void)
f65c229c 654{
323c3d80 655 int i;
f65c229c 656
323c3d80
JR		 657 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
658
659 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
660 u32 offset;
661
662 offset = svm_msrpm_offset(direct_access_msrs[i].index);
663 BUG_ON(offset == MSR_INVALID);
664
665 add_msr_offset(offset);
666 }
f65c229c
JR		 667}
668
24e09cbf
JR		 669static void svm_enable_lbrv(struct vcpu_svm *svm)
670{
671 u32 *msrpm = svm->msrpm;
672
0dc92119 673 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
24e09cbf
JR		 674 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
675 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
676 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
677 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
678}
679
680static void svm_disable_lbrv(struct vcpu_svm *svm)
681{
682 u32 *msrpm = svm->msrpm;
683
0dc92119 684 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
24e09cbf
JR		 685 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
686 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
687 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
688 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
689}
690
883b0a91 691void disable_nmi_singlestep(struct vcpu_svm *svm)
4aebd0e9
LP		 692{
693 svm->nmi_singlestep = false;
640bd6e5 694
ab2f4d73
LP		 695 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
696 /* Clear our flags if they were not set by the guest */
697 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
698 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
699 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
700 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
701 }
4aebd0e9
LP		 702}
703
8566ac8b
BM		 704static void grow_ple_window(struct kvm_vcpu *vcpu)
705{
706 struct vcpu_svm *svm = to_svm(vcpu);
707 struct vmcb_control_area *control = &svm->vmcb->control;
708 int old = control->pause_filter_count;
709
710 control->pause_filter_count = __grow_ple_window(old,
711 pause_filter_count,
712 pause_filter_count_grow,
713 pause_filter_count_max);
714
4f75bcc3 715 if (control->pause_filter_count != old) {
8566ac8b 716 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 717 trace_kvm_ple_window_update(vcpu->vcpu_id,
718 control->pause_filter_count, old);
719 }
8566ac8b
BM		 720}
721
722static void shrink_ple_window(struct kvm_vcpu *vcpu)
723{
724 struct vcpu_svm *svm = to_svm(vcpu);
725 struct vmcb_control_area *control = &svm->vmcb->control;
726 int old = control->pause_filter_count;
727
728 control->pause_filter_count =
729 __shrink_ple_window(old,
730 pause_filter_count,
731 pause_filter_count_shrink,
732 pause_filter_count);
4f75bcc3 733 if (control->pause_filter_count != old) {
8566ac8b 734 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 735 trace_kvm_ple_window_update(vcpu->vcpu_id,
736 control->pause_filter_count, old);
737 }
8566ac8b
BM		 738}
739
52918ed5
TL		 740/*
741 * The default MMIO mask is a single bit (excluding the present bit),
742 * which could conflict with the memory encryption bit. Check for
743 * memory encryption support and override the default MMIO mask if
744 * memory encryption is enabled.
745 */
746static __init void svm_adjust_mmio_mask(void)
747{
748 unsigned int enc_bit, mask_bit;
749 u64 msr, mask;
750
751 /* If there is no memory encryption support, use existing mask */
752 if (cpuid_eax(0x80000000) < 0x8000001f)
753 return;
754
755 /* If memory encryption is not enabled, use existing mask */
756 rdmsrl(MSR_K8_SYSCFG, msr);
757 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
758 return;
759
760 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
761 mask_bit = boot_cpu_data.x86_phys_bits;
762
763 /* Increment the mask bit if it is the same as the encryption bit */
764 if (enc_bit == mask_bit)
765 mask_bit++;
766
767 /*
768 * If the mask bit location is below 52, then some bits above the
769 * physical addressing limit will always be reserved, so use the
770 * rsvd_bits() function to generate the mask. This mask, along with
771 * the present bit, will be used to generate a page fault with
772 * PFER.RSV = 1.
773 *
774 * If the mask bit location is 52 (or above), then clear the mask.
775 */
776 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
777
e7581cac 778 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
52918ed5
TL		 779}
780
dd58f3c9
LR		 781static void svm_hardware_teardown(void)
782{
783 int cpu;
784
eaf78265
JR		 785 if (svm_sev_enabled())
786 sev_hardware_teardown();
dd58f3c9
LR		 787
788 for_each_possible_cpu(cpu)
789 svm_cpu_uninit(cpu);
790
791 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
792 iopm_base = 0;
793}
794
9b58b985
SC		 795static __init void svm_set_cpu_caps(void)
796{
797 kvm_set_cpu_caps();
798
408e9a31
PB		 799 supported_xss = 0;
800
a50718cc
SC		 801 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
802 if (nested) {
9b58b985
SC		 803 kvm_cpu_cap_set(X86_FEATURE_SVM);
804
4eb87460 805 if (nrips)
a50718cc
SC		 806 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
807
808 if (npt_enabled)
809 kvm_cpu_cap_set(X86_FEATURE_NPT);
810 }
811
93c380e7
SC		 812 /* CPUID 0x80000008 */
813 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
814 boot_cpu_has(X86_FEATURE_AMD_SSBD))
815 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
9b58b985
SC		 816}
817
6aa8b732
AK		 818static __init int svm_hardware_setup(void)
819{
820 int cpu;
821 struct page *iopm_pages;
f65c229c 822 void *iopm_va;
6aa8b732
AK		 823 int r;
824
6aa8b732
AK		 825 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
826
827 if (!iopm_pages)
828 return -ENOMEM;
c8681339
AL		 829
830 iopm_va = page_address(iopm_pages);
831 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 832 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
833
323c3d80
JR		 834 init_msrpm_offsets();
835
cfc48181
SC		 836 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
837
50a37eb4
JR		 838 if (boot_cpu_has(X86_FEATURE_NX))
839 kvm_enable_efer_bits(EFER_NX);
840
1b2fd70c
AG		 841 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
842 kvm_enable_efer_bits(EFER_FFXSR);
843
92a1f12d 844 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
92a1f12d 845 kvm_has_tsc_control = true;
bc9b961b
HZ		 846 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
847 kvm_tsc_scaling_ratio_frac_bits = 32;
92a1f12d
JR		 848 }
849
8566ac8b
BM		 850 /* Check for pause filtering support */
851 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
852 pause_filter_count = 0;
853 pause_filter_thresh = 0;
854 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
855 pause_filter_thresh = 0;
856 }
857
236de055
AG		 858 if (nested) {
859 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 860 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 861 }
862
e9df0942
BS		 863 if (sev) {
864 if (boot_cpu_has(X86_FEATURE_SEV) &&
865 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
866 r = sev_hardware_setup();
867 if (r)
868 sev = false;
869 } else {
870 sev = false;
871 }
872 }
873
52918ed5
TL		 874 svm_adjust_mmio_mask();
875
3230bb47 876 for_each_possible_cpu(cpu) {
6aa8b732
AK		 877 r = svm_cpu_init(cpu);
878 if (r)
f65c229c 879 goto err;
6aa8b732 880 }
33bd6a0b 881
2a6b20b8 882 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 883 npt_enabled = false;
884
213e0e1f 885 if (npt_enabled && !npt)
6c7dac72 886 npt_enabled = false;
6c7dac72 887
3bae0459 888 kvm_configure_mmu(npt_enabled, PG_LEVEL_1G);
213e0e1f 889 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
e3da3acd 890
d647eb63
PB		 891 if (nrips) {
892 if (!boot_cpu_has(X86_FEATURE_NRIPS))
893 nrips = false;
894 }
895
5b8abf1f
SS		 896 if (avic) {
897 if (!npt_enabled ||
898 !boot_cpu_has(X86_FEATURE_AVIC) ||
5881f737 899 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
5b8abf1f 900 avic = false;
5881f737 901 } else {
5b8abf1f 902 pr_info("AVIC enabled\n");
5881f737 903
5881f737
SS		 904 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
905 }
5b8abf1f 906 }
44a95dae 907
89c8a498
JN		 908 if (vls) {
909 if (!npt_enabled ||
5442c269 910 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
89c8a498
JN		 911 !IS_ENABLED(CONFIG_X86_64)) {
912 vls = false;
913 } else {
914 pr_info("Virtual VMLOAD VMSAVE supported\n");
915 }
916 }
917
640bd6e5
JN		 918 if (vgif) {
919 if (!boot_cpu_has(X86_FEATURE_VGIF))
920 vgif = false;
921 else
922 pr_info("Virtual GIF supported\n");
923 }
924
9b58b985 925 svm_set_cpu_caps();
66a6950f 926
6aa8b732
AK		 927 return 0;
928
f65c229c 929err:
dd58f3c9 930 svm_hardware_teardown();
6aa8b732
AK		 931 return r;
932}
933
6aa8b732
AK		 934static void init_seg(struct vmcb_seg *seg)
935{
936 seg->selector = 0;
937 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 938 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 939 seg->limit = 0xffff;
940 seg->base = 0;
941}
942
943static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
944{
945 seg->selector = 0;
946 seg->attrib = SVM_SELECTOR_P_MASK | type;
947 seg->limit = 0xffff;
948 seg->base = 0;
949}
950
326e7425 951static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
f4e1b3c8
ZA		 952{
953 struct vcpu_svm *svm = to_svm(vcpu);
954 u64 g_tsc_offset = 0;
955
2030753d 956 if (is_guest_mode(vcpu)) {
e79f245d 957 /* Write L1's TSC offset. */
f4e1b3c8
ZA		 958 g_tsc_offset = svm->vmcb->control.tsc_offset -
959 svm->nested.hsave->control.tsc_offset;
960 svm->nested.hsave->control.tsc_offset = offset;
45c3af97
PB		 961 }
962
963 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
964 svm->vmcb->control.tsc_offset - g_tsc_offset,
965 offset);
f4e1b3c8
ZA		 966
967 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23
JR		 968
969 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
326e7425 970 return svm->vmcb->control.tsc_offset;
f4e1b3c8
ZA		 971}
972
5690891b 973static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 974{
e6101a96
JR		 975 struct vmcb_control_area *control = &svm->vmcb->control;
976 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 977
4ee546b4 978 svm->vcpu.arch.hflags = 0;
bff78274 979
4ee546b4
RJ		 980 set_cr_intercept(svm, INTERCEPT_CR0_READ);
981 set_cr_intercept(svm, INTERCEPT_CR3_READ);
982 set_cr_intercept(svm, INTERCEPT_CR4_READ);
983 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
984 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
985 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
3bbf3565
SS		 986 if (!kvm_vcpu_apicv_active(&svm->vcpu))
987 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 988
5315c716 989 set_dr_intercepts(svm);
6aa8b732 990
18c918c5
JR		 991 set_exception_intercept(svm, PF_VECTOR);
992 set_exception_intercept(svm, UD_VECTOR);
993 set_exception_intercept(svm, MC_VECTOR);
54a20552 994 set_exception_intercept(svm, AC_VECTOR);
cbdb967a 995 set_exception_intercept(svm, DB_VECTOR);
9718420e
LA		 996 /*
997 * Guest access to VMware backdoor ports could legitimately
998 * trigger #GP because of TSS I/O permission bitmap.
999 * We intercept those #GP and allow access to them anyway
1000 * as VMware does.
1001 */
1002 if (enable_vmware_backdoor)
1003 set_exception_intercept(svm, GP_VECTOR);
6aa8b732 1004
8a05a1b8
JR		 1005 set_intercept(svm, INTERCEPT_INTR);
1006 set_intercept(svm, INTERCEPT_NMI);
1007 set_intercept(svm, INTERCEPT_SMI);
1008 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
332b56e4 1009 set_intercept(svm, INTERCEPT_RDPMC);
8a05a1b8
JR		 1010 set_intercept(svm, INTERCEPT_CPUID);
1011 set_intercept(svm, INTERCEPT_INVD);
8a05a1b8
JR		 1012 set_intercept(svm, INTERCEPT_INVLPG);
1013 set_intercept(svm, INTERCEPT_INVLPGA);
1014 set_intercept(svm, INTERCEPT_IOIO_PROT);
1015 set_intercept(svm, INTERCEPT_MSR_PROT);
1016 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1017 set_intercept(svm, INTERCEPT_SHUTDOWN);
1018 set_intercept(svm, INTERCEPT_VMRUN);
1019 set_intercept(svm, INTERCEPT_VMMCALL);
1020 set_intercept(svm, INTERCEPT_VMLOAD);
1021 set_intercept(svm, INTERCEPT_VMSAVE);
1022 set_intercept(svm, INTERCEPT_STGI);
1023 set_intercept(svm, INTERCEPT_CLGI);
1024 set_intercept(svm, INTERCEPT_SKINIT);
1025 set_intercept(svm, INTERCEPT_WBINVD);
81dd35d4 1026 set_intercept(svm, INTERCEPT_XSETBV);
0cb8410b 1027 set_intercept(svm, INTERCEPT_RDPRU);
7607b717 1028 set_intercept(svm, INTERCEPT_RSM);
6aa8b732 1029
4d5422ce 1030 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
668fffa3
MT		 1031 set_intercept(svm, INTERCEPT_MONITOR);
1032 set_intercept(svm, INTERCEPT_MWAIT);
1033 }
1034
caa057a2
WL		 1035 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1036 set_intercept(svm, INTERCEPT_HLT);
1037
d0ec49d4
TL		 1038 control->iopm_base_pa = __sme_set(iopm_base);
1039 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
6aa8b732
AK		 1040 control->int_ctl = V_INTR_MASKING_MASK;
1041
1042 init_seg(&save->es);
1043 init_seg(&save->ss);
1044 init_seg(&save->ds);
1045 init_seg(&save->fs);
1046 init_seg(&save->gs);
1047
1048 save->cs.selector = 0xf000;
04b66839 1049 save->cs.base = 0xffff0000;
6aa8b732
AK		 1050 /* Executable/Readable Code Segment */
1051 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1052 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1053 save->cs.limit = 0xffff;
6aa8b732
AK		 1054
1055 save->gdtr.limit = 0xffff;
1056 save->idtr.limit = 0xffff;
1057
1058 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1059 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1060
5690891b 1061 svm_set_efer(&svm->vcpu, 0);
d77c26fc 1062 save->dr6 = 0xffff0ff0;
f6e78475 1063 kvm_set_rflags(&svm->vcpu, 2);
6aa8b732 1064 save->rip = 0x0000fff0;
5fdbf976 1065 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 1066
e0231715 1067 /*
18fa000a 1068 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
d28bc9dd 1069 * It also updates the guest-visible cr0 value.
6aa8b732 1070 */
79a8059d 1071 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
ebae871a 1072 kvm_mmu_reset_context(&svm->vcpu);
18fa000a 1073
66aee91a 1074 save->cr4 = X86_CR4_PAE;
6aa8b732 1075 /* rdx = ?? */
709ddebf
JR		 1076
1077 if (npt_enabled) {
1078 /* Setup VMCB for Nested Paging */
cea3a19b 1079 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
8a05a1b8 1080 clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 1081 clr_exception_intercept(svm, PF_VECTOR);
4ee546b4
RJ		 1082 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1083 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
74545705 1084 save->g_pat = svm->vcpu.arch.pat;
709ddebf
JR		 1085 save->cr3 = 0;
1086 save->cr4 = 0;
1087 }
f40f6a45 1088 svm->asid_generation = 0;
1371d904 1089
e6aa9abd 1090 svm->nested.vmcb = 0;
2af9194d
JR		 1091 svm->vcpu.arch.hflags = 0;
1092
8566ac8b
BM		 1093 if (pause_filter_count) {
1094 control->pause_filter_count = pause_filter_count;
1095 if (pause_filter_thresh)
1096 control->pause_filter_thresh = pause_filter_thresh;
8a05a1b8 1097 set_intercept(svm, INTERCEPT_PAUSE);
8566ac8b
BM		 1098 } else {
1099 clr_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1100 }
1101
67034bb9 1102 if (kvm_vcpu_apicv_active(&svm->vcpu))
44a95dae
SS		 1103 avic_init_vmcb(svm);
1104
89c8a498
JN		 1105 /*
1106 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1107 * in VMCB and clear intercepts to avoid #VMEXIT.
1108 */
1109 if (vls) {
1110 clr_intercept(svm, INTERCEPT_VMLOAD);
1111 clr_intercept(svm, INTERCEPT_VMSAVE);
1112 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1113 }
1114
640bd6e5
JN		 1115 if (vgif) {
1116 clr_intercept(svm, INTERCEPT_STGI);
1117 clr_intercept(svm, INTERCEPT_CLGI);
1118 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1119 }
1120
35c6f649 1121 if (sev_guest(svm->vcpu.kvm)) {
1654efcb 1122 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
35c6f649
BS		 1123 clr_exception_intercept(svm, UD_VECTOR);
1124 }
1654efcb 1125
8d28fec4
RJ		 1126 mark_all_dirty(svm->vmcb);
1127
2af9194d 1128 enable_gif(svm);
44a95dae
SS		 1129
1130}
1131
d28bc9dd 1132static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
04d2cc77
AK		 1133{
1134 struct vcpu_svm *svm = to_svm(vcpu);
66f7b72e
JS		 1135 u32 dummy;
1136 u32 eax = 1;
04d2cc77 1137
b2ac58f9 1138 svm->spec_ctrl = 0;
ccbcd267 1139 svm->virt_spec_ctrl = 0;
b2ac58f9 1140
d28bc9dd
NA		 1141 if (!init_event) {
1142 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1143 MSR_IA32_APICBASE_ENABLE;
1144 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1145 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1146 }
5690891b 1147 init_vmcb(svm);
70433389 1148
f91af517 1149 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
de3cd117 1150 kvm_rdx_write(vcpu, eax);
44a95dae
SS		 1151
1152 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1153 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
04d2cc77
AK		 1154}
1155
987b2594 1156static int svm_create_vcpu(struct kvm_vcpu *vcpu)
6aa8b732 1157{
a2fa3e9f 1158 struct vcpu_svm *svm;
6aa8b732 1159 struct page *page;
f65c229c 1160 struct page *msrpm_pages;
b286d5d8 1161 struct page *hsave_page;
3d6368ef 1162 struct page *nested_msrpm_pages;
fb3f0f51 1163 int err;
6aa8b732 1164
a9dd6f09
SC		 1165 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1166 svm = to_svm(vcpu);
fb3f0f51 1167
b7af4043 1168 err = -ENOMEM;
1ec69647 1169 page = alloc_page(GFP_KERNEL_ACCOUNT);
b7af4043 1170 if (!page)
987b2594 1171 goto out;
6aa8b732 1172
1ec69647 1173 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
f65c229c 1174 if (!msrpm_pages)
b7af4043 1175 goto free_page1;
3d6368ef 1176
1ec69647 1177 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
3d6368ef 1178 if (!nested_msrpm_pages)
b7af4043 1179 goto free_page2;
f65c229c 1180
1ec69647 1181 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
b286d5d8 1182 if (!hsave_page)
b7af4043
TY		 1183 goto free_page3;
1184
dfa20099
SS		 1185 err = avic_init_vcpu(svm);
1186 if (err)
1187 goto free_page4;
44a95dae 1188
8221c137
SS		 1189 /* We initialize this flag to true to make sure that the is_running
1190 * bit would be set the first time the vcpu is loaded.
1191 */
6c3e4422
SS		 1192 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1193 svm->avic_is_running = true;
8221c137 1194
e6aa9abd 1195 svm->nested.hsave = page_address(hsave_page);
b286d5d8 1196
b7af4043
TY		 1197 svm->msrpm = page_address(msrpm_pages);
1198 svm_vcpu_init_msrpm(svm->msrpm);
1199
e6aa9abd 1200 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 1201 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 1202
a2fa3e9f
GH		 1203 svm->vmcb = page_address(page);
1204 clear_page(svm->vmcb);
d0ec49d4 1205 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
a2fa3e9f 1206 svm->asid_generation = 0;
5690891b 1207 init_vmcb(svm);
6aa8b732 1208
7f27179a 1209 svm_init_osvw(vcpu);
bab0c318 1210 vcpu->arch.microcode_version = 0x01000065;
2b036c6b 1211
a9dd6f09 1212 return 0;
36241b8c 1213
44a95dae
SS		 1214free_page4:
1215 __free_page(hsave_page);
b7af4043
TY		 1216free_page3:
1217 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1218free_page2:
1219 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1220free_page1:
1221 __free_page(page);
987b2594 1222out:
a9dd6f09 1223 return err;
6aa8b732
AK		 1224}
1225
fd65d314
JM		 1226static void svm_clear_current_vmcb(struct vmcb *vmcb)
1227{
1228 int i;
1229
1230 for_each_online_cpu(i)
1231 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1232}
1233
6aa8b732
AK		 1234static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1235{
a2fa3e9f
GH		 1236 struct vcpu_svm *svm = to_svm(vcpu);
1237
fd65d314
JM		 1238 /*
1239 * The vmcb page can be recycled, causing a false negative in
1240 * svm_vcpu_load(). So, ensure that no logical CPU has this
1241 * vmcb page recorded as its current vmcb.
1242 */
1243 svm_clear_current_vmcb(svm->vmcb);
1244
d0ec49d4 1245 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
f65c229c 1246 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1247 __free_page(virt_to_page(svm->nested.hsave));
1248 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
6aa8b732
AK		 1249}
1250
15ad7146 1251static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1252{
a2fa3e9f 1253 struct vcpu_svm *svm = to_svm(vcpu);
15d45071 1254 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
15ad7146 1255 int i;
0cc5064d 1256
0cc5064d 1257 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1258 svm->asid_generation = 0;
8d28fec4 1259 mark_all_dirty(svm->vmcb);
0cc5064d 1260 }
94dfbdb3 1261
82ca2d10
AK		 1262#ifdef CONFIG_X86_64
1263 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1264#endif
dacccfdd
AK		 1265 savesegment(fs, svm->host.fs);
1266 savesegment(gs, svm->host.gs);
1267 svm->host.ldt = kvm_read_ldt();
1268
94dfbdb3 1269 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1270 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
fbc0db76 1271
ad721883
HZ		 1272 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1273 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1274 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1275 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1276 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1277 }
fbc0db76 1278 }
46896c73
PB		 1279 /* This assumes that the kernel never uses MSR_TSC_AUX */
1280 if (static_cpu_has(X86_FEATURE_RDTSCP))
1281 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
8221c137 1282
15d45071
AR		 1283 if (sd->current_vmcb != svm->vmcb) {
1284 sd->current_vmcb = svm->vmcb;
1285 indirect_branch_prediction_barrier();
1286 }
8221c137 1287 avic_vcpu_load(vcpu, cpu);
6aa8b732
AK		 1288}
1289
1290static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1291{
a2fa3e9f 1292 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1293 int i;
1294
8221c137
SS		 1295 avic_vcpu_put(vcpu);
1296
e1beb1d3 1297 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1298 kvm_load_ldt(svm->host.ldt);
1299#ifdef CONFIG_X86_64
1300 loadsegment(fs, svm->host.fs);
296f781a 1301 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
893a5ab6 1302 load_gs_index(svm->host.gs);
dacccfdd 1303#else
831ca609 1304#ifdef CONFIG_X86_32_LAZY_GS
dacccfdd 1305 loadsegment(gs, svm->host.gs);
831ca609 1306#endif
dacccfdd 1307#endif
94dfbdb3 1308 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1309 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1310}
1311
6aa8b732
AK		 1312static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1313{
9b611747
LP		 1314 struct vcpu_svm *svm = to_svm(vcpu);
1315 unsigned long rflags = svm->vmcb->save.rflags;
1316
1317 if (svm->nmi_singlestep) {
1318 /* Hide our flags if they were not set by the guest */
1319 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1320 rflags &= ~X86_EFLAGS_TF;
1321 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1322 rflags &= ~X86_EFLAGS_RF;
1323 }
1324 return rflags;
6aa8b732
AK		 1325}
1326
1327static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1328{
9b611747
LP		 1329 if (to_svm(vcpu)->nmi_singlestep)
1330 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1331
ae9fedc7 1332 /*
bb3541f1 1333 * Any change of EFLAGS.VM is accompanied by a reload of SS
ae9fedc7
PB		 1334 * (caused by either a task switch or an inter-privilege IRET),
1335 * so we do not need to update the CPL here.
1336 */
a2fa3e9f 1337 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1338}
1339
6de4f3ad
AK		 1340static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1341{
1342 switch (reg) {
1343 case VCPU_EXREG_PDPTR:
1344 BUG_ON(!npt_enabled);
9f8fe504 1345 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6de4f3ad
AK		 1346 break;
1347 default:
34059c25 1348 WARN_ON_ONCE(1);
6de4f3ad
AK		 1349 }
1350}
1351
e14b7786 1352static void svm_set_vintr(struct vcpu_svm *svm)
64b5bd27
PB		 1353{
1354 struct vmcb_control_area *control;
1355
1356 /* The following fields are ignored when AVIC is enabled */
1357 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
e14b7786 1358 set_intercept(svm, INTERCEPT_VINTR);
64b5bd27
PB		 1359
1360 /*
1361 * This is just a dummy VINTR to actually cause a vmexit to happen.
1362 * Actual injection of virtual interrupts happens through EVENTINJ.
1363 */
1364 control = &svm->vmcb->control;
1365 control->int_vector = 0x0;
1366 control->int_ctl &= ~V_INTR_PRIO_MASK;
1367 control->int_ctl |= V_IRQ_MASK |
1368 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1369 mark_dirty(svm->vmcb, VMCB_INTR);
1370}
1371
f0b85051
AG		 1372static void svm_clear_vintr(struct vcpu_svm *svm)
1373{
d8e4e58f 1374 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
8a05a1b8 1375 clr_intercept(svm, INTERCEPT_VINTR);
64b5bd27 1376
d8e4e58f
PB		 1377 /* Drop int_ctl fields related to VINTR injection. */
1378 svm->vmcb->control.int_ctl &= mask;
1379 if (is_guest_mode(&svm->vcpu)) {
1380 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1381 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1382 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1383 }
1384
64b5bd27 1385 mark_dirty(svm->vmcb, VMCB_INTR);
f0b85051
AG		 1386}
1387
6aa8b732
AK		 1388static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1389{
a2fa3e9f 1390 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1391
1392 switch (seg) {
1393 case VCPU_SREG_CS: return &save->cs;
1394 case VCPU_SREG_DS: return &save->ds;
1395 case VCPU_SREG_ES: return &save->es;
1396 case VCPU_SREG_FS: return &save->fs;
1397 case VCPU_SREG_GS: return &save->gs;
1398 case VCPU_SREG_SS: return &save->ss;
1399 case VCPU_SREG_TR: return &save->tr;
1400 case VCPU_SREG_LDTR: return &save->ldtr;
1401 }
1402 BUG();
8b6d44c7 1403 return NULL;
6aa8b732
AK		 1404}
1405
1406static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1407{
1408 struct vmcb_seg *s = svm_seg(vcpu, seg);
1409
1410 return s->base;
1411}
1412
1413static void svm_get_segment(struct kvm_vcpu *vcpu,
1414 struct kvm_segment *var, int seg)
1415{
1416 struct vmcb_seg *s = svm_seg(vcpu, seg);
1417
1418 var->base = s->base;
1419 var->limit = s->limit;
1420 var->selector = s->selector;
1421 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1422 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1423 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1424 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1425 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1426 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1427 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
80112c89
JM		 1428
1429 /*
1430 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1431 * However, the SVM spec states that the G bit is not observed by the
1432 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1433 * So let's synthesize a legal G bit for all segments, this helps
1434 * running KVM nested. It also helps cross-vendor migration, because
1435 * Intel's vmentry has a check on the 'G' bit.
1436 */
1437 var->g = s->limit > 0xfffff;
25022acc 1438
e0231715
JR		 1439 /*
1440 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1441 * for cross vendor migration purposes by "not present"
1442 */
8eae9570 1443 var->unusable = !var->present;
19bca6ab 1444
1fbdc7a5 1445 switch (seg) {
1fbdc7a5
AP		 1446 case VCPU_SREG_TR:
1447 /*
1448 * Work around a bug where the busy flag in the tr selector
1449 * isn't exposed
1450 */
c0d09828 1451 var->type |= 0x2;
1fbdc7a5
AP		 1452 break;
1453 case VCPU_SREG_DS:
1454 case VCPU_SREG_ES:
1455 case VCPU_SREG_FS:
1456 case VCPU_SREG_GS:
1457 /*
1458 * The accessed bit must always be set in the segment
1459 * descriptor cache, although it can be cleared in the
1460 * descriptor, the cached bit always remains at 1. Since
1461 * Intel has a check on this, set it here to support
1462 * cross-vendor migration.
1463 */
1464 if (!var->unusable)
1465 var->type |= 0x1;
1466 break;
b586eb02 1467 case VCPU_SREG_SS:
e0231715
JR		 1468 /*
1469 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1470 * descriptor is left as 1, although the whole segment has
1471 * been made unusable. Clear it here to pass an Intel VMX
1472 * entry check when cross vendor migrating.
1473 */
1474 if (var->unusable)
1475 var->db = 0;
d9c1b543 1476 /* This is symmetric with svm_set_segment() */
33b458d2 1477 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
b586eb02 1478 break;
1fbdc7a5 1479 }
6aa8b732
AK		 1480}
1481
2e4d2653
IE		 1482static int svm_get_cpl(struct kvm_vcpu *vcpu)
1483{
1484 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1485
1486 return save->cpl;
1487}
1488
89a27f4d 1489static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1490{
a2fa3e9f
GH		 1491 struct vcpu_svm *svm = to_svm(vcpu);
1492
89a27f4d
GN		 1493 dt->size = svm->vmcb->save.idtr.limit;
1494 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1495}
1496
89a27f4d 1497static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1498{
a2fa3e9f
GH		 1499 struct vcpu_svm *svm = to_svm(vcpu);
1500
89a27f4d
GN		 1501 svm->vmcb->save.idtr.limit = dt->size;
1502 svm->vmcb->save.idtr.base = dt->address ;
17a703cb 1503 mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1504}
1505
89a27f4d 1506static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1507{
a2fa3e9f
GH		 1508 struct vcpu_svm *svm = to_svm(vcpu);
1509
89a27f4d
GN		 1510 dt->size = svm->vmcb->save.gdtr.limit;
1511 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1512}
1513
89a27f4d 1514static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1515{
a2fa3e9f
GH		 1516 struct vcpu_svm *svm = to_svm(vcpu);
1517
89a27f4d
GN		 1518 svm->vmcb->save.gdtr.limit = dt->size;
1519 svm->vmcb->save.gdtr.base = dt->address ;
17a703cb 1520 mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1521}
1522
d225157b
AK		 1523static void update_cr0_intercept(struct vcpu_svm *svm)
1524{
1525 ulong gcr0 = svm->vcpu.arch.cr0;
1526 u64 *hcr0 = &svm->vmcb->save.cr0;
1527
bd7e5b08
PB		 1528 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1529 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
d225157b 1530
dcca1a65 1531 mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1532
bd7e5b08 1533 if (gcr0 == *hcr0) {
4ee546b4
RJ		 1534 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1535 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1536 } else {
4ee546b4
RJ		 1537 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1538 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1539 }
1540}
1541
883b0a91 1542void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 1543{
a2fa3e9f
GH		 1544 struct vcpu_svm *svm = to_svm(vcpu);
1545
05b3e0c2 1546#ifdef CONFIG_X86_64
f6801dff 1547 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1548 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1549 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1550 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1551 }
1552
d77c26fc 1553 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1554 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1555 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1556 }
1557 }
1558#endif
ad312c7c 1559 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1560
1561 if (!npt_enabled)
1562 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21 1563
bcf166a9
PB		 1564 /*
1565 * re-enable caching here because the QEMU bios
1566 * does not do it - this results in some delay at
1567 * reboot
1568 */
1569 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1570 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1571 svm->vmcb->save.cr0 = cr0;
dcca1a65 1572 mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1573 update_cr0_intercept(svm);
6aa8b732
AK		 1574}
1575
883b0a91 1576int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 1577{
1e02ce4c 1578 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
e5eab0ce
JR		 1579 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1580
5e1746d6
NHE		 1581 if (cr4 & X86_CR4_VMXE)
1582 return 1;
1583
e5eab0ce 1584 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
f55ac304 1585 svm_flush_tlb(vcpu);
6394b649 1586
ec077263
JR		 1587 vcpu->arch.cr4 = cr4;
1588 if (!npt_enabled)
1589 cr4 |= X86_CR4_PAE;
6394b649 1590 cr4 |= host_cr4_mce;
ec077263 1591 to_svm(vcpu)->vmcb->save.cr4 = cr4;
dcca1a65 1592 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
5e1746d6 1593 return 0;
6aa8b732
AK		 1594}
1595
1596static void svm_set_segment(struct kvm_vcpu *vcpu,
1597 struct kvm_segment *var, int seg)
1598{
a2fa3e9f 1599 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1600 struct vmcb_seg *s = svm_seg(vcpu, seg);
1601
1602 s->base = var->base;
1603 s->limit = var->limit;
1604 s->selector = var->selector;
d9c1b543
RP		 1605 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1606 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1607 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1608 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1609 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1610 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1611 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1612 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
ae9fedc7
PB		 1613
1614 /*
1615 * This is always accurate, except if SYSRET returned to a segment
1616 * with SS.DPL != 3. Intel does not have this quirk, and always
1617 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1618 * would entail passing the CPL to userspace and back.
1619 */
1620 if (seg == VCPU_SREG_SS)
d9c1b543
RP		 1621 /* This is symmetric with svm_get_segment() */
1622 svm->vmcb->save.cpl = (var->dpl & 3);
6aa8b732 1623
060d0c9a 1624 mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1625}
1626
cbdb967a 1627static void update_bp_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1628{
d0bfb940
JK		 1629 struct vcpu_svm *svm = to_svm(vcpu);
1630
18c918c5 1631 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1632
d0bfb940 1633 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940 1634 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1635 set_exception_intercept(svm, BP_VECTOR);
d0bfb940
JK		 1636 } else
1637 vcpu->guest_debug = 0;
44c11430
GN		 1638}
1639
0fe1e009 1640static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1641{
0fe1e009
TH		 1642 if (sd->next_asid > sd->max_asid) {
1643 ++sd->asid_generation;
4faefff3 1644 sd->next_asid = sd->min_asid;
a2fa3e9f 1645 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1646 }
1647
0fe1e009
TH		 1648 svm->asid_generation = sd->asid_generation;
1649 svm->vmcb->control.asid = sd->next_asid++;
d48086d1
JR		 1650
1651 mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1652}
1653
d67668e9 1654static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
73aaf249 1655{
d67668e9 1656 struct vmcb *vmcb = svm->vmcb;
73aaf249 1657
d67668e9
PB		 1658 if (unlikely(value != vmcb->save.dr6)) {
1659 vmcb->save.dr6 = value;
1660 mark_dirty(vmcb, VMCB_DR);
1661 }
73aaf249
JK		 1662}
1663
facb0139
PB		 1664static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1665{
1666 struct vcpu_svm *svm = to_svm(vcpu);
1667
1668 get_debugreg(vcpu->arch.db[0], 0);
1669 get_debugreg(vcpu->arch.db[1], 1);
1670 get_debugreg(vcpu->arch.db[2], 2);
1671 get_debugreg(vcpu->arch.db[3], 3);
d67668e9
PB		 1672 /*
1673 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1674 * because db_interception might need it. We can do it before vmentry.
1675 */
5679b803 1676 vcpu->arch.dr6 = svm->vmcb->save.dr6;
facb0139 1677 vcpu->arch.dr7 = svm->vmcb->save.dr7;
facb0139
PB		 1678 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1679 set_dr_intercepts(svm);
1680}
1681
020df079 1682static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1683{
42dbaa5a 1684 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1685
020df079 1686 svm->vmcb->save.dr7 = value;
72214b96 1687 mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1688}
1689
851ba692 1690static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1691{
0ede79e1 1692 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1261bfa3 1693 u64 error_code = svm->vmcb->control.exit_info_1;
6aa8b732 1694
1261bfa3 1695 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
00b10fe1
BS		 1696 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1697 svm->vmcb->control.insn_bytes : NULL,
d0006530
PB		 1698 svm->vmcb->control.insn_len);
1699}
1700
1701static int npf_interception(struct vcpu_svm *svm)
1702{
0ede79e1 1703 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
d0006530
PB		 1704 u64 error_code = svm->vmcb->control.exit_info_1;
1705
1706 trace_kvm_page_fault(fault_address, error_code);
1707 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
00b10fe1
BS		 1708 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1709 svm->vmcb->control.insn_bytes : NULL,
d0006530 1710 svm->vmcb->control.insn_len);
6aa8b732
AK		 1711}
1712
851ba692 1713static int db_interception(struct vcpu_svm *svm)
d0bfb940 1714{
851ba692 1715 struct kvm_run *kvm_run = svm->vcpu.run;
99c22179 1716 struct kvm_vcpu *vcpu = &svm->vcpu;
851ba692 1717
d0bfb940 1718 if (!(svm->vcpu.guest_debug &
44c11430 1719 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1720 !svm->nmi_singlestep) {
d67668e9
PB		 1721 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1722 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
d0bfb940
JK		 1723 return 1;
1724 }
44c11430 1725
6be7d306 1726 if (svm->nmi_singlestep) {
4aebd0e9 1727 disable_nmi_singlestep(svm);
99c22179
VK		 1728 /* Make sure we check for pending NMIs upon entry */
1729 kvm_make_request(KVM_REQ_EVENT, vcpu);
44c11430
GN		 1730 }
1731
1732 if (svm->vcpu.guest_debug &
e0231715 1733 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430 1734 kvm_run->exit_reason = KVM_EXIT_DEBUG;
dee919d1
PB		 1735 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1736 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
44c11430
GN		 1737 kvm_run->debug.arch.pc =
1738 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1739 kvm_run->debug.arch.exception = DB_VECTOR;
1740 return 0;
1741 }
1742
1743 return 1;
d0bfb940
JK		 1744}
1745
851ba692 1746static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1747{
851ba692
AK		 1748 struct kvm_run *kvm_run = svm->vcpu.run;
1749
d0bfb940
JK		 1750 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1751 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1752 kvm_run->debug.arch.exception = BP_VECTOR;
1753 return 0;
1754}
1755
851ba692 1756static int ud_interception(struct vcpu_svm *svm)
7aa81cc0 1757{
082d06ed 1758 return handle_ud(&svm->vcpu);
7aa81cc0
AL		 1759}
1760
54a20552
EN		 1761static int ac_interception(struct vcpu_svm *svm)
1762{
1763 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1764 return 1;
1765}
1766
9718420e
LA		 1767static int gp_interception(struct vcpu_svm *svm)
1768{
1769 struct kvm_vcpu *vcpu = &svm->vcpu;
1770 u32 error_code = svm->vmcb->control.exit_info_1;
9718420e
LA		 1771
1772 WARN_ON_ONCE(!enable_vmware_backdoor);
1773
a6c6ed1e
SC		 1774 /*
1775 * VMware backdoor emulation on #GP interception only handles IN{S},
1776 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1777 */
1778 if (error_code) {
1779 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1780 return 1;
1781 }
60fc3d02 1782 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9718420e
LA		 1783}
1784
67ec6607
JR		 1785static bool is_erratum_383(void)
1786{
1787 int err, i;
1788 u64 value;
1789
1790 if (!erratum_383_found)
1791 return false;
1792
1793 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1794 if (err)
1795 return false;
1796
1797 /* Bit 62 may or may not be set for this mce */
1798 value &= ~(1ULL << 62);
1799
1800 if (value != 0xb600000000010015ULL)
1801 return false;
1802
1803 /* Clear MCi_STATUS registers */
1804 for (i = 0; i < 6; ++i)
1805 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1806
1807 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1808 if (!err) {
1809 u32 low, high;
1810
1811 value &= ~(1ULL << 2);
1812 low = lower_32_bits(value);
1813 high = upper_32_bits(value);
1814
1815 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1816 }
1817
1818 /* Flush tlb to evict multi-match entries */
1819 __flush_tlb_all();
1820
1821 return true;
1822}
1823
1c164cb3
UB		 1824/*
1825 * Trigger machine check on the host. We assume all the MSRs are already set up
1826 * by the CPU and that we still run on the same CPU as the MCE occurred on.
1827 * We pass a fake environment to the machine check handler because we want
1828 * the guest to be always treated like user space, no matter what context
1829 * it used internally.
1830 */
1831static void kvm_machine_check(void)
1832{
1833#if defined(CONFIG_X86_MCE)
1834 struct pt_regs regs = {
1835 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1836 .flags = X86_EFLAGS_IF,
1837 };
1838
1839 do_machine_check(&regs, 0);
1840#endif
1841}
1842
fe5913e4 1843static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1844{
67ec6607
JR		 1845 if (is_erratum_383()) {
1846 /*
1847 * Erratum 383 triggered. Guest state is corrupt so kill the
1848 * guest.
1849 */
1850 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1851
a8eeb04a 1852 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1853
1854 return;
1855 }
1856
53371b50
JR		 1857 /*
1858 * On an #MC intercept the MCE handler is not called automatically in
1859 * the host. So do it by hand here.
1860 */
1c164cb3 1861 kvm_machine_check();
fe5913e4
JR		 1862}
1863
1864static int mc_interception(struct vcpu_svm *svm)
1865{
53371b50
JR		 1866 return 1;
1867}
1868
851ba692 1869static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1870{
851ba692
AK		 1871 struct kvm_run *kvm_run = svm->vcpu.run;
1872
46fe4ddd
JR		 1873 /*
1874 * VMCB is undefined after a SHUTDOWN intercept
1875 * so reinitialize it.
1876 */
a2fa3e9f 1877 clear_page(svm->vmcb);
5690891b 1878 init_vmcb(svm);
46fe4ddd
JR		 1879
1880 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1881 return 0;
1882}
1883
851ba692 1884static int io_interception(struct vcpu_svm *svm)
6aa8b732 1885{
cf8f70bf 1886 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1887 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
dca7f128 1888 int size, in, string;
039576c0 1889 unsigned port;
6aa8b732 1890
e756fc62 1891 ++svm->vcpu.stat.io_exits;
e70669ab 1892 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1893 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
8370c3d0 1894 if (string)
60fc3d02 1895 return kvm_emulate_instruction(vcpu, 0);
cf8f70bf 1896
039576c0
AK		 1897 port = io_info >> 16;
1898 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1899 svm->next_rip = svm->vmcb->control.exit_info_2;
cf8f70bf 1900
dca7f128 1901 return kvm_fast_pio(&svm->vcpu, size, port, in);
6aa8b732
AK		 1902}
1903
851ba692 1904static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1905{
1906 return 1;
1907}
1908
851ba692 1909static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1910{
1911 ++svm->vcpu.stat.irq_exits;
1912 return 1;
1913}
1914
851ba692 1915static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1916{
1917 return 1;
1918}
1919
851ba692 1920static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1921{
e756fc62 1922 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1923}
1924
851ba692 1925static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1926{
0d9c055e 1927 return kvm_emulate_hypercall(&svm->vcpu);
02e235bc
AK		 1928}
1929
851ba692 1930static int vmload_interception(struct vcpu_svm *svm)
5542675b 1931{
9966bf68 1932 struct vmcb *nested_vmcb;
8c5fbf1a 1933 struct kvm_host_map map;
b742c1e6 1934 int ret;
9966bf68 1935
5542675b
AG		 1936 if (nested_svm_check_permissions(svm))
1937 return 1;
1938
8c5fbf1a
KA		 1939 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1940 if (ret) {
1941 if (ret == -EINVAL)
1942 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1943 return 1;
8c5fbf1a
KA		 1944 }
1945
1946 nested_vmcb = map.hva;
9966bf68 1947
b742c1e6 1948 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1949
9966bf68 1950 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
8c5fbf1a 1951 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1952
b742c1e6 1953 return ret;
5542675b
AG		 1954}
1955
851ba692 1956static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1957{
9966bf68 1958 struct vmcb *nested_vmcb;
8c5fbf1a 1959 struct kvm_host_map map;
b742c1e6 1960 int ret;
9966bf68 1961
5542675b
AG		 1962 if (nested_svm_check_permissions(svm))
1963 return 1;
1964
8c5fbf1a
KA		 1965 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1966 if (ret) {
1967 if (ret == -EINVAL)
1968 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1969 return 1;
8c5fbf1a
KA		 1970 }
1971
1972 nested_vmcb = map.hva;
9966bf68 1973
b742c1e6 1974 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1975
9966bf68 1976 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
8c5fbf1a 1977 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1978
b742c1e6 1979 return ret;
5542675b
AG		 1980}
1981
851ba692 1982static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1983{
3d6368ef
AG		 1984 if (nested_svm_check_permissions(svm))
1985 return 1;
1986
e7134c1b 1987 return nested_svm_vmrun(svm);
3d6368ef
AG		 1988}
1989
ffdf7f9e
PB		 1990void svm_set_gif(struct vcpu_svm *svm, bool value)
1991{
1992 if (value) {
1993 /*
1994 * If VGIF is enabled, the STGI intercept is only added to
1995 * detect the opening of the SMI/NMI window; remove it now.
1996 * Likewise, clear the VINTR intercept, we will set it
1997 * again while processing KVM_REQ_EVENT if needed.
1998 */
1999 if (vgif_enabled(svm))
2000 clr_intercept(svm, INTERCEPT_STGI);
2001 if (is_intercept(svm, SVM_EXIT_VINTR))
2002 svm_clear_vintr(svm);
2003
2004 enable_gif(svm);
2005 if (svm->vcpu.arch.smi_pending ||
2006 svm->vcpu.arch.nmi_pending ||
2007 kvm_cpu_has_injectable_intr(&svm->vcpu))
2008 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2009 } else {
2010 disable_gif(svm);
2011
2012 /*
2013 * After a CLGI no interrupts should come. But if vGIF is
2014 * in use, we still rely on the VINTR intercept (rather than
2015 * STGI) to detect an open interrupt window.
2016 */
2017 if (!vgif_enabled(svm))
2018 svm_clear_vintr(svm);
2019 }
2020}
2021
851ba692 2022static int stgi_interception(struct vcpu_svm *svm)
1371d904 2023{
b742c1e6
LP		 2024 int ret;
2025
1371d904
AG		 2026 if (nested_svm_check_permissions(svm))
2027 return 1;
2028
b742c1e6 2029 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2030 svm_set_gif(svm, true);
b742c1e6 2031 return ret;
1371d904
AG		 2032}
2033
851ba692 2034static int clgi_interception(struct vcpu_svm *svm)
1371d904 2035{
b742c1e6
LP		 2036 int ret;
2037
1371d904
AG		 2038 if (nested_svm_check_permissions(svm))
2039 return 1;
2040
b742c1e6 2041 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2042 svm_set_gif(svm, false);
b742c1e6 2043 return ret;
1371d904
AG		 2044}
2045
851ba692 2046static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2047{
2048 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2049
de3cd117
SC		 2050 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2051 kvm_rax_read(&svm->vcpu));
ec1ff790 2052
ff092385 2053 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
de3cd117 2054 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
ff092385 2055
b742c1e6 2056 return kvm_skip_emulated_instruction(&svm->vcpu);
ff092385
AG		 2057}
2058
532a46b9
JR		 2059static int skinit_interception(struct vcpu_svm *svm)
2060{
de3cd117 2061 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
532a46b9
JR		 2062
2063 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2064 return 1;
2065}
2066
dab429a7
DK		 2067static int wbinvd_interception(struct vcpu_svm *svm)
2068{
6affcbed 2069 return kvm_emulate_wbinvd(&svm->vcpu);
dab429a7
DK		 2070}
2071
81dd35d4
JR		 2072static int xsetbv_interception(struct vcpu_svm *svm)
2073{
2074 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
de3cd117 2075 u32 index = kvm_rcx_read(&svm->vcpu);
81dd35d4
JR		 2076
2077 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
b742c1e6 2078 return kvm_skip_emulated_instruction(&svm->vcpu);
81dd35d4
JR		 2079 }
2080
2081 return 1;
2082}
2083
0cb8410b
JM		 2084static int rdpru_interception(struct vcpu_svm *svm)
2085{
2086 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2087 return 1;
2088}
2089
851ba692 2090static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2091{
37817f29 2092 u16 tss_selector;
64a7ec06
GN		 2093 int reason;
2094 int int_type = svm->vmcb->control.exit_int_info &
2095 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2096 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2097 uint32_t type =
2098 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2099 uint32_t idt_v =
2100 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2101 bool has_error_code = false;
2102 u32 error_code = 0;
37817f29
IE		 2103
2104 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2105
37817f29
IE		 2106 if (svm->vmcb->control.exit_info_2 &
2107 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2108 reason = TASK_SWITCH_IRET;
2109 else if (svm->vmcb->control.exit_info_2 &
2110 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2111 reason = TASK_SWITCH_JMP;
fe8e7f83 2112 else if (idt_v)
64a7ec06
GN		 2113 reason = TASK_SWITCH_GATE;
2114 else
2115 reason = TASK_SWITCH_CALL;
2116
fe8e7f83
GN		 2117 if (reason == TASK_SWITCH_GATE) {
2118 switch (type) {
2119 case SVM_EXITINTINFO_TYPE_NMI:
2120 svm->vcpu.arch.nmi_injected = false;
2121 break;
2122 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2123 if (svm->vmcb->control.exit_info_2 &
2124 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2125 has_error_code = true;
2126 error_code =
2127 (u32)svm->vmcb->control.exit_info_2;
2128 }
fe8e7f83
GN		 2129 kvm_clear_exception_queue(&svm->vcpu);
2130 break;
2131 case SVM_EXITINTINFO_TYPE_INTR:
2132 kvm_clear_interrupt_queue(&svm->vcpu);
2133 break;
2134 default:
2135 break;
2136 }
2137 }
64a7ec06 2138
8317c298
GN		 2139 if (reason != TASK_SWITCH_GATE ||
2140 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2141 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f8ea7c60 2142 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
60fc3d02 2143 if (!skip_emulated_instruction(&svm->vcpu))
738fece4 2144 return 0;
f8ea7c60 2145 }
64a7ec06 2146
7f3d35fd
KW		 2147 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2148 int_vec = -1;
2149
1051778f 2150 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
60fc3d02 2151 has_error_code, error_code);
6aa8b732
AK		 2152}
2153
851ba692 2154static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2155{
6a908b62 2156 return kvm_emulate_cpuid(&svm->vcpu);
6aa8b732
AK		 2157}
2158
851ba692 2159static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2160{
2161 ++svm->vcpu.stat.nmi_window_exits;
8a05a1b8 2162 clr_intercept(svm, INTERCEPT_IRET);
44c11430 2163 svm->vcpu.arch.hflags |= HF_IRET_MASK;
bd3d1ec3 2164 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
f303b4ce 2165 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
95ba8273
GN		 2166 return 1;
2167}
2168
851ba692 2169static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2170{
df4f3108 2171 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
60fc3d02 2172 return kvm_emulate_instruction(&svm->vcpu, 0);
df4f3108
AP		 2173
2174 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
b742c1e6 2175 return kvm_skip_emulated_instruction(&svm->vcpu);
a7052897
MT		 2176}
2177
851ba692 2178static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2179{
60fc3d02 2180 return kvm_emulate_instruction(&svm->vcpu, 0);
6aa8b732
AK		 2181}
2182
7607b717
BS		 2183static int rsm_interception(struct vcpu_svm *svm)
2184{
60fc3d02 2185 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
7607b717
BS		 2186}
2187
332b56e4
AK		 2188static int rdpmc_interception(struct vcpu_svm *svm)
2189{
2190 int err;
2191
d647eb63 2192 if (!nrips)
332b56e4
AK		 2193 return emulate_on_interception(svm);
2194
2195 err = kvm_rdpmc(&svm->vcpu);
6affcbed 2196 return kvm_complete_insn_gp(&svm->vcpu, err);
332b56e4
AK		 2197}
2198
52eb5a6d
XL		 2199static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2200 unsigned long val)
628afd2a
JR		 2201{
2202 unsigned long cr0 = svm->vcpu.arch.cr0;
2203 bool ret = false;
2204 u64 intercept;
2205
e670bf68 2206 intercept = svm->nested.ctl.intercept;
628afd2a
JR		 2207
2208 if (!is_guest_mode(&svm->vcpu) ||
2209 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2210 return false;
2211
2212 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2213 val &= ~SVM_CR0_SELECTIVE_MASK;
2214
2215 if (cr0 ^ val) {
2216 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2217 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2218 }
2219
2220 return ret;
2221}
2222
7ff76d58
AP		 2223#define CR_VALID (1ULL << 63)
2224
2225static int cr_interception(struct vcpu_svm *svm)
2226{
2227 int reg, cr;
2228 unsigned long val;
2229 int err;
2230
2231 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2232 return emulate_on_interception(svm);
2233
2234 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2235 return emulate_on_interception(svm);
2236
2237 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
5e57518d
DK		 2238 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2239 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2240 else
2241 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
7ff76d58
AP		 2242
2243 err = 0;
2244 if (cr >= 16) { /* mov to cr */
2245 cr -= 16;
2246 val = kvm_register_read(&svm->vcpu, reg);
2247 switch (cr) {
2248 case 0:
628afd2a
JR		 2249 if (!check_selective_cr0_intercepted(svm, val))
2250 err = kvm_set_cr0(&svm->vcpu, val);
977b2d03
JR		 2251 else
2252 return 1;
2253
7ff76d58
AP		 2254 break;
2255 case 3:
2256 err = kvm_set_cr3(&svm->vcpu, val);
2257 break;
2258 case 4:
2259 err = kvm_set_cr4(&svm->vcpu, val);
2260 break;
2261 case 8:
2262 err = kvm_set_cr8(&svm->vcpu, val);
2263 break;
2264 default:
2265 WARN(1, "unhandled write to CR%d", cr);
2266 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2267 return 1;
2268 }
2269 } else { /* mov from cr */
2270 switch (cr) {
2271 case 0:
2272 val = kvm_read_cr0(&svm->vcpu);
2273 break;
2274 case 2:
2275 val = svm->vcpu.arch.cr2;
2276 break;
2277 case 3:
9f8fe504 2278 val = kvm_read_cr3(&svm->vcpu);
7ff76d58
AP		 2279 break;
2280 case 4:
2281 val = kvm_read_cr4(&svm->vcpu);
2282 break;
2283 case 8:
2284 val = kvm_get_cr8(&svm->vcpu);
2285 break;
2286 default:
2287 WARN(1, "unhandled read from CR%d", cr);
2288 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2289 return 1;
2290 }
2291 kvm_register_write(&svm->vcpu, reg, val);
2292 }
6affcbed 2293 return kvm_complete_insn_gp(&svm->vcpu, err);
7ff76d58
AP		 2294}
2295
cae3797a
AP		 2296static int dr_interception(struct vcpu_svm *svm)
2297{
2298 int reg, dr;
2299 unsigned long val;
cae3797a 2300
facb0139
PB		 2301 if (svm->vcpu.guest_debug == 0) {
2302 /*
2303 * No more DR vmexits; force a reload of the debug registers
2304 * and reenter on this instruction. The next vmexit will
2305 * retrieve the full state of the debug registers.
2306 */
2307 clr_dr_intercepts(svm);
2308 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2309 return 1;
2310 }
2311
cae3797a
AP		 2312 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2313 return emulate_on_interception(svm);
2314
2315 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2316 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2317
2318 if (dr >= 16) { /* mov to DRn */
16f8a6f9
NA		 2319 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2320 return 1;
cae3797a
AP		 2321 val = kvm_register_read(&svm->vcpu, reg);
2322 kvm_set_dr(&svm->vcpu, dr - 16, val);
2323 } else {
16f8a6f9
NA		 2324 if (!kvm_require_dr(&svm->vcpu, dr))
2325 return 1;
2326 kvm_get_dr(&svm->vcpu, dr, &val);
2327 kvm_register_write(&svm->vcpu, reg, val);
cae3797a
AP		 2328 }
2329
b742c1e6 2330 return kvm_skip_emulated_instruction(&svm->vcpu);
cae3797a
AP		 2331}
2332
851ba692 2333static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2334{
851ba692 2335 struct kvm_run *kvm_run = svm->vcpu.run;
eea1cff9 2336 int r;
851ba692 2337
0a5fff19
GN		 2338 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2339 /* instruction emulation calls kvm_set_cr8() */
7ff76d58 2340 r = cr_interception(svm);
35754c98 2341 if (lapic_in_kernel(&svm->vcpu))
7ff76d58 2342 return r;
0a5fff19 2343 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
7ff76d58 2344 return r;
1d075434
JR		 2345 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2346 return 0;
2347}
2348
801e459a
TL		 2349static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2350{
d1d93fa9
TL		 2351 msr->data = 0;
2352
2353 switch (msr->index) {
2354 case MSR_F10H_DECFG:
2355 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2356 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2357 break;
2358 default:
2359 return 1;
2360 }
2361
2362 return 0;
801e459a
TL		 2363}
2364
609e36d3 2365static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2366{
a2fa3e9f
GH		 2367 struct vcpu_svm *svm = to_svm(vcpu);
2368
609e36d3 2369 switch (msr_info->index) {
8c06585d 2370 case MSR_STAR:
609e36d3 2371 msr_info->data = svm->vmcb->save.star;
6aa8b732 2372 break;
0e859cac 2373#ifdef CONFIG_X86_64
6aa8b732 2374 case MSR_LSTAR:
609e36d3 2375 msr_info->data = svm->vmcb->save.lstar;
6aa8b732
AK		 2376 break;
2377 case MSR_CSTAR:
609e36d3 2378 msr_info->data = svm->vmcb->save.cstar;
6aa8b732
AK		 2379 break;
2380 case MSR_KERNEL_GS_BASE:
609e36d3 2381 msr_info->data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2382 break;
2383 case MSR_SYSCALL_MASK:
609e36d3 2384 msr_info->data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2385 break;
2386#endif
2387 case MSR_IA32_SYSENTER_CS:
609e36d3 2388 msr_info->data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2389 break;
2390 case MSR_IA32_SYSENTER_EIP:
609e36d3 2391 msr_info->data = svm->sysenter_eip;
6aa8b732
AK		 2392 break;
2393 case MSR_IA32_SYSENTER_ESP:
609e36d3 2394 msr_info->data = svm->sysenter_esp;
6aa8b732 2395 break;
46896c73
PB		 2396 case MSR_TSC_AUX:
2397 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2398 return 1;
2399 msr_info->data = svm->tsc_aux;
2400 break;
e0231715
JR		 2401 /*
2402 * Nobody will change the following 5 values in the VMCB so we can
2403 * safely return them on rdmsr. They will always be 0 until LBRV is
2404 * implemented.
2405 */
a2938c80 2406 case MSR_IA32_DEBUGCTLMSR:
609e36d3 2407 msr_info->data = svm->vmcb->save.dbgctl;
a2938c80
JR		 2408 break;
2409 case MSR_IA32_LASTBRANCHFROMIP:
609e36d3 2410 msr_info->data = svm->vmcb->save.br_from;
a2938c80
JR		 2411 break;
2412 case MSR_IA32_LASTBRANCHTOIP:
609e36d3 2413 msr_info->data = svm->vmcb->save.br_to;
a2938c80
JR		 2414 break;
2415 case MSR_IA32_LASTINTFROMIP:
609e36d3 2416 msr_info->data = svm->vmcb->save.last_excp_from;
a2938c80
JR		 2417 break;
2418 case MSR_IA32_LASTINTTOIP:
609e36d3 2419 msr_info->data = svm->vmcb->save.last_excp_to;
a2938c80 2420 break;
b286d5d8 2421 case MSR_VM_HSAVE_PA:
609e36d3 2422 msr_info->data = svm->nested.hsave_msr;
b286d5d8 2423 break;
eb6f302e 2424 case MSR_VM_CR:
609e36d3 2425 msr_info->data = svm->nested.vm_cr_msr;
eb6f302e 2426 break;
b2ac58f9
KA		 2427 case MSR_IA32_SPEC_CTRL:
2428 if (!msr_info->host_initiated &&
df7e8818
PB		 2429 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2430 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2431 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2432 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2433 return 1;
2434
2435 msr_info->data = svm->spec_ctrl;
2436 break;
bc226f07
TL		 2437 case MSR_AMD64_VIRT_SPEC_CTRL:
2438 if (!msr_info->host_initiated &&
2439 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2440 return 1;
2441
2442 msr_info->data = svm->virt_spec_ctrl;
2443 break;
ae8b7875
BP		 2444 case MSR_F15H_IC_CFG: {
2445
2446 int family, model;
2447
2448 family = guest_cpuid_family(vcpu);
2449 model = guest_cpuid_model(vcpu);
2450
2451 if (family < 0 || model < 0)
2452 return kvm_get_msr_common(vcpu, msr_info);
2453
2454 msr_info->data = 0;
2455
2456 if (family == 0x15 &&
2457 (model >= 0x2 && model < 0x20))
2458 msr_info->data = 0x1E;
2459 }
2460 break;
d1d93fa9
TL		 2461 case MSR_F10H_DECFG:
2462 msr_info->data = svm->msr_decfg;
2463 break;
6aa8b732 2464 default:
609e36d3 2465 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2466 }
2467 return 0;
2468}
2469
851ba692 2470static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2471{
1edce0a9 2472 return kvm_emulate_rdmsr(&svm->vcpu);
6aa8b732
AK		 2473}
2474
4a810181
JR		 2475static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2476{
2477 struct vcpu_svm *svm = to_svm(vcpu);
2478 int svm_dis, chg_mask;
2479
2480 if (data & ~SVM_VM_CR_VALID_MASK)
2481 return 1;
2482
2483 chg_mask = SVM_VM_CR_VALID_MASK;
2484
2485 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2486 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2487
2488 svm->nested.vm_cr_msr &= ~chg_mask;
2489 svm->nested.vm_cr_msr |= (data & chg_mask);
2490
2491 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2492
2493 /* check for svm_disable while efer.svme is set */
2494 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2495 return 1;
2496
2497 return 0;
2498}
2499
8fe8ab46 2500static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
6aa8b732 2501{
a2fa3e9f
GH		 2502 struct vcpu_svm *svm = to_svm(vcpu);
2503
8fe8ab46
WA		 2504 u32 ecx = msr->index;
2505 u64 data = msr->data;
6aa8b732 2506 switch (ecx) {
15038e14
PB		 2507 case MSR_IA32_CR_PAT:
2508 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2509 return 1;
2510 vcpu->arch.pat = data;
2511 svm->vmcb->save.g_pat = data;
2512 mark_dirty(svm->vmcb, VMCB_NPT);
2513 break;
b2ac58f9
KA		 2514 case MSR_IA32_SPEC_CTRL:
2515 if (!msr->host_initiated &&
df7e8818
PB		 2516 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2517 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2518 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2519 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2520 return 1;
2521
6441fa61 2522 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
b2ac58f9
KA		 2523 return 1;
2524
2525 svm->spec_ctrl = data;
b2ac58f9
KA		 2526 if (!data)
2527 break;
2528
2529 /*
2530 * For non-nested:
2531 * When it's written (to non-zero) for the first time, pass
2532 * it through.
2533 *
2534 * For nested:
2535 * The handling of the MSR bitmap for L2 guests is done in
2536 * nested_svm_vmrun_msrpm.
2537 * We update the L1 MSR bit as well since it will end up
2538 * touching the MSR anyway now.
2539 */
2540 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2541 break;
15d45071
AR		 2542 case MSR_IA32_PRED_CMD:
2543 if (!msr->host_initiated &&
e7c587da 2544 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
15d45071
AR		 2545 return 1;
2546
2547 if (data & ~PRED_CMD_IBPB)
2548 return 1;
6441fa61
PB		 2549 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2550 return 1;
15d45071
AR		 2551 if (!data)
2552 break;
2553
2554 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
15d45071
AR		 2555 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2556 break;
bc226f07
TL		 2557 case MSR_AMD64_VIRT_SPEC_CTRL:
2558 if (!msr->host_initiated &&
2559 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2560 return 1;
2561
2562 if (data & ~SPEC_CTRL_SSBD)
2563 return 1;
2564
2565 svm->virt_spec_ctrl = data;
2566 break;
8c06585d 2567 case MSR_STAR:
a2fa3e9f 2568 svm->vmcb->save.star = data;
6aa8b732 2569 break;
49b14f24 2570#ifdef CONFIG_X86_64
6aa8b732 2571 case MSR_LSTAR:
a2fa3e9f 2572 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2573 break;
2574 case MSR_CSTAR:
a2fa3e9f 2575 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2576 break;
2577 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2578 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2579 break;
2580 case MSR_SYSCALL_MASK:
a2fa3e9f 2581 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2582 break;
2583#endif
2584 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2585 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2586 break;
2587 case MSR_IA32_SYSENTER_EIP:
017cb99e 2588 svm->sysenter_eip = data;
a2fa3e9f 2589 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2590 break;
2591 case MSR_IA32_SYSENTER_ESP:
017cb99e 2592 svm->sysenter_esp = data;
a2fa3e9f 2593 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2594 break;
46896c73
PB		 2595 case MSR_TSC_AUX:
2596 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2597 return 1;
2598
2599 /*
2600 * This is rare, so we update the MSR here instead of using
2601 * direct_access_msrs. Doing that would require a rdmsr in
2602 * svm_vcpu_put.
2603 */
2604 svm->tsc_aux = data;
2605 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2606 break;
a2938c80 2607 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2608 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
a737f256
CD		 2609 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2610 __func__, data);
24e09cbf
JR		 2611 break;
2612 }
2613 if (data & DEBUGCTL_RESERVED_BITS)
2614 return 1;
2615
2616 svm->vmcb->save.dbgctl = data;
b53ba3f9 2617 mark_dirty(svm->vmcb, VMCB_LBR);
24e09cbf
JR		 2618 if (data & (1ULL<<0))
2619 svm_enable_lbrv(svm);
2620 else
2621 svm_disable_lbrv(svm);
a2938c80 2622 break;
b286d5d8 2623 case MSR_VM_HSAVE_PA:
e6aa9abd 2624 svm->nested.hsave_msr = data;
62b9abaa 2625 break;
3c5d0a44 2626 case MSR_VM_CR:
4a810181 2627 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2628 case MSR_VM_IGNNE:
a737f256 2629 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3c5d0a44 2630 break;
d1d93fa9
TL		 2631 case MSR_F10H_DECFG: {
2632 struct kvm_msr_entry msr_entry;
2633
2634 msr_entry.index = msr->index;
2635 if (svm_get_msr_feature(&msr_entry))
2636 return 1;
2637
2638 /* Check the supported bits */
2639 if (data & ~msr_entry.data)
2640 return 1;
2641
2642 /* Don't allow the guest to change a bit, #GP */
2643 if (!msr->host_initiated && (data ^ msr_entry.data))
2644 return 1;
2645
2646 svm->msr_decfg = data;
2647 break;
2648 }
44a95dae
SS		 2649 case MSR_IA32_APICBASE:
2650 if (kvm_vcpu_apicv_active(vcpu))
2651 avic_update_vapic_bar(to_svm(vcpu), data);
b2869f28 2652 /* Fall through */
6aa8b732 2653 default:
8fe8ab46 2654 return kvm_set_msr_common(vcpu, msr);
6aa8b732
AK		 2655 }
2656 return 0;
2657}
2658
851ba692 2659static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2660{
1edce0a9 2661 return kvm_emulate_wrmsr(&svm->vcpu);
6aa8b732
AK		 2662}
2663
851ba692 2664static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2665{
e756fc62 2666 if (svm->vmcb->control.exit_info_1)
851ba692 2667 return wrmsr_interception(svm);
6aa8b732 2668 else
851ba692 2669 return rdmsr_interception(svm);
6aa8b732
AK		 2670}
2671
851ba692 2672static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2673{
3842d135 2674 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2675 svm_clear_vintr(svm);
f3515dc3
SS		 2676
2677 /*
2678 * For AVIC, the only reason to end up here is ExtINTs.
2679 * In this case AVIC was temporarily disabled for
2680 * requesting the IRQ window and we have to re-enable it.
2681 */
2682 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2683
675acb75 2684 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2685 return 1;
2686}
2687
565d0998
ML		 2688static int pause_interception(struct vcpu_svm *svm)
2689{
de63ad4c
LM		 2690 struct kvm_vcpu *vcpu = &svm->vcpu;
2691 bool in_kernel = (svm_get_cpl(vcpu) == 0);
2692
8566ac8b
BM		 2693 if (pause_filter_thresh)
2694 grow_ple_window(vcpu);
2695
de63ad4c 2696 kvm_vcpu_on_spin(vcpu, in_kernel);
565d0998
ML		 2697 return 1;
2698}
2699
87c00572
GS		 2700static int nop_interception(struct vcpu_svm *svm)
2701{
b742c1e6 2702 return kvm_skip_emulated_instruction(&(svm->vcpu));
87c00572
GS		 2703}
2704
2705static int monitor_interception(struct vcpu_svm *svm)
2706{
2707 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2708 return nop_interception(svm);
2709}
2710
2711static int mwait_interception(struct vcpu_svm *svm)
2712{
2713 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2714 return nop_interception(svm);
2715}
2716
09941fbb 2717static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
7ff76d58
AP		 2718 [SVM_EXIT_READ_CR0] = cr_interception,
2719 [SVM_EXIT_READ_CR3] = cr_interception,
2720 [SVM_EXIT_READ_CR4] = cr_interception,
2721 [SVM_EXIT_READ_CR8] = cr_interception,
5e57518d 2722 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
628afd2a 2723 [SVM_EXIT_WRITE_CR0] = cr_interception,
7ff76d58
AP		 2724 [SVM_EXIT_WRITE_CR3] = cr_interception,
2725 [SVM_EXIT_WRITE_CR4] = cr_interception,
e0231715 2726 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
cae3797a
AP		 2727 [SVM_EXIT_READ_DR0] = dr_interception,
2728 [SVM_EXIT_READ_DR1] = dr_interception,
2729 [SVM_EXIT_READ_DR2] = dr_interception,
2730 [SVM_EXIT_READ_DR3] = dr_interception,
2731 [SVM_EXIT_READ_DR4] = dr_interception,
2732 [SVM_EXIT_READ_DR5] = dr_interception,
2733 [SVM_EXIT_READ_DR6] = dr_interception,
2734 [SVM_EXIT_READ_DR7] = dr_interception,
2735 [SVM_EXIT_WRITE_DR0] = dr_interception,
2736 [SVM_EXIT_WRITE_DR1] = dr_interception,
2737 [SVM_EXIT_WRITE_DR2] = dr_interception,
2738 [SVM_EXIT_WRITE_DR3] = dr_interception,
2739 [SVM_EXIT_WRITE_DR4] = dr_interception,
2740 [SVM_EXIT_WRITE_DR5] = dr_interception,
2741 [SVM_EXIT_WRITE_DR6] = dr_interception,
2742 [SVM_EXIT_WRITE_DR7] = dr_interception,
d0bfb940
JK		 2743 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2744 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2745 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715 2746 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
e0231715 2747 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
54a20552 2748 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
9718420e 2749 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
e0231715 2750 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2751 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2752 [SVM_EXIT_SMI] = nop_on_interception,
2753 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2754 [SVM_EXIT_VINTR] = interrupt_window_interception,
332b56e4 2755 [SVM_EXIT_RDPMC] = rdpmc_interception,
6aa8b732 2756 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2757 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2758 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2759 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2760 [SVM_EXIT_HLT] = halt_interception,
a7052897 2761 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2762 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2763 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2764 [SVM_EXIT_MSR] = msr_interception,
2765 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2766 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2767 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2768 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2769 [SVM_EXIT_VMLOAD] = vmload_interception,
2770 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2771 [SVM_EXIT_STGI] = stgi_interception,
2772 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2773 [SVM_EXIT_SKINIT] = skinit_interception,
dab429a7 2774 [SVM_EXIT_WBINVD] = wbinvd_interception,
87c00572
GS		 2775 [SVM_EXIT_MONITOR] = monitor_interception,
2776 [SVM_EXIT_MWAIT] = mwait_interception,
81dd35d4 2777 [SVM_EXIT_XSETBV] = xsetbv_interception,
0cb8410b 2778 [SVM_EXIT_RDPRU] = rdpru_interception,
d0006530 2779 [SVM_EXIT_NPF] = npf_interception,
7607b717 2780 [SVM_EXIT_RSM] = rsm_interception,
18f40c53
SS		 2781 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2782 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
6aa8b732
AK		 2783};
2784
ae8cc059 2785static void dump_vmcb(struct kvm_vcpu *vcpu)
3f10c846
JR		 2786{
2787 struct vcpu_svm *svm = to_svm(vcpu);
2788 struct vmcb_control_area *control = &svm->vmcb->control;
2789 struct vmcb_save_area *save = &svm->vmcb->save;
2790
6f2f8453
PB		 2791 if (!dump_invalid_vmcb) {
2792 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2793 return;
2794 }
2795
3f10c846 2796 pr_err("VMCB Control Area:\n");
ae8cc059
JP		 2797 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2798 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2799 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2800 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2801 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2802 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2803 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
1d8fb44a
BM		 2804 pr_err("%-20s%d\n", "pause filter threshold:",
2805 control->pause_filter_thresh);
ae8cc059
JP		 2806 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2807 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2808 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2809 pr_err("%-20s%d\n", "asid:", control->asid);
2810 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2811 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2812 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2813 pr_err("%-20s%08x\n", "int_state:", control->int_state);
2814 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2815 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2816 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2817 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2818 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2819 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2820 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
44a95dae 2821 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
ae8cc059
JP		 2822 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2823 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
0dc92119 2824 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
ae8cc059 2825 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
44a95dae
SS		 2826 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2827 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2828 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3f10c846 2829 pr_err("VMCB State Save Area:\n");
ae8cc059
JP		 2830 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2831 "es:",
2832 save->es.selector, save->es.attrib,
2833 save->es.limit, save->es.base);
2834 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2835 "cs:",
2836 save->cs.selector, save->cs.attrib,
2837 save->cs.limit, save->cs.base);
2838 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2839 "ss:",
2840 save->ss.selector, save->ss.attrib,
2841 save->ss.limit, save->ss.base);
2842 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2843 "ds:",
2844 save->ds.selector, save->ds.attrib,
2845 save->ds.limit, save->ds.base);
2846 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2847 "fs:",
2848 save->fs.selector, save->fs.attrib,
2849 save->fs.limit, save->fs.base);
2850 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2851 "gs:",
2852 save->gs.selector, save->gs.attrib,
2853 save->gs.limit, save->gs.base);
2854 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2855 "gdtr:",
2856 save->gdtr.selector, save->gdtr.attrib,
2857 save->gdtr.limit, save->gdtr.base);
2858 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2859 "ldtr:",
2860 save->ldtr.selector, save->ldtr.attrib,
2861 save->ldtr.limit, save->ldtr.base);
2862 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2863 "idtr:",
2864 save->idtr.selector, save->idtr.attrib,
2865 save->idtr.limit, save->idtr.base);
2866 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2867 "tr:",
2868 save->tr.selector, save->tr.attrib,
2869 save->tr.limit, save->tr.base);
3f10c846
JR		 2870 pr_err("cpl: %d efer: %016llx\n",
2871 save->cpl, save->efer);
ae8cc059
JP		 2872 pr_err("%-15s %016llx %-13s %016llx\n",
2873 "cr0:", save->cr0, "cr2:", save->cr2);
2874 pr_err("%-15s %016llx %-13s %016llx\n",
2875 "cr3:", save->cr3, "cr4:", save->cr4);
2876 pr_err("%-15s %016llx %-13s %016llx\n",
2877 "dr6:", save->dr6, "dr7:", save->dr7);
2878 pr_err("%-15s %016llx %-13s %016llx\n",
2879 "rip:", save->rip, "rflags:", save->rflags);
2880 pr_err("%-15s %016llx %-13s %016llx\n",
2881 "rsp:", save->rsp, "rax:", save->rax);
2882 pr_err("%-15s %016llx %-13s %016llx\n",
2883 "star:", save->star, "lstar:", save->lstar);
2884 pr_err("%-15s %016llx %-13s %016llx\n",
2885 "cstar:", save->cstar, "sfmask:", save->sfmask);
2886 pr_err("%-15s %016llx %-13s %016llx\n",
2887 "kernel_gs_base:", save->kernel_gs_base,
2888 "sysenter_cs:", save->sysenter_cs);
2889 pr_err("%-15s %016llx %-13s %016llx\n",
2890 "sysenter_esp:", save->sysenter_esp,
2891 "sysenter_eip:", save->sysenter_eip);
2892 pr_err("%-15s %016llx %-13s %016llx\n",
2893 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2894 pr_err("%-15s %016llx %-13s %016llx\n",
2895 "br_from:", save->br_from, "br_to:", save->br_to);
2896 pr_err("%-15s %016llx %-13s %016llx\n",
2897 "excp_from:", save->last_excp_from,
2898 "excp_to:", save->last_excp_to);
3f10c846
JR		 2899}
2900
586f9607
AK		 2901static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2902{
2903 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2904
2905 *info1 = control->exit_info_1;
2906 *info2 = control->exit_info_2;
2907}
2908
404d5d7b 2909static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6aa8b732 2910{
04d2cc77 2911 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2912 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2913 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2914
8b89fe1f
PB		 2915 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2916
4ee546b4 2917 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 2918 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2919 if (npt_enabled)
2920 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2921
36e2e983
PB		 2922 svm_complete_interrupts(svm);
2923
2030753d 2924 if (is_guest_mode(vcpu)) {
410e4d57
JR		 2925 int vmexit;
2926
d8cabddf
JR		 2927 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2928 svm->vmcb->control.exit_info_1,
2929 svm->vmcb->control.exit_info_2,
2930 svm->vmcb->control.exit_int_info,
e097e5ff
SH		 2931 svm->vmcb->control.exit_int_info_err,
2932 KVM_ISA_SVM);
d8cabddf 2933
410e4d57
JR		 2934 vmexit = nested_svm_exit_special(svm);
2935
2936 if (vmexit == NESTED_EXIT_CONTINUE)
2937 vmexit = nested_svm_exit_handled(svm);
2938
2939 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2940 return 1;
cf74a78b
AG		 2941 }
2942
04d2cc77
AK		 2943 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2944 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2945 kvm_run->fail_entry.hardware_entry_failure_reason
2946 = svm->vmcb->control.exit_code;
3f10c846 2947 dump_vmcb(vcpu);
04d2cc77
AK		 2948 return 0;
2949 }
2950
a2fa3e9f 2951 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2952 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 2953 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2954 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6614c7d0 2955 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
6aa8b732 2956 "exit_code 0x%x\n",
b8688d51 2957 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2958 exit_code);
2959
404d5d7b 2960 if (exit_fastpath != EXIT_FASTPATH_NONE)
1e9e2622 2961 return 1;
404d5d7b
WL		 2962
2963 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2964 || !svm_exit_handlers[exit_code]) {
7396d337
LA		 2965 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2966 dump_vmcb(vcpu);
2967 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2968 vcpu->run->internal.suberror =
2969 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
2970 vcpu->run->internal.ndata = 1;
2971 vcpu->run->internal.data[0] = exit_code;
2972 return 0;
6aa8b732
AK		 2973 }
2974
3dcb2a3f
AA		 2975#ifdef CONFIG_RETPOLINE
2976 if (exit_code == SVM_EXIT_MSR)
2977 return msr_interception(svm);
2978 else if (exit_code == SVM_EXIT_VINTR)
2979 return interrupt_window_interception(svm);
2980 else if (exit_code == SVM_EXIT_INTR)
2981 return intr_interception(svm);
2982 else if (exit_code == SVM_EXIT_HLT)
2983 return halt_interception(svm);
2984 else if (exit_code == SVM_EXIT_NPF)
2985 return npf_interception(svm);
2986#endif
851ba692 2987 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2988}
2989
2990static void reload_tss(struct kvm_vcpu *vcpu)
2991{
2992 int cpu = raw_smp_processor_id();
2993
0fe1e009
TH		 2994 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2995 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2996 load_TR_desc();
2997}
2998
e756fc62 2999static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3000{
3001 int cpu = raw_smp_processor_id();
3002
0fe1e009 3003 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3004
70cd94e6
BS		 3005 if (sev_guest(svm->vcpu.kvm))
3006 return pre_sev_run(svm, cpu);
3007
4b656b12 3008 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3009 if (svm->asid_generation != sd->asid_generation)
3010 new_asid(svm, sd);
6aa8b732
AK		 3011}
3012
95ba8273
GN		 3013static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3014{
3015 struct vcpu_svm *svm = to_svm(vcpu);
3016
3017 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3018 vcpu->arch.hflags |= HF_NMI_MASK;
8a05a1b8 3019 set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3020 ++vcpu->stat.nmi_injections;
3021}
6aa8b732 3022
66fd3f7f 3023static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3024{
3025 struct vcpu_svm *svm = to_svm(vcpu);
3026
2af9194d 3027 BUG_ON(!(gif_set(svm)));
cf74a78b 3028
9fb2d2b4
GN		 3029 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3030 ++vcpu->stat.irq_injections;
3031
219b65dc
AG		 3032 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3033 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3034}
3035
95ba8273 3036static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3037{
3038 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3039
49d654d8 3040 if (svm_nested_virtualize_tpr(vcpu))
88ab24ad
JR		 3041 return;
3042
596f3142
RK		 3043 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3044
95ba8273 3045 if (irr == -1)
aaacfc9a
JR		 3046 return;
3047
95ba8273 3048 if (tpr >= irr)
4ee546b4 3049 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3050}
aaacfc9a 3051
cae96af1 3052bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
95ba8273
GN		 3053{
3054 struct vcpu_svm *svm = to_svm(vcpu);
3055 struct vmcb *vmcb = svm->vmcb;
88c604b6 3056 bool ret;
9c3d370a 3057
cae96af1 3058 if (!gif_set(svm))
bbdad0b5
PB		 3059 return true;
3060
cae96af1
PB		 3061 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3062 return false;
3063
3064 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3065 (svm->vcpu.arch.hflags & HF_NMI_MASK);
924584cc
JR		 3066
3067 return ret;
aaacfc9a
JR		 3068}
3069
c9d40913 3070static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3071{
3072 struct vcpu_svm *svm = to_svm(vcpu);
3073 if (svm->nested.nested_run_pending)
c9d40913 3074 return -EBUSY;
cae96af1 3075
c300ab9f
PB		 3076 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3077 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
c9d40913 3078 return -EBUSY;
c300ab9f
PB		 3079
3080 return !svm_nmi_blocked(vcpu);
cae96af1
PB		 3081}
3082
3cfc3092
JK		 3083static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3084{
3085 struct vcpu_svm *svm = to_svm(vcpu);
3086
3087 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3088}
3089
3090static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3091{
3092 struct vcpu_svm *svm = to_svm(vcpu);
3093
3094 if (masked) {
3095 svm->vcpu.arch.hflags |= HF_NMI_MASK;
8a05a1b8 3096 set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3097 } else {
3098 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
8a05a1b8 3099 clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3100 }
3101}
3102
cae96af1 3103bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
78646121
GN		 3104{
3105 struct vcpu_svm *svm = to_svm(vcpu);
3106 struct vmcb *vmcb = svm->vmcb;
7fcdb510 3107
fc6f7c03 3108 if (!gif_set(svm))
cae96af1 3109 return true;
7fcdb510 3110
fc6f7c03
PB		 3111 if (is_guest_mode(vcpu)) {
3112 /* As long as interrupts are being delivered... */
e9fd761a 3113 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
08245e6d 3114 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
fc6f7c03
PB		 3115 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3116 return true;
3117
3118 /* ... vmexits aren't blocked by the interrupt shadow */
3119 if (nested_exit_on_intr(svm))
3120 return false;
3121 } else {
3122 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3123 return true;
3124 }
3125
3126 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
cae96af1
PB		 3127}
3128
c9d40913 3129static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3130{
3131 struct vcpu_svm *svm = to_svm(vcpu);
3132 if (svm->nested.nested_run_pending)
c9d40913 3133 return -EBUSY;
cae96af1 3134
c300ab9f
PB		 3135 /*
3136 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3137 * e.g. if the IRQ arrived asynchronously after checking nested events.
3138 */
3139 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
c9d40913 3140 return -EBUSY;
c300ab9f
PB		 3141
3142 return !svm_interrupt_blocked(vcpu);
78646121
GN		 3143}
3144
c9a7953f 3145static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3146{
219b65dc 3147 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3148
e0231715
JR		 3149 /*
3150 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3151 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3152 * get that intercept, this function will be called again though and
640bd6e5
JN		 3153 * we'll get the vintr intercept. However, if the vGIF feature is
3154 * enabled, the STGI interception will not occur. Enable the irq
3155 * window under the assumption that the hardware will set the GIF.
e0231715 3156 */
b518ba9f 3157 if (vgif_enabled(svm) || gif_set(svm)) {
f3515dc3
SS		 3158 /*
3159 * IRQ window is not needed when AVIC is enabled,
3160 * unless we have pending ExtINT since it cannot be injected
3161 * via AVIC. In such case, we need to temporarily disable AVIC,
3162 * and fallback to injecting IRQ via V_IRQ.
3163 */
3164 svm_toggle_avic_for_irq_window(vcpu, false);
219b65dc 3165 svm_set_vintr(svm);
219b65dc 3166 }
85f455f7
ED		 3167}
3168
c9a7953f 3169static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3170{
04d2cc77 3171 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3172
44c11430
GN		 3173 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3174 == HF_NMI_MASK)
c9a7953f 3175 return; /* IRET will cause a vm exit */
44c11430 3176
640bd6e5
JN		 3177 if (!gif_set(svm)) {
3178 if (vgif_enabled(svm))
3179 set_intercept(svm, INTERCEPT_STGI);
1a5e1852 3180 return; /* STGI will cause a vm exit */
640bd6e5 3181 }
1a5e1852 3182
e0231715
JR		 3183 /*
3184 * Something prevents NMI from been injected. Single step over possible
3185 * problem (IRET or exception injection or interrupt shadow)
3186 */
ab2f4d73 3187 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
6be7d306 3188 svm->nmi_singlestep = true;
44c11430 3189 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
c1150d8c
DL		 3190}
3191
cbc94022
IE		 3192static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3193{
3194 return 0;
3195}
3196
2ac52ab8
SC		 3197static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3198{
3199 return 0;
3200}
3201
f55ac304 3202void svm_flush_tlb(struct kvm_vcpu *vcpu)
d9e368d6 3203{
38e5e92f
JR		 3204 struct vcpu_svm *svm = to_svm(vcpu);
3205
4a41e43c
SC		 3206 /*
3207 * Flush only the current ASID even if the TLB flush was invoked via
3208 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3209 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3210 * unconditionally does a TLB flush on both nested VM-Enter and nested
3211 * VM-Exit (via kvm_mmu_reset_context()).
3212 */
38e5e92f
JR		 3213 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3214 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3215 else
3216 svm->asid_generation--;
d9e368d6
AK		 3217}
3218
faff8758
JS		 3219static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3220{
3221 struct vcpu_svm *svm = to_svm(vcpu);
3222
3223 invlpga(gva, svm->vmcb->control.asid);
3224}
3225
04d2cc77
AK		 3226static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3227{
3228}
3229
d7bf8221
JR		 3230static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3231{
3232 struct vcpu_svm *svm = to_svm(vcpu);
3233
3bbf3565 3234 if (svm_nested_virtualize_tpr(vcpu))
88ab24ad
JR		 3235 return;
3236
4ee546b4 3237 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3238 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3239 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3240 }
3241}
3242
649d6864
JR		 3243static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3244{
3245 struct vcpu_svm *svm = to_svm(vcpu);
3246 u64 cr8;
3247
3bbf3565
SS		 3248 if (svm_nested_virtualize_tpr(vcpu) ||
3249 kvm_vcpu_apicv_active(vcpu))
88ab24ad
JR		 3250 return;
3251
649d6864
JR		 3252 cr8 = kvm_get_cr8(vcpu);
3253 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3254 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3255}
3256
9222be18
GN		 3257static void svm_complete_interrupts(struct vcpu_svm *svm)
3258{
3259 u8 vector;
3260 int type;
3261 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3262 unsigned int3_injected = svm->int3_injected;
3263
3264 svm->int3_injected = 0;
9222be18 3265
bd3d1ec3
AK		 3266 /*
3267 * If we've made progress since setting HF_IRET_MASK, we've
3268 * executed an IRET and can allow NMI injection.
3269 */
3270 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3271 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
44c11430 3272 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3273 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3274 }
44c11430 3275
9222be18
GN		 3276 svm->vcpu.arch.nmi_injected = false;
3277 kvm_clear_exception_queue(&svm->vcpu);
3278 kvm_clear_interrupt_queue(&svm->vcpu);
3279
3280 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3281 return;
3282
3842d135
AK		 3283 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3284
9222be18
GN		 3285 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3286 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3287
3288 switch (type) {
3289 case SVM_EXITINTINFO_TYPE_NMI:
3290 svm->vcpu.arch.nmi_injected = true;
3291 break;
3292 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3293 /*
3294 * In case of software exceptions, do not reinject the vector,
3295 * but re-execute the instruction instead. Rewind RIP first
3296 * if we emulated INT3 before.
3297 */
3298 if (kvm_exception_is_soft(vector)) {
3299 if (vector == BP_VECTOR && int3_injected &&
3300 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3301 kvm_rip_write(&svm->vcpu,
3302 kvm_rip_read(&svm->vcpu) -
3303 int3_injected);
9222be18 3304 break;
66b7138f 3305 }
9222be18
GN		 3306 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3307 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3308 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3309
3310 } else
ce7ddec4 3311 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3312 break;
3313 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3314 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3315 break;
3316 default:
3317 break;
3318 }
3319}
3320
b463a6f7
AK		 3321static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3322{
3323 struct vcpu_svm *svm = to_svm(vcpu);
3324 struct vmcb_control_area *control = &svm->vmcb->control;
3325
3326 control->exit_int_info = control->event_inj;
3327 control->exit_int_info_err = control->event_inj_err;
3328 control->event_inj = 0;
3329 svm_complete_interrupts(svm);
3330}
3331
404d5d7b 3332static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
a9ab13ff
WL		 3333{
3334 if (!is_guest_mode(vcpu) &&
3335 to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3336 to_svm(vcpu)->vmcb->control.exit_info_1)
3337 return handle_fastpath_set_msr_irqoff(vcpu);
3338
3339 return EXIT_FASTPATH_NONE;
3340}
3341
56a87e5d 3342void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
199cd1d7 3343
404d5d7b 3344static fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3345{
404d5d7b 3346 fastpath_t exit_fastpath;
a2fa3e9f 3347 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3348
2041a06a
JR		 3349 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3350 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3351 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3352
a12713c2
LP		 3353 /*
3354 * Disable singlestep if we're injecting an interrupt/exception.
3355 * We don't want our modified rflags to be pushed on the stack where
3356 * we might not be able to easily reset them if we disabled NMI
3357 * singlestep later.
3358 */
3359 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3360 /*
3361 * Event injection happens before external interrupts cause a
3362 * vmexit and interrupts are disabled here, so smp_send_reschedule
3363 * is enough to force an immediate vmexit.
3364 */
3365 disable_nmi_singlestep(svm);
3366 smp_send_reschedule(vcpu->cpu);
3367 }
3368
e756fc62 3369 pre_svm_run(svm);
6aa8b732 3370
649d6864
JR		 3371 sync_lapic_to_cr8(vcpu);
3372
cda0ffdd 3373 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3374
d67668e9
PB		 3375 /*
3376 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3377 * of a #DB.
3378 */
3379 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3380 svm_set_dr6(svm, vcpu->arch.dr6);
3381 else
3382 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3383
04d2cc77 3384 clgi();
139a12cf 3385 kvm_load_guest_xsave_state(vcpu);
04d2cc77 3386
b6c4bc65
WL		 3387 if (lapic_in_kernel(vcpu) &&
3388 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3389 kvm_wait_lapic_expire(vcpu);
3390
b2ac58f9
KA		 3391 /*
3392 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3393 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3394 * is no need to worry about the conditional branch over the wrmsr
3395 * being speculatively taken.
3396 */
ccbcd267 3397 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
b2ac58f9 3398
199cd1d7 3399 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
6aa8b732 3400
15e6c22f
TG		 3401#ifdef CONFIG_X86_64
3402 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3403#else
3404 loadsegment(fs, svm->host.fs);
3405#ifndef CONFIG_X86_32_LAZY_GS
3406 loadsegment(gs, svm->host.gs);
3407#endif
3408#endif
3409
b2ac58f9
KA		 3410 /*
3411 * We do not use IBRS in the kernel. If this vCPU has used the
3412 * SPEC_CTRL MSR it may have left it on; save the value and
3413 * turn it off. This is much more efficient than blindly adding
3414 * it to the atomic save/restore list. Especially as the former
3415 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3416 *
3417 * For non-nested case:
3418 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3419 * save it.
3420 *
3421 * For nested case:
3422 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3423 * save it.
3424 */
946fbbc1 3425 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
ecb586bd 3426 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b2ac58f9 3427
6aa8b732
AK		 3428 reload_tss(vcpu);
3429
024d83ca
TG		 3430 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3431
13c34e07
AK		 3432 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3433 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3434 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3435 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3436
3781c01c 3437 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3438 kvm_before_interrupt(&svm->vcpu);
3781c01c 3439
139a12cf 3440 kvm_load_host_xsave_state(vcpu);
3781c01c
JR		 3441 stgi();
3442
3443 /* Any pending NMI will happen here */
a9ab13ff 3444 exit_fastpath = svm_exit_handlers_fastpath(vcpu);
3781c01c
JR		 3445
3446 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3447 kvm_after_interrupt(&svm->vcpu);
3781c01c 3448
d7bf8221
JR		 3449 sync_cr8_to_lapic(vcpu);
3450
a2fa3e9f 3451 svm->next_rip = 0;
2d8a42be
PB		 3452 if (is_guest_mode(&svm->vcpu)) {
3453 sync_nested_vmcb_control(svm);
3454 svm->nested.nested_run_pending = 0;
3455 }
9222be18 3456
38e5e92f
JR		 3457 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3458
631bc487
GN		 3459 /* if exit due to PF check for async PF */
3460 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
1261bfa3 3461 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
631bc487 3462
6de4f3ad
AK		 3463 if (npt_enabled) {
3464 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3465 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3466 }
fe5913e4
JR		 3467
3468 /*
3469 * We need to handle MC intercepts here before the vcpu has a chance to
3470 * change the physical cpu
3471 */
3472 if (unlikely(svm->vmcb->control.exit_code ==
3473 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3474 svm_handle_mce(svm);
8d28fec4
RJ		 3475
3476 mark_all_clean(svm->vmcb);
a9ab13ff 3477 return exit_fastpath;
6aa8b732
AK		 3478}
3479
727a7e27 3480static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root)
6aa8b732 3481{
a2fa3e9f 3482 struct vcpu_svm *svm = to_svm(vcpu);
689f3bf2 3483 unsigned long cr3;
a2fa3e9f 3484
689f3bf2
PB		 3485 cr3 = __sme_set(root);
3486 if (npt_enabled) {
3487 svm->vmcb->control.nested_cr3 = cr3;
3488 mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0 3489
689f3bf2 3490 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
978ce583
PB		 3491 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3492 return;
3493 cr3 = vcpu->arch.cr3;
689f3bf2 3494 }
1c97f0a0 3495
978ce583
PB		 3496 svm->vmcb->save.cr3 = cr3;
3497 mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0
JR		 3498}
3499
6aa8b732
AK		 3500static int is_disabled(void)
3501{
6031a61c
JR		 3502 u64 vm_cr;
3503
3504 rdmsrl(MSR_VM_CR, vm_cr);
3505 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3506 return 1;
3507
6aa8b732
AK		 3508 return 0;
3509}
3510
102d8325
IM		 3511static void
3512svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3513{
3514 /*
3515 * Patch in the VMMCALL instruction:
3516 */
3517 hypercall[0] = 0x0f;
3518 hypercall[1] = 0x01;
3519 hypercall[2] = 0xd9;
102d8325
IM		 3520}
3521
f257d6dc 3522static int __init svm_check_processor_compat(void)
002c7f7c 3523{
f257d6dc 3524 return 0;
002c7f7c
YS		 3525}
3526
774ead3a
AK		 3527static bool svm_cpu_has_accelerated_tpr(void)
3528{
3529 return false;
3530}
3531
cb97c2d6 3532static bool svm_has_emulated_msr(u32 index)
6d396b55 3533{
e87555e5
VK		 3534 switch (index) {
3535 case MSR_IA32_MCG_EXT_CTL:
95c5c7c7 3536 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
e87555e5
VK		 3537 return false;
3538 default:
3539 break;
3540 }
3541
6d396b55
PB		 3542 return true;
3543}
3544
fc07e76a
PB		 3545static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3546{
3547 return 0;
3548}
3549
0e851880
SY		 3550static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3551{
6092d3d3
JR		 3552 struct vcpu_svm *svm = to_svm(vcpu);
3553
7204160e 3554 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
96be4e06 3555 boot_cpu_has(X86_FEATURE_XSAVE) &&
7204160e
AL		 3556 boot_cpu_has(X86_FEATURE_XSAVES);
3557
6092d3d3 3558 /* Update nrips enabled cache */
4eb87460
SC		 3559 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3560 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
46781eae
SS		 3561
3562 if (!kvm_vcpu_apicv_active(vcpu))
3563 return;
3564
cc7f5577
OU		 3565 /*
3566 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3567 * is exposed to the guest, disable AVIC.
3568 */
3569 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3570 kvm_request_apicv_update(vcpu->kvm, false,
3571 APICV_INHIBIT_REASON_X2APIC);
9a0bf054
SS		 3572
3573 /*
3574 * Currently, AVIC does not work with nested virtualization.
3575 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3576 */
3577 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3578 kvm_request_apicv_update(vcpu->kvm, false,
3579 APICV_INHIBIT_REASON_NESTED);
0e851880
SY		 3580}
3581
f5f48ee1
SY		 3582static bool svm_has_wbinvd_exit(void)
3583{
3584 return true;
3585}
3586
8061252e 3587#define PRE_EX(exit) { .exit_code = (exit), \
40e19b51 3588 .stage = X86_ICPT_PRE_EXCEPT, }
cfec82cb 3589#define POST_EX(exit) { .exit_code = (exit), \
40e19b51 3590 .stage = X86_ICPT_POST_EXCEPT, }
d7eb8203 3591#define POST_MEM(exit) { .exit_code = (exit), \
40e19b51 3592 .stage = X86_ICPT_POST_MEMACCESS, }
cfec82cb 3593
09941fbb 3594static const struct __x86_intercept {
cfec82cb
JR		 3595 u32 exit_code;
3596 enum x86_intercept_stage stage;
cfec82cb
JR		 3597} x86_intercept_map[] = {
3598 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3599 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3600 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3601 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3602 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3b88e41a
JR		 3603 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3604 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
dee6bb70
JR		 3605 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3606 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3607 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3608 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3609 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3610 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3611 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3612 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
01de8b09
JR		 3613 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3614 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3615 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3616 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3617 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3618 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3619 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3620 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
d7eb8203
JR		 3621 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3622 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3623 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
8061252e
JR		 3624 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3625 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3626 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3627 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3628 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3629 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3630 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3631 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3632 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
bf608f88
JR		 3633 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3634 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3635 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3636 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3637 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3638 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3639 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
f6511935
JR		 3640 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3641 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3642 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3643 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
02d4160f 3644 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
cfec82cb
JR		 3645};
3646
8061252e 3647#undef PRE_EX
cfec82cb 3648#undef POST_EX
d7eb8203 3649#undef POST_MEM
cfec82cb 3650
8a76d7f2
JR		 3651static int svm_check_intercept(struct kvm_vcpu *vcpu,
3652 struct x86_instruction_info *info,
21f1b8f2
SC		 3653 enum x86_intercept_stage stage,
3654 struct x86_exception *exception)
8a76d7f2 3655{
cfec82cb
JR		 3656 struct vcpu_svm *svm = to_svm(vcpu);
3657 int vmexit, ret = X86EMUL_CONTINUE;
3658 struct __x86_intercept icpt_info;
3659 struct vmcb *vmcb = svm->vmcb;
3660
3661 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3662 goto out;
3663
3664 icpt_info = x86_intercept_map[info->intercept];
3665
40e19b51 3666 if (stage != icpt_info.stage)
cfec82cb
JR		 3667 goto out;
3668
3669 switch (icpt_info.exit_code) {
3670 case SVM_EXIT_READ_CR0:
3671 if (info->intercept == x86_intercept_cr_read)
3672 icpt_info.exit_code += info->modrm_reg;
3673 break;
3674 case SVM_EXIT_WRITE_CR0: {
3675 unsigned long cr0, val;
3676 u64 intercept;
3677
3678 if (info->intercept == x86_intercept_cr_write)
3679 icpt_info.exit_code += info->modrm_reg;
3680
62baf44c
JK		 3681 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3682 info->intercept == x86_intercept_clts)
cfec82cb
JR		 3683 break;
3684
e670bf68 3685 intercept = svm->nested.ctl.intercept;
cfec82cb
JR		 3686
3687 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3688 break;
3689
3690 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3691 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3692
3693 if (info->intercept == x86_intercept_lmsw) {
3694 cr0 &= 0xfUL;
3695 val &= 0xfUL;
3696 /* lmsw can't clear PE - catch this here */
3697 if (cr0 & X86_CR0_PE)
3698 val |= X86_CR0_PE;
3699 }
3700
3701 if (cr0 ^ val)
3702 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3703
3704 break;
3705 }
3b88e41a
JR		 3706 case SVM_EXIT_READ_DR0:
3707 case SVM_EXIT_WRITE_DR0:
3708 icpt_info.exit_code += info->modrm_reg;
3709 break;
8061252e
JR		 3710 case SVM_EXIT_MSR:
3711 if (info->intercept == x86_intercept_wrmsr)
3712 vmcb->control.exit_info_1 = 1;
3713 else
3714 vmcb->control.exit_info_1 = 0;
3715 break;
bf608f88
JR		 3716 case SVM_EXIT_PAUSE:
3717 /*
3718 * We get this for NOP only, but pause
3719 * is rep not, check this here
3720 */
3721 if (info->rep_prefix != REPE_PREFIX)
3722 goto out;
49a8afca 3723 break;
f6511935
JR		 3724 case SVM_EXIT_IOIO: {
3725 u64 exit_info;
3726 u32 bytes;
3727
f6511935
JR		 3728 if (info->intercept == x86_intercept_in ||
3729 info->intercept == x86_intercept_ins) {
6cbc5f5a
JK		 3730 exit_info = ((info->src_val & 0xffff) << 16) |
3731 SVM_IOIO_TYPE_MASK;
f6511935 3732 bytes = info->dst_bytes;
6493f157 3733 } else {
6cbc5f5a 3734 exit_info = (info->dst_val & 0xffff) << 16;
6493f157 3735 bytes = info->src_bytes;
f6511935
JR		 3736 }
3737
3738 if (info->intercept == x86_intercept_outs ||
3739 info->intercept == x86_intercept_ins)
3740 exit_info |= SVM_IOIO_STR_MASK;
3741
3742 if (info->rep_prefix)
3743 exit_info |= SVM_IOIO_REP_MASK;
3744
3745 bytes = min(bytes, 4u);
3746
3747 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3748
3749 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3750
3751 vmcb->control.exit_info_1 = exit_info;
3752 vmcb->control.exit_info_2 = info->next_rip;
3753
3754 break;
3755 }
cfec82cb
JR		 3756 default:
3757 break;
3758 }
3759
f104765b
BD		 3760 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3761 if (static_cpu_has(X86_FEATURE_NRIPS))
3762 vmcb->control.next_rip = info->next_rip;
cfec82cb
JR		 3763 vmcb->control.exit_code = icpt_info.exit_code;
3764 vmexit = nested_svm_exit_handled(svm);
3765
3766 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3767 : X86EMUL_CONTINUE;
3768
3769out:
3770 return ret;
8a76d7f2
JR		 3771}
3772
a9ab13ff 3773static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
a547c6db 3774{
a547c6db
YZ		 3775}
3776
ae97a3b8
RK		 3777static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3778{
8566ac8b
BM		 3779 if (pause_filter_thresh)
3780 shrink_ple_window(vcpu);
ae97a3b8
RK		 3781}
3782
74f16909
BP		 3783static void svm_setup_mce(struct kvm_vcpu *vcpu)
3784{
3785 /* [63:9] are reserved. */
3786 vcpu->arch.mcg_cap &= 0x1ff;
3787}
3788
cae96af1 3789bool svm_smi_blocked(struct kvm_vcpu *vcpu)
72d7b374 3790{
05cade71
LP		 3791 struct vcpu_svm *svm = to_svm(vcpu);
3792
3793 /* Per APM Vol.2 15.22.2 "Response to SMI" */
3794 if (!gif_set(svm))
cae96af1
PB		 3795 return true;
3796
3797 return is_smm(vcpu);
3798}
3799
c9d40913 3800static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3801{
3802 struct vcpu_svm *svm = to_svm(vcpu);
3803 if (svm->nested.nested_run_pending)
c9d40913 3804 return -EBUSY;
05cade71 3805
c300ab9f
PB		 3806 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
3807 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
c9d40913 3808 return -EBUSY;
c300ab9f 3809
cae96af1 3810 return !svm_smi_blocked(vcpu);
72d7b374
LP		 3811}
3812
0234bf88
LP		 3813static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3814{
05cade71
LP		 3815 struct vcpu_svm *svm = to_svm(vcpu);
3816 int ret;
3817
3818 if (is_guest_mode(vcpu)) {
3819 /* FED8h - SVM Guest */
3820 put_smstate(u64, smstate, 0x7ed8, 1);
3821 /* FEE0h - SVM Guest VMCB Physical Address */
3822 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3823
3824 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3825 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3826 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3827
3828 ret = nested_svm_vmexit(svm);
3829 if (ret)
3830 return ret;
3831 }
0234bf88
LP		 3832 return 0;
3833}
3834
ed19321f 3835static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 3836{
05cade71
LP		 3837 struct vcpu_svm *svm = to_svm(vcpu);
3838 struct vmcb *nested_vmcb;
8c5fbf1a 3839 struct kvm_host_map map;
ed19321f
SC		 3840 u64 guest;
3841 u64 vmcb;
05cade71 3842
ed19321f
SC		 3843 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3844 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
05cade71 3845
ed19321f 3846 if (guest) {
8c5fbf1a 3847 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
9ec19493 3848 return 1;
8c5fbf1a 3849 nested_vmcb = map.hva;
69c9dfa2
PB		 3850 enter_svm_guest_mode(svm, vmcb, nested_vmcb);
3851 kvm_vcpu_unmap(&svm->vcpu, &map, true);
05cade71 3852 }
9ec19493 3853 return 0;
0234bf88
LP		 3854}
3855
c9d40913 3856static void enable_smi_window(struct kvm_vcpu *vcpu)
cc3d967f
LP		 3857{
3858 struct vcpu_svm *svm = to_svm(vcpu);
3859
3860 if (!gif_set(svm)) {
3861 if (vgif_enabled(svm))
3862 set_intercept(svm, INTERCEPT_STGI);
3863 /* STGI will cause a vm exit */
c9d40913
PB		 3864 } else {
3865 /* We must be in SMM; RSM will cause a vmexit anyway. */
cc3d967f 3866 }
cc3d967f
LP		 3867}
3868
05d5a486
SB		 3869static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3870{
118154bd
LA		 3871 unsigned long cr4 = kvm_read_cr4(vcpu);
3872 bool smep = cr4 & X86_CR4_SMEP;
3873 bool smap = cr4 & X86_CR4_SMAP;
3874 bool is_user = svm_get_cpl(vcpu) == 3;
05d5a486 3875
e72436bc
PB		 3876 /*
3877 * If RIP is invalid, go ahead with emulation which will cause an
3878 * internal error exit.
3879 */
3880 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3881 return true;
3882
05d5a486 3883 /*
118154bd
LA		 3884 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3885 *
3886 * Errata:
3887 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3888 * possible that CPU microcode implementing DecodeAssist will fail
3889 * to read bytes of instruction which caused #NPF. In this case,
3890 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3891 * return 0 instead of the correct guest instruction bytes.
3892 *
3893 * This happens because CPU microcode reading instruction bytes
3894 * uses a special opcode which attempts to read data using CPL=0
3895 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3896 * fault, it gives up and returns no instruction bytes.
3897 *
3898 * Detection:
3899 * We reach here in case CPU supports DecodeAssist, raised #NPF and
3900 * returned 0 in GuestIntrBytes field of the VMCB.
3901 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3902 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3903 * in case vCPU CPL==3 (Because otherwise guest would have triggered
3904 * a SMEP fault instead of #NPF).
3905 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3906 * As most guests enable SMAP if they have also enabled SMEP, use above
3907 * logic in order to attempt minimize false-positive of detecting errata
3908 * while still preserving all cases semantic correctness.
3909 *
3910 * Workaround:
3911 * To determine what instruction the guest was executing, the hypervisor
3912 * will have to decode the instruction at the instruction pointer.
05d5a486
SB		 3913 *
3914 * In non SEV guest, hypervisor will be able to read the guest
3915 * memory to decode the instruction pointer when insn_len is zero
3916 * so we return true to indicate that decoding is possible.
3917 *
3918 * But in the SEV guest, the guest memory is encrypted with the
3919 * guest specific key and hypervisor will not be able to decode the
3920 * instruction pointer so we will not able to workaround it. Lets
3921 * print the error and request to kill the guest.
3922 */
118154bd 3923 if (smap && (!smep || is_user)) {
05d5a486
SB		 3924 if (!sev_guest(vcpu->kvm))
3925 return true;
3926
118154bd 3927 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
05d5a486
SB		 3928 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3929 }
3930
3931 return false;
3932}
3933
4b9852f4
LA		 3934static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
3935{
3936 struct vcpu_svm *svm = to_svm(vcpu);
3937
3938 /*
3939 * TODO: Last condition latch INIT signals on vCPU when
3940 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
33b22172
PB		 3941 * To properly emulate the INIT intercept,
3942 * svm_check_nested_events() should call nested_svm_vmexit()
3943 * if an INIT signal is pending.
4b9852f4
LA		 3944 */
3945 return !gif_set(svm) ||
3946 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
3947}
3948
eaf78265
JR		 3949static void svm_vm_destroy(struct kvm *kvm)
3950{
3951 avic_vm_destroy(kvm);
3952 sev_vm_destroy(kvm);
3953}
3954
3955static int svm_vm_init(struct kvm *kvm)
3956{
3957 if (avic) {
3958 int ret = avic_vm_init(kvm);
3959 if (ret)
3960 return ret;
3961 }
3962
3963 kvm_apicv_init(kvm, avic);
3964 return 0;
3965}
3966
9c14ee21 3967static struct kvm_x86_ops svm_x86_ops __initdata = {
dd58f3c9 3968 .hardware_unsetup = svm_hardware_teardown,
6aa8b732
AK		 3969 .hardware_enable = svm_hardware_enable,
3970 .hardware_disable = svm_hardware_disable,
774ead3a 3971 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
bc226f07 3972 .has_emulated_msr = svm_has_emulated_msr,
6aa8b732
AK		 3973
3974 .vcpu_create = svm_create_vcpu,
3975 .vcpu_free = svm_free_vcpu,
04d2cc77 3976 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3977
562b6b08 3978 .vm_size = sizeof(struct kvm_svm),
4e19c36f 3979 .vm_init = svm_vm_init,
1654efcb 3980 .vm_destroy = svm_vm_destroy,
44a95dae 3981
04d2cc77 3982 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3983 .vcpu_load = svm_vcpu_load,
3984 .vcpu_put = svm_vcpu_put,
8221c137
SS		 3985 .vcpu_blocking = svm_vcpu_blocking,
3986 .vcpu_unblocking = svm_vcpu_unblocking,
6aa8b732 3987
a96036b8 3988 .update_bp_intercept = update_bp_intercept,
801e459a 3989 .get_msr_feature = svm_get_msr_feature,
6aa8b732
AK		 3990 .get_msr = svm_get_msr,
3991 .set_msr = svm_set_msr,
3992 .get_segment_base = svm_get_segment_base,
3993 .get_segment = svm_get_segment,
3994 .set_segment = svm_set_segment,
2e4d2653 3995 .get_cpl = svm_get_cpl,
1747fb71 3996 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
6aa8b732 3997 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3998 .set_cr4 = svm_set_cr4,
3999 .set_efer = svm_set_efer,
4000 .get_idt = svm_get_idt,
4001 .set_idt = svm_set_idt,
4002 .get_gdt = svm_get_gdt,
4003 .set_gdt = svm_set_gdt,
020df079 4004 .set_dr7 = svm_set_dr7,
facb0139 4005 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
6de4f3ad 4006 .cache_reg = svm_cache_reg,
6aa8b732
AK		 4007 .get_rflags = svm_get_rflags,
4008 .set_rflags = svm_set_rflags,
be94f6b7 4009
7780938c 4010 .tlb_flush_all = svm_flush_tlb,
eeeb4f67 4011 .tlb_flush_current = svm_flush_tlb,
faff8758 4012 .tlb_flush_gva = svm_flush_tlb_gva,
72b38320 4013 .tlb_flush_guest = svm_flush_tlb,
6aa8b732 4014
6aa8b732 4015 .run = svm_vcpu_run,
04d2cc77 4016 .handle_exit = handle_exit,
6aa8b732 4017 .skip_emulated_instruction = skip_emulated_instruction,
5ef8acbd 4018 .update_emulated_instruction = NULL,
2809f5d2
GC		 4019 .set_interrupt_shadow = svm_set_interrupt_shadow,
4020 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 4021 .patch_hypercall = svm_patch_hypercall,
2a8067f1 4022 .set_irq = svm_set_irq,
95ba8273 4023 .set_nmi = svm_inject_nmi,
298101da 4024 .queue_exception = svm_queue_exception,
b463a6f7 4025 .cancel_injection = svm_cancel_injection,
78646121 4026 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 4027 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 4028 .get_nmi_mask = svm_get_nmi_mask,
4029 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 4030 .enable_nmi_window = enable_nmi_window,
4031 .enable_irq_window = enable_irq_window,
4032 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 4033 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
d62caabb 4034 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
ef8efd7a 4035 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
2de9d0cc 4036 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
c7c9c56c 4037 .load_eoi_exitmap = svm_load_eoi_exitmap,
44a95dae
SS		 4038 .hwapic_irr_update = svm_hwapic_irr_update,
4039 .hwapic_isr_update = svm_hwapic_isr_update,
fa59cc00 4040 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
be8ca170 4041 .apicv_post_state_restore = avic_post_state_restore,
cbc94022
IE		 4042
4043 .set_tss_addr = svm_set_tss_addr,
2ac52ab8 4044 .set_identity_map_addr = svm_set_identity_map_addr,
67253af5 4045 .get_tdp_level = get_npt_level,
4b12f0de 4046 .get_mt_mask = svm_get_mt_mask,
229456fc 4047
586f9607 4048 .get_exit_info = svm_get_exit_info,
586f9607 4049
0e851880 4050 .cpuid_update = svm_cpuid_update,
4e47c7a6 4051
f5f48ee1 4052 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a 4053
326e7425 4054 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
1c97f0a0 4055
727a7e27 4056 .load_mmu_pgd = svm_load_mmu_pgd,
8a76d7f2
JR		 4057
4058 .check_intercept = svm_check_intercept,
95b5a48c 4059 .handle_exit_irqoff = svm_handle_exit_irqoff,
ae97a3b8 4060
d264ee0c
SC		 4061 .request_immediate_exit = __kvm_request_immediate_exit,
4062
ae97a3b8 4063 .sched_in = svm_sched_in,
25462f7f
WH		 4064
4065 .pmu_ops = &amd_pmu_ops,
33b22172
PB		 4066 .nested_ops = &svm_nested_ops,
4067
340d3bc3 4068 .deliver_posted_interrupt = svm_deliver_avic_intr,
17e433b5 4069 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
411b44ba 4070 .update_pi_irte = svm_update_pi_irte,
74f16909 4071 .setup_mce = svm_setup_mce,
0234bf88 4072
72d7b374 4073 .smi_allowed = svm_smi_allowed,
0234bf88
LP		 4074 .pre_enter_smm = svm_pre_enter_smm,
4075 .pre_leave_smm = svm_pre_leave_smm,
cc3d967f 4076 .enable_smi_window = enable_smi_window,
1654efcb
BS		 4077
4078 .mem_enc_op = svm_mem_enc_op,
1e80fdc0
BS		 4079 .mem_enc_reg_region = svm_register_enc_region,
4080 .mem_enc_unreg_region = svm_unregister_enc_region,
57b119da 4081
05d5a486 4082 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4b9852f4
LA		 4083
4084 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
6aa8b732
AK		 4085};
4086
d008dfdb
SC		 4087static struct kvm_x86_init_ops svm_init_ops __initdata = {
4088 .cpu_has_kvm_support = has_svm,
4089 .disabled_by_bios = is_disabled,
4090 .hardware_setup = svm_hardware_setup,
4091 .check_processor_compatibility = svm_check_processor_compat,
4092
4093 .runtime_ops = &svm_x86_ops,
6aa8b732
AK		 4094};
4095
4096static int __init svm_init(void)
4097{
d008dfdb 4098 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
0ee75bea 4099 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 4100}
4101
4102static void __exit svm_exit(void)
4103{
cb498ea2 4104 kvm_exit();
6aa8b732
AK		 4105}
4106
4107module_init(svm_init)
4108module_exit(svm_exit)
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