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KVM: nSVM: reset nested_run_pending upon nested_svm_vmrun_msrpm() failure
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / svm / svm.c
CommitLineData
44a95dae
SS		 1#define pr_fmt(fmt) "SVM: " fmt
2
edf88417
AK		 3#include <linux/kvm_host.h>
4
85f455f7 5#include "irq.h"
1d737c8a 6#include "mmu.h"
5fdbf976 7#include "kvm_cache_regs.h"
fe4c7b19 8#include "x86.h"
66f7b72e 9#include "cpuid.h"
25462f7f 10#include "pmu.h"
e495606d 11
6aa8b732 12#include <linux/module.h>
ae759544 13#include <linux/mod_devicetable.h>
9d8f549d 14#include <linux/kernel.h>
6aa8b732
AK		 15#include <linux/vmalloc.h>
16#include <linux/highmem.h>
ef0f6496 17#include <linux/amd-iommu.h>
e8edc6e0 18#include <linux/sched.h>
af658dca 19#include <linux/trace_events.h>
5a0e3ad6 20#include <linux/slab.h>
5881f737 21#include <linux/hashtable.h>
c207aee4 22#include <linux/frame.h>
e9df0942 23#include <linux/psp-sev.h>
1654efcb 24#include <linux/file.h>
89c50580
BS		 25#include <linux/pagemap.h>
26#include <linux/swap.h>
33af3a7e 27#include <linux/rwsem.h>
6aa8b732 28
8221c137 29#include <asm/apic.h>
1018faa6 30#include <asm/perf_event.h>
67ec6607 31#include <asm/tlbflush.h>
e495606d 32#include <asm/desc.h>
facb0139 33#include <asm/debugreg.h>
631bc487 34#include <asm/kvm_para.h>
411b44ba 35#include <asm/irq_remapping.h>
1c164cb3 36#include <asm/mce.h>
28a27752 37#include <asm/spec-ctrl.h>
ba5bade4 38#include <asm/cpu_device_id.h>
6aa8b732 39
63d1142f 40#include <asm/virtext.h>
229456fc 41#include "trace.h"
63d1142f 42
883b0a91
JR		 43#include "svm.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
575b255c 50#ifdef MODULE
ae759544 51static const struct x86_cpu_id svm_cpu_id[] = {
320debe5 52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
ae759544
JT		 53 {}
54};
55MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
575b255c 56#endif
ae759544 57
6aa8b732
AK		 58#define IOPM_ALLOC_ORDER 2
59#define MSRPM_ALLOC_ORDER 1
60
6aa8b732
AK		 61#define SEG_TYPE_LDT 2
62#define SEG_TYPE_BUSY_TSS16 3
63
6bc31bdc
AP		 64#define SVM_FEATURE_LBRV (1 << 1)
65#define SVM_FEATURE_SVML (1 << 2)
ddce97aa
AP		 66#define SVM_FEATURE_TSC_RATE (1 << 4)
67#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68#define SVM_FEATURE_FLUSH_ASID (1 << 6)
69#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
6bc31bdc 70#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 71
24e09cbf
JR		 72#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73
fbc0db76 74#define TSC_RATIO_RSVD 0xffffff0000000000ULL
92a1f12d
JR		 75#define TSC_RATIO_MIN 0x0000000000000001ULL
76#define TSC_RATIO_MAX 0x000000ffffffffffULL
fbc0db76 77
67ec6607
JR		 78static bool erratum_383_found __read_mostly;
79
883b0a91 80u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
323c3d80 81
2b036c6b
BO		 82/*
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
85 */
86static uint64_t osvw_len = 4, osvw_status;
87
fbc0db76
JR		 88static DEFINE_PER_CPU(u64, current_tsc_ratio);
89#define TSC_RATIO_DEFAULT 0x0100000000ULL
90
09941fbb 91static const struct svm_direct_access_msrs {
ac72a9b7
JR		 92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94} direct_access_msrs[] = {
8c06585d 95 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
97#ifdef CONFIG_X86_64
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
104#endif
b2ac58f9 105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
15d45071 106 { .index = MSR_IA32_PRED_CMD, .always = false },
ac72a9b7
JR		 107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
883b0a91 116bool npt_enabled = true;
709ddebf 117#else
883b0a91 118bool npt_enabled;
709ddebf 119#endif
6c7dac72 120
8566ac8b
BM		 121/*
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
131 *
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
148 * count only mode.
149 */
150
151static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152module_param(pause_filter_thresh, ushort, 0444);
153
154static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155module_param(pause_filter_count, ushort, 0444);
156
157/* Default doubles per-vcpu window every exit. */
158static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159module_param(pause_filter_count_grow, ushort, 0444);
160
161/* Default resets per-vcpu window every exit to pause_filter_count. */
162static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163module_param(pause_filter_count_shrink, ushort, 0444);
164
165/* Default is to compute the maximum so we can never overflow. */
166static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167module_param(pause_filter_count_max, ushort, 0444);
168
e2358851
DB		 169/* allow nested paging (virtualized MMU) for all guests */
170static int npt = true;
6c7dac72 171module_param(npt, int, S_IRUGO);
e3da3acd 172
e2358851
DB		 173/* allow nested virtualization in KVM/SVM */
174static int nested = true;
236de055
AG		 175module_param(nested, int, S_IRUGO);
176
d647eb63
PB		 177/* enable/disable Next RIP Save */
178static int nrips = true;
179module_param(nrips, int, 0444);
180
89c8a498
JN		 181/* enable/disable Virtual VMLOAD VMSAVE */
182static int vls = true;
183module_param(vls, int, 0444);
184
640bd6e5
JN		 185/* enable/disable Virtual GIF */
186static int vgif = true;
187module_param(vgif, int, 0444);
5ea11f2b 188
e9df0942
BS		 189/* enable/disable SEV support */
190static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191module_param(sev, int, 0444);
192
6f2f8453
PB		 193static bool __read_mostly dump_invalid_vmcb = 0;
194module_param(dump_invalid_vmcb, bool, 0644);
195
7607b717
BS		 196static u8 rsm_ins_bytes[] = "\x0f\xaa";
197
a5c3832d 198static void svm_complete_interrupts(struct vcpu_svm *svm);
44a95dae 199
4866d5e3 200static unsigned long iopm_base;
6aa8b732
AK		 201
202struct kvm_ldttss_desc {
203 u16 limit0;
204 u16 base0;
e0231715
JR		 205 unsigned base1:8, type:5, dpl:2, p:1;
206 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 207 u32 base3;
208 u32 zero1;
209} __attribute__((packed));
210
eaf78265 211DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
6aa8b732 212
09941fbb 213static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
6aa8b732 214
9d8f549d 215#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 216#define MSRS_RANGE_SIZE 2048
217#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
218
883b0a91 219u32 svm_msrpm_offset(u32 msr)
455716fa
JR		 220{
221 u32 offset;
222 int i;
223
224 for (i = 0; i < NUM_MSR_MAPS; i++) {
225 if (msr < msrpm_ranges[i] ||
226 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
227 continue;
228
229 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
230 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
231
232 /* Now we have the u8 offset - but need the u32 offset */
233 return offset / 4;
234 }
235
236 /* MSR not in any range */
237 return MSR_INVALID;
238}
239
6aa8b732
AK		 240#define MAX_INST_SIZE 15
241
6aa8b732
AK		 242static inline void clgi(void)
243{
ac5ffda2 244 asm volatile (__ex("clgi"));
6aa8b732
AK		 245}
246
247static inline void stgi(void)
248{
ac5ffda2 249 asm volatile (__ex("stgi"));
6aa8b732
AK		 250}
251
252static inline void invlpga(unsigned long addr, u32 asid)
253{
ac5ffda2 254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
6aa8b732
AK		 255}
256
855feb67 257static int get_npt_level(struct kvm_vcpu *vcpu)
4b16184c
JR		 258{
259#ifdef CONFIG_X86_64
2a7266a8 260 return PT64_ROOT_4LEVEL;
4b16184c
JR		 261#else
262 return PT32E_ROOT_LEVEL;
263#endif
264}
265
883b0a91 266void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
6aa8b732 267{
c513f484 268 struct vcpu_svm *svm = to_svm(vcpu);
6dc696d4 269 vcpu->arch.efer = efer;
9167ab79
PB		 270
271 if (!npt_enabled) {
272 /* Shadow paging assumes NX to be available. */
273 efer |= EFER_NX;
274
275 if (!(efer & EFER_LMA))
276 efer &= ~EFER_LME;
277 }
6aa8b732 278
c513f484
PB		 279 if (!(efer & EFER_SVME)) {
280 svm_leave_nested(svm);
281 svm_set_gif(svm, true);
282 }
283
284 svm->vmcb->save.efer = efer | EFER_SVME;
06e7852c 285 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
6aa8b732
AK		 286}
287
6aa8b732
AK		 288static int is_external_interrupt(u32 info)
289{
290 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
291 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
292}
293
37ccdcbe 294static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 295{
296 struct vcpu_svm *svm = to_svm(vcpu);
297 u32 ret = 0;
298
299 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
37ccdcbe
PB		 300 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
301 return ret;
2809f5d2
GC		 302}
303
304static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
305{
306 struct vcpu_svm *svm = to_svm(vcpu);
307
308 if (mask == 0)
309 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
310 else
311 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
312
313}
314
f8ea7c60 315static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732 316{
a2fa3e9f
GH		 317 struct vcpu_svm *svm = to_svm(vcpu);
318
d647eb63 319 if (nrips && svm->vmcb->control.next_rip != 0) {
d2922422 320 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
6bc31bdc 321 svm->next_rip = svm->vmcb->control.next_rip;
f104765b 322 }
6bc31bdc 323
1957aa63
SC		 324 if (!svm->next_rip) {
325 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
326 return 0;
327 } else {
1957aa63
SC		 328 kvm_rip_write(vcpu, svm->next_rip);
329 }
2809f5d2 330 svm_set_interrupt_shadow(vcpu, 0);
f8ea7c60 331
60fc3d02 332 return 1;
6aa8b732
AK		 333}
334
cfcd20e5 335static void svm_queue_exception(struct kvm_vcpu *vcpu)
116a4752
JK		 336{
337 struct vcpu_svm *svm = to_svm(vcpu);
cfcd20e5
WL		 338 unsigned nr = vcpu->arch.exception.nr;
339 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 340 u32 error_code = vcpu->arch.exception.error_code;
116a4752 341
da998b46
JM		 342 kvm_deliver_exception_payload(&svm->vcpu);
343
d647eb63 344 if (nr == BP_VECTOR && !nrips) {
66b7138f
JK		 345 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
346
347 /*
348 * For guest debugging where we have to reinject #BP if some
349 * INT3 is guest-owned:
350 * Emulate nRIP by moving RIP forward. Will fail if injection
351 * raises a fault that is not intercepted. Still better than
352 * failing in all cases.
353 */
f8ea7c60 354 (void)skip_emulated_instruction(&svm->vcpu);
66b7138f
JK		 355 rip = kvm_rip_read(&svm->vcpu);
356 svm->int3_rip = rip + svm->vmcb->save.cs.base;
357 svm->int3_injected = rip - old_rip;
358 }
359
116a4752
JK		 360 svm->vmcb->control.event_inj = nr
361 | SVM_EVTINJ_VALID
362 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
363 | SVM_EVTINJ_TYPE_EXEPT;
364 svm->vmcb->control.event_inj_err = error_code;
365}
366
67ec6607
JR		 367static void svm_init_erratum_383(void)
368{
369 u32 low, high;
370 int err;
371 u64 val;
372
e6ee94d5 373 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
67ec6607
JR		 374 return;
375
376 /* Use _safe variants to not break nested virtualization */
377 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
378 if (err)
379 return;
380
381 val |= (1ULL << 47);
382
383 low = lower_32_bits(val);
384 high = upper_32_bits(val);
385
386 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
387
388 erratum_383_found = true;
389}
390
2b036c6b
BO		 391static void svm_init_osvw(struct kvm_vcpu *vcpu)
392{
393 /*
394 * Guests should see errata 400 and 415 as fixed (assuming that
395 * HLT and IO instructions are intercepted).
396 */
397 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
398 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
399
400 /*
401 * By increasing VCPU's osvw.length to 3 we are telling the guest that
402 * all osvw.status bits inside that length, including bit 0 (which is
403 * reserved for erratum 298), are valid. However, if host processor's
404 * osvw_len is 0 then osvw_status[0] carries no information. We need to
405 * be conservative here and therefore we tell the guest that erratum 298
406 * is present (because we really don't know).
407 */
408 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
409 vcpu->arch.osvw.status |= 1;
410}
411
6aa8b732
AK		 412static int has_svm(void)
413{
63d1142f 414 const char *msg;
6aa8b732 415
63d1142f 416 if (!cpu_has_svm(&msg)) {
ff81ff10 417 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 418 return 0;
419 }
420
6aa8b732
AK		 421 return 1;
422}
423
13a34e06 424static void svm_hardware_disable(void)
6aa8b732 425{
fbc0db76
JR		 426 /* Make sure we clean up behind us */
427 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
428 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
429
2c8dceeb 430 cpu_svm_disable();
1018faa6
JR		 431
432 amd_pmu_disable_virt();
6aa8b732
AK		 433}
434
13a34e06 435static int svm_hardware_enable(void)
6aa8b732
AK		 436{
437
0fe1e009 438 struct svm_cpu_data *sd;
6aa8b732 439 uint64_t efer;
6aa8b732
AK		 440 struct desc_struct *gdt;
441 int me = raw_smp_processor_id();
442
10474ae8
AG		 443 rdmsrl(MSR_EFER, efer);
444 if (efer & EFER_SVME)
445 return -EBUSY;
446
6aa8b732 447 if (!has_svm()) {
1f5b77f5 448 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
10474ae8 449 return -EINVAL;
6aa8b732 450 }
0fe1e009 451 sd = per_cpu(svm_data, me);
0fe1e009 452 if (!sd) {
1f5b77f5 453 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
10474ae8 454 return -EINVAL;
6aa8b732
AK		 455 }
456
0fe1e009
TH		 457 sd->asid_generation = 1;
458 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
459 sd->next_asid = sd->max_asid + 1;
ed3cd233 460 sd->min_asid = max_sev_asid + 1;
6aa8b732 461
45fc8757 462 gdt = get_current_gdt_rw();
0fe1e009 463 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 464
9962d032 465 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 466
d0316554 467 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 468
fbc0db76
JR		 469 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
470 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
89cbc767 471 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
fbc0db76
JR		 472 }
473
2b036c6b
BO		 474
475 /*
476 * Get OSVW bits.
477 *
478 * Note that it is possible to have a system with mixed processor
479 * revisions and therefore different OSVW bits. If bits are not the same
480 * on different processors then choose the worst case (i.e. if erratum
481 * is present on one processor and not on another then assume that the
482 * erratum is present everywhere).
483 */
484 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
485 uint64_t len, status = 0;
486 int err;
487
488 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
489 if (!err)
490 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
491 &err);
492
493 if (err)
494 osvw_status = osvw_len = 0;
495 else {
496 if (len < osvw_len)
497 osvw_len = len;
498 osvw_status |= status;
499 osvw_status &= (1ULL << osvw_len) - 1;
500 }
501 } else
502 osvw_status = osvw_len = 0;
503
67ec6607
JR		 504 svm_init_erratum_383();
505
1018faa6
JR		 506 amd_pmu_enable_virt();
507
10474ae8 508 return 0;
6aa8b732
AK		 509}
510
0da1db75
JR		 511static void svm_cpu_uninit(int cpu)
512{
0fe1e009 513 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 514
0fe1e009 515 if (!sd)
0da1db75
JR		 516 return;
517
518 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
70cd94e6 519 kfree(sd->sev_vmcbs);
0fe1e009
TH		 520 __free_page(sd->save_area);
521 kfree(sd);
0da1db75
JR		 522}
523
6aa8b732
AK		 524static int svm_cpu_init(int cpu)
525{
0fe1e009 526 struct svm_cpu_data *sd;
6aa8b732 527
0fe1e009
TH		 528 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
529 if (!sd)
6aa8b732 530 return -ENOMEM;
0fe1e009 531 sd->cpu = cpu;
70cd94e6 532 sd->save_area = alloc_page(GFP_KERNEL);
0fe1e009 533 if (!sd->save_area)
d80b64ff 534 goto free_cpu_data;
6aa8b732 535
70cd94e6 536 if (svm_sev_enabled()) {
6da2ec56
KC		 537 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
538 sizeof(void *),
539 GFP_KERNEL);
70cd94e6 540 if (!sd->sev_vmcbs)
d80b64ff 541 goto free_save_area;
70cd94e6
BS		 542 }
543
0fe1e009 544 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 545
546 return 0;
547
d80b64ff
ML		 548free_save_area:
549 __free_page(sd->save_area);
550free_cpu_data:
0fe1e009 551 kfree(sd);
d80b64ff 552 return -ENOMEM;
6aa8b732
AK		 553
554}
555
ac72a9b7
JR		 556static bool valid_msr_intercept(u32 index)
557{
558 int i;
559
560 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
561 if (direct_access_msrs[i].index == index)
562 return true;
563
564 return false;
565}
566
b2ac58f9
KA		 567static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
568{
569 u8 bit_write;
570 unsigned long tmp;
571 u32 offset;
572 u32 *msrpm;
573
574 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
575 to_svm(vcpu)->msrpm;
576
577 offset = svm_msrpm_offset(msr);
578 bit_write = 2 * (msr & 0x0f) + 1;
579 tmp = msrpm[offset];
580
581 BUG_ON(offset == MSR_INVALID);
582
583 return !!test_bit(bit_write, &tmp);
584}
585
bfc733a7
RR		 586static void set_msr_interception(u32 *msrpm, unsigned msr,
587 int read, int write)
6aa8b732 588{
455716fa
JR		 589 u8 bit_read, bit_write;
590 unsigned long tmp;
591 u32 offset;
6aa8b732 592
ac72a9b7
JR		 593 /*
594 * If this warning triggers extend the direct_access_msrs list at the
595 * beginning of the file
596 */
597 WARN_ON(!valid_msr_intercept(msr));
598
455716fa
JR		 599 offset = svm_msrpm_offset(msr);
600 bit_read = 2 * (msr & 0x0f);
601 bit_write = 2 * (msr & 0x0f) + 1;
602 tmp = msrpm[offset];
603
604 BUG_ON(offset == MSR_INVALID);
605
606 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
607 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
608
609 msrpm[offset] = tmp;
6aa8b732
AK		 610}
611
f65c229c 612static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 613{
614 int i;
615
f65c229c
JR		 616 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
617
ac72a9b7
JR		 618 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
619 if (!direct_access_msrs[i].always)
620 continue;
621
622 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
623 }
f65c229c
JR		 624}
625
323c3d80
JR		 626static void add_msr_offset(u32 offset)
627{
628 int i;
629
630 for (i = 0; i < MSRPM_OFFSETS; ++i) {
631
632 /* Offset already in list? */
633 if (msrpm_offsets[i] == offset)
bfc733a7 634 return;
323c3d80
JR		 635
636 /* Slot used by another offset? */
637 if (msrpm_offsets[i] != MSR_INVALID)
638 continue;
639
640 /* Add offset to list */
641 msrpm_offsets[i] = offset;
642
643 return;
6aa8b732 644 }
323c3d80
JR		 645
646 /*
647 * If this BUG triggers the msrpm_offsets table has an overflow. Just
648 * increase MSRPM_OFFSETS in this case.
649 */
bfc733a7 650 BUG();
6aa8b732
AK		 651}
652
323c3d80 653static void init_msrpm_offsets(void)
f65c229c 654{
323c3d80 655 int i;
f65c229c 656
323c3d80
JR		 657 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
658
659 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
660 u32 offset;
661
662 offset = svm_msrpm_offset(direct_access_msrs[i].index);
663 BUG_ON(offset == MSR_INVALID);
664
665 add_msr_offset(offset);
666 }
f65c229c
JR		 667}
668
24e09cbf
JR		 669static void svm_enable_lbrv(struct vcpu_svm *svm)
670{
671 u32 *msrpm = svm->msrpm;
672
0dc92119 673 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
24e09cbf
JR		 674 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
675 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
676 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
677 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
678}
679
680static void svm_disable_lbrv(struct vcpu_svm *svm)
681{
682 u32 *msrpm = svm->msrpm;
683
0dc92119 684 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
24e09cbf
JR		 685 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
686 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
687 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
688 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
689}
690
883b0a91 691void disable_nmi_singlestep(struct vcpu_svm *svm)
4aebd0e9
LP		 692{
693 svm->nmi_singlestep = false;
640bd6e5 694
ab2f4d73
LP		 695 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
696 /* Clear our flags if they were not set by the guest */
697 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
698 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
699 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
700 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
701 }
4aebd0e9
LP		 702}
703
8566ac8b
BM		 704static void grow_ple_window(struct kvm_vcpu *vcpu)
705{
706 struct vcpu_svm *svm = to_svm(vcpu);
707 struct vmcb_control_area *control = &svm->vmcb->control;
708 int old = control->pause_filter_count;
709
710 control->pause_filter_count = __grow_ple_window(old,
711 pause_filter_count,
712 pause_filter_count_grow,
713 pause_filter_count_max);
714
4f75bcc3 715 if (control->pause_filter_count != old) {
06e7852c 716 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 717 trace_kvm_ple_window_update(vcpu->vcpu_id,
718 control->pause_filter_count, old);
719 }
8566ac8b
BM		 720}
721
722static void shrink_ple_window(struct kvm_vcpu *vcpu)
723{
724 struct vcpu_svm *svm = to_svm(vcpu);
725 struct vmcb_control_area *control = &svm->vmcb->control;
726 int old = control->pause_filter_count;
727
728 control->pause_filter_count =
729 __shrink_ple_window(old,
730 pause_filter_count,
731 pause_filter_count_shrink,
732 pause_filter_count);
4f75bcc3 733 if (control->pause_filter_count != old) {
06e7852c 734 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 735 trace_kvm_ple_window_update(vcpu->vcpu_id,
736 control->pause_filter_count, old);
737 }
8566ac8b
BM		 738}
739
52918ed5
TL		 740/*
741 * The default MMIO mask is a single bit (excluding the present bit),
742 * which could conflict with the memory encryption bit. Check for
743 * memory encryption support and override the default MMIO mask if
744 * memory encryption is enabled.
745 */
746static __init void svm_adjust_mmio_mask(void)
747{
748 unsigned int enc_bit, mask_bit;
749 u64 msr, mask;
750
751 /* If there is no memory encryption support, use existing mask */
752 if (cpuid_eax(0x80000000) < 0x8000001f)
753 return;
754
755 /* If memory encryption is not enabled, use existing mask */
756 rdmsrl(MSR_K8_SYSCFG, msr);
757 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
758 return;
759
760 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
761 mask_bit = boot_cpu_data.x86_phys_bits;
762
763 /* Increment the mask bit if it is the same as the encryption bit */
764 if (enc_bit == mask_bit)
765 mask_bit++;
766
767 /*
768 * If the mask bit location is below 52, then some bits above the
769 * physical addressing limit will always be reserved, so use the
770 * rsvd_bits() function to generate the mask. This mask, along with
771 * the present bit, will be used to generate a page fault with
772 * PFER.RSV = 1.
773 *
774 * If the mask bit location is 52 (or above), then clear the mask.
775 */
776 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
777
e7581cac 778 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
52918ed5
TL		 779}
780
dd58f3c9
LR		 781static void svm_hardware_teardown(void)
782{
783 int cpu;
784
eaf78265
JR		 785 if (svm_sev_enabled())
786 sev_hardware_teardown();
dd58f3c9
LR		 787
788 for_each_possible_cpu(cpu)
789 svm_cpu_uninit(cpu);
790
791 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
792 iopm_base = 0;
793}
794
9b58b985
SC		 795static __init void svm_set_cpu_caps(void)
796{
797 kvm_set_cpu_caps();
798
408e9a31
PB		 799 supported_xss = 0;
800
a50718cc
SC		 801 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
802 if (nested) {
9b58b985
SC		 803 kvm_cpu_cap_set(X86_FEATURE_SVM);
804
4eb87460 805 if (nrips)
a50718cc
SC		 806 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
807
808 if (npt_enabled)
809 kvm_cpu_cap_set(X86_FEATURE_NPT);
810 }
811
93c380e7
SC		 812 /* CPUID 0x80000008 */
813 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
814 boot_cpu_has(X86_FEATURE_AMD_SSBD))
815 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
9b58b985
SC		 816}
817
6aa8b732
AK		 818static __init int svm_hardware_setup(void)
819{
820 int cpu;
821 struct page *iopm_pages;
f65c229c 822 void *iopm_va;
6aa8b732
AK		 823 int r;
824
6aa8b732
AK		 825 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
826
827 if (!iopm_pages)
828 return -ENOMEM;
c8681339
AL		 829
830 iopm_va = page_address(iopm_pages);
831 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 832 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
833
323c3d80
JR		 834 init_msrpm_offsets();
835
cfc48181
SC		 836 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
837
50a37eb4
JR		 838 if (boot_cpu_has(X86_FEATURE_NX))
839 kvm_enable_efer_bits(EFER_NX);
840
1b2fd70c
AG		 841 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
842 kvm_enable_efer_bits(EFER_FFXSR);
843
92a1f12d 844 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
92a1f12d 845 kvm_has_tsc_control = true;
bc9b961b
HZ		 846 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
847 kvm_tsc_scaling_ratio_frac_bits = 32;
92a1f12d
JR		 848 }
849
8566ac8b
BM		 850 /* Check for pause filtering support */
851 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
852 pause_filter_count = 0;
853 pause_filter_thresh = 0;
854 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
855 pause_filter_thresh = 0;
856 }
857
236de055
AG		 858 if (nested) {
859 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 860 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 861 }
862
e9df0942
BS		 863 if (sev) {
864 if (boot_cpu_has(X86_FEATURE_SEV) &&
865 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
866 r = sev_hardware_setup();
867 if (r)
868 sev = false;
869 } else {
870 sev = false;
871 }
872 }
873
52918ed5
TL		 874 svm_adjust_mmio_mask();
875
3230bb47 876 for_each_possible_cpu(cpu) {
6aa8b732
AK		 877 r = svm_cpu_init(cpu);
878 if (r)
f65c229c 879 goto err;
6aa8b732 880 }
33bd6a0b 881
2a6b20b8 882 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 883 npt_enabled = false;
884
213e0e1f 885 if (npt_enabled && !npt)
6c7dac72 886 npt_enabled = false;
6c7dac72 887
3bae0459 888 kvm_configure_mmu(npt_enabled, PG_LEVEL_1G);
213e0e1f 889 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
e3da3acd 890
d647eb63
PB		 891 if (nrips) {
892 if (!boot_cpu_has(X86_FEATURE_NRIPS))
893 nrips = false;
894 }
895
5b8abf1f
SS		 896 if (avic) {
897 if (!npt_enabled ||
898 !boot_cpu_has(X86_FEATURE_AVIC) ||
5881f737 899 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
5b8abf1f 900 avic = false;
5881f737 901 } else {
5b8abf1f 902 pr_info("AVIC enabled\n");
5881f737 903
5881f737
SS		 904 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
905 }
5b8abf1f 906 }
44a95dae 907
89c8a498
JN		 908 if (vls) {
909 if (!npt_enabled ||
5442c269 910 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
89c8a498
JN		 911 !IS_ENABLED(CONFIG_X86_64)) {
912 vls = false;
913 } else {
914 pr_info("Virtual VMLOAD VMSAVE supported\n");
915 }
916 }
917
640bd6e5
JN		 918 if (vgif) {
919 if (!boot_cpu_has(X86_FEATURE_VGIF))
920 vgif = false;
921 else
922 pr_info("Virtual GIF supported\n");
923 }
924
9b58b985 925 svm_set_cpu_caps();
66a6950f 926
6aa8b732
AK		 927 return 0;
928
f65c229c 929err:
dd58f3c9 930 svm_hardware_teardown();
6aa8b732
AK		 931 return r;
932}
933
6aa8b732
AK		 934static void init_seg(struct vmcb_seg *seg)
935{
936 seg->selector = 0;
937 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 938 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 939 seg->limit = 0xffff;
940 seg->base = 0;
941}
942
943static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
944{
945 seg->selector = 0;
946 seg->attrib = SVM_SELECTOR_P_MASK | type;
947 seg->limit = 0xffff;
948 seg->base = 0;
949}
950
326e7425 951static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
f4e1b3c8
ZA		 952{
953 struct vcpu_svm *svm = to_svm(vcpu);
954 u64 g_tsc_offset = 0;
955
2030753d 956 if (is_guest_mode(vcpu)) {
e79f245d 957 /* Write L1's TSC offset. */
f4e1b3c8
ZA		 958 g_tsc_offset = svm->vmcb->control.tsc_offset -
959 svm->nested.hsave->control.tsc_offset;
960 svm->nested.hsave->control.tsc_offset = offset;
45c3af97
PB		 961 }
962
963 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
964 svm->vmcb->control.tsc_offset - g_tsc_offset,
965 offset);
f4e1b3c8
ZA		 966
967 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23 968
06e7852c 969 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
326e7425 970 return svm->vmcb->control.tsc_offset;
f4e1b3c8
ZA		 971}
972
5690891b 973static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 974{
e6101a96
JR		 975 struct vmcb_control_area *control = &svm->vmcb->control;
976 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 977
4ee546b4 978 svm->vcpu.arch.hflags = 0;
bff78274 979
4ee546b4
RJ		 980 set_cr_intercept(svm, INTERCEPT_CR0_READ);
981 set_cr_intercept(svm, INTERCEPT_CR3_READ);
982 set_cr_intercept(svm, INTERCEPT_CR4_READ);
983 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
984 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
985 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
3bbf3565
SS		 986 if (!kvm_vcpu_apicv_active(&svm->vcpu))
987 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 988
5315c716 989 set_dr_intercepts(svm);
6aa8b732 990
18c918c5
JR		 991 set_exception_intercept(svm, PF_VECTOR);
992 set_exception_intercept(svm, UD_VECTOR);
993 set_exception_intercept(svm, MC_VECTOR);
54a20552 994 set_exception_intercept(svm, AC_VECTOR);
cbdb967a 995 set_exception_intercept(svm, DB_VECTOR);
9718420e
LA		 996 /*
997 * Guest access to VMware backdoor ports could legitimately
998 * trigger #GP because of TSS I/O permission bitmap.
999 * We intercept those #GP and allow access to them anyway
1000 * as VMware does.
1001 */
1002 if (enable_vmware_backdoor)
1003 set_exception_intercept(svm, GP_VECTOR);
6aa8b732 1004
a284ba56
JR		 1005 svm_set_intercept(svm, INTERCEPT_INTR);
1006 svm_set_intercept(svm, INTERCEPT_NMI);
1007 svm_set_intercept(svm, INTERCEPT_SMI);
1008 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1009 svm_set_intercept(svm, INTERCEPT_RDPMC);
1010 svm_set_intercept(svm, INTERCEPT_CPUID);
1011 svm_set_intercept(svm, INTERCEPT_INVD);
1012 svm_set_intercept(svm, INTERCEPT_INVLPG);
1013 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1014 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1015 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1016 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1017 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1018 svm_set_intercept(svm, INTERCEPT_VMRUN);
1019 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1020 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1021 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1022 svm_set_intercept(svm, INTERCEPT_STGI);
1023 svm_set_intercept(svm, INTERCEPT_CLGI);
1024 svm_set_intercept(svm, INTERCEPT_SKINIT);
1025 svm_set_intercept(svm, INTERCEPT_WBINVD);
1026 svm_set_intercept(svm, INTERCEPT_XSETBV);
1027 svm_set_intercept(svm, INTERCEPT_RDPRU);
1028 svm_set_intercept(svm, INTERCEPT_RSM);
6aa8b732 1029
4d5422ce 1030 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
a284ba56
JR		 1031 svm_set_intercept(svm, INTERCEPT_MONITOR);
1032 svm_set_intercept(svm, INTERCEPT_MWAIT);
668fffa3
MT		 1033 }
1034
caa057a2 1035 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
a284ba56 1036 svm_set_intercept(svm, INTERCEPT_HLT);
caa057a2 1037
d0ec49d4
TL		 1038 control->iopm_base_pa = __sme_set(iopm_base);
1039 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
6aa8b732
AK		 1040 control->int_ctl = V_INTR_MASKING_MASK;
1041
1042 init_seg(&save->es);
1043 init_seg(&save->ss);
1044 init_seg(&save->ds);
1045 init_seg(&save->fs);
1046 init_seg(&save->gs);
1047
1048 save->cs.selector = 0xf000;
04b66839 1049 save->cs.base = 0xffff0000;
6aa8b732
AK		 1050 /* Executable/Readable Code Segment */
1051 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1052 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1053 save->cs.limit = 0xffff;
6aa8b732
AK		 1054
1055 save->gdtr.limit = 0xffff;
1056 save->idtr.limit = 0xffff;
1057
1058 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1059 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1060
5690891b 1061 svm_set_efer(&svm->vcpu, 0);
d77c26fc 1062 save->dr6 = 0xffff0ff0;
f6e78475 1063 kvm_set_rflags(&svm->vcpu, 2);
6aa8b732 1064 save->rip = 0x0000fff0;
5fdbf976 1065 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 1066
e0231715 1067 /*
18fa000a 1068 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
d28bc9dd 1069 * It also updates the guest-visible cr0 value.
6aa8b732 1070 */
79a8059d 1071 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
ebae871a 1072 kvm_mmu_reset_context(&svm->vcpu);
18fa000a 1073
66aee91a 1074 save->cr4 = X86_CR4_PAE;
6aa8b732 1075 /* rdx = ?? */
709ddebf
JR		 1076
1077 if (npt_enabled) {
1078 /* Setup VMCB for Nested Paging */
cea3a19b 1079 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
a284ba56 1080 svm_clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 1081 clr_exception_intercept(svm, PF_VECTOR);
4ee546b4
RJ		 1082 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1083 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
74545705 1084 save->g_pat = svm->vcpu.arch.pat;
709ddebf
JR		 1085 save->cr3 = 0;
1086 save->cr4 = 0;
1087 }
f40f6a45 1088 svm->asid_generation = 0;
1371d904 1089
e6aa9abd 1090 svm->nested.vmcb = 0;
2af9194d
JR		 1091 svm->vcpu.arch.hflags = 0;
1092
8566ac8b
BM		 1093 if (pause_filter_count) {
1094 control->pause_filter_count = pause_filter_count;
1095 if (pause_filter_thresh)
1096 control->pause_filter_thresh = pause_filter_thresh;
a284ba56 1097 svm_set_intercept(svm, INTERCEPT_PAUSE);
8566ac8b 1098 } else {
a284ba56 1099 svm_clr_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1100 }
1101
67034bb9 1102 if (kvm_vcpu_apicv_active(&svm->vcpu))
44a95dae
SS		 1103 avic_init_vmcb(svm);
1104
89c8a498
JN		 1105 /*
1106 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1107 * in VMCB and clear intercepts to avoid #VMEXIT.
1108 */
1109 if (vls) {
a284ba56
JR		 1110 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1111 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
89c8a498
JN		 1112 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1113 }
1114
640bd6e5 1115 if (vgif) {
a284ba56
JR		 1116 svm_clr_intercept(svm, INTERCEPT_STGI);
1117 svm_clr_intercept(svm, INTERCEPT_CLGI);
640bd6e5
JN		 1118 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1119 }
1120
35c6f649 1121 if (sev_guest(svm->vcpu.kvm)) {
1654efcb 1122 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
35c6f649
BS		 1123 clr_exception_intercept(svm, UD_VECTOR);
1124 }
1654efcb 1125
06e7852c 1126 vmcb_mark_all_dirty(svm->vmcb);
8d28fec4 1127
2af9194d 1128 enable_gif(svm);
44a95dae
SS		 1129
1130}
1131
d28bc9dd 1132static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
04d2cc77
AK		 1133{
1134 struct vcpu_svm *svm = to_svm(vcpu);
66f7b72e
JS		 1135 u32 dummy;
1136 u32 eax = 1;
04d2cc77 1137
b2ac58f9 1138 svm->spec_ctrl = 0;
ccbcd267 1139 svm->virt_spec_ctrl = 0;
b2ac58f9 1140
d28bc9dd
NA		 1141 if (!init_event) {
1142 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1143 MSR_IA32_APICBASE_ENABLE;
1144 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1145 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1146 }
5690891b 1147 init_vmcb(svm);
70433389 1148
f91af517 1149 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
de3cd117 1150 kvm_rdx_write(vcpu, eax);
44a95dae
SS		 1151
1152 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1153 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
04d2cc77
AK		 1154}
1155
987b2594 1156static int svm_create_vcpu(struct kvm_vcpu *vcpu)
6aa8b732 1157{
a2fa3e9f 1158 struct vcpu_svm *svm;
6aa8b732 1159 struct page *page;
f65c229c 1160 struct page *msrpm_pages;
b286d5d8 1161 struct page *hsave_page;
3d6368ef 1162 struct page *nested_msrpm_pages;
fb3f0f51 1163 int err;
6aa8b732 1164
a9dd6f09
SC		 1165 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1166 svm = to_svm(vcpu);
fb3f0f51 1167
b7af4043 1168 err = -ENOMEM;
1ec69647 1169 page = alloc_page(GFP_KERNEL_ACCOUNT);
b7af4043 1170 if (!page)
987b2594 1171 goto out;
6aa8b732 1172
1ec69647 1173 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
f65c229c 1174 if (!msrpm_pages)
b7af4043 1175 goto free_page1;
3d6368ef 1176
1ec69647 1177 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
3d6368ef 1178 if (!nested_msrpm_pages)
b7af4043 1179 goto free_page2;
f65c229c 1180
1ec69647 1181 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
b286d5d8 1182 if (!hsave_page)
b7af4043
TY		 1183 goto free_page3;
1184
dfa20099
SS		 1185 err = avic_init_vcpu(svm);
1186 if (err)
1187 goto free_page4;
44a95dae 1188
8221c137
SS		 1189 /* We initialize this flag to true to make sure that the is_running
1190 * bit would be set the first time the vcpu is loaded.
1191 */
6c3e4422
SS		 1192 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1193 svm->avic_is_running = true;
8221c137 1194
e6aa9abd 1195 svm->nested.hsave = page_address(hsave_page);
cc440cda 1196 clear_page(svm->nested.hsave);
b286d5d8 1197
b7af4043
TY		 1198 svm->msrpm = page_address(msrpm_pages);
1199 svm_vcpu_init_msrpm(svm->msrpm);
1200
e6aa9abd 1201 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 1202 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 1203
a2fa3e9f
GH		 1204 svm->vmcb = page_address(page);
1205 clear_page(svm->vmcb);
d0ec49d4 1206 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
a2fa3e9f 1207 svm->asid_generation = 0;
5690891b 1208 init_vmcb(svm);
6aa8b732 1209
7f27179a 1210 svm_init_osvw(vcpu);
bab0c318 1211 vcpu->arch.microcode_version = 0x01000065;
2b036c6b 1212
a9dd6f09 1213 return 0;
36241b8c 1214
44a95dae
SS		 1215free_page4:
1216 __free_page(hsave_page);
b7af4043
TY		 1217free_page3:
1218 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1219free_page2:
1220 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1221free_page1:
1222 __free_page(page);
987b2594 1223out:
a9dd6f09 1224 return err;
6aa8b732
AK		 1225}
1226
fd65d314
JM		 1227static void svm_clear_current_vmcb(struct vmcb *vmcb)
1228{
1229 int i;
1230
1231 for_each_online_cpu(i)
1232 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1233}
1234
6aa8b732
AK		 1235static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1236{
a2fa3e9f
GH		 1237 struct vcpu_svm *svm = to_svm(vcpu);
1238
fd65d314
JM		 1239 /*
1240 * The vmcb page can be recycled, causing a false negative in
1241 * svm_vcpu_load(). So, ensure that no logical CPU has this
1242 * vmcb page recorded as its current vmcb.
1243 */
1244 svm_clear_current_vmcb(svm->vmcb);
1245
d0ec49d4 1246 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
f65c229c 1247 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1248 __free_page(virt_to_page(svm->nested.hsave));
1249 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
6aa8b732
AK		 1250}
1251
15ad7146 1252static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1253{
a2fa3e9f 1254 struct vcpu_svm *svm = to_svm(vcpu);
15d45071 1255 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
15ad7146 1256 int i;
0cc5064d 1257
0cc5064d 1258 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1259 svm->asid_generation = 0;
06e7852c 1260 vmcb_mark_all_dirty(svm->vmcb);
0cc5064d 1261 }
94dfbdb3 1262
82ca2d10
AK		 1263#ifdef CONFIG_X86_64
1264 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1265#endif
dacccfdd
AK		 1266 savesegment(fs, svm->host.fs);
1267 savesegment(gs, svm->host.gs);
1268 svm->host.ldt = kvm_read_ldt();
1269
94dfbdb3 1270 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1271 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
fbc0db76 1272
ad721883
HZ		 1273 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1274 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1275 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1276 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1277 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1278 }
fbc0db76 1279 }
46896c73
PB		 1280 /* This assumes that the kernel never uses MSR_TSC_AUX */
1281 if (static_cpu_has(X86_FEATURE_RDTSCP))
1282 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
8221c137 1283
15d45071
AR		 1284 if (sd->current_vmcb != svm->vmcb) {
1285 sd->current_vmcb = svm->vmcb;
1286 indirect_branch_prediction_barrier();
1287 }
8221c137 1288 avic_vcpu_load(vcpu, cpu);
6aa8b732
AK		 1289}
1290
1291static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1292{
a2fa3e9f 1293 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1294 int i;
1295
8221c137
SS		 1296 avic_vcpu_put(vcpu);
1297
e1beb1d3 1298 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1299 kvm_load_ldt(svm->host.ldt);
1300#ifdef CONFIG_X86_64
1301 loadsegment(fs, svm->host.fs);
296f781a 1302 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
893a5ab6 1303 load_gs_index(svm->host.gs);
dacccfdd 1304#else
831ca609 1305#ifdef CONFIG_X86_32_LAZY_GS
dacccfdd 1306 loadsegment(gs, svm->host.gs);
831ca609 1307#endif
dacccfdd 1308#endif
94dfbdb3 1309 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1310 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1311}
1312
6aa8b732
AK		 1313static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1314{
9b611747
LP		 1315 struct vcpu_svm *svm = to_svm(vcpu);
1316 unsigned long rflags = svm->vmcb->save.rflags;
1317
1318 if (svm->nmi_singlestep) {
1319 /* Hide our flags if they were not set by the guest */
1320 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1321 rflags &= ~X86_EFLAGS_TF;
1322 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1323 rflags &= ~X86_EFLAGS_RF;
1324 }
1325 return rflags;
6aa8b732
AK		 1326}
1327
1328static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1329{
9b611747
LP		 1330 if (to_svm(vcpu)->nmi_singlestep)
1331 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1332
ae9fedc7 1333 /*
bb3541f1 1334 * Any change of EFLAGS.VM is accompanied by a reload of SS
ae9fedc7
PB		 1335 * (caused by either a task switch or an inter-privilege IRET),
1336 * so we do not need to update the CPL here.
1337 */
a2fa3e9f 1338 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1339}
1340
6de4f3ad
AK		 1341static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1342{
1343 switch (reg) {
1344 case VCPU_EXREG_PDPTR:
1345 BUG_ON(!npt_enabled);
9f8fe504 1346 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6de4f3ad
AK		 1347 break;
1348 default:
34059c25 1349 WARN_ON_ONCE(1);
6de4f3ad
AK		 1350 }
1351}
1352
e14b7786 1353static void svm_set_vintr(struct vcpu_svm *svm)
64b5bd27
PB		 1354{
1355 struct vmcb_control_area *control;
1356
1357 /* The following fields are ignored when AVIC is enabled */
1358 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
a284ba56 1359 svm_set_intercept(svm, INTERCEPT_VINTR);
64b5bd27
PB		 1360
1361 /*
1362 * This is just a dummy VINTR to actually cause a vmexit to happen.
1363 * Actual injection of virtual interrupts happens through EVENTINJ.
1364 */
1365 control = &svm->vmcb->control;
1366 control->int_vector = 0x0;
1367 control->int_ctl &= ~V_INTR_PRIO_MASK;
1368 control->int_ctl |= V_IRQ_MASK |
1369 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
06e7852c 1370 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
64b5bd27
PB		 1371}
1372
f0b85051
AG		 1373static void svm_clear_vintr(struct vcpu_svm *svm)
1374{
d8e4e58f 1375 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
a284ba56 1376 svm_clr_intercept(svm, INTERCEPT_VINTR);
64b5bd27 1377
d8e4e58f
PB		 1378 /* Drop int_ctl fields related to VINTR injection. */
1379 svm->vmcb->control.int_ctl &= mask;
1380 if (is_guest_mode(&svm->vcpu)) {
fb7333df
PB		 1381 svm->nested.hsave->control.int_ctl &= mask;
1382
d8e4e58f
PB		 1383 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1384 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1385 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1386 }
1387
06e7852c 1388 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
f0b85051
AG		 1389}
1390
6aa8b732
AK		 1391static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1392{
a2fa3e9f 1393 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1394
1395 switch (seg) {
1396 case VCPU_SREG_CS: return &save->cs;
1397 case VCPU_SREG_DS: return &save->ds;
1398 case VCPU_SREG_ES: return &save->es;
1399 case VCPU_SREG_FS: return &save->fs;
1400 case VCPU_SREG_GS: return &save->gs;
1401 case VCPU_SREG_SS: return &save->ss;
1402 case VCPU_SREG_TR: return &save->tr;
1403 case VCPU_SREG_LDTR: return &save->ldtr;
1404 }
1405 BUG();
8b6d44c7 1406 return NULL;
6aa8b732
AK		 1407}
1408
1409static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1410{
1411 struct vmcb_seg *s = svm_seg(vcpu, seg);
1412
1413 return s->base;
1414}
1415
1416static void svm_get_segment(struct kvm_vcpu *vcpu,
1417 struct kvm_segment *var, int seg)
1418{
1419 struct vmcb_seg *s = svm_seg(vcpu, seg);
1420
1421 var->base = s->base;
1422 var->limit = s->limit;
1423 var->selector = s->selector;
1424 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1425 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1426 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1427 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1428 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1429 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1430 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
80112c89
JM		 1431
1432 /*
1433 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1434 * However, the SVM spec states that the G bit is not observed by the
1435 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1436 * So let's synthesize a legal G bit for all segments, this helps
1437 * running KVM nested. It also helps cross-vendor migration, because
1438 * Intel's vmentry has a check on the 'G' bit.
1439 */
1440 var->g = s->limit > 0xfffff;
25022acc 1441
e0231715
JR		 1442 /*
1443 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1444 * for cross vendor migration purposes by "not present"
1445 */
8eae9570 1446 var->unusable = !var->present;
19bca6ab 1447
1fbdc7a5 1448 switch (seg) {
1fbdc7a5
AP		 1449 case VCPU_SREG_TR:
1450 /*
1451 * Work around a bug where the busy flag in the tr selector
1452 * isn't exposed
1453 */
c0d09828 1454 var->type |= 0x2;
1fbdc7a5
AP		 1455 break;
1456 case VCPU_SREG_DS:
1457 case VCPU_SREG_ES:
1458 case VCPU_SREG_FS:
1459 case VCPU_SREG_GS:
1460 /*
1461 * The accessed bit must always be set in the segment
1462 * descriptor cache, although it can be cleared in the
1463 * descriptor, the cached bit always remains at 1. Since
1464 * Intel has a check on this, set it here to support
1465 * cross-vendor migration.
1466 */
1467 if (!var->unusable)
1468 var->type |= 0x1;
1469 break;
b586eb02 1470 case VCPU_SREG_SS:
e0231715
JR		 1471 /*
1472 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1473 * descriptor is left as 1, although the whole segment has
1474 * been made unusable. Clear it here to pass an Intel VMX
1475 * entry check when cross vendor migrating.
1476 */
1477 if (var->unusable)
1478 var->db = 0;
d9c1b543 1479 /* This is symmetric with svm_set_segment() */
33b458d2 1480 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
b586eb02 1481 break;
1fbdc7a5 1482 }
6aa8b732
AK		 1483}
1484
2e4d2653
IE		 1485static int svm_get_cpl(struct kvm_vcpu *vcpu)
1486{
1487 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1488
1489 return save->cpl;
1490}
1491
89a27f4d 1492static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1493{
a2fa3e9f
GH		 1494 struct vcpu_svm *svm = to_svm(vcpu);
1495
89a27f4d
GN		 1496 dt->size = svm->vmcb->save.idtr.limit;
1497 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1498}
1499
89a27f4d 1500static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1501{
a2fa3e9f
GH		 1502 struct vcpu_svm *svm = to_svm(vcpu);
1503
89a27f4d
GN		 1504 svm->vmcb->save.idtr.limit = dt->size;
1505 svm->vmcb->save.idtr.base = dt->address ;
06e7852c 1506 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1507}
1508
89a27f4d 1509static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1510{
a2fa3e9f
GH		 1511 struct vcpu_svm *svm = to_svm(vcpu);
1512
89a27f4d
GN		 1513 dt->size = svm->vmcb->save.gdtr.limit;
1514 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1515}
1516
89a27f4d 1517static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1518{
a2fa3e9f
GH		 1519 struct vcpu_svm *svm = to_svm(vcpu);
1520
89a27f4d
GN		 1521 svm->vmcb->save.gdtr.limit = dt->size;
1522 svm->vmcb->save.gdtr.base = dt->address ;
06e7852c 1523 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1524}
1525
d225157b
AK		 1526static void update_cr0_intercept(struct vcpu_svm *svm)
1527{
1528 ulong gcr0 = svm->vcpu.arch.cr0;
1529 u64 *hcr0 = &svm->vmcb->save.cr0;
1530
bd7e5b08
PB		 1531 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1532 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
d225157b 1533
06e7852c 1534 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1535
bd7e5b08 1536 if (gcr0 == *hcr0) {
4ee546b4
RJ		 1537 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1538 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1539 } else {
4ee546b4
RJ		 1540 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1541 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1542 }
1543}
1544
883b0a91 1545void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 1546{
a2fa3e9f
GH		 1547 struct vcpu_svm *svm = to_svm(vcpu);
1548
05b3e0c2 1549#ifdef CONFIG_X86_64
f6801dff 1550 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1551 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1552 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1553 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1554 }
1555
d77c26fc 1556 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1557 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1558 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1559 }
1560 }
1561#endif
ad312c7c 1562 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1563
1564 if (!npt_enabled)
1565 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21 1566
bcf166a9
PB		 1567 /*
1568 * re-enable caching here because the QEMU bios
1569 * does not do it - this results in some delay at
1570 * reboot
1571 */
1572 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1573 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1574 svm->vmcb->save.cr0 = cr0;
06e7852c 1575 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1576 update_cr0_intercept(svm);
6aa8b732
AK		 1577}
1578
883b0a91 1579int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 1580{
1e02ce4c 1581 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
e5eab0ce
JR		 1582 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1583
5e1746d6
NHE		 1584 if (cr4 & X86_CR4_VMXE)
1585 return 1;
1586
e5eab0ce 1587 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
f55ac304 1588 svm_flush_tlb(vcpu);
6394b649 1589
ec077263
JR		 1590 vcpu->arch.cr4 = cr4;
1591 if (!npt_enabled)
1592 cr4 |= X86_CR4_PAE;
6394b649 1593 cr4 |= host_cr4_mce;
ec077263 1594 to_svm(vcpu)->vmcb->save.cr4 = cr4;
06e7852c 1595 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
5e1746d6 1596 return 0;
6aa8b732
AK		 1597}
1598
1599static void svm_set_segment(struct kvm_vcpu *vcpu,
1600 struct kvm_segment *var, int seg)
1601{
a2fa3e9f 1602 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1603 struct vmcb_seg *s = svm_seg(vcpu, seg);
1604
1605 s->base = var->base;
1606 s->limit = var->limit;
1607 s->selector = var->selector;
d9c1b543
RP		 1608 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1609 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1610 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1611 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1612 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1613 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1614 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1615 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
ae9fedc7
PB		 1616
1617 /*
1618 * This is always accurate, except if SYSRET returned to a segment
1619 * with SS.DPL != 3. Intel does not have this quirk, and always
1620 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1621 * would entail passing the CPL to userspace and back.
1622 */
1623 if (seg == VCPU_SREG_SS)
d9c1b543
RP		 1624 /* This is symmetric with svm_get_segment() */
1625 svm->vmcb->save.cpl = (var->dpl & 3);
6aa8b732 1626
06e7852c 1627 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1628}
1629
cbdb967a 1630static void update_bp_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1631{
d0bfb940
JK		 1632 struct vcpu_svm *svm = to_svm(vcpu);
1633
18c918c5 1634 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1635
d0bfb940 1636 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940 1637 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1638 set_exception_intercept(svm, BP_VECTOR);
d0bfb940
JK		 1639 } else
1640 vcpu->guest_debug = 0;
44c11430
GN		 1641}
1642
0fe1e009 1643static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1644{
0fe1e009
TH		 1645 if (sd->next_asid > sd->max_asid) {
1646 ++sd->asid_generation;
4faefff3 1647 sd->next_asid = sd->min_asid;
a2fa3e9f 1648 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1649 }
1650
0fe1e009
TH		 1651 svm->asid_generation = sd->asid_generation;
1652 svm->vmcb->control.asid = sd->next_asid++;
d48086d1 1653
06e7852c 1654 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1655}
1656
d67668e9 1657static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
73aaf249 1658{
d67668e9 1659 struct vmcb *vmcb = svm->vmcb;
73aaf249 1660
d67668e9
PB		 1661 if (unlikely(value != vmcb->save.dr6)) {
1662 vmcb->save.dr6 = value;
06e7852c 1663 vmcb_mark_dirty(vmcb, VMCB_DR);
d67668e9 1664 }
73aaf249
JK		 1665}
1666
facb0139
PB		 1667static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1668{
1669 struct vcpu_svm *svm = to_svm(vcpu);
1670
1671 get_debugreg(vcpu->arch.db[0], 0);
1672 get_debugreg(vcpu->arch.db[1], 1);
1673 get_debugreg(vcpu->arch.db[2], 2);
1674 get_debugreg(vcpu->arch.db[3], 3);
d67668e9
PB		 1675 /*
1676 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1677 * because db_interception might need it. We can do it before vmentry.
1678 */
5679b803 1679 vcpu->arch.dr6 = svm->vmcb->save.dr6;
facb0139 1680 vcpu->arch.dr7 = svm->vmcb->save.dr7;
facb0139
PB		 1681 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1682 set_dr_intercepts(svm);
1683}
1684
020df079 1685static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1686{
42dbaa5a 1687 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1688
020df079 1689 svm->vmcb->save.dr7 = value;
06e7852c 1690 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1691}
1692
851ba692 1693static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1694{
0ede79e1 1695 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1261bfa3 1696 u64 error_code = svm->vmcb->control.exit_info_1;
6aa8b732 1697
1261bfa3 1698 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
00b10fe1
BS		 1699 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1700 svm->vmcb->control.insn_bytes : NULL,
d0006530
PB		 1701 svm->vmcb->control.insn_len);
1702}
1703
1704static int npf_interception(struct vcpu_svm *svm)
1705{
0ede79e1 1706 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
d0006530
PB		 1707 u64 error_code = svm->vmcb->control.exit_info_1;
1708
1709 trace_kvm_page_fault(fault_address, error_code);
1710 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
00b10fe1
BS		 1711 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1712 svm->vmcb->control.insn_bytes : NULL,
d0006530 1713 svm->vmcb->control.insn_len);
6aa8b732
AK		 1714}
1715
851ba692 1716static int db_interception(struct vcpu_svm *svm)
d0bfb940 1717{
851ba692 1718 struct kvm_run *kvm_run = svm->vcpu.run;
99c22179 1719 struct kvm_vcpu *vcpu = &svm->vcpu;
851ba692 1720
d0bfb940 1721 if (!(svm->vcpu.guest_debug &
44c11430 1722 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1723 !svm->nmi_singlestep) {
d67668e9
PB		 1724 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1725 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
d0bfb940
JK		 1726 return 1;
1727 }
44c11430 1728
6be7d306 1729 if (svm->nmi_singlestep) {
4aebd0e9 1730 disable_nmi_singlestep(svm);
99c22179
VK		 1731 /* Make sure we check for pending NMIs upon entry */
1732 kvm_make_request(KVM_REQ_EVENT, vcpu);
44c11430
GN		 1733 }
1734
1735 if (svm->vcpu.guest_debug &
e0231715 1736 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430 1737 kvm_run->exit_reason = KVM_EXIT_DEBUG;
dee919d1
PB		 1738 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1739 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
44c11430
GN		 1740 kvm_run->debug.arch.pc =
1741 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1742 kvm_run->debug.arch.exception = DB_VECTOR;
1743 return 0;
1744 }
1745
1746 return 1;
d0bfb940
JK		 1747}
1748
851ba692 1749static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1750{
851ba692
AK		 1751 struct kvm_run *kvm_run = svm->vcpu.run;
1752
d0bfb940
JK		 1753 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1754 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1755 kvm_run->debug.arch.exception = BP_VECTOR;
1756 return 0;
1757}
1758
851ba692 1759static int ud_interception(struct vcpu_svm *svm)
7aa81cc0 1760{
082d06ed 1761 return handle_ud(&svm->vcpu);
7aa81cc0
AL		 1762}
1763
54a20552
EN		 1764static int ac_interception(struct vcpu_svm *svm)
1765{
1766 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1767 return 1;
1768}
1769
9718420e
LA		 1770static int gp_interception(struct vcpu_svm *svm)
1771{
1772 struct kvm_vcpu *vcpu = &svm->vcpu;
1773 u32 error_code = svm->vmcb->control.exit_info_1;
9718420e
LA		 1774
1775 WARN_ON_ONCE(!enable_vmware_backdoor);
1776
a6c6ed1e
SC		 1777 /*
1778 * VMware backdoor emulation on #GP interception only handles IN{S},
1779 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1780 */
1781 if (error_code) {
1782 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1783 return 1;
1784 }
60fc3d02 1785 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9718420e
LA		 1786}
1787
67ec6607
JR		 1788static bool is_erratum_383(void)
1789{
1790 int err, i;
1791 u64 value;
1792
1793 if (!erratum_383_found)
1794 return false;
1795
1796 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1797 if (err)
1798 return false;
1799
1800 /* Bit 62 may or may not be set for this mce */
1801 value &= ~(1ULL << 62);
1802
1803 if (value != 0xb600000000010015ULL)
1804 return false;
1805
1806 /* Clear MCi_STATUS registers */
1807 for (i = 0; i < 6; ++i)
1808 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1809
1810 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1811 if (!err) {
1812 u32 low, high;
1813
1814 value &= ~(1ULL << 2);
1815 low = lower_32_bits(value);
1816 high = upper_32_bits(value);
1817
1818 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1819 }
1820
1821 /* Flush tlb to evict multi-match entries */
1822 __flush_tlb_all();
1823
1824 return true;
1825}
1826
1c164cb3
UB		 1827/*
1828 * Trigger machine check on the host. We assume all the MSRs are already set up
1829 * by the CPU and that we still run on the same CPU as the MCE occurred on.
1830 * We pass a fake environment to the machine check handler because we want
1831 * the guest to be always treated like user space, no matter what context
1832 * it used internally.
1833 */
1834static void kvm_machine_check(void)
1835{
1836#if defined(CONFIG_X86_MCE)
1837 struct pt_regs regs = {
1838 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1839 .flags = X86_EFLAGS_IF,
1840 };
1841
8cd501c1 1842 do_machine_check(&regs);
1c164cb3
UB		 1843#endif
1844}
1845
fe5913e4 1846static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1847{
67ec6607
JR		 1848 if (is_erratum_383()) {
1849 /*
1850 * Erratum 383 triggered. Guest state is corrupt so kill the
1851 * guest.
1852 */
1853 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1854
a8eeb04a 1855 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1856
1857 return;
1858 }
1859
53371b50
JR		 1860 /*
1861 * On an #MC intercept the MCE handler is not called automatically in
1862 * the host. So do it by hand here.
1863 */
1c164cb3 1864 kvm_machine_check();
fe5913e4
JR		 1865}
1866
1867static int mc_interception(struct vcpu_svm *svm)
1868{
53371b50
JR		 1869 return 1;
1870}
1871
851ba692 1872static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1873{
851ba692
AK		 1874 struct kvm_run *kvm_run = svm->vcpu.run;
1875
46fe4ddd
JR		 1876 /*
1877 * VMCB is undefined after a SHUTDOWN intercept
1878 * so reinitialize it.
1879 */
a2fa3e9f 1880 clear_page(svm->vmcb);
5690891b 1881 init_vmcb(svm);
46fe4ddd
JR		 1882
1883 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1884 return 0;
1885}
1886
851ba692 1887static int io_interception(struct vcpu_svm *svm)
6aa8b732 1888{
cf8f70bf 1889 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1890 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
dca7f128 1891 int size, in, string;
039576c0 1892 unsigned port;
6aa8b732 1893
e756fc62 1894 ++svm->vcpu.stat.io_exits;
e70669ab 1895 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1896 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
8370c3d0 1897 if (string)
60fc3d02 1898 return kvm_emulate_instruction(vcpu, 0);
cf8f70bf 1899
039576c0
AK		 1900 port = io_info >> 16;
1901 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1902 svm->next_rip = svm->vmcb->control.exit_info_2;
cf8f70bf 1903
dca7f128 1904 return kvm_fast_pio(&svm->vcpu, size, port, in);
6aa8b732
AK		 1905}
1906
851ba692 1907static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1908{
1909 return 1;
1910}
1911
851ba692 1912static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1913{
1914 ++svm->vcpu.stat.irq_exits;
1915 return 1;
1916}
1917
851ba692 1918static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1919{
1920 return 1;
1921}
1922
851ba692 1923static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1924{
e756fc62 1925 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1926}
1927
851ba692 1928static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1929{
0d9c055e 1930 return kvm_emulate_hypercall(&svm->vcpu);
02e235bc
AK		 1931}
1932
851ba692 1933static int vmload_interception(struct vcpu_svm *svm)
5542675b 1934{
9966bf68 1935 struct vmcb *nested_vmcb;
8c5fbf1a 1936 struct kvm_host_map map;
b742c1e6 1937 int ret;
9966bf68 1938
5542675b
AG		 1939 if (nested_svm_check_permissions(svm))
1940 return 1;
1941
8c5fbf1a
KA		 1942 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1943 if (ret) {
1944 if (ret == -EINVAL)
1945 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1946 return 1;
8c5fbf1a
KA		 1947 }
1948
1949 nested_vmcb = map.hva;
9966bf68 1950
b742c1e6 1951 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1952
9966bf68 1953 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
8c5fbf1a 1954 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1955
b742c1e6 1956 return ret;
5542675b
AG		 1957}
1958
851ba692 1959static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1960{
9966bf68 1961 struct vmcb *nested_vmcb;
8c5fbf1a 1962 struct kvm_host_map map;
b742c1e6 1963 int ret;
9966bf68 1964
5542675b
AG		 1965 if (nested_svm_check_permissions(svm))
1966 return 1;
1967
8c5fbf1a
KA		 1968 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1969 if (ret) {
1970 if (ret == -EINVAL)
1971 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1972 return 1;
8c5fbf1a
KA		 1973 }
1974
1975 nested_vmcb = map.hva;
9966bf68 1976
b742c1e6 1977 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1978
9966bf68 1979 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
8c5fbf1a 1980 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1981
b742c1e6 1982 return ret;
5542675b
AG		 1983}
1984
851ba692 1985static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1986{
3d6368ef
AG		 1987 if (nested_svm_check_permissions(svm))
1988 return 1;
1989
e7134c1b 1990 return nested_svm_vmrun(svm);
3d6368ef
AG		 1991}
1992
ffdf7f9e
PB		 1993void svm_set_gif(struct vcpu_svm *svm, bool value)
1994{
1995 if (value) {
1996 /*
1997 * If VGIF is enabled, the STGI intercept is only added to
1998 * detect the opening of the SMI/NMI window; remove it now.
1999 * Likewise, clear the VINTR intercept, we will set it
2000 * again while processing KVM_REQ_EVENT if needed.
2001 */
2002 if (vgif_enabled(svm))
a284ba56
JR		 2003 svm_clr_intercept(svm, INTERCEPT_STGI);
2004 if (svm_is_intercept(svm, INTERCEPT_VINTR))
ffdf7f9e
PB		 2005 svm_clear_vintr(svm);
2006
2007 enable_gif(svm);
2008 if (svm->vcpu.arch.smi_pending ||
2009 svm->vcpu.arch.nmi_pending ||
2010 kvm_cpu_has_injectable_intr(&svm->vcpu))
2011 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2012 } else {
2013 disable_gif(svm);
2014
2015 /*
2016 * After a CLGI no interrupts should come. But if vGIF is
2017 * in use, we still rely on the VINTR intercept (rather than
2018 * STGI) to detect an open interrupt window.
2019 */
2020 if (!vgif_enabled(svm))
2021 svm_clear_vintr(svm);
2022 }
2023}
2024
851ba692 2025static int stgi_interception(struct vcpu_svm *svm)
1371d904 2026{
b742c1e6
LP		 2027 int ret;
2028
1371d904
AG		 2029 if (nested_svm_check_permissions(svm))
2030 return 1;
2031
b742c1e6 2032 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2033 svm_set_gif(svm, true);
b742c1e6 2034 return ret;
1371d904
AG		 2035}
2036
851ba692 2037static int clgi_interception(struct vcpu_svm *svm)
1371d904 2038{
b742c1e6
LP		 2039 int ret;
2040
1371d904
AG		 2041 if (nested_svm_check_permissions(svm))
2042 return 1;
2043
b742c1e6 2044 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2045 svm_set_gif(svm, false);
b742c1e6 2046 return ret;
1371d904
AG		 2047}
2048
851ba692 2049static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2050{
2051 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2052
de3cd117
SC		 2053 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2054 kvm_rax_read(&svm->vcpu));
ec1ff790 2055
ff092385 2056 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
de3cd117 2057 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
ff092385 2058
b742c1e6 2059 return kvm_skip_emulated_instruction(&svm->vcpu);
ff092385
AG		 2060}
2061
532a46b9
JR		 2062static int skinit_interception(struct vcpu_svm *svm)
2063{
de3cd117 2064 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
532a46b9
JR		 2065
2066 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2067 return 1;
2068}
2069
dab429a7
DK		 2070static int wbinvd_interception(struct vcpu_svm *svm)
2071{
6affcbed 2072 return kvm_emulate_wbinvd(&svm->vcpu);
dab429a7
DK		 2073}
2074
81dd35d4
JR		 2075static int xsetbv_interception(struct vcpu_svm *svm)
2076{
2077 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
de3cd117 2078 u32 index = kvm_rcx_read(&svm->vcpu);
81dd35d4
JR		 2079
2080 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
b742c1e6 2081 return kvm_skip_emulated_instruction(&svm->vcpu);
81dd35d4
JR		 2082 }
2083
2084 return 1;
2085}
2086
0cb8410b
JM		 2087static int rdpru_interception(struct vcpu_svm *svm)
2088{
2089 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2090 return 1;
2091}
2092
851ba692 2093static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2094{
37817f29 2095 u16 tss_selector;
64a7ec06
GN		 2096 int reason;
2097 int int_type = svm->vmcb->control.exit_int_info &
2098 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2099 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2100 uint32_t type =
2101 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2102 uint32_t idt_v =
2103 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2104 bool has_error_code = false;
2105 u32 error_code = 0;
37817f29
IE		 2106
2107 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2108
37817f29
IE		 2109 if (svm->vmcb->control.exit_info_2 &
2110 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2111 reason = TASK_SWITCH_IRET;
2112 else if (svm->vmcb->control.exit_info_2 &
2113 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2114 reason = TASK_SWITCH_JMP;
fe8e7f83 2115 else if (idt_v)
64a7ec06
GN		 2116 reason = TASK_SWITCH_GATE;
2117 else
2118 reason = TASK_SWITCH_CALL;
2119
fe8e7f83
GN		 2120 if (reason == TASK_SWITCH_GATE) {
2121 switch (type) {
2122 case SVM_EXITINTINFO_TYPE_NMI:
2123 svm->vcpu.arch.nmi_injected = false;
2124 break;
2125 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2126 if (svm->vmcb->control.exit_info_2 &
2127 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2128 has_error_code = true;
2129 error_code =
2130 (u32)svm->vmcb->control.exit_info_2;
2131 }
fe8e7f83
GN		 2132 kvm_clear_exception_queue(&svm->vcpu);
2133 break;
2134 case SVM_EXITINTINFO_TYPE_INTR:
2135 kvm_clear_interrupt_queue(&svm->vcpu);
2136 break;
2137 default:
2138 break;
2139 }
2140 }
64a7ec06 2141
8317c298
GN		 2142 if (reason != TASK_SWITCH_GATE ||
2143 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2144 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f8ea7c60 2145 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
60fc3d02 2146 if (!skip_emulated_instruction(&svm->vcpu))
738fece4 2147 return 0;
f8ea7c60 2148 }
64a7ec06 2149
7f3d35fd
KW		 2150 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2151 int_vec = -1;
2152
1051778f 2153 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
60fc3d02 2154 has_error_code, error_code);
6aa8b732
AK		 2155}
2156
851ba692 2157static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2158{
6a908b62 2159 return kvm_emulate_cpuid(&svm->vcpu);
6aa8b732
AK		 2160}
2161
851ba692 2162static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2163{
2164 ++svm->vcpu.stat.nmi_window_exits;
a284ba56 2165 svm_clr_intercept(svm, INTERCEPT_IRET);
44c11430 2166 svm->vcpu.arch.hflags |= HF_IRET_MASK;
bd3d1ec3 2167 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
f303b4ce 2168 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
95ba8273
GN		 2169 return 1;
2170}
2171
851ba692 2172static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2173{
df4f3108 2174 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
60fc3d02 2175 return kvm_emulate_instruction(&svm->vcpu, 0);
df4f3108
AP		 2176
2177 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
b742c1e6 2178 return kvm_skip_emulated_instruction(&svm->vcpu);
a7052897
MT		 2179}
2180
851ba692 2181static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2182{
60fc3d02 2183 return kvm_emulate_instruction(&svm->vcpu, 0);
6aa8b732
AK		 2184}
2185
7607b717
BS		 2186static int rsm_interception(struct vcpu_svm *svm)
2187{
60fc3d02 2188 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
7607b717
BS		 2189}
2190
332b56e4
AK		 2191static int rdpmc_interception(struct vcpu_svm *svm)
2192{
2193 int err;
2194
d647eb63 2195 if (!nrips)
332b56e4
AK		 2196 return emulate_on_interception(svm);
2197
2198 err = kvm_rdpmc(&svm->vcpu);
6affcbed 2199 return kvm_complete_insn_gp(&svm->vcpu, err);
332b56e4
AK		 2200}
2201
52eb5a6d
XL		 2202static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2203 unsigned long val)
628afd2a
JR		 2204{
2205 unsigned long cr0 = svm->vcpu.arch.cr0;
2206 bool ret = false;
2207 u64 intercept;
2208
e670bf68 2209 intercept = svm->nested.ctl.intercept;
628afd2a
JR		 2210
2211 if (!is_guest_mode(&svm->vcpu) ||
2212 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2213 return false;
2214
2215 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2216 val &= ~SVM_CR0_SELECTIVE_MASK;
2217
2218 if (cr0 ^ val) {
2219 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2220 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2221 }
2222
2223 return ret;
2224}
2225
7ff76d58
AP		 2226#define CR_VALID (1ULL << 63)
2227
2228static int cr_interception(struct vcpu_svm *svm)
2229{
2230 int reg, cr;
2231 unsigned long val;
2232 int err;
2233
2234 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2235 return emulate_on_interception(svm);
2236
2237 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2238 return emulate_on_interception(svm);
2239
2240 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
5e57518d
DK		 2241 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2242 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2243 else
2244 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
7ff76d58
AP		 2245
2246 err = 0;
2247 if (cr >= 16) { /* mov to cr */
2248 cr -= 16;
2249 val = kvm_register_read(&svm->vcpu, reg);
2250 switch (cr) {
2251 case 0:
628afd2a
JR		 2252 if (!check_selective_cr0_intercepted(svm, val))
2253 err = kvm_set_cr0(&svm->vcpu, val);
977b2d03
JR		 2254 else
2255 return 1;
2256
7ff76d58
AP		 2257 break;
2258 case 3:
2259 err = kvm_set_cr3(&svm->vcpu, val);
2260 break;
2261 case 4:
2262 err = kvm_set_cr4(&svm->vcpu, val);
2263 break;
2264 case 8:
2265 err = kvm_set_cr8(&svm->vcpu, val);
2266 break;
2267 default:
2268 WARN(1, "unhandled write to CR%d", cr);
2269 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2270 return 1;
2271 }
2272 } else { /* mov from cr */
2273 switch (cr) {
2274 case 0:
2275 val = kvm_read_cr0(&svm->vcpu);
2276 break;
2277 case 2:
2278 val = svm->vcpu.arch.cr2;
2279 break;
2280 case 3:
9f8fe504 2281 val = kvm_read_cr3(&svm->vcpu);
7ff76d58
AP		 2282 break;
2283 case 4:
2284 val = kvm_read_cr4(&svm->vcpu);
2285 break;
2286 case 8:
2287 val = kvm_get_cr8(&svm->vcpu);
2288 break;
2289 default:
2290 WARN(1, "unhandled read from CR%d", cr);
2291 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2292 return 1;
2293 }
2294 kvm_register_write(&svm->vcpu, reg, val);
2295 }
6affcbed 2296 return kvm_complete_insn_gp(&svm->vcpu, err);
7ff76d58
AP		 2297}
2298
cae3797a
AP		 2299static int dr_interception(struct vcpu_svm *svm)
2300{
2301 int reg, dr;
2302 unsigned long val;
cae3797a 2303
facb0139
PB		 2304 if (svm->vcpu.guest_debug == 0) {
2305 /*
2306 * No more DR vmexits; force a reload of the debug registers
2307 * and reenter on this instruction. The next vmexit will
2308 * retrieve the full state of the debug registers.
2309 */
2310 clr_dr_intercepts(svm);
2311 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2312 return 1;
2313 }
2314
cae3797a
AP		 2315 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2316 return emulate_on_interception(svm);
2317
2318 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2319 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2320
2321 if (dr >= 16) { /* mov to DRn */
16f8a6f9
NA		 2322 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2323 return 1;
cae3797a
AP		 2324 val = kvm_register_read(&svm->vcpu, reg);
2325 kvm_set_dr(&svm->vcpu, dr - 16, val);
2326 } else {
16f8a6f9
NA		 2327 if (!kvm_require_dr(&svm->vcpu, dr))
2328 return 1;
2329 kvm_get_dr(&svm->vcpu, dr, &val);
2330 kvm_register_write(&svm->vcpu, reg, val);
cae3797a
AP		 2331 }
2332
b742c1e6 2333 return kvm_skip_emulated_instruction(&svm->vcpu);
cae3797a
AP		 2334}
2335
851ba692 2336static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2337{
851ba692 2338 struct kvm_run *kvm_run = svm->vcpu.run;
eea1cff9 2339 int r;
851ba692 2340
0a5fff19
GN		 2341 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2342 /* instruction emulation calls kvm_set_cr8() */
7ff76d58 2343 r = cr_interception(svm);
35754c98 2344 if (lapic_in_kernel(&svm->vcpu))
7ff76d58 2345 return r;
0a5fff19 2346 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
7ff76d58 2347 return r;
1d075434
JR		 2348 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2349 return 0;
2350}
2351
801e459a
TL		 2352static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2353{
d1d93fa9
TL		 2354 msr->data = 0;
2355
2356 switch (msr->index) {
2357 case MSR_F10H_DECFG:
2358 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2359 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2360 break;
d574c539
VK		 2361 case MSR_IA32_PERF_CAPABILITIES:
2362 return 0;
d1d93fa9 2363 default:
12bc2132 2364 return KVM_MSR_RET_INVALID;
d1d93fa9
TL		 2365 }
2366
2367 return 0;
801e459a
TL		 2368}
2369
609e36d3 2370static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2371{
a2fa3e9f
GH		 2372 struct vcpu_svm *svm = to_svm(vcpu);
2373
609e36d3 2374 switch (msr_info->index) {
8c06585d 2375 case MSR_STAR:
609e36d3 2376 msr_info->data = svm->vmcb->save.star;
6aa8b732 2377 break;
0e859cac 2378#ifdef CONFIG_X86_64
6aa8b732 2379 case MSR_LSTAR:
609e36d3 2380 msr_info->data = svm->vmcb->save.lstar;
6aa8b732
AK		 2381 break;
2382 case MSR_CSTAR:
609e36d3 2383 msr_info->data = svm->vmcb->save.cstar;
6aa8b732
AK		 2384 break;
2385 case MSR_KERNEL_GS_BASE:
609e36d3 2386 msr_info->data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2387 break;
2388 case MSR_SYSCALL_MASK:
609e36d3 2389 msr_info->data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2390 break;
2391#endif
2392 case MSR_IA32_SYSENTER_CS:
609e36d3 2393 msr_info->data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2394 break;
2395 case MSR_IA32_SYSENTER_EIP:
609e36d3 2396 msr_info->data = svm->sysenter_eip;
6aa8b732
AK		 2397 break;
2398 case MSR_IA32_SYSENTER_ESP:
609e36d3 2399 msr_info->data = svm->sysenter_esp;
6aa8b732 2400 break;
46896c73
PB		 2401 case MSR_TSC_AUX:
2402 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2403 return 1;
2404 msr_info->data = svm->tsc_aux;
2405 break;
e0231715
JR		 2406 /*
2407 * Nobody will change the following 5 values in the VMCB so we can
2408 * safely return them on rdmsr. They will always be 0 until LBRV is
2409 * implemented.
2410 */
a2938c80 2411 case MSR_IA32_DEBUGCTLMSR:
609e36d3 2412 msr_info->data = svm->vmcb->save.dbgctl;
a2938c80
JR		 2413 break;
2414 case MSR_IA32_LASTBRANCHFROMIP:
609e36d3 2415 msr_info->data = svm->vmcb->save.br_from;
a2938c80
JR		 2416 break;
2417 case MSR_IA32_LASTBRANCHTOIP:
609e36d3 2418 msr_info->data = svm->vmcb->save.br_to;
a2938c80
JR		 2419 break;
2420 case MSR_IA32_LASTINTFROMIP:
609e36d3 2421 msr_info->data = svm->vmcb->save.last_excp_from;
a2938c80
JR		 2422 break;
2423 case MSR_IA32_LASTINTTOIP:
609e36d3 2424 msr_info->data = svm->vmcb->save.last_excp_to;
a2938c80 2425 break;
b286d5d8 2426 case MSR_VM_HSAVE_PA:
609e36d3 2427 msr_info->data = svm->nested.hsave_msr;
b286d5d8 2428 break;
eb6f302e 2429 case MSR_VM_CR:
609e36d3 2430 msr_info->data = svm->nested.vm_cr_msr;
eb6f302e 2431 break;
b2ac58f9
KA		 2432 case MSR_IA32_SPEC_CTRL:
2433 if (!msr_info->host_initiated &&
df7e8818
PB		 2434 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2435 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2436 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2437 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2438 return 1;
2439
2440 msr_info->data = svm->spec_ctrl;
2441 break;
bc226f07
TL		 2442 case MSR_AMD64_VIRT_SPEC_CTRL:
2443 if (!msr_info->host_initiated &&
2444 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2445 return 1;
2446
2447 msr_info->data = svm->virt_spec_ctrl;
2448 break;
ae8b7875
BP		 2449 case MSR_F15H_IC_CFG: {
2450
2451 int family, model;
2452
2453 family = guest_cpuid_family(vcpu);
2454 model = guest_cpuid_model(vcpu);
2455
2456 if (family < 0 || model < 0)
2457 return kvm_get_msr_common(vcpu, msr_info);
2458
2459 msr_info->data = 0;
2460
2461 if (family == 0x15 &&
2462 (model >= 0x2 && model < 0x20))
2463 msr_info->data = 0x1E;
2464 }
2465 break;
d1d93fa9
TL		 2466 case MSR_F10H_DECFG:
2467 msr_info->data = svm->msr_decfg;
2468 break;
6aa8b732 2469 default:
609e36d3 2470 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2471 }
2472 return 0;
2473}
2474
851ba692 2475static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2476{
1edce0a9 2477 return kvm_emulate_rdmsr(&svm->vcpu);
6aa8b732
AK		 2478}
2479
4a810181
JR		 2480static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2481{
2482 struct vcpu_svm *svm = to_svm(vcpu);
2483 int svm_dis, chg_mask;
2484
2485 if (data & ~SVM_VM_CR_VALID_MASK)
2486 return 1;
2487
2488 chg_mask = SVM_VM_CR_VALID_MASK;
2489
2490 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2491 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2492
2493 svm->nested.vm_cr_msr &= ~chg_mask;
2494 svm->nested.vm_cr_msr |= (data & chg_mask);
2495
2496 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2497
2498 /* check for svm_disable while efer.svme is set */
2499 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2500 return 1;
2501
2502 return 0;
2503}
2504
8fe8ab46 2505static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
6aa8b732 2506{
a2fa3e9f
GH		 2507 struct vcpu_svm *svm = to_svm(vcpu);
2508
8fe8ab46
WA		 2509 u32 ecx = msr->index;
2510 u64 data = msr->data;
6aa8b732 2511 switch (ecx) {
15038e14
PB		 2512 case MSR_IA32_CR_PAT:
2513 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2514 return 1;
2515 vcpu->arch.pat = data;
2516 svm->vmcb->save.g_pat = data;
06e7852c 2517 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
15038e14 2518 break;
b2ac58f9
KA		 2519 case MSR_IA32_SPEC_CTRL:
2520 if (!msr->host_initiated &&
df7e8818
PB		 2521 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2522 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2523 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2524 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2525 return 1;
2526
841c2be0 2527 if (kvm_spec_ctrl_test_value(data))
b2ac58f9
KA		 2528 return 1;
2529
2530 svm->spec_ctrl = data;
b2ac58f9
KA		 2531 if (!data)
2532 break;
2533
2534 /*
2535 * For non-nested:
2536 * When it's written (to non-zero) for the first time, pass
2537 * it through.
2538 *
2539 * For nested:
2540 * The handling of the MSR bitmap for L2 guests is done in
2541 * nested_svm_vmrun_msrpm.
2542 * We update the L1 MSR bit as well since it will end up
2543 * touching the MSR anyway now.
2544 */
2545 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2546 break;
15d45071
AR		 2547 case MSR_IA32_PRED_CMD:
2548 if (!msr->host_initiated &&
e7c587da 2549 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
15d45071
AR		 2550 return 1;
2551
2552 if (data & ~PRED_CMD_IBPB)
2553 return 1;
6441fa61
PB		 2554 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2555 return 1;
15d45071
AR		 2556 if (!data)
2557 break;
2558
2559 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
15d45071
AR		 2560 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2561 break;
bc226f07
TL		 2562 case MSR_AMD64_VIRT_SPEC_CTRL:
2563 if (!msr->host_initiated &&
2564 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2565 return 1;
2566
2567 if (data & ~SPEC_CTRL_SSBD)
2568 return 1;
2569
2570 svm->virt_spec_ctrl = data;
2571 break;
8c06585d 2572 case MSR_STAR:
a2fa3e9f 2573 svm->vmcb->save.star = data;
6aa8b732 2574 break;
49b14f24 2575#ifdef CONFIG_X86_64
6aa8b732 2576 case MSR_LSTAR:
a2fa3e9f 2577 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2578 break;
2579 case MSR_CSTAR:
a2fa3e9f 2580 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2581 break;
2582 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2583 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2584 break;
2585 case MSR_SYSCALL_MASK:
a2fa3e9f 2586 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2587 break;
2588#endif
2589 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2590 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2591 break;
2592 case MSR_IA32_SYSENTER_EIP:
017cb99e 2593 svm->sysenter_eip = data;
a2fa3e9f 2594 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2595 break;
2596 case MSR_IA32_SYSENTER_ESP:
017cb99e 2597 svm->sysenter_esp = data;
a2fa3e9f 2598 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2599 break;
46896c73
PB		 2600 case MSR_TSC_AUX:
2601 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2602 return 1;
2603
2604 /*
2605 * This is rare, so we update the MSR here instead of using
2606 * direct_access_msrs. Doing that would require a rdmsr in
2607 * svm_vcpu_put.
2608 */
2609 svm->tsc_aux = data;
2610 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2611 break;
a2938c80 2612 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2613 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
a737f256
CD		 2614 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2615 __func__, data);
24e09cbf
JR		 2616 break;
2617 }
2618 if (data & DEBUGCTL_RESERVED_BITS)
2619 return 1;
2620
2621 svm->vmcb->save.dbgctl = data;
06e7852c 2622 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
24e09cbf
JR		 2623 if (data & (1ULL<<0))
2624 svm_enable_lbrv(svm);
2625 else
2626 svm_disable_lbrv(svm);
a2938c80 2627 break;
b286d5d8 2628 case MSR_VM_HSAVE_PA:
e6aa9abd 2629 svm->nested.hsave_msr = data;
62b9abaa 2630 break;
3c5d0a44 2631 case MSR_VM_CR:
4a810181 2632 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2633 case MSR_VM_IGNNE:
a737f256 2634 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3c5d0a44 2635 break;
d1d93fa9
TL		 2636 case MSR_F10H_DECFG: {
2637 struct kvm_msr_entry msr_entry;
2638
2639 msr_entry.index = msr->index;
2640 if (svm_get_msr_feature(&msr_entry))
2641 return 1;
2642
2643 /* Check the supported bits */
2644 if (data & ~msr_entry.data)
2645 return 1;
2646
2647 /* Don't allow the guest to change a bit, #GP */
2648 if (!msr->host_initiated && (data ^ msr_entry.data))
2649 return 1;
2650
2651 svm->msr_decfg = data;
2652 break;
2653 }
44a95dae
SS		 2654 case MSR_IA32_APICBASE:
2655 if (kvm_vcpu_apicv_active(vcpu))
2656 avic_update_vapic_bar(to_svm(vcpu), data);
b2869f28 2657 /* Fall through */
6aa8b732 2658 default:
8fe8ab46 2659 return kvm_set_msr_common(vcpu, msr);
6aa8b732
AK		 2660 }
2661 return 0;
2662}
2663
851ba692 2664static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2665{
1edce0a9 2666 return kvm_emulate_wrmsr(&svm->vcpu);
6aa8b732
AK		 2667}
2668
851ba692 2669static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2670{
e756fc62 2671 if (svm->vmcb->control.exit_info_1)
851ba692 2672 return wrmsr_interception(svm);
6aa8b732 2673 else
851ba692 2674 return rdmsr_interception(svm);
6aa8b732
AK		 2675}
2676
851ba692 2677static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2678{
3842d135 2679 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2680 svm_clear_vintr(svm);
f3515dc3
SS		 2681
2682 /*
2683 * For AVIC, the only reason to end up here is ExtINTs.
2684 * In this case AVIC was temporarily disabled for
2685 * requesting the IRQ window and we have to re-enable it.
2686 */
2687 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2688
675acb75 2689 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2690 return 1;
2691}
2692
565d0998
ML		 2693static int pause_interception(struct vcpu_svm *svm)
2694{
de63ad4c
LM		 2695 struct kvm_vcpu *vcpu = &svm->vcpu;
2696 bool in_kernel = (svm_get_cpl(vcpu) == 0);
2697
8566ac8b
BM		 2698 if (pause_filter_thresh)
2699 grow_ple_window(vcpu);
2700
de63ad4c 2701 kvm_vcpu_on_spin(vcpu, in_kernel);
565d0998
ML		 2702 return 1;
2703}
2704
87c00572
GS		 2705static int nop_interception(struct vcpu_svm *svm)
2706{
b742c1e6 2707 return kvm_skip_emulated_instruction(&(svm->vcpu));
87c00572
GS		 2708}
2709
2710static int monitor_interception(struct vcpu_svm *svm)
2711{
2712 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2713 return nop_interception(svm);
2714}
2715
2716static int mwait_interception(struct vcpu_svm *svm)
2717{
2718 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2719 return nop_interception(svm);
2720}
2721
09941fbb 2722static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
7ff76d58
AP		 2723 [SVM_EXIT_READ_CR0] = cr_interception,
2724 [SVM_EXIT_READ_CR3] = cr_interception,
2725 [SVM_EXIT_READ_CR4] = cr_interception,
2726 [SVM_EXIT_READ_CR8] = cr_interception,
5e57518d 2727 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
628afd2a 2728 [SVM_EXIT_WRITE_CR0] = cr_interception,
7ff76d58
AP		 2729 [SVM_EXIT_WRITE_CR3] = cr_interception,
2730 [SVM_EXIT_WRITE_CR4] = cr_interception,
e0231715 2731 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
cae3797a
AP		 2732 [SVM_EXIT_READ_DR0] = dr_interception,
2733 [SVM_EXIT_READ_DR1] = dr_interception,
2734 [SVM_EXIT_READ_DR2] = dr_interception,
2735 [SVM_EXIT_READ_DR3] = dr_interception,
2736 [SVM_EXIT_READ_DR4] = dr_interception,
2737 [SVM_EXIT_READ_DR5] = dr_interception,
2738 [SVM_EXIT_READ_DR6] = dr_interception,
2739 [SVM_EXIT_READ_DR7] = dr_interception,
2740 [SVM_EXIT_WRITE_DR0] = dr_interception,
2741 [SVM_EXIT_WRITE_DR1] = dr_interception,
2742 [SVM_EXIT_WRITE_DR2] = dr_interception,
2743 [SVM_EXIT_WRITE_DR3] = dr_interception,
2744 [SVM_EXIT_WRITE_DR4] = dr_interception,
2745 [SVM_EXIT_WRITE_DR5] = dr_interception,
2746 [SVM_EXIT_WRITE_DR6] = dr_interception,
2747 [SVM_EXIT_WRITE_DR7] = dr_interception,
d0bfb940
JK		 2748 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2749 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2750 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715 2751 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
e0231715 2752 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
54a20552 2753 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
9718420e 2754 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
e0231715 2755 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2756 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2757 [SVM_EXIT_SMI] = nop_on_interception,
2758 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2759 [SVM_EXIT_VINTR] = interrupt_window_interception,
332b56e4 2760 [SVM_EXIT_RDPMC] = rdpmc_interception,
6aa8b732 2761 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2762 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2763 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2764 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2765 [SVM_EXIT_HLT] = halt_interception,
a7052897 2766 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2767 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2768 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2769 [SVM_EXIT_MSR] = msr_interception,
2770 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2771 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2772 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2773 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2774 [SVM_EXIT_VMLOAD] = vmload_interception,
2775 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2776 [SVM_EXIT_STGI] = stgi_interception,
2777 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2778 [SVM_EXIT_SKINIT] = skinit_interception,
dab429a7 2779 [SVM_EXIT_WBINVD] = wbinvd_interception,
87c00572
GS		 2780 [SVM_EXIT_MONITOR] = monitor_interception,
2781 [SVM_EXIT_MWAIT] = mwait_interception,
81dd35d4 2782 [SVM_EXIT_XSETBV] = xsetbv_interception,
0cb8410b 2783 [SVM_EXIT_RDPRU] = rdpru_interception,
d0006530 2784 [SVM_EXIT_NPF] = npf_interception,
7607b717 2785 [SVM_EXIT_RSM] = rsm_interception,
18f40c53
SS		 2786 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2787 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
6aa8b732
AK		 2788};
2789
ae8cc059 2790static void dump_vmcb(struct kvm_vcpu *vcpu)
3f10c846
JR		 2791{
2792 struct vcpu_svm *svm = to_svm(vcpu);
2793 struct vmcb_control_area *control = &svm->vmcb->control;
2794 struct vmcb_save_area *save = &svm->vmcb->save;
2795
6f2f8453
PB		 2796 if (!dump_invalid_vmcb) {
2797 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2798 return;
2799 }
2800
3f10c846 2801 pr_err("VMCB Control Area:\n");
ae8cc059
JP		 2802 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2803 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2804 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2805 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2806 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2807 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2808 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
1d8fb44a
BM		 2809 pr_err("%-20s%d\n", "pause filter threshold:",
2810 control->pause_filter_thresh);
ae8cc059
JP		 2811 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2812 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2813 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2814 pr_err("%-20s%d\n", "asid:", control->asid);
2815 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2816 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2817 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2818 pr_err("%-20s%08x\n", "int_state:", control->int_state);
2819 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2820 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2821 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2822 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2823 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2824 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2825 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
44a95dae 2826 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
ae8cc059
JP		 2827 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2828 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
0dc92119 2829 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
ae8cc059 2830 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
44a95dae
SS		 2831 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2832 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2833 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3f10c846 2834 pr_err("VMCB State Save Area:\n");
ae8cc059
JP		 2835 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2836 "es:",
2837 save->es.selector, save->es.attrib,
2838 save->es.limit, save->es.base);
2839 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2840 "cs:",
2841 save->cs.selector, save->cs.attrib,
2842 save->cs.limit, save->cs.base);
2843 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2844 "ss:",
2845 save->ss.selector, save->ss.attrib,
2846 save->ss.limit, save->ss.base);
2847 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2848 "ds:",
2849 save->ds.selector, save->ds.attrib,
2850 save->ds.limit, save->ds.base);
2851 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2852 "fs:",
2853 save->fs.selector, save->fs.attrib,
2854 save->fs.limit, save->fs.base);
2855 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2856 "gs:",
2857 save->gs.selector, save->gs.attrib,
2858 save->gs.limit, save->gs.base);
2859 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2860 "gdtr:",
2861 save->gdtr.selector, save->gdtr.attrib,
2862 save->gdtr.limit, save->gdtr.base);
2863 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2864 "ldtr:",
2865 save->ldtr.selector, save->ldtr.attrib,
2866 save->ldtr.limit, save->ldtr.base);
2867 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2868 "idtr:",
2869 save->idtr.selector, save->idtr.attrib,
2870 save->idtr.limit, save->idtr.base);
2871 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2872 "tr:",
2873 save->tr.selector, save->tr.attrib,
2874 save->tr.limit, save->tr.base);
3f10c846
JR		 2875 pr_err("cpl: %d efer: %016llx\n",
2876 save->cpl, save->efer);
ae8cc059
JP		 2877 pr_err("%-15s %016llx %-13s %016llx\n",
2878 "cr0:", save->cr0, "cr2:", save->cr2);
2879 pr_err("%-15s %016llx %-13s %016llx\n",
2880 "cr3:", save->cr3, "cr4:", save->cr4);
2881 pr_err("%-15s %016llx %-13s %016llx\n",
2882 "dr6:", save->dr6, "dr7:", save->dr7);
2883 pr_err("%-15s %016llx %-13s %016llx\n",
2884 "rip:", save->rip, "rflags:", save->rflags);
2885 pr_err("%-15s %016llx %-13s %016llx\n",
2886 "rsp:", save->rsp, "rax:", save->rax);
2887 pr_err("%-15s %016llx %-13s %016llx\n",
2888 "star:", save->star, "lstar:", save->lstar);
2889 pr_err("%-15s %016llx %-13s %016llx\n",
2890 "cstar:", save->cstar, "sfmask:", save->sfmask);
2891 pr_err("%-15s %016llx %-13s %016llx\n",
2892 "kernel_gs_base:", save->kernel_gs_base,
2893 "sysenter_cs:", save->sysenter_cs);
2894 pr_err("%-15s %016llx %-13s %016llx\n",
2895 "sysenter_esp:", save->sysenter_esp,
2896 "sysenter_eip:", save->sysenter_eip);
2897 pr_err("%-15s %016llx %-13s %016llx\n",
2898 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2899 pr_err("%-15s %016llx %-13s %016llx\n",
2900 "br_from:", save->br_from, "br_to:", save->br_to);
2901 pr_err("%-15s %016llx %-13s %016llx\n",
2902 "excp_from:", save->last_excp_from,
2903 "excp_to:", save->last_excp_to);
3f10c846
JR		 2904}
2905
586f9607
AK		 2906static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2907{
2908 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2909
2910 *info1 = control->exit_info_1;
2911 *info2 = control->exit_info_2;
2912}
2913
404d5d7b 2914static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6aa8b732 2915{
04d2cc77 2916 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2917 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2918 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2919
8b89fe1f
PB		 2920 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2921
4ee546b4 2922 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 2923 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2924 if (npt_enabled)
2925 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2926
36e2e983
PB		 2927 svm_complete_interrupts(svm);
2928
2030753d 2929 if (is_guest_mode(vcpu)) {
410e4d57
JR		 2930 int vmexit;
2931
d8cabddf
JR		 2932 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2933 svm->vmcb->control.exit_info_1,
2934 svm->vmcb->control.exit_info_2,
2935 svm->vmcb->control.exit_int_info,
e097e5ff
SH		 2936 svm->vmcb->control.exit_int_info_err,
2937 KVM_ISA_SVM);
d8cabddf 2938
410e4d57
JR		 2939 vmexit = nested_svm_exit_special(svm);
2940
2941 if (vmexit == NESTED_EXIT_CONTINUE)
2942 vmexit = nested_svm_exit_handled(svm);
2943
2944 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2945 return 1;
cf74a78b
AG		 2946 }
2947
04d2cc77
AK		 2948 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2949 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2950 kvm_run->fail_entry.hardware_entry_failure_reason
2951 = svm->vmcb->control.exit_code;
8a14fe4f 2952 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3f10c846 2953 dump_vmcb(vcpu);
04d2cc77
AK		 2954 return 0;
2955 }
2956
a2fa3e9f 2957 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2958 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 2959 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2960 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6614c7d0 2961 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
6aa8b732 2962 "exit_code 0x%x\n",
b8688d51 2963 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2964 exit_code);
2965
404d5d7b 2966 if (exit_fastpath != EXIT_FASTPATH_NONE)
1e9e2622 2967 return 1;
404d5d7b
WL		 2968
2969 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2970 || !svm_exit_handlers[exit_code]) {
7396d337
LA		 2971 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2972 dump_vmcb(vcpu);
2973 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2974 vcpu->run->internal.suberror =
2975 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
1aa561b1 2976 vcpu->run->internal.ndata = 2;
7396d337 2977 vcpu->run->internal.data[0] = exit_code;
8a14fe4f 2978 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
7396d337 2979 return 0;
6aa8b732
AK		 2980 }
2981
3dcb2a3f
AA		 2982#ifdef CONFIG_RETPOLINE
2983 if (exit_code == SVM_EXIT_MSR)
2984 return msr_interception(svm);
2985 else if (exit_code == SVM_EXIT_VINTR)
2986 return interrupt_window_interception(svm);
2987 else if (exit_code == SVM_EXIT_INTR)
2988 return intr_interception(svm);
2989 else if (exit_code == SVM_EXIT_HLT)
2990 return halt_interception(svm);
2991 else if (exit_code == SVM_EXIT_NPF)
2992 return npf_interception(svm);
2993#endif
851ba692 2994 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2995}
2996
2997static void reload_tss(struct kvm_vcpu *vcpu)
2998{
73cd6e5f 2999 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
6aa8b732 3000
0fe1e009 3001 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3002 load_TR_desc();
3003}
3004
e756fc62 3005static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732 3006{
73cd6e5f 3007 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
6aa8b732 3008
70cd94e6 3009 if (sev_guest(svm->vcpu.kvm))
73cd6e5f 3010 return pre_sev_run(svm, svm->vcpu.cpu);
70cd94e6 3011
4b656b12 3012 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3013 if (svm->asid_generation != sd->asid_generation)
3014 new_asid(svm, sd);
6aa8b732
AK		 3015}
3016
95ba8273
GN		 3017static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3018{
3019 struct vcpu_svm *svm = to_svm(vcpu);
3020
3021 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3022 vcpu->arch.hflags |= HF_NMI_MASK;
a284ba56 3023 svm_set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3024 ++vcpu->stat.nmi_injections;
3025}
6aa8b732 3026
66fd3f7f 3027static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3028{
3029 struct vcpu_svm *svm = to_svm(vcpu);
3030
2af9194d 3031 BUG_ON(!(gif_set(svm)));
cf74a78b 3032
9fb2d2b4
GN		 3033 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3034 ++vcpu->stat.irq_injections;
3035
219b65dc
AG		 3036 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3037 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3038}
3039
95ba8273 3040static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3041{
3042 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3043
01c3b2b5 3044 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3045 return;
3046
596f3142
RK		 3047 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3048
95ba8273 3049 if (irr == -1)
aaacfc9a
JR		 3050 return;
3051
95ba8273 3052 if (tpr >= irr)
4ee546b4 3053 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3054}
aaacfc9a 3055
cae96af1 3056bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
95ba8273
GN		 3057{
3058 struct vcpu_svm *svm = to_svm(vcpu);
3059 struct vmcb *vmcb = svm->vmcb;
88c604b6 3060 bool ret;
9c3d370a 3061
cae96af1 3062 if (!gif_set(svm))
bbdad0b5
PB		 3063 return true;
3064
cae96af1
PB		 3065 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3066 return false;
3067
3068 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3069 (svm->vcpu.arch.hflags & HF_NMI_MASK);
924584cc
JR		 3070
3071 return ret;
aaacfc9a
JR		 3072}
3073
c9d40913 3074static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3075{
3076 struct vcpu_svm *svm = to_svm(vcpu);
3077 if (svm->nested.nested_run_pending)
c9d40913 3078 return -EBUSY;
cae96af1 3079
c300ab9f
PB		 3080 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3081 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
c9d40913 3082 return -EBUSY;
c300ab9f
PB		 3083
3084 return !svm_nmi_blocked(vcpu);
cae96af1
PB		 3085}
3086
3cfc3092
JK		 3087static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3088{
3089 struct vcpu_svm *svm = to_svm(vcpu);
3090
3091 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3092}
3093
3094static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3095{
3096 struct vcpu_svm *svm = to_svm(vcpu);
3097
3098 if (masked) {
3099 svm->vcpu.arch.hflags |= HF_NMI_MASK;
a284ba56 3100 svm_set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3101 } else {
3102 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
a284ba56 3103 svm_clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3104 }
3105}
3106
cae96af1 3107bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
78646121
GN		 3108{
3109 struct vcpu_svm *svm = to_svm(vcpu);
3110 struct vmcb *vmcb = svm->vmcb;
7fcdb510 3111
fc6f7c03 3112 if (!gif_set(svm))
cae96af1 3113 return true;
7fcdb510 3114
fc6f7c03
PB		 3115 if (is_guest_mode(vcpu)) {
3116 /* As long as interrupts are being delivered... */
e9fd761a 3117 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
08245e6d 3118 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
fc6f7c03
PB		 3119 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3120 return true;
3121
3122 /* ... vmexits aren't blocked by the interrupt shadow */
3123 if (nested_exit_on_intr(svm))
3124 return false;
3125 } else {
3126 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3127 return true;
3128 }
3129
3130 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
cae96af1
PB		 3131}
3132
c9d40913 3133static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3134{
3135 struct vcpu_svm *svm = to_svm(vcpu);
3136 if (svm->nested.nested_run_pending)
c9d40913 3137 return -EBUSY;
cae96af1 3138
c300ab9f
PB		 3139 /*
3140 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3141 * e.g. if the IRQ arrived asynchronously after checking nested events.
3142 */
3143 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
c9d40913 3144 return -EBUSY;
c300ab9f
PB		 3145
3146 return !svm_interrupt_blocked(vcpu);
78646121
GN		 3147}
3148
c9a7953f 3149static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3150{
219b65dc 3151 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3152
e0231715
JR		 3153 /*
3154 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3155 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3156 * get that intercept, this function will be called again though and
640bd6e5
JN		 3157 * we'll get the vintr intercept. However, if the vGIF feature is
3158 * enabled, the STGI interception will not occur. Enable the irq
3159 * window under the assumption that the hardware will set the GIF.
e0231715 3160 */
b518ba9f 3161 if (vgif_enabled(svm) || gif_set(svm)) {
f3515dc3
SS		 3162 /*
3163 * IRQ window is not needed when AVIC is enabled,
3164 * unless we have pending ExtINT since it cannot be injected
3165 * via AVIC. In such case, we need to temporarily disable AVIC,
3166 * and fallback to injecting IRQ via V_IRQ.
3167 */
3168 svm_toggle_avic_for_irq_window(vcpu, false);
219b65dc 3169 svm_set_vintr(svm);
219b65dc 3170 }
85f455f7
ED		 3171}
3172
c9a7953f 3173static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3174{
04d2cc77 3175 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3176
44c11430
GN		 3177 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3178 == HF_NMI_MASK)
c9a7953f 3179 return; /* IRET will cause a vm exit */
44c11430 3180
640bd6e5
JN		 3181 if (!gif_set(svm)) {
3182 if (vgif_enabled(svm))
a284ba56 3183 svm_set_intercept(svm, INTERCEPT_STGI);
1a5e1852 3184 return; /* STGI will cause a vm exit */
640bd6e5 3185 }
1a5e1852 3186
e0231715
JR		 3187 /*
3188 * Something prevents NMI from been injected. Single step over possible
3189 * problem (IRET or exception injection or interrupt shadow)
3190 */
ab2f4d73 3191 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
6be7d306 3192 svm->nmi_singlestep = true;
44c11430 3193 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
c1150d8c
DL		 3194}
3195
cbc94022
IE		 3196static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3197{
3198 return 0;
3199}
3200
2ac52ab8
SC		 3201static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3202{
3203 return 0;
3204}
3205
f55ac304 3206void svm_flush_tlb(struct kvm_vcpu *vcpu)
d9e368d6 3207{
38e5e92f
JR		 3208 struct vcpu_svm *svm = to_svm(vcpu);
3209
4a41e43c
SC		 3210 /*
3211 * Flush only the current ASID even if the TLB flush was invoked via
3212 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3213 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3214 * unconditionally does a TLB flush on both nested VM-Enter and nested
3215 * VM-Exit (via kvm_mmu_reset_context()).
3216 */
38e5e92f
JR		 3217 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3218 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3219 else
3220 svm->asid_generation--;
d9e368d6
AK		 3221}
3222
faff8758
JS		 3223static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3224{
3225 struct vcpu_svm *svm = to_svm(vcpu);
3226
3227 invlpga(gva, svm->vmcb->control.asid);
3228}
3229
04d2cc77
AK		 3230static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3231{
3232}
3233
d7bf8221
JR		 3234static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3235{
3236 struct vcpu_svm *svm = to_svm(vcpu);
3237
01c3b2b5 3238 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3239 return;
3240
4ee546b4 3241 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3242 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3243 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3244 }
3245}
3246
649d6864
JR		 3247static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3248{
3249 struct vcpu_svm *svm = to_svm(vcpu);
3250 u64 cr8;
3251
01c3b2b5 3252 if (nested_svm_virtualize_tpr(vcpu) ||
3bbf3565 3253 kvm_vcpu_apicv_active(vcpu))
88ab24ad
JR		 3254 return;
3255
649d6864
JR		 3256 cr8 = kvm_get_cr8(vcpu);
3257 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3258 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3259}
3260
9222be18
GN		 3261static void svm_complete_interrupts(struct vcpu_svm *svm)
3262{
3263 u8 vector;
3264 int type;
3265 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3266 unsigned int3_injected = svm->int3_injected;
3267
3268 svm->int3_injected = 0;
9222be18 3269
bd3d1ec3
AK		 3270 /*
3271 * If we've made progress since setting HF_IRET_MASK, we've
3272 * executed an IRET and can allow NMI injection.
3273 */
3274 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3275 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
44c11430 3276 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3277 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3278 }
44c11430 3279
9222be18
GN		 3280 svm->vcpu.arch.nmi_injected = false;
3281 kvm_clear_exception_queue(&svm->vcpu);
3282 kvm_clear_interrupt_queue(&svm->vcpu);
3283
3284 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3285 return;
3286
3842d135
AK		 3287 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3288
9222be18
GN		 3289 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3290 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3291
3292 switch (type) {
3293 case SVM_EXITINTINFO_TYPE_NMI:
3294 svm->vcpu.arch.nmi_injected = true;
3295 break;
3296 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3297 /*
3298 * In case of software exceptions, do not reinject the vector,
3299 * but re-execute the instruction instead. Rewind RIP first
3300 * if we emulated INT3 before.
3301 */
3302 if (kvm_exception_is_soft(vector)) {
3303 if (vector == BP_VECTOR && int3_injected &&
3304 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3305 kvm_rip_write(&svm->vcpu,
3306 kvm_rip_read(&svm->vcpu) -
3307 int3_injected);
9222be18 3308 break;
66b7138f 3309 }
9222be18
GN		 3310 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3311 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3312 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3313
3314 } else
ce7ddec4 3315 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3316 break;
3317 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3318 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3319 break;
3320 default:
3321 break;
3322 }
3323}
3324
b463a6f7
AK		 3325static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3326{
3327 struct vcpu_svm *svm = to_svm(vcpu);
3328 struct vmcb_control_area *control = &svm->vmcb->control;
3329
3330 control->exit_int_info = control->event_inj;
3331 control->exit_int_info_err = control->event_inj_err;
3332 control->event_inj = 0;
3333 svm_complete_interrupts(svm);
3334}
3335
404d5d7b 3336static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
a9ab13ff
WL		 3337{
3338 if (!is_guest_mode(vcpu) &&
3339 to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3340 to_svm(vcpu)->vmcb->control.exit_info_1)
3341 return handle_fastpath_set_msr_irqoff(vcpu);
3342
3343 return EXIT_FASTPATH_NONE;
3344}
3345
56a87e5d 3346void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
199cd1d7 3347
135961e0
TG		 3348static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3349 struct vcpu_svm *svm)
3350{
3351 /*
3352 * VMENTER enables interrupts (host state), but the kernel state is
3353 * interrupts disabled when this is invoked. Also tell RCU about
3354 * it. This is the same logic as for exit_to_user_mode().
3355 *
3356 * This ensures that e.g. latency analysis on the host observes
3357 * guest mode as interrupt enabled.
3358 *
3359 * guest_enter_irqoff() informs context tracking about the
3360 * transition to guest mode and if enabled adjusts RCU state
3361 * accordingly.
3362 */
3363 instrumentation_begin();
3364 trace_hardirqs_on_prepare();
3365 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3366 instrumentation_end();
3367
3368 guest_enter_irqoff();
3369 lockdep_hardirqs_on(CALLER_ADDR0);
3370
3371 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3372
3373#ifdef CONFIG_X86_64
c3f08ed1 3374 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
135961e0
TG		 3375#else
3376 loadsegment(fs, svm->host.fs);
3377#ifndef CONFIG_X86_32_LAZY_GS
3378 loadsegment(gs, svm->host.gs);
3379#endif
3380#endif
3381
3382 /*
3383 * VMEXIT disables interrupts (host state), but tracing and lockdep
3384 * have them in state 'on' as recorded before entering guest mode.
3385 * Same as enter_from_user_mode().
3386 *
3387 * guest_exit_irqoff() restores host context and reinstates RCU if
3388 * enabled and required.
3389 *
3390 * This needs to be done before the below as native_read_msr()
3391 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3392 * into world and some more.
3393 */
3394 lockdep_hardirqs_off(CALLER_ADDR0);
3395 guest_exit_irqoff();
3396
3397 instrumentation_begin();
3398 trace_hardirqs_off_finish();
3399 instrumentation_end();
3400}
3401
b95273f1 3402static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3403{
404d5d7b 3404 fastpath_t exit_fastpath;
a2fa3e9f 3405 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3406
2041a06a
JR		 3407 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3408 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3409 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3410
a12713c2
LP		 3411 /*
3412 * Disable singlestep if we're injecting an interrupt/exception.
3413 * We don't want our modified rflags to be pushed on the stack where
3414 * we might not be able to easily reset them if we disabled NMI
3415 * singlestep later.
3416 */
3417 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3418 /*
3419 * Event injection happens before external interrupts cause a
3420 * vmexit and interrupts are disabled here, so smp_send_reschedule
3421 * is enough to force an immediate vmexit.
3422 */
3423 disable_nmi_singlestep(svm);
3424 smp_send_reschedule(vcpu->cpu);
3425 }
3426
e756fc62 3427 pre_svm_run(svm);
6aa8b732 3428
649d6864
JR		 3429 sync_lapic_to_cr8(vcpu);
3430
cda0ffdd 3431 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3432
d67668e9
PB		 3433 /*
3434 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3435 * of a #DB.
3436 */
3437 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3438 svm_set_dr6(svm, vcpu->arch.dr6);
3439 else
3440 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3441
04d2cc77 3442 clgi();
139a12cf 3443 kvm_load_guest_xsave_state(vcpu);
04d2cc77 3444
b6c4bc65
WL		 3445 if (lapic_in_kernel(vcpu) &&
3446 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3447 kvm_wait_lapic_expire(vcpu);
3448
b2ac58f9
KA		 3449 /*
3450 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3451 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3452 * is no need to worry about the conditional branch over the wrmsr
3453 * being speculatively taken.
3454 */
ccbcd267 3455 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
b2ac58f9 3456
135961e0 3457 svm_vcpu_enter_exit(vcpu, svm);
15e6c22f 3458
b2ac58f9
KA		 3459 /*
3460 * We do not use IBRS in the kernel. If this vCPU has used the
3461 * SPEC_CTRL MSR it may have left it on; save the value and
3462 * turn it off. This is much more efficient than blindly adding
3463 * it to the atomic save/restore list. Especially as the former
3464 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3465 *
3466 * For non-nested case:
3467 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3468 * save it.
3469 *
3470 * For nested case:
3471 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3472 * save it.
3473 */
946fbbc1 3474 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
ecb586bd 3475 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b2ac58f9 3476
6aa8b732
AK		 3477 reload_tss(vcpu);
3478
024d83ca
TG		 3479 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3480
13c34e07
AK		 3481 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3482 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3483 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3484 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3485
3781c01c 3486 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3487 kvm_before_interrupt(&svm->vcpu);
3781c01c 3488
139a12cf 3489 kvm_load_host_xsave_state(vcpu);
3781c01c
JR		 3490 stgi();
3491
3492 /* Any pending NMI will happen here */
a9ab13ff 3493 exit_fastpath = svm_exit_handlers_fastpath(vcpu);
3781c01c
JR		 3494
3495 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3496 kvm_after_interrupt(&svm->vcpu);
3781c01c 3497
d7bf8221
JR		 3498 sync_cr8_to_lapic(vcpu);
3499
a2fa3e9f 3500 svm->next_rip = 0;
2d8a42be
PB		 3501 if (is_guest_mode(&svm->vcpu)) {
3502 sync_nested_vmcb_control(svm);
3503 svm->nested.nested_run_pending = 0;
3504 }
9222be18 3505
38e5e92f
JR		 3506 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3507
631bc487
GN		 3508 /* if exit due to PF check for async PF */
3509 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
68fd66f1
VK		 3510 svm->vcpu.arch.apf.host_apf_flags =
3511 kvm_read_and_reset_apf_flags();
631bc487 3512
6de4f3ad
AK		 3513 if (npt_enabled) {
3514 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3515 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3516 }
fe5913e4
JR		 3517
3518 /*
3519 * We need to handle MC intercepts here before the vcpu has a chance to
3520 * change the physical cpu
3521 */
3522 if (unlikely(svm->vmcb->control.exit_code ==
3523 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3524 svm_handle_mce(svm);
8d28fec4 3525
06e7852c 3526 vmcb_mark_all_clean(svm->vmcb);
a9ab13ff 3527 return exit_fastpath;
6aa8b732
AK		 3528}
3529
727a7e27 3530static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root)
6aa8b732 3531{
a2fa3e9f 3532 struct vcpu_svm *svm = to_svm(vcpu);
689f3bf2 3533 unsigned long cr3;
a2fa3e9f 3534
689f3bf2
PB		 3535 cr3 = __sme_set(root);
3536 if (npt_enabled) {
3537 svm->vmcb->control.nested_cr3 = cr3;
06e7852c 3538 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0 3539
689f3bf2 3540 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
978ce583
PB		 3541 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3542 return;
3543 cr3 = vcpu->arch.cr3;
689f3bf2 3544 }
1c97f0a0 3545
978ce583 3546 svm->vmcb->save.cr3 = cr3;
06e7852c 3547 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0
JR		 3548}
3549
6aa8b732
AK		 3550static int is_disabled(void)
3551{
6031a61c
JR		 3552 u64 vm_cr;
3553
3554 rdmsrl(MSR_VM_CR, vm_cr);
3555 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3556 return 1;
3557
6aa8b732
AK		 3558 return 0;
3559}
3560
102d8325
IM		 3561static void
3562svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3563{
3564 /*
3565 * Patch in the VMMCALL instruction:
3566 */
3567 hypercall[0] = 0x0f;
3568 hypercall[1] = 0x01;
3569 hypercall[2] = 0xd9;
102d8325
IM		 3570}
3571
f257d6dc 3572static int __init svm_check_processor_compat(void)
002c7f7c 3573{
f257d6dc 3574 return 0;
002c7f7c
YS		 3575}
3576
774ead3a
AK		 3577static bool svm_cpu_has_accelerated_tpr(void)
3578{
3579 return false;
3580}
3581
cb97c2d6 3582static bool svm_has_emulated_msr(u32 index)
6d396b55 3583{
e87555e5
VK		 3584 switch (index) {
3585 case MSR_IA32_MCG_EXT_CTL:
95c5c7c7 3586 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
e87555e5
VK		 3587 return false;
3588 default:
3589 break;
3590 }
3591
6d396b55
PB		 3592 return true;
3593}
3594
fc07e76a
PB		 3595static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3596{
3597 return 0;
3598}
3599
7c1b761b 3600static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
0e851880 3601{
6092d3d3
JR		 3602 struct vcpu_svm *svm = to_svm(vcpu);
3603
7204160e 3604 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
96be4e06 3605 boot_cpu_has(X86_FEATURE_XSAVE) &&
7204160e
AL		 3606 boot_cpu_has(X86_FEATURE_XSAVES);
3607
6092d3d3 3608 /* Update nrips enabled cache */
4eb87460
SC		 3609 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3610 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
46781eae
SS		 3611
3612 if (!kvm_vcpu_apicv_active(vcpu))
3613 return;
3614
cc7f5577
OU		 3615 /*
3616 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3617 * is exposed to the guest, disable AVIC.
3618 */
3619 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3620 kvm_request_apicv_update(vcpu->kvm, false,
3621 APICV_INHIBIT_REASON_X2APIC);
9a0bf054
SS		 3622
3623 /*
3624 * Currently, AVIC does not work with nested virtualization.
3625 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3626 */
3627 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3628 kvm_request_apicv_update(vcpu->kvm, false,
3629 APICV_INHIBIT_REASON_NESTED);
0e851880
SY		 3630}
3631
f5f48ee1
SY		 3632static bool svm_has_wbinvd_exit(void)
3633{
3634 return true;
3635}
3636
8061252e 3637#define PRE_EX(exit) { .exit_code = (exit), \
40e19b51 3638 .stage = X86_ICPT_PRE_EXCEPT, }
cfec82cb 3639#define POST_EX(exit) { .exit_code = (exit), \
40e19b51 3640 .stage = X86_ICPT_POST_EXCEPT, }
d7eb8203 3641#define POST_MEM(exit) { .exit_code = (exit), \
40e19b51 3642 .stage = X86_ICPT_POST_MEMACCESS, }
cfec82cb 3643
09941fbb 3644static const struct __x86_intercept {
cfec82cb
JR		 3645 u32 exit_code;
3646 enum x86_intercept_stage stage;
cfec82cb
JR		 3647} x86_intercept_map[] = {
3648 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3649 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3650 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3651 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3652 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3b88e41a
JR		 3653 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3654 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
dee6bb70
JR		 3655 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3656 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3657 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3658 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3659 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3660 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3661 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3662 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
01de8b09
JR		 3663 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3664 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3665 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3666 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3667 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3668 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3669 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3670 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
d7eb8203
JR		 3671 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3672 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3673 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
8061252e
JR		 3674 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3675 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3676 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3677 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3678 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3679 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3680 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3681 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3682 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
bf608f88
JR		 3683 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3684 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3685 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3686 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3687 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3688 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3689 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
f6511935
JR		 3690 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3691 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3692 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3693 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
02d4160f 3694 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
cfec82cb
JR		 3695};
3696
8061252e 3697#undef PRE_EX
cfec82cb 3698#undef POST_EX
d7eb8203 3699#undef POST_MEM
cfec82cb 3700
8a76d7f2
JR		 3701static int svm_check_intercept(struct kvm_vcpu *vcpu,
3702 struct x86_instruction_info *info,
21f1b8f2
SC		 3703 enum x86_intercept_stage stage,
3704 struct x86_exception *exception)
8a76d7f2 3705{
cfec82cb
JR		 3706 struct vcpu_svm *svm = to_svm(vcpu);
3707 int vmexit, ret = X86EMUL_CONTINUE;
3708 struct __x86_intercept icpt_info;
3709 struct vmcb *vmcb = svm->vmcb;
3710
3711 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3712 goto out;
3713
3714 icpt_info = x86_intercept_map[info->intercept];
3715
40e19b51 3716 if (stage != icpt_info.stage)
cfec82cb
JR		 3717 goto out;
3718
3719 switch (icpt_info.exit_code) {
3720 case SVM_EXIT_READ_CR0:
3721 if (info->intercept == x86_intercept_cr_read)
3722 icpt_info.exit_code += info->modrm_reg;
3723 break;
3724 case SVM_EXIT_WRITE_CR0: {
3725 unsigned long cr0, val;
3726 u64 intercept;
3727
3728 if (info->intercept == x86_intercept_cr_write)
3729 icpt_info.exit_code += info->modrm_reg;
3730
62baf44c
JK		 3731 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3732 info->intercept == x86_intercept_clts)
cfec82cb
JR		 3733 break;
3734
e670bf68 3735 intercept = svm->nested.ctl.intercept;
cfec82cb
JR		 3736
3737 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3738 break;
3739
3740 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3741 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3742
3743 if (info->intercept == x86_intercept_lmsw) {
3744 cr0 &= 0xfUL;
3745 val &= 0xfUL;
3746 /* lmsw can't clear PE - catch this here */
3747 if (cr0 & X86_CR0_PE)
3748 val |= X86_CR0_PE;
3749 }
3750
3751 if (cr0 ^ val)
3752 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3753
3754 break;
3755 }
3b88e41a
JR		 3756 case SVM_EXIT_READ_DR0:
3757 case SVM_EXIT_WRITE_DR0:
3758 icpt_info.exit_code += info->modrm_reg;
3759 break;
8061252e
JR		 3760 case SVM_EXIT_MSR:
3761 if (info->intercept == x86_intercept_wrmsr)
3762 vmcb->control.exit_info_1 = 1;
3763 else
3764 vmcb->control.exit_info_1 = 0;
3765 break;
bf608f88
JR		 3766 case SVM_EXIT_PAUSE:
3767 /*
3768 * We get this for NOP only, but pause
3769 * is rep not, check this here
3770 */
3771 if (info->rep_prefix != REPE_PREFIX)
3772 goto out;
49a8afca 3773 break;
f6511935
JR		 3774 case SVM_EXIT_IOIO: {
3775 u64 exit_info;
3776 u32 bytes;
3777
f6511935
JR		 3778 if (info->intercept == x86_intercept_in ||
3779 info->intercept == x86_intercept_ins) {
6cbc5f5a
JK		 3780 exit_info = ((info->src_val & 0xffff) << 16) |
3781 SVM_IOIO_TYPE_MASK;
f6511935 3782 bytes = info->dst_bytes;
6493f157 3783 } else {
6cbc5f5a 3784 exit_info = (info->dst_val & 0xffff) << 16;
6493f157 3785 bytes = info->src_bytes;
f6511935
JR		 3786 }
3787
3788 if (info->intercept == x86_intercept_outs ||
3789 info->intercept == x86_intercept_ins)
3790 exit_info |= SVM_IOIO_STR_MASK;
3791
3792 if (info->rep_prefix)
3793 exit_info |= SVM_IOIO_REP_MASK;
3794
3795 bytes = min(bytes, 4u);
3796
3797 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3798
3799 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3800
3801 vmcb->control.exit_info_1 = exit_info;
3802 vmcb->control.exit_info_2 = info->next_rip;
3803
3804 break;
3805 }
cfec82cb
JR		 3806 default:
3807 break;
3808 }
3809
f104765b
BD		 3810 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3811 if (static_cpu_has(X86_FEATURE_NRIPS))
3812 vmcb->control.next_rip = info->next_rip;
cfec82cb
JR		 3813 vmcb->control.exit_code = icpt_info.exit_code;
3814 vmexit = nested_svm_exit_handled(svm);
3815
3816 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3817 : X86EMUL_CONTINUE;
3818
3819out:
3820 return ret;
8a76d7f2
JR		 3821}
3822
a9ab13ff 3823static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
a547c6db 3824{
a547c6db
YZ		 3825}
3826
ae97a3b8
RK		 3827static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3828{
8566ac8b
BM		 3829 if (pause_filter_thresh)
3830 shrink_ple_window(vcpu);
ae97a3b8
RK		 3831}
3832
74f16909
BP		 3833static void svm_setup_mce(struct kvm_vcpu *vcpu)
3834{
3835 /* [63:9] are reserved. */
3836 vcpu->arch.mcg_cap &= 0x1ff;
3837}
3838
cae96af1 3839bool svm_smi_blocked(struct kvm_vcpu *vcpu)
72d7b374 3840{
05cade71
LP		 3841 struct vcpu_svm *svm = to_svm(vcpu);
3842
3843 /* Per APM Vol.2 15.22.2 "Response to SMI" */
3844 if (!gif_set(svm))
cae96af1
PB		 3845 return true;
3846
3847 return is_smm(vcpu);
3848}
3849
c9d40913 3850static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3851{
3852 struct vcpu_svm *svm = to_svm(vcpu);
3853 if (svm->nested.nested_run_pending)
c9d40913 3854 return -EBUSY;
05cade71 3855
c300ab9f
PB		 3856 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
3857 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
c9d40913 3858 return -EBUSY;
c300ab9f 3859
cae96af1 3860 return !svm_smi_blocked(vcpu);
72d7b374
LP		 3861}
3862
0234bf88
LP		 3863static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3864{
05cade71
LP		 3865 struct vcpu_svm *svm = to_svm(vcpu);
3866 int ret;
3867
3868 if (is_guest_mode(vcpu)) {
3869 /* FED8h - SVM Guest */
3870 put_smstate(u64, smstate, 0x7ed8, 1);
3871 /* FEE0h - SVM Guest VMCB Physical Address */
3872 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3873
3874 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3875 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3876 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3877
3878 ret = nested_svm_vmexit(svm);
3879 if (ret)
3880 return ret;
3881 }
0234bf88
LP		 3882 return 0;
3883}
3884
ed19321f 3885static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 3886{
05cade71
LP		 3887 struct vcpu_svm *svm = to_svm(vcpu);
3888 struct vmcb *nested_vmcb;
8c5fbf1a 3889 struct kvm_host_map map;
ed19321f
SC		 3890 u64 guest;
3891 u64 vmcb;
05cade71 3892
ed19321f
SC		 3893 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3894 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
05cade71 3895
ed19321f 3896 if (guest) {
8c5fbf1a 3897 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
9ec19493 3898 return 1;
8c5fbf1a 3899 nested_vmcb = map.hva;
69c9dfa2
PB		 3900 enter_svm_guest_mode(svm, vmcb, nested_vmcb);
3901 kvm_vcpu_unmap(&svm->vcpu, &map, true);
05cade71 3902 }
9ec19493 3903 return 0;
0234bf88
LP		 3904}
3905
c9d40913 3906static void enable_smi_window(struct kvm_vcpu *vcpu)
cc3d967f
LP		 3907{
3908 struct vcpu_svm *svm = to_svm(vcpu);
3909
3910 if (!gif_set(svm)) {
3911 if (vgif_enabled(svm))
a284ba56 3912 svm_set_intercept(svm, INTERCEPT_STGI);
cc3d967f 3913 /* STGI will cause a vm exit */
c9d40913
PB		 3914 } else {
3915 /* We must be in SMM; RSM will cause a vmexit anyway. */
cc3d967f 3916 }
cc3d967f
LP		 3917}
3918
05d5a486
SB		 3919static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3920{
118154bd
LA		 3921 unsigned long cr4 = kvm_read_cr4(vcpu);
3922 bool smep = cr4 & X86_CR4_SMEP;
3923 bool smap = cr4 & X86_CR4_SMAP;
3924 bool is_user = svm_get_cpl(vcpu) == 3;
05d5a486 3925
e72436bc
PB		 3926 /*
3927 * If RIP is invalid, go ahead with emulation which will cause an
3928 * internal error exit.
3929 */
3930 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3931 return true;
3932
05d5a486 3933 /*
118154bd
LA		 3934 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3935 *
3936 * Errata:
3937 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3938 * possible that CPU microcode implementing DecodeAssist will fail
3939 * to read bytes of instruction which caused #NPF. In this case,
3940 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3941 * return 0 instead of the correct guest instruction bytes.
3942 *
3943 * This happens because CPU microcode reading instruction bytes
3944 * uses a special opcode which attempts to read data using CPL=0
3945 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3946 * fault, it gives up and returns no instruction bytes.
3947 *
3948 * Detection:
3949 * We reach here in case CPU supports DecodeAssist, raised #NPF and
3950 * returned 0 in GuestIntrBytes field of the VMCB.
3951 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3952 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3953 * in case vCPU CPL==3 (Because otherwise guest would have triggered
3954 * a SMEP fault instead of #NPF).
3955 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3956 * As most guests enable SMAP if they have also enabled SMEP, use above
3957 * logic in order to attempt minimize false-positive of detecting errata
3958 * while still preserving all cases semantic correctness.
3959 *
3960 * Workaround:
3961 * To determine what instruction the guest was executing, the hypervisor
3962 * will have to decode the instruction at the instruction pointer.
05d5a486
SB		 3963 *
3964 * In non SEV guest, hypervisor will be able to read the guest
3965 * memory to decode the instruction pointer when insn_len is zero
3966 * so we return true to indicate that decoding is possible.
3967 *
3968 * But in the SEV guest, the guest memory is encrypted with the
3969 * guest specific key and hypervisor will not be able to decode the
3970 * instruction pointer so we will not able to workaround it. Lets
3971 * print the error and request to kill the guest.
3972 */
118154bd 3973 if (smap && (!smep || is_user)) {
05d5a486
SB		 3974 if (!sev_guest(vcpu->kvm))
3975 return true;
3976
118154bd 3977 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
05d5a486
SB		 3978 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3979 }
3980
3981 return false;
3982}
3983
4b9852f4
LA		 3984static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
3985{
3986 struct vcpu_svm *svm = to_svm(vcpu);
3987
3988 /*
3989 * TODO: Last condition latch INIT signals on vCPU when
3990 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
33b22172
PB		 3991 * To properly emulate the INIT intercept,
3992 * svm_check_nested_events() should call nested_svm_vmexit()
3993 * if an INIT signal is pending.
4b9852f4
LA		 3994 */
3995 return !gif_set(svm) ||
3996 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
3997}
3998
eaf78265
JR		 3999static void svm_vm_destroy(struct kvm *kvm)
4000{
4001 avic_vm_destroy(kvm);
4002 sev_vm_destroy(kvm);
4003}
4004
4005static int svm_vm_init(struct kvm *kvm)
4006{
4007 if (avic) {
4008 int ret = avic_vm_init(kvm);
4009 if (ret)
4010 return ret;
4011 }
4012
4013 kvm_apicv_init(kvm, avic);
4014 return 0;
4015}
4016
9c14ee21 4017static struct kvm_x86_ops svm_x86_ops __initdata = {
dd58f3c9 4018 .hardware_unsetup = svm_hardware_teardown,
6aa8b732
AK		 4019 .hardware_enable = svm_hardware_enable,
4020 .hardware_disable = svm_hardware_disable,
774ead3a 4021 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
bc226f07 4022 .has_emulated_msr = svm_has_emulated_msr,
6aa8b732
AK		 4023
4024 .vcpu_create = svm_create_vcpu,
4025 .vcpu_free = svm_free_vcpu,
04d2cc77 4026 .vcpu_reset = svm_vcpu_reset,
6aa8b732 4027
562b6b08 4028 .vm_size = sizeof(struct kvm_svm),
4e19c36f 4029 .vm_init = svm_vm_init,
1654efcb 4030 .vm_destroy = svm_vm_destroy,
44a95dae 4031
04d2cc77 4032 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 4033 .vcpu_load = svm_vcpu_load,
4034 .vcpu_put = svm_vcpu_put,
8221c137
SS		 4035 .vcpu_blocking = svm_vcpu_blocking,
4036 .vcpu_unblocking = svm_vcpu_unblocking,
6aa8b732 4037
a96036b8 4038 .update_bp_intercept = update_bp_intercept,
801e459a 4039 .get_msr_feature = svm_get_msr_feature,
6aa8b732
AK		 4040 .get_msr = svm_get_msr,
4041 .set_msr = svm_set_msr,
4042 .get_segment_base = svm_get_segment_base,
4043 .get_segment = svm_get_segment,
4044 .set_segment = svm_set_segment,
2e4d2653 4045 .get_cpl = svm_get_cpl,
1747fb71 4046 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
6aa8b732 4047 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 4048 .set_cr4 = svm_set_cr4,
4049 .set_efer = svm_set_efer,
4050 .get_idt = svm_get_idt,
4051 .set_idt = svm_set_idt,
4052 .get_gdt = svm_get_gdt,
4053 .set_gdt = svm_set_gdt,
020df079 4054 .set_dr7 = svm_set_dr7,
facb0139 4055 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
6de4f3ad 4056 .cache_reg = svm_cache_reg,
6aa8b732
AK		 4057 .get_rflags = svm_get_rflags,
4058 .set_rflags = svm_set_rflags,
be94f6b7 4059
7780938c 4060 .tlb_flush_all = svm_flush_tlb,
eeeb4f67 4061 .tlb_flush_current = svm_flush_tlb,
faff8758 4062 .tlb_flush_gva = svm_flush_tlb_gva,
72b38320 4063 .tlb_flush_guest = svm_flush_tlb,
6aa8b732 4064
6aa8b732 4065 .run = svm_vcpu_run,
04d2cc77 4066 .handle_exit = handle_exit,
6aa8b732 4067 .skip_emulated_instruction = skip_emulated_instruction,
5ef8acbd 4068 .update_emulated_instruction = NULL,
2809f5d2
GC		 4069 .set_interrupt_shadow = svm_set_interrupt_shadow,
4070 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 4071 .patch_hypercall = svm_patch_hypercall,
2a8067f1 4072 .set_irq = svm_set_irq,
95ba8273 4073 .set_nmi = svm_inject_nmi,
298101da 4074 .queue_exception = svm_queue_exception,
b463a6f7 4075 .cancel_injection = svm_cancel_injection,
78646121 4076 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 4077 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 4078 .get_nmi_mask = svm_get_nmi_mask,
4079 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 4080 .enable_nmi_window = enable_nmi_window,
4081 .enable_irq_window = enable_irq_window,
4082 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 4083 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
d62caabb 4084 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
ef8efd7a 4085 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
2de9d0cc 4086 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
c7c9c56c 4087 .load_eoi_exitmap = svm_load_eoi_exitmap,
44a95dae
SS		 4088 .hwapic_irr_update = svm_hwapic_irr_update,
4089 .hwapic_isr_update = svm_hwapic_isr_update,
fa59cc00 4090 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
be8ca170 4091 .apicv_post_state_restore = avic_post_state_restore,
cbc94022
IE		 4092
4093 .set_tss_addr = svm_set_tss_addr,
2ac52ab8 4094 .set_identity_map_addr = svm_set_identity_map_addr,
67253af5 4095 .get_tdp_level = get_npt_level,
4b12f0de 4096 .get_mt_mask = svm_get_mt_mask,
229456fc 4097
586f9607 4098 .get_exit_info = svm_get_exit_info,
586f9607 4099
7c1b761b 4100 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4e47c7a6 4101
f5f48ee1 4102 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a 4103
326e7425 4104 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
1c97f0a0 4105
727a7e27 4106 .load_mmu_pgd = svm_load_mmu_pgd,
8a76d7f2
JR		 4107
4108 .check_intercept = svm_check_intercept,
95b5a48c 4109 .handle_exit_irqoff = svm_handle_exit_irqoff,
ae97a3b8 4110
d264ee0c
SC		 4111 .request_immediate_exit = __kvm_request_immediate_exit,
4112
ae97a3b8 4113 .sched_in = svm_sched_in,
25462f7f
WH		 4114
4115 .pmu_ops = &amd_pmu_ops,
33b22172
PB		 4116 .nested_ops = &svm_nested_ops,
4117
340d3bc3 4118 .deliver_posted_interrupt = svm_deliver_avic_intr,
17e433b5 4119 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
411b44ba 4120 .update_pi_irte = svm_update_pi_irte,
74f16909 4121 .setup_mce = svm_setup_mce,
0234bf88 4122
72d7b374 4123 .smi_allowed = svm_smi_allowed,
0234bf88
LP		 4124 .pre_enter_smm = svm_pre_enter_smm,
4125 .pre_leave_smm = svm_pre_leave_smm,
cc3d967f 4126 .enable_smi_window = enable_smi_window,
1654efcb
BS		 4127
4128 .mem_enc_op = svm_mem_enc_op,
1e80fdc0
BS		 4129 .mem_enc_reg_region = svm_register_enc_region,
4130 .mem_enc_unreg_region = svm_unregister_enc_region,
57b119da 4131
05d5a486 4132 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4b9852f4
LA		 4133
4134 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
6aa8b732
AK		 4135};
4136
d008dfdb
SC		 4137static struct kvm_x86_init_ops svm_init_ops __initdata = {
4138 .cpu_has_kvm_support = has_svm,
4139 .disabled_by_bios = is_disabled,
4140 .hardware_setup = svm_hardware_setup,
4141 .check_processor_compatibility = svm_check_processor_compat,
4142
4143 .runtime_ops = &svm_x86_ops,
6aa8b732
AK		 4144};
4145
4146static int __init svm_init(void)
4147{
d008dfdb 4148 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
0ee75bea 4149 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 4150}
4151
4152static void __exit svm_exit(void)
4153{
cb498ea2 4154 kvm_exit();
6aa8b732
AK		 4155}
4156
4157module_init(svm_init)
4158module_exit(svm_exit)
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