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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
631bc487 | 34 | #include <asm/kvm_para.h> |
6aa8b732 | 35 | |
63d1142f | 36 | #include <asm/virtext.h> |
229456fc | 37 | #include "trace.h" |
63d1142f | 38 | |
4ecac3fd AK |
39 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
40 | ||
6aa8b732 AK |
41 | MODULE_AUTHOR("Qumranet"); |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | #define IOPM_ALLOC_ORDER 2 | |
45 | #define MSRPM_ALLOC_ORDER 1 | |
46 | ||
6aa8b732 AK |
47 | #define SEG_TYPE_LDT 2 |
48 | #define SEG_TYPE_BUSY_TSS16 3 | |
49 | ||
6bc31bdc AP |
50 | #define SVM_FEATURE_NPT (1 << 0) |
51 | #define SVM_FEATURE_LBRV (1 << 1) | |
52 | #define SVM_FEATURE_SVML (1 << 2) | |
53 | #define SVM_FEATURE_NRIP (1 << 3) | |
54 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) | |
80b7706e | 55 | |
410e4d57 JR |
56 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
57 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
58 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
59 | ||
24e09cbf JR |
60 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
61 | ||
67ec6607 JR |
62 | static bool erratum_383_found __read_mostly; |
63 | ||
6c8166a7 AK |
64 | static const u32 host_save_user_msrs[] = { |
65 | #ifdef CONFIG_X86_64 | |
66 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
67 | MSR_FS_BASE, | |
68 | #endif | |
69 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
70 | }; | |
71 | ||
72 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
73 | ||
74 | struct kvm_vcpu; | |
75 | ||
e6aa9abd JR |
76 | struct nested_state { |
77 | struct vmcb *hsave; | |
78 | u64 hsave_msr; | |
4a810181 | 79 | u64 vm_cr_msr; |
e6aa9abd JR |
80 | u64 vmcb; |
81 | ||
82 | /* These are the merged vectors */ | |
83 | u32 *msrpm; | |
84 | ||
85 | /* gpa pointers to the real vectors */ | |
86 | u64 vmcb_msrpm; | |
ce2ac085 | 87 | u64 vmcb_iopm; |
aad42c64 | 88 | |
cd3ff653 JR |
89 | /* A VMEXIT is required but not yet emulated */ |
90 | bool exit_required; | |
91 | ||
cda00082 JR |
92 | /* |
93 | * If we vmexit during an instruction emulation we need this to restore | |
94 | * the l1 guest rip after the emulation | |
95 | */ | |
96 | unsigned long vmexit_rip; | |
97 | unsigned long vmexit_rsp; | |
98 | unsigned long vmexit_rax; | |
99 | ||
aad42c64 | 100 | /* cache for intercepts of the guest */ |
4ee546b4 | 101 | u32 intercept_cr; |
3aed041a | 102 | u32 intercept_dr; |
aad42c64 JR |
103 | u32 intercept_exceptions; |
104 | u64 intercept; | |
105 | ||
5bd2edc3 JR |
106 | /* Nested Paging related state */ |
107 | u64 nested_cr3; | |
e6aa9abd JR |
108 | }; |
109 | ||
323c3d80 JR |
110 | #define MSRPM_OFFSETS 16 |
111 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
112 | ||
6c8166a7 AK |
113 | struct vcpu_svm { |
114 | struct kvm_vcpu vcpu; | |
115 | struct vmcb *vmcb; | |
116 | unsigned long vmcb_pa; | |
117 | struct svm_cpu_data *svm_data; | |
118 | uint64_t asid_generation; | |
119 | uint64_t sysenter_esp; | |
120 | uint64_t sysenter_eip; | |
121 | ||
122 | u64 next_rip; | |
123 | ||
124 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 125 | struct { |
dacccfdd AK |
126 | u16 fs; |
127 | u16 gs; | |
128 | u16 ldt; | |
afe9e66f AK |
129 | u64 gs_base; |
130 | } host; | |
6c8166a7 AK |
131 | |
132 | u32 *msrpm; | |
6c8166a7 | 133 | |
e6aa9abd | 134 | struct nested_state nested; |
6be7d306 JK |
135 | |
136 | bool nmi_singlestep; | |
66b7138f JK |
137 | |
138 | unsigned int3_injected; | |
139 | unsigned long int3_rip; | |
631bc487 | 140 | u32 apf_reason; |
6c8166a7 AK |
141 | }; |
142 | ||
455716fa JR |
143 | #define MSR_INVALID 0xffffffffU |
144 | ||
ac72a9b7 JR |
145 | static struct svm_direct_access_msrs { |
146 | u32 index; /* Index of the MSR */ | |
147 | bool always; /* True if intercept is always on */ | |
148 | } direct_access_msrs[] = { | |
8c06585d | 149 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
150 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
151 | #ifdef CONFIG_X86_64 | |
152 | { .index = MSR_GS_BASE, .always = true }, | |
153 | { .index = MSR_FS_BASE, .always = true }, | |
154 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
155 | { .index = MSR_LSTAR, .always = true }, | |
156 | { .index = MSR_CSTAR, .always = true }, | |
157 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
158 | #endif | |
159 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
160 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
161 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
162 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
163 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
164 | }; |
165 | ||
709ddebf JR |
166 | /* enable NPT for AMD64 and X86 with PAE */ |
167 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
168 | static bool npt_enabled = true; | |
169 | #else | |
e0231715 | 170 | static bool npt_enabled; |
709ddebf | 171 | #endif |
6c7dac72 JR |
172 | static int npt = 1; |
173 | ||
174 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 175 | |
4b6e4dca | 176 | static int nested = 1; |
236de055 AG |
177 | module_param(nested, int, S_IRUGO); |
178 | ||
44874f84 | 179 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 180 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 181 | |
410e4d57 | 182 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 183 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 184 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
185 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
186 | bool has_error_code, u32 error_code); | |
187 | ||
a2fa3e9f GH |
188 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
189 | { | |
fb3f0f51 | 190 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
191 | } |
192 | ||
384c6368 JR |
193 | static void recalc_intercepts(struct vcpu_svm *svm) |
194 | { | |
195 | struct vmcb_control_area *c, *h; | |
196 | struct nested_state *g; | |
197 | ||
198 | if (!is_guest_mode(&svm->vcpu)) | |
199 | return; | |
200 | ||
201 | c = &svm->vmcb->control; | |
202 | h = &svm->nested.hsave->control; | |
203 | g = &svm->nested; | |
204 | ||
4ee546b4 | 205 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 206 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
207 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
208 | c->intercept = h->intercept | g->intercept; | |
209 | } | |
210 | ||
4ee546b4 RJ |
211 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
212 | { | |
213 | if (is_guest_mode(&svm->vcpu)) | |
214 | return svm->nested.hsave; | |
215 | else | |
216 | return svm->vmcb; | |
217 | } | |
218 | ||
219 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
220 | { | |
221 | struct vmcb *vmcb = get_host_vmcb(svm); | |
222 | ||
223 | vmcb->control.intercept_cr |= (1U << bit); | |
224 | ||
225 | recalc_intercepts(svm); | |
226 | } | |
227 | ||
228 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
229 | { | |
230 | struct vmcb *vmcb = get_host_vmcb(svm); | |
231 | ||
232 | vmcb->control.intercept_cr &= ~(1U << bit); | |
233 | ||
234 | recalc_intercepts(svm); | |
235 | } | |
236 | ||
237 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
238 | { | |
239 | struct vmcb *vmcb = get_host_vmcb(svm); | |
240 | ||
241 | return vmcb->control.intercept_cr & (1U << bit); | |
242 | } | |
243 | ||
3aed041a JR |
244 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
245 | { | |
246 | struct vmcb *vmcb = get_host_vmcb(svm); | |
247 | ||
248 | vmcb->control.intercept_dr |= (1U << bit); | |
249 | ||
250 | recalc_intercepts(svm); | |
251 | } | |
252 | ||
253 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
254 | { | |
255 | struct vmcb *vmcb = get_host_vmcb(svm); | |
256 | ||
257 | vmcb->control.intercept_dr &= ~(1U << bit); | |
258 | ||
259 | recalc_intercepts(svm); | |
260 | } | |
261 | ||
2af9194d JR |
262 | static inline void enable_gif(struct vcpu_svm *svm) |
263 | { | |
264 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
265 | } | |
266 | ||
267 | static inline void disable_gif(struct vcpu_svm *svm) | |
268 | { | |
269 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
270 | } | |
271 | ||
272 | static inline bool gif_set(struct vcpu_svm *svm) | |
273 | { | |
274 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
275 | } | |
276 | ||
4866d5e3 | 277 | static unsigned long iopm_base; |
6aa8b732 AK |
278 | |
279 | struct kvm_ldttss_desc { | |
280 | u16 limit0; | |
281 | u16 base0; | |
e0231715 JR |
282 | unsigned base1:8, type:5, dpl:2, p:1; |
283 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
284 | u32 base3; |
285 | u32 zero1; | |
286 | } __attribute__((packed)); | |
287 | ||
288 | struct svm_cpu_data { | |
289 | int cpu; | |
290 | ||
5008fdf5 AK |
291 | u64 asid_generation; |
292 | u32 max_asid; | |
293 | u32 next_asid; | |
6aa8b732 AK |
294 | struct kvm_ldttss_desc *tss_desc; |
295 | ||
296 | struct page *save_area; | |
297 | }; | |
298 | ||
299 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 300 | static uint32_t svm_features; |
6aa8b732 AK |
301 | |
302 | struct svm_init_data { | |
303 | int cpu; | |
304 | int r; | |
305 | }; | |
306 | ||
307 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
308 | ||
9d8f549d | 309 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
310 | #define MSRS_RANGE_SIZE 2048 |
311 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
312 | ||
455716fa JR |
313 | static u32 svm_msrpm_offset(u32 msr) |
314 | { | |
315 | u32 offset; | |
316 | int i; | |
317 | ||
318 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
319 | if (msr < msrpm_ranges[i] || | |
320 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
321 | continue; | |
322 | ||
323 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
324 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
325 | ||
326 | /* Now we have the u8 offset - but need the u32 offset */ | |
327 | return offset / 4; | |
328 | } | |
329 | ||
330 | /* MSR not in any range */ | |
331 | return MSR_INVALID; | |
332 | } | |
333 | ||
6aa8b732 AK |
334 | #define MAX_INST_SIZE 15 |
335 | ||
6aa8b732 AK |
336 | static inline void clgi(void) |
337 | { | |
4ecac3fd | 338 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
339 | } |
340 | ||
341 | static inline void stgi(void) | |
342 | { | |
4ecac3fd | 343 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
344 | } |
345 | ||
346 | static inline void invlpga(unsigned long addr, u32 asid) | |
347 | { | |
e0231715 | 348 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
349 | } |
350 | ||
6aa8b732 AK |
351 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
352 | { | |
a2fa3e9f | 353 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
354 | } |
355 | ||
356 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
357 | { | |
358 | force_new_asid(vcpu); | |
359 | } | |
360 | ||
4b16184c JR |
361 | static int get_npt_level(void) |
362 | { | |
363 | #ifdef CONFIG_X86_64 | |
364 | return PT64_ROOT_LEVEL; | |
365 | #else | |
366 | return PT32E_ROOT_LEVEL; | |
367 | #endif | |
368 | } | |
369 | ||
6aa8b732 AK |
370 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
371 | { | |
6dc696d4 | 372 | vcpu->arch.efer = efer; |
709ddebf | 373 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 374 | efer &= ~EFER_LME; |
6aa8b732 | 375 | |
9962d032 | 376 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
6aa8b732 AK |
377 | } |
378 | ||
6aa8b732 AK |
379 | static int is_external_interrupt(u32 info) |
380 | { | |
381 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
382 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
383 | } | |
384 | ||
2809f5d2 GC |
385 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
386 | { | |
387 | struct vcpu_svm *svm = to_svm(vcpu); | |
388 | u32 ret = 0; | |
389 | ||
390 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 391 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
392 | return ret & mask; |
393 | } | |
394 | ||
395 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
396 | { | |
397 | struct vcpu_svm *svm = to_svm(vcpu); | |
398 | ||
399 | if (mask == 0) | |
400 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
401 | else | |
402 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
403 | ||
404 | } | |
405 | ||
6aa8b732 AK |
406 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
407 | { | |
a2fa3e9f GH |
408 | struct vcpu_svm *svm = to_svm(vcpu); |
409 | ||
6bc31bdc AP |
410 | if (svm->vmcb->control.next_rip != 0) |
411 | svm->next_rip = svm->vmcb->control.next_rip; | |
412 | ||
a2fa3e9f | 413 | if (!svm->next_rip) { |
851ba692 | 414 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != |
f629cf84 GN |
415 | EMULATE_DONE) |
416 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
417 | return; |
418 | } | |
5fdbf976 MT |
419 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
420 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
421 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 422 | |
5fdbf976 | 423 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 424 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
425 | } |
426 | ||
116a4752 | 427 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
428 | bool has_error_code, u32 error_code, |
429 | bool reinject) | |
116a4752 JK |
430 | { |
431 | struct vcpu_svm *svm = to_svm(vcpu); | |
432 | ||
e0231715 JR |
433 | /* |
434 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
435 | * handle the exception | |
436 | */ | |
ce7ddec4 JR |
437 | if (!reinject && |
438 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
439 | return; |
440 | ||
2a6b20b8 | 441 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
442 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
443 | ||
444 | /* | |
445 | * For guest debugging where we have to reinject #BP if some | |
446 | * INT3 is guest-owned: | |
447 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
448 | * raises a fault that is not intercepted. Still better than | |
449 | * failing in all cases. | |
450 | */ | |
451 | skip_emulated_instruction(&svm->vcpu); | |
452 | rip = kvm_rip_read(&svm->vcpu); | |
453 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
454 | svm->int3_injected = rip - old_rip; | |
455 | } | |
456 | ||
116a4752 JK |
457 | svm->vmcb->control.event_inj = nr |
458 | | SVM_EVTINJ_VALID | |
459 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
460 | | SVM_EVTINJ_TYPE_EXEPT; | |
461 | svm->vmcb->control.event_inj_err = error_code; | |
462 | } | |
463 | ||
67ec6607 JR |
464 | static void svm_init_erratum_383(void) |
465 | { | |
466 | u32 low, high; | |
467 | int err; | |
468 | u64 val; | |
469 | ||
1be85a6d | 470 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
471 | return; |
472 | ||
473 | /* Use _safe variants to not break nested virtualization */ | |
474 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
475 | if (err) | |
476 | return; | |
477 | ||
478 | val |= (1ULL << 47); | |
479 | ||
480 | low = lower_32_bits(val); | |
481 | high = upper_32_bits(val); | |
482 | ||
483 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
484 | ||
485 | erratum_383_found = true; | |
486 | } | |
487 | ||
6aa8b732 AK |
488 | static int has_svm(void) |
489 | { | |
63d1142f | 490 | const char *msg; |
6aa8b732 | 491 | |
63d1142f | 492 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 493 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
494 | return 0; |
495 | } | |
496 | ||
6aa8b732 AK |
497 | return 1; |
498 | } | |
499 | ||
500 | static void svm_hardware_disable(void *garbage) | |
501 | { | |
2c8dceeb | 502 | cpu_svm_disable(); |
6aa8b732 AK |
503 | } |
504 | ||
10474ae8 | 505 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
506 | { |
507 | ||
0fe1e009 | 508 | struct svm_cpu_data *sd; |
6aa8b732 | 509 | uint64_t efer; |
89a27f4d | 510 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
511 | struct desc_struct *gdt; |
512 | int me = raw_smp_processor_id(); | |
513 | ||
10474ae8 AG |
514 | rdmsrl(MSR_EFER, efer); |
515 | if (efer & EFER_SVME) | |
516 | return -EBUSY; | |
517 | ||
6aa8b732 | 518 | if (!has_svm()) { |
e6732a5a ZA |
519 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
520 | me); | |
10474ae8 | 521 | return -EINVAL; |
6aa8b732 | 522 | } |
0fe1e009 | 523 | sd = per_cpu(svm_data, me); |
6aa8b732 | 524 | |
0fe1e009 | 525 | if (!sd) { |
e6732a5a | 526 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 527 | me); |
10474ae8 | 528 | return -EINVAL; |
6aa8b732 AK |
529 | } |
530 | ||
0fe1e009 TH |
531 | sd->asid_generation = 1; |
532 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
533 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 534 | |
d6ab1ed4 | 535 | native_store_gdt(&gdt_descr); |
89a27f4d | 536 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 537 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 538 | |
9962d032 | 539 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 540 | |
d0316554 | 541 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 542 | |
67ec6607 JR |
543 | svm_init_erratum_383(); |
544 | ||
10474ae8 | 545 | return 0; |
6aa8b732 AK |
546 | } |
547 | ||
0da1db75 JR |
548 | static void svm_cpu_uninit(int cpu) |
549 | { | |
0fe1e009 | 550 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 551 | |
0fe1e009 | 552 | if (!sd) |
0da1db75 JR |
553 | return; |
554 | ||
555 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
556 | __free_page(sd->save_area); |
557 | kfree(sd); | |
0da1db75 JR |
558 | } |
559 | ||
6aa8b732 AK |
560 | static int svm_cpu_init(int cpu) |
561 | { | |
0fe1e009 | 562 | struct svm_cpu_data *sd; |
6aa8b732 AK |
563 | int r; |
564 | ||
0fe1e009 TH |
565 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
566 | if (!sd) | |
6aa8b732 | 567 | return -ENOMEM; |
0fe1e009 TH |
568 | sd->cpu = cpu; |
569 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 570 | r = -ENOMEM; |
0fe1e009 | 571 | if (!sd->save_area) |
6aa8b732 AK |
572 | goto err_1; |
573 | ||
0fe1e009 | 574 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
575 | |
576 | return 0; | |
577 | ||
578 | err_1: | |
0fe1e009 | 579 | kfree(sd); |
6aa8b732 AK |
580 | return r; |
581 | ||
582 | } | |
583 | ||
ac72a9b7 JR |
584 | static bool valid_msr_intercept(u32 index) |
585 | { | |
586 | int i; | |
587 | ||
588 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
589 | if (direct_access_msrs[i].index == index) | |
590 | return true; | |
591 | ||
592 | return false; | |
593 | } | |
594 | ||
bfc733a7 RR |
595 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
596 | int read, int write) | |
6aa8b732 | 597 | { |
455716fa JR |
598 | u8 bit_read, bit_write; |
599 | unsigned long tmp; | |
600 | u32 offset; | |
6aa8b732 | 601 | |
ac72a9b7 JR |
602 | /* |
603 | * If this warning triggers extend the direct_access_msrs list at the | |
604 | * beginning of the file | |
605 | */ | |
606 | WARN_ON(!valid_msr_intercept(msr)); | |
607 | ||
455716fa JR |
608 | offset = svm_msrpm_offset(msr); |
609 | bit_read = 2 * (msr & 0x0f); | |
610 | bit_write = 2 * (msr & 0x0f) + 1; | |
611 | tmp = msrpm[offset]; | |
612 | ||
613 | BUG_ON(offset == MSR_INVALID); | |
614 | ||
615 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
616 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
617 | ||
618 | msrpm[offset] = tmp; | |
6aa8b732 AK |
619 | } |
620 | ||
f65c229c | 621 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
622 | { |
623 | int i; | |
624 | ||
f65c229c JR |
625 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
626 | ||
ac72a9b7 JR |
627 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
628 | if (!direct_access_msrs[i].always) | |
629 | continue; | |
630 | ||
631 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
632 | } | |
f65c229c JR |
633 | } |
634 | ||
323c3d80 JR |
635 | static void add_msr_offset(u32 offset) |
636 | { | |
637 | int i; | |
638 | ||
639 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
640 | ||
641 | /* Offset already in list? */ | |
642 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 643 | return; |
323c3d80 JR |
644 | |
645 | /* Slot used by another offset? */ | |
646 | if (msrpm_offsets[i] != MSR_INVALID) | |
647 | continue; | |
648 | ||
649 | /* Add offset to list */ | |
650 | msrpm_offsets[i] = offset; | |
651 | ||
652 | return; | |
6aa8b732 | 653 | } |
323c3d80 JR |
654 | |
655 | /* | |
656 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
657 | * increase MSRPM_OFFSETS in this case. | |
658 | */ | |
bfc733a7 | 659 | BUG(); |
6aa8b732 AK |
660 | } |
661 | ||
323c3d80 | 662 | static void init_msrpm_offsets(void) |
f65c229c | 663 | { |
323c3d80 | 664 | int i; |
f65c229c | 665 | |
323c3d80 JR |
666 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
667 | ||
668 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
669 | u32 offset; | |
670 | ||
671 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
672 | BUG_ON(offset == MSR_INVALID); | |
673 | ||
674 | add_msr_offset(offset); | |
675 | } | |
f65c229c JR |
676 | } |
677 | ||
24e09cbf JR |
678 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
679 | { | |
680 | u32 *msrpm = svm->msrpm; | |
681 | ||
682 | svm->vmcb->control.lbr_ctl = 1; | |
683 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
684 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
685 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
686 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
687 | } | |
688 | ||
689 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
690 | { | |
691 | u32 *msrpm = svm->msrpm; | |
692 | ||
693 | svm->vmcb->control.lbr_ctl = 0; | |
694 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
695 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
696 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
697 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
698 | } | |
699 | ||
6aa8b732 AK |
700 | static __init int svm_hardware_setup(void) |
701 | { | |
702 | int cpu; | |
703 | struct page *iopm_pages; | |
f65c229c | 704 | void *iopm_va; |
6aa8b732 AK |
705 | int r; |
706 | ||
6aa8b732 AK |
707 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
708 | ||
709 | if (!iopm_pages) | |
710 | return -ENOMEM; | |
c8681339 AL |
711 | |
712 | iopm_va = page_address(iopm_pages); | |
713 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
714 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
715 | ||
323c3d80 JR |
716 | init_msrpm_offsets(); |
717 | ||
50a37eb4 JR |
718 | if (boot_cpu_has(X86_FEATURE_NX)) |
719 | kvm_enable_efer_bits(EFER_NX); | |
720 | ||
1b2fd70c AG |
721 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
722 | kvm_enable_efer_bits(EFER_FFXSR); | |
723 | ||
236de055 AG |
724 | if (nested) { |
725 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 726 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
727 | } |
728 | ||
3230bb47 | 729 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
730 | r = svm_cpu_init(cpu); |
731 | if (r) | |
f65c229c | 732 | goto err; |
6aa8b732 | 733 | } |
33bd6a0b JR |
734 | |
735 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
736 | ||
2a6b20b8 | 737 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
738 | npt_enabled = false; |
739 | ||
6c7dac72 JR |
740 | if (npt_enabled && !npt) { |
741 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
742 | npt_enabled = false; | |
743 | } | |
744 | ||
18552672 | 745 | if (npt_enabled) { |
e3da3acd | 746 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 747 | kvm_enable_tdp(); |
5f4cb662 JR |
748 | } else |
749 | kvm_disable_tdp(); | |
e3da3acd | 750 | |
6aa8b732 AK |
751 | return 0; |
752 | ||
f65c229c | 753 | err: |
6aa8b732 AK |
754 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
755 | iopm_base = 0; | |
756 | return r; | |
757 | } | |
758 | ||
759 | static __exit void svm_hardware_unsetup(void) | |
760 | { | |
0da1db75 JR |
761 | int cpu; |
762 | ||
3230bb47 | 763 | for_each_possible_cpu(cpu) |
0da1db75 JR |
764 | svm_cpu_uninit(cpu); |
765 | ||
6aa8b732 | 766 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 767 | iopm_base = 0; |
6aa8b732 AK |
768 | } |
769 | ||
770 | static void init_seg(struct vmcb_seg *seg) | |
771 | { | |
772 | seg->selector = 0; | |
773 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 774 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
775 | seg->limit = 0xffff; |
776 | seg->base = 0; | |
777 | } | |
778 | ||
779 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
780 | { | |
781 | seg->selector = 0; | |
782 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
783 | seg->limit = 0xffff; | |
784 | seg->base = 0; | |
785 | } | |
786 | ||
f4e1b3c8 ZA |
787 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
788 | { | |
789 | struct vcpu_svm *svm = to_svm(vcpu); | |
790 | u64 g_tsc_offset = 0; | |
791 | ||
2030753d | 792 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
793 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
794 | svm->nested.hsave->control.tsc_offset; | |
795 | svm->nested.hsave->control.tsc_offset = offset; | |
796 | } | |
797 | ||
798 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
799 | } | |
800 | ||
e48672fa ZA |
801 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
802 | { | |
803 | struct vcpu_svm *svm = to_svm(vcpu); | |
804 | ||
805 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 806 | if (is_guest_mode(vcpu)) |
e48672fa ZA |
807 | svm->nested.hsave->control.tsc_offset += adjustment; |
808 | } | |
809 | ||
e6101a96 | 810 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 811 | { |
e6101a96 JR |
812 | struct vmcb_control_area *control = &svm->vmcb->control; |
813 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 814 | |
bff78274 | 815 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 816 | svm->vcpu.arch.hflags = 0; |
bff78274 | 817 | |
4ee546b4 RJ |
818 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
819 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
820 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
821 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
822 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
823 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
824 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 825 | |
3aed041a JR |
826 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
827 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
828 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
829 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
830 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
831 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
832 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
833 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
834 | ||
835 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
836 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
837 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
838 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
839 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
840 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
841 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
842 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 843 | |
7aa81cc0 | 844 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
845 | (1 << UD_VECTOR) | |
846 | (1 << MC_VECTOR); | |
6aa8b732 AK |
847 | |
848 | ||
e0231715 | 849 | control->intercept = (1ULL << INTERCEPT_INTR) | |
6aa8b732 | 850 | (1ULL << INTERCEPT_NMI) | |
0152527b | 851 | (1ULL << INTERCEPT_SMI) | |
d225157b | 852 | (1ULL << INTERCEPT_SELECTIVE_CR0) | |
6aa8b732 | 853 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 854 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 855 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 856 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
857 | (1ULL << INTERCEPT_INVLPGA) | |
858 | (1ULL << INTERCEPT_IOIO_PROT) | | |
859 | (1ULL << INTERCEPT_MSR_PROT) | | |
860 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 861 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
862 | (1ULL << INTERCEPT_VMRUN) | |
863 | (1ULL << INTERCEPT_VMMCALL) | | |
864 | (1ULL << INTERCEPT_VMLOAD) | | |
865 | (1ULL << INTERCEPT_VMSAVE) | | |
866 | (1ULL << INTERCEPT_STGI) | | |
867 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 868 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 869 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
870 | (1ULL << INTERCEPT_MONITOR) | |
871 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
872 | |
873 | control->iopm_base_pa = iopm_base; | |
f65c229c | 874 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
875 | control->int_ctl = V_INTR_MASKING_MASK; |
876 | ||
877 | init_seg(&save->es); | |
878 | init_seg(&save->ss); | |
879 | init_seg(&save->ds); | |
880 | init_seg(&save->fs); | |
881 | init_seg(&save->gs); | |
882 | ||
883 | save->cs.selector = 0xf000; | |
884 | /* Executable/Readable Code Segment */ | |
885 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
886 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
887 | save->cs.limit = 0xffff; | |
d92899a0 AK |
888 | /* |
889 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
890 | * be consistent with it. | |
891 | * | |
892 | * Replace when we have real mode working for vmx. | |
893 | */ | |
894 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
895 | |
896 | save->gdtr.limit = 0xffff; | |
897 | save->idtr.limit = 0xffff; | |
898 | ||
899 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
900 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
901 | ||
eaa48512 | 902 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 903 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
904 | save->dr7 = 0x400; |
905 | save->rflags = 2; | |
906 | save->rip = 0x0000fff0; | |
5fdbf976 | 907 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 908 | |
e0231715 JR |
909 | /* |
910 | * This is the guest-visible cr0 value. | |
18fa000a | 911 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 912 | */ |
678041ad MT |
913 | svm->vcpu.arch.cr0 = 0; |
914 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 915 | |
66aee91a | 916 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 917 | /* rdx = ?? */ |
709ddebf JR |
918 | |
919 | if (npt_enabled) { | |
920 | /* Setup VMCB for Nested Paging */ | |
921 | control->nested_ctl = 1; | |
a7052897 MT |
922 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
923 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf | 924 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
4ee546b4 RJ |
925 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
926 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 927 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
928 | save->cr3 = 0; |
929 | save->cr4 = 0; | |
930 | } | |
a79d2f18 | 931 | force_new_asid(&svm->vcpu); |
1371d904 | 932 | |
e6aa9abd | 933 | svm->nested.vmcb = 0; |
2af9194d JR |
934 | svm->vcpu.arch.hflags = 0; |
935 | ||
2a6b20b8 | 936 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 ML |
937 | control->pause_filter_count = 3000; |
938 | control->intercept |= (1ULL << INTERCEPT_PAUSE); | |
939 | } | |
940 | ||
2af9194d | 941 | enable_gif(svm); |
6aa8b732 AK |
942 | } |
943 | ||
e00c8cf2 | 944 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
945 | { |
946 | struct vcpu_svm *svm = to_svm(vcpu); | |
947 | ||
e6101a96 | 948 | init_vmcb(svm); |
70433389 | 949 | |
c5af89b6 | 950 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 951 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
952 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
953 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 954 | } |
5fdbf976 MT |
955 | vcpu->arch.regs_avail = ~0; |
956 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
957 | |
958 | return 0; | |
04d2cc77 AK |
959 | } |
960 | ||
fb3f0f51 | 961 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 962 | { |
a2fa3e9f | 963 | struct vcpu_svm *svm; |
6aa8b732 | 964 | struct page *page; |
f65c229c | 965 | struct page *msrpm_pages; |
b286d5d8 | 966 | struct page *hsave_page; |
3d6368ef | 967 | struct page *nested_msrpm_pages; |
fb3f0f51 | 968 | int err; |
6aa8b732 | 969 | |
c16f862d | 970 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
971 | if (!svm) { |
972 | err = -ENOMEM; | |
973 | goto out; | |
974 | } | |
975 | ||
976 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
977 | if (err) | |
978 | goto free_svm; | |
979 | ||
b7af4043 | 980 | err = -ENOMEM; |
6aa8b732 | 981 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 982 | if (!page) |
fb3f0f51 | 983 | goto uninit; |
6aa8b732 | 984 | |
f65c229c JR |
985 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
986 | if (!msrpm_pages) | |
b7af4043 | 987 | goto free_page1; |
3d6368ef AG |
988 | |
989 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
990 | if (!nested_msrpm_pages) | |
b7af4043 | 991 | goto free_page2; |
f65c229c | 992 | |
b286d5d8 AG |
993 | hsave_page = alloc_page(GFP_KERNEL); |
994 | if (!hsave_page) | |
b7af4043 TY |
995 | goto free_page3; |
996 | ||
e6aa9abd | 997 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 998 | |
b7af4043 TY |
999 | svm->msrpm = page_address(msrpm_pages); |
1000 | svm_vcpu_init_msrpm(svm->msrpm); | |
1001 | ||
e6aa9abd | 1002 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1003 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1004 | |
a2fa3e9f GH |
1005 | svm->vmcb = page_address(page); |
1006 | clear_page(svm->vmcb); | |
1007 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1008 | svm->asid_generation = 0; | |
e6101a96 | 1009 | init_vmcb(svm); |
99e3e30a | 1010 | kvm_write_tsc(&svm->vcpu, 0); |
a2fa3e9f | 1011 | |
10ab25cd JK |
1012 | err = fx_init(&svm->vcpu); |
1013 | if (err) | |
1014 | goto free_page4; | |
1015 | ||
ad312c7c | 1016 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1017 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1018 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1019 | |
fb3f0f51 | 1020 | return &svm->vcpu; |
36241b8c | 1021 | |
10ab25cd JK |
1022 | free_page4: |
1023 | __free_page(hsave_page); | |
b7af4043 TY |
1024 | free_page3: |
1025 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1026 | free_page2: | |
1027 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1028 | free_page1: | |
1029 | __free_page(page); | |
fb3f0f51 RR |
1030 | uninit: |
1031 | kvm_vcpu_uninit(&svm->vcpu); | |
1032 | free_svm: | |
a4770347 | 1033 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1034 | out: |
1035 | return ERR_PTR(err); | |
6aa8b732 AK |
1036 | } |
1037 | ||
1038 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1039 | { | |
a2fa3e9f GH |
1040 | struct vcpu_svm *svm = to_svm(vcpu); |
1041 | ||
fb3f0f51 | 1042 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1043 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1044 | __free_page(virt_to_page(svm->nested.hsave)); |
1045 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1046 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1047 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1048 | } |
1049 | ||
15ad7146 | 1050 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1051 | { |
a2fa3e9f | 1052 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1053 | int i; |
0cc5064d | 1054 | |
0cc5064d | 1055 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1056 | svm->asid_generation = 0; |
0cc5064d | 1057 | } |
94dfbdb3 | 1058 | |
82ca2d10 AK |
1059 | #ifdef CONFIG_X86_64 |
1060 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1061 | #endif | |
dacccfdd AK |
1062 | savesegment(fs, svm->host.fs); |
1063 | savesegment(gs, svm->host.gs); | |
1064 | svm->host.ldt = kvm_read_ldt(); | |
1065 | ||
94dfbdb3 | 1066 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1067 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1068 | } |
1069 | ||
1070 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1071 | { | |
a2fa3e9f | 1072 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1073 | int i; |
1074 | ||
e1beb1d3 | 1075 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1076 | kvm_load_ldt(svm->host.ldt); |
1077 | #ifdef CONFIG_X86_64 | |
1078 | loadsegment(fs, svm->host.fs); | |
1079 | load_gs_index(svm->host.gs); | |
1080 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); | |
1081 | #else | |
1082 | loadsegment(gs, svm->host.gs); | |
1083 | #endif | |
94dfbdb3 | 1084 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1085 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1086 | } |
1087 | ||
6aa8b732 AK |
1088 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1089 | { | |
a2fa3e9f | 1090 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1091 | } |
1092 | ||
1093 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1094 | { | |
a2fa3e9f | 1095 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1096 | } |
1097 | ||
6de4f3ad AK |
1098 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1099 | { | |
1100 | switch (reg) { | |
1101 | case VCPU_EXREG_PDPTR: | |
1102 | BUG_ON(!npt_enabled); | |
ff03a073 | 1103 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3); |
6de4f3ad AK |
1104 | break; |
1105 | default: | |
1106 | BUG(); | |
1107 | } | |
1108 | } | |
1109 | ||
f0b85051 AG |
1110 | static void svm_set_vintr(struct vcpu_svm *svm) |
1111 | { | |
1112 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
1113 | } | |
1114 | ||
1115 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1116 | { | |
1117 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1118 | } | |
1119 | ||
6aa8b732 AK |
1120 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1121 | { | |
a2fa3e9f | 1122 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1123 | |
1124 | switch (seg) { | |
1125 | case VCPU_SREG_CS: return &save->cs; | |
1126 | case VCPU_SREG_DS: return &save->ds; | |
1127 | case VCPU_SREG_ES: return &save->es; | |
1128 | case VCPU_SREG_FS: return &save->fs; | |
1129 | case VCPU_SREG_GS: return &save->gs; | |
1130 | case VCPU_SREG_SS: return &save->ss; | |
1131 | case VCPU_SREG_TR: return &save->tr; | |
1132 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1133 | } | |
1134 | BUG(); | |
8b6d44c7 | 1135 | return NULL; |
6aa8b732 AK |
1136 | } |
1137 | ||
1138 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1139 | { | |
1140 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1141 | ||
1142 | return s->base; | |
1143 | } | |
1144 | ||
1145 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1146 | struct kvm_segment *var, int seg) | |
1147 | { | |
1148 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1149 | ||
1150 | var->base = s->base; | |
1151 | var->limit = s->limit; | |
1152 | var->selector = s->selector; | |
1153 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1154 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1155 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1156 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1157 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1158 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1159 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1160 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1161 | |
e0231715 JR |
1162 | /* |
1163 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1164 | * for cross vendor migration purposes by "not present" |
1165 | */ | |
1166 | var->unusable = !var->present || (var->type == 0); | |
1167 | ||
1fbdc7a5 AP |
1168 | switch (seg) { |
1169 | case VCPU_SREG_CS: | |
1170 | /* | |
1171 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1172 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1173 | * Intel's VMENTRY has a check on the 'G' bit. | |
1174 | */ | |
25022acc | 1175 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1176 | break; |
1177 | case VCPU_SREG_TR: | |
1178 | /* | |
1179 | * Work around a bug where the busy flag in the tr selector | |
1180 | * isn't exposed | |
1181 | */ | |
c0d09828 | 1182 | var->type |= 0x2; |
1fbdc7a5 AP |
1183 | break; |
1184 | case VCPU_SREG_DS: | |
1185 | case VCPU_SREG_ES: | |
1186 | case VCPU_SREG_FS: | |
1187 | case VCPU_SREG_GS: | |
1188 | /* | |
1189 | * The accessed bit must always be set in the segment | |
1190 | * descriptor cache, although it can be cleared in the | |
1191 | * descriptor, the cached bit always remains at 1. Since | |
1192 | * Intel has a check on this, set it here to support | |
1193 | * cross-vendor migration. | |
1194 | */ | |
1195 | if (!var->unusable) | |
1196 | var->type |= 0x1; | |
1197 | break; | |
b586eb02 | 1198 | case VCPU_SREG_SS: |
e0231715 JR |
1199 | /* |
1200 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1201 | * descriptor is left as 1, although the whole segment has |
1202 | * been made unusable. Clear it here to pass an Intel VMX | |
1203 | * entry check when cross vendor migrating. | |
1204 | */ | |
1205 | if (var->unusable) | |
1206 | var->db = 0; | |
1207 | break; | |
1fbdc7a5 | 1208 | } |
6aa8b732 AK |
1209 | } |
1210 | ||
2e4d2653 IE |
1211 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1212 | { | |
1213 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1214 | ||
1215 | return save->cpl; | |
1216 | } | |
1217 | ||
89a27f4d | 1218 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1219 | { |
a2fa3e9f GH |
1220 | struct vcpu_svm *svm = to_svm(vcpu); |
1221 | ||
89a27f4d GN |
1222 | dt->size = svm->vmcb->save.idtr.limit; |
1223 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1224 | } |
1225 | ||
89a27f4d | 1226 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1227 | { |
a2fa3e9f GH |
1228 | struct vcpu_svm *svm = to_svm(vcpu); |
1229 | ||
89a27f4d GN |
1230 | svm->vmcb->save.idtr.limit = dt->size; |
1231 | svm->vmcb->save.idtr.base = dt->address ; | |
6aa8b732 AK |
1232 | } |
1233 | ||
89a27f4d | 1234 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1235 | { |
a2fa3e9f GH |
1236 | struct vcpu_svm *svm = to_svm(vcpu); |
1237 | ||
89a27f4d GN |
1238 | dt->size = svm->vmcb->save.gdtr.limit; |
1239 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1240 | } |
1241 | ||
89a27f4d | 1242 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1243 | { |
a2fa3e9f GH |
1244 | struct vcpu_svm *svm = to_svm(vcpu); |
1245 | ||
89a27f4d GN |
1246 | svm->vmcb->save.gdtr.limit = dt->size; |
1247 | svm->vmcb->save.gdtr.base = dt->address ; | |
6aa8b732 AK |
1248 | } |
1249 | ||
e8467fda AK |
1250 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1251 | { | |
1252 | } | |
1253 | ||
25c4c276 | 1254 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1255 | { |
1256 | } | |
1257 | ||
d225157b AK |
1258 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1259 | { | |
1260 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1261 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1262 | ||
1263 | if (!svm->vcpu.fpu_active) | |
1264 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1265 | else | |
1266 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1267 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1268 | ||
1269 | ||
1270 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1271 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1272 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1273 | } else { |
4ee546b4 RJ |
1274 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1275 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1276 | } |
1277 | } | |
1278 | ||
6aa8b732 AK |
1279 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1280 | { | |
a2fa3e9f GH |
1281 | struct vcpu_svm *svm = to_svm(vcpu); |
1282 | ||
2030753d | 1283 | if (is_guest_mode(vcpu)) { |
7f5d8b56 JR |
1284 | /* |
1285 | * We are here because we run in nested mode, the host kvm | |
1286 | * intercepts cr0 writes but the l1 hypervisor does not. | |
1287 | * But the L1 hypervisor may intercept selective cr0 writes. | |
1288 | * This needs to be checked here. | |
1289 | */ | |
1290 | unsigned long old, new; | |
1291 | ||
1292 | /* Remove bits that would trigger a real cr0 write intercept */ | |
1293 | old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK; | |
1294 | new = cr0 & SVM_CR0_SELECTIVE_MASK; | |
1295 | ||
1296 | if (old == new) { | |
1297 | /* cr0 write with ts and mp unchanged */ | |
1298 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
cda00082 JR |
1299 | if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) { |
1300 | svm->nested.vmexit_rip = kvm_rip_read(vcpu); | |
1301 | svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
1302 | svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
7f5d8b56 | 1303 | return; |
cda00082 | 1304 | } |
7f5d8b56 JR |
1305 | } |
1306 | } | |
1307 | ||
05b3e0c2 | 1308 | #ifdef CONFIG_X86_64 |
f6801dff | 1309 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1310 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1311 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1312 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1313 | } |
1314 | ||
d77c26fc | 1315 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1316 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1317 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1318 | } |
1319 | } | |
1320 | #endif | |
ad312c7c | 1321 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1322 | |
1323 | if (!npt_enabled) | |
1324 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1325 | |
1326 | if (!vcpu->fpu_active) | |
334df50a | 1327 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1328 | /* |
1329 | * re-enable caching here because the QEMU bios | |
1330 | * does not do it - this results in some delay at | |
1331 | * reboot | |
1332 | */ | |
1333 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1334 | svm->vmcb->save.cr0 = cr0; |
d225157b | 1335 | update_cr0_intercept(svm); |
6aa8b732 AK |
1336 | } |
1337 | ||
1338 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1339 | { | |
6394b649 | 1340 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1341 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1342 | ||
1343 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1344 | force_new_asid(vcpu); | |
6394b649 | 1345 | |
ec077263 JR |
1346 | vcpu->arch.cr4 = cr4; |
1347 | if (!npt_enabled) | |
1348 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1349 | cr4 |= host_cr4_mce; |
ec077263 | 1350 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
1351 | } |
1352 | ||
1353 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1354 | struct kvm_segment *var, int seg) | |
1355 | { | |
a2fa3e9f | 1356 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1357 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1358 | ||
1359 | s->base = var->base; | |
1360 | s->limit = var->limit; | |
1361 | s->selector = var->selector; | |
1362 | if (var->unusable) | |
1363 | s->attrib = 0; | |
1364 | else { | |
1365 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1366 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1367 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1368 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1369 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1370 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1371 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1372 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1373 | } | |
1374 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1375 | svm->vmcb->save.cpl |
1376 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1377 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1378 | ||
1379 | } | |
1380 | ||
44c11430 | 1381 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1382 | { |
d0bfb940 JK |
1383 | struct vcpu_svm *svm = to_svm(vcpu); |
1384 | ||
d0bfb940 JK |
1385 | svm->vmcb->control.intercept_exceptions &= |
1386 | ~((1 << DB_VECTOR) | (1 << BP_VECTOR)); | |
44c11430 | 1387 | |
6be7d306 | 1388 | if (svm->nmi_singlestep) |
44c11430 GN |
1389 | svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR); |
1390 | ||
d0bfb940 JK |
1391 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1392 | if (vcpu->guest_debug & | |
1393 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
1394 | svm->vmcb->control.intercept_exceptions |= | |
1395 | 1 << DB_VECTOR; | |
1396 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
1397 | svm->vmcb->control.intercept_exceptions |= | |
1398 | 1 << BP_VECTOR; | |
1399 | } else | |
1400 | vcpu->guest_debug = 0; | |
44c11430 GN |
1401 | } |
1402 | ||
355be0b9 | 1403 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1404 | { |
44c11430 GN |
1405 | struct vcpu_svm *svm = to_svm(vcpu); |
1406 | ||
ae675ef0 JK |
1407 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1408 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1409 | else | |
1410 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1411 | ||
355be0b9 | 1412 | update_db_intercept(vcpu); |
6aa8b732 AK |
1413 | } |
1414 | ||
0fe1e009 | 1415 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1416 | { |
0fe1e009 TH |
1417 | if (sd->next_asid > sd->max_asid) { |
1418 | ++sd->asid_generation; | |
1419 | sd->next_asid = 1; | |
a2fa3e9f | 1420 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1421 | } |
1422 | ||
0fe1e009 TH |
1423 | svm->asid_generation = sd->asid_generation; |
1424 | svm->vmcb->control.asid = sd->next_asid++; | |
6aa8b732 AK |
1425 | } |
1426 | ||
020df079 | 1427 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1428 | { |
42dbaa5a | 1429 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1430 | |
020df079 | 1431 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
1432 | } |
1433 | ||
851ba692 | 1434 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1435 | { |
631bc487 | 1436 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1437 | u32 error_code; |
631bc487 | 1438 | int r = 1; |
6aa8b732 | 1439 | |
631bc487 GN |
1440 | switch (svm->apf_reason) { |
1441 | default: | |
1442 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1443 | |
631bc487 GN |
1444 | trace_kvm_page_fault(fault_address, error_code); |
1445 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1446 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
1447 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); | |
1448 | break; | |
1449 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1450 | svm->apf_reason = 0; | |
1451 | local_irq_disable(); | |
1452 | kvm_async_pf_task_wait(fault_address); | |
1453 | local_irq_enable(); | |
1454 | break; | |
1455 | case KVM_PV_REASON_PAGE_READY: | |
1456 | svm->apf_reason = 0; | |
1457 | local_irq_disable(); | |
1458 | kvm_async_pf_task_wake(fault_address); | |
1459 | local_irq_enable(); | |
1460 | break; | |
1461 | } | |
1462 | return r; | |
6aa8b732 AK |
1463 | } |
1464 | ||
851ba692 | 1465 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1466 | { |
851ba692 AK |
1467 | struct kvm_run *kvm_run = svm->vcpu.run; |
1468 | ||
d0bfb940 | 1469 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1470 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1471 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1472 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1473 | return 1; | |
1474 | } | |
44c11430 | 1475 | |
6be7d306 JK |
1476 | if (svm->nmi_singlestep) { |
1477 | svm->nmi_singlestep = false; | |
44c11430 GN |
1478 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1479 | svm->vmcb->save.rflags &= | |
1480 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1481 | update_db_intercept(&svm->vcpu); | |
1482 | } | |
1483 | ||
1484 | if (svm->vcpu.guest_debug & | |
e0231715 | 1485 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1486 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1487 | kvm_run->debug.arch.pc = | |
1488 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1489 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1490 | return 0; | |
1491 | } | |
1492 | ||
1493 | return 1; | |
d0bfb940 JK |
1494 | } |
1495 | ||
851ba692 | 1496 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1497 | { |
851ba692 AK |
1498 | struct kvm_run *kvm_run = svm->vcpu.run; |
1499 | ||
d0bfb940 JK |
1500 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1501 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1502 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1503 | return 0; | |
1504 | } | |
1505 | ||
851ba692 | 1506 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1507 | { |
1508 | int er; | |
1509 | ||
851ba692 | 1510 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1511 | if (er != EMULATE_DONE) |
7ee5d940 | 1512 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1513 | return 1; |
1514 | } | |
1515 | ||
6b52d186 | 1516 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1517 | { |
6b52d186 | 1518 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 JR |
1519 | u32 excp; |
1520 | ||
2030753d | 1521 | if (is_guest_mode(vcpu)) { |
66a562f7 JR |
1522 | u32 h_excp, n_excp; |
1523 | ||
1524 | h_excp = svm->nested.hsave->control.intercept_exceptions; | |
1525 | n_excp = svm->nested.intercept_exceptions; | |
1526 | h_excp &= ~(1 << NM_VECTOR); | |
1527 | excp = h_excp | n_excp; | |
1528 | } else { | |
1529 | excp = svm->vmcb->control.intercept_exceptions; | |
e0231715 | 1530 | excp &= ~(1 << NM_VECTOR); |
66a562f7 JR |
1531 | } |
1532 | ||
1533 | svm->vmcb->control.intercept_exceptions = excp; | |
1534 | ||
e756fc62 | 1535 | svm->vcpu.fpu_active = 1; |
d225157b | 1536 | update_cr0_intercept(svm); |
6b52d186 | 1537 | } |
a2fa3e9f | 1538 | |
6b52d186 AK |
1539 | static int nm_interception(struct vcpu_svm *svm) |
1540 | { | |
1541 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1542 | return 1; |
7807fa6c AL |
1543 | } |
1544 | ||
67ec6607 JR |
1545 | static bool is_erratum_383(void) |
1546 | { | |
1547 | int err, i; | |
1548 | u64 value; | |
1549 | ||
1550 | if (!erratum_383_found) | |
1551 | return false; | |
1552 | ||
1553 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1554 | if (err) | |
1555 | return false; | |
1556 | ||
1557 | /* Bit 62 may or may not be set for this mce */ | |
1558 | value &= ~(1ULL << 62); | |
1559 | ||
1560 | if (value != 0xb600000000010015ULL) | |
1561 | return false; | |
1562 | ||
1563 | /* Clear MCi_STATUS registers */ | |
1564 | for (i = 0; i < 6; ++i) | |
1565 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1566 | ||
1567 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1568 | if (!err) { | |
1569 | u32 low, high; | |
1570 | ||
1571 | value &= ~(1ULL << 2); | |
1572 | low = lower_32_bits(value); | |
1573 | high = upper_32_bits(value); | |
1574 | ||
1575 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1576 | } | |
1577 | ||
1578 | /* Flush tlb to evict multi-match entries */ | |
1579 | __flush_tlb_all(); | |
1580 | ||
1581 | return true; | |
1582 | } | |
1583 | ||
fe5913e4 | 1584 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1585 | { |
67ec6607 JR |
1586 | if (is_erratum_383()) { |
1587 | /* | |
1588 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1589 | * guest. | |
1590 | */ | |
1591 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1592 | ||
a8eeb04a | 1593 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1594 | |
1595 | return; | |
1596 | } | |
1597 | ||
53371b50 JR |
1598 | /* |
1599 | * On an #MC intercept the MCE handler is not called automatically in | |
1600 | * the host. So do it by hand here. | |
1601 | */ | |
1602 | asm volatile ( | |
1603 | "int $0x12\n"); | |
1604 | /* not sure if we ever come back to this point */ | |
1605 | ||
fe5913e4 JR |
1606 | return; |
1607 | } | |
1608 | ||
1609 | static int mc_interception(struct vcpu_svm *svm) | |
1610 | { | |
53371b50 JR |
1611 | return 1; |
1612 | } | |
1613 | ||
851ba692 | 1614 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1615 | { |
851ba692 AK |
1616 | struct kvm_run *kvm_run = svm->vcpu.run; |
1617 | ||
46fe4ddd JR |
1618 | /* |
1619 | * VMCB is undefined after a SHUTDOWN intercept | |
1620 | * so reinitialize it. | |
1621 | */ | |
a2fa3e9f | 1622 | clear_page(svm->vmcb); |
e6101a96 | 1623 | init_vmcb(svm); |
46fe4ddd JR |
1624 | |
1625 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1626 | return 0; | |
1627 | } | |
1628 | ||
851ba692 | 1629 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1630 | { |
cf8f70bf | 1631 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1632 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1633 | int size, in, string; |
039576c0 | 1634 | unsigned port; |
6aa8b732 | 1635 | |
e756fc62 | 1636 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1637 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1638 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1639 | if (string || in) |
6d77dbfc | 1640 | return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE; |
cf8f70bf | 1641 | |
039576c0 AK |
1642 | port = io_info >> 16; |
1643 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1644 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1645 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1646 | |
1647 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1648 | } |
1649 | ||
851ba692 | 1650 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1651 | { |
1652 | return 1; | |
1653 | } | |
1654 | ||
851ba692 | 1655 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1656 | { |
1657 | ++svm->vcpu.stat.irq_exits; | |
1658 | return 1; | |
1659 | } | |
1660 | ||
851ba692 | 1661 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1662 | { |
1663 | return 1; | |
1664 | } | |
1665 | ||
851ba692 | 1666 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1667 | { |
5fdbf976 | 1668 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1669 | skip_emulated_instruction(&svm->vcpu); |
1670 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1671 | } |
1672 | ||
851ba692 | 1673 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1674 | { |
5fdbf976 | 1675 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1676 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1677 | kvm_emulate_hypercall(&svm->vcpu); |
1678 | return 1; | |
02e235bc AK |
1679 | } |
1680 | ||
5bd2edc3 JR |
1681 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1682 | { | |
1683 | struct vcpu_svm *svm = to_svm(vcpu); | |
1684 | ||
1685 | return svm->nested.nested_cr3; | |
1686 | } | |
1687 | ||
1688 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, | |
1689 | unsigned long root) | |
1690 | { | |
1691 | struct vcpu_svm *svm = to_svm(vcpu); | |
1692 | ||
1693 | svm->vmcb->control.nested_cr3 = root; | |
1694 | force_new_asid(vcpu); | |
1695 | } | |
1696 | ||
6389ee94 AK |
1697 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1698 | struct x86_exception *fault) | |
5bd2edc3 JR |
1699 | { |
1700 | struct vcpu_svm *svm = to_svm(vcpu); | |
1701 | ||
1702 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1703 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1704 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1705 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1706 | |
1707 | nested_svm_vmexit(svm); | |
1708 | } | |
1709 | ||
4b16184c JR |
1710 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1711 | { | |
1712 | int r; | |
1713 | ||
1714 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1715 | ||
1716 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1717 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
1718 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; | |
1719 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1720 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1721 | ||
1722 | return r; | |
1723 | } | |
1724 | ||
1725 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1726 | { | |
1727 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1728 | } | |
1729 | ||
c0725420 AG |
1730 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1731 | { | |
f6801dff | 1732 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1733 | || !is_paging(&svm->vcpu)) { |
1734 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1735 | return 1; | |
1736 | } | |
1737 | ||
1738 | if (svm->vmcb->save.cpl) { | |
1739 | kvm_inject_gp(&svm->vcpu, 0); | |
1740 | return 1; | |
1741 | } | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
cf74a78b AG |
1746 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1747 | bool has_error_code, u32 error_code) | |
1748 | { | |
b8e88bc8 JR |
1749 | int vmexit; |
1750 | ||
2030753d | 1751 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1752 | return 0; |
cf74a78b | 1753 | |
0295ad7d JR |
1754 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1755 | svm->vmcb->control.exit_code_hi = 0; | |
1756 | svm->vmcb->control.exit_info_1 = error_code; | |
1757 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1758 | ||
b8e88bc8 JR |
1759 | vmexit = nested_svm_intercept(svm); |
1760 | if (vmexit == NESTED_EXIT_DONE) | |
1761 | svm->nested.exit_required = true; | |
1762 | ||
1763 | return vmexit; | |
cf74a78b AG |
1764 | } |
1765 | ||
8fe54654 JR |
1766 | /* This function returns true if it is save to enable the irq window */ |
1767 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1768 | { |
2030753d | 1769 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 1770 | return true; |
cf74a78b | 1771 | |
26666957 | 1772 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1773 | return true; |
cf74a78b | 1774 | |
26666957 | 1775 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1776 | return false; |
cf74a78b | 1777 | |
a0a07cd2 GN |
1778 | /* |
1779 | * if vmexit was already requested (by intercepted exception | |
1780 | * for instance) do not overwrite it with "external interrupt" | |
1781 | * vmexit. | |
1782 | */ | |
1783 | if (svm->nested.exit_required) | |
1784 | return false; | |
1785 | ||
197717d5 JR |
1786 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1787 | svm->vmcb->control.exit_info_1 = 0; | |
1788 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1789 | |
cd3ff653 JR |
1790 | if (svm->nested.intercept & 1ULL) { |
1791 | /* | |
1792 | * The #vmexit can't be emulated here directly because this | |
1793 | * code path runs with irqs and preemtion disabled. A | |
1794 | * #vmexit emulation might sleep. Only signal request for | |
1795 | * the #vmexit here. | |
1796 | */ | |
1797 | svm->nested.exit_required = true; | |
236649de | 1798 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 1799 | return false; |
cf74a78b AG |
1800 | } |
1801 | ||
8fe54654 | 1802 | return true; |
cf74a78b AG |
1803 | } |
1804 | ||
887f500c JR |
1805 | /* This function returns true if it is save to enable the nmi window */ |
1806 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1807 | { | |
2030753d | 1808 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
1809 | return true; |
1810 | ||
1811 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1812 | return true; | |
1813 | ||
1814 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1815 | svm->nested.exit_required = true; | |
1816 | ||
1817 | return false; | |
cf74a78b AG |
1818 | } |
1819 | ||
7597f129 | 1820 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1821 | { |
1822 | struct page *page; | |
1823 | ||
6c3bd3d7 JR |
1824 | might_sleep(); |
1825 | ||
34f80cfa | 1826 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1827 | if (is_error_page(page)) |
1828 | goto error; | |
1829 | ||
7597f129 JR |
1830 | *_page = page; |
1831 | ||
1832 | return kmap(page); | |
34f80cfa JR |
1833 | |
1834 | error: | |
1835 | kvm_release_page_clean(page); | |
1836 | kvm_inject_gp(&svm->vcpu, 0); | |
1837 | ||
1838 | return NULL; | |
1839 | } | |
1840 | ||
7597f129 | 1841 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1842 | { |
7597f129 | 1843 | kunmap(page); |
34f80cfa JR |
1844 | kvm_release_page_dirty(page); |
1845 | } | |
34f80cfa | 1846 | |
ce2ac085 JR |
1847 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
1848 | { | |
1849 | unsigned port; | |
1850 | u8 val, bit; | |
1851 | u64 gpa; | |
34f80cfa | 1852 | |
ce2ac085 JR |
1853 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
1854 | return NESTED_EXIT_HOST; | |
34f80cfa | 1855 | |
ce2ac085 JR |
1856 | port = svm->vmcb->control.exit_info_1 >> 16; |
1857 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1858 | bit = port % 8; | |
1859 | val = 0; | |
1860 | ||
1861 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1862 | val &= (1 << bit); | |
1863 | ||
1864 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
1865 | } |
1866 | ||
d2477826 | 1867 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1868 | { |
0d6b3537 JR |
1869 | u32 offset, msr, value; |
1870 | int write, mask; | |
4c2161ae | 1871 | |
3d62d9aa | 1872 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 1873 | return NESTED_EXIT_HOST; |
3d62d9aa | 1874 | |
0d6b3537 JR |
1875 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1876 | offset = svm_msrpm_offset(msr); | |
1877 | write = svm->vmcb->control.exit_info_1 & 1; | |
1878 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 1879 | |
0d6b3537 JR |
1880 | if (offset == MSR_INVALID) |
1881 | return NESTED_EXIT_DONE; | |
4c2161ae | 1882 | |
0d6b3537 JR |
1883 | /* Offset is in 32 bit units but need in 8 bit units */ |
1884 | offset *= 4; | |
4c2161ae | 1885 | |
0d6b3537 JR |
1886 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
1887 | return NESTED_EXIT_DONE; | |
3d62d9aa | 1888 | |
0d6b3537 | 1889 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
1890 | } |
1891 | ||
410e4d57 | 1892 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1893 | { |
cf74a78b | 1894 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1895 | |
410e4d57 JR |
1896 | switch (exit_code) { |
1897 | case SVM_EXIT_INTR: | |
1898 | case SVM_EXIT_NMI: | |
ff47a49b | 1899 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 1900 | return NESTED_EXIT_HOST; |
410e4d57 | 1901 | case SVM_EXIT_NPF: |
e0231715 | 1902 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1903 | if (npt_enabled) |
1904 | return NESTED_EXIT_HOST; | |
1905 | break; | |
410e4d57 | 1906 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
1907 | /* When we're shadowing, trap PFs, but not async PF */ |
1908 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
1909 | return NESTED_EXIT_HOST; |
1910 | break; | |
66a562f7 JR |
1911 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
1912 | nm_interception(svm); | |
1913 | break; | |
410e4d57 JR |
1914 | default: |
1915 | break; | |
cf74a78b AG |
1916 | } |
1917 | ||
410e4d57 JR |
1918 | return NESTED_EXIT_CONTINUE; |
1919 | } | |
1920 | ||
1921 | /* | |
1922 | * If this function returns true, this #vmexit was already handled | |
1923 | */ | |
b8e88bc8 | 1924 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
1925 | { |
1926 | u32 exit_code = svm->vmcb->control.exit_code; | |
1927 | int vmexit = NESTED_EXIT_HOST; | |
1928 | ||
cf74a78b | 1929 | switch (exit_code) { |
9c4e40b9 | 1930 | case SVM_EXIT_MSR: |
3d62d9aa | 1931 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1932 | break; |
ce2ac085 JR |
1933 | case SVM_EXIT_IOIO: |
1934 | vmexit = nested_svm_intercept_ioio(svm); | |
1935 | break; | |
4ee546b4 RJ |
1936 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
1937 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
1938 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 1939 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1940 | break; |
1941 | } | |
3aed041a JR |
1942 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
1943 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
1944 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 1945 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1946 | break; |
1947 | } | |
1948 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1949 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1950 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1951 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
1952 | /* async page fault always cause vmexit */ |
1953 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
1954 | svm->apf_reason != 0) | |
1955 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
1956 | break; |
1957 | } | |
228070b1 JR |
1958 | case SVM_EXIT_ERR: { |
1959 | vmexit = NESTED_EXIT_DONE; | |
1960 | break; | |
1961 | } | |
cf74a78b AG |
1962 | default: { |
1963 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 1964 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 1965 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1966 | } |
1967 | } | |
1968 | ||
b8e88bc8 JR |
1969 | return vmexit; |
1970 | } | |
1971 | ||
1972 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1973 | { | |
1974 | int vmexit; | |
1975 | ||
1976 | vmexit = nested_svm_intercept(svm); | |
1977 | ||
1978 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 1979 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
1980 | |
1981 | return vmexit; | |
cf74a78b AG |
1982 | } |
1983 | ||
0460a979 JR |
1984 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
1985 | { | |
1986 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
1987 | struct vmcb_control_area *from = &from_vmcb->control; | |
1988 | ||
4ee546b4 | 1989 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 1990 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
1991 | dst->intercept_exceptions = from->intercept_exceptions; |
1992 | dst->intercept = from->intercept; | |
1993 | dst->iopm_base_pa = from->iopm_base_pa; | |
1994 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
1995 | dst->tsc_offset = from->tsc_offset; | |
1996 | dst->asid = from->asid; | |
1997 | dst->tlb_ctl = from->tlb_ctl; | |
1998 | dst->int_ctl = from->int_ctl; | |
1999 | dst->int_vector = from->int_vector; | |
2000 | dst->int_state = from->int_state; | |
2001 | dst->exit_code = from->exit_code; | |
2002 | dst->exit_code_hi = from->exit_code_hi; | |
2003 | dst->exit_info_1 = from->exit_info_1; | |
2004 | dst->exit_info_2 = from->exit_info_2; | |
2005 | dst->exit_int_info = from->exit_int_info; | |
2006 | dst->exit_int_info_err = from->exit_int_info_err; | |
2007 | dst->nested_ctl = from->nested_ctl; | |
2008 | dst->event_inj = from->event_inj; | |
2009 | dst->event_inj_err = from->event_inj_err; | |
2010 | dst->nested_cr3 = from->nested_cr3; | |
2011 | dst->lbr_ctl = from->lbr_ctl; | |
2012 | } | |
2013 | ||
34f80cfa | 2014 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2015 | { |
34f80cfa | 2016 | struct vmcb *nested_vmcb; |
e6aa9abd | 2017 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2018 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2019 | struct page *page; |
cf74a78b | 2020 | |
17897f36 JR |
2021 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2022 | vmcb->control.exit_info_1, | |
2023 | vmcb->control.exit_info_2, | |
2024 | vmcb->control.exit_int_info, | |
2025 | vmcb->control.exit_int_info_err); | |
2026 | ||
7597f129 | 2027 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2028 | if (!nested_vmcb) |
2029 | return 1; | |
2030 | ||
2030753d JR |
2031 | /* Exit Guest-Mode */ |
2032 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2033 | svm->nested.vmcb = 0; |
2034 | ||
cf74a78b | 2035 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2036 | disable_gif(svm); |
2037 | ||
2038 | nested_vmcb->save.es = vmcb->save.es; | |
2039 | nested_vmcb->save.cs = vmcb->save.cs; | |
2040 | nested_vmcb->save.ss = vmcb->save.ss; | |
2041 | nested_vmcb->save.ds = vmcb->save.ds; | |
2042 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2043 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2044 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2045 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
2be4fc7a | 2046 | nested_vmcb->save.cr3 = svm->vcpu.arch.cr3; |
33740e40 | 2047 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2048 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
33740e40 JR |
2049 | nested_vmcb->save.rflags = vmcb->save.rflags; |
2050 | nested_vmcb->save.rip = vmcb->save.rip; | |
2051 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2052 | nested_vmcb->save.rax = vmcb->save.rax; | |
2053 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2054 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2055 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2056 | ||
2057 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2058 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2059 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2060 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2061 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2062 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2063 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2064 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2065 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2066 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2067 | |
2068 | /* | |
2069 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2070 | * to make sure that we do not lose injected events. So check event_inj | |
2071 | * here and copy it to exit_int_info if it is valid. | |
2072 | * Exit_int_info and event_inj can't be both valid because the case | |
2073 | * below only happens on a VMRUN instruction intercept which has | |
2074 | * no valid exit_int_info set. | |
2075 | */ | |
2076 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2077 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2078 | ||
2079 | nc->exit_int_info = vmcb->control.event_inj; | |
2080 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2081 | } | |
2082 | ||
33740e40 JR |
2083 | nested_vmcb->control.tlb_ctl = 0; |
2084 | nested_vmcb->control.event_inj = 0; | |
2085 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2086 | |
2087 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2088 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2089 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2090 | ||
cf74a78b | 2091 | /* Restore the original control entries */ |
0460a979 | 2092 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2093 | |
219b65dc AG |
2094 | kvm_clear_exception_queue(&svm->vcpu); |
2095 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2096 | |
4b16184c JR |
2097 | svm->nested.nested_cr3 = 0; |
2098 | ||
cf74a78b AG |
2099 | /* Restore selected save entries */ |
2100 | svm->vmcb->save.es = hsave->save.es; | |
2101 | svm->vmcb->save.cs = hsave->save.cs; | |
2102 | svm->vmcb->save.ss = hsave->save.ss; | |
2103 | svm->vmcb->save.ds = hsave->save.ds; | |
2104 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2105 | svm->vmcb->save.idtr = hsave->save.idtr; | |
2106 | svm->vmcb->save.rflags = hsave->save.rflags; | |
2107 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
2108 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2109 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2110 | if (npt_enabled) { | |
2111 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2112 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2113 | } else { | |
2390218b | 2114 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2115 | } |
2116 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2117 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2118 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2119 | svm->vmcb->save.dr7 = 0; | |
2120 | svm->vmcb->save.cpl = 0; | |
2121 | svm->vmcb->control.exit_int_info = 0; | |
2122 | ||
7597f129 | 2123 | nested_svm_unmap(page); |
cf74a78b | 2124 | |
4b16184c | 2125 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2126 | kvm_mmu_reset_context(&svm->vcpu); |
2127 | kvm_mmu_load(&svm->vcpu); | |
2128 | ||
2129 | return 0; | |
2130 | } | |
3d6368ef | 2131 | |
9738b2c9 | 2132 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2133 | { |
323c3d80 JR |
2134 | /* |
2135 | * This function merges the msr permission bitmaps of kvm and the | |
2136 | * nested vmcb. It is omptimized in that it only merges the parts where | |
2137 | * the kvm msr permission bitmap may contain zero bits | |
2138 | */ | |
3d6368ef | 2139 | int i; |
9738b2c9 | 2140 | |
323c3d80 JR |
2141 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2142 | return true; | |
9738b2c9 | 2143 | |
323c3d80 JR |
2144 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2145 | u32 value, p; | |
2146 | u64 offset; | |
9738b2c9 | 2147 | |
323c3d80 JR |
2148 | if (msrpm_offsets[i] == 0xffffffff) |
2149 | break; | |
3d6368ef | 2150 | |
0d6b3537 JR |
2151 | p = msrpm_offsets[i]; |
2152 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2153 | |
2154 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2155 | return false; | |
2156 | ||
2157 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2158 | } | |
3d6368ef | 2159 | |
323c3d80 | 2160 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2161 | |
2162 | return true; | |
3d6368ef AG |
2163 | } |
2164 | ||
52c65a30 JR |
2165 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2166 | { | |
2167 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2168 | return false; | |
2169 | ||
dbe77584 JR |
2170 | if (vmcb->control.asid == 0) |
2171 | return false; | |
2172 | ||
4b16184c JR |
2173 | if (vmcb->control.nested_ctl && !npt_enabled) |
2174 | return false; | |
2175 | ||
52c65a30 JR |
2176 | return true; |
2177 | } | |
2178 | ||
9738b2c9 | 2179 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2180 | { |
9738b2c9 | 2181 | struct vmcb *nested_vmcb; |
e6aa9abd | 2182 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2183 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2184 | struct page *page; |
06fc7772 | 2185 | u64 vmcb_gpa; |
3d6368ef | 2186 | |
06fc7772 | 2187 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2188 | |
7597f129 | 2189 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2190 | if (!nested_vmcb) |
2191 | return false; | |
2192 | ||
52c65a30 JR |
2193 | if (!nested_vmcb_checks(nested_vmcb)) { |
2194 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2195 | nested_vmcb->control.exit_code_hi = 0; | |
2196 | nested_vmcb->control.exit_info_1 = 0; | |
2197 | nested_vmcb->control.exit_info_2 = 0; | |
2198 | ||
2199 | nested_svm_unmap(page); | |
2200 | ||
2201 | return false; | |
2202 | } | |
2203 | ||
b75f4eb3 | 2204 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2205 | nested_vmcb->save.rip, |
2206 | nested_vmcb->control.int_ctl, | |
2207 | nested_vmcb->control.event_inj, | |
2208 | nested_vmcb->control.nested_ctl); | |
2209 | ||
4ee546b4 RJ |
2210 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2211 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2212 | nested_vmcb->control.intercept_exceptions, |
2213 | nested_vmcb->control.intercept); | |
2214 | ||
3d6368ef | 2215 | /* Clear internal status */ |
219b65dc AG |
2216 | kvm_clear_exception_queue(&svm->vcpu); |
2217 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2218 | |
e0231715 JR |
2219 | /* |
2220 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2221 | * restore everything when a VMEXIT occurs | |
2222 | */ | |
defbba56 JR |
2223 | hsave->save.es = vmcb->save.es; |
2224 | hsave->save.cs = vmcb->save.cs; | |
2225 | hsave->save.ss = vmcb->save.ss; | |
2226 | hsave->save.ds = vmcb->save.ds; | |
2227 | hsave->save.gdtr = vmcb->save.gdtr; | |
2228 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2229 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2230 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 JR |
2231 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
2232 | hsave->save.rflags = vmcb->save.rflags; | |
b75f4eb3 | 2233 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2234 | hsave->save.rsp = vmcb->save.rsp; |
2235 | hsave->save.rax = vmcb->save.rax; | |
2236 | if (npt_enabled) | |
2237 | hsave->save.cr3 = vmcb->save.cr3; | |
2238 | else | |
2239 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
2240 | ||
0460a979 | 2241 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
2242 | |
2243 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
2244 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
2245 | else | |
2246 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2247 | ||
4b16184c JR |
2248 | if (nested_vmcb->control.nested_ctl) { |
2249 | kvm_mmu_unload(&svm->vcpu); | |
2250 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2251 | nested_svm_init_mmu_context(&svm->vcpu); | |
2252 | } | |
2253 | ||
3d6368ef AG |
2254 | /* Load the nested guest state */ |
2255 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2256 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2257 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2258 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2259 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2260 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
2261 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
2262 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
2263 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2264 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2265 | if (npt_enabled) { | |
2266 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2267 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2268 | } else |
2390218b | 2269 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2270 | |
2271 | /* Guest paging mode is active - reset mmu */ | |
2272 | kvm_mmu_reset_context(&svm->vcpu); | |
2273 | ||
defbba56 | 2274 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2275 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2276 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2277 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2278 | |
3d6368ef AG |
2279 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2280 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2281 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2282 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2283 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2284 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2285 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2286 | ||
f7138538 | 2287 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2288 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2289 | |
aad42c64 | 2290 | /* cache intercepts */ |
4ee546b4 | 2291 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2292 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2293 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2294 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2295 | ||
3d6368ef | 2296 | force_new_asid(&svm->vcpu); |
3d6368ef | 2297 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2298 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2299 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2300 | else | |
2301 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2302 | ||
88ab24ad JR |
2303 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2304 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2305 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2306 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2307 | } |
2308 | ||
0d945bd9 JR |
2309 | /* We don't want to see VMMCALLs from a nested guest */ |
2310 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL); | |
2311 | ||
88ab24ad | 2312 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2313 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2314 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2315 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2316 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2317 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2318 | ||
7597f129 | 2319 | nested_svm_unmap(page); |
9738b2c9 | 2320 | |
2030753d JR |
2321 | /* Enter Guest-Mode */ |
2322 | enter_guest_mode(&svm->vcpu); | |
2323 | ||
384c6368 JR |
2324 | /* |
2325 | * Merge guest and host intercepts - must be called with vcpu in | |
2326 | * guest-mode to take affect here | |
2327 | */ | |
2328 | recalc_intercepts(svm); | |
2329 | ||
06fc7772 | 2330 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2331 | |
2af9194d | 2332 | enable_gif(svm); |
3d6368ef | 2333 | |
9738b2c9 | 2334 | return true; |
3d6368ef AG |
2335 | } |
2336 | ||
9966bf68 | 2337 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2338 | { |
2339 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2340 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2341 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2342 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2343 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2344 | to_vmcb->save.star = from_vmcb->save.star; | |
2345 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2346 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2347 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2348 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2349 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2350 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2351 | } |
2352 | ||
851ba692 | 2353 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2354 | { |
9966bf68 | 2355 | struct vmcb *nested_vmcb; |
7597f129 | 2356 | struct page *page; |
9966bf68 | 2357 | |
5542675b AG |
2358 | if (nested_svm_check_permissions(svm)) |
2359 | return 1; | |
2360 | ||
2361 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2362 | skip_emulated_instruction(&svm->vcpu); | |
2363 | ||
7597f129 | 2364 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2365 | if (!nested_vmcb) |
2366 | return 1; | |
2367 | ||
2368 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 2369 | nested_svm_unmap(page); |
5542675b AG |
2370 | |
2371 | return 1; | |
2372 | } | |
2373 | ||
851ba692 | 2374 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2375 | { |
9966bf68 | 2376 | struct vmcb *nested_vmcb; |
7597f129 | 2377 | struct page *page; |
9966bf68 | 2378 | |
5542675b AG |
2379 | if (nested_svm_check_permissions(svm)) |
2380 | return 1; | |
2381 | ||
2382 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2383 | skip_emulated_instruction(&svm->vcpu); | |
2384 | ||
7597f129 | 2385 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2386 | if (!nested_vmcb) |
2387 | return 1; | |
2388 | ||
2389 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 2390 | nested_svm_unmap(page); |
5542675b AG |
2391 | |
2392 | return 1; | |
2393 | } | |
2394 | ||
851ba692 | 2395 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2396 | { |
3d6368ef AG |
2397 | if (nested_svm_check_permissions(svm)) |
2398 | return 1; | |
2399 | ||
b75f4eb3 RJ |
2400 | /* Save rip after vmrun instruction */ |
2401 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2402 | |
9738b2c9 | 2403 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2404 | return 1; |
2405 | ||
9738b2c9 | 2406 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2407 | goto failed; |
2408 | ||
2409 | return 1; | |
2410 | ||
2411 | failed: | |
2412 | ||
2413 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2414 | svm->vmcb->control.exit_code_hi = 0; | |
2415 | svm->vmcb->control.exit_info_1 = 0; | |
2416 | svm->vmcb->control.exit_info_2 = 0; | |
2417 | ||
2418 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2419 | |
2420 | return 1; | |
2421 | } | |
2422 | ||
851ba692 | 2423 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2424 | { |
2425 | if (nested_svm_check_permissions(svm)) | |
2426 | return 1; | |
2427 | ||
2428 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2429 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2430 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2431 | |
2af9194d | 2432 | enable_gif(svm); |
1371d904 AG |
2433 | |
2434 | return 1; | |
2435 | } | |
2436 | ||
851ba692 | 2437 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2438 | { |
2439 | if (nested_svm_check_permissions(svm)) | |
2440 | return 1; | |
2441 | ||
2442 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2443 | skip_emulated_instruction(&svm->vcpu); | |
2444 | ||
2af9194d | 2445 | disable_gif(svm); |
1371d904 AG |
2446 | |
2447 | /* After a CLGI no interrupts should come */ | |
2448 | svm_clear_vintr(svm); | |
2449 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2450 | ||
2451 | return 1; | |
2452 | } | |
2453 | ||
851ba692 | 2454 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2455 | { |
2456 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2457 | |
ec1ff790 JR |
2458 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2459 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2460 | ||
ff092385 AG |
2461 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2462 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2463 | ||
2464 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2465 | skip_emulated_instruction(&svm->vcpu); | |
2466 | return 1; | |
2467 | } | |
2468 | ||
532a46b9 JR |
2469 | static int skinit_interception(struct vcpu_svm *svm) |
2470 | { | |
2471 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2472 | ||
2473 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2474 | return 1; | |
2475 | } | |
2476 | ||
851ba692 | 2477 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2478 | { |
7ee5d940 | 2479 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2480 | return 1; |
2481 | } | |
2482 | ||
851ba692 | 2483 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2484 | { |
37817f29 | 2485 | u16 tss_selector; |
64a7ec06 GN |
2486 | int reason; |
2487 | int int_type = svm->vmcb->control.exit_int_info & | |
2488 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2489 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2490 | uint32_t type = |
2491 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2492 | uint32_t idt_v = | |
2493 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2494 | bool has_error_code = false; |
2495 | u32 error_code = 0; | |
37817f29 IE |
2496 | |
2497 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2498 | |
37817f29 IE |
2499 | if (svm->vmcb->control.exit_info_2 & |
2500 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2501 | reason = TASK_SWITCH_IRET; |
2502 | else if (svm->vmcb->control.exit_info_2 & | |
2503 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2504 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2505 | else if (idt_v) |
64a7ec06 GN |
2506 | reason = TASK_SWITCH_GATE; |
2507 | else | |
2508 | reason = TASK_SWITCH_CALL; | |
2509 | ||
fe8e7f83 GN |
2510 | if (reason == TASK_SWITCH_GATE) { |
2511 | switch (type) { | |
2512 | case SVM_EXITINTINFO_TYPE_NMI: | |
2513 | svm->vcpu.arch.nmi_injected = false; | |
2514 | break; | |
2515 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2516 | if (svm->vmcb->control.exit_info_2 & |
2517 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2518 | has_error_code = true; | |
2519 | error_code = | |
2520 | (u32)svm->vmcb->control.exit_info_2; | |
2521 | } | |
fe8e7f83 GN |
2522 | kvm_clear_exception_queue(&svm->vcpu); |
2523 | break; | |
2524 | case SVM_EXITINTINFO_TYPE_INTR: | |
2525 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2526 | break; | |
2527 | default: | |
2528 | break; | |
2529 | } | |
2530 | } | |
64a7ec06 | 2531 | |
8317c298 GN |
2532 | if (reason != TASK_SWITCH_GATE || |
2533 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2534 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2535 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2536 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2537 | |
acb54517 GN |
2538 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2539 | has_error_code, error_code) == EMULATE_FAIL) { | |
2540 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2541 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2542 | svm->vcpu.run->internal.ndata = 0; | |
2543 | return 0; | |
2544 | } | |
2545 | return 1; | |
6aa8b732 AK |
2546 | } |
2547 | ||
851ba692 | 2548 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2549 | { |
5fdbf976 | 2550 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2551 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2552 | return 1; |
6aa8b732 AK |
2553 | } |
2554 | ||
851ba692 | 2555 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2556 | { |
2557 | ++svm->vcpu.stat.nmi_window_exits; | |
061e2fd1 | 2558 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET); |
44c11430 | 2559 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2560 | return 1; |
2561 | } | |
2562 | ||
851ba692 | 2563 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2564 | { |
6d77dbfc | 2565 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; |
a7052897 MT |
2566 | } |
2567 | ||
851ba692 | 2568 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2569 | { |
6d77dbfc | 2570 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; |
6aa8b732 AK |
2571 | } |
2572 | ||
cda00082 JR |
2573 | static int cr0_write_interception(struct vcpu_svm *svm) |
2574 | { | |
2575 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
2576 | int r; | |
2577 | ||
2578 | r = emulate_instruction(&svm->vcpu, 0, 0, 0); | |
2579 | ||
2580 | if (svm->nested.vmexit_rip) { | |
2581 | kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip); | |
2582 | kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp); | |
2583 | kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax); | |
2584 | svm->nested.vmexit_rip = 0; | |
2585 | } | |
2586 | ||
2587 | return r == EMULATE_DONE; | |
2588 | } | |
2589 | ||
851ba692 | 2590 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2591 | { |
851ba692 AK |
2592 | struct kvm_run *kvm_run = svm->vcpu.run; |
2593 | ||
0a5fff19 GN |
2594 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2595 | /* instruction emulation calls kvm_set_cr8() */ | |
851ba692 | 2596 | emulate_instruction(&svm->vcpu, 0, 0, 0); |
95ba8273 | 2597 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2598 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
1d075434 | 2599 | return 1; |
95ba8273 | 2600 | } |
0a5fff19 GN |
2601 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
2602 | return 1; | |
1d075434 JR |
2603 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2604 | return 0; | |
2605 | } | |
2606 | ||
6aa8b732 AK |
2607 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2608 | { | |
a2fa3e9f GH |
2609 | struct vcpu_svm *svm = to_svm(vcpu); |
2610 | ||
6aa8b732 | 2611 | switch (ecx) { |
af24a4e4 | 2612 | case MSR_IA32_TSC: { |
20824f30 | 2613 | u64 tsc_offset; |
6aa8b732 | 2614 | |
2030753d | 2615 | if (is_guest_mode(vcpu)) |
20824f30 JR |
2616 | tsc_offset = svm->nested.hsave->control.tsc_offset; |
2617 | else | |
2618 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2619 | ||
2620 | *data = tsc_offset + native_read_tsc(); | |
6aa8b732 AK |
2621 | break; |
2622 | } | |
8c06585d | 2623 | case MSR_STAR: |
a2fa3e9f | 2624 | *data = svm->vmcb->save.star; |
6aa8b732 | 2625 | break; |
0e859cac | 2626 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2627 | case MSR_LSTAR: |
a2fa3e9f | 2628 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2629 | break; |
2630 | case MSR_CSTAR: | |
a2fa3e9f | 2631 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2632 | break; |
2633 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2634 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2635 | break; |
2636 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2637 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2638 | break; |
2639 | #endif | |
2640 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2641 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2642 | break; |
2643 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2644 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2645 | break; |
2646 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2647 | *data = svm->sysenter_esp; |
6aa8b732 | 2648 | break; |
e0231715 JR |
2649 | /* |
2650 | * Nobody will change the following 5 values in the VMCB so we can | |
2651 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2652 | * implemented. | |
2653 | */ | |
a2938c80 JR |
2654 | case MSR_IA32_DEBUGCTLMSR: |
2655 | *data = svm->vmcb->save.dbgctl; | |
2656 | break; | |
2657 | case MSR_IA32_LASTBRANCHFROMIP: | |
2658 | *data = svm->vmcb->save.br_from; | |
2659 | break; | |
2660 | case MSR_IA32_LASTBRANCHTOIP: | |
2661 | *data = svm->vmcb->save.br_to; | |
2662 | break; | |
2663 | case MSR_IA32_LASTINTFROMIP: | |
2664 | *data = svm->vmcb->save.last_excp_from; | |
2665 | break; | |
2666 | case MSR_IA32_LASTINTTOIP: | |
2667 | *data = svm->vmcb->save.last_excp_to; | |
2668 | break; | |
b286d5d8 | 2669 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2670 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2671 | break; |
eb6f302e | 2672 | case MSR_VM_CR: |
4a810181 | 2673 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 2674 | break; |
c8a73f18 AG |
2675 | case MSR_IA32_UCODE_REV: |
2676 | *data = 0x01000065; | |
2677 | break; | |
6aa8b732 | 2678 | default: |
3bab1f5d | 2679 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2680 | } |
2681 | return 0; | |
2682 | } | |
2683 | ||
851ba692 | 2684 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2685 | { |
ad312c7c | 2686 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2687 | u64 data; |
2688 | ||
59200273 AK |
2689 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2690 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2691 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2692 | } else { |
229456fc | 2693 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2694 | |
5fdbf976 | 2695 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2696 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2697 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2698 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2699 | } |
2700 | return 1; | |
2701 | } | |
2702 | ||
4a810181 JR |
2703 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
2704 | { | |
2705 | struct vcpu_svm *svm = to_svm(vcpu); | |
2706 | int svm_dis, chg_mask; | |
2707 | ||
2708 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2709 | return 1; | |
2710 | ||
2711 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2712 | ||
2713 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2714 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2715 | ||
2716 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2717 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2718 | ||
2719 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2720 | ||
2721 | /* check for svm_disable while efer.svme is set */ | |
2722 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2723 | return 1; | |
2724 | ||
2725 | return 0; | |
2726 | } | |
2727 | ||
6aa8b732 AK |
2728 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
2729 | { | |
a2fa3e9f GH |
2730 | struct vcpu_svm *svm = to_svm(vcpu); |
2731 | ||
6aa8b732 | 2732 | switch (ecx) { |
f4e1b3c8 | 2733 | case MSR_IA32_TSC: |
99e3e30a | 2734 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 2735 | break; |
8c06585d | 2736 | case MSR_STAR: |
a2fa3e9f | 2737 | svm->vmcb->save.star = data; |
6aa8b732 | 2738 | break; |
49b14f24 | 2739 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2740 | case MSR_LSTAR: |
a2fa3e9f | 2741 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2742 | break; |
2743 | case MSR_CSTAR: | |
a2fa3e9f | 2744 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2745 | break; |
2746 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2747 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2748 | break; |
2749 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2750 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2751 | break; |
2752 | #endif | |
2753 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2754 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2755 | break; |
2756 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2757 | svm->sysenter_eip = data; |
a2fa3e9f | 2758 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2759 | break; |
2760 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2761 | svm->sysenter_esp = data; |
a2fa3e9f | 2762 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2763 | break; |
a2938c80 | 2764 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 2765 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
24e09cbf | 2766 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
b8688d51 | 2767 | __func__, data); |
24e09cbf JR |
2768 | break; |
2769 | } | |
2770 | if (data & DEBUGCTL_RESERVED_BITS) | |
2771 | return 1; | |
2772 | ||
2773 | svm->vmcb->save.dbgctl = data; | |
2774 | if (data & (1ULL<<0)) | |
2775 | svm_enable_lbrv(svm); | |
2776 | else | |
2777 | svm_disable_lbrv(svm); | |
a2938c80 | 2778 | break; |
b286d5d8 | 2779 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2780 | svm->nested.hsave_msr = data; |
62b9abaa | 2781 | break; |
3c5d0a44 | 2782 | case MSR_VM_CR: |
4a810181 | 2783 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 2784 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
2785 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2786 | break; | |
6aa8b732 | 2787 | default: |
3bab1f5d | 2788 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2789 | } |
2790 | return 0; | |
2791 | } | |
2792 | ||
851ba692 | 2793 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2794 | { |
ad312c7c | 2795 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2796 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2797 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2798 | |
af9ca2d7 | 2799 | |
5fdbf976 | 2800 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2801 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2802 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 2803 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
2804 | } else { |
2805 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 2806 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 2807 | } |
6aa8b732 AK |
2808 | return 1; |
2809 | } | |
2810 | ||
851ba692 | 2811 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2812 | { |
e756fc62 | 2813 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2814 | return wrmsr_interception(svm); |
6aa8b732 | 2815 | else |
851ba692 | 2816 | return rdmsr_interception(svm); |
6aa8b732 AK |
2817 | } |
2818 | ||
851ba692 | 2819 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2820 | { |
851ba692 AK |
2821 | struct kvm_run *kvm_run = svm->vcpu.run; |
2822 | ||
3842d135 | 2823 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 2824 | svm_clear_vintr(svm); |
85f455f7 | 2825 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2826 | /* |
2827 | * If the user space waits to inject interrupts, exit as soon as | |
2828 | * possible | |
2829 | */ | |
8061823a GN |
2830 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
2831 | kvm_run->request_interrupt_window && | |
2832 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 2833 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2834 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2835 | return 0; | |
2836 | } | |
2837 | ||
2838 | return 1; | |
2839 | } | |
2840 | ||
565d0998 ML |
2841 | static int pause_interception(struct vcpu_svm *svm) |
2842 | { | |
2843 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
2844 | return 1; | |
2845 | } | |
2846 | ||
851ba692 | 2847 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
e0231715 JR |
2848 | [SVM_EXIT_READ_CR0] = emulate_on_interception, |
2849 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2850 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
2851 | [SVM_EXIT_READ_CR8] = emulate_on_interception, | |
d225157b | 2852 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
cda00082 | 2853 | [SVM_EXIT_WRITE_CR0] = cr0_write_interception, |
e0231715 JR |
2854 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, |
2855 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
2856 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, | |
2857 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
6aa8b732 AK |
2858 | [SVM_EXIT_READ_DR1] = emulate_on_interception, |
2859 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2860 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
727f5a23 JK |
2861 | [SVM_EXIT_READ_DR4] = emulate_on_interception, |
2862 | [SVM_EXIT_READ_DR5] = emulate_on_interception, | |
2863 | [SVM_EXIT_READ_DR6] = emulate_on_interception, | |
2864 | [SVM_EXIT_READ_DR7] = emulate_on_interception, | |
6aa8b732 AK |
2865 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, |
2866 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2867 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2868 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
727f5a23 | 2869 | [SVM_EXIT_WRITE_DR4] = emulate_on_interception, |
6aa8b732 | 2870 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, |
727f5a23 | 2871 | [SVM_EXIT_WRITE_DR6] = emulate_on_interception, |
6aa8b732 | 2872 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, |
d0bfb940 JK |
2873 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
2874 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 2875 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
2876 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
2877 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
2878 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
2879 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 2880 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2881 | [SVM_EXIT_SMI] = nop_on_interception, |
2882 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2883 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 | 2884 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 2885 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 2886 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 2887 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 2888 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2889 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 2890 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 2891 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
2892 | [SVM_EXIT_MSR] = msr_interception, |
2893 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2894 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2895 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2896 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2897 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2898 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2899 | [SVM_EXIT_STGI] = stgi_interception, |
2900 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 2901 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 2902 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2903 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2904 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2905 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2906 | }; |
2907 | ||
3f10c846 JR |
2908 | void dump_vmcb(struct kvm_vcpu *vcpu) |
2909 | { | |
2910 | struct vcpu_svm *svm = to_svm(vcpu); | |
2911 | struct vmcb_control_area *control = &svm->vmcb->control; | |
2912 | struct vmcb_save_area *save = &svm->vmcb->save; | |
2913 | ||
2914 | pr_err("VMCB Control Area:\n"); | |
4ee546b4 RJ |
2915 | pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff); |
2916 | pr_err("cr_write: %04x\n", control->intercept_cr >> 16); | |
3aed041a JR |
2917 | pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff); |
2918 | pr_err("dr_write: %04x\n", control->intercept_dr >> 16); | |
3f10c846 JR |
2919 | pr_err("exceptions: %08x\n", control->intercept_exceptions); |
2920 | pr_err("intercepts: %016llx\n", control->intercept); | |
2921 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
2922 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
2923 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
2924 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
2925 | pr_err("asid: %d\n", control->asid); | |
2926 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
2927 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
2928 | pr_err("int_vector: %08x\n", control->int_vector); | |
2929 | pr_err("int_state: %08x\n", control->int_state); | |
2930 | pr_err("exit_code: %08x\n", control->exit_code); | |
2931 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
2932 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
2933 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
2934 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
2935 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
2936 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
2937 | pr_err("event_inj: %08x\n", control->event_inj); | |
2938 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
2939 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
2940 | pr_err("next_rip: %016llx\n", control->next_rip); | |
2941 | pr_err("VMCB State Save Area:\n"); | |
2942 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
2943 | save->es.selector, save->es.attrib, | |
2944 | save->es.limit, save->es.base); | |
2945 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2946 | save->cs.selector, save->cs.attrib, | |
2947 | save->cs.limit, save->cs.base); | |
2948 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
2949 | save->ss.selector, save->ss.attrib, | |
2950 | save->ss.limit, save->ss.base); | |
2951 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
2952 | save->ds.selector, save->ds.attrib, | |
2953 | save->ds.limit, save->ds.base); | |
2954 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2955 | save->fs.selector, save->fs.attrib, | |
2956 | save->fs.limit, save->fs.base); | |
2957 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2958 | save->gs.selector, save->gs.attrib, | |
2959 | save->gs.limit, save->gs.base); | |
2960 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2961 | save->gdtr.selector, save->gdtr.attrib, | |
2962 | save->gdtr.limit, save->gdtr.base); | |
2963 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2964 | save->ldtr.selector, save->ldtr.attrib, | |
2965 | save->ldtr.limit, save->ldtr.base); | |
2966 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2967 | save->idtr.selector, save->idtr.attrib, | |
2968 | save->idtr.limit, save->idtr.base); | |
2969 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2970 | save->tr.selector, save->tr.attrib, | |
2971 | save->tr.limit, save->tr.base); | |
2972 | pr_err("cpl: %d efer: %016llx\n", | |
2973 | save->cpl, save->efer); | |
2974 | pr_err("cr0: %016llx cr2: %016llx\n", | |
2975 | save->cr0, save->cr2); | |
2976 | pr_err("cr3: %016llx cr4: %016llx\n", | |
2977 | save->cr3, save->cr4); | |
2978 | pr_err("dr6: %016llx dr7: %016llx\n", | |
2979 | save->dr6, save->dr7); | |
2980 | pr_err("rip: %016llx rflags: %016llx\n", | |
2981 | save->rip, save->rflags); | |
2982 | pr_err("rsp: %016llx rax: %016llx\n", | |
2983 | save->rsp, save->rax); | |
2984 | pr_err("star: %016llx lstar: %016llx\n", | |
2985 | save->star, save->lstar); | |
2986 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
2987 | save->cstar, save->sfmask); | |
2988 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
2989 | save->kernel_gs_base, save->sysenter_cs); | |
2990 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
2991 | save->sysenter_esp, save->sysenter_eip); | |
2992 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
2993 | save->g_pat, save->dbgctl); | |
2994 | pr_err("br_from: %016llx br_to: %016llx\n", | |
2995 | save->br_from, save->br_to); | |
2996 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
2997 | save->last_excp_from, save->last_excp_to); | |
2998 | ||
2999 | } | |
3000 | ||
586f9607 AK |
3001 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3002 | { | |
3003 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3004 | ||
3005 | *info1 = control->exit_info_1; | |
3006 | *info2 = control->exit_info_2; | |
3007 | } | |
3008 | ||
851ba692 | 3009 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3010 | { |
04d2cc77 | 3011 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3012 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3013 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3014 | |
aa17911e | 3015 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
af9ca2d7 | 3016 | |
4ee546b4 | 3017 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3018 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3019 | if (npt_enabled) | |
3020 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3021 | |
cd3ff653 JR |
3022 | if (unlikely(svm->nested.exit_required)) { |
3023 | nested_svm_vmexit(svm); | |
3024 | svm->nested.exit_required = false; | |
3025 | ||
3026 | return 1; | |
3027 | } | |
3028 | ||
2030753d | 3029 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3030 | int vmexit; |
3031 | ||
d8cabddf JR |
3032 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3033 | svm->vmcb->control.exit_info_1, | |
3034 | svm->vmcb->control.exit_info_2, | |
3035 | svm->vmcb->control.exit_int_info, | |
3036 | svm->vmcb->control.exit_int_info_err); | |
3037 | ||
410e4d57 JR |
3038 | vmexit = nested_svm_exit_special(svm); |
3039 | ||
3040 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3041 | vmexit = nested_svm_exit_handled(svm); | |
3042 | ||
3043 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3044 | return 1; |
cf74a78b AG |
3045 | } |
3046 | ||
a5c3832d JR |
3047 | svm_complete_interrupts(svm); |
3048 | ||
04d2cc77 AK |
3049 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3050 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3051 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3052 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3053 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3054 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3055 | return 0; |
3056 | } | |
3057 | ||
a2fa3e9f | 3058 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3059 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3060 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3061 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3062 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3063 | "exit_code 0x%x\n", | |
b8688d51 | 3064 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3065 | exit_code); |
3066 | ||
9d8f549d | 3067 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3068 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3069 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3070 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3071 | return 0; |
3072 | } | |
3073 | ||
851ba692 | 3074 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3075 | } |
3076 | ||
3077 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3078 | { | |
3079 | int cpu = raw_smp_processor_id(); | |
3080 | ||
0fe1e009 TH |
3081 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3082 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3083 | load_TR_desc(); |
3084 | } | |
3085 | ||
e756fc62 | 3086 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3087 | { |
3088 | int cpu = raw_smp_processor_id(); | |
3089 | ||
0fe1e009 | 3090 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3091 | |
a2fa3e9f | 3092 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4b656b12 | 3093 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3094 | if (svm->asid_generation != sd->asid_generation) |
3095 | new_asid(svm, sd); | |
6aa8b732 AK |
3096 | } |
3097 | ||
95ba8273 GN |
3098 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3099 | { | |
3100 | struct vcpu_svm *svm = to_svm(vcpu); | |
3101 | ||
3102 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3103 | vcpu->arch.hflags |= HF_NMI_MASK; | |
061e2fd1 | 3104 | svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET); |
95ba8273 GN |
3105 | ++vcpu->stat.nmi_injections; |
3106 | } | |
6aa8b732 | 3107 | |
85f455f7 | 3108 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3109 | { |
3110 | struct vmcb_control_area *control; | |
3111 | ||
e756fc62 | 3112 | control = &svm->vmcb->control; |
85f455f7 | 3113 | control->int_vector = irq; |
6aa8b732 AK |
3114 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3115 | control->int_ctl |= V_IRQ_MASK | | |
3116 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
3117 | } | |
3118 | ||
66fd3f7f | 3119 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3120 | { |
3121 | struct vcpu_svm *svm = to_svm(vcpu); | |
3122 | ||
2af9194d | 3123 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3124 | |
9fb2d2b4 GN |
3125 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3126 | ++vcpu->stat.irq_injections; | |
3127 | ||
219b65dc AG |
3128 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3129 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3130 | } |
3131 | ||
95ba8273 | 3132 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3133 | { |
3134 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3135 | |
2030753d | 3136 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3137 | return; |
3138 | ||
95ba8273 | 3139 | if (irr == -1) |
aaacfc9a JR |
3140 | return; |
3141 | ||
95ba8273 | 3142 | if (tpr >= irr) |
4ee546b4 | 3143 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3144 | } |
aaacfc9a | 3145 | |
95ba8273 GN |
3146 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3147 | { | |
3148 | struct vcpu_svm *svm = to_svm(vcpu); | |
3149 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3150 | int ret; |
3151 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3152 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3153 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3154 | ||
3155 | return ret; | |
aaacfc9a JR |
3156 | } |
3157 | ||
3cfc3092 JK |
3158 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3159 | { | |
3160 | struct vcpu_svm *svm = to_svm(vcpu); | |
3161 | ||
3162 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3163 | } | |
3164 | ||
3165 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3166 | { | |
3167 | struct vcpu_svm *svm = to_svm(vcpu); | |
3168 | ||
3169 | if (masked) { | |
3170 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
061e2fd1 | 3171 | svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET); |
3cfc3092 JK |
3172 | } else { |
3173 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
061e2fd1 | 3174 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET); |
3cfc3092 JK |
3175 | } |
3176 | } | |
3177 | ||
78646121 GN |
3178 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3179 | { | |
3180 | struct vcpu_svm *svm = to_svm(vcpu); | |
3181 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3182 | int ret; |
3183 | ||
3184 | if (!gif_set(svm) || | |
3185 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3186 | return 0; | |
3187 | ||
3188 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
3189 | ||
2030753d | 3190 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3191 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3192 | ||
3193 | return ret; | |
78646121 GN |
3194 | } |
3195 | ||
9222be18 | 3196 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3197 | { |
219b65dc | 3198 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3199 | |
e0231715 JR |
3200 | /* |
3201 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3202 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3203 | * get that intercept, this function will be called again though and | |
3204 | * we'll get the vintr intercept. | |
3205 | */ | |
8fe54654 | 3206 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3207 | svm_set_vintr(svm); |
3208 | svm_inject_irq(svm, 0x0); | |
3209 | } | |
85f455f7 ED |
3210 | } |
3211 | ||
95ba8273 | 3212 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3213 | { |
04d2cc77 | 3214 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3215 | |
44c11430 GN |
3216 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3217 | == HF_NMI_MASK) | |
3218 | return; /* IRET will cause a vm exit */ | |
3219 | ||
e0231715 JR |
3220 | /* |
3221 | * Something prevents NMI from been injected. Single step over possible | |
3222 | * problem (IRET or exception injection or interrupt shadow) | |
3223 | */ | |
6be7d306 | 3224 | svm->nmi_singlestep = true; |
44c11430 GN |
3225 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3226 | update_db_intercept(vcpu); | |
c1150d8c DL |
3227 | } |
3228 | ||
cbc94022 IE |
3229 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3230 | { | |
3231 | return 0; | |
3232 | } | |
3233 | ||
d9e368d6 AK |
3234 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3235 | { | |
3236 | force_new_asid(vcpu); | |
3237 | } | |
3238 | ||
04d2cc77 AK |
3239 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3240 | { | |
3241 | } | |
3242 | ||
d7bf8221 JR |
3243 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3244 | { | |
3245 | struct vcpu_svm *svm = to_svm(vcpu); | |
3246 | ||
2030753d | 3247 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3248 | return; |
3249 | ||
4ee546b4 | 3250 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3251 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3252 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3253 | } |
3254 | } | |
3255 | ||
649d6864 JR |
3256 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3257 | { | |
3258 | struct vcpu_svm *svm = to_svm(vcpu); | |
3259 | u64 cr8; | |
3260 | ||
2030753d | 3261 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3262 | return; |
3263 | ||
649d6864 JR |
3264 | cr8 = kvm_get_cr8(vcpu); |
3265 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3266 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3267 | } | |
3268 | ||
9222be18 GN |
3269 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3270 | { | |
3271 | u8 vector; | |
3272 | int type; | |
3273 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3274 | unsigned int3_injected = svm->int3_injected; |
3275 | ||
3276 | svm->int3_injected = 0; | |
9222be18 | 3277 | |
3842d135 | 3278 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) { |
44c11430 | 3279 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3280 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3281 | } | |
44c11430 | 3282 | |
9222be18 GN |
3283 | svm->vcpu.arch.nmi_injected = false; |
3284 | kvm_clear_exception_queue(&svm->vcpu); | |
3285 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3286 | ||
3287 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3288 | return; | |
3289 | ||
3842d135 AK |
3290 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3291 | ||
9222be18 GN |
3292 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3293 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3294 | ||
3295 | switch (type) { | |
3296 | case SVM_EXITINTINFO_TYPE_NMI: | |
3297 | svm->vcpu.arch.nmi_injected = true; | |
3298 | break; | |
3299 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3300 | /* |
3301 | * In case of software exceptions, do not reinject the vector, | |
3302 | * but re-execute the instruction instead. Rewind RIP first | |
3303 | * if we emulated INT3 before. | |
3304 | */ | |
3305 | if (kvm_exception_is_soft(vector)) { | |
3306 | if (vector == BP_VECTOR && int3_injected && | |
3307 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3308 | kvm_rip_write(&svm->vcpu, | |
3309 | kvm_rip_read(&svm->vcpu) - | |
3310 | int3_injected); | |
9222be18 | 3311 | break; |
66b7138f | 3312 | } |
9222be18 GN |
3313 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3314 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3315 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3316 | |
3317 | } else | |
ce7ddec4 | 3318 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3319 | break; |
3320 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3321 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3322 | break; |
3323 | default: | |
3324 | break; | |
3325 | } | |
3326 | } | |
3327 | ||
b463a6f7 AK |
3328 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3329 | { | |
3330 | struct vcpu_svm *svm = to_svm(vcpu); | |
3331 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3332 | ||
3333 | control->exit_int_info = control->event_inj; | |
3334 | control->exit_int_info_err = control->event_inj_err; | |
3335 | control->event_inj = 0; | |
3336 | svm_complete_interrupts(svm); | |
3337 | } | |
3338 | ||
80e31d4f AK |
3339 | #ifdef CONFIG_X86_64 |
3340 | #define R "r" | |
3341 | #else | |
3342 | #define R "e" | |
3343 | #endif | |
3344 | ||
851ba692 | 3345 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3346 | { |
a2fa3e9f | 3347 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3348 | |
2041a06a JR |
3349 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3350 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3351 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3352 | ||
cd3ff653 JR |
3353 | /* |
3354 | * A vmexit emulation is required before the vcpu can be executed | |
3355 | * again. | |
3356 | */ | |
3357 | if (unlikely(svm->nested.exit_required)) | |
3358 | return; | |
3359 | ||
e756fc62 | 3360 | pre_svm_run(svm); |
6aa8b732 | 3361 | |
649d6864 JR |
3362 | sync_lapic_to_cr8(vcpu); |
3363 | ||
cda0ffdd | 3364 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3365 | |
04d2cc77 AK |
3366 | clgi(); |
3367 | ||
3368 | local_irq_enable(); | |
36241b8c | 3369 | |
6aa8b732 | 3370 | asm volatile ( |
80e31d4f AK |
3371 | "push %%"R"bp; \n\t" |
3372 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3373 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3374 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3375 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3376 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3377 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3378 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3379 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3380 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3381 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3382 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3383 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3384 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3385 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3386 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3387 | #endif |
3388 | ||
6aa8b732 | 3389 | /* Enter guest mode */ |
80e31d4f AK |
3390 | "push %%"R"ax \n\t" |
3391 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3392 | __ex(SVM_VMLOAD) "\n\t" |
3393 | __ex(SVM_VMRUN) "\n\t" | |
3394 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3395 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3396 | |
3397 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3398 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3399 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3400 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3401 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3402 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3403 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3404 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3405 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3406 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3407 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3408 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3409 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3410 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3411 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3412 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3413 | #endif |
80e31d4f | 3414 | "pop %%"R"bp" |
6aa8b732 | 3415 | : |
fb3f0f51 | 3416 | : [svm]"a"(svm), |
6aa8b732 | 3417 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3418 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3419 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3420 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3421 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3422 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3423 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3424 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3425 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3426 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3427 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3428 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3429 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3430 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3431 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3432 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3433 | #endif |
54a08c04 | 3434 | : "cc", "memory" |
80e31d4f | 3435 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3436 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3437 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3438 | #endif | |
3439 | ); | |
6aa8b732 | 3440 | |
82ca2d10 AK |
3441 | #ifdef CONFIG_X86_64 |
3442 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3443 | #else | |
dacccfdd | 3444 | loadsegment(fs, svm->host.fs); |
9581d442 | 3445 | #endif |
6aa8b732 AK |
3446 | |
3447 | reload_tss(vcpu); | |
3448 | ||
56ba47dd AK |
3449 | local_irq_disable(); |
3450 | ||
3451 | stgi(); | |
3452 | ||
13c34e07 AK |
3453 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3454 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3455 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3456 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3457 | ||
d7bf8221 JR |
3458 | sync_cr8_to_lapic(vcpu); |
3459 | ||
a2fa3e9f | 3460 | svm->next_rip = 0; |
9222be18 | 3461 | |
631bc487 GN |
3462 | /* if exit due to PF check for async PF */ |
3463 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3464 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3465 | ||
6de4f3ad AK |
3466 | if (npt_enabled) { |
3467 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3468 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3469 | } | |
fe5913e4 JR |
3470 | |
3471 | /* | |
3472 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3473 | * change the physical cpu | |
3474 | */ | |
3475 | if (unlikely(svm->vmcb->control.exit_code == | |
3476 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3477 | svm_handle_mce(svm); | |
6aa8b732 AK |
3478 | } |
3479 | ||
80e31d4f AK |
3480 | #undef R |
3481 | ||
6aa8b732 AK |
3482 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3483 | { | |
a2fa3e9f GH |
3484 | struct vcpu_svm *svm = to_svm(vcpu); |
3485 | ||
3486 | svm->vmcb->save.cr3 = root; | |
6aa8b732 AK |
3487 | force_new_asid(vcpu); |
3488 | } | |
3489 | ||
1c97f0a0 JR |
3490 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3491 | { | |
3492 | struct vcpu_svm *svm = to_svm(vcpu); | |
3493 | ||
3494 | svm->vmcb->control.nested_cr3 = root; | |
3495 | ||
3496 | /* Also sync guest cr3 here in case we live migrate */ | |
3497 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
3498 | ||
3499 | force_new_asid(vcpu); | |
3500 | } | |
3501 | ||
6aa8b732 AK |
3502 | static int is_disabled(void) |
3503 | { | |
6031a61c JR |
3504 | u64 vm_cr; |
3505 | ||
3506 | rdmsrl(MSR_VM_CR, vm_cr); | |
3507 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3508 | return 1; | |
3509 | ||
6aa8b732 AK |
3510 | return 0; |
3511 | } | |
3512 | ||
102d8325 IM |
3513 | static void |
3514 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3515 | { | |
3516 | /* | |
3517 | * Patch in the VMMCALL instruction: | |
3518 | */ | |
3519 | hypercall[0] = 0x0f; | |
3520 | hypercall[1] = 0x01; | |
3521 | hypercall[2] = 0xd9; | |
102d8325 IM |
3522 | } |
3523 | ||
002c7f7c YS |
3524 | static void svm_check_processor_compat(void *rtn) |
3525 | { | |
3526 | *(int *)rtn = 0; | |
3527 | } | |
3528 | ||
774ead3a AK |
3529 | static bool svm_cpu_has_accelerated_tpr(void) |
3530 | { | |
3531 | return false; | |
3532 | } | |
3533 | ||
4b12f0de | 3534 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3535 | { |
3536 | return 0; | |
3537 | } | |
3538 | ||
0e851880 SY |
3539 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3540 | { | |
3541 | } | |
3542 | ||
d4330ef2 JR |
3543 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3544 | { | |
c2c63a49 | 3545 | switch (func) { |
24d1b15f JR |
3546 | case 0x00000001: |
3547 | /* Mask out xsave bit as long as it is not supported by SVM */ | |
3548 | entry->ecx &= ~(bit(X86_FEATURE_XSAVE)); | |
3549 | break; | |
4c62a2dc JR |
3550 | case 0x80000001: |
3551 | if (nested) | |
3552 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3553 | break; | |
c2c63a49 JR |
3554 | case 0x8000000A: |
3555 | entry->eax = 1; /* SVM revision 1 */ | |
3556 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3557 | ASID emulation to nested SVM */ | |
3558 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
3559 | entry->edx = 0; /* Per default do not support any |
3560 | additional features */ | |
3561 | ||
3562 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 3563 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 3564 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 3565 | |
3d4aeaad JR |
3566 | /* Support NPT for the guest if enabled */ |
3567 | if (npt_enabled) | |
3568 | entry->edx |= SVM_FEATURE_NPT; | |
3569 | ||
c2c63a49 JR |
3570 | break; |
3571 | } | |
d4330ef2 JR |
3572 | } |
3573 | ||
229456fc | 3574 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
e0231715 JR |
3575 | { SVM_EXIT_READ_CR0, "read_cr0" }, |
3576 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3577 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3578 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3579 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3580 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3581 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3582 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3583 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3584 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3585 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3586 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3587 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3588 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3589 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3590 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3591 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3592 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
229456fc MT |
3593 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, |
3594 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3595 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3596 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3597 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3598 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3599 | { SVM_EXIT_INTR, "interrupt" }, | |
3600 | { SVM_EXIT_NMI, "nmi" }, | |
3601 | { SVM_EXIT_SMI, "smi" }, | |
3602 | { SVM_EXIT_INIT, "init" }, | |
3603 | { SVM_EXIT_VINTR, "vintr" }, | |
3604 | { SVM_EXIT_CPUID, "cpuid" }, | |
3605 | { SVM_EXIT_INVD, "invd" }, | |
3606 | { SVM_EXIT_HLT, "hlt" }, | |
3607 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3608 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3609 | { SVM_EXIT_IOIO, "io" }, | |
3610 | { SVM_EXIT_MSR, "msr" }, | |
3611 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3612 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3613 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3614 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3615 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3616 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3617 | { SVM_EXIT_STGI, "stgi" }, | |
3618 | { SVM_EXIT_CLGI, "clgi" }, | |
3619 | { SVM_EXIT_SKINIT, "skinit" }, | |
3620 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3621 | { SVM_EXIT_MONITOR, "monitor" }, | |
3622 | { SVM_EXIT_MWAIT, "mwait" }, | |
3623 | { SVM_EXIT_NPF, "npf" }, | |
3624 | { -1, NULL } | |
3625 | }; | |
3626 | ||
17cc3935 | 3627 | static int svm_get_lpage_level(void) |
344f414f | 3628 | { |
17cc3935 | 3629 | return PT_PDPE_LEVEL; |
344f414f JR |
3630 | } |
3631 | ||
4e47c7a6 SY |
3632 | static bool svm_rdtscp_supported(void) |
3633 | { | |
3634 | return false; | |
3635 | } | |
3636 | ||
f5f48ee1 SY |
3637 | static bool svm_has_wbinvd_exit(void) |
3638 | { | |
3639 | return true; | |
3640 | } | |
3641 | ||
02daab21 AK |
3642 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
3643 | { | |
3644 | struct vcpu_svm *svm = to_svm(vcpu); | |
3645 | ||
02daab21 | 3646 | svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR; |
2030753d | 3647 | if (is_guest_mode(vcpu)) |
66a562f7 JR |
3648 | svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR; |
3649 | update_cr0_intercept(svm); | |
02daab21 AK |
3650 | } |
3651 | ||
cbdd1bea | 3652 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
3653 | .cpu_has_kvm_support = has_svm, |
3654 | .disabled_by_bios = is_disabled, | |
3655 | .hardware_setup = svm_hardware_setup, | |
3656 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 3657 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
3658 | .hardware_enable = svm_hardware_enable, |
3659 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 3660 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
3661 | |
3662 | .vcpu_create = svm_create_vcpu, | |
3663 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 3664 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 3665 | |
04d2cc77 | 3666 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
3667 | .vcpu_load = svm_vcpu_load, |
3668 | .vcpu_put = svm_vcpu_put, | |
3669 | ||
3670 | .set_guest_debug = svm_guest_debug, | |
3671 | .get_msr = svm_get_msr, | |
3672 | .set_msr = svm_set_msr, | |
3673 | .get_segment_base = svm_get_segment_base, | |
3674 | .get_segment = svm_get_segment, | |
3675 | .set_segment = svm_set_segment, | |
2e4d2653 | 3676 | .get_cpl = svm_get_cpl, |
1747fb71 | 3677 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 3678 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
25c4c276 | 3679 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 3680 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
3681 | .set_cr3 = svm_set_cr3, |
3682 | .set_cr4 = svm_set_cr4, | |
3683 | .set_efer = svm_set_efer, | |
3684 | .get_idt = svm_get_idt, | |
3685 | .set_idt = svm_set_idt, | |
3686 | .get_gdt = svm_get_gdt, | |
3687 | .set_gdt = svm_set_gdt, | |
020df079 | 3688 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 3689 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
3690 | .get_rflags = svm_get_rflags, |
3691 | .set_rflags = svm_set_rflags, | |
6b52d186 | 3692 | .fpu_activate = svm_fpu_activate, |
02daab21 | 3693 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 3694 | |
6aa8b732 | 3695 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 3696 | |
6aa8b732 | 3697 | .run = svm_vcpu_run, |
04d2cc77 | 3698 | .handle_exit = handle_exit, |
6aa8b732 | 3699 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
3700 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
3701 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 3702 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 3703 | .set_irq = svm_set_irq, |
95ba8273 | 3704 | .set_nmi = svm_inject_nmi, |
298101da | 3705 | .queue_exception = svm_queue_exception, |
b463a6f7 | 3706 | .cancel_injection = svm_cancel_injection, |
78646121 | 3707 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 3708 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
3709 | .get_nmi_mask = svm_get_nmi_mask, |
3710 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
3711 | .enable_nmi_window = enable_nmi_window, |
3712 | .enable_irq_window = enable_irq_window, | |
3713 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
3714 | |
3715 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 3716 | .get_tdp_level = get_npt_level, |
4b12f0de | 3717 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 3718 | |
586f9607 | 3719 | .get_exit_info = svm_get_exit_info, |
229456fc | 3720 | .exit_reasons_str = svm_exit_reasons_str, |
586f9607 | 3721 | |
17cc3935 | 3722 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
3723 | |
3724 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
3725 | |
3726 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
3727 | |
3728 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
3729 | |
3730 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
3731 | |
3732 | .write_tsc_offset = svm_write_tsc_offset, | |
e48672fa | 3733 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
1c97f0a0 JR |
3734 | |
3735 | .set_tdp_cr3 = set_tdp_cr3, | |
6aa8b732 AK |
3736 | }; |
3737 | ||
3738 | static int __init svm_init(void) | |
3739 | { | |
cb498ea2 | 3740 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 3741 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
3742 | } |
3743 | ||
3744 | static void __exit svm_exit(void) | |
3745 | { | |
cb498ea2 | 3746 | kvm_exit(); |
6aa8b732 AK |
3747 | } |
3748 | ||
3749 | module_init(svm_init) | |
3750 | module_exit(svm_exit) |