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KVM: SVM: Move guest register save out of interrupts disabled section
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 55
410e4d57
JR		 56#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
24e09cbf
JR		 60#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
67ec6607
JR		 62static bool erratum_383_found __read_mostly;
63
6c8166a7
AK		 64static const u32 host_save_user_msrs[] = {
65#ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68#endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70};
71
72#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74struct kvm_vcpu;
75
e6aa9abd
JR		 76struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
4a810181 79 u64 vm_cr_msr;
e6aa9abd
JR		 80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
ce2ac085 87 u64 vmcb_iopm;
aad42c64 88
cd3ff653
JR		 89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
cda00082
JR		 92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
aad42c64
JR		 100 /* cache for intercepts of the guest */
101 u16 intercept_cr_read;
102 u16 intercept_cr_write;
103 u16 intercept_dr_read;
104 u16 intercept_dr_write;
105 u32 intercept_exceptions;
106 u64 intercept;
107
5bd2edc3
JR		 108 /* Nested Paging related state */
109 u64 nested_cr3;
e6aa9abd
JR		 110};
111
323c3d80
JR		 112#define MSRPM_OFFSETS 16
113static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114
6c8166a7
AK		 115struct vcpu_svm {
116 struct kvm_vcpu vcpu;
117 struct vmcb *vmcb;
118 unsigned long vmcb_pa;
119 struct svm_cpu_data *svm_data;
120 uint64_t asid_generation;
121 uint64_t sysenter_esp;
122 uint64_t sysenter_eip;
123
124 u64 next_rip;
125
126 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
127 u64 host_gs_base;
6c8166a7
AK		 128
129 u32 *msrpm;
6c8166a7 130
e6aa9abd 131 struct nested_state nested;
6be7d306
JK		 132
133 bool nmi_singlestep;
66b7138f
JK		 134
135 unsigned int3_injected;
136 unsigned long int3_rip;
631bc487 137 u32 apf_reason;
6c8166a7
AK		 138};
139
455716fa
JR		 140#define MSR_INVALID 0xffffffffU
141
ac72a9b7
JR		 142static struct svm_direct_access_msrs {
143 u32 index; /* Index of the MSR */
144 bool always; /* True if intercept is always on */
145} direct_access_msrs[] = {
8c06585d 146 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 147 { .index = MSR_IA32_SYSENTER_CS, .always = true },
148#ifdef CONFIG_X86_64
149 { .index = MSR_GS_BASE, .always = true },
150 { .index = MSR_FS_BASE, .always = true },
151 { .index = MSR_KERNEL_GS_BASE, .always = true },
152 { .index = MSR_LSTAR, .always = true },
153 { .index = MSR_CSTAR, .always = true },
154 { .index = MSR_SYSCALL_MASK, .always = true },
155#endif
156 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
157 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
158 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
159 { .index = MSR_IA32_LASTINTTOIP, .always = false },
160 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 161};
162
709ddebf
JR		 163/* enable NPT for AMD64 and X86 with PAE */
164#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
165static bool npt_enabled = true;
166#else
e0231715 167static bool npt_enabled;
709ddebf 168#endif
6c7dac72
JR		 169static int npt = 1;
170
171module_param(npt, int, S_IRUGO);
e3da3acd 172
4b6e4dca 173static int nested = 1;
236de055
AG		 174module_param(nested, int, S_IRUGO);
175
44874f84 176static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 177static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 178
410e4d57 179static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 180static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 181static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 182static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
183 bool has_error_code, u32 error_code);
184
a2fa3e9f
GH		 185static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
186{
fb3f0f51 187 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 188}
189
3d6368ef
AG		 190static inline bool is_nested(struct vcpu_svm *svm)
191{
e6aa9abd 192 return svm->nested.vmcb;
3d6368ef
AG		 193}
194
2af9194d
JR		 195static inline void enable_gif(struct vcpu_svm *svm)
196{
197 svm->vcpu.arch.hflags |= HF_GIF_MASK;
198}
199
200static inline void disable_gif(struct vcpu_svm *svm)
201{
202 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
203}
204
205static inline bool gif_set(struct vcpu_svm *svm)
206{
207 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
208}
209
4866d5e3 210static unsigned long iopm_base;
6aa8b732
AK		 211
212struct kvm_ldttss_desc {
213 u16 limit0;
214 u16 base0;
e0231715
JR		 215 unsigned base1:8, type:5, dpl:2, p:1;
216 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 217 u32 base3;
218 u32 zero1;
219} __attribute__((packed));
220
221struct svm_cpu_data {
222 int cpu;
223
5008fdf5
AK		 224 u64 asid_generation;
225 u32 max_asid;
226 u32 next_asid;
6aa8b732
AK		 227 struct kvm_ldttss_desc *tss_desc;
228
229 struct page *save_area;
230};
231
232static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 233static uint32_t svm_features;
6aa8b732
AK		 234
235struct svm_init_data {
236 int cpu;
237 int r;
238};
239
240static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
241
9d8f549d 242#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 243#define MSRS_RANGE_SIZE 2048
244#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
245
455716fa
JR		 246static u32 svm_msrpm_offset(u32 msr)
247{
248 u32 offset;
249 int i;
250
251 for (i = 0; i < NUM_MSR_MAPS; i++) {
252 if (msr < msrpm_ranges[i] ||
253 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
254 continue;
255
256 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
257 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
258
259 /* Now we have the u8 offset - but need the u32 offset */
260 return offset / 4;
261 }
262
263 /* MSR not in any range */
264 return MSR_INVALID;
265}
266
6aa8b732
AK		 267#define MAX_INST_SIZE 15
268
80b7706e
JR		 269static inline u32 svm_has(u32 feat)
270{
271 return svm_features & feat;
272}
273
6aa8b732
AK		 274static inline void clgi(void)
275{
4ecac3fd 276 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 277}
278
279static inline void stgi(void)
280{
4ecac3fd 281 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 282}
283
284static inline void invlpga(unsigned long addr, u32 asid)
285{
e0231715 286 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 287}
288
6aa8b732
AK		 289static inline void force_new_asid(struct kvm_vcpu *vcpu)
290{
a2fa3e9f 291 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 292}
293
294static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
295{
296 force_new_asid(vcpu);
297}
298
4b16184c
JR		 299static int get_npt_level(void)
300{
301#ifdef CONFIG_X86_64
302 return PT64_ROOT_LEVEL;
303#else
304 return PT32E_ROOT_LEVEL;
305#endif
306}
307
6aa8b732
AK		 308static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
309{
6dc696d4 310 vcpu->arch.efer = efer;
709ddebf 311 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 312 efer &= ~EFER_LME;
6aa8b732 313
9962d032 314 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 315}
316
6aa8b732
AK		 317static int is_external_interrupt(u32 info)
318{
319 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
320 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
321}
322
2809f5d2
GC		 323static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
324{
325 struct vcpu_svm *svm = to_svm(vcpu);
326 u32 ret = 0;
327
328 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 329 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 330 return ret & mask;
331}
332
333static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
334{
335 struct vcpu_svm *svm = to_svm(vcpu);
336
337 if (mask == 0)
338 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
339 else
340 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
341
342}
343
6aa8b732
AK		 344static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
345{
a2fa3e9f
GH		 346 struct vcpu_svm *svm = to_svm(vcpu);
347
6bc31bdc
AP		 348 if (svm->vmcb->control.next_rip != 0)
349 svm->next_rip = svm->vmcb->control.next_rip;
350
a2fa3e9f 351 if (!svm->next_rip) {
851ba692 352 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 353 EMULATE_DONE)
354 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 355 return;
356 }
5fdbf976
MT		 357 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
358 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
359 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 360
5fdbf976 361 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 362 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 363}
364
116a4752 365static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 366 bool has_error_code, u32 error_code,
367 bool reinject)
116a4752
JK		 368{
369 struct vcpu_svm *svm = to_svm(vcpu);
370
e0231715
JR		 371 /*
372 * If we are within a nested VM we'd better #VMEXIT and let the guest
373 * handle the exception
374 */
ce7ddec4
JR		 375 if (!reinject &&
376 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 377 return;
378
66b7138f
JK		 379 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
380 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
381
382 /*
383 * For guest debugging where we have to reinject #BP if some
384 * INT3 is guest-owned:
385 * Emulate nRIP by moving RIP forward. Will fail if injection
386 * raises a fault that is not intercepted. Still better than
387 * failing in all cases.
388 */
389 skip_emulated_instruction(&svm->vcpu);
390 rip = kvm_rip_read(&svm->vcpu);
391 svm->int3_rip = rip + svm->vmcb->save.cs.base;
392 svm->int3_injected = rip - old_rip;
393 }
394
116a4752
JK		 395 svm->vmcb->control.event_inj = nr
396 | SVM_EVTINJ_VALID
397 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
398 | SVM_EVTINJ_TYPE_EXEPT;
399 svm->vmcb->control.event_inj_err = error_code;
400}
401
67ec6607
JR		 402static void svm_init_erratum_383(void)
403{
404 u32 low, high;
405 int err;
406 u64 val;
407
1be85a6d 408 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 409 return;
410
411 /* Use _safe variants to not break nested virtualization */
412 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
413 if (err)
414 return;
415
416 val |= (1ULL << 47);
417
418 low = lower_32_bits(val);
419 high = upper_32_bits(val);
420
421 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
422
423 erratum_383_found = true;
424}
425
6aa8b732
AK		 426static int has_svm(void)
427{
63d1142f 428 const char *msg;
6aa8b732 429
63d1142f 430 if (!cpu_has_svm(&msg)) {
ff81ff10 431 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 432 return 0;
433 }
434
6aa8b732
AK		 435 return 1;
436}
437
438static void svm_hardware_disable(void *garbage)
439{
2c8dceeb 440 cpu_svm_disable();
6aa8b732
AK		 441}
442
10474ae8 443static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 444{
445
0fe1e009 446 struct svm_cpu_data *sd;
6aa8b732 447 uint64_t efer;
89a27f4d 448 struct desc_ptr gdt_descr;
6aa8b732
AK		 449 struct desc_struct *gdt;
450 int me = raw_smp_processor_id();
451
10474ae8
AG		 452 rdmsrl(MSR_EFER, efer);
453 if (efer & EFER_SVME)
454 return -EBUSY;
455
6aa8b732 456 if (!has_svm()) {
e6732a5a
ZA		 457 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
458 me);
10474ae8 459 return -EINVAL;
6aa8b732 460 }
0fe1e009 461 sd = per_cpu(svm_data, me);
6aa8b732 462
0fe1e009 463 if (!sd) {
e6732a5a 464 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 465 me);
10474ae8 466 return -EINVAL;
6aa8b732
AK		 467 }
468
0fe1e009
TH		 469 sd->asid_generation = 1;
470 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
471 sd->next_asid = sd->max_asid + 1;
6aa8b732 472
d6ab1ed4 473 native_store_gdt(&gdt_descr);
89a27f4d 474 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 475 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 476
9962d032 477 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 478
d0316554 479 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 480
67ec6607
JR		 481 svm_init_erratum_383();
482
10474ae8 483 return 0;
6aa8b732
AK		 484}
485
0da1db75
JR		 486static void svm_cpu_uninit(int cpu)
487{
0fe1e009 488 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 489
0fe1e009 490 if (!sd)
0da1db75
JR		 491 return;
492
493 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 494 __free_page(sd->save_area);
495 kfree(sd);
0da1db75
JR		 496}
497
6aa8b732
AK		 498static int svm_cpu_init(int cpu)
499{
0fe1e009 500 struct svm_cpu_data *sd;
6aa8b732
AK		 501 int r;
502
0fe1e009
TH		 503 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
504 if (!sd)
6aa8b732 505 return -ENOMEM;
0fe1e009
TH		 506 sd->cpu = cpu;
507 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 508 r = -ENOMEM;
0fe1e009 509 if (!sd->save_area)
6aa8b732
AK		 510 goto err_1;
511
0fe1e009 512 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 513
514 return 0;
515
516err_1:
0fe1e009 517 kfree(sd);
6aa8b732
AK		 518 return r;
519
520}
521
ac72a9b7
JR		 522static bool valid_msr_intercept(u32 index)
523{
524 int i;
525
526 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
527 if (direct_access_msrs[i].index == index)
528 return true;
529
530 return false;
531}
532
bfc733a7
RR		 533static void set_msr_interception(u32 *msrpm, unsigned msr,
534 int read, int write)
6aa8b732 535{
455716fa
JR		 536 u8 bit_read, bit_write;
537 unsigned long tmp;
538 u32 offset;
6aa8b732 539
ac72a9b7
JR		 540 /*
541 * If this warning triggers extend the direct_access_msrs list at the
542 * beginning of the file
543 */
544 WARN_ON(!valid_msr_intercept(msr));
545
455716fa
JR		 546 offset = svm_msrpm_offset(msr);
547 bit_read = 2 * (msr & 0x0f);
548 bit_write = 2 * (msr & 0x0f) + 1;
549 tmp = msrpm[offset];
550
551 BUG_ON(offset == MSR_INVALID);
552
553 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
554 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
555
556 msrpm[offset] = tmp;
6aa8b732
AK		 557}
558
f65c229c 559static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 560{
561 int i;
562
f65c229c
JR		 563 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
564
ac72a9b7
JR		 565 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
566 if (!direct_access_msrs[i].always)
567 continue;
568
569 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
570 }
f65c229c
JR		 571}
572
323c3d80
JR		 573static void add_msr_offset(u32 offset)
574{
575 int i;
576
577 for (i = 0; i < MSRPM_OFFSETS; ++i) {
578
579 /* Offset already in list? */
580 if (msrpm_offsets[i] == offset)
bfc733a7 581 return;
323c3d80
JR		 582
583 /* Slot used by another offset? */
584 if (msrpm_offsets[i] != MSR_INVALID)
585 continue;
586
587 /* Add offset to list */
588 msrpm_offsets[i] = offset;
589
590 return;
6aa8b732 591 }
323c3d80
JR		 592
593 /*
594 * If this BUG triggers the msrpm_offsets table has an overflow. Just
595 * increase MSRPM_OFFSETS in this case.
596 */
bfc733a7 597 BUG();
6aa8b732
AK		 598}
599
323c3d80 600static void init_msrpm_offsets(void)
f65c229c 601{
323c3d80 602 int i;
f65c229c 603
323c3d80
JR		 604 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
605
606 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
607 u32 offset;
608
609 offset = svm_msrpm_offset(direct_access_msrs[i].index);
610 BUG_ON(offset == MSR_INVALID);
611
612 add_msr_offset(offset);
613 }
f65c229c
JR		 614}
615
24e09cbf
JR		 616static void svm_enable_lbrv(struct vcpu_svm *svm)
617{
618 u32 *msrpm = svm->msrpm;
619
620 svm->vmcb->control.lbr_ctl = 1;
621 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
622 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
623 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
624 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
625}
626
627static void svm_disable_lbrv(struct vcpu_svm *svm)
628{
629 u32 *msrpm = svm->msrpm;
630
631 svm->vmcb->control.lbr_ctl = 0;
632 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
633 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
634 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
635 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
636}
637
6aa8b732
AK		 638static __init int svm_hardware_setup(void)
639{
640 int cpu;
641 struct page *iopm_pages;
f65c229c 642 void *iopm_va;
6aa8b732
AK		 643 int r;
644
6aa8b732
AK		 645 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
646
647 if (!iopm_pages)
648 return -ENOMEM;
c8681339
AL		 649
650 iopm_va = page_address(iopm_pages);
651 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 652 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
653
323c3d80
JR		 654 init_msrpm_offsets();
655
50a37eb4
JR		 656 if (boot_cpu_has(X86_FEATURE_NX))
657 kvm_enable_efer_bits(EFER_NX);
658
1b2fd70c
AG		 659 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
660 kvm_enable_efer_bits(EFER_FFXSR);
661
236de055
AG		 662 if (nested) {
663 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 664 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 665 }
666
3230bb47 667 for_each_possible_cpu(cpu) {
6aa8b732
AK		 668 r = svm_cpu_init(cpu);
669 if (r)
f65c229c 670 goto err;
6aa8b732 671 }
33bd6a0b
JR		 672
673 svm_features = cpuid_edx(SVM_CPUID_FUNC);
674
e3da3acd
JR		 675 if (!svm_has(SVM_FEATURE_NPT))
676 npt_enabled = false;
677
6c7dac72
JR		 678 if (npt_enabled && !npt) {
679 printk(KERN_INFO "kvm: Nested Paging disabled\n");
680 npt_enabled = false;
681 }
682
18552672 683 if (npt_enabled) {
e3da3acd 684 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 685 kvm_enable_tdp();
5f4cb662
JR		 686 } else
687 kvm_disable_tdp();
e3da3acd 688
6aa8b732
AK		 689 return 0;
690
f65c229c 691err:
6aa8b732
AK		 692 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
693 iopm_base = 0;
694 return r;
695}
696
697static __exit void svm_hardware_unsetup(void)
698{
0da1db75
JR		 699 int cpu;
700
3230bb47 701 for_each_possible_cpu(cpu)
0da1db75
JR		 702 svm_cpu_uninit(cpu);
703
6aa8b732 704 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 705 iopm_base = 0;
6aa8b732
AK		 706}
707
708static void init_seg(struct vmcb_seg *seg)
709{
710 seg->selector = 0;
711 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 712 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 713 seg->limit = 0xffff;
714 seg->base = 0;
715}
716
717static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
718{
719 seg->selector = 0;
720 seg->attrib = SVM_SELECTOR_P_MASK | type;
721 seg->limit = 0xffff;
722 seg->base = 0;
723}
724
f4e1b3c8
ZA		 725static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
726{
727 struct vcpu_svm *svm = to_svm(vcpu);
728 u64 g_tsc_offset = 0;
729
730 if (is_nested(svm)) {
731 g_tsc_offset = svm->vmcb->control.tsc_offset -
732 svm->nested.hsave->control.tsc_offset;
733 svm->nested.hsave->control.tsc_offset = offset;
734 }
735
736 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
737}
738
e48672fa
ZA		 739static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
740{
741 struct vcpu_svm *svm = to_svm(vcpu);
742
743 svm->vmcb->control.tsc_offset += adjustment;
744 if (is_nested(svm))
745 svm->nested.hsave->control.tsc_offset += adjustment;
746}
747
e6101a96 748static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 749{
e6101a96
JR		 750 struct vmcb_control_area *control = &svm->vmcb->control;
751 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 752
bff78274
AK		 753 svm->vcpu.fpu_active = 1;
754
e0231715 755 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 756 INTERCEPT_CR3_MASK |
649d6864 757 INTERCEPT_CR4_MASK;
6aa8b732 758
e0231715 759 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 760 INTERCEPT_CR3_MASK |
80a8119c
AK		 761 INTERCEPT_CR4_MASK |
762 INTERCEPT_CR8_MASK;
6aa8b732 763
e0231715 764 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 765 INTERCEPT_DR1_MASK |
766 INTERCEPT_DR2_MASK |
727f5a23
JK		 767 INTERCEPT_DR3_MASK |
768 INTERCEPT_DR4_MASK |
769 INTERCEPT_DR5_MASK |
770 INTERCEPT_DR6_MASK |
771 INTERCEPT_DR7_MASK;
6aa8b732 772
e0231715 773 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 774 INTERCEPT_DR1_MASK |
775 INTERCEPT_DR2_MASK |
776 INTERCEPT_DR3_MASK |
727f5a23 777 INTERCEPT_DR4_MASK |
6aa8b732 778 INTERCEPT_DR5_MASK |
727f5a23 779 INTERCEPT_DR6_MASK |
6aa8b732
AK		 780 INTERCEPT_DR7_MASK;
781
7aa81cc0 782 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 783 (1 << UD_VECTOR) |
784 (1 << MC_VECTOR);
6aa8b732
AK		 785
786
e0231715 787 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 788 (1ULL << INTERCEPT_NMI) |
0152527b 789 (1ULL << INTERCEPT_SMI) |
d225157b 790 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 791 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 792 (1ULL << INTERCEPT_INVD) |
6aa8b732 793 (1ULL << INTERCEPT_HLT) |
a7052897 794 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 795 (1ULL << INTERCEPT_INVLPGA) |
796 (1ULL << INTERCEPT_IOIO_PROT) |
797 (1ULL << INTERCEPT_MSR_PROT) |
798 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 799 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 800 (1ULL << INTERCEPT_VMRUN) |
801 (1ULL << INTERCEPT_VMMCALL) |
802 (1ULL << INTERCEPT_VMLOAD) |
803 (1ULL << INTERCEPT_VMSAVE) |
804 (1ULL << INTERCEPT_STGI) |
805 (1ULL << INTERCEPT_CLGI) |
916ce236 806 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 807 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 808 (1ULL << INTERCEPT_MONITOR) |
809 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 810
811 control->iopm_base_pa = iopm_base;
f65c229c 812 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 813 control->int_ctl = V_INTR_MASKING_MASK;
814
815 init_seg(&save->es);
816 init_seg(&save->ss);
817 init_seg(&save->ds);
818 init_seg(&save->fs);
819 init_seg(&save->gs);
820
821 save->cs.selector = 0xf000;
822 /* Executable/Readable Code Segment */
823 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
824 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
825 save->cs.limit = 0xffff;
d92899a0
AK		 826 /*
827 * cs.base should really be 0xffff0000, but vmx can't handle that, so
828 * be consistent with it.
829 *
830 * Replace when we have real mode working for vmx.
831 */
832 save->cs.base = 0xf0000;
6aa8b732
AK		 833
834 save->gdtr.limit = 0xffff;
835 save->idtr.limit = 0xffff;
836
837 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
838 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
839
eaa48512 840 svm_set_efer(&svm->vcpu, 0);
d77c26fc 841 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 842 save->dr7 = 0x400;
843 save->rflags = 2;
844 save->rip = 0x0000fff0;
5fdbf976 845 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 846
e0231715
JR		 847 /*
848 * This is the guest-visible cr0 value.
18fa000a 849 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 850 */
678041ad
MT		 851 svm->vcpu.arch.cr0 = 0;
852 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 853
66aee91a 854 save->cr4 = X86_CR4_PAE;
6aa8b732 855 /* rdx = ?? */
709ddebf
JR		 856
857 if (npt_enabled) {
858 /* Setup VMCB for Nested Paging */
859 control->nested_ctl = 1;
a7052897
MT		 860 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
861 (1ULL << INTERCEPT_INVLPG));
709ddebf 862 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 863 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
864 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 865 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 866 save->cr3 = 0;
867 save->cr4 = 0;
868 }
a79d2f18 869 force_new_asid(&svm->vcpu);
1371d904 870
e6aa9abd 871 svm->nested.vmcb = 0;
2af9194d
JR		 872 svm->vcpu.arch.hflags = 0;
873
565d0998
ML		 874 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
875 control->pause_filter_count = 3000;
876 control->intercept |= (1ULL << INTERCEPT_PAUSE);
877 }
878
2af9194d 879 enable_gif(svm);
6aa8b732
AK		 880}
881
e00c8cf2 882static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 883{
884 struct vcpu_svm *svm = to_svm(vcpu);
885
e6101a96 886 init_vmcb(svm);
70433389 887
c5af89b6 888 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 889 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 890 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
891 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 892 }
5fdbf976
MT		 893 vcpu->arch.regs_avail = ~0;
894 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 895
896 return 0;
04d2cc77
AK		 897}
898
fb3f0f51 899static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 900{
a2fa3e9f 901 struct vcpu_svm *svm;
6aa8b732 902 struct page *page;
f65c229c 903 struct page *msrpm_pages;
b286d5d8 904 struct page *hsave_page;
3d6368ef 905 struct page *nested_msrpm_pages;
fb3f0f51 906 int err;
6aa8b732 907
c16f862d 908 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 909 if (!svm) {
910 err = -ENOMEM;
911 goto out;
912 }
913
914 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
915 if (err)
916 goto free_svm;
917
b7af4043 918 err = -ENOMEM;
6aa8b732 919 page = alloc_page(GFP_KERNEL);
b7af4043 920 if (!page)
fb3f0f51 921 goto uninit;
6aa8b732 922
f65c229c
JR		 923 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
924 if (!msrpm_pages)
b7af4043 925 goto free_page1;
3d6368ef
AG		 926
927 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
928 if (!nested_msrpm_pages)
b7af4043 929 goto free_page2;
f65c229c 930
b286d5d8
AG		 931 hsave_page = alloc_page(GFP_KERNEL);
932 if (!hsave_page)
b7af4043
TY		 933 goto free_page3;
934
e6aa9abd 935 svm->nested.hsave = page_address(hsave_page);
b286d5d8 936
b7af4043
TY		 937 svm->msrpm = page_address(msrpm_pages);
938 svm_vcpu_init_msrpm(svm->msrpm);
939
e6aa9abd 940 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 941 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 942
a2fa3e9f
GH		 943 svm->vmcb = page_address(page);
944 clear_page(svm->vmcb);
945 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
946 svm->asid_generation = 0;
e6101a96 947 init_vmcb(svm);
99e3e30a 948 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 949
10ab25cd
JK		 950 err = fx_init(&svm->vcpu);
951 if (err)
952 goto free_page4;
953
ad312c7c 954 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 955 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 956 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 957
fb3f0f51 958 return &svm->vcpu;
36241b8c 959
10ab25cd
JK		 960free_page4:
961 __free_page(hsave_page);
b7af4043
TY		 962free_page3:
963 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
964free_page2:
965 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
966free_page1:
967 __free_page(page);
fb3f0f51
RR		 968uninit:
969 kvm_vcpu_uninit(&svm->vcpu);
970free_svm:
a4770347 971 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 972out:
973 return ERR_PTR(err);
6aa8b732
AK		 974}
975
976static void svm_free_vcpu(struct kvm_vcpu *vcpu)
977{
a2fa3e9f
GH		 978 struct vcpu_svm *svm = to_svm(vcpu);
979
fb3f0f51 980 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 981 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 982 __free_page(virt_to_page(svm->nested.hsave));
983 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 984 kvm_vcpu_uninit(vcpu);
a4770347 985 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 986}
987
15ad7146 988static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 989{
a2fa3e9f 990 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 991 int i;
0cc5064d 992
0cc5064d 993 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 994 svm->asid_generation = 0;
0cc5064d 995 }
94dfbdb3
AL		 996
997 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 998 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 999}
1000
1001static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1002{
a2fa3e9f 1003 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1004 int i;
1005
e1beb1d3 1006 ++vcpu->stat.host_state_reload;
94dfbdb3 1007 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1008 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1009}
1010
6aa8b732
AK		 1011static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1012{
a2fa3e9f 1013 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1014}
1015
1016static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1017{
a2fa3e9f 1018 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1019}
1020
6de4f3ad
AK		 1021static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1022{
1023 switch (reg) {
1024 case VCPU_EXREG_PDPTR:
1025 BUG_ON(!npt_enabled);
ff03a073 1026 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1027 break;
1028 default:
1029 BUG();
1030 }
1031}
1032
f0b85051
AG		 1033static void svm_set_vintr(struct vcpu_svm *svm)
1034{
1035 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1036}
1037
1038static void svm_clear_vintr(struct vcpu_svm *svm)
1039{
1040 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1041}
1042
6aa8b732
AK		 1043static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1044{
a2fa3e9f 1045 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1046
1047 switch (seg) {
1048 case VCPU_SREG_CS: return &save->cs;
1049 case VCPU_SREG_DS: return &save->ds;
1050 case VCPU_SREG_ES: return &save->es;
1051 case VCPU_SREG_FS: return &save->fs;
1052 case VCPU_SREG_GS: return &save->gs;
1053 case VCPU_SREG_SS: return &save->ss;
1054 case VCPU_SREG_TR: return &save->tr;
1055 case VCPU_SREG_LDTR: return &save->ldtr;
1056 }
1057 BUG();
8b6d44c7 1058 return NULL;
6aa8b732
AK		 1059}
1060
1061static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1062{
1063 struct vmcb_seg *s = svm_seg(vcpu, seg);
1064
1065 return s->base;
1066}
1067
1068static void svm_get_segment(struct kvm_vcpu *vcpu,
1069 struct kvm_segment *var, int seg)
1070{
1071 struct vmcb_seg *s = svm_seg(vcpu, seg);
1072
1073 var->base = s->base;
1074 var->limit = s->limit;
1075 var->selector = s->selector;
1076 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1077 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1078 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1079 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1080 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1081 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1082 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1083 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1084
e0231715
JR		 1085 /*
1086 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1087 * for cross vendor migration purposes by "not present"
1088 */
1089 var->unusable = !var->present || (var->type == 0);
1090
1fbdc7a5
AP		 1091 switch (seg) {
1092 case VCPU_SREG_CS:
1093 /*
1094 * SVM always stores 0 for the 'G' bit in the CS selector in
1095 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1096 * Intel's VMENTRY has a check on the 'G' bit.
1097 */
25022acc 1098 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1099 break;
1100 case VCPU_SREG_TR:
1101 /*
1102 * Work around a bug where the busy flag in the tr selector
1103 * isn't exposed
1104 */
c0d09828 1105 var->type |= 0x2;
1fbdc7a5
AP		 1106 break;
1107 case VCPU_SREG_DS:
1108 case VCPU_SREG_ES:
1109 case VCPU_SREG_FS:
1110 case VCPU_SREG_GS:
1111 /*
1112 * The accessed bit must always be set in the segment
1113 * descriptor cache, although it can be cleared in the
1114 * descriptor, the cached bit always remains at 1. Since
1115 * Intel has a check on this, set it here to support
1116 * cross-vendor migration.
1117 */
1118 if (!var->unusable)
1119 var->type |= 0x1;
1120 break;
b586eb02 1121 case VCPU_SREG_SS:
e0231715
JR		 1122 /*
1123 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1124 * descriptor is left as 1, although the whole segment has
1125 * been made unusable. Clear it here to pass an Intel VMX
1126 * entry check when cross vendor migrating.
1127 */
1128 if (var->unusable)
1129 var->db = 0;
1130 break;
1fbdc7a5 1131 }
6aa8b732
AK		 1132}
1133
2e4d2653
IE		 1134static int svm_get_cpl(struct kvm_vcpu *vcpu)
1135{
1136 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1137
1138 return save->cpl;
1139}
1140
89a27f4d 1141static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1142{
a2fa3e9f
GH		 1143 struct vcpu_svm *svm = to_svm(vcpu);
1144
89a27f4d
GN		 1145 dt->size = svm->vmcb->save.idtr.limit;
1146 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1147}
1148
89a27f4d 1149static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1150{
a2fa3e9f
GH		 1151 struct vcpu_svm *svm = to_svm(vcpu);
1152
89a27f4d
GN		 1153 svm->vmcb->save.idtr.limit = dt->size;
1154 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1155}
1156
89a27f4d 1157static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1158{
a2fa3e9f
GH		 1159 struct vcpu_svm *svm = to_svm(vcpu);
1160
89a27f4d
GN		 1161 dt->size = svm->vmcb->save.gdtr.limit;
1162 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1163}
1164
89a27f4d 1165static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1166{
a2fa3e9f
GH		 1167 struct vcpu_svm *svm = to_svm(vcpu);
1168
89a27f4d
GN		 1169 svm->vmcb->save.gdtr.limit = dt->size;
1170 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1171}
1172
e8467fda
AK		 1173static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1174{
1175}
1176
25c4c276 1177static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1178{
1179}
1180
d225157b
AK		 1181static void update_cr0_intercept(struct vcpu_svm *svm)
1182{
66a562f7 1183 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1184 ulong gcr0 = svm->vcpu.arch.cr0;
1185 u64 *hcr0 = &svm->vmcb->save.cr0;
1186
1187 if (!svm->vcpu.fpu_active)
1188 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1189 else
1190 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1191 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1192
1193
1194 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1195 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1196 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1197 if (is_nested(svm)) {
1198 struct vmcb *hsave = svm->nested.hsave;
1199
1200 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1201 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1202 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1203 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1204 }
d225157b
AK		 1205 } else {
1206 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1207 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1208 if (is_nested(svm)) {
1209 struct vmcb *hsave = svm->nested.hsave;
1210
1211 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1212 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1213 }
d225157b
AK		 1214 }
1215}
1216
6aa8b732
AK		 1217static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1218{
a2fa3e9f
GH		 1219 struct vcpu_svm *svm = to_svm(vcpu);
1220
7f5d8b56
JR		 1221 if (is_nested(svm)) {
1222 /*
1223 * We are here because we run in nested mode, the host kvm
1224 * intercepts cr0 writes but the l1 hypervisor does not.
1225 * But the L1 hypervisor may intercept selective cr0 writes.
1226 * This needs to be checked here.
1227 */
1228 unsigned long old, new;
1229
1230 /* Remove bits that would trigger a real cr0 write intercept */
1231 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1232 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1233
1234 if (old == new) {
1235 /* cr0 write with ts and mp unchanged */
1236 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1237 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1238 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1239 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1240 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1241 return;
cda00082 1242 }
7f5d8b56
JR		 1243 }
1244 }
1245
05b3e0c2 1246#ifdef CONFIG_X86_64
f6801dff 1247 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1248 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1249 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1250 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1251 }
1252
d77c26fc 1253 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1254 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1255 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1256 }
1257 }
1258#endif
ad312c7c 1259 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1260
1261 if (!npt_enabled)
1262 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1263
1264 if (!vcpu->fpu_active)
334df50a 1265 cr0 |= X86_CR0_TS;
709ddebf
JR		 1266 /*
1267 * re-enable caching here because the QEMU bios
1268 * does not do it - this results in some delay at
1269 * reboot
1270 */
1271 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1272 svm->vmcb->save.cr0 = cr0;
d225157b 1273 update_cr0_intercept(svm);
6aa8b732
AK		 1274}
1275
1276static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1277{
6394b649 1278 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1279 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1280
1281 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1282 force_new_asid(vcpu);
6394b649 1283
ec077263
JR		 1284 vcpu->arch.cr4 = cr4;
1285 if (!npt_enabled)
1286 cr4 |= X86_CR4_PAE;
6394b649 1287 cr4 |= host_cr4_mce;
ec077263 1288 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1289}
1290
1291static void svm_set_segment(struct kvm_vcpu *vcpu,
1292 struct kvm_segment *var, int seg)
1293{
a2fa3e9f 1294 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1295 struct vmcb_seg *s = svm_seg(vcpu, seg);
1296
1297 s->base = var->base;
1298 s->limit = var->limit;
1299 s->selector = var->selector;
1300 if (var->unusable)
1301 s->attrib = 0;
1302 else {
1303 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1304 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1305 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1306 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1307 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1308 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1309 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1310 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1311 }
1312 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1313 svm->vmcb->save.cpl
1314 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1315 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1316
1317}
1318
44c11430 1319static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1320{
d0bfb940
JK		 1321 struct vcpu_svm *svm = to_svm(vcpu);
1322
d0bfb940
JK		 1323 svm->vmcb->control.intercept_exceptions &=
1324 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1325
6be7d306 1326 if (svm->nmi_singlestep)
44c11430
GN		 1327 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1328
d0bfb940
JK		 1329 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1330 if (vcpu->guest_debug &
1331 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1332 svm->vmcb->control.intercept_exceptions |=
1333 1 << DB_VECTOR;
1334 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1335 svm->vmcb->control.intercept_exceptions |=
1336 1 << BP_VECTOR;
1337 } else
1338 vcpu->guest_debug = 0;
44c11430
GN		 1339}
1340
355be0b9 1341static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1342{
44c11430
GN		 1343 struct vcpu_svm *svm = to_svm(vcpu);
1344
ae675ef0
JK		 1345 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1346 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1347 else
1348 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1349
355be0b9 1350 update_db_intercept(vcpu);
6aa8b732
AK		 1351}
1352
1353static void load_host_msrs(struct kvm_vcpu *vcpu)
1354{
94dfbdb3 1355#ifdef CONFIG_X86_64
a2fa3e9f 1356 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1357#endif
6aa8b732
AK		 1358}
1359
1360static void save_host_msrs(struct kvm_vcpu *vcpu)
1361{
94dfbdb3 1362#ifdef CONFIG_X86_64
a2fa3e9f 1363 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1364#endif
6aa8b732
AK		 1365}
1366
0fe1e009 1367static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1368{
0fe1e009
TH		 1369 if (sd->next_asid > sd->max_asid) {
1370 ++sd->asid_generation;
1371 sd->next_asid = 1;
a2fa3e9f 1372 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1373 }
1374
0fe1e009
TH		 1375 svm->asid_generation = sd->asid_generation;
1376 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1377}
1378
020df079 1379static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1380{
42dbaa5a 1381 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1382
020df079 1383 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1384}
1385
851ba692 1386static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1387{
631bc487 1388 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1389 u32 error_code;
631bc487 1390 int r = 1;
6aa8b732 1391
631bc487
GN		 1392 switch (svm->apf_reason) {
1393 default:
1394 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1395
631bc487
GN		 1396 trace_kvm_page_fault(fault_address, error_code);
1397 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1398 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1399 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1400 break;
1401 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1402 svm->apf_reason = 0;
1403 local_irq_disable();
1404 kvm_async_pf_task_wait(fault_address);
1405 local_irq_enable();
1406 break;
1407 case KVM_PV_REASON_PAGE_READY:
1408 svm->apf_reason = 0;
1409 local_irq_disable();
1410 kvm_async_pf_task_wake(fault_address);
1411 local_irq_enable();
1412 break;
1413 }
1414 return r;
6aa8b732
AK		 1415}
1416
851ba692 1417static int db_interception(struct vcpu_svm *svm)
d0bfb940 1418{
851ba692
AK		 1419 struct kvm_run *kvm_run = svm->vcpu.run;
1420
d0bfb940 1421 if (!(svm->vcpu.guest_debug &
44c11430 1422 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1423 !svm->nmi_singlestep) {
d0bfb940
JK		 1424 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1425 return 1;
1426 }
44c11430 1427
6be7d306
JK		 1428 if (svm->nmi_singlestep) {
1429 svm->nmi_singlestep = false;
44c11430
GN		 1430 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1431 svm->vmcb->save.rflags &=
1432 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1433 update_db_intercept(&svm->vcpu);
1434 }
1435
1436 if (svm->vcpu.guest_debug &
e0231715 1437 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1438 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1439 kvm_run->debug.arch.pc =
1440 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1441 kvm_run->debug.arch.exception = DB_VECTOR;
1442 return 0;
1443 }
1444
1445 return 1;
d0bfb940
JK		 1446}
1447
851ba692 1448static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1449{
851ba692
AK		 1450 struct kvm_run *kvm_run = svm->vcpu.run;
1451
d0bfb940
JK		 1452 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1453 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1454 kvm_run->debug.arch.exception = BP_VECTOR;
1455 return 0;
1456}
1457
851ba692 1458static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1459{
1460 int er;
1461
851ba692 1462 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1463 if (er != EMULATE_DONE)
7ee5d940 1464 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1465 return 1;
1466}
1467
6b52d186 1468static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1469{
6b52d186 1470 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1471 u32 excp;
1472
1473 if (is_nested(svm)) {
1474 u32 h_excp, n_excp;
1475
1476 h_excp = svm->nested.hsave->control.intercept_exceptions;
1477 n_excp = svm->nested.intercept_exceptions;
1478 h_excp &= ~(1 << NM_VECTOR);
1479 excp = h_excp | n_excp;
1480 } else {
1481 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1482 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1483 }
1484
1485 svm->vmcb->control.intercept_exceptions = excp;
1486
e756fc62 1487 svm->vcpu.fpu_active = 1;
d225157b 1488 update_cr0_intercept(svm);
6b52d186 1489}
a2fa3e9f 1490
6b52d186
AK		 1491static int nm_interception(struct vcpu_svm *svm)
1492{
1493 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1494 return 1;
7807fa6c
AL		 1495}
1496
67ec6607
JR		 1497static bool is_erratum_383(void)
1498{
1499 int err, i;
1500 u64 value;
1501
1502 if (!erratum_383_found)
1503 return false;
1504
1505 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1506 if (err)
1507 return false;
1508
1509 /* Bit 62 may or may not be set for this mce */
1510 value &= ~(1ULL << 62);
1511
1512 if (value != 0xb600000000010015ULL)
1513 return false;
1514
1515 /* Clear MCi_STATUS registers */
1516 for (i = 0; i < 6; ++i)
1517 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1518
1519 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1520 if (!err) {
1521 u32 low, high;
1522
1523 value &= ~(1ULL << 2);
1524 low = lower_32_bits(value);
1525 high = upper_32_bits(value);
1526
1527 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1528 }
1529
1530 /* Flush tlb to evict multi-match entries */
1531 __flush_tlb_all();
1532
1533 return true;
1534}
1535
fe5913e4 1536static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1537{
67ec6607
JR		 1538 if (is_erratum_383()) {
1539 /*
1540 * Erratum 383 triggered. Guest state is corrupt so kill the
1541 * guest.
1542 */
1543 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1544
a8eeb04a 1545 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1546
1547 return;
1548 }
1549
53371b50
JR		 1550 /*
1551 * On an #MC intercept the MCE handler is not called automatically in
1552 * the host. So do it by hand here.
1553 */
1554 asm volatile (
1555 "int $0x12\n");
1556 /* not sure if we ever come back to this point */
1557
fe5913e4
JR		 1558 return;
1559}
1560
1561static int mc_interception(struct vcpu_svm *svm)
1562{
53371b50
JR		 1563 return 1;
1564}
1565
851ba692 1566static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1567{
851ba692
AK		 1568 struct kvm_run *kvm_run = svm->vcpu.run;
1569
46fe4ddd
JR		 1570 /*
1571 * VMCB is undefined after a SHUTDOWN intercept
1572 * so reinitialize it.
1573 */
a2fa3e9f 1574 clear_page(svm->vmcb);
e6101a96 1575 init_vmcb(svm);
46fe4ddd
JR		 1576
1577 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1578 return 0;
1579}
1580
851ba692 1581static int io_interception(struct vcpu_svm *svm)
6aa8b732 1582{
cf8f70bf 1583 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1584 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1585 int size, in, string;
039576c0 1586 unsigned port;
6aa8b732 1587
e756fc62 1588 ++svm->vcpu.stat.io_exits;
e70669ab 1589 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1590 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1591 if (string || in)
6d77dbfc 1592 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1593
039576c0
AK		 1594 port = io_info >> 16;
1595 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1596 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1597 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1598
1599 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1600}
1601
851ba692 1602static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1603{
1604 return 1;
1605}
1606
851ba692 1607static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1608{
1609 ++svm->vcpu.stat.irq_exits;
1610 return 1;
1611}
1612
851ba692 1613static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1614{
1615 return 1;
1616}
1617
851ba692 1618static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1619{
5fdbf976 1620 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1621 skip_emulated_instruction(&svm->vcpu);
1622 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1623}
1624
851ba692 1625static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1626{
5fdbf976 1627 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1628 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1629 kvm_emulate_hypercall(&svm->vcpu);
1630 return 1;
02e235bc
AK		 1631}
1632
5bd2edc3
JR		 1633static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1634{
1635 struct vcpu_svm *svm = to_svm(vcpu);
1636
1637 return svm->nested.nested_cr3;
1638}
1639
1640static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1641 unsigned long root)
1642{
1643 struct vcpu_svm *svm = to_svm(vcpu);
1644
1645 svm->vmcb->control.nested_cr3 = root;
1646 force_new_asid(vcpu);
1647}
1648
1649static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu)
1650{
1651 struct vcpu_svm *svm = to_svm(vcpu);
1652
1653 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1654 svm->vmcb->control.exit_code_hi = 0;
1655 svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code;
1656 svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address;
1657
1658 nested_svm_vmexit(svm);
1659}
1660
4b16184c
JR		 1661static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1662{
1663 int r;
1664
1665 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1666
1667 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1668 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1669 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1670 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1671 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1672
1673 return r;
1674}
1675
1676static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1677{
1678 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1679}
1680
c0725420
AG		 1681static int nested_svm_check_permissions(struct vcpu_svm *svm)
1682{
f6801dff 1683 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1684 || !is_paging(&svm->vcpu)) {
1685 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1686 return 1;
1687 }
1688
1689 if (svm->vmcb->save.cpl) {
1690 kvm_inject_gp(&svm->vcpu, 0);
1691 return 1;
1692 }
1693
1694 return 0;
1695}
1696
cf74a78b
AG		 1697static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1698 bool has_error_code, u32 error_code)
1699{
b8e88bc8
JR		 1700 int vmexit;
1701
0295ad7d
JR		 1702 if (!is_nested(svm))
1703 return 0;
cf74a78b 1704
0295ad7d
JR		 1705 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1706 svm->vmcb->control.exit_code_hi = 0;
1707 svm->vmcb->control.exit_info_1 = error_code;
1708 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1709
b8e88bc8
JR		 1710 vmexit = nested_svm_intercept(svm);
1711 if (vmexit == NESTED_EXIT_DONE)
1712 svm->nested.exit_required = true;
1713
1714 return vmexit;
cf74a78b
AG		 1715}
1716
8fe54654
JR		 1717/* This function returns true if it is save to enable the irq window */
1718static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1719{
26666957 1720 if (!is_nested(svm))
8fe54654 1721 return true;
cf74a78b 1722
26666957 1723 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1724 return true;
cf74a78b 1725
26666957 1726 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1727 return false;
cf74a78b 1728
a0a07cd2
GN		 1729 /*
1730 * if vmexit was already requested (by intercepted exception
1731 * for instance) do not overwrite it with "external interrupt"
1732 * vmexit.
1733 */
1734 if (svm->nested.exit_required)
1735 return false;
1736
197717d5
JR		 1737 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1738 svm->vmcb->control.exit_info_1 = 0;
1739 svm->vmcb->control.exit_info_2 = 0;
26666957 1740
cd3ff653
JR		 1741 if (svm->nested.intercept & 1ULL) {
1742 /*
1743 * The #vmexit can't be emulated here directly because this
1744 * code path runs with irqs and preemtion disabled. A
1745 * #vmexit emulation might sleep. Only signal request for
1746 * the #vmexit here.
1747 */
1748 svm->nested.exit_required = true;
236649de 1749 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1750 return false;
cf74a78b
AG		 1751 }
1752
8fe54654 1753 return true;
cf74a78b
AG		 1754}
1755
887f500c
JR		 1756/* This function returns true if it is save to enable the nmi window */
1757static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1758{
1759 if (!is_nested(svm))
1760 return true;
1761
1762 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1763 return true;
1764
1765 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1766 svm->nested.exit_required = true;
1767
1768 return false;
cf74a78b
AG		 1769}
1770
7597f129 1771static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1772{
1773 struct page *page;
1774
6c3bd3d7
JR		 1775 might_sleep();
1776
34f80cfa 1777 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1778 if (is_error_page(page))
1779 goto error;
1780
7597f129
JR		 1781 *_page = page;
1782
1783 return kmap(page);
34f80cfa
JR		 1784
1785error:
1786 kvm_release_page_clean(page);
1787 kvm_inject_gp(&svm->vcpu, 0);
1788
1789 return NULL;
1790}
1791
7597f129 1792static void nested_svm_unmap(struct page *page)
34f80cfa 1793{
7597f129 1794 kunmap(page);
34f80cfa
JR		 1795 kvm_release_page_dirty(page);
1796}
34f80cfa 1797
ce2ac085
JR		 1798static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1799{
1800 unsigned port;
1801 u8 val, bit;
1802 u64 gpa;
34f80cfa 1803
ce2ac085
JR		 1804 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1805 return NESTED_EXIT_HOST;
34f80cfa 1806
ce2ac085
JR		 1807 port = svm->vmcb->control.exit_info_1 >> 16;
1808 gpa = svm->nested.vmcb_iopm + (port / 8);
1809 bit = port % 8;
1810 val = 0;
1811
1812 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1813 val &= (1 << bit);
1814
1815 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1816}
1817
d2477826 1818static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1819{
0d6b3537
JR		 1820 u32 offset, msr, value;
1821 int write, mask;
4c2161ae 1822
3d62d9aa 1823 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1824 return NESTED_EXIT_HOST;
3d62d9aa 1825
0d6b3537
JR		 1826 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1827 offset = svm_msrpm_offset(msr);
1828 write = svm->vmcb->control.exit_info_1 & 1;
1829 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1830
0d6b3537
JR		 1831 if (offset == MSR_INVALID)
1832 return NESTED_EXIT_DONE;
4c2161ae 1833
0d6b3537
JR		 1834 /* Offset is in 32 bit units but need in 8 bit units */
1835 offset *= 4;
4c2161ae 1836
0d6b3537
JR		 1837 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1838 return NESTED_EXIT_DONE;
3d62d9aa 1839
0d6b3537 1840 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1841}
1842
410e4d57 1843static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1844{
cf74a78b 1845 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1846
410e4d57
JR		 1847 switch (exit_code) {
1848 case SVM_EXIT_INTR:
1849 case SVM_EXIT_NMI:
ff47a49b 1850 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1851 return NESTED_EXIT_HOST;
410e4d57 1852 case SVM_EXIT_NPF:
e0231715 1853 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1854 if (npt_enabled)
1855 return NESTED_EXIT_HOST;
1856 break;
410e4d57 1857 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 1858 /* When we're shadowing, trap PFs, but not async PF */
1859 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 1860 return NESTED_EXIT_HOST;
1861 break;
66a562f7
JR		 1862 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1863 nm_interception(svm);
1864 break;
410e4d57
JR		 1865 default:
1866 break;
cf74a78b
AG		 1867 }
1868
410e4d57
JR		 1869 return NESTED_EXIT_CONTINUE;
1870}
1871
1872/*
1873 * If this function returns true, this #vmexit was already handled
1874 */
b8e88bc8 1875static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1876{
1877 u32 exit_code = svm->vmcb->control.exit_code;
1878 int vmexit = NESTED_EXIT_HOST;
1879
cf74a78b 1880 switch (exit_code) {
9c4e40b9 1881 case SVM_EXIT_MSR:
3d62d9aa 1882 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1883 break;
ce2ac085
JR		 1884 case SVM_EXIT_IOIO:
1885 vmexit = nested_svm_intercept_ioio(svm);
1886 break;
cf74a78b
AG		 1887 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1888 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1889 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1890 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1891 break;
1892 }
1893 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1894 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1895 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1896 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1897 break;
1898 }
1899 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1900 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1901 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1902 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1903 break;
1904 }
1905 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1906 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1907 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1908 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1909 break;
1910 }
1911 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1912 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1913 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1914 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 1915 /* async page fault always cause vmexit */
1916 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1917 svm->apf_reason != 0)
1918 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1919 break;
1920 }
228070b1
JR		 1921 case SVM_EXIT_ERR: {
1922 vmexit = NESTED_EXIT_DONE;
1923 break;
1924 }
cf74a78b
AG		 1925 default: {
1926 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1927 if (svm->nested.intercept & exit_bits)
410e4d57 1928 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1929 }
1930 }
1931
b8e88bc8
JR		 1932 return vmexit;
1933}
1934
1935static int nested_svm_exit_handled(struct vcpu_svm *svm)
1936{
1937 int vmexit;
1938
1939 vmexit = nested_svm_intercept(svm);
1940
1941 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1942 nested_svm_vmexit(svm);
9c4e40b9
JR		 1943
1944 return vmexit;
cf74a78b
AG		 1945}
1946
0460a979
JR		 1947static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1948{
1949 struct vmcb_control_area *dst = &dst_vmcb->control;
1950 struct vmcb_control_area *from = &from_vmcb->control;
1951
1952 dst->intercept_cr_read = from->intercept_cr_read;
1953 dst->intercept_cr_write = from->intercept_cr_write;
1954 dst->intercept_dr_read = from->intercept_dr_read;
1955 dst->intercept_dr_write = from->intercept_dr_write;
1956 dst->intercept_exceptions = from->intercept_exceptions;
1957 dst->intercept = from->intercept;
1958 dst->iopm_base_pa = from->iopm_base_pa;
1959 dst->msrpm_base_pa = from->msrpm_base_pa;
1960 dst->tsc_offset = from->tsc_offset;
1961 dst->asid = from->asid;
1962 dst->tlb_ctl = from->tlb_ctl;
1963 dst->int_ctl = from->int_ctl;
1964 dst->int_vector = from->int_vector;
1965 dst->int_state = from->int_state;
1966 dst->exit_code = from->exit_code;
1967 dst->exit_code_hi = from->exit_code_hi;
1968 dst->exit_info_1 = from->exit_info_1;
1969 dst->exit_info_2 = from->exit_info_2;
1970 dst->exit_int_info = from->exit_int_info;
1971 dst->exit_int_info_err = from->exit_int_info_err;
1972 dst->nested_ctl = from->nested_ctl;
1973 dst->event_inj = from->event_inj;
1974 dst->event_inj_err = from->event_inj_err;
1975 dst->nested_cr3 = from->nested_cr3;
1976 dst->lbr_ctl = from->lbr_ctl;
1977}
1978
34f80cfa 1979static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1980{
34f80cfa 1981 struct vmcb *nested_vmcb;
e6aa9abd 1982 struct vmcb *hsave = svm->nested.hsave;
33740e40 1983 struct vmcb *vmcb = svm->vmcb;
7597f129 1984 struct page *page;
cf74a78b 1985
17897f36
JR		 1986 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1987 vmcb->control.exit_info_1,
1988 vmcb->control.exit_info_2,
1989 vmcb->control.exit_int_info,
1990 vmcb->control.exit_int_info_err);
1991
7597f129 1992 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1993 if (!nested_vmcb)
1994 return 1;
1995
06fc7772
JR		 1996 /* Exit nested SVM mode */
1997 svm->nested.vmcb = 0;
1998
cf74a78b 1999 /* Give the current vmcb to the guest */
33740e40
JR		 2000 disable_gif(svm);
2001
2002 nested_vmcb->save.es = vmcb->save.es;
2003 nested_vmcb->save.cs = vmcb->save.cs;
2004 nested_vmcb->save.ss = vmcb->save.ss;
2005 nested_vmcb->save.ds = vmcb->save.ds;
2006 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2007 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2008 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2009 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 2010 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 2011 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2012 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 2013 nested_vmcb->save.rflags = vmcb->save.rflags;
2014 nested_vmcb->save.rip = vmcb->save.rip;
2015 nested_vmcb->save.rsp = vmcb->save.rsp;
2016 nested_vmcb->save.rax = vmcb->save.rax;
2017 nested_vmcb->save.dr7 = vmcb->save.dr7;
2018 nested_vmcb->save.dr6 = vmcb->save.dr6;
2019 nested_vmcb->save.cpl = vmcb->save.cpl;
2020
2021 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2022 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2023 nested_vmcb->control.int_state = vmcb->control.int_state;
2024 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2025 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2026 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2027 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2028 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2029 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2030 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2031
2032 /*
2033 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2034 * to make sure that we do not lose injected events. So check event_inj
2035 * here and copy it to exit_int_info if it is valid.
2036 * Exit_int_info and event_inj can't be both valid because the case
2037 * below only happens on a VMRUN instruction intercept which has
2038 * no valid exit_int_info set.
2039 */
2040 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2041 struct vmcb_control_area *nc = &nested_vmcb->control;
2042
2043 nc->exit_int_info = vmcb->control.event_inj;
2044 nc->exit_int_info_err = vmcb->control.event_inj_err;
2045 }
2046
33740e40
JR		 2047 nested_vmcb->control.tlb_ctl = 0;
2048 nested_vmcb->control.event_inj = 0;
2049 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2050
2051 /* We always set V_INTR_MASKING and remember the old value in hflags */
2052 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2053 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2054
cf74a78b 2055 /* Restore the original control entries */
0460a979 2056 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2057
219b65dc
AG		 2058 kvm_clear_exception_queue(&svm->vcpu);
2059 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2060
4b16184c
JR		 2061 svm->nested.nested_cr3 = 0;
2062
cf74a78b
AG		 2063 /* Restore selected save entries */
2064 svm->vmcb->save.es = hsave->save.es;
2065 svm->vmcb->save.cs = hsave->save.cs;
2066 svm->vmcb->save.ss = hsave->save.ss;
2067 svm->vmcb->save.ds = hsave->save.ds;
2068 svm->vmcb->save.gdtr = hsave->save.gdtr;
2069 svm->vmcb->save.idtr = hsave->save.idtr;
2070 svm->vmcb->save.rflags = hsave->save.rflags;
2071 svm_set_efer(&svm->vcpu, hsave->save.efer);
2072 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2073 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2074 if (npt_enabled) {
2075 svm->vmcb->save.cr3 = hsave->save.cr3;
2076 svm->vcpu.arch.cr3 = hsave->save.cr3;
2077 } else {
2390218b 2078 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2079 }
2080 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2081 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2082 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2083 svm->vmcb->save.dr7 = 0;
2084 svm->vmcb->save.cpl = 0;
2085 svm->vmcb->control.exit_int_info = 0;
2086
7597f129 2087 nested_svm_unmap(page);
cf74a78b 2088
4b16184c 2089 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2090 kvm_mmu_reset_context(&svm->vcpu);
2091 kvm_mmu_load(&svm->vcpu);
2092
2093 return 0;
2094}
3d6368ef 2095
9738b2c9 2096static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2097{
323c3d80
JR		 2098 /*
2099 * This function merges the msr permission bitmaps of kvm and the
2100 * nested vmcb. It is omptimized in that it only merges the parts where
2101 * the kvm msr permission bitmap may contain zero bits
2102 */
3d6368ef 2103 int i;
9738b2c9 2104
323c3d80
JR		 2105 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2106 return true;
9738b2c9 2107
323c3d80
JR		 2108 for (i = 0; i < MSRPM_OFFSETS; i++) {
2109 u32 value, p;
2110 u64 offset;
9738b2c9 2111
323c3d80
JR		 2112 if (msrpm_offsets[i] == 0xffffffff)
2113 break;
3d6368ef 2114
0d6b3537
JR		 2115 p = msrpm_offsets[i];
2116 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2117
2118 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2119 return false;
2120
2121 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2122 }
3d6368ef 2123
323c3d80 2124 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2125
2126 return true;
3d6368ef
AG		 2127}
2128
52c65a30
JR		 2129static bool nested_vmcb_checks(struct vmcb *vmcb)
2130{
2131 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2132 return false;
2133
dbe77584
JR		 2134 if (vmcb->control.asid == 0)
2135 return false;
2136
4b16184c
JR		 2137 if (vmcb->control.nested_ctl && !npt_enabled)
2138 return false;
2139
52c65a30
JR		 2140 return true;
2141}
2142
9738b2c9 2143static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2144{
9738b2c9 2145 struct vmcb *nested_vmcb;
e6aa9abd 2146 struct vmcb *hsave = svm->nested.hsave;
defbba56 2147 struct vmcb *vmcb = svm->vmcb;
7597f129 2148 struct page *page;
06fc7772 2149 u64 vmcb_gpa;
3d6368ef 2150
06fc7772 2151 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2152
7597f129 2153 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2154 if (!nested_vmcb)
2155 return false;
2156
52c65a30
JR		 2157 if (!nested_vmcb_checks(nested_vmcb)) {
2158 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2159 nested_vmcb->control.exit_code_hi = 0;
2160 nested_vmcb->control.exit_info_1 = 0;
2161 nested_vmcb->control.exit_info_2 = 0;
2162
2163 nested_svm_unmap(page);
2164
2165 return false;
2166 }
2167
b75f4eb3 2168 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2169 nested_vmcb->save.rip,
2170 nested_vmcb->control.int_ctl,
2171 nested_vmcb->control.event_inj,
2172 nested_vmcb->control.nested_ctl);
2173
2e554e8d
JR		 2174 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2175 nested_vmcb->control.intercept_cr_write,
2176 nested_vmcb->control.intercept_exceptions,
2177 nested_vmcb->control.intercept);
2178
3d6368ef 2179 /* Clear internal status */
219b65dc
AG		 2180 kvm_clear_exception_queue(&svm->vcpu);
2181 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2182
e0231715
JR		 2183 /*
2184 * Save the old vmcb, so we don't need to pick what we save, but can
2185 * restore everything when a VMEXIT occurs
2186 */
defbba56
JR		 2187 hsave->save.es = vmcb->save.es;
2188 hsave->save.cs = vmcb->save.cs;
2189 hsave->save.ss = vmcb->save.ss;
2190 hsave->save.ds = vmcb->save.ds;
2191 hsave->save.gdtr = vmcb->save.gdtr;
2192 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2193 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2194 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2195 hsave->save.cr4 = svm->vcpu.arch.cr4;
2196 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2197 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2198 hsave->save.rsp = vmcb->save.rsp;
2199 hsave->save.rax = vmcb->save.rax;
2200 if (npt_enabled)
2201 hsave->save.cr3 = vmcb->save.cr3;
2202 else
2203 hsave->save.cr3 = svm->vcpu.arch.cr3;
2204
0460a979 2205 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2206
2207 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2208 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2209 else
2210 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2211
4b16184c
JR		 2212 if (nested_vmcb->control.nested_ctl) {
2213 kvm_mmu_unload(&svm->vcpu);
2214 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2215 nested_svm_init_mmu_context(&svm->vcpu);
2216 }
2217
3d6368ef
AG		 2218 /* Load the nested guest state */
2219 svm->vmcb->save.es = nested_vmcb->save.es;
2220 svm->vmcb->save.cs = nested_vmcb->save.cs;
2221 svm->vmcb->save.ss = nested_vmcb->save.ss;
2222 svm->vmcb->save.ds = nested_vmcb->save.ds;
2223 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2224 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2225 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2226 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2227 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2228 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2229 if (npt_enabled) {
2230 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2231 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2232 } else
2390218b 2233 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2234
2235 /* Guest paging mode is active - reset mmu */
2236 kvm_mmu_reset_context(&svm->vcpu);
2237
defbba56 2238 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2239 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2240 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2241 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2242
3d6368ef
AG		 2243 /* In case we don't even reach vcpu_run, the fields are not updated */
2244 svm->vmcb->save.rax = nested_vmcb->save.rax;
2245 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2246 svm->vmcb->save.rip = nested_vmcb->save.rip;
2247 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2248 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2249 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2250
f7138538 2251 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2252 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2253
aad42c64
JR		 2254 /* cache intercepts */
2255 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2256 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2257 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2258 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2259 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2260 svm->nested.intercept = nested_vmcb->control.intercept;
2261
3d6368ef 2262 force_new_asid(&svm->vcpu);
3d6368ef 2263 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2264 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2265 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2266 else
2267 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2268
88ab24ad
JR		 2269 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2270 /* We only want the cr8 intercept bits of the guest */
2271 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2272 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2273 }
2274
0d945bd9
JR		 2275 /* We don't want to see VMMCALLs from a nested guest */
2276 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2277
e0231715
JR		 2278 /*
2279 * We don't want a nested guest to be more powerful than the guest, so
2280 * all intercepts are ORed
2281 */
88ab24ad
JR		 2282 svm->vmcb->control.intercept_cr_read |=
2283 nested_vmcb->control.intercept_cr_read;
2284 svm->vmcb->control.intercept_cr_write |=
2285 nested_vmcb->control.intercept_cr_write;
2286 svm->vmcb->control.intercept_dr_read |=
2287 nested_vmcb->control.intercept_dr_read;
2288 svm->vmcb->control.intercept_dr_write |=
2289 nested_vmcb->control.intercept_dr_write;
2290 svm->vmcb->control.intercept_exceptions |=
2291 nested_vmcb->control.intercept_exceptions;
2292
2293 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2294
2295 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2296 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2297 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2298 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2299 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2300 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2301
7597f129 2302 nested_svm_unmap(page);
9738b2c9 2303
06fc7772
JR		 2304 /* nested_vmcb is our indicator if nested SVM is activated */
2305 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2306
2af9194d 2307 enable_gif(svm);
3d6368ef 2308
9738b2c9 2309 return true;
3d6368ef
AG		 2310}
2311
9966bf68 2312static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2313{
2314 to_vmcb->save.fs = from_vmcb->save.fs;
2315 to_vmcb->save.gs = from_vmcb->save.gs;
2316 to_vmcb->save.tr = from_vmcb->save.tr;
2317 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2318 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2319 to_vmcb->save.star = from_vmcb->save.star;
2320 to_vmcb->save.lstar = from_vmcb->save.lstar;
2321 to_vmcb->save.cstar = from_vmcb->save.cstar;
2322 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2323 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2324 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2325 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2326}
2327
851ba692 2328static int vmload_interception(struct vcpu_svm *svm)
5542675b 2329{
9966bf68 2330 struct vmcb *nested_vmcb;
7597f129 2331 struct page *page;
9966bf68 2332
5542675b
AG		 2333 if (nested_svm_check_permissions(svm))
2334 return 1;
2335
2336 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2337 skip_emulated_instruction(&svm->vcpu);
2338
7597f129 2339 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2340 if (!nested_vmcb)
2341 return 1;
2342
2343 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2344 nested_svm_unmap(page);
5542675b
AG		 2345
2346 return 1;
2347}
2348
851ba692 2349static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2350{
9966bf68 2351 struct vmcb *nested_vmcb;
7597f129 2352 struct page *page;
9966bf68 2353
5542675b
AG		 2354 if (nested_svm_check_permissions(svm))
2355 return 1;
2356
2357 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2358 skip_emulated_instruction(&svm->vcpu);
2359
7597f129 2360 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2361 if (!nested_vmcb)
2362 return 1;
2363
2364 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2365 nested_svm_unmap(page);
5542675b
AG		 2366
2367 return 1;
2368}
2369
851ba692 2370static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2371{
3d6368ef
AG		 2372 if (nested_svm_check_permissions(svm))
2373 return 1;
2374
b75f4eb3
RJ		 2375 /* Save rip after vmrun instruction */
2376 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2377
9738b2c9 2378 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2379 return 1;
2380
9738b2c9 2381 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2382 goto failed;
2383
2384 return 1;
2385
2386failed:
2387
2388 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2389 svm->vmcb->control.exit_code_hi = 0;
2390 svm->vmcb->control.exit_info_1 = 0;
2391 svm->vmcb->control.exit_info_2 = 0;
2392
2393 nested_svm_vmexit(svm);
3d6368ef
AG		 2394
2395 return 1;
2396}
2397
851ba692 2398static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2399{
2400 if (nested_svm_check_permissions(svm))
2401 return 1;
2402
2403 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2404 skip_emulated_instruction(&svm->vcpu);
3842d135 2405 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2406
2af9194d 2407 enable_gif(svm);
1371d904
AG		 2408
2409 return 1;
2410}
2411
851ba692 2412static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2413{
2414 if (nested_svm_check_permissions(svm))
2415 return 1;
2416
2417 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2418 skip_emulated_instruction(&svm->vcpu);
2419
2af9194d 2420 disable_gif(svm);
1371d904
AG		 2421
2422 /* After a CLGI no interrupts should come */
2423 svm_clear_vintr(svm);
2424 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2425
2426 return 1;
2427}
2428
851ba692 2429static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2430{
2431 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2432
ec1ff790
JR		 2433 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2434 vcpu->arch.regs[VCPU_REGS_RAX]);
2435
ff092385
AG		 2436 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2437 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2438
2439 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2440 skip_emulated_instruction(&svm->vcpu);
2441 return 1;
2442}
2443
532a46b9
JR		 2444static int skinit_interception(struct vcpu_svm *svm)
2445{
2446 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2447
2448 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2449 return 1;
2450}
2451
851ba692 2452static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2453{
7ee5d940 2454 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2455 return 1;
2456}
2457
851ba692 2458static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2459{
37817f29 2460 u16 tss_selector;
64a7ec06
GN		 2461 int reason;
2462 int int_type = svm->vmcb->control.exit_int_info &
2463 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2464 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2465 uint32_t type =
2466 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2467 uint32_t idt_v =
2468 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2469 bool has_error_code = false;
2470 u32 error_code = 0;
37817f29
IE		 2471
2472 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2473
37817f29
IE		 2474 if (svm->vmcb->control.exit_info_2 &
2475 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2476 reason = TASK_SWITCH_IRET;
2477 else if (svm->vmcb->control.exit_info_2 &
2478 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2479 reason = TASK_SWITCH_JMP;
fe8e7f83 2480 else if (idt_v)
64a7ec06
GN		 2481 reason = TASK_SWITCH_GATE;
2482 else
2483 reason = TASK_SWITCH_CALL;
2484
fe8e7f83
GN		 2485 if (reason == TASK_SWITCH_GATE) {
2486 switch (type) {
2487 case SVM_EXITINTINFO_TYPE_NMI:
2488 svm->vcpu.arch.nmi_injected = false;
2489 break;
2490 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2491 if (svm->vmcb->control.exit_info_2 &
2492 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2493 has_error_code = true;
2494 error_code =
2495 (u32)svm->vmcb->control.exit_info_2;
2496 }
fe8e7f83
GN		 2497 kvm_clear_exception_queue(&svm->vcpu);
2498 break;
2499 case SVM_EXITINTINFO_TYPE_INTR:
2500 kvm_clear_interrupt_queue(&svm->vcpu);
2501 break;
2502 default:
2503 break;
2504 }
2505 }
64a7ec06 2506
8317c298
GN		 2507 if (reason != TASK_SWITCH_GATE ||
2508 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2509 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2510 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2511 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2512
acb54517
GN		 2513 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2514 has_error_code, error_code) == EMULATE_FAIL) {
2515 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2516 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2517 svm->vcpu.run->internal.ndata = 0;
2518 return 0;
2519 }
2520 return 1;
6aa8b732
AK		 2521}
2522
851ba692 2523static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2524{
5fdbf976 2525 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2526 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2527 return 1;
6aa8b732
AK		 2528}
2529
851ba692 2530static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2531{
2532 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2533 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2534 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2535 return 1;
2536}
2537
851ba692 2538static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2539{
6d77dbfc 2540 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2541}
2542
851ba692 2543static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2544{
6d77dbfc 2545 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2546}
2547
cda00082
JR		 2548static int cr0_write_interception(struct vcpu_svm *svm)
2549{
2550 struct kvm_vcpu *vcpu = &svm->vcpu;
2551 int r;
2552
2553 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2554
2555 if (svm->nested.vmexit_rip) {
2556 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2557 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2558 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2559 svm->nested.vmexit_rip = 0;
2560 }
2561
2562 return r == EMULATE_DONE;
2563}
2564
851ba692 2565static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2566{
851ba692
AK		 2567 struct kvm_run *kvm_run = svm->vcpu.run;
2568
0a5fff19
GN		 2569 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2570 /* instruction emulation calls kvm_set_cr8() */
851ba692 2571 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2572 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2573 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2574 return 1;
95ba8273 2575 }
0a5fff19
GN		 2576 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2577 return 1;
1d075434
JR		 2578 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2579 return 0;
2580}
2581
6aa8b732
AK		 2582static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2583{
a2fa3e9f
GH		 2584 struct vcpu_svm *svm = to_svm(vcpu);
2585
6aa8b732 2586 switch (ecx) {
af24a4e4 2587 case MSR_IA32_TSC: {
20824f30 2588 u64 tsc_offset;
6aa8b732 2589
20824f30
JR		 2590 if (is_nested(svm))
2591 tsc_offset = svm->nested.hsave->control.tsc_offset;
2592 else
2593 tsc_offset = svm->vmcb->control.tsc_offset;
2594
2595 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2596 break;
2597 }
8c06585d 2598 case MSR_STAR:
a2fa3e9f 2599 *data = svm->vmcb->save.star;
6aa8b732 2600 break;
0e859cac 2601#ifdef CONFIG_X86_64
6aa8b732 2602 case MSR_LSTAR:
a2fa3e9f 2603 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2604 break;
2605 case MSR_CSTAR:
a2fa3e9f 2606 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2607 break;
2608 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2609 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2610 break;
2611 case MSR_SYSCALL_MASK:
a2fa3e9f 2612 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2613 break;
2614#endif
2615 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2616 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2617 break;
2618 case MSR_IA32_SYSENTER_EIP:
017cb99e 2619 *data = svm->sysenter_eip;
6aa8b732
AK		 2620 break;
2621 case MSR_IA32_SYSENTER_ESP:
017cb99e 2622 *data = svm->sysenter_esp;
6aa8b732 2623 break;
e0231715
JR		 2624 /*
2625 * Nobody will change the following 5 values in the VMCB so we can
2626 * safely return them on rdmsr. They will always be 0 until LBRV is
2627 * implemented.
2628 */
a2938c80
JR		 2629 case MSR_IA32_DEBUGCTLMSR:
2630 *data = svm->vmcb->save.dbgctl;
2631 break;
2632 case MSR_IA32_LASTBRANCHFROMIP:
2633 *data = svm->vmcb->save.br_from;
2634 break;
2635 case MSR_IA32_LASTBRANCHTOIP:
2636 *data = svm->vmcb->save.br_to;
2637 break;
2638 case MSR_IA32_LASTINTFROMIP:
2639 *data = svm->vmcb->save.last_excp_from;
2640 break;
2641 case MSR_IA32_LASTINTTOIP:
2642 *data = svm->vmcb->save.last_excp_to;
2643 break;
b286d5d8 2644 case MSR_VM_HSAVE_PA:
e6aa9abd 2645 *data = svm->nested.hsave_msr;
b286d5d8 2646 break;
eb6f302e 2647 case MSR_VM_CR:
4a810181 2648 *data = svm->nested.vm_cr_msr;
eb6f302e 2649 break;
c8a73f18
AG		 2650 case MSR_IA32_UCODE_REV:
2651 *data = 0x01000065;
2652 break;
6aa8b732 2653 default:
3bab1f5d 2654 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2655 }
2656 return 0;
2657}
2658
851ba692 2659static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2660{
ad312c7c 2661 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2662 u64 data;
2663
59200273
AK		 2664 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2665 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2666 kvm_inject_gp(&svm->vcpu, 0);
59200273 2667 } else {
229456fc 2668 trace_kvm_msr_read(ecx, data);
af9ca2d7 2669
5fdbf976 2670 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2671 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2672 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2673 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2674 }
2675 return 1;
2676}
2677
4a810181
JR		 2678static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2679{
2680 struct vcpu_svm *svm = to_svm(vcpu);
2681 int svm_dis, chg_mask;
2682
2683 if (data & ~SVM_VM_CR_VALID_MASK)
2684 return 1;
2685
2686 chg_mask = SVM_VM_CR_VALID_MASK;
2687
2688 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2689 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2690
2691 svm->nested.vm_cr_msr &= ~chg_mask;
2692 svm->nested.vm_cr_msr |= (data & chg_mask);
2693
2694 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2695
2696 /* check for svm_disable while efer.svme is set */
2697 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2698 return 1;
2699
2700 return 0;
2701}
2702
6aa8b732
AK		 2703static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2704{
a2fa3e9f
GH		 2705 struct vcpu_svm *svm = to_svm(vcpu);
2706
6aa8b732 2707 switch (ecx) {
f4e1b3c8 2708 case MSR_IA32_TSC:
99e3e30a 2709 kvm_write_tsc(vcpu, data);
6aa8b732 2710 break;
8c06585d 2711 case MSR_STAR:
a2fa3e9f 2712 svm->vmcb->save.star = data;
6aa8b732 2713 break;
49b14f24 2714#ifdef CONFIG_X86_64
6aa8b732 2715 case MSR_LSTAR:
a2fa3e9f 2716 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2717 break;
2718 case MSR_CSTAR:
a2fa3e9f 2719 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2720 break;
2721 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2722 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2723 break;
2724 case MSR_SYSCALL_MASK:
a2fa3e9f 2725 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2726 break;
2727#endif
2728 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2729 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2730 break;
2731 case MSR_IA32_SYSENTER_EIP:
017cb99e 2732 svm->sysenter_eip = data;
a2fa3e9f 2733 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2734 break;
2735 case MSR_IA32_SYSENTER_ESP:
017cb99e 2736 svm->sysenter_esp = data;
a2fa3e9f 2737 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2738 break;
a2938c80 2739 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2740 if (!svm_has(SVM_FEATURE_LBRV)) {
2741 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2742 __func__, data);
24e09cbf
JR		 2743 break;
2744 }
2745 if (data & DEBUGCTL_RESERVED_BITS)
2746 return 1;
2747
2748 svm->vmcb->save.dbgctl = data;
2749 if (data & (1ULL<<0))
2750 svm_enable_lbrv(svm);
2751 else
2752 svm_disable_lbrv(svm);
a2938c80 2753 break;
b286d5d8 2754 case MSR_VM_HSAVE_PA:
e6aa9abd 2755 svm->nested.hsave_msr = data;
62b9abaa 2756 break;
3c5d0a44 2757 case MSR_VM_CR:
4a810181 2758 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2759 case MSR_VM_IGNNE:
3c5d0a44
AG		 2760 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2761 break;
6aa8b732 2762 default:
3bab1f5d 2763 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2764 }
2765 return 0;
2766}
2767
851ba692 2768static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2769{
ad312c7c 2770 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2771 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2772 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2773
af9ca2d7 2774
5fdbf976 2775 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2776 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2777 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2778 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2779 } else {
2780 trace_kvm_msr_write(ecx, data);
e756fc62 2781 skip_emulated_instruction(&svm->vcpu);
59200273 2782 }
6aa8b732
AK		 2783 return 1;
2784}
2785
851ba692 2786static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2787{
e756fc62 2788 if (svm->vmcb->control.exit_info_1)
851ba692 2789 return wrmsr_interception(svm);
6aa8b732 2790 else
851ba692 2791 return rdmsr_interception(svm);
6aa8b732
AK		 2792}
2793
851ba692 2794static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2795{
851ba692
AK		 2796 struct kvm_run *kvm_run = svm->vcpu.run;
2797
3842d135 2798 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2799 svm_clear_vintr(svm);
85f455f7 2800 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2801 /*
2802 * If the user space waits to inject interrupts, exit as soon as
2803 * possible
2804 */
8061823a
GN		 2805 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2806 kvm_run->request_interrupt_window &&
2807 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2808 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2809 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2810 return 0;
2811 }
2812
2813 return 1;
2814}
2815
565d0998
ML		 2816static int pause_interception(struct vcpu_svm *svm)
2817{
2818 kvm_vcpu_on_spin(&(svm->vcpu));
2819 return 1;
2820}
2821
851ba692 2822static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2823 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2824 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2825 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2826 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2827 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2828 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2829 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2830 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2831 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2832 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2833 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2834 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2835 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2836 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2837 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2838 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2839 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2840 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2841 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2842 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2843 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2844 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2845 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2846 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2847 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2848 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2849 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2850 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2851 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2852 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2853 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2854 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2855 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2856 [SVM_EXIT_SMI] = nop_on_interception,
2857 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2858 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2859 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2860 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2861 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2862 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2863 [SVM_EXIT_HLT] = halt_interception,
a7052897 2864 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2865 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2866 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2867 [SVM_EXIT_MSR] = msr_interception,
2868 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2869 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2870 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2871 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2872 [SVM_EXIT_VMLOAD] = vmload_interception,
2873 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2874 [SVM_EXIT_STGI] = stgi_interception,
2875 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2876 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2877 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2878 [SVM_EXIT_MONITOR] = invalid_op_interception,
2879 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2880 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2881};
2882
3f10c846
JR		 2883void dump_vmcb(struct kvm_vcpu *vcpu)
2884{
2885 struct vcpu_svm *svm = to_svm(vcpu);
2886 struct vmcb_control_area *control = &svm->vmcb->control;
2887 struct vmcb_save_area *save = &svm->vmcb->save;
2888
2889 pr_err("VMCB Control Area:\n");
2890 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2891 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2892 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2893 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2894 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2895 pr_err("intercepts: %016llx\n", control->intercept);
2896 pr_err("pause filter count: %d\n", control->pause_filter_count);
2897 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2898 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2899 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2900 pr_err("asid: %d\n", control->asid);
2901 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2902 pr_err("int_ctl: %08x\n", control->int_ctl);
2903 pr_err("int_vector: %08x\n", control->int_vector);
2904 pr_err("int_state: %08x\n", control->int_state);
2905 pr_err("exit_code: %08x\n", control->exit_code);
2906 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2907 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2908 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2909 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2910 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2911 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2912 pr_err("event_inj: %08x\n", control->event_inj);
2913 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2914 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2915 pr_err("next_rip: %016llx\n", control->next_rip);
2916 pr_err("VMCB State Save Area:\n");
2917 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2918 save->es.selector, save->es.attrib,
2919 save->es.limit, save->es.base);
2920 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2921 save->cs.selector, save->cs.attrib,
2922 save->cs.limit, save->cs.base);
2923 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2924 save->ss.selector, save->ss.attrib,
2925 save->ss.limit, save->ss.base);
2926 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2927 save->ds.selector, save->ds.attrib,
2928 save->ds.limit, save->ds.base);
2929 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2930 save->fs.selector, save->fs.attrib,
2931 save->fs.limit, save->fs.base);
2932 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2933 save->gs.selector, save->gs.attrib,
2934 save->gs.limit, save->gs.base);
2935 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2936 save->gdtr.selector, save->gdtr.attrib,
2937 save->gdtr.limit, save->gdtr.base);
2938 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2939 save->ldtr.selector, save->ldtr.attrib,
2940 save->ldtr.limit, save->ldtr.base);
2941 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2942 save->idtr.selector, save->idtr.attrib,
2943 save->idtr.limit, save->idtr.base);
2944 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2945 save->tr.selector, save->tr.attrib,
2946 save->tr.limit, save->tr.base);
2947 pr_err("cpl: %d efer: %016llx\n",
2948 save->cpl, save->efer);
2949 pr_err("cr0: %016llx cr2: %016llx\n",
2950 save->cr0, save->cr2);
2951 pr_err("cr3: %016llx cr4: %016llx\n",
2952 save->cr3, save->cr4);
2953 pr_err("dr6: %016llx dr7: %016llx\n",
2954 save->dr6, save->dr7);
2955 pr_err("rip: %016llx rflags: %016llx\n",
2956 save->rip, save->rflags);
2957 pr_err("rsp: %016llx rax: %016llx\n",
2958 save->rsp, save->rax);
2959 pr_err("star: %016llx lstar: %016llx\n",
2960 save->star, save->lstar);
2961 pr_err("cstar: %016llx sfmask: %016llx\n",
2962 save->cstar, save->sfmask);
2963 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2964 save->kernel_gs_base, save->sysenter_cs);
2965 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2966 save->sysenter_esp, save->sysenter_eip);
2967 pr_err("gpat: %016llx dbgctl: %016llx\n",
2968 save->g_pat, save->dbgctl);
2969 pr_err("br_from: %016llx br_to: %016llx\n",
2970 save->br_from, save->br_to);
2971 pr_err("excp_from: %016llx excp_to: %016llx\n",
2972 save->last_excp_from, save->last_excp_to);
2973
2974}
2975
851ba692 2976static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2977{
04d2cc77 2978 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2979 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2980 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2981
5bfd8b54 2982 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2983
2be4fc7a
JR		 2984 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2985 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2986 if (npt_enabled)
2987 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2988
cd3ff653
JR		 2989 if (unlikely(svm->nested.exit_required)) {
2990 nested_svm_vmexit(svm);
2991 svm->nested.exit_required = false;
2992
2993 return 1;
2994 }
2995
cf74a78b 2996 if (is_nested(svm)) {
410e4d57
JR		 2997 int vmexit;
2998
d8cabddf
JR		 2999 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3000 svm->vmcb->control.exit_info_1,
3001 svm->vmcb->control.exit_info_2,
3002 svm->vmcb->control.exit_int_info,
3003 svm->vmcb->control.exit_int_info_err);
3004
410e4d57
JR		 3005 vmexit = nested_svm_exit_special(svm);
3006
3007 if (vmexit == NESTED_EXIT_CONTINUE)
3008 vmexit = nested_svm_exit_handled(svm);
3009
3010 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3011 return 1;
cf74a78b
AG		 3012 }
3013
a5c3832d
JR		 3014 svm_complete_interrupts(svm);
3015
04d2cc77
AK		 3016 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3017 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3018 kvm_run->fail_entry.hardware_entry_failure_reason
3019 = svm->vmcb->control.exit_code;
3f10c846
JR		 3020 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3021 dump_vmcb(vcpu);
04d2cc77
AK		 3022 return 0;
3023 }
3024
a2fa3e9f 3025 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3026 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3027 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3028 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3029 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3030 "exit_code 0x%x\n",
b8688d51 3031 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3032 exit_code);
3033
9d8f549d 3034 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3035 || !svm_exit_handlers[exit_code]) {
6aa8b732 3036 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3037 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3038 return 0;
3039 }
3040
851ba692 3041 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3042}
3043
3044static void reload_tss(struct kvm_vcpu *vcpu)
3045{
3046 int cpu = raw_smp_processor_id();
3047
0fe1e009
TH		 3048 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3049 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3050 load_TR_desc();
3051}
3052
e756fc62 3053static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3054{
3055 int cpu = raw_smp_processor_id();
3056
0fe1e009 3057 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3058
a2fa3e9f 3059 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 3060 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3061 if (svm->asid_generation != sd->asid_generation)
3062 new_asid(svm, sd);
6aa8b732
AK		 3063}
3064
95ba8273
GN		 3065static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3066{
3067 struct vcpu_svm *svm = to_svm(vcpu);
3068
3069 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3070 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 3071 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 3072 ++vcpu->stat.nmi_injections;
3073}
6aa8b732 3074
85f455f7 3075static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3076{
3077 struct vmcb_control_area *control;
3078
e756fc62 3079 control = &svm->vmcb->control;
85f455f7 3080 control->int_vector = irq;
6aa8b732
AK		 3081 control->int_ctl &= ~V_INTR_PRIO_MASK;
3082 control->int_ctl |= V_IRQ_MASK |
3083 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3084}
3085
66fd3f7f 3086static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3087{
3088 struct vcpu_svm *svm = to_svm(vcpu);
3089
2af9194d 3090 BUG_ON(!(gif_set(svm)));
cf74a78b 3091
9fb2d2b4
GN		 3092 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3093 ++vcpu->stat.irq_injections;
3094
219b65dc
AG		 3095 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3096 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3097}
3098
95ba8273 3099static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3100{
3101 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3102
88ab24ad
JR		 3103 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3104 return;
3105
95ba8273 3106 if (irr == -1)
aaacfc9a
JR		 3107 return;
3108
95ba8273
GN		 3109 if (tpr >= irr)
3110 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3111}
aaacfc9a 3112
95ba8273
GN		 3113static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3114{
3115 struct vcpu_svm *svm = to_svm(vcpu);
3116 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3117 int ret;
3118 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3119 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3120 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3121
3122 return ret;
aaacfc9a
JR		 3123}
3124
3cfc3092
JK		 3125static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3126{
3127 struct vcpu_svm *svm = to_svm(vcpu);
3128
3129 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3130}
3131
3132static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3133{
3134 struct vcpu_svm *svm = to_svm(vcpu);
3135
3136 if (masked) {
3137 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3138 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3139 } else {
3140 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3141 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3142 }
3143}
3144
78646121
GN		 3145static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3146{
3147 struct vcpu_svm *svm = to_svm(vcpu);
3148 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3149 int ret;
3150
3151 if (!gif_set(svm) ||
3152 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3153 return 0;
3154
3155 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3156
3157 if (is_nested(svm))
3158 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3159
3160 return ret;
78646121
GN		 3161}
3162
9222be18 3163static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3164{
219b65dc 3165 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3166
e0231715
JR		 3167 /*
3168 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3169 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3170 * get that intercept, this function will be called again though and
3171 * we'll get the vintr intercept.
3172 */
8fe54654 3173 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3174 svm_set_vintr(svm);
3175 svm_inject_irq(svm, 0x0);
3176 }
85f455f7
ED		 3177}
3178
95ba8273 3179static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3180{
04d2cc77 3181 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3182
44c11430
GN		 3183 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3184 == HF_NMI_MASK)
3185 return; /* IRET will cause a vm exit */
3186
e0231715
JR		 3187 /*
3188 * Something prevents NMI from been injected. Single step over possible
3189 * problem (IRET or exception injection or interrupt shadow)
3190 */
6be7d306 3191 svm->nmi_singlestep = true;
44c11430
GN		 3192 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3193 update_db_intercept(vcpu);
c1150d8c
DL		 3194}
3195
cbc94022
IE		 3196static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3197{
3198 return 0;
3199}
3200
d9e368d6
AK		 3201static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3202{
3203 force_new_asid(vcpu);
3204}
3205
04d2cc77
AK		 3206static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3207{
3208}
3209
d7bf8221
JR		 3210static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3211{
3212 struct vcpu_svm *svm = to_svm(vcpu);
3213
88ab24ad
JR		 3214 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3215 return;
3216
d7bf8221
JR		 3217 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3218 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3219 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3220 }
3221}
3222
649d6864
JR		 3223static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3224{
3225 struct vcpu_svm *svm = to_svm(vcpu);
3226 u64 cr8;
3227
88ab24ad
JR		 3228 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3229 return;
3230
649d6864
JR		 3231 cr8 = kvm_get_cr8(vcpu);
3232 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3233 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3234}
3235
9222be18
GN		 3236static void svm_complete_interrupts(struct vcpu_svm *svm)
3237{
3238 u8 vector;
3239 int type;
3240 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3241 unsigned int3_injected = svm->int3_injected;
3242
3243 svm->int3_injected = 0;
9222be18 3244
3842d135 3245 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
44c11430 3246 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3247 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3248 }
44c11430 3249
9222be18
GN		 3250 svm->vcpu.arch.nmi_injected = false;
3251 kvm_clear_exception_queue(&svm->vcpu);
3252 kvm_clear_interrupt_queue(&svm->vcpu);
3253
3254 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3255 return;
3256
3842d135
AK		 3257 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3258
9222be18
GN		 3259 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3260 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3261
3262 switch (type) {
3263 case SVM_EXITINTINFO_TYPE_NMI:
3264 svm->vcpu.arch.nmi_injected = true;
3265 break;
3266 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3267 /*
3268 * In case of software exceptions, do not reinject the vector,
3269 * but re-execute the instruction instead. Rewind RIP first
3270 * if we emulated INT3 before.
3271 */
3272 if (kvm_exception_is_soft(vector)) {
3273 if (vector == BP_VECTOR && int3_injected &&
3274 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3275 kvm_rip_write(&svm->vcpu,
3276 kvm_rip_read(&svm->vcpu) -
3277 int3_injected);
9222be18 3278 break;
66b7138f 3279 }
9222be18
GN		 3280 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3281 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3282 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3283
3284 } else
ce7ddec4 3285 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3286 break;
3287 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3288 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3289 break;
3290 default:
3291 break;
3292 }
3293}
3294
b463a6f7
AK		 3295static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3296{
3297 struct vcpu_svm *svm = to_svm(vcpu);
3298 struct vmcb_control_area *control = &svm->vmcb->control;
3299
3300 control->exit_int_info = control->event_inj;
3301 control->exit_int_info_err = control->event_inj_err;
3302 control->event_inj = 0;
3303 svm_complete_interrupts(svm);
3304}
3305
80e31d4f
AK		 3306#ifdef CONFIG_X86_64
3307#define R "r"
3308#else
3309#define R "e"
3310#endif
3311
851ba692 3312static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3313{
a2fa3e9f 3314 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3315 u16 fs_selector;
3316 u16 gs_selector;
3317 u16 ldt_selector;
d9e368d6 3318
2041a06a
JR		 3319 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3320 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3321 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3322
cd3ff653
JR		 3323 /*
3324 * A vmexit emulation is required before the vcpu can be executed
3325 * again.
3326 */
3327 if (unlikely(svm->nested.exit_required))
3328 return;
3329
e756fc62 3330 pre_svm_run(svm);
6aa8b732 3331
649d6864
JR		 3332 sync_lapic_to_cr8(vcpu);
3333
6aa8b732 3334 save_host_msrs(vcpu);
9581d442
AK		 3335 savesegment(fs, fs_selector);
3336 savesegment(gs, gs_selector);
d6e88aec 3337 ldt_selector = kvm_read_ldt();
cda0ffdd 3338 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3339
04d2cc77
AK		 3340 clgi();
3341
3342 local_irq_enable();
36241b8c 3343
6aa8b732 3344 asm volatile (
80e31d4f
AK		 3345 "push %%"R"bp; \n\t"
3346 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3347 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3348 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3349 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3350 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3351 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3352#ifdef CONFIG_X86_64
fb3f0f51
RR		 3353 "mov %c[r8](%[svm]), %%r8 \n\t"
3354 "mov %c[r9](%[svm]), %%r9 \n\t"
3355 "mov %c[r10](%[svm]), %%r10 \n\t"
3356 "mov %c[r11](%[svm]), %%r11 \n\t"
3357 "mov %c[r12](%[svm]), %%r12 \n\t"
3358 "mov %c[r13](%[svm]), %%r13 \n\t"
3359 "mov %c[r14](%[svm]), %%r14 \n\t"
3360 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3361#endif
3362
6aa8b732 3363 /* Enter guest mode */
80e31d4f
AK		 3364 "push %%"R"ax \n\t"
3365 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3366 __ex(SVM_VMLOAD) "\n\t"
3367 __ex(SVM_VMRUN) "\n\t"
3368 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3369 "pop %%"R"ax \n\t"
6aa8b732
AK		 3370
3371 /* Save guest registers, load host registers */
80e31d4f
AK		 3372 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3373 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3374 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3375 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3376 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3377 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3378#ifdef CONFIG_X86_64
fb3f0f51
RR		 3379 "mov %%r8, %c[r8](%[svm]) \n\t"
3380 "mov %%r9, %c[r9](%[svm]) \n\t"
3381 "mov %%r10, %c[r10](%[svm]) \n\t"
3382 "mov %%r11, %c[r11](%[svm]) \n\t"
3383 "mov %%r12, %c[r12](%[svm]) \n\t"
3384 "mov %%r13, %c[r13](%[svm]) \n\t"
3385 "mov %%r14, %c[r14](%[svm]) \n\t"
3386 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3387#endif
80e31d4f 3388 "pop %%"R"bp"
6aa8b732 3389 :
fb3f0f51 3390 : [svm]"a"(svm),
6aa8b732 3391 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3392 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3393 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3394 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3395 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3396 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3397 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3398#ifdef CONFIG_X86_64
ad312c7c
ZX		 3399 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3400 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3401 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3402 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3403 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3404 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3405 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3406 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3407#endif
54a08c04 3408 : "cc", "memory"
80e31d4f 3409 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3410#ifdef CONFIG_X86_64
54a08c04
LV		 3411 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3412#endif
3413 );
6aa8b732 3414
6aa8b732 3415 load_host_msrs(vcpu);
0a77fe4c 3416 kvm_load_ldt(ldt_selector);
9581d442
AK		 3417 loadsegment(fs, fs_selector);
3418#ifdef CONFIG_X86_64
3419 load_gs_index(gs_selector);
3420 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3421#else
3422 loadsegment(gs, gs_selector);
3423#endif
6aa8b732
AK		 3424
3425 reload_tss(vcpu);
3426
56ba47dd
AK		 3427 local_irq_disable();
3428
3429 stgi();
3430
13c34e07
AK		 3431 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3432 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3433 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3434 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3435
d7bf8221
JR		 3436 sync_cr8_to_lapic(vcpu);
3437
a2fa3e9f 3438 svm->next_rip = 0;
9222be18 3439
631bc487
GN		 3440 /* if exit due to PF check for async PF */
3441 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3442 svm->apf_reason = kvm_read_and_reset_pf_reason();
3443
6de4f3ad
AK		 3444 if (npt_enabled) {
3445 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3446 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3447 }
fe5913e4
JR		 3448
3449 /*
3450 * We need to handle MC intercepts here before the vcpu has a chance to
3451 * change the physical cpu
3452 */
3453 if (unlikely(svm->vmcb->control.exit_code ==
3454 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3455 svm_handle_mce(svm);
6aa8b732
AK		 3456}
3457
80e31d4f
AK		 3458#undef R
3459
6aa8b732
AK		 3460static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3461{
a2fa3e9f
GH		 3462 struct vcpu_svm *svm = to_svm(vcpu);
3463
3464 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3465 force_new_asid(vcpu);
3466}
3467
1c97f0a0
JR		 3468static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3469{
3470 struct vcpu_svm *svm = to_svm(vcpu);
3471
3472 svm->vmcb->control.nested_cr3 = root;
3473
3474 /* Also sync guest cr3 here in case we live migrate */
3475 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3476
3477 force_new_asid(vcpu);
3478}
3479
6aa8b732
AK		 3480static int is_disabled(void)
3481{
6031a61c
JR		 3482 u64 vm_cr;
3483
3484 rdmsrl(MSR_VM_CR, vm_cr);
3485 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3486 return 1;
3487
6aa8b732
AK		 3488 return 0;
3489}
3490
102d8325
IM		 3491static void
3492svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3493{
3494 /*
3495 * Patch in the VMMCALL instruction:
3496 */
3497 hypercall[0] = 0x0f;
3498 hypercall[1] = 0x01;
3499 hypercall[2] = 0xd9;
102d8325
IM		 3500}
3501
002c7f7c
YS		 3502static void svm_check_processor_compat(void *rtn)
3503{
3504 *(int *)rtn = 0;
3505}
3506
774ead3a
AK		 3507static bool svm_cpu_has_accelerated_tpr(void)
3508{
3509 return false;
3510}
3511
4b12f0de 3512static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3513{
3514 return 0;
3515}
3516
0e851880
SY		 3517static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3518{
3519}
3520
d4330ef2
JR		 3521static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3522{
c2c63a49 3523 switch (func) {
24d1b15f
JR		 3524 case 0x00000001:
3525 /* Mask out xsave bit as long as it is not supported by SVM */
3526 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3527 break;
4c62a2dc
JR		 3528 case 0x80000001:
3529 if (nested)
3530 entry->ecx |= (1 << 2); /* Set SVM bit */
3531 break;
c2c63a49
JR		 3532 case 0x8000000A:
3533 entry->eax = 1; /* SVM revision 1 */
3534 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3535 ASID emulation to nested SVM */
3536 entry->ecx = 0; /* Reserved */
7a190667
JR		 3537 entry->edx = 0; /* Per default do not support any
3538 additional features */
3539
3540 /* Support next_rip if host supports it */
3541 if (svm_has(SVM_FEATURE_NRIP))
3542 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3543
3d4aeaad
JR		 3544 /* Support NPT for the guest if enabled */
3545 if (npt_enabled)
3546 entry->edx |= SVM_FEATURE_NPT;
3547
c2c63a49
JR		 3548 break;
3549 }
d4330ef2
JR		 3550}
3551
229456fc 3552static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3553 { SVM_EXIT_READ_CR0, "read_cr0" },
3554 { SVM_EXIT_READ_CR3, "read_cr3" },
3555 { SVM_EXIT_READ_CR4, "read_cr4" },
3556 { SVM_EXIT_READ_CR8, "read_cr8" },
3557 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3558 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3559 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3560 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3561 { SVM_EXIT_READ_DR0, "read_dr0" },
3562 { SVM_EXIT_READ_DR1, "read_dr1" },
3563 { SVM_EXIT_READ_DR2, "read_dr2" },
3564 { SVM_EXIT_READ_DR3, "read_dr3" },
3565 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3566 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3567 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3568 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3569 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3570 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3571 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3572 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3573 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3574 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3575 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3576 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3577 { SVM_EXIT_INTR, "interrupt" },
3578 { SVM_EXIT_NMI, "nmi" },
3579 { SVM_EXIT_SMI, "smi" },
3580 { SVM_EXIT_INIT, "init" },
3581 { SVM_EXIT_VINTR, "vintr" },
3582 { SVM_EXIT_CPUID, "cpuid" },
3583 { SVM_EXIT_INVD, "invd" },
3584 { SVM_EXIT_HLT, "hlt" },
3585 { SVM_EXIT_INVLPG, "invlpg" },
3586 { SVM_EXIT_INVLPGA, "invlpga" },
3587 { SVM_EXIT_IOIO, "io" },
3588 { SVM_EXIT_MSR, "msr" },
3589 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3590 { SVM_EXIT_SHUTDOWN, "shutdown" },
3591 { SVM_EXIT_VMRUN, "vmrun" },
3592 { SVM_EXIT_VMMCALL, "hypercall" },
3593 { SVM_EXIT_VMLOAD, "vmload" },
3594 { SVM_EXIT_VMSAVE, "vmsave" },
3595 { SVM_EXIT_STGI, "stgi" },
3596 { SVM_EXIT_CLGI, "clgi" },
3597 { SVM_EXIT_SKINIT, "skinit" },
3598 { SVM_EXIT_WBINVD, "wbinvd" },
3599 { SVM_EXIT_MONITOR, "monitor" },
3600 { SVM_EXIT_MWAIT, "mwait" },
3601 { SVM_EXIT_NPF, "npf" },
3602 { -1, NULL }
3603};
3604
17cc3935 3605static int svm_get_lpage_level(void)
344f414f 3606{
17cc3935 3607 return PT_PDPE_LEVEL;
344f414f
JR		 3608}
3609
4e47c7a6
SY		 3610static bool svm_rdtscp_supported(void)
3611{
3612 return false;
3613}
3614
f5f48ee1
SY		 3615static bool svm_has_wbinvd_exit(void)
3616{
3617 return true;
3618}
3619
02daab21
AK		 3620static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3621{
3622 struct vcpu_svm *svm = to_svm(vcpu);
3623
02daab21 3624 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3625 if (is_nested(svm))
3626 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3627 update_cr0_intercept(svm);
02daab21
AK		 3628}
3629
cbdd1bea 3630static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3631 .cpu_has_kvm_support = has_svm,
3632 .disabled_by_bios = is_disabled,
3633 .hardware_setup = svm_hardware_setup,
3634 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3635 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3636 .hardware_enable = svm_hardware_enable,
3637 .hardware_disable = svm_hardware_disable,
774ead3a 3638 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3639
3640 .vcpu_create = svm_create_vcpu,
3641 .vcpu_free = svm_free_vcpu,
04d2cc77 3642 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3643
04d2cc77 3644 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3645 .vcpu_load = svm_vcpu_load,
3646 .vcpu_put = svm_vcpu_put,
3647
3648 .set_guest_debug = svm_guest_debug,
3649 .get_msr = svm_get_msr,
3650 .set_msr = svm_set_msr,
3651 .get_segment_base = svm_get_segment_base,
3652 .get_segment = svm_get_segment,
3653 .set_segment = svm_set_segment,
2e4d2653 3654 .get_cpl = svm_get_cpl,
1747fb71 3655 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3656 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3657 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3658 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3659 .set_cr3 = svm_set_cr3,
3660 .set_cr4 = svm_set_cr4,
3661 .set_efer = svm_set_efer,
3662 .get_idt = svm_get_idt,
3663 .set_idt = svm_set_idt,
3664 .get_gdt = svm_get_gdt,
3665 .set_gdt = svm_set_gdt,
020df079 3666 .set_dr7 = svm_set_dr7,
6de4f3ad 3667 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3668 .get_rflags = svm_get_rflags,
3669 .set_rflags = svm_set_rflags,
6b52d186 3670 .fpu_activate = svm_fpu_activate,
02daab21 3671 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3672
6aa8b732 3673 .tlb_flush = svm_flush_tlb,
6aa8b732 3674
6aa8b732 3675 .run = svm_vcpu_run,
04d2cc77 3676 .handle_exit = handle_exit,
6aa8b732 3677 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3678 .set_interrupt_shadow = svm_set_interrupt_shadow,
3679 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3680 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3681 .set_irq = svm_set_irq,
95ba8273 3682 .set_nmi = svm_inject_nmi,
298101da 3683 .queue_exception = svm_queue_exception,
b463a6f7 3684 .cancel_injection = svm_cancel_injection,
78646121 3685 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3686 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3687 .get_nmi_mask = svm_get_nmi_mask,
3688 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3689 .enable_nmi_window = enable_nmi_window,
3690 .enable_irq_window = enable_irq_window,
3691 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3692
3693 .set_tss_addr = svm_set_tss_addr,
67253af5 3694 .get_tdp_level = get_npt_level,
4b12f0de 3695 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3696
3697 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3698 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3699
3700 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3701
3702 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3703
3704 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3705
3706 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3707
3708 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3709 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3710
3711 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3712};
3713
3714static int __init svm_init(void)
3715{
cb498ea2 3716 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3717 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3718}
3719
3720static void __exit svm_exit(void)
3721{
cb498ea2 3722 kvm_exit();
6aa8b732
AK		 3723}
3724
3725module_init(svm_init)
3726module_exit(svm_exit)
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