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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
44a95dae SS |
17 | |
18 | #define pr_fmt(fmt) "SVM: " fmt | |
19 | ||
edf88417 AK |
20 | #include <linux/kvm_host.h> |
21 | ||
85f455f7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
fe4c7b19 | 25 | #include "x86.h" |
66f7b72e | 26 | #include "cpuid.h" |
25462f7f | 27 | #include "pmu.h" |
e495606d | 28 | |
6aa8b732 | 29 | #include <linux/module.h> |
ae759544 | 30 | #include <linux/mod_devicetable.h> |
9d8f549d | 31 | #include <linux/kernel.h> |
6aa8b732 AK |
32 | #include <linux/vmalloc.h> |
33 | #include <linux/highmem.h> | |
e8edc6e0 | 34 | #include <linux/sched.h> |
af658dca | 35 | #include <linux/trace_events.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
5881f737 SS |
37 | #include <linux/amd-iommu.h> |
38 | #include <linux/hashtable.h> | |
c207aee4 | 39 | #include <linux/frame.h> |
6aa8b732 | 40 | |
8221c137 | 41 | #include <asm/apic.h> |
1018faa6 | 42 | #include <asm/perf_event.h> |
67ec6607 | 43 | #include <asm/tlbflush.h> |
e495606d | 44 | #include <asm/desc.h> |
facb0139 | 45 | #include <asm/debugreg.h> |
631bc487 | 46 | #include <asm/kvm_para.h> |
411b44ba | 47 | #include <asm/irq_remapping.h> |
6aa8b732 | 48 | |
63d1142f | 49 | #include <asm/virtext.h> |
229456fc | 50 | #include "trace.h" |
63d1142f | 51 | |
4ecac3fd AK |
52 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
53 | ||
6aa8b732 AK |
54 | MODULE_AUTHOR("Qumranet"); |
55 | MODULE_LICENSE("GPL"); | |
56 | ||
ae759544 JT |
57 | static const struct x86_cpu_id svm_cpu_id[] = { |
58 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
59 | {} | |
60 | }; | |
61 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
62 | ||
6aa8b732 AK |
63 | #define IOPM_ALLOC_ORDER 2 |
64 | #define MSRPM_ALLOC_ORDER 1 | |
65 | ||
6aa8b732 AK |
66 | #define SEG_TYPE_LDT 2 |
67 | #define SEG_TYPE_BUSY_TSS16 3 | |
68 | ||
6bc31bdc AP |
69 | #define SVM_FEATURE_NPT (1 << 0) |
70 | #define SVM_FEATURE_LBRV (1 << 1) | |
71 | #define SVM_FEATURE_SVML (1 << 2) | |
72 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
73 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
74 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
75 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
76 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 77 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 78 | |
340d3bc3 SS |
79 | #define SVM_AVIC_DOORBELL 0xc001011b |
80 | ||
410e4d57 JR |
81 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
82 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
83 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
84 | ||
24e09cbf JR |
85 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
86 | ||
fbc0db76 | 87 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
88 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
89 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 90 | |
5446a979 | 91 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) |
44a95dae SS |
92 | |
93 | /* | |
94 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
95 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
96 | */ | |
97 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
98 | ||
18f40c53 SS |
99 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 |
100 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
101 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
102 | ||
5ea11f2b SS |
103 | /* AVIC GATAG is encoded using VM and VCPU IDs */ |
104 | #define AVIC_VCPU_ID_BITS 8 | |
105 | #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1) | |
106 | ||
107 | #define AVIC_VM_ID_BITS 24 | |
108 | #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS) | |
109 | #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1) | |
110 | ||
111 | #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \ | |
112 | (y & AVIC_VCPU_ID_MASK)) | |
113 | #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK) | |
114 | #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) | |
115 | ||
67ec6607 JR |
116 | static bool erratum_383_found __read_mostly; |
117 | ||
6c8166a7 AK |
118 | static const u32 host_save_user_msrs[] = { |
119 | #ifdef CONFIG_X86_64 | |
120 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
121 | MSR_FS_BASE, | |
122 | #endif | |
123 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 124 | MSR_TSC_AUX, |
6c8166a7 AK |
125 | }; |
126 | ||
127 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
128 | ||
129 | struct kvm_vcpu; | |
130 | ||
e6aa9abd JR |
131 | struct nested_state { |
132 | struct vmcb *hsave; | |
133 | u64 hsave_msr; | |
4a810181 | 134 | u64 vm_cr_msr; |
e6aa9abd JR |
135 | u64 vmcb; |
136 | ||
137 | /* These are the merged vectors */ | |
138 | u32 *msrpm; | |
139 | ||
140 | /* gpa pointers to the real vectors */ | |
141 | u64 vmcb_msrpm; | |
ce2ac085 | 142 | u64 vmcb_iopm; |
aad42c64 | 143 | |
cd3ff653 JR |
144 | /* A VMEXIT is required but not yet emulated */ |
145 | bool exit_required; | |
146 | ||
aad42c64 | 147 | /* cache for intercepts of the guest */ |
4ee546b4 | 148 | u32 intercept_cr; |
3aed041a | 149 | u32 intercept_dr; |
aad42c64 JR |
150 | u32 intercept_exceptions; |
151 | u64 intercept; | |
152 | ||
5bd2edc3 JR |
153 | /* Nested Paging related state */ |
154 | u64 nested_cr3; | |
e6aa9abd JR |
155 | }; |
156 | ||
323c3d80 JR |
157 | #define MSRPM_OFFSETS 16 |
158 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
159 | ||
2b036c6b BO |
160 | /* |
161 | * Set osvw_len to higher value when updated Revision Guides | |
162 | * are published and we know what the new status bits are | |
163 | */ | |
164 | static uint64_t osvw_len = 4, osvw_status; | |
165 | ||
6c8166a7 AK |
166 | struct vcpu_svm { |
167 | struct kvm_vcpu vcpu; | |
168 | struct vmcb *vmcb; | |
169 | unsigned long vmcb_pa; | |
170 | struct svm_cpu_data *svm_data; | |
171 | uint64_t asid_generation; | |
172 | uint64_t sysenter_esp; | |
173 | uint64_t sysenter_eip; | |
46896c73 | 174 | uint64_t tsc_aux; |
6c8166a7 AK |
175 | |
176 | u64 next_rip; | |
177 | ||
178 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 179 | struct { |
dacccfdd AK |
180 | u16 fs; |
181 | u16 gs; | |
182 | u16 ldt; | |
afe9e66f AK |
183 | u64 gs_base; |
184 | } host; | |
6c8166a7 AK |
185 | |
186 | u32 *msrpm; | |
6c8166a7 | 187 | |
bd3d1ec3 AK |
188 | ulong nmi_iret_rip; |
189 | ||
e6aa9abd | 190 | struct nested_state nested; |
6be7d306 JK |
191 | |
192 | bool nmi_singlestep; | |
ab2f4d73 | 193 | u64 nmi_singlestep_guest_rflags; |
66b7138f JK |
194 | |
195 | unsigned int3_injected; | |
196 | unsigned long int3_rip; | |
fbc0db76 | 197 | |
6092d3d3 JR |
198 | /* cached guest cpuid flags for faster access */ |
199 | bool nrips_enabled : 1; | |
44a95dae | 200 | |
18f40c53 | 201 | u32 ldr_reg; |
44a95dae SS |
202 | struct page *avic_backing_page; |
203 | u64 *avic_physical_id_cache; | |
8221c137 | 204 | bool avic_is_running; |
411b44ba SS |
205 | |
206 | /* | |
207 | * Per-vcpu list of struct amd_svm_iommu_ir: | |
208 | * This is used mainly to store interrupt remapping information used | |
209 | * when update the vcpu affinity. This avoids the need to scan for | |
210 | * IRTE and try to match ga_tag in the IOMMU driver. | |
211 | */ | |
212 | struct list_head ir_list; | |
213 | spinlock_t ir_list_lock; | |
214 | }; | |
215 | ||
216 | /* | |
217 | * This is a wrapper of struct amd_iommu_ir_data. | |
218 | */ | |
219 | struct amd_svm_iommu_ir { | |
220 | struct list_head node; /* Used by SVM for per-vcpu ir_list */ | |
221 | void *data; /* Storing pointer to struct amd_ir_data */ | |
6c8166a7 AK |
222 | }; |
223 | ||
44a95dae SS |
224 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
225 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
226 | ||
227 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
228 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
229 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
230 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
231 | ||
fbc0db76 JR |
232 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
233 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
234 | ||
455716fa JR |
235 | #define MSR_INVALID 0xffffffffU |
236 | ||
09941fbb | 237 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
238 | u32 index; /* Index of the MSR */ |
239 | bool always; /* True if intercept is always on */ | |
240 | } direct_access_msrs[] = { | |
8c06585d | 241 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
242 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
243 | #ifdef CONFIG_X86_64 | |
244 | { .index = MSR_GS_BASE, .always = true }, | |
245 | { .index = MSR_FS_BASE, .always = true }, | |
246 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
247 | { .index = MSR_LSTAR, .always = true }, | |
248 | { .index = MSR_CSTAR, .always = true }, | |
249 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
250 | #endif | |
251 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
252 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
253 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
254 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
255 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
256 | }; |
257 | ||
709ddebf JR |
258 | /* enable NPT for AMD64 and X86 with PAE */ |
259 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
260 | static bool npt_enabled = true; | |
261 | #else | |
e0231715 | 262 | static bool npt_enabled; |
709ddebf | 263 | #endif |
6c7dac72 | 264 | |
e2358851 DB |
265 | /* allow nested paging (virtualized MMU) for all guests */ |
266 | static int npt = true; | |
6c7dac72 | 267 | module_param(npt, int, S_IRUGO); |
e3da3acd | 268 | |
e2358851 DB |
269 | /* allow nested virtualization in KVM/SVM */ |
270 | static int nested = true; | |
236de055 AG |
271 | module_param(nested, int, S_IRUGO); |
272 | ||
44a95dae SS |
273 | /* enable / disable AVIC */ |
274 | static int avic; | |
5b8abf1f | 275 | #ifdef CONFIG_X86_LOCAL_APIC |
44a95dae | 276 | module_param(avic, int, S_IRUGO); |
5b8abf1f | 277 | #endif |
44a95dae | 278 | |
89c8a498 JN |
279 | /* enable/disable Virtual VMLOAD VMSAVE */ |
280 | static int vls = true; | |
281 | module_param(vls, int, 0444); | |
282 | ||
640bd6e5 JN |
283 | /* enable/disable Virtual GIF */ |
284 | static int vgif = true; | |
285 | module_param(vgif, int, 0444); | |
5ea11f2b | 286 | |
79a8059d | 287 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
44874f84 | 288 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 289 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 290 | |
410e4d57 | 291 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 292 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 293 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
294 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
295 | bool has_error_code, u32 error_code); | |
296 | ||
8d28fec4 | 297 | enum { |
116a0a23 JR |
298 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
299 | pause filter count */ | |
f56838e4 | 300 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 301 | VMCB_ASID, /* ASID */ |
decdbf6a | 302 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 303 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 304 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 305 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 306 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 307 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 308 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 309 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
310 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
311 | * AVIC PHYSICAL_TABLE pointer, | |
312 | * AVIC LOGICAL_TABLE pointer | |
313 | */ | |
8d28fec4 RJ |
314 | VMCB_DIRTY_MAX, |
315 | }; | |
316 | ||
0574dec0 JR |
317 | /* TPR and CR2 are always written before VMRUN */ |
318 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 319 | |
44a95dae SS |
320 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
321 | ||
8d28fec4 RJ |
322 | static inline void mark_all_dirty(struct vmcb *vmcb) |
323 | { | |
324 | vmcb->control.clean = 0; | |
325 | } | |
326 | ||
327 | static inline void mark_all_clean(struct vmcb *vmcb) | |
328 | { | |
329 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
330 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
331 | } | |
332 | ||
333 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
334 | { | |
335 | vmcb->control.clean &= ~(1 << bit); | |
336 | } | |
337 | ||
a2fa3e9f GH |
338 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
339 | { | |
fb3f0f51 | 340 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
341 | } |
342 | ||
44a95dae SS |
343 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
344 | { | |
345 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
346 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
347 | } | |
348 | ||
340d3bc3 SS |
349 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
350 | { | |
351 | struct vcpu_svm *svm = to_svm(vcpu); | |
352 | u64 *entry = svm->avic_physical_id_cache; | |
353 | ||
354 | if (!entry) | |
355 | return false; | |
356 | ||
357 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
358 | } | |
359 | ||
384c6368 JR |
360 | static void recalc_intercepts(struct vcpu_svm *svm) |
361 | { | |
362 | struct vmcb_control_area *c, *h; | |
363 | struct nested_state *g; | |
364 | ||
116a0a23 JR |
365 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
366 | ||
384c6368 JR |
367 | if (!is_guest_mode(&svm->vcpu)) |
368 | return; | |
369 | ||
370 | c = &svm->vmcb->control; | |
371 | h = &svm->nested.hsave->control; | |
372 | g = &svm->nested; | |
373 | ||
4ee546b4 | 374 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 375 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
376 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
377 | c->intercept = h->intercept | g->intercept; | |
378 | } | |
379 | ||
4ee546b4 RJ |
380 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
381 | { | |
382 | if (is_guest_mode(&svm->vcpu)) | |
383 | return svm->nested.hsave; | |
384 | else | |
385 | return svm->vmcb; | |
386 | } | |
387 | ||
388 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
389 | { | |
390 | struct vmcb *vmcb = get_host_vmcb(svm); | |
391 | ||
392 | vmcb->control.intercept_cr |= (1U << bit); | |
393 | ||
394 | recalc_intercepts(svm); | |
395 | } | |
396 | ||
397 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
398 | { | |
399 | struct vmcb *vmcb = get_host_vmcb(svm); | |
400 | ||
401 | vmcb->control.intercept_cr &= ~(1U << bit); | |
402 | ||
403 | recalc_intercepts(svm); | |
404 | } | |
405 | ||
406 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
407 | { | |
408 | struct vmcb *vmcb = get_host_vmcb(svm); | |
409 | ||
410 | return vmcb->control.intercept_cr & (1U << bit); | |
411 | } | |
412 | ||
5315c716 | 413 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
414 | { |
415 | struct vmcb *vmcb = get_host_vmcb(svm); | |
416 | ||
5315c716 PB |
417 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
418 | | (1 << INTERCEPT_DR1_READ) | |
419 | | (1 << INTERCEPT_DR2_READ) | |
420 | | (1 << INTERCEPT_DR3_READ) | |
421 | | (1 << INTERCEPT_DR4_READ) | |
422 | | (1 << INTERCEPT_DR5_READ) | |
423 | | (1 << INTERCEPT_DR6_READ) | |
424 | | (1 << INTERCEPT_DR7_READ) | |
425 | | (1 << INTERCEPT_DR0_WRITE) | |
426 | | (1 << INTERCEPT_DR1_WRITE) | |
427 | | (1 << INTERCEPT_DR2_WRITE) | |
428 | | (1 << INTERCEPT_DR3_WRITE) | |
429 | | (1 << INTERCEPT_DR4_WRITE) | |
430 | | (1 << INTERCEPT_DR5_WRITE) | |
431 | | (1 << INTERCEPT_DR6_WRITE) | |
432 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
433 | |
434 | recalc_intercepts(svm); | |
435 | } | |
436 | ||
5315c716 | 437 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
438 | { |
439 | struct vmcb *vmcb = get_host_vmcb(svm); | |
440 | ||
5315c716 | 441 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
442 | |
443 | recalc_intercepts(svm); | |
444 | } | |
445 | ||
18c918c5 JR |
446 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
447 | { | |
448 | struct vmcb *vmcb = get_host_vmcb(svm); | |
449 | ||
450 | vmcb->control.intercept_exceptions |= (1U << bit); | |
451 | ||
452 | recalc_intercepts(svm); | |
453 | } | |
454 | ||
455 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
456 | { | |
457 | struct vmcb *vmcb = get_host_vmcb(svm); | |
458 | ||
459 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
460 | ||
461 | recalc_intercepts(svm); | |
462 | } | |
463 | ||
8a05a1b8 JR |
464 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
465 | { | |
466 | struct vmcb *vmcb = get_host_vmcb(svm); | |
467 | ||
468 | vmcb->control.intercept |= (1ULL << bit); | |
469 | ||
470 | recalc_intercepts(svm); | |
471 | } | |
472 | ||
473 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
474 | { | |
475 | struct vmcb *vmcb = get_host_vmcb(svm); | |
476 | ||
477 | vmcb->control.intercept &= ~(1ULL << bit); | |
478 | ||
479 | recalc_intercepts(svm); | |
480 | } | |
481 | ||
640bd6e5 JN |
482 | static inline bool vgif_enabled(struct vcpu_svm *svm) |
483 | { | |
484 | return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); | |
485 | } | |
486 | ||
2af9194d JR |
487 | static inline void enable_gif(struct vcpu_svm *svm) |
488 | { | |
640bd6e5 JN |
489 | if (vgif_enabled(svm)) |
490 | svm->vmcb->control.int_ctl |= V_GIF_MASK; | |
491 | else | |
492 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
2af9194d JR |
493 | } |
494 | ||
495 | static inline void disable_gif(struct vcpu_svm *svm) | |
496 | { | |
640bd6e5 JN |
497 | if (vgif_enabled(svm)) |
498 | svm->vmcb->control.int_ctl &= ~V_GIF_MASK; | |
499 | else | |
500 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
2af9194d JR |
501 | } |
502 | ||
503 | static inline bool gif_set(struct vcpu_svm *svm) | |
504 | { | |
640bd6e5 JN |
505 | if (vgif_enabled(svm)) |
506 | return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); | |
507 | else | |
508 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
2af9194d JR |
509 | } |
510 | ||
4866d5e3 | 511 | static unsigned long iopm_base; |
6aa8b732 AK |
512 | |
513 | struct kvm_ldttss_desc { | |
514 | u16 limit0; | |
515 | u16 base0; | |
e0231715 JR |
516 | unsigned base1:8, type:5, dpl:2, p:1; |
517 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
518 | u32 base3; |
519 | u32 zero1; | |
520 | } __attribute__((packed)); | |
521 | ||
522 | struct svm_cpu_data { | |
523 | int cpu; | |
524 | ||
5008fdf5 AK |
525 | u64 asid_generation; |
526 | u32 max_asid; | |
527 | u32 next_asid; | |
6aa8b732 AK |
528 | struct kvm_ldttss_desc *tss_desc; |
529 | ||
530 | struct page *save_area; | |
531 | }; | |
532 | ||
533 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
534 | ||
535 | struct svm_init_data { | |
536 | int cpu; | |
537 | int r; | |
538 | }; | |
539 | ||
09941fbb | 540 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 541 | |
9d8f549d | 542 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
543 | #define MSRS_RANGE_SIZE 2048 |
544 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
545 | ||
455716fa JR |
546 | static u32 svm_msrpm_offset(u32 msr) |
547 | { | |
548 | u32 offset; | |
549 | int i; | |
550 | ||
551 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
552 | if (msr < msrpm_ranges[i] || | |
553 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
554 | continue; | |
555 | ||
556 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
557 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
558 | ||
559 | /* Now we have the u8 offset - but need the u32 offset */ | |
560 | return offset / 4; | |
561 | } | |
562 | ||
563 | /* MSR not in any range */ | |
564 | return MSR_INVALID; | |
565 | } | |
566 | ||
6aa8b732 AK |
567 | #define MAX_INST_SIZE 15 |
568 | ||
6aa8b732 AK |
569 | static inline void clgi(void) |
570 | { | |
4ecac3fd | 571 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
572 | } |
573 | ||
574 | static inline void stgi(void) | |
575 | { | |
4ecac3fd | 576 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
577 | } |
578 | ||
579 | static inline void invlpga(unsigned long addr, u32 asid) | |
580 | { | |
e0231715 | 581 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
582 | } |
583 | ||
855feb67 | 584 | static int get_npt_level(struct kvm_vcpu *vcpu) |
4b16184c JR |
585 | { |
586 | #ifdef CONFIG_X86_64 | |
2a7266a8 | 587 | return PT64_ROOT_4LEVEL; |
4b16184c JR |
588 | #else |
589 | return PT32E_ROOT_LEVEL; | |
590 | #endif | |
591 | } | |
592 | ||
6aa8b732 AK |
593 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
594 | { | |
6dc696d4 | 595 | vcpu->arch.efer = efer; |
709ddebf | 596 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 597 | efer &= ~EFER_LME; |
6aa8b732 | 598 | |
9962d032 | 599 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 600 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
601 | } |
602 | ||
6aa8b732 AK |
603 | static int is_external_interrupt(u32 info) |
604 | { | |
605 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
606 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
607 | } | |
608 | ||
37ccdcbe | 609 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
610 | { |
611 | struct vcpu_svm *svm = to_svm(vcpu); | |
612 | u32 ret = 0; | |
613 | ||
614 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
615 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
616 | return ret; | |
2809f5d2 GC |
617 | } |
618 | ||
619 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
620 | { | |
621 | struct vcpu_svm *svm = to_svm(vcpu); | |
622 | ||
623 | if (mask == 0) | |
624 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
625 | else | |
626 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
627 | ||
628 | } | |
629 | ||
6aa8b732 AK |
630 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
631 | { | |
a2fa3e9f GH |
632 | struct vcpu_svm *svm = to_svm(vcpu); |
633 | ||
f104765b | 634 | if (svm->vmcb->control.next_rip != 0) { |
d2922422 | 635 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 636 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 637 | } |
6bc31bdc | 638 | |
a2fa3e9f | 639 | if (!svm->next_rip) { |
51d8b661 | 640 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
641 | EMULATE_DONE) |
642 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
643 | return; |
644 | } | |
5fdbf976 MT |
645 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
646 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
647 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 648 | |
5fdbf976 | 649 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 650 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
651 | } |
652 | ||
cfcd20e5 | 653 | static void svm_queue_exception(struct kvm_vcpu *vcpu) |
116a4752 JK |
654 | { |
655 | struct vcpu_svm *svm = to_svm(vcpu); | |
cfcd20e5 WL |
656 | unsigned nr = vcpu->arch.exception.nr; |
657 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
664f8e26 | 658 | bool reinject = vcpu->arch.exception.injected; |
cfcd20e5 | 659 | u32 error_code = vcpu->arch.exception.error_code; |
116a4752 | 660 | |
e0231715 JR |
661 | /* |
662 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
663 | * handle the exception | |
664 | */ | |
ce7ddec4 JR |
665 | if (!reinject && |
666 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
667 | return; |
668 | ||
2a6b20b8 | 669 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
670 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
671 | ||
672 | /* | |
673 | * For guest debugging where we have to reinject #BP if some | |
674 | * INT3 is guest-owned: | |
675 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
676 | * raises a fault that is not intercepted. Still better than | |
677 | * failing in all cases. | |
678 | */ | |
679 | skip_emulated_instruction(&svm->vcpu); | |
680 | rip = kvm_rip_read(&svm->vcpu); | |
681 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
682 | svm->int3_injected = rip - old_rip; | |
683 | } | |
684 | ||
116a4752 JK |
685 | svm->vmcb->control.event_inj = nr |
686 | | SVM_EVTINJ_VALID | |
687 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
688 | | SVM_EVTINJ_TYPE_EXEPT; | |
689 | svm->vmcb->control.event_inj_err = error_code; | |
690 | } | |
691 | ||
67ec6607 JR |
692 | static void svm_init_erratum_383(void) |
693 | { | |
694 | u32 low, high; | |
695 | int err; | |
696 | u64 val; | |
697 | ||
e6ee94d5 | 698 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
699 | return; |
700 | ||
701 | /* Use _safe variants to not break nested virtualization */ | |
702 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
703 | if (err) | |
704 | return; | |
705 | ||
706 | val |= (1ULL << 47); | |
707 | ||
708 | low = lower_32_bits(val); | |
709 | high = upper_32_bits(val); | |
710 | ||
711 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
712 | ||
713 | erratum_383_found = true; | |
714 | } | |
715 | ||
2b036c6b BO |
716 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
717 | { | |
718 | /* | |
719 | * Guests should see errata 400 and 415 as fixed (assuming that | |
720 | * HLT and IO instructions are intercepted). | |
721 | */ | |
722 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
723 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
724 | ||
725 | /* | |
726 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
727 | * all osvw.status bits inside that length, including bit 0 (which is | |
728 | * reserved for erratum 298), are valid. However, if host processor's | |
729 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
730 | * be conservative here and therefore we tell the guest that erratum 298 | |
731 | * is present (because we really don't know). | |
732 | */ | |
733 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
734 | vcpu->arch.osvw.status |= 1; | |
735 | } | |
736 | ||
6aa8b732 AK |
737 | static int has_svm(void) |
738 | { | |
63d1142f | 739 | const char *msg; |
6aa8b732 | 740 | |
63d1142f | 741 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 742 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
743 | return 0; |
744 | } | |
745 | ||
6aa8b732 AK |
746 | return 1; |
747 | } | |
748 | ||
13a34e06 | 749 | static void svm_hardware_disable(void) |
6aa8b732 | 750 | { |
fbc0db76 JR |
751 | /* Make sure we clean up behind us */ |
752 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
753 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
754 | ||
2c8dceeb | 755 | cpu_svm_disable(); |
1018faa6 JR |
756 | |
757 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
758 | } |
759 | ||
13a34e06 | 760 | static int svm_hardware_enable(void) |
6aa8b732 AK |
761 | { |
762 | ||
0fe1e009 | 763 | struct svm_cpu_data *sd; |
6aa8b732 | 764 | uint64_t efer; |
6aa8b732 AK |
765 | struct desc_struct *gdt; |
766 | int me = raw_smp_processor_id(); | |
767 | ||
10474ae8 AG |
768 | rdmsrl(MSR_EFER, efer); |
769 | if (efer & EFER_SVME) | |
770 | return -EBUSY; | |
771 | ||
6aa8b732 | 772 | if (!has_svm()) { |
1f5b77f5 | 773 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 774 | return -EINVAL; |
6aa8b732 | 775 | } |
0fe1e009 | 776 | sd = per_cpu(svm_data, me); |
0fe1e009 | 777 | if (!sd) { |
1f5b77f5 | 778 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 779 | return -EINVAL; |
6aa8b732 AK |
780 | } |
781 | ||
0fe1e009 TH |
782 | sd->asid_generation = 1; |
783 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
784 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 785 | |
45fc8757 | 786 | gdt = get_current_gdt_rw(); |
0fe1e009 | 787 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 788 | |
9962d032 | 789 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 790 | |
d0316554 | 791 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 792 | |
fbc0db76 JR |
793 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
794 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 795 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
796 | } |
797 | ||
2b036c6b BO |
798 | |
799 | /* | |
800 | * Get OSVW bits. | |
801 | * | |
802 | * Note that it is possible to have a system with mixed processor | |
803 | * revisions and therefore different OSVW bits. If bits are not the same | |
804 | * on different processors then choose the worst case (i.e. if erratum | |
805 | * is present on one processor and not on another then assume that the | |
806 | * erratum is present everywhere). | |
807 | */ | |
808 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
809 | uint64_t len, status = 0; | |
810 | int err; | |
811 | ||
812 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
813 | if (!err) | |
814 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
815 | &err); | |
816 | ||
817 | if (err) | |
818 | osvw_status = osvw_len = 0; | |
819 | else { | |
820 | if (len < osvw_len) | |
821 | osvw_len = len; | |
822 | osvw_status |= status; | |
823 | osvw_status &= (1ULL << osvw_len) - 1; | |
824 | } | |
825 | } else | |
826 | osvw_status = osvw_len = 0; | |
827 | ||
67ec6607 JR |
828 | svm_init_erratum_383(); |
829 | ||
1018faa6 JR |
830 | amd_pmu_enable_virt(); |
831 | ||
10474ae8 | 832 | return 0; |
6aa8b732 AK |
833 | } |
834 | ||
0da1db75 JR |
835 | static void svm_cpu_uninit(int cpu) |
836 | { | |
0fe1e009 | 837 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 838 | |
0fe1e009 | 839 | if (!sd) |
0da1db75 JR |
840 | return; |
841 | ||
842 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
843 | __free_page(sd->save_area); |
844 | kfree(sd); | |
0da1db75 JR |
845 | } |
846 | ||
6aa8b732 AK |
847 | static int svm_cpu_init(int cpu) |
848 | { | |
0fe1e009 | 849 | struct svm_cpu_data *sd; |
6aa8b732 AK |
850 | int r; |
851 | ||
0fe1e009 TH |
852 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
853 | if (!sd) | |
6aa8b732 | 854 | return -ENOMEM; |
0fe1e009 TH |
855 | sd->cpu = cpu; |
856 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 857 | r = -ENOMEM; |
0fe1e009 | 858 | if (!sd->save_area) |
6aa8b732 AK |
859 | goto err_1; |
860 | ||
0fe1e009 | 861 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
862 | |
863 | return 0; | |
864 | ||
865 | err_1: | |
0fe1e009 | 866 | kfree(sd); |
6aa8b732 AK |
867 | return r; |
868 | ||
869 | } | |
870 | ||
ac72a9b7 JR |
871 | static bool valid_msr_intercept(u32 index) |
872 | { | |
873 | int i; | |
874 | ||
875 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
876 | if (direct_access_msrs[i].index == index) | |
877 | return true; | |
878 | ||
879 | return false; | |
880 | } | |
881 | ||
bfc733a7 RR |
882 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
883 | int read, int write) | |
6aa8b732 | 884 | { |
455716fa JR |
885 | u8 bit_read, bit_write; |
886 | unsigned long tmp; | |
887 | u32 offset; | |
6aa8b732 | 888 | |
ac72a9b7 JR |
889 | /* |
890 | * If this warning triggers extend the direct_access_msrs list at the | |
891 | * beginning of the file | |
892 | */ | |
893 | WARN_ON(!valid_msr_intercept(msr)); | |
894 | ||
455716fa JR |
895 | offset = svm_msrpm_offset(msr); |
896 | bit_read = 2 * (msr & 0x0f); | |
897 | bit_write = 2 * (msr & 0x0f) + 1; | |
898 | tmp = msrpm[offset]; | |
899 | ||
900 | BUG_ON(offset == MSR_INVALID); | |
901 | ||
902 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
903 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
904 | ||
905 | msrpm[offset] = tmp; | |
6aa8b732 AK |
906 | } |
907 | ||
f65c229c | 908 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
909 | { |
910 | int i; | |
911 | ||
f65c229c JR |
912 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
913 | ||
ac72a9b7 JR |
914 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
915 | if (!direct_access_msrs[i].always) | |
916 | continue; | |
917 | ||
918 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
919 | } | |
f65c229c JR |
920 | } |
921 | ||
323c3d80 JR |
922 | static void add_msr_offset(u32 offset) |
923 | { | |
924 | int i; | |
925 | ||
926 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
927 | ||
928 | /* Offset already in list? */ | |
929 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 930 | return; |
323c3d80 JR |
931 | |
932 | /* Slot used by another offset? */ | |
933 | if (msrpm_offsets[i] != MSR_INVALID) | |
934 | continue; | |
935 | ||
936 | /* Add offset to list */ | |
937 | msrpm_offsets[i] = offset; | |
938 | ||
939 | return; | |
6aa8b732 | 940 | } |
323c3d80 JR |
941 | |
942 | /* | |
943 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
944 | * increase MSRPM_OFFSETS in this case. | |
945 | */ | |
bfc733a7 | 946 | BUG(); |
6aa8b732 AK |
947 | } |
948 | ||
323c3d80 | 949 | static void init_msrpm_offsets(void) |
f65c229c | 950 | { |
323c3d80 | 951 | int i; |
f65c229c | 952 | |
323c3d80 JR |
953 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
954 | ||
955 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
956 | u32 offset; | |
957 | ||
958 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
959 | BUG_ON(offset == MSR_INVALID); | |
960 | ||
961 | add_msr_offset(offset); | |
962 | } | |
f65c229c JR |
963 | } |
964 | ||
24e09cbf JR |
965 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
966 | { | |
967 | u32 *msrpm = svm->msrpm; | |
968 | ||
0dc92119 | 969 | svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
970 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); |
971 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
972 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
973 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
974 | } | |
975 | ||
976 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
977 | { | |
978 | u32 *msrpm = svm->msrpm; | |
979 | ||
0dc92119 | 980 | svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
981 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); |
982 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
983 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
984 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
985 | } | |
986 | ||
4aebd0e9 LP |
987 | static void disable_nmi_singlestep(struct vcpu_svm *svm) |
988 | { | |
989 | svm->nmi_singlestep = false; | |
640bd6e5 | 990 | |
ab2f4d73 LP |
991 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) { |
992 | /* Clear our flags if they were not set by the guest */ | |
993 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
994 | svm->vmcb->save.rflags &= ~X86_EFLAGS_TF; | |
995 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
996 | svm->vmcb->save.rflags &= ~X86_EFLAGS_RF; | |
997 | } | |
4aebd0e9 LP |
998 | } |
999 | ||
5881f737 SS |
1000 | /* Note: |
1001 | * This hash table is used to map VM_ID to a struct kvm_arch, | |
1002 | * when handling AMD IOMMU GALOG notification to schedule in | |
1003 | * a particular vCPU. | |
1004 | */ | |
1005 | #define SVM_VM_DATA_HASH_BITS 8 | |
681bcea8 | 1006 | static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); |
3f0d4db7 DV |
1007 | static u32 next_vm_id = 0; |
1008 | static bool next_vm_id_wrapped = 0; | |
681bcea8 | 1009 | static DEFINE_SPINLOCK(svm_vm_data_hash_lock); |
5881f737 SS |
1010 | |
1011 | /* Note: | |
1012 | * This function is called from IOMMU driver to notify | |
1013 | * SVM to schedule in a particular vCPU of a particular VM. | |
1014 | */ | |
1015 | static int avic_ga_log_notifier(u32 ga_tag) | |
1016 | { | |
1017 | unsigned long flags; | |
1018 | struct kvm_arch *ka = NULL; | |
1019 | struct kvm_vcpu *vcpu = NULL; | |
1020 | u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag); | |
1021 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag); | |
1022 | ||
1023 | pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id); | |
1024 | ||
1025 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1026 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1027 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1028 | struct kvm_arch *vm_data = &kvm->arch; | |
1029 | ||
1030 | if (vm_data->avic_vm_id != vm_id) | |
1031 | continue; | |
1032 | vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
1033 | break; | |
1034 | } | |
1035 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1036 | ||
5881f737 SS |
1037 | /* Note: |
1038 | * At this point, the IOMMU should have already set the pending | |
1039 | * bit in the vAPIC backing page. So, we just need to schedule | |
1040 | * in the vcpu. | |
1041 | */ | |
1cf53587 | 1042 | if (vcpu) |
5881f737 SS |
1043 | kvm_vcpu_wake_up(vcpu); |
1044 | ||
1045 | return 0; | |
1046 | } | |
1047 | ||
6aa8b732 AK |
1048 | static __init int svm_hardware_setup(void) |
1049 | { | |
1050 | int cpu; | |
1051 | struct page *iopm_pages; | |
f65c229c | 1052 | void *iopm_va; |
6aa8b732 AK |
1053 | int r; |
1054 | ||
6aa8b732 AK |
1055 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
1056 | ||
1057 | if (!iopm_pages) | |
1058 | return -ENOMEM; | |
c8681339 AL |
1059 | |
1060 | iopm_va = page_address(iopm_pages); | |
1061 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
1062 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
1063 | ||
323c3d80 JR |
1064 | init_msrpm_offsets(); |
1065 | ||
50a37eb4 JR |
1066 | if (boot_cpu_has(X86_FEATURE_NX)) |
1067 | kvm_enable_efer_bits(EFER_NX); | |
1068 | ||
1b2fd70c AG |
1069 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
1070 | kvm_enable_efer_bits(EFER_FFXSR); | |
1071 | ||
92a1f12d | 1072 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 1073 | kvm_has_tsc_control = true; |
bc9b961b HZ |
1074 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
1075 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
1076 | } |
1077 | ||
236de055 AG |
1078 | if (nested) { |
1079 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 1080 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
1081 | } |
1082 | ||
3230bb47 | 1083 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1084 | r = svm_cpu_init(cpu); |
1085 | if (r) | |
f65c229c | 1086 | goto err; |
6aa8b732 | 1087 | } |
33bd6a0b | 1088 | |
2a6b20b8 | 1089 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
1090 | npt_enabled = false; |
1091 | ||
6c7dac72 JR |
1092 | if (npt_enabled && !npt) { |
1093 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
1094 | npt_enabled = false; | |
1095 | } | |
1096 | ||
18552672 | 1097 | if (npt_enabled) { |
e3da3acd | 1098 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 1099 | kvm_enable_tdp(); |
5f4cb662 JR |
1100 | } else |
1101 | kvm_disable_tdp(); | |
e3da3acd | 1102 | |
5b8abf1f SS |
1103 | if (avic) { |
1104 | if (!npt_enabled || | |
1105 | !boot_cpu_has(X86_FEATURE_AVIC) || | |
5881f737 | 1106 | !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { |
5b8abf1f | 1107 | avic = false; |
5881f737 | 1108 | } else { |
5b8abf1f | 1109 | pr_info("AVIC enabled\n"); |
5881f737 | 1110 | |
5881f737 SS |
1111 | amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); |
1112 | } | |
5b8abf1f | 1113 | } |
44a95dae | 1114 | |
89c8a498 JN |
1115 | if (vls) { |
1116 | if (!npt_enabled || | |
5442c269 | 1117 | !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) || |
89c8a498 JN |
1118 | !IS_ENABLED(CONFIG_X86_64)) { |
1119 | vls = false; | |
1120 | } else { | |
1121 | pr_info("Virtual VMLOAD VMSAVE supported\n"); | |
1122 | } | |
1123 | } | |
1124 | ||
640bd6e5 JN |
1125 | if (vgif) { |
1126 | if (!boot_cpu_has(X86_FEATURE_VGIF)) | |
1127 | vgif = false; | |
1128 | else | |
1129 | pr_info("Virtual GIF supported\n"); | |
1130 | } | |
1131 | ||
6aa8b732 AK |
1132 | return 0; |
1133 | ||
f65c229c | 1134 | err: |
6aa8b732 AK |
1135 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
1136 | iopm_base = 0; | |
1137 | return r; | |
1138 | } | |
1139 | ||
1140 | static __exit void svm_hardware_unsetup(void) | |
1141 | { | |
0da1db75 JR |
1142 | int cpu; |
1143 | ||
3230bb47 | 1144 | for_each_possible_cpu(cpu) |
0da1db75 JR |
1145 | svm_cpu_uninit(cpu); |
1146 | ||
6aa8b732 | 1147 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 1148 | iopm_base = 0; |
6aa8b732 AK |
1149 | } |
1150 | ||
1151 | static void init_seg(struct vmcb_seg *seg) | |
1152 | { | |
1153 | seg->selector = 0; | |
1154 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1155 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1156 | seg->limit = 0xffff; |
1157 | seg->base = 0; | |
1158 | } | |
1159 | ||
1160 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1161 | { | |
1162 | seg->selector = 0; | |
1163 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1164 | seg->limit = 0xffff; | |
1165 | seg->base = 0; | |
1166 | } | |
1167 | ||
f4e1b3c8 ZA |
1168 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1169 | { | |
1170 | struct vcpu_svm *svm = to_svm(vcpu); | |
1171 | u64 g_tsc_offset = 0; | |
1172 | ||
2030753d | 1173 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1174 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1175 | svm->nested.hsave->control.tsc_offset; | |
1176 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
1177 | } else |
1178 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1179 | svm->vmcb->control.tsc_offset, | |
1180 | offset); | |
f4e1b3c8 ZA |
1181 | |
1182 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1183 | |
1184 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1185 | } |
1186 | ||
44a95dae SS |
1187 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1188 | { | |
1189 | struct vmcb *vmcb = svm->vmcb; | |
1190 | struct kvm_arch *vm_data = &svm->vcpu.kvm->arch; | |
d0ec49d4 TL |
1191 | phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page)); |
1192 | phys_addr_t lpa = __sme_set(page_to_phys(vm_data->avic_logical_id_table_page)); | |
1193 | phys_addr_t ppa = __sme_set(page_to_phys(vm_data->avic_physical_id_table_page)); | |
44a95dae SS |
1194 | |
1195 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1196 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1197 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1198 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
1199 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
44a95dae SS |
1200 | } |
1201 | ||
5690891b | 1202 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1203 | { |
e6101a96 JR |
1204 | struct vmcb_control_area *control = &svm->vmcb->control; |
1205 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1206 | |
4ee546b4 | 1207 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1208 | |
4ee546b4 RJ |
1209 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1210 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1211 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1212 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1213 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1214 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
3bbf3565 SS |
1215 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
1216 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1217 | |
5315c716 | 1218 | set_dr_intercepts(svm); |
6aa8b732 | 1219 | |
18c918c5 JR |
1220 | set_exception_intercept(svm, PF_VECTOR); |
1221 | set_exception_intercept(svm, UD_VECTOR); | |
1222 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1223 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1224 | set_exception_intercept(svm, DB_VECTOR); |
6aa8b732 | 1225 | |
8a05a1b8 JR |
1226 | set_intercept(svm, INTERCEPT_INTR); |
1227 | set_intercept(svm, INTERCEPT_NMI); | |
1228 | set_intercept(svm, INTERCEPT_SMI); | |
1229 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1230 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1231 | set_intercept(svm, INTERCEPT_CPUID); |
1232 | set_intercept(svm, INTERCEPT_INVD); | |
1233 | set_intercept(svm, INTERCEPT_HLT); | |
1234 | set_intercept(svm, INTERCEPT_INVLPG); | |
1235 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1236 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1237 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1238 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1239 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1240 | set_intercept(svm, INTERCEPT_VMRUN); | |
1241 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1242 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1243 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1244 | set_intercept(svm, INTERCEPT_STGI); | |
1245 | set_intercept(svm, INTERCEPT_CLGI); | |
1246 | set_intercept(svm, INTERCEPT_SKINIT); | |
1247 | set_intercept(svm, INTERCEPT_WBINVD); | |
81dd35d4 | 1248 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 | 1249 | |
668fffa3 MT |
1250 | if (!kvm_mwait_in_guest()) { |
1251 | set_intercept(svm, INTERCEPT_MONITOR); | |
1252 | set_intercept(svm, INTERCEPT_MWAIT); | |
1253 | } | |
1254 | ||
d0ec49d4 TL |
1255 | control->iopm_base_pa = __sme_set(iopm_base); |
1256 | control->msrpm_base_pa = __sme_set(__pa(svm->msrpm)); | |
6aa8b732 AK |
1257 | control->int_ctl = V_INTR_MASKING_MASK; |
1258 | ||
1259 | init_seg(&save->es); | |
1260 | init_seg(&save->ss); | |
1261 | init_seg(&save->ds); | |
1262 | init_seg(&save->fs); | |
1263 | init_seg(&save->gs); | |
1264 | ||
1265 | save->cs.selector = 0xf000; | |
04b66839 | 1266 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1267 | /* Executable/Readable Code Segment */ |
1268 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1269 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1270 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1271 | |
1272 | save->gdtr.limit = 0xffff; | |
1273 | save->idtr.limit = 0xffff; | |
1274 | ||
1275 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1276 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1277 | ||
5690891b | 1278 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1279 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1280 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1281 | save->rip = 0x0000fff0; |
5fdbf976 | 1282 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1283 | |
e0231715 | 1284 | /* |
18fa000a | 1285 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1286 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1287 | */ |
79a8059d | 1288 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1289 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1290 | |
66aee91a | 1291 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1292 | /* rdx = ?? */ |
709ddebf JR |
1293 | |
1294 | if (npt_enabled) { | |
1295 | /* Setup VMCB for Nested Paging */ | |
1296 | control->nested_ctl = 1; | |
8a05a1b8 | 1297 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1298 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1299 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1300 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1301 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1302 | save->cr3 = 0; |
1303 | save->cr4 = 0; | |
1304 | } | |
f40f6a45 | 1305 | svm->asid_generation = 0; |
1371d904 | 1306 | |
e6aa9abd | 1307 | svm->nested.vmcb = 0; |
2af9194d JR |
1308 | svm->vcpu.arch.hflags = 0; |
1309 | ||
2a6b20b8 | 1310 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1311 | control->pause_filter_count = 3000; |
8a05a1b8 | 1312 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1313 | } |
1314 | ||
67034bb9 | 1315 | if (kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
1316 | avic_init_vmcb(svm); |
1317 | ||
89c8a498 JN |
1318 | /* |
1319 | * If hardware supports Virtual VMLOAD VMSAVE then enable it | |
1320 | * in VMCB and clear intercepts to avoid #VMEXIT. | |
1321 | */ | |
1322 | if (vls) { | |
1323 | clr_intercept(svm, INTERCEPT_VMLOAD); | |
1324 | clr_intercept(svm, INTERCEPT_VMSAVE); | |
1325 | svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; | |
1326 | } | |
1327 | ||
640bd6e5 JN |
1328 | if (vgif) { |
1329 | clr_intercept(svm, INTERCEPT_STGI); | |
1330 | clr_intercept(svm, INTERCEPT_CLGI); | |
1331 | svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK; | |
1332 | } | |
1333 | ||
8d28fec4 RJ |
1334 | mark_all_dirty(svm->vmcb); |
1335 | ||
2af9194d | 1336 | enable_gif(svm); |
44a95dae SS |
1337 | |
1338 | } | |
1339 | ||
d3e7dec0 DC |
1340 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, |
1341 | unsigned int index) | |
44a95dae SS |
1342 | { |
1343 | u64 *avic_physical_id_table; | |
1344 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
1345 | ||
1346 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1347 | return NULL; | |
1348 | ||
1349 | avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page); | |
1350 | ||
1351 | return &avic_physical_id_table[index]; | |
1352 | } | |
1353 | ||
1354 | /** | |
1355 | * Note: | |
1356 | * AVIC hardware walks the nested page table to check permissions, | |
1357 | * but does not use the SPA address specified in the leaf page | |
1358 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1359 | * field of the VMCB. Therefore, we set up the | |
1360 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1361 | */ | |
1362 | static int avic_init_access_page(struct kvm_vcpu *vcpu) | |
1363 | { | |
1364 | struct kvm *kvm = vcpu->kvm; | |
1365 | int ret; | |
1366 | ||
1367 | if (kvm->arch.apic_access_page_done) | |
1368 | return 0; | |
1369 | ||
1370 | ret = x86_set_memory_region(kvm, | |
1371 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1372 | APIC_DEFAULT_PHYS_BASE, | |
1373 | PAGE_SIZE); | |
1374 | if (ret) | |
1375 | return ret; | |
1376 | ||
1377 | kvm->arch.apic_access_page_done = true; | |
1378 | return 0; | |
1379 | } | |
1380 | ||
1381 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1382 | { | |
1383 | int ret; | |
1384 | u64 *entry, new_entry; | |
1385 | int id = vcpu->vcpu_id; | |
1386 | struct vcpu_svm *svm = to_svm(vcpu); | |
1387 | ||
1388 | ret = avic_init_access_page(vcpu); | |
1389 | if (ret) | |
1390 | return ret; | |
1391 | ||
1392 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1393 | return -EINVAL; | |
1394 | ||
1395 | if (!svm->vcpu.arch.apic->regs) | |
1396 | return -EINVAL; | |
1397 | ||
1398 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); | |
1399 | ||
1400 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1401 | entry = avic_get_physical_id_entry(vcpu, id); | |
1402 | if (!entry) | |
1403 | return -EINVAL; | |
1404 | ||
1405 | new_entry = READ_ONCE(*entry); | |
d0ec49d4 TL |
1406 | new_entry = __sme_set((page_to_phys(svm->avic_backing_page) & |
1407 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1408 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); | |
44a95dae SS |
1409 | WRITE_ONCE(*entry, new_entry); |
1410 | ||
1411 | svm->avic_physical_id_cache = entry; | |
1412 | ||
1413 | return 0; | |
1414 | } | |
1415 | ||
1416 | static void avic_vm_destroy(struct kvm *kvm) | |
1417 | { | |
5881f737 | 1418 | unsigned long flags; |
44a95dae SS |
1419 | struct kvm_arch *vm_data = &kvm->arch; |
1420 | ||
3863dff0 DV |
1421 | if (!avic) |
1422 | return; | |
1423 | ||
44a95dae SS |
1424 | if (vm_data->avic_logical_id_table_page) |
1425 | __free_page(vm_data->avic_logical_id_table_page); | |
1426 | if (vm_data->avic_physical_id_table_page) | |
1427 | __free_page(vm_data->avic_physical_id_table_page); | |
5881f737 SS |
1428 | |
1429 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1430 | hash_del(&vm_data->hnode); | |
1431 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
44a95dae SS |
1432 | } |
1433 | ||
1434 | static int avic_vm_init(struct kvm *kvm) | |
1435 | { | |
5881f737 | 1436 | unsigned long flags; |
3f0d4db7 | 1437 | int err = -ENOMEM; |
44a95dae SS |
1438 | struct kvm_arch *vm_data = &kvm->arch; |
1439 | struct page *p_page; | |
1440 | struct page *l_page; | |
3f0d4db7 DV |
1441 | struct kvm_arch *ka; |
1442 | u32 vm_id; | |
44a95dae SS |
1443 | |
1444 | if (!avic) | |
1445 | return 0; | |
1446 | ||
1447 | /* Allocating physical APIC ID table (4KB) */ | |
1448 | p_page = alloc_page(GFP_KERNEL); | |
1449 | if (!p_page) | |
1450 | goto free_avic; | |
1451 | ||
1452 | vm_data->avic_physical_id_table_page = p_page; | |
1453 | clear_page(page_address(p_page)); | |
1454 | ||
1455 | /* Allocating logical APIC ID table (4KB) */ | |
1456 | l_page = alloc_page(GFP_KERNEL); | |
1457 | if (!l_page) | |
1458 | goto free_avic; | |
1459 | ||
1460 | vm_data->avic_logical_id_table_page = l_page; | |
1461 | clear_page(page_address(l_page)); | |
1462 | ||
5881f737 | 1463 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); |
3f0d4db7 DV |
1464 | again: |
1465 | vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK; | |
1466 | if (vm_id == 0) { /* id is 1-based, zero is not okay */ | |
1467 | next_vm_id_wrapped = 1; | |
1468 | goto again; | |
1469 | } | |
1470 | /* Is it still in use? Only possible if wrapped at least once */ | |
1471 | if (next_vm_id_wrapped) { | |
1472 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1473 | struct kvm *k2 = container_of(ka, struct kvm, arch); | |
1474 | struct kvm_arch *vd2 = &k2->arch; | |
1475 | if (vd2->avic_vm_id == vm_id) | |
1476 | goto again; | |
1477 | } | |
1478 | } | |
1479 | vm_data->avic_vm_id = vm_id; | |
5881f737 SS |
1480 | hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id); |
1481 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1482 | ||
44a95dae SS |
1483 | return 0; |
1484 | ||
1485 | free_avic: | |
1486 | avic_vm_destroy(kvm); | |
1487 | return err; | |
6aa8b732 AK |
1488 | } |
1489 | ||
411b44ba SS |
1490 | static inline int |
1491 | avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) | |
8221c137 | 1492 | { |
411b44ba SS |
1493 | int ret = 0; |
1494 | unsigned long flags; | |
1495 | struct amd_svm_iommu_ir *ir; | |
8221c137 SS |
1496 | struct vcpu_svm *svm = to_svm(vcpu); |
1497 | ||
411b44ba SS |
1498 | if (!kvm_arch_has_assigned_device(vcpu->kvm)) |
1499 | return 0; | |
8221c137 | 1500 | |
411b44ba SS |
1501 | /* |
1502 | * Here, we go through the per-vcpu ir_list to update all existing | |
1503 | * interrupt remapping table entry targeting this vcpu. | |
1504 | */ | |
1505 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
8221c137 | 1506 | |
411b44ba SS |
1507 | if (list_empty(&svm->ir_list)) |
1508 | goto out; | |
8221c137 | 1509 | |
411b44ba SS |
1510 | list_for_each_entry(ir, &svm->ir_list, node) { |
1511 | ret = amd_iommu_update_ga(cpu, r, ir->data); | |
1512 | if (ret) | |
1513 | break; | |
1514 | } | |
1515 | out: | |
1516 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
1517 | return ret; | |
8221c137 SS |
1518 | } |
1519 | ||
1520 | static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
1521 | { | |
1522 | u64 entry; | |
1523 | /* ID = 0xff (broadcast), ID > 0xff (reserved) */ | |
7d669f50 | 1524 | int h_physical_id = kvm_cpu_get_apicid(cpu); |
8221c137 SS |
1525 | struct vcpu_svm *svm = to_svm(vcpu); |
1526 | ||
1527 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1528 | return; | |
1529 | ||
1530 | if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT)) | |
1531 | return; | |
1532 | ||
1533 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
1534 | WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
1535 | ||
1536 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; | |
1537 | entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); | |
1538 | ||
1539 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1540 | if (svm->avic_is_running) | |
1541 | entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1542 | ||
1543 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
411b44ba SS |
1544 | avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, |
1545 | svm->avic_is_running); | |
8221c137 SS |
1546 | } |
1547 | ||
1548 | static void avic_vcpu_put(struct kvm_vcpu *vcpu) | |
1549 | { | |
1550 | u64 entry; | |
1551 | struct vcpu_svm *svm = to_svm(vcpu); | |
1552 | ||
1553 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1554 | return; | |
1555 | ||
1556 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
411b44ba SS |
1557 | if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) |
1558 | avic_update_iommu_vcpu_affinity(vcpu, -1, 0); | |
1559 | ||
8221c137 SS |
1560 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; |
1561 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
6aa8b732 AK |
1562 | } |
1563 | ||
411b44ba SS |
1564 | /** |
1565 | * This function is called during VCPU halt/unhalt. | |
1566 | */ | |
1567 | static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) | |
1568 | { | |
1569 | struct vcpu_svm *svm = to_svm(vcpu); | |
1570 | ||
1571 | svm->avic_is_running = is_run; | |
1572 | if (is_run) | |
1573 | avic_vcpu_load(vcpu, vcpu->cpu); | |
1574 | else | |
1575 | avic_vcpu_put(vcpu); | |
1576 | } | |
1577 | ||
d28bc9dd | 1578 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
1579 | { |
1580 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1581 | u32 dummy; |
1582 | u32 eax = 1; | |
04d2cc77 | 1583 | |
d28bc9dd NA |
1584 | if (!init_event) { |
1585 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
1586 | MSR_IA32_APICBASE_ENABLE; | |
1587 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
1588 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
1589 | } | |
5690891b | 1590 | init_vmcb(svm); |
70433389 | 1591 | |
e911eb3b | 1592 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true); |
66f7b72e | 1593 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); |
44a95dae SS |
1594 | |
1595 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
1596 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
1597 | } |
1598 | ||
dfa20099 SS |
1599 | static int avic_init_vcpu(struct vcpu_svm *svm) |
1600 | { | |
1601 | int ret; | |
1602 | ||
67034bb9 | 1603 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
dfa20099 SS |
1604 | return 0; |
1605 | ||
1606 | ret = avic_init_backing_page(&svm->vcpu); | |
1607 | if (ret) | |
1608 | return ret; | |
1609 | ||
1610 | INIT_LIST_HEAD(&svm->ir_list); | |
1611 | spin_lock_init(&svm->ir_list_lock); | |
1612 | ||
1613 | return ret; | |
1614 | } | |
1615 | ||
fb3f0f51 | 1616 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1617 | { |
a2fa3e9f | 1618 | struct vcpu_svm *svm; |
6aa8b732 | 1619 | struct page *page; |
f65c229c | 1620 | struct page *msrpm_pages; |
b286d5d8 | 1621 | struct page *hsave_page; |
3d6368ef | 1622 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1623 | int err; |
6aa8b732 | 1624 | |
c16f862d | 1625 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1626 | if (!svm) { |
1627 | err = -ENOMEM; | |
1628 | goto out; | |
1629 | } | |
1630 | ||
1631 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1632 | if (err) | |
1633 | goto free_svm; | |
1634 | ||
b7af4043 | 1635 | err = -ENOMEM; |
6aa8b732 | 1636 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1637 | if (!page) |
fb3f0f51 | 1638 | goto uninit; |
6aa8b732 | 1639 | |
f65c229c JR |
1640 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1641 | if (!msrpm_pages) | |
b7af4043 | 1642 | goto free_page1; |
3d6368ef AG |
1643 | |
1644 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1645 | if (!nested_msrpm_pages) | |
b7af4043 | 1646 | goto free_page2; |
f65c229c | 1647 | |
b286d5d8 AG |
1648 | hsave_page = alloc_page(GFP_KERNEL); |
1649 | if (!hsave_page) | |
b7af4043 TY |
1650 | goto free_page3; |
1651 | ||
dfa20099 SS |
1652 | err = avic_init_vcpu(svm); |
1653 | if (err) | |
1654 | goto free_page4; | |
44a95dae | 1655 | |
8221c137 SS |
1656 | /* We initialize this flag to true to make sure that the is_running |
1657 | * bit would be set the first time the vcpu is loaded. | |
1658 | */ | |
1659 | svm->avic_is_running = true; | |
1660 | ||
e6aa9abd | 1661 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1662 | |
b7af4043 TY |
1663 | svm->msrpm = page_address(msrpm_pages); |
1664 | svm_vcpu_init_msrpm(svm->msrpm); | |
1665 | ||
e6aa9abd | 1666 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1667 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1668 | |
a2fa3e9f GH |
1669 | svm->vmcb = page_address(page); |
1670 | clear_page(svm->vmcb); | |
d0ec49d4 | 1671 | svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT); |
a2fa3e9f | 1672 | svm->asid_generation = 0; |
5690891b | 1673 | init_vmcb(svm); |
6aa8b732 | 1674 | |
2b036c6b BO |
1675 | svm_init_osvw(&svm->vcpu); |
1676 | ||
fb3f0f51 | 1677 | return &svm->vcpu; |
36241b8c | 1678 | |
44a95dae SS |
1679 | free_page4: |
1680 | __free_page(hsave_page); | |
b7af4043 TY |
1681 | free_page3: |
1682 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1683 | free_page2: | |
1684 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1685 | free_page1: | |
1686 | __free_page(page); | |
fb3f0f51 RR |
1687 | uninit: |
1688 | kvm_vcpu_uninit(&svm->vcpu); | |
1689 | free_svm: | |
a4770347 | 1690 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1691 | out: |
1692 | return ERR_PTR(err); | |
6aa8b732 AK |
1693 | } |
1694 | ||
1695 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1696 | { | |
a2fa3e9f GH |
1697 | struct vcpu_svm *svm = to_svm(vcpu); |
1698 | ||
d0ec49d4 | 1699 | __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT)); |
f65c229c | 1700 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1701 | __free_page(virt_to_page(svm->nested.hsave)); |
1702 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1703 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1704 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1705 | } |
1706 | ||
15ad7146 | 1707 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1708 | { |
a2fa3e9f | 1709 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1710 | int i; |
0cc5064d | 1711 | |
0cc5064d | 1712 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1713 | svm->asid_generation = 0; |
8d28fec4 | 1714 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1715 | } |
94dfbdb3 | 1716 | |
82ca2d10 AK |
1717 | #ifdef CONFIG_X86_64 |
1718 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1719 | #endif | |
dacccfdd AK |
1720 | savesegment(fs, svm->host.fs); |
1721 | savesegment(gs, svm->host.gs); | |
1722 | svm->host.ldt = kvm_read_ldt(); | |
1723 | ||
94dfbdb3 | 1724 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1725 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 1726 | |
ad721883 HZ |
1727 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
1728 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
1729 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
1730 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
1731 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
1732 | } | |
fbc0db76 | 1733 | } |
46896c73 PB |
1734 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
1735 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
1736 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
8221c137 SS |
1737 | |
1738 | avic_vcpu_load(vcpu, cpu); | |
6aa8b732 AK |
1739 | } |
1740 | ||
1741 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1742 | { | |
a2fa3e9f | 1743 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1744 | int i; |
1745 | ||
8221c137 SS |
1746 | avic_vcpu_put(vcpu); |
1747 | ||
e1beb1d3 | 1748 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1749 | kvm_load_ldt(svm->host.ldt); |
1750 | #ifdef CONFIG_X86_64 | |
1751 | loadsegment(fs, svm->host.fs); | |
296f781a | 1752 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase); |
893a5ab6 | 1753 | load_gs_index(svm->host.gs); |
dacccfdd | 1754 | #else |
831ca609 | 1755 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1756 | loadsegment(gs, svm->host.gs); |
831ca609 | 1757 | #endif |
dacccfdd | 1758 | #endif |
94dfbdb3 | 1759 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1760 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1761 | } |
1762 | ||
8221c137 SS |
1763 | static void svm_vcpu_blocking(struct kvm_vcpu *vcpu) |
1764 | { | |
1765 | avic_set_running(vcpu, false); | |
1766 | } | |
1767 | ||
1768 | static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1769 | { | |
1770 | avic_set_running(vcpu, true); | |
1771 | } | |
1772 | ||
6aa8b732 AK |
1773 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1774 | { | |
9b611747 LP |
1775 | struct vcpu_svm *svm = to_svm(vcpu); |
1776 | unsigned long rflags = svm->vmcb->save.rflags; | |
1777 | ||
1778 | if (svm->nmi_singlestep) { | |
1779 | /* Hide our flags if they were not set by the guest */ | |
1780 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
1781 | rflags &= ~X86_EFLAGS_TF; | |
1782 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
1783 | rflags &= ~X86_EFLAGS_RF; | |
1784 | } | |
1785 | return rflags; | |
6aa8b732 AK |
1786 | } |
1787 | ||
1788 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1789 | { | |
9b611747 LP |
1790 | if (to_svm(vcpu)->nmi_singlestep) |
1791 | rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1792 | ||
ae9fedc7 | 1793 | /* |
bb3541f1 | 1794 | * Any change of EFLAGS.VM is accompanied by a reload of SS |
ae9fedc7 PB |
1795 | * (caused by either a task switch or an inter-privilege IRET), |
1796 | * so we do not need to update the CPL here. | |
1797 | */ | |
a2fa3e9f | 1798 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1799 | } |
1800 | ||
6de4f3ad AK |
1801 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1802 | { | |
1803 | switch (reg) { | |
1804 | case VCPU_EXREG_PDPTR: | |
1805 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1806 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1807 | break; |
1808 | default: | |
1809 | BUG(); | |
1810 | } | |
1811 | } | |
1812 | ||
f0b85051 AG |
1813 | static void svm_set_vintr(struct vcpu_svm *svm) |
1814 | { | |
8a05a1b8 | 1815 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1816 | } |
1817 | ||
1818 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1819 | { | |
8a05a1b8 | 1820 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1821 | } |
1822 | ||
6aa8b732 AK |
1823 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1824 | { | |
a2fa3e9f | 1825 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1826 | |
1827 | switch (seg) { | |
1828 | case VCPU_SREG_CS: return &save->cs; | |
1829 | case VCPU_SREG_DS: return &save->ds; | |
1830 | case VCPU_SREG_ES: return &save->es; | |
1831 | case VCPU_SREG_FS: return &save->fs; | |
1832 | case VCPU_SREG_GS: return &save->gs; | |
1833 | case VCPU_SREG_SS: return &save->ss; | |
1834 | case VCPU_SREG_TR: return &save->tr; | |
1835 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1836 | } | |
1837 | BUG(); | |
8b6d44c7 | 1838 | return NULL; |
6aa8b732 AK |
1839 | } |
1840 | ||
1841 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1842 | { | |
1843 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1844 | ||
1845 | return s->base; | |
1846 | } | |
1847 | ||
1848 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1849 | struct kvm_segment *var, int seg) | |
1850 | { | |
1851 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1852 | ||
1853 | var->base = s->base; | |
1854 | var->limit = s->limit; | |
1855 | var->selector = s->selector; | |
1856 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1857 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1858 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1859 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1860 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1861 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1862 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
1863 | |
1864 | /* | |
1865 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
1866 | * However, the SVM spec states that the G bit is not observed by the | |
1867 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
1868 | * So let's synthesize a legal G bit for all segments, this helps | |
1869 | * running KVM nested. It also helps cross-vendor migration, because | |
1870 | * Intel's vmentry has a check on the 'G' bit. | |
1871 | */ | |
1872 | var->g = s->limit > 0xfffff; | |
25022acc | 1873 | |
e0231715 JR |
1874 | /* |
1875 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1876 | * for cross vendor migration purposes by "not present" |
1877 | */ | |
8eae9570 | 1878 | var->unusable = !var->present; |
19bca6ab | 1879 | |
1fbdc7a5 | 1880 | switch (seg) { |
1fbdc7a5 AP |
1881 | case VCPU_SREG_TR: |
1882 | /* | |
1883 | * Work around a bug where the busy flag in the tr selector | |
1884 | * isn't exposed | |
1885 | */ | |
c0d09828 | 1886 | var->type |= 0x2; |
1fbdc7a5 AP |
1887 | break; |
1888 | case VCPU_SREG_DS: | |
1889 | case VCPU_SREG_ES: | |
1890 | case VCPU_SREG_FS: | |
1891 | case VCPU_SREG_GS: | |
1892 | /* | |
1893 | * The accessed bit must always be set in the segment | |
1894 | * descriptor cache, although it can be cleared in the | |
1895 | * descriptor, the cached bit always remains at 1. Since | |
1896 | * Intel has a check on this, set it here to support | |
1897 | * cross-vendor migration. | |
1898 | */ | |
1899 | if (!var->unusable) | |
1900 | var->type |= 0x1; | |
1901 | break; | |
b586eb02 | 1902 | case VCPU_SREG_SS: |
e0231715 JR |
1903 | /* |
1904 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1905 | * descriptor is left as 1, although the whole segment has |
1906 | * been made unusable. Clear it here to pass an Intel VMX | |
1907 | * entry check when cross vendor migrating. | |
1908 | */ | |
1909 | if (var->unusable) | |
1910 | var->db = 0; | |
d9c1b543 | 1911 | /* This is symmetric with svm_set_segment() */ |
33b458d2 | 1912 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 1913 | break; |
1fbdc7a5 | 1914 | } |
6aa8b732 AK |
1915 | } |
1916 | ||
2e4d2653 IE |
1917 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1918 | { | |
1919 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1920 | ||
1921 | return save->cpl; | |
1922 | } | |
1923 | ||
89a27f4d | 1924 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1925 | { |
a2fa3e9f GH |
1926 | struct vcpu_svm *svm = to_svm(vcpu); |
1927 | ||
89a27f4d GN |
1928 | dt->size = svm->vmcb->save.idtr.limit; |
1929 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1930 | } |
1931 | ||
89a27f4d | 1932 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1933 | { |
a2fa3e9f GH |
1934 | struct vcpu_svm *svm = to_svm(vcpu); |
1935 | ||
89a27f4d GN |
1936 | svm->vmcb->save.idtr.limit = dt->size; |
1937 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1938 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1939 | } |
1940 | ||
89a27f4d | 1941 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1942 | { |
a2fa3e9f GH |
1943 | struct vcpu_svm *svm = to_svm(vcpu); |
1944 | ||
89a27f4d GN |
1945 | dt->size = svm->vmcb->save.gdtr.limit; |
1946 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1947 | } |
1948 | ||
89a27f4d | 1949 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1950 | { |
a2fa3e9f GH |
1951 | struct vcpu_svm *svm = to_svm(vcpu); |
1952 | ||
89a27f4d GN |
1953 | svm->vmcb->save.gdtr.limit = dt->size; |
1954 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1955 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1956 | } |
1957 | ||
e8467fda AK |
1958 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1959 | { | |
1960 | } | |
1961 | ||
aff48baa AK |
1962 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1963 | { | |
1964 | } | |
1965 | ||
25c4c276 | 1966 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1967 | { |
1968 | } | |
1969 | ||
d225157b AK |
1970 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1971 | { | |
1972 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1973 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1974 | ||
bd7e5b08 PB |
1975 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) |
1976 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
d225157b | 1977 | |
dcca1a65 | 1978 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1979 | |
bd7e5b08 | 1980 | if (gcr0 == *hcr0) { |
4ee546b4 RJ |
1981 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1982 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1983 | } else { |
4ee546b4 RJ |
1984 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1985 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1986 | } |
1987 | } | |
1988 | ||
6aa8b732 AK |
1989 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1990 | { | |
a2fa3e9f GH |
1991 | struct vcpu_svm *svm = to_svm(vcpu); |
1992 | ||
05b3e0c2 | 1993 | #ifdef CONFIG_X86_64 |
f6801dff | 1994 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1995 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1996 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1997 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1998 | } |
1999 | ||
d77c26fc | 2000 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 2001 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 2002 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
2003 | } |
2004 | } | |
2005 | #endif | |
ad312c7c | 2006 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
2007 | |
2008 | if (!npt_enabled) | |
2009 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 | 2010 | |
bcf166a9 PB |
2011 | /* |
2012 | * re-enable caching here because the QEMU bios | |
2013 | * does not do it - this results in some delay at | |
2014 | * reboot | |
2015 | */ | |
2016 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
2017 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 2018 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 2019 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2020 | update_cr0_intercept(svm); |
6aa8b732 AK |
2021 | } |
2022 | ||
5e1746d6 | 2023 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 2024 | { |
1e02ce4c | 2025 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
2026 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
2027 | ||
5e1746d6 NHE |
2028 | if (cr4 & X86_CR4_VMXE) |
2029 | return 1; | |
2030 | ||
e5eab0ce | 2031 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 2032 | svm_flush_tlb(vcpu); |
6394b649 | 2033 | |
ec077263 JR |
2034 | vcpu->arch.cr4 = cr4; |
2035 | if (!npt_enabled) | |
2036 | cr4 |= X86_CR4_PAE; | |
6394b649 | 2037 | cr4 |= host_cr4_mce; |
ec077263 | 2038 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 2039 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 2040 | return 0; |
6aa8b732 AK |
2041 | } |
2042 | ||
2043 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
2044 | struct kvm_segment *var, int seg) | |
2045 | { | |
a2fa3e9f | 2046 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2047 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
2048 | ||
2049 | s->base = var->base; | |
2050 | s->limit = var->limit; | |
2051 | s->selector = var->selector; | |
d9c1b543 RP |
2052 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); |
2053 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
2054 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
2055 | s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT; | |
2056 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
2057 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
2058 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
2059 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
ae9fedc7 PB |
2060 | |
2061 | /* | |
2062 | * This is always accurate, except if SYSRET returned to a segment | |
2063 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
2064 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
2065 | * would entail passing the CPL to userspace and back. | |
2066 | */ | |
2067 | if (seg == VCPU_SREG_SS) | |
d9c1b543 RP |
2068 | /* This is symmetric with svm_get_segment() */ |
2069 | svm->vmcb->save.cpl = (var->dpl & 3); | |
6aa8b732 | 2070 | |
060d0c9a | 2071 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
2072 | } |
2073 | ||
cbdb967a | 2074 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 2075 | { |
d0bfb940 JK |
2076 | struct vcpu_svm *svm = to_svm(vcpu); |
2077 | ||
18c918c5 | 2078 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 2079 | |
d0bfb940 | 2080 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 2081 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 2082 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
2083 | } else |
2084 | vcpu->guest_debug = 0; | |
44c11430 GN |
2085 | } |
2086 | ||
0fe1e009 | 2087 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 2088 | { |
0fe1e009 TH |
2089 | if (sd->next_asid > sd->max_asid) { |
2090 | ++sd->asid_generation; | |
2091 | sd->next_asid = 1; | |
a2fa3e9f | 2092 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
2093 | } |
2094 | ||
0fe1e009 TH |
2095 | svm->asid_generation = sd->asid_generation; |
2096 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
2097 | |
2098 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
2099 | } |
2100 | ||
73aaf249 JK |
2101 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
2102 | { | |
2103 | return to_svm(vcpu)->vmcb->save.dr6; | |
2104 | } | |
2105 | ||
2106 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
2107 | { | |
2108 | struct vcpu_svm *svm = to_svm(vcpu); | |
2109 | ||
2110 | svm->vmcb->save.dr6 = value; | |
2111 | mark_dirty(svm->vmcb, VMCB_DR); | |
2112 | } | |
2113 | ||
facb0139 PB |
2114 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
2115 | { | |
2116 | struct vcpu_svm *svm = to_svm(vcpu); | |
2117 | ||
2118 | get_debugreg(vcpu->arch.db[0], 0); | |
2119 | get_debugreg(vcpu->arch.db[1], 1); | |
2120 | get_debugreg(vcpu->arch.db[2], 2); | |
2121 | get_debugreg(vcpu->arch.db[3], 3); | |
2122 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
2123 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
2124 | ||
2125 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
2126 | set_dr_intercepts(svm); | |
2127 | } | |
2128 | ||
020df079 | 2129 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 2130 | { |
42dbaa5a | 2131 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 2132 | |
020df079 | 2133 | svm->vmcb->save.dr7 = value; |
72214b96 | 2134 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
2135 | } |
2136 | ||
851ba692 | 2137 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 2138 | { |
631bc487 | 2139 | u64 fault_address = svm->vmcb->control.exit_info_2; |
1261bfa3 | 2140 | u64 error_code = svm->vmcb->control.exit_info_1; |
6aa8b732 | 2141 | |
1261bfa3 | 2142 | return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address, |
dc25e89e | 2143 | svm->vmcb->control.insn_bytes, |
1261bfa3 | 2144 | svm->vmcb->control.insn_len, !npt_enabled); |
6aa8b732 AK |
2145 | } |
2146 | ||
851ba692 | 2147 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 2148 | { |
851ba692 AK |
2149 | struct kvm_run *kvm_run = svm->vcpu.run; |
2150 | ||
d0bfb940 | 2151 | if (!(svm->vcpu.guest_debug & |
44c11430 | 2152 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 2153 | !svm->nmi_singlestep) { |
d0bfb940 JK |
2154 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
2155 | return 1; | |
2156 | } | |
44c11430 | 2157 | |
6be7d306 | 2158 | if (svm->nmi_singlestep) { |
4aebd0e9 | 2159 | disable_nmi_singlestep(svm); |
44c11430 GN |
2160 | } |
2161 | ||
2162 | if (svm->vcpu.guest_debug & | |
e0231715 | 2163 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
2164 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2165 | kvm_run->debug.arch.pc = | |
2166 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2167 | kvm_run->debug.arch.exception = DB_VECTOR; | |
2168 | return 0; | |
2169 | } | |
2170 | ||
2171 | return 1; | |
d0bfb940 JK |
2172 | } |
2173 | ||
851ba692 | 2174 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 2175 | { |
851ba692 AK |
2176 | struct kvm_run *kvm_run = svm->vcpu.run; |
2177 | ||
d0bfb940 JK |
2178 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2179 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2180 | kvm_run->debug.arch.exception = BP_VECTOR; | |
2181 | return 0; | |
2182 | } | |
2183 | ||
851ba692 | 2184 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
2185 | { |
2186 | int er; | |
2187 | ||
51d8b661 | 2188 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2189 | if (er != EMULATE_DONE) |
7ee5d940 | 2190 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
2191 | return 1; |
2192 | } | |
2193 | ||
54a20552 EN |
2194 | static int ac_interception(struct vcpu_svm *svm) |
2195 | { | |
2196 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
2197 | return 1; | |
2198 | } | |
2199 | ||
67ec6607 JR |
2200 | static bool is_erratum_383(void) |
2201 | { | |
2202 | int err, i; | |
2203 | u64 value; | |
2204 | ||
2205 | if (!erratum_383_found) | |
2206 | return false; | |
2207 | ||
2208 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
2209 | if (err) | |
2210 | return false; | |
2211 | ||
2212 | /* Bit 62 may or may not be set for this mce */ | |
2213 | value &= ~(1ULL << 62); | |
2214 | ||
2215 | if (value != 0xb600000000010015ULL) | |
2216 | return false; | |
2217 | ||
2218 | /* Clear MCi_STATUS registers */ | |
2219 | for (i = 0; i < 6; ++i) | |
2220 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
2221 | ||
2222 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
2223 | if (!err) { | |
2224 | u32 low, high; | |
2225 | ||
2226 | value &= ~(1ULL << 2); | |
2227 | low = lower_32_bits(value); | |
2228 | high = upper_32_bits(value); | |
2229 | ||
2230 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
2231 | } | |
2232 | ||
2233 | /* Flush tlb to evict multi-match entries */ | |
2234 | __flush_tlb_all(); | |
2235 | ||
2236 | return true; | |
2237 | } | |
2238 | ||
fe5913e4 | 2239 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 2240 | { |
67ec6607 JR |
2241 | if (is_erratum_383()) { |
2242 | /* | |
2243 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
2244 | * guest. | |
2245 | */ | |
2246 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
2247 | ||
a8eeb04a | 2248 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
2249 | |
2250 | return; | |
2251 | } | |
2252 | ||
53371b50 JR |
2253 | /* |
2254 | * On an #MC intercept the MCE handler is not called automatically in | |
2255 | * the host. So do it by hand here. | |
2256 | */ | |
2257 | asm volatile ( | |
2258 | "int $0x12\n"); | |
2259 | /* not sure if we ever come back to this point */ | |
2260 | ||
fe5913e4 JR |
2261 | return; |
2262 | } | |
2263 | ||
2264 | static int mc_interception(struct vcpu_svm *svm) | |
2265 | { | |
53371b50 JR |
2266 | return 1; |
2267 | } | |
2268 | ||
851ba692 | 2269 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2270 | { |
851ba692 AK |
2271 | struct kvm_run *kvm_run = svm->vcpu.run; |
2272 | ||
46fe4ddd JR |
2273 | /* |
2274 | * VMCB is undefined after a SHUTDOWN intercept | |
2275 | * so reinitialize it. | |
2276 | */ | |
a2fa3e9f | 2277 | clear_page(svm->vmcb); |
5690891b | 2278 | init_vmcb(svm); |
46fe4ddd JR |
2279 | |
2280 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2281 | return 0; | |
2282 | } | |
2283 | ||
851ba692 | 2284 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2285 | { |
cf8f70bf | 2286 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2287 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
b742c1e6 | 2288 | int size, in, string, ret; |
039576c0 | 2289 | unsigned port; |
6aa8b732 | 2290 | |
e756fc62 | 2291 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2292 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2293 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
8370c3d0 | 2294 | if (string) |
51d8b661 | 2295 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 2296 | |
039576c0 AK |
2297 | port = io_info >> 16; |
2298 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2299 | svm->next_rip = svm->vmcb->control.exit_info_2; |
b742c1e6 | 2300 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
cf8f70bf | 2301 | |
b742c1e6 LP |
2302 | /* |
2303 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
2304 | * KVM_EXIT_DEBUG here. | |
2305 | */ | |
2306 | if (in) | |
2307 | return kvm_fast_pio_in(vcpu, size, port) && ret; | |
2308 | else | |
2309 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
2310 | } |
2311 | ||
851ba692 | 2312 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2313 | { |
2314 | return 1; | |
2315 | } | |
2316 | ||
851ba692 | 2317 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2318 | { |
2319 | ++svm->vcpu.stat.irq_exits; | |
2320 | return 1; | |
2321 | } | |
2322 | ||
851ba692 | 2323 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2324 | { |
2325 | return 1; | |
2326 | } | |
2327 | ||
851ba692 | 2328 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2329 | { |
5fdbf976 | 2330 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 | 2331 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2332 | } |
2333 | ||
851ba692 | 2334 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2335 | { |
5fdbf976 | 2336 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
0d9c055e | 2337 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2338 | } |
2339 | ||
5bd2edc3 JR |
2340 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2341 | { | |
2342 | struct vcpu_svm *svm = to_svm(vcpu); | |
2343 | ||
2344 | return svm->nested.nested_cr3; | |
2345 | } | |
2346 | ||
e4e517b4 AK |
2347 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2348 | { | |
2349 | struct vcpu_svm *svm = to_svm(vcpu); | |
2350 | u64 cr3 = svm->nested.nested_cr3; | |
2351 | u64 pdpte; | |
2352 | int ret; | |
2353 | ||
d0ec49d4 | 2354 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte, |
54bf36aa | 2355 | offset_in_page(cr3) + index * 8, 8); |
e4e517b4 AK |
2356 | if (ret) |
2357 | return 0; | |
2358 | return pdpte; | |
2359 | } | |
2360 | ||
5bd2edc3 JR |
2361 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2362 | unsigned long root) | |
2363 | { | |
2364 | struct vcpu_svm *svm = to_svm(vcpu); | |
2365 | ||
d0ec49d4 | 2366 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 2367 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 2368 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
2369 | } |
2370 | ||
6389ee94 AK |
2371 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2372 | struct x86_exception *fault) | |
5bd2edc3 JR |
2373 | { |
2374 | struct vcpu_svm *svm = to_svm(vcpu); | |
2375 | ||
5e352519 PB |
2376 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2377 | /* | |
2378 | * TODO: track the cause of the nested page fault, and | |
2379 | * correctly fill in the high bits of exit_info_1. | |
2380 | */ | |
2381 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2382 | svm->vmcb->control.exit_code_hi = 0; | |
2383 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
2384 | svm->vmcb->control.exit_info_2 = fault->address; | |
2385 | } | |
2386 | ||
2387 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
2388 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
2389 | ||
2390 | /* | |
2391 | * The present bit is always zero for page structure faults on real | |
2392 | * hardware. | |
2393 | */ | |
2394 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
2395 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
2396 | |
2397 | nested_svm_vmexit(svm); | |
2398 | } | |
2399 | ||
8a3c1a33 | 2400 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 2401 | { |
ad896af0 PB |
2402 | WARN_ON(mmu_is_nested(vcpu)); |
2403 | kvm_init_shadow_mmu(vcpu); | |
4b16184c JR |
2404 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; |
2405 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 2406 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c | 2407 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
855feb67 | 2408 | vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu); |
c258b62b | 2409 | reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu); |
4b16184c | 2410 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
2411 | } |
2412 | ||
2413 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
2414 | { | |
2415 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
2416 | } | |
2417 | ||
c0725420 AG |
2418 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
2419 | { | |
e9196ceb DC |
2420 | if (!(svm->vcpu.arch.efer & EFER_SVME) || |
2421 | !is_paging(&svm->vcpu)) { | |
c0725420 AG |
2422 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
2423 | return 1; | |
2424 | } | |
2425 | ||
2426 | if (svm->vmcb->save.cpl) { | |
2427 | kvm_inject_gp(&svm->vcpu, 0); | |
2428 | return 1; | |
2429 | } | |
2430 | ||
e9196ceb | 2431 | return 0; |
c0725420 AG |
2432 | } |
2433 | ||
cf74a78b AG |
2434 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2435 | bool has_error_code, u32 error_code) | |
2436 | { | |
b8e88bc8 JR |
2437 | int vmexit; |
2438 | ||
2030753d | 2439 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2440 | return 0; |
cf74a78b | 2441 | |
adfe20fb WL |
2442 | vmexit = nested_svm_intercept(svm); |
2443 | if (vmexit != NESTED_EXIT_DONE) | |
2444 | return 0; | |
2445 | ||
0295ad7d JR |
2446 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2447 | svm->vmcb->control.exit_code_hi = 0; | |
2448 | svm->vmcb->control.exit_info_1 = error_code; | |
b96fb439 PB |
2449 | |
2450 | /* | |
2451 | * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception. | |
2452 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2453 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be | |
2454 | * written only when inject_pending_event runs (DR6 would written here | |
2455 | * too). This should be conditional on a new capability---if the | |
2456 | * capability is disabled, kvm_multiple_exception would write the | |
2457 | * ancillary information to CR2 or DR6, for backwards ABI-compatibility. | |
2458 | */ | |
adfe20fb WL |
2459 | if (svm->vcpu.arch.exception.nested_apf) |
2460 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token; | |
2461 | else | |
2462 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
b8e88bc8 | 2463 | |
adfe20fb | 2464 | svm->nested.exit_required = true; |
b8e88bc8 | 2465 | return vmexit; |
cf74a78b AG |
2466 | } |
2467 | ||
8fe54654 JR |
2468 | /* This function returns true if it is save to enable the irq window */ |
2469 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2470 | { |
2030753d | 2471 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2472 | return true; |
cf74a78b | 2473 | |
26666957 | 2474 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2475 | return true; |
cf74a78b | 2476 | |
26666957 | 2477 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2478 | return false; |
cf74a78b | 2479 | |
a0a07cd2 GN |
2480 | /* |
2481 | * if vmexit was already requested (by intercepted exception | |
2482 | * for instance) do not overwrite it with "external interrupt" | |
2483 | * vmexit. | |
2484 | */ | |
2485 | if (svm->nested.exit_required) | |
2486 | return false; | |
2487 | ||
197717d5 JR |
2488 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2489 | svm->vmcb->control.exit_info_1 = 0; | |
2490 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2491 | |
cd3ff653 JR |
2492 | if (svm->nested.intercept & 1ULL) { |
2493 | /* | |
2494 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2495 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2496 | * #vmexit emulation might sleep. Only signal request for |
2497 | * the #vmexit here. | |
2498 | */ | |
2499 | svm->nested.exit_required = true; | |
236649de | 2500 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2501 | return false; |
cf74a78b AG |
2502 | } |
2503 | ||
8fe54654 | 2504 | return true; |
cf74a78b AG |
2505 | } |
2506 | ||
887f500c JR |
2507 | /* This function returns true if it is save to enable the nmi window */ |
2508 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2509 | { | |
2030753d | 2510 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2511 | return true; |
2512 | ||
2513 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2514 | return true; | |
2515 | ||
2516 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2517 | svm->nested.exit_required = true; | |
2518 | ||
2519 | return false; | |
cf74a78b AG |
2520 | } |
2521 | ||
7597f129 | 2522 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2523 | { |
2524 | struct page *page; | |
2525 | ||
6c3bd3d7 JR |
2526 | might_sleep(); |
2527 | ||
54bf36aa | 2528 | page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2529 | if (is_error_page(page)) |
2530 | goto error; | |
2531 | ||
7597f129 JR |
2532 | *_page = page; |
2533 | ||
2534 | return kmap(page); | |
34f80cfa JR |
2535 | |
2536 | error: | |
34f80cfa JR |
2537 | kvm_inject_gp(&svm->vcpu, 0); |
2538 | ||
2539 | return NULL; | |
2540 | } | |
2541 | ||
7597f129 | 2542 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2543 | { |
7597f129 | 2544 | kunmap(page); |
34f80cfa JR |
2545 | kvm_release_page_dirty(page); |
2546 | } | |
34f80cfa | 2547 | |
ce2ac085 JR |
2548 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2549 | { | |
9bf41833 JK |
2550 | unsigned port, size, iopm_len; |
2551 | u16 val, mask; | |
2552 | u8 start_bit; | |
ce2ac085 | 2553 | u64 gpa; |
34f80cfa | 2554 | |
ce2ac085 JR |
2555 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2556 | return NESTED_EXIT_HOST; | |
34f80cfa | 2557 | |
ce2ac085 | 2558 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
2559 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
2560 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 2561 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
2562 | start_bit = port % 8; |
2563 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
2564 | mask = (0xf >> (4 - size)) << start_bit; | |
2565 | val = 0; | |
ce2ac085 | 2566 | |
54bf36aa | 2567 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 2568 | return NESTED_EXIT_DONE; |
ce2ac085 | 2569 | |
9bf41833 | 2570 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
2571 | } |
2572 | ||
d2477826 | 2573 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2574 | { |
0d6b3537 JR |
2575 | u32 offset, msr, value; |
2576 | int write, mask; | |
4c2161ae | 2577 | |
3d62d9aa | 2578 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2579 | return NESTED_EXIT_HOST; |
3d62d9aa | 2580 | |
0d6b3537 JR |
2581 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2582 | offset = svm_msrpm_offset(msr); | |
2583 | write = svm->vmcb->control.exit_info_1 & 1; | |
2584 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2585 | |
0d6b3537 JR |
2586 | if (offset == MSR_INVALID) |
2587 | return NESTED_EXIT_DONE; | |
4c2161ae | 2588 | |
0d6b3537 JR |
2589 | /* Offset is in 32 bit units but need in 8 bit units */ |
2590 | offset *= 4; | |
4c2161ae | 2591 | |
54bf36aa | 2592 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 2593 | return NESTED_EXIT_DONE; |
3d62d9aa | 2594 | |
0d6b3537 | 2595 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2596 | } |
2597 | ||
ab2f4d73 LP |
2598 | /* DB exceptions for our internal use must not cause vmexit */ |
2599 | static int nested_svm_intercept_db(struct vcpu_svm *svm) | |
2600 | { | |
2601 | unsigned long dr6; | |
2602 | ||
2603 | /* if we're not singlestepping, it's not ours */ | |
2604 | if (!svm->nmi_singlestep) | |
2605 | return NESTED_EXIT_DONE; | |
2606 | ||
2607 | /* if it's not a singlestep exception, it's not ours */ | |
2608 | if (kvm_get_dr(&svm->vcpu, 6, &dr6)) | |
2609 | return NESTED_EXIT_DONE; | |
2610 | if (!(dr6 & DR6_BS)) | |
2611 | return NESTED_EXIT_DONE; | |
2612 | ||
2613 | /* if the guest is singlestepping, it should get the vmexit */ | |
2614 | if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) { | |
2615 | disable_nmi_singlestep(svm); | |
2616 | return NESTED_EXIT_DONE; | |
2617 | } | |
2618 | ||
2619 | /* it's ours, the nested hypervisor must not see this one */ | |
2620 | return NESTED_EXIT_HOST; | |
2621 | } | |
2622 | ||
410e4d57 | 2623 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2624 | { |
cf74a78b | 2625 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2626 | |
410e4d57 JR |
2627 | switch (exit_code) { |
2628 | case SVM_EXIT_INTR: | |
2629 | case SVM_EXIT_NMI: | |
ff47a49b | 2630 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2631 | return NESTED_EXIT_HOST; |
410e4d57 | 2632 | case SVM_EXIT_NPF: |
e0231715 | 2633 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2634 | if (npt_enabled) |
2635 | return NESTED_EXIT_HOST; | |
2636 | break; | |
410e4d57 | 2637 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 | 2638 | /* When we're shadowing, trap PFs, but not async PF */ |
1261bfa3 | 2639 | if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0) |
410e4d57 JR |
2640 | return NESTED_EXIT_HOST; |
2641 | break; | |
2642 | default: | |
2643 | break; | |
cf74a78b AG |
2644 | } |
2645 | ||
410e4d57 JR |
2646 | return NESTED_EXIT_CONTINUE; |
2647 | } | |
2648 | ||
2649 | /* | |
2650 | * If this function returns true, this #vmexit was already handled | |
2651 | */ | |
b8e88bc8 | 2652 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2653 | { |
2654 | u32 exit_code = svm->vmcb->control.exit_code; | |
2655 | int vmexit = NESTED_EXIT_HOST; | |
2656 | ||
cf74a78b | 2657 | switch (exit_code) { |
9c4e40b9 | 2658 | case SVM_EXIT_MSR: |
3d62d9aa | 2659 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2660 | break; |
ce2ac085 JR |
2661 | case SVM_EXIT_IOIO: |
2662 | vmexit = nested_svm_intercept_ioio(svm); | |
2663 | break; | |
4ee546b4 RJ |
2664 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2665 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2666 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2667 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2668 | break; |
2669 | } | |
3aed041a JR |
2670 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2671 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2672 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2673 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2674 | break; |
2675 | } | |
2676 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2677 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
ab2f4d73 LP |
2678 | if (svm->nested.intercept_exceptions & excp_bits) { |
2679 | if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR) | |
2680 | vmexit = nested_svm_intercept_db(svm); | |
2681 | else | |
2682 | vmexit = NESTED_EXIT_DONE; | |
2683 | } | |
631bc487 GN |
2684 | /* async page fault always cause vmexit */ |
2685 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
adfe20fb | 2686 | svm->vcpu.arch.exception.nested_apf != 0) |
631bc487 | 2687 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2688 | break; |
2689 | } | |
228070b1 JR |
2690 | case SVM_EXIT_ERR: { |
2691 | vmexit = NESTED_EXIT_DONE; | |
2692 | break; | |
2693 | } | |
cf74a78b AG |
2694 | default: { |
2695 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2696 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2697 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2698 | } |
2699 | } | |
2700 | ||
b8e88bc8 JR |
2701 | return vmexit; |
2702 | } | |
2703 | ||
2704 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2705 | { | |
2706 | int vmexit; | |
2707 | ||
2708 | vmexit = nested_svm_intercept(svm); | |
2709 | ||
2710 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2711 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2712 | |
2713 | return vmexit; | |
cf74a78b AG |
2714 | } |
2715 | ||
0460a979 JR |
2716 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2717 | { | |
2718 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2719 | struct vmcb_control_area *from = &from_vmcb->control; | |
2720 | ||
4ee546b4 | 2721 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2722 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2723 | dst->intercept_exceptions = from->intercept_exceptions; |
2724 | dst->intercept = from->intercept; | |
2725 | dst->iopm_base_pa = from->iopm_base_pa; | |
2726 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2727 | dst->tsc_offset = from->tsc_offset; | |
2728 | dst->asid = from->asid; | |
2729 | dst->tlb_ctl = from->tlb_ctl; | |
2730 | dst->int_ctl = from->int_ctl; | |
2731 | dst->int_vector = from->int_vector; | |
2732 | dst->int_state = from->int_state; | |
2733 | dst->exit_code = from->exit_code; | |
2734 | dst->exit_code_hi = from->exit_code_hi; | |
2735 | dst->exit_info_1 = from->exit_info_1; | |
2736 | dst->exit_info_2 = from->exit_info_2; | |
2737 | dst->exit_int_info = from->exit_int_info; | |
2738 | dst->exit_int_info_err = from->exit_int_info_err; | |
2739 | dst->nested_ctl = from->nested_ctl; | |
2740 | dst->event_inj = from->event_inj; | |
2741 | dst->event_inj_err = from->event_inj_err; | |
2742 | dst->nested_cr3 = from->nested_cr3; | |
0dc92119 | 2743 | dst->virt_ext = from->virt_ext; |
0460a979 JR |
2744 | } |
2745 | ||
34f80cfa | 2746 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2747 | { |
34f80cfa | 2748 | struct vmcb *nested_vmcb; |
e6aa9abd | 2749 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2750 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2751 | struct page *page; |
cf74a78b | 2752 | |
17897f36 JR |
2753 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2754 | vmcb->control.exit_info_1, | |
2755 | vmcb->control.exit_info_2, | |
2756 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2757 | vmcb->control.exit_int_info_err, |
2758 | KVM_ISA_SVM); | |
17897f36 | 2759 | |
7597f129 | 2760 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2761 | if (!nested_vmcb) |
2762 | return 1; | |
2763 | ||
2030753d JR |
2764 | /* Exit Guest-Mode */ |
2765 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2766 | svm->nested.vmcb = 0; |
2767 | ||
cf74a78b | 2768 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2769 | disable_gif(svm); |
2770 | ||
2771 | nested_vmcb->save.es = vmcb->save.es; | |
2772 | nested_vmcb->save.cs = vmcb->save.cs; | |
2773 | nested_vmcb->save.ss = vmcb->save.ss; | |
2774 | nested_vmcb->save.ds = vmcb->save.ds; | |
2775 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2776 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2777 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2778 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2779 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2780 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2781 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2782 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2783 | nested_vmcb->save.rip = vmcb->save.rip; |
2784 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2785 | nested_vmcb->save.rax = vmcb->save.rax; | |
2786 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2787 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2788 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2789 | ||
2790 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2791 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2792 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2793 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2794 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2795 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2796 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2797 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2798 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
2799 | |
2800 | if (svm->nrips_enabled) | |
2801 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
2802 | |
2803 | /* | |
2804 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2805 | * to make sure that we do not lose injected events. So check event_inj | |
2806 | * here and copy it to exit_int_info if it is valid. | |
2807 | * Exit_int_info and event_inj can't be both valid because the case | |
2808 | * below only happens on a VMRUN instruction intercept which has | |
2809 | * no valid exit_int_info set. | |
2810 | */ | |
2811 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2812 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2813 | ||
2814 | nc->exit_int_info = vmcb->control.event_inj; | |
2815 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2816 | } | |
2817 | ||
33740e40 JR |
2818 | nested_vmcb->control.tlb_ctl = 0; |
2819 | nested_vmcb->control.event_inj = 0; | |
2820 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2821 | |
2822 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2823 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2824 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2825 | ||
cf74a78b | 2826 | /* Restore the original control entries */ |
0460a979 | 2827 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2828 | |
219b65dc AG |
2829 | kvm_clear_exception_queue(&svm->vcpu); |
2830 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2831 | |
4b16184c JR |
2832 | svm->nested.nested_cr3 = 0; |
2833 | ||
cf74a78b AG |
2834 | /* Restore selected save entries */ |
2835 | svm->vmcb->save.es = hsave->save.es; | |
2836 | svm->vmcb->save.cs = hsave->save.cs; | |
2837 | svm->vmcb->save.ss = hsave->save.ss; | |
2838 | svm->vmcb->save.ds = hsave->save.ds; | |
2839 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2840 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2841 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2842 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2843 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2844 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2845 | if (npt_enabled) { | |
2846 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2847 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2848 | } else { | |
2390218b | 2849 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2850 | } |
2851 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2852 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2853 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2854 | svm->vmcb->save.dr7 = 0; | |
2855 | svm->vmcb->save.cpl = 0; | |
2856 | svm->vmcb->control.exit_int_info = 0; | |
2857 | ||
8d28fec4 RJ |
2858 | mark_all_dirty(svm->vmcb); |
2859 | ||
7597f129 | 2860 | nested_svm_unmap(page); |
cf74a78b | 2861 | |
4b16184c | 2862 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2863 | kvm_mmu_reset_context(&svm->vcpu); |
2864 | kvm_mmu_load(&svm->vcpu); | |
2865 | ||
2866 | return 0; | |
2867 | } | |
3d6368ef | 2868 | |
9738b2c9 | 2869 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2870 | { |
323c3d80 JR |
2871 | /* |
2872 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2873 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2874 | * the kvm msr permission bitmap may contain zero bits |
2875 | */ | |
3d6368ef | 2876 | int i; |
9738b2c9 | 2877 | |
323c3d80 JR |
2878 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2879 | return true; | |
9738b2c9 | 2880 | |
323c3d80 JR |
2881 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2882 | u32 value, p; | |
2883 | u64 offset; | |
9738b2c9 | 2884 | |
323c3d80 JR |
2885 | if (msrpm_offsets[i] == 0xffffffff) |
2886 | break; | |
3d6368ef | 2887 | |
0d6b3537 JR |
2888 | p = msrpm_offsets[i]; |
2889 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 2890 | |
54bf36aa | 2891 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
2892 | return false; |
2893 | ||
2894 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2895 | } | |
3d6368ef | 2896 | |
d0ec49d4 | 2897 | svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm)); |
9738b2c9 JR |
2898 | |
2899 | return true; | |
3d6368ef AG |
2900 | } |
2901 | ||
52c65a30 JR |
2902 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2903 | { | |
2904 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2905 | return false; | |
2906 | ||
dbe77584 JR |
2907 | if (vmcb->control.asid == 0) |
2908 | return false; | |
2909 | ||
4b16184c JR |
2910 | if (vmcb->control.nested_ctl && !npt_enabled) |
2911 | return false; | |
2912 | ||
52c65a30 JR |
2913 | return true; |
2914 | } | |
2915 | ||
9738b2c9 | 2916 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2917 | { |
9738b2c9 | 2918 | struct vmcb *nested_vmcb; |
e6aa9abd | 2919 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2920 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2921 | struct page *page; |
06fc7772 | 2922 | u64 vmcb_gpa; |
3d6368ef | 2923 | |
06fc7772 | 2924 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2925 | |
7597f129 | 2926 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2927 | if (!nested_vmcb) |
2928 | return false; | |
2929 | ||
52c65a30 JR |
2930 | if (!nested_vmcb_checks(nested_vmcb)) { |
2931 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2932 | nested_vmcb->control.exit_code_hi = 0; | |
2933 | nested_vmcb->control.exit_info_1 = 0; | |
2934 | nested_vmcb->control.exit_info_2 = 0; | |
2935 | ||
2936 | nested_svm_unmap(page); | |
2937 | ||
2938 | return false; | |
2939 | } | |
2940 | ||
b75f4eb3 | 2941 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2942 | nested_vmcb->save.rip, |
2943 | nested_vmcb->control.int_ctl, | |
2944 | nested_vmcb->control.event_inj, | |
2945 | nested_vmcb->control.nested_ctl); | |
2946 | ||
4ee546b4 RJ |
2947 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2948 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2949 | nested_vmcb->control.intercept_exceptions, |
2950 | nested_vmcb->control.intercept); | |
2951 | ||
3d6368ef | 2952 | /* Clear internal status */ |
219b65dc AG |
2953 | kvm_clear_exception_queue(&svm->vcpu); |
2954 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2955 | |
e0231715 JR |
2956 | /* |
2957 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2958 | * restore everything when a VMEXIT occurs | |
2959 | */ | |
defbba56 JR |
2960 | hsave->save.es = vmcb->save.es; |
2961 | hsave->save.cs = vmcb->save.cs; | |
2962 | hsave->save.ss = vmcb->save.ss; | |
2963 | hsave->save.ds = vmcb->save.ds; | |
2964 | hsave->save.gdtr = vmcb->save.gdtr; | |
2965 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2966 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2967 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2968 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2969 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2970 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2971 | hsave->save.rsp = vmcb->save.rsp; |
2972 | hsave->save.rax = vmcb->save.rax; | |
2973 | if (npt_enabled) | |
2974 | hsave->save.cr3 = vmcb->save.cr3; | |
2975 | else | |
9f8fe504 | 2976 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2977 | |
0460a979 | 2978 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2979 | |
f6e78475 | 2980 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2981 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2982 | else | |
2983 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2984 | ||
4b16184c JR |
2985 | if (nested_vmcb->control.nested_ctl) { |
2986 | kvm_mmu_unload(&svm->vcpu); | |
2987 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2988 | nested_svm_init_mmu_context(&svm->vcpu); | |
2989 | } | |
2990 | ||
3d6368ef AG |
2991 | /* Load the nested guest state */ |
2992 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2993 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2994 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2995 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2996 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2997 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2998 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2999 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
3000 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
3001 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
3002 | if (npt_enabled) { | |
3003 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
3004 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 3005 | } else |
2390218b | 3006 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
3007 | |
3008 | /* Guest paging mode is active - reset mmu */ | |
3009 | kvm_mmu_reset_context(&svm->vcpu); | |
3010 | ||
defbba56 | 3011 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
3012 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
3013 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
3014 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 3015 | |
3d6368ef AG |
3016 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
3017 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
3018 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
3019 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
3020 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
3021 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
3022 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
3023 | ||
f7138538 | 3024 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 3025 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 3026 | |
aad42c64 | 3027 | /* cache intercepts */ |
4ee546b4 | 3028 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 3029 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
3030 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
3031 | svm->nested.intercept = nested_vmcb->control.intercept; | |
3032 | ||
f40f6a45 | 3033 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 3034 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
3035 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
3036 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
3037 | else | |
3038 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
3039 | ||
88ab24ad JR |
3040 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
3041 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
3042 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
3043 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
3044 | } |
3045 | ||
0d945bd9 | 3046 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 3047 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 3048 | |
0dc92119 | 3049 | svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext; |
3d6368ef AG |
3050 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
3051 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
3052 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
3053 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
3054 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
3055 | ||
7597f129 | 3056 | nested_svm_unmap(page); |
9738b2c9 | 3057 | |
2030753d JR |
3058 | /* Enter Guest-Mode */ |
3059 | enter_guest_mode(&svm->vcpu); | |
3060 | ||
384c6368 JR |
3061 | /* |
3062 | * Merge guest and host intercepts - must be called with vcpu in | |
3063 | * guest-mode to take affect here | |
3064 | */ | |
3065 | recalc_intercepts(svm); | |
3066 | ||
06fc7772 | 3067 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 3068 | |
2af9194d | 3069 | enable_gif(svm); |
3d6368ef | 3070 | |
8d28fec4 RJ |
3071 | mark_all_dirty(svm->vmcb); |
3072 | ||
9738b2c9 | 3073 | return true; |
3d6368ef AG |
3074 | } |
3075 | ||
9966bf68 | 3076 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
3077 | { |
3078 | to_vmcb->save.fs = from_vmcb->save.fs; | |
3079 | to_vmcb->save.gs = from_vmcb->save.gs; | |
3080 | to_vmcb->save.tr = from_vmcb->save.tr; | |
3081 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
3082 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
3083 | to_vmcb->save.star = from_vmcb->save.star; | |
3084 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
3085 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
3086 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
3087 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
3088 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
3089 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
3090 | } |
3091 | ||
851ba692 | 3092 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 3093 | { |
9966bf68 | 3094 | struct vmcb *nested_vmcb; |
7597f129 | 3095 | struct page *page; |
b742c1e6 | 3096 | int ret; |
9966bf68 | 3097 | |
5542675b AG |
3098 | if (nested_svm_check_permissions(svm)) |
3099 | return 1; | |
3100 | ||
7597f129 | 3101 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3102 | if (!nested_vmcb) |
3103 | return 1; | |
3104 | ||
e3e9ed3d | 3105 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3106 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3107 | |
9966bf68 | 3108 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 3109 | nested_svm_unmap(page); |
5542675b | 3110 | |
b742c1e6 | 3111 | return ret; |
5542675b AG |
3112 | } |
3113 | ||
851ba692 | 3114 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 3115 | { |
9966bf68 | 3116 | struct vmcb *nested_vmcb; |
7597f129 | 3117 | struct page *page; |
b742c1e6 | 3118 | int ret; |
9966bf68 | 3119 | |
5542675b AG |
3120 | if (nested_svm_check_permissions(svm)) |
3121 | return 1; | |
3122 | ||
7597f129 | 3123 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3124 | if (!nested_vmcb) |
3125 | return 1; | |
3126 | ||
e3e9ed3d | 3127 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3128 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3129 | |
9966bf68 | 3130 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 3131 | nested_svm_unmap(page); |
5542675b | 3132 | |
b742c1e6 | 3133 | return ret; |
5542675b AG |
3134 | } |
3135 | ||
851ba692 | 3136 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 3137 | { |
3d6368ef AG |
3138 | if (nested_svm_check_permissions(svm)) |
3139 | return 1; | |
3140 | ||
b75f4eb3 RJ |
3141 | /* Save rip after vmrun instruction */ |
3142 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 3143 | |
9738b2c9 | 3144 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
3145 | return 1; |
3146 | ||
9738b2c9 | 3147 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
3148 | goto failed; |
3149 | ||
3150 | return 1; | |
3151 | ||
3152 | failed: | |
3153 | ||
3154 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
3155 | svm->vmcb->control.exit_code_hi = 0; | |
3156 | svm->vmcb->control.exit_info_1 = 0; | |
3157 | svm->vmcb->control.exit_info_2 = 0; | |
3158 | ||
3159 | nested_svm_vmexit(svm); | |
3d6368ef AG |
3160 | |
3161 | return 1; | |
3162 | } | |
3163 | ||
851ba692 | 3164 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 | 3165 | { |
b742c1e6 LP |
3166 | int ret; |
3167 | ||
1371d904 AG |
3168 | if (nested_svm_check_permissions(svm)) |
3169 | return 1; | |
3170 | ||
640bd6e5 JN |
3171 | /* |
3172 | * If VGIF is enabled, the STGI intercept is only added to | |
3173 | * detect the opening of the NMI window; remove it now. | |
3174 | */ | |
3175 | if (vgif_enabled(svm)) | |
3176 | clr_intercept(svm, INTERCEPT_STGI); | |
3177 | ||
1371d904 | 3178 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3179 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
3842d135 | 3180 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 3181 | |
2af9194d | 3182 | enable_gif(svm); |
1371d904 | 3183 | |
b742c1e6 | 3184 | return ret; |
1371d904 AG |
3185 | } |
3186 | ||
851ba692 | 3187 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 | 3188 | { |
b742c1e6 LP |
3189 | int ret; |
3190 | ||
1371d904 AG |
3191 | if (nested_svm_check_permissions(svm)) |
3192 | return 1; | |
3193 | ||
3194 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3195 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
1371d904 | 3196 | |
2af9194d | 3197 | disable_gif(svm); |
1371d904 AG |
3198 | |
3199 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
3200 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
3201 | svm_clear_vintr(svm); | |
3202 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
3203 | mark_dirty(svm->vmcb, VMCB_INTR); | |
3204 | } | |
decdbf6a | 3205 | |
b742c1e6 | 3206 | return ret; |
1371d904 AG |
3207 | } |
3208 | ||
851ba692 | 3209 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
3210 | { |
3211 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 3212 | |
668f198f DK |
3213 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX), |
3214 | kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); | |
ec1ff790 | 3215 | |
ff092385 | 3216 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
668f198f | 3217 | kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
ff092385 AG |
3218 | |
3219 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3220 | return kvm_skip_emulated_instruction(&svm->vcpu); |
ff092385 AG |
3221 | } |
3222 | ||
532a46b9 JR |
3223 | static int skinit_interception(struct vcpu_svm *svm) |
3224 | { | |
668f198f | 3225 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
532a46b9 JR |
3226 | |
3227 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3228 | return 1; | |
3229 | } | |
3230 | ||
dab429a7 DK |
3231 | static int wbinvd_interception(struct vcpu_svm *svm) |
3232 | { | |
6affcbed | 3233 | return kvm_emulate_wbinvd(&svm->vcpu); |
dab429a7 DK |
3234 | } |
3235 | ||
81dd35d4 JR |
3236 | static int xsetbv_interception(struct vcpu_svm *svm) |
3237 | { | |
3238 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
3239 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
3240 | ||
3241 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
3242 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3243 | return kvm_skip_emulated_instruction(&svm->vcpu); |
81dd35d4 JR |
3244 | } |
3245 | ||
3246 | return 1; | |
3247 | } | |
3248 | ||
851ba692 | 3249 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 3250 | { |
37817f29 | 3251 | u16 tss_selector; |
64a7ec06 GN |
3252 | int reason; |
3253 | int int_type = svm->vmcb->control.exit_int_info & | |
3254 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 3255 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
3256 | uint32_t type = |
3257 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
3258 | uint32_t idt_v = | |
3259 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
3260 | bool has_error_code = false; |
3261 | u32 error_code = 0; | |
37817f29 IE |
3262 | |
3263 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 3264 | |
37817f29 IE |
3265 | if (svm->vmcb->control.exit_info_2 & |
3266 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
3267 | reason = TASK_SWITCH_IRET; |
3268 | else if (svm->vmcb->control.exit_info_2 & | |
3269 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
3270 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 3271 | else if (idt_v) |
64a7ec06 GN |
3272 | reason = TASK_SWITCH_GATE; |
3273 | else | |
3274 | reason = TASK_SWITCH_CALL; | |
3275 | ||
fe8e7f83 GN |
3276 | if (reason == TASK_SWITCH_GATE) { |
3277 | switch (type) { | |
3278 | case SVM_EXITINTINFO_TYPE_NMI: | |
3279 | svm->vcpu.arch.nmi_injected = false; | |
3280 | break; | |
3281 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
3282 | if (svm->vmcb->control.exit_info_2 & |
3283 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
3284 | has_error_code = true; | |
3285 | error_code = | |
3286 | (u32)svm->vmcb->control.exit_info_2; | |
3287 | } | |
fe8e7f83 GN |
3288 | kvm_clear_exception_queue(&svm->vcpu); |
3289 | break; | |
3290 | case SVM_EXITINTINFO_TYPE_INTR: | |
3291 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3292 | break; | |
3293 | default: | |
3294 | break; | |
3295 | } | |
3296 | } | |
64a7ec06 | 3297 | |
8317c298 GN |
3298 | if (reason != TASK_SWITCH_GATE || |
3299 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
3300 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
3301 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
3302 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 3303 | |
7f3d35fd KW |
3304 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
3305 | int_vec = -1; | |
3306 | ||
3307 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
3308 | has_error_code, error_code) == EMULATE_FAIL) { |
3309 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3310 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3311 | svm->vcpu.run->internal.ndata = 0; | |
3312 | return 0; | |
3313 | } | |
3314 | return 1; | |
6aa8b732 AK |
3315 | } |
3316 | ||
851ba692 | 3317 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3318 | { |
5fdbf976 | 3319 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
6a908b62 | 3320 | return kvm_emulate_cpuid(&svm->vcpu); |
6aa8b732 AK |
3321 | } |
3322 | ||
851ba692 | 3323 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3324 | { |
3325 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3326 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3327 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3328 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3329 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3330 | return 1; |
3331 | } | |
3332 | ||
851ba692 | 3333 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3334 | { |
df4f3108 AP |
3335 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3336 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
3337 | ||
3338 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
b742c1e6 | 3339 | return kvm_skip_emulated_instruction(&svm->vcpu); |
a7052897 MT |
3340 | } |
3341 | ||
851ba692 | 3342 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3343 | { |
51d8b661 | 3344 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
3345 | } |
3346 | ||
332b56e4 AK |
3347 | static int rdpmc_interception(struct vcpu_svm *svm) |
3348 | { | |
3349 | int err; | |
3350 | ||
3351 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
3352 | return emulate_on_interception(svm); | |
3353 | ||
3354 | err = kvm_rdpmc(&svm->vcpu); | |
6affcbed | 3355 | return kvm_complete_insn_gp(&svm->vcpu, err); |
332b56e4 AK |
3356 | } |
3357 | ||
52eb5a6d XL |
3358 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3359 | unsigned long val) | |
628afd2a JR |
3360 | { |
3361 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3362 | bool ret = false; | |
3363 | u64 intercept; | |
3364 | ||
3365 | intercept = svm->nested.intercept; | |
3366 | ||
3367 | if (!is_guest_mode(&svm->vcpu) || | |
3368 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
3369 | return false; | |
3370 | ||
3371 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
3372 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
3373 | ||
3374 | if (cr0 ^ val) { | |
3375 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3376 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
3377 | } | |
3378 | ||
3379 | return ret; | |
3380 | } | |
3381 | ||
7ff76d58 AP |
3382 | #define CR_VALID (1ULL << 63) |
3383 | ||
3384 | static int cr_interception(struct vcpu_svm *svm) | |
3385 | { | |
3386 | int reg, cr; | |
3387 | unsigned long val; | |
3388 | int err; | |
3389 | ||
3390 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
3391 | return emulate_on_interception(svm); | |
3392 | ||
3393 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
3394 | return emulate_on_interception(svm); | |
3395 | ||
3396 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
3397 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
3398 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
3399 | else | |
3400 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
3401 | |
3402 | err = 0; | |
3403 | if (cr >= 16) { /* mov to cr */ | |
3404 | cr -= 16; | |
3405 | val = kvm_register_read(&svm->vcpu, reg); | |
3406 | switch (cr) { | |
3407 | case 0: | |
628afd2a JR |
3408 | if (!check_selective_cr0_intercepted(svm, val)) |
3409 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
3410 | else |
3411 | return 1; | |
3412 | ||
7ff76d58 AP |
3413 | break; |
3414 | case 3: | |
3415 | err = kvm_set_cr3(&svm->vcpu, val); | |
3416 | break; | |
3417 | case 4: | |
3418 | err = kvm_set_cr4(&svm->vcpu, val); | |
3419 | break; | |
3420 | case 8: | |
3421 | err = kvm_set_cr8(&svm->vcpu, val); | |
3422 | break; | |
3423 | default: | |
3424 | WARN(1, "unhandled write to CR%d", cr); | |
3425 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3426 | return 1; | |
3427 | } | |
3428 | } else { /* mov from cr */ | |
3429 | switch (cr) { | |
3430 | case 0: | |
3431 | val = kvm_read_cr0(&svm->vcpu); | |
3432 | break; | |
3433 | case 2: | |
3434 | val = svm->vcpu.arch.cr2; | |
3435 | break; | |
3436 | case 3: | |
9f8fe504 | 3437 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
3438 | break; |
3439 | case 4: | |
3440 | val = kvm_read_cr4(&svm->vcpu); | |
3441 | break; | |
3442 | case 8: | |
3443 | val = kvm_get_cr8(&svm->vcpu); | |
3444 | break; | |
3445 | default: | |
3446 | WARN(1, "unhandled read from CR%d", cr); | |
3447 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3448 | return 1; | |
3449 | } | |
3450 | kvm_register_write(&svm->vcpu, reg, val); | |
3451 | } | |
6affcbed | 3452 | return kvm_complete_insn_gp(&svm->vcpu, err); |
7ff76d58 AP |
3453 | } |
3454 | ||
cae3797a AP |
3455 | static int dr_interception(struct vcpu_svm *svm) |
3456 | { | |
3457 | int reg, dr; | |
3458 | unsigned long val; | |
cae3797a | 3459 | |
facb0139 PB |
3460 | if (svm->vcpu.guest_debug == 0) { |
3461 | /* | |
3462 | * No more DR vmexits; force a reload of the debug registers | |
3463 | * and reenter on this instruction. The next vmexit will | |
3464 | * retrieve the full state of the debug registers. | |
3465 | */ | |
3466 | clr_dr_intercepts(svm); | |
3467 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
3468 | return 1; | |
3469 | } | |
3470 | ||
cae3797a AP |
3471 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3472 | return emulate_on_interception(svm); | |
3473 | ||
3474 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
3475 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
3476 | ||
3477 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
3478 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
3479 | return 1; | |
cae3797a AP |
3480 | val = kvm_register_read(&svm->vcpu, reg); |
3481 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
3482 | } else { | |
16f8a6f9 NA |
3483 | if (!kvm_require_dr(&svm->vcpu, dr)) |
3484 | return 1; | |
3485 | kvm_get_dr(&svm->vcpu, dr, &val); | |
3486 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
3487 | } |
3488 | ||
b742c1e6 | 3489 | return kvm_skip_emulated_instruction(&svm->vcpu); |
cae3797a AP |
3490 | } |
3491 | ||
851ba692 | 3492 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 3493 | { |
851ba692 | 3494 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 3495 | int r; |
851ba692 | 3496 | |
0a5fff19 GN |
3497 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
3498 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 3499 | r = cr_interception(svm); |
35754c98 | 3500 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 3501 | return r; |
0a5fff19 | 3502 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3503 | return r; |
1d075434 JR |
3504 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3505 | return 0; | |
3506 | } | |
3507 | ||
609e36d3 | 3508 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3509 | { |
a2fa3e9f GH |
3510 | struct vcpu_svm *svm = to_svm(vcpu); |
3511 | ||
609e36d3 | 3512 | switch (msr_info->index) { |
af24a4e4 | 3513 | case MSR_IA32_TSC: { |
609e36d3 | 3514 | msr_info->data = svm->vmcb->control.tsc_offset + |
35181e86 | 3515 | kvm_scale_tsc(vcpu, rdtsc()); |
fbc0db76 | 3516 | |
6aa8b732 AK |
3517 | break; |
3518 | } | |
8c06585d | 3519 | case MSR_STAR: |
609e36d3 | 3520 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 3521 | break; |
0e859cac | 3522 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3523 | case MSR_LSTAR: |
609e36d3 | 3524 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3525 | break; |
3526 | case MSR_CSTAR: | |
609e36d3 | 3527 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3528 | break; |
3529 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 3530 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3531 | break; |
3532 | case MSR_SYSCALL_MASK: | |
609e36d3 | 3533 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3534 | break; |
3535 | #endif | |
3536 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3537 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3538 | break; |
3539 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3540 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
3541 | break; |
3542 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3543 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 3544 | break; |
46896c73 PB |
3545 | case MSR_TSC_AUX: |
3546 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3547 | return 1; | |
3548 | msr_info->data = svm->tsc_aux; | |
3549 | break; | |
e0231715 JR |
3550 | /* |
3551 | * Nobody will change the following 5 values in the VMCB so we can | |
3552 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3553 | * implemented. | |
3554 | */ | |
a2938c80 | 3555 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 3556 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
3557 | break; |
3558 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 3559 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
3560 | break; |
3561 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 3562 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
3563 | break; |
3564 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 3565 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
3566 | break; |
3567 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 3568 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 3569 | break; |
b286d5d8 | 3570 | case MSR_VM_HSAVE_PA: |
609e36d3 | 3571 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 3572 | break; |
eb6f302e | 3573 | case MSR_VM_CR: |
609e36d3 | 3574 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 3575 | break; |
c8a73f18 | 3576 | case MSR_IA32_UCODE_REV: |
609e36d3 | 3577 | msr_info->data = 0x01000065; |
c8a73f18 | 3578 | break; |
ae8b7875 BP |
3579 | case MSR_F15H_IC_CFG: { |
3580 | ||
3581 | int family, model; | |
3582 | ||
3583 | family = guest_cpuid_family(vcpu); | |
3584 | model = guest_cpuid_model(vcpu); | |
3585 | ||
3586 | if (family < 0 || model < 0) | |
3587 | return kvm_get_msr_common(vcpu, msr_info); | |
3588 | ||
3589 | msr_info->data = 0; | |
3590 | ||
3591 | if (family == 0x15 && | |
3592 | (model >= 0x2 && model < 0x20)) | |
3593 | msr_info->data = 0x1E; | |
3594 | } | |
3595 | break; | |
6aa8b732 | 3596 | default: |
609e36d3 | 3597 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3598 | } |
3599 | return 0; | |
3600 | } | |
3601 | ||
851ba692 | 3602 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3603 | { |
668f198f | 3604 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
609e36d3 | 3605 | struct msr_data msr_info; |
6aa8b732 | 3606 | |
609e36d3 PB |
3607 | msr_info.index = ecx; |
3608 | msr_info.host_initiated = false; | |
3609 | if (svm_get_msr(&svm->vcpu, &msr_info)) { | |
59200273 | 3610 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3611 | kvm_inject_gp(&svm->vcpu, 0); |
b742c1e6 | 3612 | return 1; |
59200273 | 3613 | } else { |
609e36d3 | 3614 | trace_kvm_msr_read(ecx, msr_info.data); |
af9ca2d7 | 3615 | |
609e36d3 PB |
3616 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, |
3617 | msr_info.data & 0xffffffff); | |
3618 | kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, | |
3619 | msr_info.data >> 32); | |
5fdbf976 | 3620 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
b742c1e6 | 3621 | return kvm_skip_emulated_instruction(&svm->vcpu); |
6aa8b732 | 3622 | } |
6aa8b732 AK |
3623 | } |
3624 | ||
4a810181 JR |
3625 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3626 | { | |
3627 | struct vcpu_svm *svm = to_svm(vcpu); | |
3628 | int svm_dis, chg_mask; | |
3629 | ||
3630 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3631 | return 1; | |
3632 | ||
3633 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3634 | ||
3635 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3636 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3637 | ||
3638 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3639 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3640 | ||
3641 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3642 | ||
3643 | /* check for svm_disable while efer.svme is set */ | |
3644 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3645 | return 1; | |
3646 | ||
3647 | return 0; | |
3648 | } | |
3649 | ||
8fe8ab46 | 3650 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3651 | { |
a2fa3e9f GH |
3652 | struct vcpu_svm *svm = to_svm(vcpu); |
3653 | ||
8fe8ab46 WA |
3654 | u32 ecx = msr->index; |
3655 | u64 data = msr->data; | |
6aa8b732 | 3656 | switch (ecx) { |
f4e1b3c8 | 3657 | case MSR_IA32_TSC: |
8fe8ab46 | 3658 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3659 | break; |
8c06585d | 3660 | case MSR_STAR: |
a2fa3e9f | 3661 | svm->vmcb->save.star = data; |
6aa8b732 | 3662 | break; |
49b14f24 | 3663 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3664 | case MSR_LSTAR: |
a2fa3e9f | 3665 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3666 | break; |
3667 | case MSR_CSTAR: | |
a2fa3e9f | 3668 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3669 | break; |
3670 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3671 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3672 | break; |
3673 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3674 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3675 | break; |
3676 | #endif | |
3677 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3678 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3679 | break; |
3680 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3681 | svm->sysenter_eip = data; |
a2fa3e9f | 3682 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3683 | break; |
3684 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3685 | svm->sysenter_esp = data; |
a2fa3e9f | 3686 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3687 | break; |
46896c73 PB |
3688 | case MSR_TSC_AUX: |
3689 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3690 | return 1; | |
3691 | ||
3692 | /* | |
3693 | * This is rare, so we update the MSR here instead of using | |
3694 | * direct_access_msrs. Doing that would require a rdmsr in | |
3695 | * svm_vcpu_put. | |
3696 | */ | |
3697 | svm->tsc_aux = data; | |
3698 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
3699 | break; | |
a2938c80 | 3700 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3701 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3702 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3703 | __func__, data); | |
24e09cbf JR |
3704 | break; |
3705 | } | |
3706 | if (data & DEBUGCTL_RESERVED_BITS) | |
3707 | return 1; | |
3708 | ||
3709 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3710 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3711 | if (data & (1ULL<<0)) |
3712 | svm_enable_lbrv(svm); | |
3713 | else | |
3714 | svm_disable_lbrv(svm); | |
a2938c80 | 3715 | break; |
b286d5d8 | 3716 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3717 | svm->nested.hsave_msr = data; |
62b9abaa | 3718 | break; |
3c5d0a44 | 3719 | case MSR_VM_CR: |
4a810181 | 3720 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3721 | case MSR_VM_IGNNE: |
a737f256 | 3722 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3723 | break; |
44a95dae SS |
3724 | case MSR_IA32_APICBASE: |
3725 | if (kvm_vcpu_apicv_active(vcpu)) | |
3726 | avic_update_vapic_bar(to_svm(vcpu), data); | |
3727 | /* Follow through */ | |
6aa8b732 | 3728 | default: |
8fe8ab46 | 3729 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3730 | } |
3731 | return 0; | |
3732 | } | |
3733 | ||
851ba692 | 3734 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3735 | { |
8fe8ab46 | 3736 | struct msr_data msr; |
668f198f DK |
3737 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
3738 | u64 data = kvm_read_edx_eax(&svm->vcpu); | |
af9ca2d7 | 3739 | |
8fe8ab46 WA |
3740 | msr.data = data; |
3741 | msr.index = ecx; | |
3742 | msr.host_initiated = false; | |
af9ca2d7 | 3743 | |
5fdbf976 | 3744 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
854e8bb1 | 3745 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3746 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3747 | kvm_inject_gp(&svm->vcpu, 0); |
b742c1e6 | 3748 | return 1; |
59200273 AK |
3749 | } else { |
3750 | trace_kvm_msr_write(ecx, data); | |
b742c1e6 | 3751 | return kvm_skip_emulated_instruction(&svm->vcpu); |
59200273 | 3752 | } |
6aa8b732 AK |
3753 | } |
3754 | ||
851ba692 | 3755 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3756 | { |
e756fc62 | 3757 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3758 | return wrmsr_interception(svm); |
6aa8b732 | 3759 | else |
851ba692 | 3760 | return rdmsr_interception(svm); |
6aa8b732 AK |
3761 | } |
3762 | ||
851ba692 | 3763 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3764 | { |
3842d135 | 3765 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3766 | svm_clear_vintr(svm); |
85f455f7 | 3767 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3768 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3769 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3770 | return 1; |
3771 | } | |
3772 | ||
565d0998 ML |
3773 | static int pause_interception(struct vcpu_svm *svm) |
3774 | { | |
de63ad4c LM |
3775 | struct kvm_vcpu *vcpu = &svm->vcpu; |
3776 | bool in_kernel = (svm_get_cpl(vcpu) == 0); | |
3777 | ||
3778 | kvm_vcpu_on_spin(vcpu, in_kernel); | |
565d0998 ML |
3779 | return 1; |
3780 | } | |
3781 | ||
87c00572 GS |
3782 | static int nop_interception(struct vcpu_svm *svm) |
3783 | { | |
b742c1e6 | 3784 | return kvm_skip_emulated_instruction(&(svm->vcpu)); |
87c00572 GS |
3785 | } |
3786 | ||
3787 | static int monitor_interception(struct vcpu_svm *svm) | |
3788 | { | |
3789 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
3790 | return nop_interception(svm); | |
3791 | } | |
3792 | ||
3793 | static int mwait_interception(struct vcpu_svm *svm) | |
3794 | { | |
3795 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
3796 | return nop_interception(svm); | |
3797 | } | |
3798 | ||
18f40c53 SS |
3799 | enum avic_ipi_failure_cause { |
3800 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
3801 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
3802 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
3803 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
3804 | }; | |
3805 | ||
3806 | static int avic_incomplete_ipi_interception(struct vcpu_svm *svm) | |
3807 | { | |
3808 | u32 icrh = svm->vmcb->control.exit_info_1 >> 32; | |
3809 | u32 icrl = svm->vmcb->control.exit_info_1; | |
3810 | u32 id = svm->vmcb->control.exit_info_2 >> 32; | |
5446a979 | 3811 | u32 index = svm->vmcb->control.exit_info_2 & 0xFF; |
18f40c53 SS |
3812 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
3813 | ||
3814 | trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); | |
3815 | ||
3816 | switch (id) { | |
3817 | case AVIC_IPI_FAILURE_INVALID_INT_TYPE: | |
3818 | /* | |
3819 | * AVIC hardware handles the generation of | |
3820 | * IPIs when the specified Message Type is Fixed | |
3821 | * (also known as fixed delivery mode) and | |
3822 | * the Trigger Mode is edge-triggered. The hardware | |
3823 | * also supports self and broadcast delivery modes | |
3824 | * specified via the Destination Shorthand(DSH) | |
3825 | * field of the ICRL. Logical and physical APIC ID | |
3826 | * formats are supported. All other IPI types cause | |
3827 | * a #VMEXIT, which needs to emulated. | |
3828 | */ | |
3829 | kvm_lapic_reg_write(apic, APIC_ICR2, icrh); | |
3830 | kvm_lapic_reg_write(apic, APIC_ICR, icrl); | |
3831 | break; | |
3832 | case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { | |
3833 | int i; | |
3834 | struct kvm_vcpu *vcpu; | |
3835 | struct kvm *kvm = svm->vcpu.kvm; | |
3836 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3837 | ||
3838 | /* | |
3839 | * At this point, we expect that the AVIC HW has already | |
3840 | * set the appropriate IRR bits on the valid target | |
3841 | * vcpus. So, we just need to kick the appropriate vcpu. | |
3842 | */ | |
3843 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
3844 | bool m = kvm_apic_match_dest(vcpu, apic, | |
3845 | icrl & KVM_APIC_SHORT_MASK, | |
3846 | GET_APIC_DEST_FIELD(icrh), | |
3847 | icrl & KVM_APIC_DEST_MASK); | |
3848 | ||
3849 | if (m && !avic_vcpu_is_running(vcpu)) | |
3850 | kvm_vcpu_wake_up(vcpu); | |
3851 | } | |
3852 | break; | |
3853 | } | |
3854 | case AVIC_IPI_FAILURE_INVALID_TARGET: | |
3855 | break; | |
3856 | case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: | |
3857 | WARN_ONCE(1, "Invalid backing page\n"); | |
3858 | break; | |
3859 | default: | |
3860 | pr_err("Unknown IPI interception\n"); | |
3861 | } | |
3862 | ||
3863 | return 1; | |
3864 | } | |
3865 | ||
3866 | static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) | |
3867 | { | |
3868 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
3869 | int index; | |
3870 | u32 *logical_apic_id_table; | |
3871 | int dlid = GET_APIC_LOGICAL_ID(ldr); | |
3872 | ||
3873 | if (!dlid) | |
3874 | return NULL; | |
3875 | ||
3876 | if (flat) { /* flat */ | |
3877 | index = ffs(dlid) - 1; | |
3878 | if (index > 7) | |
3879 | return NULL; | |
3880 | } else { /* cluster */ | |
3881 | int cluster = (dlid & 0xf0) >> 4; | |
3882 | int apic = ffs(dlid & 0x0f) - 1; | |
3883 | ||
3884 | if ((apic < 0) || (apic > 7) || | |
3885 | (cluster >= 0xf)) | |
3886 | return NULL; | |
3887 | index = (cluster << 2) + apic; | |
3888 | } | |
3889 | ||
3890 | logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page); | |
3891 | ||
3892 | return &logical_apic_id_table[index]; | |
3893 | } | |
3894 | ||
3895 | static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr, | |
3896 | bool valid) | |
3897 | { | |
3898 | bool flat; | |
3899 | u32 *entry, new_entry; | |
3900 | ||
3901 | flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; | |
3902 | entry = avic_get_logical_id_entry(vcpu, ldr, flat); | |
3903 | if (!entry) | |
3904 | return -EINVAL; | |
3905 | ||
3906 | new_entry = READ_ONCE(*entry); | |
3907 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; | |
3908 | new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); | |
3909 | if (valid) | |
3910 | new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3911 | else | |
3912 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3913 | WRITE_ONCE(*entry, new_entry); | |
3914 | ||
3915 | return 0; | |
3916 | } | |
3917 | ||
3918 | static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) | |
3919 | { | |
3920 | int ret; | |
3921 | struct vcpu_svm *svm = to_svm(vcpu); | |
3922 | u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); | |
3923 | ||
3924 | if (!ldr) | |
3925 | return 1; | |
3926 | ||
3927 | ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true); | |
3928 | if (ret && svm->ldr_reg) { | |
3929 | avic_ldr_write(vcpu, 0, svm->ldr_reg, false); | |
3930 | svm->ldr_reg = 0; | |
3931 | } else { | |
3932 | svm->ldr_reg = ldr; | |
3933 | } | |
3934 | return ret; | |
3935 | } | |
3936 | ||
3937 | static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) | |
3938 | { | |
3939 | u64 *old, *new; | |
3940 | struct vcpu_svm *svm = to_svm(vcpu); | |
3941 | u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID); | |
3942 | u32 id = (apic_id_reg >> 24) & 0xff; | |
3943 | ||
3944 | if (vcpu->vcpu_id == id) | |
3945 | return 0; | |
3946 | ||
3947 | old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); | |
3948 | new = avic_get_physical_id_entry(vcpu, id); | |
3949 | if (!new || !old) | |
3950 | return 1; | |
3951 | ||
3952 | /* We need to move physical_id_entry to new offset */ | |
3953 | *new = *old; | |
3954 | *old = 0ULL; | |
3955 | to_svm(vcpu)->avic_physical_id_cache = new; | |
3956 | ||
3957 | /* | |
3958 | * Also update the guest physical APIC ID in the logical | |
3959 | * APIC ID table entry if already setup the LDR. | |
3960 | */ | |
3961 | if (svm->ldr_reg) | |
3962 | avic_handle_ldr_update(vcpu); | |
3963 | ||
3964 | return 0; | |
3965 | } | |
3966 | ||
3967 | static int avic_handle_dfr_update(struct kvm_vcpu *vcpu) | |
3968 | { | |
3969 | struct vcpu_svm *svm = to_svm(vcpu); | |
3970 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
3971 | u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); | |
3972 | u32 mod = (dfr >> 28) & 0xf; | |
3973 | ||
3974 | /* | |
3975 | * We assume that all local APICs are using the same type. | |
3976 | * If this changes, we need to flush the AVIC logical | |
3977 | * APID id table. | |
3978 | */ | |
3979 | if (vm_data->ldr_mode == mod) | |
3980 | return 0; | |
3981 | ||
3982 | clear_page(page_address(vm_data->avic_logical_id_table_page)); | |
3983 | vm_data->ldr_mode = mod; | |
3984 | ||
3985 | if (svm->ldr_reg) | |
3986 | avic_handle_ldr_update(vcpu); | |
3987 | return 0; | |
3988 | } | |
3989 | ||
3990 | static int avic_unaccel_trap_write(struct vcpu_svm *svm) | |
3991 | { | |
3992 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3993 | u32 offset = svm->vmcb->control.exit_info_1 & | |
3994 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
3995 | ||
3996 | switch (offset) { | |
3997 | case APIC_ID: | |
3998 | if (avic_handle_apic_id_update(&svm->vcpu)) | |
3999 | return 0; | |
4000 | break; | |
4001 | case APIC_LDR: | |
4002 | if (avic_handle_ldr_update(&svm->vcpu)) | |
4003 | return 0; | |
4004 | break; | |
4005 | case APIC_DFR: | |
4006 | avic_handle_dfr_update(&svm->vcpu); | |
4007 | break; | |
4008 | default: | |
4009 | break; | |
4010 | } | |
4011 | ||
4012 | kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); | |
4013 | ||
4014 | return 1; | |
4015 | } | |
4016 | ||
4017 | static bool is_avic_unaccelerated_access_trap(u32 offset) | |
4018 | { | |
4019 | bool ret = false; | |
4020 | ||
4021 | switch (offset) { | |
4022 | case APIC_ID: | |
4023 | case APIC_EOI: | |
4024 | case APIC_RRR: | |
4025 | case APIC_LDR: | |
4026 | case APIC_DFR: | |
4027 | case APIC_SPIV: | |
4028 | case APIC_ESR: | |
4029 | case APIC_ICR: | |
4030 | case APIC_LVTT: | |
4031 | case APIC_LVTTHMR: | |
4032 | case APIC_LVTPC: | |
4033 | case APIC_LVT0: | |
4034 | case APIC_LVT1: | |
4035 | case APIC_LVTERR: | |
4036 | case APIC_TMICT: | |
4037 | case APIC_TDCR: | |
4038 | ret = true; | |
4039 | break; | |
4040 | default: | |
4041 | break; | |
4042 | } | |
4043 | return ret; | |
4044 | } | |
4045 | ||
4046 | static int avic_unaccelerated_access_interception(struct vcpu_svm *svm) | |
4047 | { | |
4048 | int ret = 0; | |
4049 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4050 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4051 | u32 vector = svm->vmcb->control.exit_info_2 & | |
4052 | AVIC_UNACCEL_ACCESS_VECTOR_MASK; | |
4053 | bool write = (svm->vmcb->control.exit_info_1 >> 32) & | |
4054 | AVIC_UNACCEL_ACCESS_WRITE_MASK; | |
4055 | bool trap = is_avic_unaccelerated_access_trap(offset); | |
4056 | ||
4057 | trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, | |
4058 | trap, write, vector); | |
4059 | if (trap) { | |
4060 | /* Handling Trap */ | |
4061 | WARN_ONCE(!write, "svm: Handling trap read.\n"); | |
4062 | ret = avic_unaccel_trap_write(svm); | |
4063 | } else { | |
4064 | /* Handling Fault */ | |
4065 | ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE); | |
4066 | } | |
4067 | ||
4068 | return ret; | |
4069 | } | |
4070 | ||
09941fbb | 4071 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
4072 | [SVM_EXIT_READ_CR0] = cr_interception, |
4073 | [SVM_EXIT_READ_CR3] = cr_interception, | |
4074 | [SVM_EXIT_READ_CR4] = cr_interception, | |
4075 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 4076 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 4077 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
4078 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
4079 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 4080 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
4081 | [SVM_EXIT_READ_DR0] = dr_interception, |
4082 | [SVM_EXIT_READ_DR1] = dr_interception, | |
4083 | [SVM_EXIT_READ_DR2] = dr_interception, | |
4084 | [SVM_EXIT_READ_DR3] = dr_interception, | |
4085 | [SVM_EXIT_READ_DR4] = dr_interception, | |
4086 | [SVM_EXIT_READ_DR5] = dr_interception, | |
4087 | [SVM_EXIT_READ_DR6] = dr_interception, | |
4088 | [SVM_EXIT_READ_DR7] = dr_interception, | |
4089 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
4090 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
4091 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
4092 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
4093 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
4094 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
4095 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
4096 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
4097 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
4098 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 4099 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 | 4100 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
e0231715 | 4101 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
54a20552 | 4102 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
e0231715 | 4103 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 4104 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
4105 | [SVM_EXIT_SMI] = nop_on_interception, |
4106 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 4107 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 4108 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 4109 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 4110 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 4111 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 4112 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 4113 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 4114 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 4115 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 4116 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
4117 | [SVM_EXIT_MSR] = msr_interception, |
4118 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 4119 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 4120 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 4121 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
4122 | [SVM_EXIT_VMLOAD] = vmload_interception, |
4123 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
4124 | [SVM_EXIT_STGI] = stgi_interception, |
4125 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 4126 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 4127 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
4128 | [SVM_EXIT_MONITOR] = monitor_interception, |
4129 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 4130 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 4131 | [SVM_EXIT_NPF] = pf_interception, |
64d60670 | 4132 | [SVM_EXIT_RSM] = emulate_on_interception, |
18f40c53 SS |
4133 | [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, |
4134 | [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, | |
6aa8b732 AK |
4135 | }; |
4136 | ||
ae8cc059 | 4137 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
4138 | { |
4139 | struct vcpu_svm *svm = to_svm(vcpu); | |
4140 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4141 | struct vmcb_save_area *save = &svm->vmcb->save; | |
4142 | ||
4143 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
4144 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
4145 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
4146 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
4147 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
4148 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
4149 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
4150 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
4151 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
4152 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
4153 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
4154 | pr_err("%-20s%d\n", "asid:", control->asid); | |
4155 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
4156 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
4157 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
4158 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
4159 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
4160 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
4161 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
4162 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
4163 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
4164 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
4165 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 4166 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
4167 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
4168 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
0dc92119 | 4169 | pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext); |
ae8cc059 | 4170 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); |
44a95dae SS |
4171 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
4172 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
4173 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 4174 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
4175 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
4176 | "es:", | |
4177 | save->es.selector, save->es.attrib, | |
4178 | save->es.limit, save->es.base); | |
4179 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4180 | "cs:", | |
4181 | save->cs.selector, save->cs.attrib, | |
4182 | save->cs.limit, save->cs.base); | |
4183 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4184 | "ss:", | |
4185 | save->ss.selector, save->ss.attrib, | |
4186 | save->ss.limit, save->ss.base); | |
4187 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4188 | "ds:", | |
4189 | save->ds.selector, save->ds.attrib, | |
4190 | save->ds.limit, save->ds.base); | |
4191 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4192 | "fs:", | |
4193 | save->fs.selector, save->fs.attrib, | |
4194 | save->fs.limit, save->fs.base); | |
4195 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4196 | "gs:", | |
4197 | save->gs.selector, save->gs.attrib, | |
4198 | save->gs.limit, save->gs.base); | |
4199 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4200 | "gdtr:", | |
4201 | save->gdtr.selector, save->gdtr.attrib, | |
4202 | save->gdtr.limit, save->gdtr.base); | |
4203 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4204 | "ldtr:", | |
4205 | save->ldtr.selector, save->ldtr.attrib, | |
4206 | save->ldtr.limit, save->ldtr.base); | |
4207 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4208 | "idtr:", | |
4209 | save->idtr.selector, save->idtr.attrib, | |
4210 | save->idtr.limit, save->idtr.base); | |
4211 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4212 | "tr:", | |
4213 | save->tr.selector, save->tr.attrib, | |
4214 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
4215 | pr_err("cpl: %d efer: %016llx\n", |
4216 | save->cpl, save->efer); | |
ae8cc059 JP |
4217 | pr_err("%-15s %016llx %-13s %016llx\n", |
4218 | "cr0:", save->cr0, "cr2:", save->cr2); | |
4219 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4220 | "cr3:", save->cr3, "cr4:", save->cr4); | |
4221 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4222 | "dr6:", save->dr6, "dr7:", save->dr7); | |
4223 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4224 | "rip:", save->rip, "rflags:", save->rflags); | |
4225 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4226 | "rsp:", save->rsp, "rax:", save->rax); | |
4227 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4228 | "star:", save->star, "lstar:", save->lstar); | |
4229 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4230 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
4231 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4232 | "kernel_gs_base:", save->kernel_gs_base, | |
4233 | "sysenter_cs:", save->sysenter_cs); | |
4234 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4235 | "sysenter_esp:", save->sysenter_esp, | |
4236 | "sysenter_eip:", save->sysenter_eip); | |
4237 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4238 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
4239 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4240 | "br_from:", save->br_from, "br_to:", save->br_to); | |
4241 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4242 | "excp_from:", save->last_excp_from, | |
4243 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
4244 | } |
4245 | ||
586f9607 AK |
4246 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
4247 | { | |
4248 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
4249 | ||
4250 | *info1 = control->exit_info_1; | |
4251 | *info2 = control->exit_info_2; | |
4252 | } | |
4253 | ||
851ba692 | 4254 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 4255 | { |
04d2cc77 | 4256 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 4257 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 4258 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 4259 | |
8b89fe1f PB |
4260 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
4261 | ||
4ee546b4 | 4262 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
4263 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
4264 | if (npt_enabled) | |
4265 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 4266 | |
cd3ff653 JR |
4267 | if (unlikely(svm->nested.exit_required)) { |
4268 | nested_svm_vmexit(svm); | |
4269 | svm->nested.exit_required = false; | |
4270 | ||
4271 | return 1; | |
4272 | } | |
4273 | ||
2030753d | 4274 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
4275 | int vmexit; |
4276 | ||
d8cabddf JR |
4277 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
4278 | svm->vmcb->control.exit_info_1, | |
4279 | svm->vmcb->control.exit_info_2, | |
4280 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
4281 | svm->vmcb->control.exit_int_info_err, |
4282 | KVM_ISA_SVM); | |
d8cabddf | 4283 | |
410e4d57 JR |
4284 | vmexit = nested_svm_exit_special(svm); |
4285 | ||
4286 | if (vmexit == NESTED_EXIT_CONTINUE) | |
4287 | vmexit = nested_svm_exit_handled(svm); | |
4288 | ||
4289 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 4290 | return 1; |
cf74a78b AG |
4291 | } |
4292 | ||
a5c3832d JR |
4293 | svm_complete_interrupts(svm); |
4294 | ||
04d2cc77 AK |
4295 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
4296 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
4297 | kvm_run->fail_entry.hardware_entry_failure_reason | |
4298 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
4299 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
4300 | dump_vmcb(vcpu); | |
04d2cc77 AK |
4301 | return 0; |
4302 | } | |
4303 | ||
a2fa3e9f | 4304 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 4305 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
4306 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
4307 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 4308 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 4309 | "exit_code 0x%x\n", |
b8688d51 | 4310 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
4311 | exit_code); |
4312 | ||
9d8f549d | 4313 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 4314 | || !svm_exit_handlers[exit_code]) { |
faac2458 | 4315 | WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code); |
2bc19dc3 MT |
4316 | kvm_queue_exception(vcpu, UD_VECTOR); |
4317 | return 1; | |
6aa8b732 AK |
4318 | } |
4319 | ||
851ba692 | 4320 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
4321 | } |
4322 | ||
4323 | static void reload_tss(struct kvm_vcpu *vcpu) | |
4324 | { | |
4325 | int cpu = raw_smp_processor_id(); | |
4326 | ||
0fe1e009 TH |
4327 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
4328 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
4329 | load_TR_desc(); |
4330 | } | |
4331 | ||
e756fc62 | 4332 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
4333 | { |
4334 | int cpu = raw_smp_processor_id(); | |
4335 | ||
0fe1e009 | 4336 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 4337 | |
4b656b12 | 4338 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
4339 | if (svm->asid_generation != sd->asid_generation) |
4340 | new_asid(svm, sd); | |
6aa8b732 AK |
4341 | } |
4342 | ||
95ba8273 GN |
4343 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
4344 | { | |
4345 | struct vcpu_svm *svm = to_svm(vcpu); | |
4346 | ||
4347 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
4348 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4349 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
4350 | ++vcpu->stat.nmi_injections; |
4351 | } | |
6aa8b732 | 4352 | |
85f455f7 | 4353 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
4354 | { |
4355 | struct vmcb_control_area *control; | |
4356 | ||
340d3bc3 | 4357 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 4358 | control = &svm->vmcb->control; |
85f455f7 | 4359 | control->int_vector = irq; |
6aa8b732 AK |
4360 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
4361 | control->int_ctl |= V_IRQ_MASK | | |
4362 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 4363 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
4364 | } |
4365 | ||
66fd3f7f | 4366 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
4367 | { |
4368 | struct vcpu_svm *svm = to_svm(vcpu); | |
4369 | ||
2af9194d | 4370 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 4371 | |
9fb2d2b4 GN |
4372 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
4373 | ++vcpu->stat.irq_injections; | |
4374 | ||
219b65dc AG |
4375 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
4376 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
4377 | } |
4378 | ||
3bbf3565 SS |
4379 | static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu) |
4380 | { | |
4381 | return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK); | |
4382 | } | |
4383 | ||
95ba8273 | 4384 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
4385 | { |
4386 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 4387 | |
3bbf3565 SS |
4388 | if (svm_nested_virtualize_tpr(vcpu) || |
4389 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4390 | return; |
4391 | ||
596f3142 RK |
4392 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
4393 | ||
95ba8273 | 4394 | if (irr == -1) |
aaacfc9a JR |
4395 | return; |
4396 | ||
95ba8273 | 4397 | if (tpr >= irr) |
4ee546b4 | 4398 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 4399 | } |
aaacfc9a | 4400 | |
8d14695f YZ |
4401 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
4402 | { | |
4403 | return; | |
4404 | } | |
4405 | ||
b2a05fef | 4406 | static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu) |
d62caabb | 4407 | { |
67034bb9 | 4408 | return avic && irqchip_split(vcpu->kvm); |
44a95dae SS |
4409 | } |
4410 | ||
4411 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
4412 | { | |
d62caabb AS |
4413 | } |
4414 | ||
67c9dddc | 4415 | static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
44a95dae | 4416 | { |
d62caabb AS |
4417 | } |
4418 | ||
44a95dae | 4419 | /* Note: Currently only used by Hyper-V. */ |
d62caabb | 4420 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 4421 | { |
44a95dae SS |
4422 | struct vcpu_svm *svm = to_svm(vcpu); |
4423 | struct vmcb *vmcb = svm->vmcb; | |
4424 | ||
67034bb9 | 4425 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
4426 | return; |
4427 | ||
4428 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
4429 | mark_dirty(vmcb, VMCB_INTR); | |
c7c9c56c YZ |
4430 | } |
4431 | ||
6308630b | 4432 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
4433 | { |
4434 | return; | |
4435 | } | |
4436 | ||
340d3bc3 SS |
4437 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
4438 | { | |
4439 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
4440 | smp_mb__after_atomic(); | |
4441 | ||
4442 | if (avic_vcpu_is_running(vcpu)) | |
4443 | wrmsrl(SVM_AVIC_DOORBELL, | |
7d669f50 | 4444 | kvm_cpu_get_apicid(vcpu->cpu)); |
340d3bc3 SS |
4445 | else |
4446 | kvm_vcpu_wake_up(vcpu); | |
4447 | } | |
4448 | ||
411b44ba SS |
4449 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) |
4450 | { | |
4451 | unsigned long flags; | |
4452 | struct amd_svm_iommu_ir *cur; | |
4453 | ||
4454 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4455 | list_for_each_entry(cur, &svm->ir_list, node) { | |
4456 | if (cur->data != pi->ir_data) | |
4457 | continue; | |
4458 | list_del(&cur->node); | |
4459 | kfree(cur); | |
4460 | break; | |
4461 | } | |
4462 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4463 | } | |
4464 | ||
4465 | static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) | |
4466 | { | |
4467 | int ret = 0; | |
4468 | unsigned long flags; | |
4469 | struct amd_svm_iommu_ir *ir; | |
4470 | ||
4471 | /** | |
4472 | * In some cases, the existing irte is updaed and re-set, | |
4473 | * so we need to check here if it's already been * added | |
4474 | * to the ir_list. | |
4475 | */ | |
4476 | if (pi->ir_data && (pi->prev_ga_tag != 0)) { | |
4477 | struct kvm *kvm = svm->vcpu.kvm; | |
4478 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); | |
4479 | struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
4480 | struct vcpu_svm *prev_svm; | |
4481 | ||
4482 | if (!prev_vcpu) { | |
4483 | ret = -EINVAL; | |
4484 | goto out; | |
4485 | } | |
4486 | ||
4487 | prev_svm = to_svm(prev_vcpu); | |
4488 | svm_ir_list_del(prev_svm, pi); | |
4489 | } | |
4490 | ||
4491 | /** | |
4492 | * Allocating new amd_iommu_pi_data, which will get | |
4493 | * add to the per-vcpu ir_list. | |
4494 | */ | |
4495 | ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL); | |
4496 | if (!ir) { | |
4497 | ret = -ENOMEM; | |
4498 | goto out; | |
4499 | } | |
4500 | ir->data = pi->ir_data; | |
4501 | ||
4502 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4503 | list_add(&ir->node, &svm->ir_list); | |
4504 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4505 | out: | |
4506 | return ret; | |
4507 | } | |
4508 | ||
4509 | /** | |
4510 | * Note: | |
4511 | * The HW cannot support posting multicast/broadcast | |
4512 | * interrupts to a vCPU. So, we still use legacy interrupt | |
4513 | * remapping for these kind of interrupts. | |
4514 | * | |
4515 | * For lowest-priority interrupts, we only support | |
4516 | * those with single CPU as the destination, e.g. user | |
4517 | * configures the interrupts via /proc/irq or uses | |
4518 | * irqbalance to make the interrupts single-CPU. | |
4519 | */ | |
4520 | static int | |
4521 | get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, | |
4522 | struct vcpu_data *vcpu_info, struct vcpu_svm **svm) | |
4523 | { | |
4524 | struct kvm_lapic_irq irq; | |
4525 | struct kvm_vcpu *vcpu = NULL; | |
4526 | ||
4527 | kvm_set_msi_irq(kvm, e, &irq); | |
4528 | ||
4529 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { | |
4530 | pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", | |
4531 | __func__, irq.vector); | |
4532 | return -1; | |
4533 | } | |
4534 | ||
4535 | pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, | |
4536 | irq.vector); | |
4537 | *svm = to_svm(vcpu); | |
d0ec49d4 | 4538 | vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page)); |
411b44ba SS |
4539 | vcpu_info->vector = irq.vector; |
4540 | ||
4541 | return 0; | |
4542 | } | |
4543 | ||
4544 | /* | |
4545 | * svm_update_pi_irte - set IRTE for Posted-Interrupts | |
4546 | * | |
4547 | * @kvm: kvm | |
4548 | * @host_irq: host irq of the interrupt | |
4549 | * @guest_irq: gsi of the interrupt | |
4550 | * @set: set or unset PI | |
4551 | * returns 0 on success, < 0 on failure | |
4552 | */ | |
4553 | static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
4554 | uint32_t guest_irq, bool set) | |
4555 | { | |
4556 | struct kvm_kernel_irq_routing_entry *e; | |
4557 | struct kvm_irq_routing_table *irq_rt; | |
4558 | int idx, ret = -EINVAL; | |
4559 | ||
4560 | if (!kvm_arch_has_assigned_device(kvm) || | |
4561 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
4562 | return 0; | |
4563 | ||
4564 | pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n", | |
4565 | __func__, host_irq, guest_irq, set); | |
4566 | ||
4567 | idx = srcu_read_lock(&kvm->irq_srcu); | |
4568 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
4569 | WARN_ON(guest_irq >= irq_rt->nr_rt_entries); | |
4570 | ||
4571 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
4572 | struct vcpu_data vcpu_info; | |
4573 | struct vcpu_svm *svm = NULL; | |
4574 | ||
4575 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
4576 | continue; | |
4577 | ||
4578 | /** | |
4579 | * Here, we setup with legacy mode in the following cases: | |
4580 | * 1. When cannot target interrupt to a specific vcpu. | |
4581 | * 2. Unsetting posted interrupt. | |
4582 | * 3. APIC virtialization is disabled for the vcpu. | |
4583 | */ | |
4584 | if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && | |
4585 | kvm_vcpu_apicv_active(&svm->vcpu)) { | |
4586 | struct amd_iommu_pi_data pi; | |
4587 | ||
4588 | /* Try to enable guest_mode in IRTE */ | |
d0ec49d4 TL |
4589 | pi.base = __sme_set(page_to_phys(svm->avic_backing_page) & |
4590 | AVIC_HPA_MASK); | |
411b44ba SS |
4591 | pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id, |
4592 | svm->vcpu.vcpu_id); | |
4593 | pi.is_guest_mode = true; | |
4594 | pi.vcpu_data = &vcpu_info; | |
4595 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4596 | ||
4597 | /** | |
4598 | * Here, we successfully setting up vcpu affinity in | |
4599 | * IOMMU guest mode. Now, we need to store the posted | |
4600 | * interrupt information in a per-vcpu ir_list so that | |
4601 | * we can reference to them directly when we update vcpu | |
4602 | * scheduling information in IOMMU irte. | |
4603 | */ | |
4604 | if (!ret && pi.is_guest_mode) | |
4605 | svm_ir_list_add(svm, &pi); | |
4606 | } else { | |
4607 | /* Use legacy mode in IRTE */ | |
4608 | struct amd_iommu_pi_data pi; | |
4609 | ||
4610 | /** | |
4611 | * Here, pi is used to: | |
4612 | * - Tell IOMMU to use legacy mode for this interrupt. | |
4613 | * - Retrieve ga_tag of prior interrupt remapping data. | |
4614 | */ | |
4615 | pi.is_guest_mode = false; | |
4616 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4617 | ||
4618 | /** | |
4619 | * Check if the posted interrupt was previously | |
4620 | * setup with the guest_mode by checking if the ga_tag | |
4621 | * was cached. If so, we need to clean up the per-vcpu | |
4622 | * ir_list. | |
4623 | */ | |
4624 | if (!ret && pi.prev_ga_tag) { | |
4625 | int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); | |
4626 | struct kvm_vcpu *vcpu; | |
4627 | ||
4628 | vcpu = kvm_get_vcpu_by_id(kvm, id); | |
4629 | if (vcpu) | |
4630 | svm_ir_list_del(to_svm(vcpu), &pi); | |
4631 | } | |
4632 | } | |
4633 | ||
4634 | if (!ret && svm) { | |
4635 | trace_kvm_pi_irte_update(svm->vcpu.vcpu_id, | |
4636 | host_irq, e->gsi, | |
4637 | vcpu_info.vector, | |
4638 | vcpu_info.pi_desc_addr, set); | |
4639 | } | |
4640 | ||
4641 | if (ret < 0) { | |
4642 | pr_err("%s: failed to update PI IRTE\n", __func__); | |
4643 | goto out; | |
4644 | } | |
4645 | } | |
4646 | ||
4647 | ret = 0; | |
4648 | out: | |
4649 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
4650 | return ret; | |
4651 | } | |
4652 | ||
95ba8273 GN |
4653 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
4654 | { | |
4655 | struct vcpu_svm *svm = to_svm(vcpu); | |
4656 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
4657 | int ret; |
4658 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
4659 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4660 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
4661 | ||
4662 | return ret; | |
aaacfc9a JR |
4663 | } |
4664 | ||
3cfc3092 JK |
4665 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
4666 | { | |
4667 | struct vcpu_svm *svm = to_svm(vcpu); | |
4668 | ||
4669 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4670 | } | |
4671 | ||
4672 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
4673 | { | |
4674 | struct vcpu_svm *svm = to_svm(vcpu); | |
4675 | ||
4676 | if (masked) { | |
4677 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4678 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4679 | } else { |
4680 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 4681 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4682 | } |
4683 | } | |
4684 | ||
78646121 GN |
4685 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
4686 | { | |
4687 | struct vcpu_svm *svm = to_svm(vcpu); | |
4688 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
4689 | int ret; |
4690 | ||
4691 | if (!gif_set(svm) || | |
4692 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
4693 | return 0; | |
4694 | ||
f6e78475 | 4695 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 4696 | |
2030753d | 4697 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
4698 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
4699 | ||
4700 | return ret; | |
78646121 GN |
4701 | } |
4702 | ||
c9a7953f | 4703 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 4704 | { |
219b65dc | 4705 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 4706 | |
340d3bc3 SS |
4707 | if (kvm_vcpu_apicv_active(vcpu)) |
4708 | return; | |
4709 | ||
e0231715 JR |
4710 | /* |
4711 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
4712 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
4713 | * get that intercept, this function will be called again though and | |
640bd6e5 JN |
4714 | * we'll get the vintr intercept. However, if the vGIF feature is |
4715 | * enabled, the STGI interception will not occur. Enable the irq | |
4716 | * window under the assumption that the hardware will set the GIF. | |
e0231715 | 4717 | */ |
640bd6e5 | 4718 | if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) { |
219b65dc AG |
4719 | svm_set_vintr(svm); |
4720 | svm_inject_irq(svm, 0x0); | |
4721 | } | |
85f455f7 ED |
4722 | } |
4723 | ||
c9a7953f | 4724 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 4725 | { |
04d2cc77 | 4726 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 4727 | |
44c11430 GN |
4728 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
4729 | == HF_NMI_MASK) | |
c9a7953f | 4730 | return; /* IRET will cause a vm exit */ |
44c11430 | 4731 | |
640bd6e5 JN |
4732 | if (!gif_set(svm)) { |
4733 | if (vgif_enabled(svm)) | |
4734 | set_intercept(svm, INTERCEPT_STGI); | |
1a5e1852 | 4735 | return; /* STGI will cause a vm exit */ |
640bd6e5 | 4736 | } |
1a5e1852 LP |
4737 | |
4738 | if (svm->nested.exit_required) | |
4739 | return; /* we're not going to run the guest yet */ | |
4740 | ||
e0231715 JR |
4741 | /* |
4742 | * Something prevents NMI from been injected. Single step over possible | |
4743 | * problem (IRET or exception injection or interrupt shadow) | |
4744 | */ | |
ab2f4d73 | 4745 | svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu); |
6be7d306 | 4746 | svm->nmi_singlestep = true; |
44c11430 | 4747 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
4748 | } |
4749 | ||
cbc94022 IE |
4750 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
4751 | { | |
4752 | return 0; | |
4753 | } | |
4754 | ||
d9e368d6 AK |
4755 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
4756 | { | |
38e5e92f JR |
4757 | struct vcpu_svm *svm = to_svm(vcpu); |
4758 | ||
4759 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
4760 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
4761 | else | |
4762 | svm->asid_generation--; | |
d9e368d6 AK |
4763 | } |
4764 | ||
04d2cc77 AK |
4765 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
4766 | { | |
4767 | } | |
4768 | ||
d7bf8221 JR |
4769 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
4770 | { | |
4771 | struct vcpu_svm *svm = to_svm(vcpu); | |
4772 | ||
3bbf3565 | 4773 | if (svm_nested_virtualize_tpr(vcpu)) |
88ab24ad JR |
4774 | return; |
4775 | ||
4ee546b4 | 4776 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 4777 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 4778 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
4779 | } |
4780 | } | |
4781 | ||
649d6864 JR |
4782 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
4783 | { | |
4784 | struct vcpu_svm *svm = to_svm(vcpu); | |
4785 | u64 cr8; | |
4786 | ||
3bbf3565 SS |
4787 | if (svm_nested_virtualize_tpr(vcpu) || |
4788 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4789 | return; |
4790 | ||
649d6864 JR |
4791 | cr8 = kvm_get_cr8(vcpu); |
4792 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
4793 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
4794 | } | |
4795 | ||
9222be18 GN |
4796 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
4797 | { | |
4798 | u8 vector; | |
4799 | int type; | |
4800 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
4801 | unsigned int3_injected = svm->int3_injected; |
4802 | ||
4803 | svm->int3_injected = 0; | |
9222be18 | 4804 | |
bd3d1ec3 AK |
4805 | /* |
4806 | * If we've made progress since setting HF_IRET_MASK, we've | |
4807 | * executed an IRET and can allow NMI injection. | |
4808 | */ | |
4809 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
4810 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 4811 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
4812 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4813 | } | |
44c11430 | 4814 | |
9222be18 GN |
4815 | svm->vcpu.arch.nmi_injected = false; |
4816 | kvm_clear_exception_queue(&svm->vcpu); | |
4817 | kvm_clear_interrupt_queue(&svm->vcpu); | |
4818 | ||
4819 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
4820 | return; | |
4821 | ||
3842d135 AK |
4822 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4823 | ||
9222be18 GN |
4824 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
4825 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
4826 | ||
4827 | switch (type) { | |
4828 | case SVM_EXITINTINFO_TYPE_NMI: | |
4829 | svm->vcpu.arch.nmi_injected = true; | |
4830 | break; | |
4831 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
4832 | /* |
4833 | * In case of software exceptions, do not reinject the vector, | |
4834 | * but re-execute the instruction instead. Rewind RIP first | |
4835 | * if we emulated INT3 before. | |
4836 | */ | |
4837 | if (kvm_exception_is_soft(vector)) { | |
4838 | if (vector == BP_VECTOR && int3_injected && | |
4839 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
4840 | kvm_rip_write(&svm->vcpu, | |
4841 | kvm_rip_read(&svm->vcpu) - | |
4842 | int3_injected); | |
9222be18 | 4843 | break; |
66b7138f | 4844 | } |
9222be18 GN |
4845 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
4846 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 4847 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
4848 | |
4849 | } else | |
ce7ddec4 | 4850 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
4851 | break; |
4852 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 4853 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
4854 | break; |
4855 | default: | |
4856 | break; | |
4857 | } | |
4858 | } | |
4859 | ||
b463a6f7 AK |
4860 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
4861 | { | |
4862 | struct vcpu_svm *svm = to_svm(vcpu); | |
4863 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4864 | ||
4865 | control->exit_int_info = control->event_inj; | |
4866 | control->exit_int_info_err = control->event_inj_err; | |
4867 | control->event_inj = 0; | |
4868 | svm_complete_interrupts(svm); | |
4869 | } | |
4870 | ||
851ba692 | 4871 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 4872 | { |
a2fa3e9f | 4873 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 4874 | |
2041a06a JR |
4875 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
4876 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
4877 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
4878 | ||
cd3ff653 JR |
4879 | /* |
4880 | * A vmexit emulation is required before the vcpu can be executed | |
4881 | * again. | |
4882 | */ | |
4883 | if (unlikely(svm->nested.exit_required)) | |
4884 | return; | |
4885 | ||
a12713c2 LP |
4886 | /* |
4887 | * Disable singlestep if we're injecting an interrupt/exception. | |
4888 | * We don't want our modified rflags to be pushed on the stack where | |
4889 | * we might not be able to easily reset them if we disabled NMI | |
4890 | * singlestep later. | |
4891 | */ | |
4892 | if (svm->nmi_singlestep && svm->vmcb->control.event_inj) { | |
4893 | /* | |
4894 | * Event injection happens before external interrupts cause a | |
4895 | * vmexit and interrupts are disabled here, so smp_send_reschedule | |
4896 | * is enough to force an immediate vmexit. | |
4897 | */ | |
4898 | disable_nmi_singlestep(svm); | |
4899 | smp_send_reschedule(vcpu->cpu); | |
4900 | } | |
4901 | ||
e756fc62 | 4902 | pre_svm_run(svm); |
6aa8b732 | 4903 | |
649d6864 JR |
4904 | sync_lapic_to_cr8(vcpu); |
4905 | ||
cda0ffdd | 4906 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 4907 | |
04d2cc77 AK |
4908 | clgi(); |
4909 | ||
4910 | local_irq_enable(); | |
36241b8c | 4911 | |
6aa8b732 | 4912 | asm volatile ( |
7454766f AK |
4913 | "push %%" _ASM_BP "; \n\t" |
4914 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
4915 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
4916 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
4917 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
4918 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
4919 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 4920 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4921 | "mov %c[r8](%[svm]), %%r8 \n\t" |
4922 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
4923 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
4924 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
4925 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
4926 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
4927 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
4928 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
4929 | #endif |
4930 | ||
6aa8b732 | 4931 | /* Enter guest mode */ |
7454766f AK |
4932 | "push %%" _ASM_AX " \n\t" |
4933 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
4934 | __ex(SVM_VMLOAD) "\n\t" |
4935 | __ex(SVM_VMRUN) "\n\t" | |
4936 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 4937 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
4938 | |
4939 | /* Save guest registers, load host registers */ | |
7454766f AK |
4940 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
4941 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
4942 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
4943 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
4944 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
4945 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 4946 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4947 | "mov %%r8, %c[r8](%[svm]) \n\t" |
4948 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
4949 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
4950 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
4951 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
4952 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
4953 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
4954 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 4955 | #endif |
7454766f | 4956 | "pop %%" _ASM_BP |
6aa8b732 | 4957 | : |
fb3f0f51 | 4958 | : [svm]"a"(svm), |
6aa8b732 | 4959 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
4960 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
4961 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
4962 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
4963 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
4964 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
4965 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 4966 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
4967 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
4968 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
4969 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
4970 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
4971 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
4972 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
4973 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
4974 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 4975 | #endif |
54a08c04 LV |
4976 | : "cc", "memory" |
4977 | #ifdef CONFIG_X86_64 | |
7454766f | 4978 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 4979 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
4980 | #else |
4981 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
4982 | #endif |
4983 | ); | |
6aa8b732 | 4984 | |
82ca2d10 AK |
4985 | #ifdef CONFIG_X86_64 |
4986 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
4987 | #else | |
dacccfdd | 4988 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
4989 | #ifndef CONFIG_X86_32_LAZY_GS |
4990 | loadsegment(gs, svm->host.gs); | |
4991 | #endif | |
9581d442 | 4992 | #endif |
6aa8b732 AK |
4993 | |
4994 | reload_tss(vcpu); | |
4995 | ||
56ba47dd AK |
4996 | local_irq_disable(); |
4997 | ||
13c34e07 AK |
4998 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
4999 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
5000 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
5001 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
5002 | ||
3781c01c JR |
5003 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
5004 | kvm_before_handle_nmi(&svm->vcpu); | |
5005 | ||
5006 | stgi(); | |
5007 | ||
5008 | /* Any pending NMI will happen here */ | |
5009 | ||
5010 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
5011 | kvm_after_handle_nmi(&svm->vcpu); | |
5012 | ||
d7bf8221 JR |
5013 | sync_cr8_to_lapic(vcpu); |
5014 | ||
a2fa3e9f | 5015 | svm->next_rip = 0; |
9222be18 | 5016 | |
38e5e92f JR |
5017 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
5018 | ||
631bc487 GN |
5019 | /* if exit due to PF check for async PF */ |
5020 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
1261bfa3 | 5021 | svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); |
631bc487 | 5022 | |
6de4f3ad AK |
5023 | if (npt_enabled) { |
5024 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
5025 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
5026 | } | |
fe5913e4 JR |
5027 | |
5028 | /* | |
5029 | * We need to handle MC intercepts here before the vcpu has a chance to | |
5030 | * change the physical cpu | |
5031 | */ | |
5032 | if (unlikely(svm->vmcb->control.exit_code == | |
5033 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
5034 | svm_handle_mce(svm); | |
8d28fec4 RJ |
5035 | |
5036 | mark_all_clean(svm->vmcb); | |
6aa8b732 | 5037 | } |
c207aee4 | 5038 | STACK_FRAME_NON_STANDARD(svm_vcpu_run); |
6aa8b732 | 5039 | |
6aa8b732 AK |
5040 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5041 | { | |
a2fa3e9f GH |
5042 | struct vcpu_svm *svm = to_svm(vcpu); |
5043 | ||
d0ec49d4 | 5044 | svm->vmcb->save.cr3 = __sme_set(root); |
dcca1a65 | 5045 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 5046 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
5047 | } |
5048 | ||
1c97f0a0 JR |
5049 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5050 | { | |
5051 | struct vcpu_svm *svm = to_svm(vcpu); | |
5052 | ||
d0ec49d4 | 5053 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 5054 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
5055 | |
5056 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 5057 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 5058 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 5059 | |
f40f6a45 | 5060 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
5061 | } |
5062 | ||
6aa8b732 AK |
5063 | static int is_disabled(void) |
5064 | { | |
6031a61c JR |
5065 | u64 vm_cr; |
5066 | ||
5067 | rdmsrl(MSR_VM_CR, vm_cr); | |
5068 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
5069 | return 1; | |
5070 | ||
6aa8b732 AK |
5071 | return 0; |
5072 | } | |
5073 | ||
102d8325 IM |
5074 | static void |
5075 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5076 | { | |
5077 | /* | |
5078 | * Patch in the VMMCALL instruction: | |
5079 | */ | |
5080 | hypercall[0] = 0x0f; | |
5081 | hypercall[1] = 0x01; | |
5082 | hypercall[2] = 0xd9; | |
102d8325 IM |
5083 | } |
5084 | ||
002c7f7c YS |
5085 | static void svm_check_processor_compat(void *rtn) |
5086 | { | |
5087 | *(int *)rtn = 0; | |
5088 | } | |
5089 | ||
774ead3a AK |
5090 | static bool svm_cpu_has_accelerated_tpr(void) |
5091 | { | |
5092 | return false; | |
5093 | } | |
5094 | ||
6d396b55 PB |
5095 | static bool svm_has_high_real_mode_segbase(void) |
5096 | { | |
5097 | return true; | |
5098 | } | |
5099 | ||
fc07e76a PB |
5100 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
5101 | { | |
5102 | return 0; | |
5103 | } | |
5104 | ||
0e851880 SY |
5105 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
5106 | { | |
6092d3d3 JR |
5107 | struct vcpu_svm *svm = to_svm(vcpu); |
5108 | ||
5109 | /* Update nrips enabled cache */ | |
d6321d49 | 5110 | svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS); |
46781eae SS |
5111 | |
5112 | if (!kvm_vcpu_apicv_active(vcpu)) | |
5113 | return; | |
5114 | ||
1b4d56b8 | 5115 | guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC); |
0e851880 SY |
5116 | } |
5117 | ||
d4330ef2 JR |
5118 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
5119 | { | |
c2c63a49 | 5120 | switch (func) { |
46781eae SS |
5121 | case 0x1: |
5122 | if (avic) | |
5123 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
5124 | break; | |
4c62a2dc JR |
5125 | case 0x80000001: |
5126 | if (nested) | |
5127 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
5128 | break; | |
c2c63a49 JR |
5129 | case 0x8000000A: |
5130 | entry->eax = 1; /* SVM revision 1 */ | |
5131 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
5132 | ASID emulation to nested SVM */ | |
5133 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
5134 | entry->edx = 0; /* Per default do not support any |
5135 | additional features */ | |
5136 | ||
5137 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 5138 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 5139 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 5140 | |
3d4aeaad JR |
5141 | /* Support NPT for the guest if enabled */ |
5142 | if (npt_enabled) | |
5143 | entry->edx |= SVM_FEATURE_NPT; | |
5144 | ||
c2c63a49 JR |
5145 | break; |
5146 | } | |
d4330ef2 JR |
5147 | } |
5148 | ||
17cc3935 | 5149 | static int svm_get_lpage_level(void) |
344f414f | 5150 | { |
17cc3935 | 5151 | return PT_PDPE_LEVEL; |
344f414f JR |
5152 | } |
5153 | ||
4e47c7a6 SY |
5154 | static bool svm_rdtscp_supported(void) |
5155 | { | |
46896c73 | 5156 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
5157 | } |
5158 | ||
ad756a16 MJ |
5159 | static bool svm_invpcid_supported(void) |
5160 | { | |
5161 | return false; | |
5162 | } | |
5163 | ||
93c4adc7 PB |
5164 | static bool svm_mpx_supported(void) |
5165 | { | |
5166 | return false; | |
5167 | } | |
5168 | ||
55412b2e WL |
5169 | static bool svm_xsaves_supported(void) |
5170 | { | |
5171 | return false; | |
5172 | } | |
5173 | ||
f5f48ee1 SY |
5174 | static bool svm_has_wbinvd_exit(void) |
5175 | { | |
5176 | return true; | |
5177 | } | |
5178 | ||
8061252e | 5179 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5180 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 5181 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5182 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 5183 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 5184 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 5185 | |
09941fbb | 5186 | static const struct __x86_intercept { |
cfec82cb JR |
5187 | u32 exit_code; |
5188 | enum x86_intercept_stage stage; | |
cfec82cb JR |
5189 | } x86_intercept_map[] = { |
5190 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
5191 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5192 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5193 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5194 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
5195 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
5196 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
5197 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
5198 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
5199 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
5200 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
5201 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
5202 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
5203 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
5204 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
5205 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
5206 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
5207 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
5208 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
5209 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
5210 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
5211 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
5212 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
5213 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
5214 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
5215 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
5216 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
5217 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
5218 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
5219 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
5220 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
5221 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
5222 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
5223 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
5224 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
5225 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
5226 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
5227 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
5228 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
5229 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
5230 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
5231 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
5232 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
5233 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
5234 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
5235 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
5236 | }; |
5237 | ||
8061252e | 5238 | #undef PRE_EX |
cfec82cb | 5239 | #undef POST_EX |
d7eb8203 | 5240 | #undef POST_MEM |
cfec82cb | 5241 | |
8a76d7f2 JR |
5242 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
5243 | struct x86_instruction_info *info, | |
5244 | enum x86_intercept_stage stage) | |
5245 | { | |
cfec82cb JR |
5246 | struct vcpu_svm *svm = to_svm(vcpu); |
5247 | int vmexit, ret = X86EMUL_CONTINUE; | |
5248 | struct __x86_intercept icpt_info; | |
5249 | struct vmcb *vmcb = svm->vmcb; | |
5250 | ||
5251 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
5252 | goto out; | |
5253 | ||
5254 | icpt_info = x86_intercept_map[info->intercept]; | |
5255 | ||
40e19b51 | 5256 | if (stage != icpt_info.stage) |
cfec82cb JR |
5257 | goto out; |
5258 | ||
5259 | switch (icpt_info.exit_code) { | |
5260 | case SVM_EXIT_READ_CR0: | |
5261 | if (info->intercept == x86_intercept_cr_read) | |
5262 | icpt_info.exit_code += info->modrm_reg; | |
5263 | break; | |
5264 | case SVM_EXIT_WRITE_CR0: { | |
5265 | unsigned long cr0, val; | |
5266 | u64 intercept; | |
5267 | ||
5268 | if (info->intercept == x86_intercept_cr_write) | |
5269 | icpt_info.exit_code += info->modrm_reg; | |
5270 | ||
62baf44c JK |
5271 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
5272 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
5273 | break; |
5274 | ||
5275 | intercept = svm->nested.intercept; | |
5276 | ||
5277 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
5278 | break; | |
5279 | ||
5280 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
5281 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
5282 | ||
5283 | if (info->intercept == x86_intercept_lmsw) { | |
5284 | cr0 &= 0xfUL; | |
5285 | val &= 0xfUL; | |
5286 | /* lmsw can't clear PE - catch this here */ | |
5287 | if (cr0 & X86_CR0_PE) | |
5288 | val |= X86_CR0_PE; | |
5289 | } | |
5290 | ||
5291 | if (cr0 ^ val) | |
5292 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
5293 | ||
5294 | break; | |
5295 | } | |
3b88e41a JR |
5296 | case SVM_EXIT_READ_DR0: |
5297 | case SVM_EXIT_WRITE_DR0: | |
5298 | icpt_info.exit_code += info->modrm_reg; | |
5299 | break; | |
8061252e JR |
5300 | case SVM_EXIT_MSR: |
5301 | if (info->intercept == x86_intercept_wrmsr) | |
5302 | vmcb->control.exit_info_1 = 1; | |
5303 | else | |
5304 | vmcb->control.exit_info_1 = 0; | |
5305 | break; | |
bf608f88 JR |
5306 | case SVM_EXIT_PAUSE: |
5307 | /* | |
5308 | * We get this for NOP only, but pause | |
5309 | * is rep not, check this here | |
5310 | */ | |
5311 | if (info->rep_prefix != REPE_PREFIX) | |
5312 | goto out; | |
49a8afca | 5313 | break; |
f6511935 JR |
5314 | case SVM_EXIT_IOIO: { |
5315 | u64 exit_info; | |
5316 | u32 bytes; | |
5317 | ||
f6511935 JR |
5318 | if (info->intercept == x86_intercept_in || |
5319 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
5320 | exit_info = ((info->src_val & 0xffff) << 16) | |
5321 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 5322 | bytes = info->dst_bytes; |
6493f157 | 5323 | } else { |
6cbc5f5a | 5324 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 5325 | bytes = info->src_bytes; |
f6511935 JR |
5326 | } |
5327 | ||
5328 | if (info->intercept == x86_intercept_outs || | |
5329 | info->intercept == x86_intercept_ins) | |
5330 | exit_info |= SVM_IOIO_STR_MASK; | |
5331 | ||
5332 | if (info->rep_prefix) | |
5333 | exit_info |= SVM_IOIO_REP_MASK; | |
5334 | ||
5335 | bytes = min(bytes, 4u); | |
5336 | ||
5337 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
5338 | ||
5339 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
5340 | ||
5341 | vmcb->control.exit_info_1 = exit_info; | |
5342 | vmcb->control.exit_info_2 = info->next_rip; | |
5343 | ||
5344 | break; | |
5345 | } | |
cfec82cb JR |
5346 | default: |
5347 | break; | |
5348 | } | |
5349 | ||
f104765b BD |
5350 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
5351 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
5352 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
5353 | vmcb->control.exit_code = icpt_info.exit_code; |
5354 | vmexit = nested_svm_exit_handled(svm); | |
5355 | ||
5356 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
5357 | : X86EMUL_CONTINUE; | |
5358 | ||
5359 | out: | |
5360 | return ret; | |
8a76d7f2 JR |
5361 | } |
5362 | ||
a547c6db YZ |
5363 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
5364 | { | |
5365 | local_irq_enable(); | |
f2485b3e PB |
5366 | /* |
5367 | * We must have an instruction with interrupts enabled, so | |
5368 | * the timer interrupt isn't delayed by the interrupt shadow. | |
5369 | */ | |
5370 | asm("nop"); | |
5371 | local_irq_disable(); | |
a547c6db YZ |
5372 | } |
5373 | ||
ae97a3b8 RK |
5374 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
5375 | { | |
5376 | } | |
5377 | ||
be8ca170 SS |
5378 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu) |
5379 | { | |
5380 | if (avic_handle_apic_id_update(vcpu) != 0) | |
5381 | return; | |
5382 | if (avic_handle_dfr_update(vcpu) != 0) | |
5383 | return; | |
5384 | avic_handle_ldr_update(vcpu); | |
5385 | } | |
5386 | ||
74f16909 BP |
5387 | static void svm_setup_mce(struct kvm_vcpu *vcpu) |
5388 | { | |
5389 | /* [63:9] are reserved. */ | |
5390 | vcpu->arch.mcg_cap &= 0x1ff; | |
5391 | } | |
5392 | ||
404f6aac | 5393 | static struct kvm_x86_ops svm_x86_ops __ro_after_init = { |
6aa8b732 AK |
5394 | .cpu_has_kvm_support = has_svm, |
5395 | .disabled_by_bios = is_disabled, | |
5396 | .hardware_setup = svm_hardware_setup, | |
5397 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 5398 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
5399 | .hardware_enable = svm_hardware_enable, |
5400 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 5401 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6d396b55 | 5402 | .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase, |
6aa8b732 AK |
5403 | |
5404 | .vcpu_create = svm_create_vcpu, | |
5405 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 5406 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 5407 | |
44a95dae SS |
5408 | .vm_init = avic_vm_init, |
5409 | .vm_destroy = avic_vm_destroy, | |
5410 | ||
04d2cc77 | 5411 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
5412 | .vcpu_load = svm_vcpu_load, |
5413 | .vcpu_put = svm_vcpu_put, | |
8221c137 SS |
5414 | .vcpu_blocking = svm_vcpu_blocking, |
5415 | .vcpu_unblocking = svm_vcpu_unblocking, | |
6aa8b732 | 5416 | |
a96036b8 | 5417 | .update_bp_intercept = update_bp_intercept, |
6aa8b732 AK |
5418 | .get_msr = svm_get_msr, |
5419 | .set_msr = svm_set_msr, | |
5420 | .get_segment_base = svm_get_segment_base, | |
5421 | .get_segment = svm_get_segment, | |
5422 | .set_segment = svm_set_segment, | |
2e4d2653 | 5423 | .get_cpl = svm_get_cpl, |
1747fb71 | 5424 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 5425 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 5426 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 5427 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 5428 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
5429 | .set_cr3 = svm_set_cr3, |
5430 | .set_cr4 = svm_set_cr4, | |
5431 | .set_efer = svm_set_efer, | |
5432 | .get_idt = svm_get_idt, | |
5433 | .set_idt = svm_set_idt, | |
5434 | .get_gdt = svm_get_gdt, | |
5435 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
5436 | .get_dr6 = svm_get_dr6, |
5437 | .set_dr6 = svm_set_dr6, | |
020df079 | 5438 | .set_dr7 = svm_set_dr7, |
facb0139 | 5439 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 5440 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
5441 | .get_rflags = svm_get_rflags, |
5442 | .set_rflags = svm_set_rflags, | |
be94f6b7 | 5443 | |
6aa8b732 | 5444 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 5445 | |
6aa8b732 | 5446 | .run = svm_vcpu_run, |
04d2cc77 | 5447 | .handle_exit = handle_exit, |
6aa8b732 | 5448 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
5449 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
5450 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 5451 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 5452 | .set_irq = svm_set_irq, |
95ba8273 | 5453 | .set_nmi = svm_inject_nmi, |
298101da | 5454 | .queue_exception = svm_queue_exception, |
b463a6f7 | 5455 | .cancel_injection = svm_cancel_injection, |
78646121 | 5456 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 5457 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
5458 | .get_nmi_mask = svm_get_nmi_mask, |
5459 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
5460 | .enable_nmi_window = enable_nmi_window, |
5461 | .enable_irq_window = enable_irq_window, | |
5462 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 5463 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
d62caabb AS |
5464 | .get_enable_apicv = svm_get_enable_apicv, |
5465 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, | |
c7c9c56c | 5466 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
44a95dae SS |
5467 | .hwapic_irr_update = svm_hwapic_irr_update, |
5468 | .hwapic_isr_update = svm_hwapic_isr_update, | |
be8ca170 | 5469 | .apicv_post_state_restore = avic_post_state_restore, |
cbc94022 IE |
5470 | |
5471 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 5472 | .get_tdp_level = get_npt_level, |
4b12f0de | 5473 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 5474 | |
586f9607 | 5475 | .get_exit_info = svm_get_exit_info, |
586f9607 | 5476 | |
17cc3935 | 5477 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
5478 | |
5479 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
5480 | |
5481 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 5482 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 5483 | .mpx_supported = svm_mpx_supported, |
55412b2e | 5484 | .xsaves_supported = svm_xsaves_supported, |
d4330ef2 JR |
5485 | |
5486 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
5487 | |
5488 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
5489 | |
5490 | .write_tsc_offset = svm_write_tsc_offset, | |
1c97f0a0 JR |
5491 | |
5492 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
5493 | |
5494 | .check_intercept = svm_check_intercept, | |
a547c6db | 5495 | .handle_external_intr = svm_handle_external_intr, |
ae97a3b8 RK |
5496 | |
5497 | .sched_in = svm_sched_in, | |
25462f7f WH |
5498 | |
5499 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 5500 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
411b44ba | 5501 | .update_pi_irte = svm_update_pi_irte, |
74f16909 | 5502 | .setup_mce = svm_setup_mce, |
6aa8b732 AK |
5503 | }; |
5504 | ||
5505 | static int __init svm_init(void) | |
5506 | { | |
cb498ea2 | 5507 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 5508 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
5509 | } |
5510 | ||
5511 | static void __exit svm_exit(void) | |
5512 | { | |
cb498ea2 | 5513 | kvm_exit(); |
6aa8b732 AK |
5514 | } |
5515 | ||
5516 | module_init(svm_init) | |
5517 | module_exit(svm_exit) |