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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
e495606d | 22 | |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/vmalloc.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
6aa8b732 | 28 | |
e495606d | 29 | #include <asm/desc.h> |
6aa8b732 | 30 | |
4ecac3fd AK |
31 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
32 | ||
6aa8b732 AK |
33 | MODULE_AUTHOR("Qumranet"); |
34 | MODULE_LICENSE("GPL"); | |
35 | ||
36 | #define IOPM_ALLOC_ORDER 2 | |
37 | #define MSRPM_ALLOC_ORDER 1 | |
38 | ||
6aa8b732 AK |
39 | #define DR7_GD_MASK (1 << 13) |
40 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
41 | |
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
80b7706e JR |
45 | #define SVM_FEATURE_NPT (1 << 0) |
46 | #define SVM_FEATURE_LBRV (1 << 1) | |
94c935a1 | 47 | #define SVM_FEATURE_SVML (1 << 2) |
80b7706e | 48 | |
24e09cbf JR |
49 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
50 | ||
709ddebf JR |
51 | /* enable NPT for AMD64 and X86 with PAE */ |
52 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
53 | static bool npt_enabled = true; | |
54 | #else | |
e3da3acd | 55 | static bool npt_enabled = false; |
709ddebf | 56 | #endif |
6c7dac72 JR |
57 | static int npt = 1; |
58 | ||
59 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 60 | |
04d2cc77 | 61 | static void kvm_reput_irq(struct vcpu_svm *svm); |
44874f84 | 62 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
04d2cc77 | 63 | |
a2fa3e9f GH |
64 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
65 | { | |
fb3f0f51 | 66 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
67 | } |
68 | ||
4866d5e3 | 69 | static unsigned long iopm_base; |
6aa8b732 AK |
70 | |
71 | struct kvm_ldttss_desc { | |
72 | u16 limit0; | |
73 | u16 base0; | |
74 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
75 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
76 | u32 base3; | |
77 | u32 zero1; | |
78 | } __attribute__((packed)); | |
79 | ||
80 | struct svm_cpu_data { | |
81 | int cpu; | |
82 | ||
5008fdf5 AK |
83 | u64 asid_generation; |
84 | u32 max_asid; | |
85 | u32 next_asid; | |
6aa8b732 AK |
86 | struct kvm_ldttss_desc *tss_desc; |
87 | ||
88 | struct page *save_area; | |
89 | }; | |
90 | ||
91 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 92 | static uint32_t svm_features; |
6aa8b732 AK |
93 | |
94 | struct svm_init_data { | |
95 | int cpu; | |
96 | int r; | |
97 | }; | |
98 | ||
99 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
100 | ||
9d8f549d | 101 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
102 | #define MSRS_RANGE_SIZE 2048 |
103 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
104 | ||
105 | #define MAX_INST_SIZE 15 | |
106 | ||
80b7706e JR |
107 | static inline u32 svm_has(u32 feat) |
108 | { | |
109 | return svm_features & feat; | |
110 | } | |
111 | ||
6aa8b732 AK |
112 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
113 | { | |
ad312c7c ZX |
114 | int word_index = __ffs(vcpu->arch.irq_summary); |
115 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
116 | int irq = word_index * BITS_PER_LONG + bit_index; |
117 | ||
ad312c7c ZX |
118 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
119 | if (!vcpu->arch.irq_pending[word_index]) | |
120 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
121 | return irq; |
122 | } | |
123 | ||
124 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
125 | { | |
ad312c7c ZX |
126 | set_bit(irq, vcpu->arch.irq_pending); |
127 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
128 | } |
129 | ||
130 | static inline void clgi(void) | |
131 | { | |
4ecac3fd | 132 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
133 | } |
134 | ||
135 | static inline void stgi(void) | |
136 | { | |
4ecac3fd | 137 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
138 | } |
139 | ||
140 | static inline void invlpga(unsigned long addr, u32 asid) | |
141 | { | |
4ecac3fd | 142 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
143 | } |
144 | ||
145 | static inline unsigned long kvm_read_cr2(void) | |
146 | { | |
147 | unsigned long cr2; | |
148 | ||
149 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
150 | return cr2; | |
151 | } | |
152 | ||
153 | static inline void kvm_write_cr2(unsigned long val) | |
154 | { | |
155 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
156 | } | |
157 | ||
158 | static inline unsigned long read_dr6(void) | |
159 | { | |
160 | unsigned long dr6; | |
161 | ||
162 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
163 | return dr6; | |
164 | } | |
165 | ||
166 | static inline void write_dr6(unsigned long val) | |
167 | { | |
168 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
169 | } | |
170 | ||
171 | static inline unsigned long read_dr7(void) | |
172 | { | |
173 | unsigned long dr7; | |
174 | ||
175 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
176 | return dr7; | |
177 | } | |
178 | ||
179 | static inline void write_dr7(unsigned long val) | |
180 | { | |
181 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
182 | } | |
183 | ||
6aa8b732 AK |
184 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
185 | { | |
a2fa3e9f | 186 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
187 | } |
188 | ||
189 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
190 | { | |
191 | force_new_asid(vcpu); | |
192 | } | |
193 | ||
194 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
195 | { | |
709ddebf | 196 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 197 | efer &= ~EFER_LME; |
6aa8b732 | 198 | |
a2fa3e9f | 199 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
ad312c7c | 200 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
201 | } |
202 | ||
298101da AK |
203 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
204 | bool has_error_code, u32 error_code) | |
205 | { | |
206 | struct vcpu_svm *svm = to_svm(vcpu); | |
207 | ||
208 | svm->vmcb->control.event_inj = nr | |
209 | | SVM_EVTINJ_VALID | |
210 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
211 | | SVM_EVTINJ_TYPE_EXEPT; | |
212 | svm->vmcb->control.event_inj_err = error_code; | |
213 | } | |
214 | ||
215 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
216 | { | |
217 | struct vcpu_svm *svm = to_svm(vcpu); | |
218 | ||
219 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
220 | } | |
221 | ||
6aa8b732 AK |
222 | static int is_external_interrupt(u32 info) |
223 | { | |
224 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
225 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
226 | } | |
227 | ||
228 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
229 | { | |
a2fa3e9f GH |
230 | struct vcpu_svm *svm = to_svm(vcpu); |
231 | ||
232 | if (!svm->next_rip) { | |
b8688d51 | 233 | printk(KERN_DEBUG "%s: NOP\n", __func__); |
6aa8b732 AK |
234 | return; |
235 | } | |
5fdbf976 MT |
236 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
237 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
238 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 239 | |
5fdbf976 | 240 | kvm_rip_write(vcpu, svm->next_rip); |
a2fa3e9f | 241 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 242 | |
ad312c7c | 243 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
244 | } |
245 | ||
246 | static int has_svm(void) | |
247 | { | |
248 | uint32_t eax, ebx, ecx, edx; | |
249 | ||
1e885461 | 250 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
251 | printk(KERN_INFO "has_svm: not amd\n"); |
252 | return 0; | |
253 | } | |
254 | ||
255 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
256 | if (eax < SVM_CPUID_FUNC) { | |
257 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
262 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
263 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
264 | return 0; | |
265 | } | |
266 | return 1; | |
267 | } | |
268 | ||
269 | static void svm_hardware_disable(void *garbage) | |
270 | { | |
0da1db75 | 271 | uint64_t efer; |
6aa8b732 | 272 | |
0da1db75 JR |
273 | wrmsrl(MSR_VM_HSAVE_PA, 0); |
274 | rdmsrl(MSR_EFER, efer); | |
275 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
6aa8b732 AK |
276 | } |
277 | ||
278 | static void svm_hardware_enable(void *garbage) | |
279 | { | |
280 | ||
281 | struct svm_cpu_data *svm_data; | |
282 | uint64_t efer; | |
6aa8b732 | 283 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
284 | struct desc_struct *gdt; |
285 | int me = raw_smp_processor_id(); | |
286 | ||
287 | if (!has_svm()) { | |
288 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
289 | return; | |
290 | } | |
291 | svm_data = per_cpu(svm_data, me); | |
292 | ||
293 | if (!svm_data) { | |
294 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
295 | me); | |
296 | return; | |
297 | } | |
298 | ||
299 | svm_data->asid_generation = 1; | |
300 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
301 | svm_data->next_asid = svm_data->max_asid + 1; | |
302 | ||
d77c26fc | 303 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
304 | gdt = (struct desc_struct *)gdt_descr.address; |
305 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
306 | ||
307 | rdmsrl(MSR_EFER, efer); | |
308 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
309 | ||
310 | wrmsrl(MSR_VM_HSAVE_PA, | |
311 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
312 | } | |
313 | ||
0da1db75 JR |
314 | static void svm_cpu_uninit(int cpu) |
315 | { | |
316 | struct svm_cpu_data *svm_data | |
317 | = per_cpu(svm_data, raw_smp_processor_id()); | |
318 | ||
319 | if (!svm_data) | |
320 | return; | |
321 | ||
322 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
323 | __free_page(svm_data->save_area); | |
324 | kfree(svm_data); | |
325 | } | |
326 | ||
6aa8b732 AK |
327 | static int svm_cpu_init(int cpu) |
328 | { | |
329 | struct svm_cpu_data *svm_data; | |
330 | int r; | |
331 | ||
332 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
333 | if (!svm_data) | |
334 | return -ENOMEM; | |
335 | svm_data->cpu = cpu; | |
336 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
337 | r = -ENOMEM; | |
338 | if (!svm_data->save_area) | |
339 | goto err_1; | |
340 | ||
341 | per_cpu(svm_data, cpu) = svm_data; | |
342 | ||
343 | return 0; | |
344 | ||
345 | err_1: | |
346 | kfree(svm_data); | |
347 | return r; | |
348 | ||
349 | } | |
350 | ||
bfc733a7 RR |
351 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
352 | int read, int write) | |
6aa8b732 AK |
353 | { |
354 | int i; | |
355 | ||
356 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
357 | if (msr >= msrpm_ranges[i] && | |
358 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
359 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
360 | msrpm_ranges[i]) * 2; | |
361 | ||
362 | u32 *base = msrpm + (msr_offset / 32); | |
363 | u32 msr_shift = msr_offset % 32; | |
364 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
365 | *base = (*base & ~(0x3 << msr_shift)) | | |
366 | (mask << msr_shift); | |
bfc733a7 | 367 | return; |
6aa8b732 AK |
368 | } |
369 | } | |
bfc733a7 | 370 | BUG(); |
6aa8b732 AK |
371 | } |
372 | ||
f65c229c JR |
373 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
374 | { | |
375 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
376 | ||
377 | #ifdef CONFIG_X86_64 | |
378 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
379 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
380 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
381 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
382 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
383 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
384 | #endif | |
385 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
386 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
387 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); | |
388 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); | |
389 | } | |
390 | ||
24e09cbf JR |
391 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
392 | { | |
393 | u32 *msrpm = svm->msrpm; | |
394 | ||
395 | svm->vmcb->control.lbr_ctl = 1; | |
396 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
397 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
398 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
399 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
400 | } | |
401 | ||
402 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
403 | { | |
404 | u32 *msrpm = svm->msrpm; | |
405 | ||
406 | svm->vmcb->control.lbr_ctl = 0; | |
407 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
408 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
409 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
410 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
411 | } | |
412 | ||
6aa8b732 AK |
413 | static __init int svm_hardware_setup(void) |
414 | { | |
415 | int cpu; | |
416 | struct page *iopm_pages; | |
f65c229c | 417 | void *iopm_va; |
6aa8b732 AK |
418 | int r; |
419 | ||
6aa8b732 AK |
420 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
421 | ||
422 | if (!iopm_pages) | |
423 | return -ENOMEM; | |
c8681339 AL |
424 | |
425 | iopm_va = page_address(iopm_pages); | |
426 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
427 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
428 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
429 | ||
50a37eb4 JR |
430 | if (boot_cpu_has(X86_FEATURE_NX)) |
431 | kvm_enable_efer_bits(EFER_NX); | |
432 | ||
6aa8b732 AK |
433 | for_each_online_cpu(cpu) { |
434 | r = svm_cpu_init(cpu); | |
435 | if (r) | |
f65c229c | 436 | goto err; |
6aa8b732 | 437 | } |
33bd6a0b JR |
438 | |
439 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
440 | ||
e3da3acd JR |
441 | if (!svm_has(SVM_FEATURE_NPT)) |
442 | npt_enabled = false; | |
443 | ||
6c7dac72 JR |
444 | if (npt_enabled && !npt) { |
445 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
446 | npt_enabled = false; | |
447 | } | |
448 | ||
18552672 | 449 | if (npt_enabled) { |
e3da3acd | 450 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 451 | kvm_enable_tdp(); |
5f4cb662 JR |
452 | } else |
453 | kvm_disable_tdp(); | |
e3da3acd | 454 | |
6aa8b732 AK |
455 | return 0; |
456 | ||
f65c229c | 457 | err: |
6aa8b732 AK |
458 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
459 | iopm_base = 0; | |
460 | return r; | |
461 | } | |
462 | ||
463 | static __exit void svm_hardware_unsetup(void) | |
464 | { | |
0da1db75 JR |
465 | int cpu; |
466 | ||
467 | for_each_online_cpu(cpu) | |
468 | svm_cpu_uninit(cpu); | |
469 | ||
6aa8b732 | 470 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 471 | iopm_base = 0; |
6aa8b732 AK |
472 | } |
473 | ||
474 | static void init_seg(struct vmcb_seg *seg) | |
475 | { | |
476 | seg->selector = 0; | |
477 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
478 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
479 | seg->limit = 0xffff; | |
480 | seg->base = 0; | |
481 | } | |
482 | ||
483 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
484 | { | |
485 | seg->selector = 0; | |
486 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
487 | seg->limit = 0xffff; | |
488 | seg->base = 0; | |
489 | } | |
490 | ||
e6101a96 | 491 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 492 | { |
e6101a96 JR |
493 | struct vmcb_control_area *control = &svm->vmcb->control; |
494 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
495 | |
496 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
497 | INTERCEPT_CR3_MASK | | |
649d6864 | 498 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
499 | |
500 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
501 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
502 | INTERCEPT_CR4_MASK | |
503 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
504 | |
505 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
506 | INTERCEPT_DR1_MASK | | |
507 | INTERCEPT_DR2_MASK | | |
508 | INTERCEPT_DR3_MASK; | |
509 | ||
510 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
511 | INTERCEPT_DR1_MASK | | |
512 | INTERCEPT_DR2_MASK | | |
513 | INTERCEPT_DR3_MASK | | |
514 | INTERCEPT_DR5_MASK | | |
515 | INTERCEPT_DR7_MASK; | |
516 | ||
7aa81cc0 | 517 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
518 | (1 << UD_VECTOR) | |
519 | (1 << MC_VECTOR); | |
6aa8b732 AK |
520 | |
521 | ||
522 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
523 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 524 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 | 525 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 526 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 527 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 528 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
529 | (1ULL << INTERCEPT_INVLPGA) | |
530 | (1ULL << INTERCEPT_IOIO_PROT) | | |
531 | (1ULL << INTERCEPT_MSR_PROT) | | |
532 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 533 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
534 | (1ULL << INTERCEPT_VMRUN) | |
535 | (1ULL << INTERCEPT_VMMCALL) | | |
536 | (1ULL << INTERCEPT_VMLOAD) | | |
537 | (1ULL << INTERCEPT_VMSAVE) | | |
538 | (1ULL << INTERCEPT_STGI) | | |
539 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 540 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 541 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
542 | (1ULL << INTERCEPT_MONITOR) | |
543 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
544 | |
545 | control->iopm_base_pa = iopm_base; | |
f65c229c | 546 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 547 | control->tsc_offset = 0; |
6aa8b732 AK |
548 | control->int_ctl = V_INTR_MASKING_MASK; |
549 | ||
550 | init_seg(&save->es); | |
551 | init_seg(&save->ss); | |
552 | init_seg(&save->ds); | |
553 | init_seg(&save->fs); | |
554 | init_seg(&save->gs); | |
555 | ||
556 | save->cs.selector = 0xf000; | |
557 | /* Executable/Readable Code Segment */ | |
558 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
559 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
560 | save->cs.limit = 0xffff; | |
d92899a0 AK |
561 | /* |
562 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
563 | * be consistent with it. | |
564 | * | |
565 | * Replace when we have real mode working for vmx. | |
566 | */ | |
567 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
568 | |
569 | save->gdtr.limit = 0xffff; | |
570 | save->idtr.limit = 0xffff; | |
571 | ||
572 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
573 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
574 | ||
575 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 576 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
577 | save->dr7 = 0x400; |
578 | save->rflags = 2; | |
579 | save->rip = 0x0000fff0; | |
5fdbf976 | 580 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 AK |
581 | |
582 | /* | |
583 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
584 | * cache by default. the orderly way is to enable cache in bios. | |
585 | */ | |
707d92fa | 586 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 587 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 588 | /* rdx = ?? */ |
709ddebf JR |
589 | |
590 | if (npt_enabled) { | |
591 | /* Setup VMCB for Nested Paging */ | |
592 | control->nested_ctl = 1; | |
a7052897 MT |
593 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
594 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf JR |
595 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
596 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
597 | INTERCEPT_CR3_MASK); | |
598 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
599 | INTERCEPT_CR3_MASK); | |
600 | save->g_pat = 0x0007040600070406ULL; | |
601 | /* enable caching because the QEMU Bios doesn't enable it */ | |
602 | save->cr0 = X86_CR0_ET; | |
603 | save->cr3 = 0; | |
604 | save->cr4 = 0; | |
605 | } | |
a79d2f18 | 606 | force_new_asid(&svm->vcpu); |
6aa8b732 AK |
607 | } |
608 | ||
e00c8cf2 | 609 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
610 | { |
611 | struct vcpu_svm *svm = to_svm(vcpu); | |
612 | ||
e6101a96 | 613 | init_vmcb(svm); |
70433389 AK |
614 | |
615 | if (vcpu->vcpu_id != 0) { | |
5fdbf976 | 616 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
617 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
618 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 619 | } |
5fdbf976 MT |
620 | vcpu->arch.regs_avail = ~0; |
621 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
622 | |
623 | return 0; | |
04d2cc77 AK |
624 | } |
625 | ||
fb3f0f51 | 626 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 627 | { |
a2fa3e9f | 628 | struct vcpu_svm *svm; |
6aa8b732 | 629 | struct page *page; |
f65c229c | 630 | struct page *msrpm_pages; |
fb3f0f51 | 631 | int err; |
6aa8b732 | 632 | |
c16f862d | 633 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
634 | if (!svm) { |
635 | err = -ENOMEM; | |
636 | goto out; | |
637 | } | |
638 | ||
639 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
640 | if (err) | |
641 | goto free_svm; | |
642 | ||
6aa8b732 | 643 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
644 | if (!page) { |
645 | err = -ENOMEM; | |
646 | goto uninit; | |
647 | } | |
6aa8b732 | 648 | |
f65c229c JR |
649 | err = -ENOMEM; |
650 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
651 | if (!msrpm_pages) | |
652 | goto uninit; | |
653 | svm->msrpm = page_address(msrpm_pages); | |
654 | svm_vcpu_init_msrpm(svm->msrpm); | |
655 | ||
a2fa3e9f GH |
656 | svm->vmcb = page_address(page); |
657 | clear_page(svm->vmcb); | |
658 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
659 | svm->asid_generation = 0; | |
660 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
e6101a96 | 661 | init_vmcb(svm); |
a2fa3e9f | 662 | |
fb3f0f51 RR |
663 | fx_init(&svm->vcpu); |
664 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 665 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 666 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 667 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 668 | |
fb3f0f51 | 669 | return &svm->vcpu; |
36241b8c | 670 | |
fb3f0f51 RR |
671 | uninit: |
672 | kvm_vcpu_uninit(&svm->vcpu); | |
673 | free_svm: | |
a4770347 | 674 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
675 | out: |
676 | return ERR_PTR(err); | |
6aa8b732 AK |
677 | } |
678 | ||
679 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
680 | { | |
a2fa3e9f GH |
681 | struct vcpu_svm *svm = to_svm(vcpu); |
682 | ||
fb3f0f51 | 683 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 684 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
fb3f0f51 | 685 | kvm_vcpu_uninit(vcpu); |
a4770347 | 686 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
687 | } |
688 | ||
15ad7146 | 689 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 690 | { |
a2fa3e9f | 691 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 692 | int i; |
0cc5064d | 693 | |
0cc5064d AK |
694 | if (unlikely(cpu != vcpu->cpu)) { |
695 | u64 tsc_this, delta; | |
696 | ||
697 | /* | |
698 | * Make sure that the guest sees a monotonically | |
699 | * increasing TSC. | |
700 | */ | |
701 | rdtscll(tsc_this); | |
ad312c7c | 702 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 703 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 704 | vcpu->cpu = cpu; |
2f599714 | 705 | kvm_migrate_timers(vcpu); |
0cc5064d | 706 | } |
94dfbdb3 AL |
707 | |
708 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 709 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
710 | } |
711 | ||
712 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
713 | { | |
a2fa3e9f | 714 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
715 | int i; |
716 | ||
e1beb1d3 | 717 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 718 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 719 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 720 | |
ad312c7c | 721 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
722 | } |
723 | ||
6aa8b732 AK |
724 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
725 | { | |
a2fa3e9f | 726 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
727 | } |
728 | ||
729 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
730 | { | |
a2fa3e9f | 731 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
732 | } |
733 | ||
734 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
735 | { | |
a2fa3e9f | 736 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
737 | |
738 | switch (seg) { | |
739 | case VCPU_SREG_CS: return &save->cs; | |
740 | case VCPU_SREG_DS: return &save->ds; | |
741 | case VCPU_SREG_ES: return &save->es; | |
742 | case VCPU_SREG_FS: return &save->fs; | |
743 | case VCPU_SREG_GS: return &save->gs; | |
744 | case VCPU_SREG_SS: return &save->ss; | |
745 | case VCPU_SREG_TR: return &save->tr; | |
746 | case VCPU_SREG_LDTR: return &save->ldtr; | |
747 | } | |
748 | BUG(); | |
8b6d44c7 | 749 | return NULL; |
6aa8b732 AK |
750 | } |
751 | ||
752 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
753 | { | |
754 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
755 | ||
756 | return s->base; | |
757 | } | |
758 | ||
759 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
760 | struct kvm_segment *var, int seg) | |
761 | { | |
762 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
763 | ||
764 | var->base = s->base; | |
765 | var->limit = s->limit; | |
766 | var->selector = s->selector; | |
767 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
768 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
769 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
770 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
771 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
772 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
773 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
774 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc AS |
775 | |
776 | /* | |
777 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
778 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
779 | * Intel's VMENTRY has a check on the 'G' bit. | |
780 | */ | |
781 | if (seg == VCPU_SREG_CS) | |
782 | var->g = s->limit > 0xfffff; | |
783 | ||
6aa8b732 AK |
784 | var->unusable = !var->present; |
785 | } | |
786 | ||
2e4d2653 IE |
787 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
788 | { | |
789 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
790 | ||
791 | return save->cpl; | |
792 | } | |
793 | ||
6aa8b732 AK |
794 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
795 | { | |
a2fa3e9f GH |
796 | struct vcpu_svm *svm = to_svm(vcpu); |
797 | ||
798 | dt->limit = svm->vmcb->save.idtr.limit; | |
799 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
800 | } |
801 | ||
802 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
803 | { | |
a2fa3e9f GH |
804 | struct vcpu_svm *svm = to_svm(vcpu); |
805 | ||
806 | svm->vmcb->save.idtr.limit = dt->limit; | |
807 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
808 | } |
809 | ||
810 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
811 | { | |
a2fa3e9f GH |
812 | struct vcpu_svm *svm = to_svm(vcpu); |
813 | ||
814 | dt->limit = svm->vmcb->save.gdtr.limit; | |
815 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
816 | } |
817 | ||
818 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
819 | { | |
a2fa3e9f GH |
820 | struct vcpu_svm *svm = to_svm(vcpu); |
821 | ||
822 | svm->vmcb->save.gdtr.limit = dt->limit; | |
823 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
824 | } |
825 | ||
25c4c276 | 826 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
827 | { |
828 | } | |
829 | ||
6aa8b732 AK |
830 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
831 | { | |
a2fa3e9f GH |
832 | struct vcpu_svm *svm = to_svm(vcpu); |
833 | ||
05b3e0c2 | 834 | #ifdef CONFIG_X86_64 |
ad312c7c | 835 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 836 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 837 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 838 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
839 | } |
840 | ||
d77c26fc | 841 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 842 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 843 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
844 | } |
845 | } | |
846 | #endif | |
709ddebf JR |
847 | if (npt_enabled) |
848 | goto set; | |
849 | ||
ad312c7c | 850 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 851 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
852 | vcpu->fpu_active = 1; |
853 | } | |
854 | ||
ad312c7c | 855 | vcpu->arch.cr0 = cr0; |
707d92fa | 856 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
857 | if (!vcpu->fpu_active) { |
858 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 859 | cr0 |= X86_CR0_TS; |
6b390b63 | 860 | } |
709ddebf JR |
861 | set: |
862 | /* | |
863 | * re-enable caching here because the QEMU bios | |
864 | * does not do it - this results in some delay at | |
865 | * reboot | |
866 | */ | |
867 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 868 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
869 | } |
870 | ||
871 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
872 | { | |
6394b649 | 873 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
874 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
875 | ||
876 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
877 | force_new_asid(vcpu); | |
6394b649 | 878 | |
ec077263 JR |
879 | vcpu->arch.cr4 = cr4; |
880 | if (!npt_enabled) | |
881 | cr4 |= X86_CR4_PAE; | |
6394b649 | 882 | cr4 |= host_cr4_mce; |
ec077263 | 883 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
884 | } |
885 | ||
886 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
887 | struct kvm_segment *var, int seg) | |
888 | { | |
a2fa3e9f | 889 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
890 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
891 | ||
892 | s->base = var->base; | |
893 | s->limit = var->limit; | |
894 | s->selector = var->selector; | |
895 | if (var->unusable) | |
896 | s->attrib = 0; | |
897 | else { | |
898 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
899 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
900 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
901 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
902 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
903 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
904 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
905 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
906 | } | |
907 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
908 | svm->vmcb->save.cpl |
909 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
910 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
911 | ||
912 | } | |
913 | ||
6aa8b732 AK |
914 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) |
915 | { | |
916 | return -EOPNOTSUPP; | |
917 | } | |
918 | ||
2a8067f1 ED |
919 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
920 | { | |
921 | struct vcpu_svm *svm = to_svm(vcpu); | |
922 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
923 | ||
924 | if (is_external_interrupt(exit_int_info)) | |
925 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
926 | return -1; | |
927 | } | |
928 | ||
6aa8b732 AK |
929 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
930 | { | |
94dfbdb3 | 931 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 932 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 933 | #endif |
6aa8b732 AK |
934 | } |
935 | ||
936 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
937 | { | |
94dfbdb3 | 938 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 939 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 940 | #endif |
6aa8b732 AK |
941 | } |
942 | ||
e756fc62 | 943 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
944 | { |
945 | if (svm_data->next_asid > svm_data->max_asid) { | |
946 | ++svm_data->asid_generation; | |
947 | svm_data->next_asid = 1; | |
a2fa3e9f | 948 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
949 | } |
950 | ||
e756fc62 | 951 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
952 | svm->asid_generation = svm_data->asid_generation; |
953 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
954 | } |
955 | ||
6aa8b732 AK |
956 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
957 | { | |
af9ca2d7 JR |
958 | unsigned long val = to_svm(vcpu)->db_regs[dr]; |
959 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); | |
960 | return val; | |
6aa8b732 AK |
961 | } |
962 | ||
963 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
964 | int *exception) | |
965 | { | |
a2fa3e9f GH |
966 | struct vcpu_svm *svm = to_svm(vcpu); |
967 | ||
6aa8b732 AK |
968 | *exception = 0; |
969 | ||
a2fa3e9f GH |
970 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
971 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
972 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
973 | *exception = DB_VECTOR; |
974 | return; | |
975 | } | |
976 | ||
977 | switch (dr) { | |
978 | case 0 ... 3: | |
a2fa3e9f | 979 | svm->db_regs[dr] = value; |
6aa8b732 AK |
980 | return; |
981 | case 4 ... 5: | |
ad312c7c | 982 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
983 | *exception = UD_VECTOR; |
984 | return; | |
985 | } | |
986 | case 7: { | |
987 | if (value & ~((1ULL << 32) - 1)) { | |
988 | *exception = GP_VECTOR; | |
989 | return; | |
990 | } | |
a2fa3e9f | 991 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
992 | return; |
993 | } | |
994 | default: | |
995 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
b8688d51 | 996 | __func__, dr); |
6aa8b732 AK |
997 | *exception = UD_VECTOR; |
998 | return; | |
999 | } | |
1000 | } | |
1001 | ||
e756fc62 | 1002 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1003 | { |
a2fa3e9f | 1004 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 1005 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
1006 | u64 fault_address; |
1007 | u32 error_code; | |
577bdc49 | 1008 | bool event_injection = false; |
6aa8b732 | 1009 | |
85f455f7 | 1010 | if (!irqchip_in_kernel(kvm) && |
577bdc49 AK |
1011 | is_external_interrupt(exit_int_info)) { |
1012 | event_injection = true; | |
e756fc62 | 1013 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
577bdc49 | 1014 | } |
6aa8b732 | 1015 | |
a2fa3e9f GH |
1016 | fault_address = svm->vmcb->control.exit_info_2; |
1017 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 JR |
1018 | |
1019 | if (!npt_enabled) | |
1020 | KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code, | |
1021 | (u32)fault_address, (u32)(fault_address >> 32), | |
1022 | handler); | |
d2ebb410 JR |
1023 | else |
1024 | KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code, | |
1025 | (u32)fault_address, (u32)(fault_address >> 32), | |
1026 | handler); | |
44874f84 JR |
1027 | /* |
1028 | * FIXME: Tis shouldn't be necessary here, but there is a flush | |
1029 | * missing in the MMU code. Until we find this bug, flush the | |
1030 | * complete TLB here on an NPF | |
1031 | */ | |
1032 | if (npt_enabled) | |
1033 | svm_flush_tlb(&svm->vcpu); | |
af9ca2d7 | 1034 | |
48d15039 | 1035 | if (!npt_enabled && event_injection) |
577bdc49 | 1036 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); |
3067714c | 1037 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1038 | } |
1039 | ||
7aa81cc0 AL |
1040 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1041 | { | |
1042 | int er; | |
1043 | ||
571008da | 1044 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1045 | if (er != EMULATE_DONE) |
7ee5d940 | 1046 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1047 | return 1; |
1048 | } | |
1049 | ||
e756fc62 | 1050 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 1051 | { |
a2fa3e9f | 1052 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1053 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1054 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1055 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1056 | |
1057 | return 1; | |
7807fa6c AL |
1058 | } |
1059 | ||
53371b50 JR |
1060 | static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1061 | { | |
1062 | /* | |
1063 | * On an #MC intercept the MCE handler is not called automatically in | |
1064 | * the host. So do it by hand here. | |
1065 | */ | |
1066 | asm volatile ( | |
1067 | "int $0x12\n"); | |
1068 | /* not sure if we ever come back to this point */ | |
1069 | ||
1070 | return 1; | |
1071 | } | |
1072 | ||
e756fc62 | 1073 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
1074 | { |
1075 | /* | |
1076 | * VMCB is undefined after a SHUTDOWN intercept | |
1077 | * so reinitialize it. | |
1078 | */ | |
a2fa3e9f | 1079 | clear_page(svm->vmcb); |
e6101a96 | 1080 | init_vmcb(svm); |
46fe4ddd JR |
1081 | |
1082 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1083 | return 0; | |
1084 | } | |
1085 | ||
e756fc62 | 1086 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1087 | { |
d77c26fc | 1088 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1089 | int size, down, in, string, rep; |
1090 | unsigned port; | |
6aa8b732 | 1091 | |
e756fc62 | 1092 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1093 | |
a2fa3e9f | 1094 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1095 | |
e70669ab LV |
1096 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1097 | ||
1098 | if (string) { | |
3427318f LV |
1099 | if (emulate_instruction(&svm->vcpu, |
1100 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1101 | return 0; |
1102 | return 1; | |
1103 | } | |
1104 | ||
039576c0 AK |
1105 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1106 | port = io_info >> 16; | |
1107 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1108 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1109 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1110 | |
3090dd73 | 1111 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1112 | } |
1113 | ||
c47f098d JR |
1114 | static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1115 | { | |
af9ca2d7 | 1116 | KVMTRACE_0D(NMI, &svm->vcpu, handler); |
c47f098d JR |
1117 | return 1; |
1118 | } | |
1119 | ||
a0698055 JR |
1120 | static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1121 | { | |
1122 | ++svm->vcpu.stat.irq_exits; | |
af9ca2d7 | 1123 | KVMTRACE_0D(INTR, &svm->vcpu, handler); |
a0698055 JR |
1124 | return 1; |
1125 | } | |
1126 | ||
e756fc62 | 1127 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1128 | { |
1129 | return 1; | |
1130 | } | |
1131 | ||
e756fc62 | 1132 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1133 | { |
5fdbf976 | 1134 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1135 | skip_emulated_instruction(&svm->vcpu); |
1136 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1137 | } |
1138 | ||
e756fc62 | 1139 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1140 | { |
5fdbf976 | 1141 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1142 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1143 | kvm_emulate_hypercall(&svm->vcpu); |
1144 | return 1; | |
02e235bc AK |
1145 | } |
1146 | ||
e756fc62 RR |
1147 | static int invalid_op_interception(struct vcpu_svm *svm, |
1148 | struct kvm_run *kvm_run) | |
6aa8b732 | 1149 | { |
7ee5d940 | 1150 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1151 | return 1; |
1152 | } | |
1153 | ||
e756fc62 RR |
1154 | static int task_switch_interception(struct vcpu_svm *svm, |
1155 | struct kvm_run *kvm_run) | |
6aa8b732 | 1156 | { |
37817f29 IE |
1157 | u16 tss_selector; |
1158 | ||
1159 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
1160 | if (svm->vmcb->control.exit_info_2 & | |
1161 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
1162 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1163 | TASK_SWITCH_IRET); | |
1164 | if (svm->vmcb->control.exit_info_2 & | |
1165 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
1166 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1167 | TASK_SWITCH_JMP); | |
1168 | return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL); | |
6aa8b732 AK |
1169 | } |
1170 | ||
e756fc62 | 1171 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1172 | { |
5fdbf976 | 1173 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1174 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1175 | return 1; |
6aa8b732 AK |
1176 | } |
1177 | ||
a7052897 MT |
1178 | static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1179 | { | |
1180 | if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE) | |
1181 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); | |
1182 | return 1; | |
1183 | } | |
1184 | ||
e756fc62 RR |
1185 | static int emulate_on_interception(struct vcpu_svm *svm, |
1186 | struct kvm_run *kvm_run) | |
6aa8b732 | 1187 | { |
3427318f | 1188 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 1189 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
1190 | return 1; |
1191 | } | |
1192 | ||
1d075434 JR |
1193 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1194 | { | |
1195 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1196 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1197 | return 1; | |
1198 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1199 | return 0; | |
1200 | } | |
1201 | ||
6aa8b732 AK |
1202 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1203 | { | |
a2fa3e9f GH |
1204 | struct vcpu_svm *svm = to_svm(vcpu); |
1205 | ||
6aa8b732 | 1206 | switch (ecx) { |
6aa8b732 AK |
1207 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1208 | u64 tsc; | |
1209 | ||
1210 | rdtscll(tsc); | |
a2fa3e9f | 1211 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1212 | break; |
1213 | } | |
0e859cac | 1214 | case MSR_K6_STAR: |
a2fa3e9f | 1215 | *data = svm->vmcb->save.star; |
6aa8b732 | 1216 | break; |
0e859cac | 1217 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1218 | case MSR_LSTAR: |
a2fa3e9f | 1219 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1220 | break; |
1221 | case MSR_CSTAR: | |
a2fa3e9f | 1222 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1223 | break; |
1224 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1225 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1226 | break; |
1227 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1228 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1229 | break; |
1230 | #endif | |
1231 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1232 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1233 | break; |
1234 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1235 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1236 | break; |
1237 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1238 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1239 | break; |
a2938c80 JR |
1240 | /* Nobody will change the following 5 values in the VMCB so |
1241 | we can safely return them on rdmsr. They will always be 0 | |
1242 | until LBRV is implemented. */ | |
1243 | case MSR_IA32_DEBUGCTLMSR: | |
1244 | *data = svm->vmcb->save.dbgctl; | |
1245 | break; | |
1246 | case MSR_IA32_LASTBRANCHFROMIP: | |
1247 | *data = svm->vmcb->save.br_from; | |
1248 | break; | |
1249 | case MSR_IA32_LASTBRANCHTOIP: | |
1250 | *data = svm->vmcb->save.br_to; | |
1251 | break; | |
1252 | case MSR_IA32_LASTINTFROMIP: | |
1253 | *data = svm->vmcb->save.last_excp_from; | |
1254 | break; | |
1255 | case MSR_IA32_LASTINTTOIP: | |
1256 | *data = svm->vmcb->save.last_excp_to; | |
1257 | break; | |
6aa8b732 | 1258 | default: |
3bab1f5d | 1259 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1260 | } |
1261 | return 0; | |
1262 | } | |
1263 | ||
e756fc62 | 1264 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1265 | { |
ad312c7c | 1266 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1267 | u64 data; |
1268 | ||
e756fc62 | 1269 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1270 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1271 | else { |
af9ca2d7 JR |
1272 | KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data, |
1273 | (u32)(data >> 32), handler); | |
1274 | ||
5fdbf976 | 1275 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 1276 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 1277 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1278 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1279 | } |
1280 | return 1; | |
1281 | } | |
1282 | ||
1283 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1284 | { | |
a2fa3e9f GH |
1285 | struct vcpu_svm *svm = to_svm(vcpu); |
1286 | ||
6aa8b732 | 1287 | switch (ecx) { |
6aa8b732 AK |
1288 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1289 | u64 tsc; | |
1290 | ||
1291 | rdtscll(tsc); | |
a2fa3e9f | 1292 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1293 | break; |
1294 | } | |
0e859cac | 1295 | case MSR_K6_STAR: |
a2fa3e9f | 1296 | svm->vmcb->save.star = data; |
6aa8b732 | 1297 | break; |
49b14f24 | 1298 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1299 | case MSR_LSTAR: |
a2fa3e9f | 1300 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1301 | break; |
1302 | case MSR_CSTAR: | |
a2fa3e9f | 1303 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1304 | break; |
1305 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1306 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1307 | break; |
1308 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1309 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1310 | break; |
1311 | #endif | |
1312 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1313 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1314 | break; |
1315 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1316 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1317 | break; |
1318 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1319 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1320 | break; |
a2938c80 | 1321 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
1322 | if (!svm_has(SVM_FEATURE_LBRV)) { |
1323 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 1324 | __func__, data); |
24e09cbf JR |
1325 | break; |
1326 | } | |
1327 | if (data & DEBUGCTL_RESERVED_BITS) | |
1328 | return 1; | |
1329 | ||
1330 | svm->vmcb->save.dbgctl = data; | |
1331 | if (data & (1ULL<<0)) | |
1332 | svm_enable_lbrv(svm); | |
1333 | else | |
1334 | svm_disable_lbrv(svm); | |
a2938c80 | 1335 | break; |
62b9abaa JR |
1336 | case MSR_K7_EVNTSEL0: |
1337 | case MSR_K7_EVNTSEL1: | |
1338 | case MSR_K7_EVNTSEL2: | |
1339 | case MSR_K7_EVNTSEL3: | |
14ae51b6 CL |
1340 | case MSR_K7_PERFCTR0: |
1341 | case MSR_K7_PERFCTR1: | |
1342 | case MSR_K7_PERFCTR2: | |
1343 | case MSR_K7_PERFCTR3: | |
62b9abaa | 1344 | /* |
14ae51b6 CL |
1345 | * Just discard all writes to the performance counters; this |
1346 | * should keep both older linux and windows 64-bit guests | |
1347 | * happy | |
62b9abaa | 1348 | */ |
14ae51b6 CL |
1349 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data); |
1350 | ||
62b9abaa | 1351 | break; |
6aa8b732 | 1352 | default: |
3bab1f5d | 1353 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1354 | } |
1355 | return 0; | |
1356 | } | |
1357 | ||
e756fc62 | 1358 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1359 | { |
ad312c7c | 1360 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 1361 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 1362 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 JR |
1363 | |
1364 | KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32), | |
1365 | handler); | |
1366 | ||
5fdbf976 | 1367 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1368 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1369 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1370 | else |
e756fc62 | 1371 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1372 | return 1; |
1373 | } | |
1374 | ||
e756fc62 | 1375 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1376 | { |
e756fc62 RR |
1377 | if (svm->vmcb->control.exit_info_1) |
1378 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1379 | else |
e756fc62 | 1380 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1381 | } |
1382 | ||
e756fc62 | 1383 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1384 | struct kvm_run *kvm_run) |
1385 | { | |
af9ca2d7 JR |
1386 | KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler); |
1387 | ||
85f455f7 ED |
1388 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1389 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1390 | /* |
1391 | * If the user space waits to inject interrupts, exit as soon as | |
1392 | * possible | |
1393 | */ | |
1394 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1395 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1396 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1397 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | return 1; | |
1402 | } | |
1403 | ||
e756fc62 | 1404 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1405 | struct kvm_run *kvm_run) = { |
1406 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1407 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1408 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1409 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1410 | /* for now: */ |
1411 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1412 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1413 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1414 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1415 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1416 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1417 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1418 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1419 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1420 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1421 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1422 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1423 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1424 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1425 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1426 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1427 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 1428 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 1429 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 1430 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
1431 | [SVM_EXIT_SMI] = nop_on_interception, |
1432 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1433 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1434 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1435 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1436 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 | 1437 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 1438 | [SVM_EXIT_INVLPG] = invlpg_interception, |
6aa8b732 AK |
1439 | [SVM_EXIT_INVLPGA] = invalid_op_interception, |
1440 | [SVM_EXIT_IOIO] = io_interception, | |
1441 | [SVM_EXIT_MSR] = msr_interception, | |
1442 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1443 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1444 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1445 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1446 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1447 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1448 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1449 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1450 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1451 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1452 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1453 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 1454 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
1455 | }; |
1456 | ||
04d2cc77 | 1457 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1458 | { |
04d2cc77 | 1459 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1460 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1461 | |
af9ca2d7 JR |
1462 | KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip, |
1463 | (u32)((u64)svm->vmcb->save.rip >> 32), entryexit); | |
1464 | ||
709ddebf JR |
1465 | if (npt_enabled) { |
1466 | int mmu_reload = 0; | |
1467 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
1468 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
1469 | mmu_reload = 1; | |
1470 | } | |
1471 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
1472 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
1473 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1474 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1475 | kvm_inject_gp(vcpu, 0); | |
1476 | return 1; | |
1477 | } | |
1478 | } | |
1479 | if (mmu_reload) { | |
1480 | kvm_mmu_reset_context(vcpu); | |
1481 | kvm_mmu_load(vcpu); | |
1482 | } | |
1483 | } | |
1484 | ||
04d2cc77 AK |
1485 | kvm_reput_irq(svm); |
1486 | ||
1487 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1488 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1489 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1490 | = svm->vmcb->control.exit_code; | |
1491 | return 0; | |
1492 | } | |
1493 | ||
a2fa3e9f | 1494 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf JR |
1495 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
1496 | exit_code != SVM_EXIT_NPF) | |
6aa8b732 AK |
1497 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
1498 | "exit_code 0x%x\n", | |
b8688d51 | 1499 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1500 | exit_code); |
1501 | ||
9d8f549d | 1502 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1503 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1504 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1505 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1506 | return 0; |
1507 | } | |
1508 | ||
e756fc62 | 1509 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1510 | } |
1511 | ||
1512 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1513 | { | |
1514 | int cpu = raw_smp_processor_id(); | |
1515 | ||
1516 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1517 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1518 | load_TR_desc(); |
1519 | } | |
1520 | ||
e756fc62 | 1521 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1522 | { |
1523 | int cpu = raw_smp_processor_id(); | |
1524 | ||
1525 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1526 | ||
a2fa3e9f | 1527 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1528 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1529 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1530 | new_asid(svm, svm_data); |
6aa8b732 AK |
1531 | } |
1532 | ||
1533 | ||
85f455f7 | 1534 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1535 | { |
1536 | struct vmcb_control_area *control; | |
1537 | ||
af9ca2d7 JR |
1538 | KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler); |
1539 | ||
fa89a817 | 1540 | ++svm->vcpu.stat.irq_injections; |
e756fc62 | 1541 | control = &svm->vmcb->control; |
85f455f7 | 1542 | control->int_vector = irq; |
6aa8b732 AK |
1543 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1544 | control->int_ctl |= V_IRQ_MASK | | |
1545 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1546 | } | |
1547 | ||
2a8067f1 ED |
1548 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1549 | { | |
1550 | struct vcpu_svm *svm = to_svm(vcpu); | |
1551 | ||
1552 | svm_inject_irq(svm, irq); | |
1553 | } | |
1554 | ||
aaacfc9a JR |
1555 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
1556 | { | |
1557 | struct vcpu_svm *svm = to_svm(vcpu); | |
1558 | struct vmcb *vmcb = svm->vmcb; | |
1559 | int max_irr, tpr; | |
1560 | ||
1561 | if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr) | |
1562 | return; | |
1563 | ||
1564 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1565 | ||
1566 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
1567 | if (max_irr == -1) | |
1568 | return; | |
1569 | ||
1570 | tpr = kvm_lapic_get_cr8(vcpu) << 4; | |
1571 | ||
1572 | if (tpr >= (max_irr & 0xf0)) | |
1573 | vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
1574 | } | |
1575 | ||
04d2cc77 | 1576 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1577 | { |
04d2cc77 | 1578 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1579 | struct vmcb *vmcb = svm->vmcb; |
1580 | int intr_vector = -1; | |
1581 | ||
1582 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1583 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1584 | intr_vector = vmcb->control.exit_int_info & | |
1585 | SVM_EVTINJ_VEC_MASK; | |
1586 | vmcb->control.exit_int_info = 0; | |
1587 | svm_inject_irq(svm, intr_vector); | |
aaacfc9a | 1588 | goto out; |
85f455f7 ED |
1589 | } |
1590 | ||
1591 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
aaacfc9a | 1592 | goto out; |
85f455f7 | 1593 | |
1b9778da | 1594 | if (!kvm_cpu_has_interrupt(vcpu)) |
aaacfc9a | 1595 | goto out; |
85f455f7 ED |
1596 | |
1597 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1598 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1599 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1600 | /* unable to deliver irq, set pending irq */ | |
1601 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1602 | svm_inject_irq(svm, 0x0); | |
aaacfc9a | 1603 | goto out; |
85f455f7 ED |
1604 | } |
1605 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1606 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1607 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1608 | kvm_timer_intr_post(vcpu, intr_vector); |
aaacfc9a JR |
1609 | out: |
1610 | update_cr8_intercept(vcpu); | |
85f455f7 ED |
1611 | } |
1612 | ||
1613 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1614 | { | |
e756fc62 | 1615 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1616 | |
7017fc3d ED |
1617 | if ((control->int_ctl & V_IRQ_MASK) |
1618 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1619 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1620 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1621 | } |
c1150d8c | 1622 | |
ad312c7c | 1623 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1624 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1625 | } | |
1626 | ||
85f455f7 ED |
1627 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1628 | { | |
1629 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1630 | int word_index = __ffs(vcpu->arch.irq_summary); |
1631 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1632 | int irq = word_index * BITS_PER_LONG + bit_index; |
1633 | ||
ad312c7c ZX |
1634 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1635 | if (!vcpu->arch.irq_pending[word_index]) | |
1636 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1637 | svm_inject_irq(svm, irq); |
1638 | } | |
1639 | ||
04d2cc77 | 1640 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1641 | struct kvm_run *kvm_run) |
1642 | { | |
04d2cc77 | 1643 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1644 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1645 | |
ad312c7c | 1646 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1647 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1648 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1649 | |
ad312c7c | 1650 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1651 | /* |
1652 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1653 | */ | |
85f455f7 | 1654 | svm_do_inject_vector(svm); |
c1150d8c DL |
1655 | |
1656 | /* | |
1657 | * Interrupts blocked. Wait for unblock. | |
1658 | */ | |
ad312c7c ZX |
1659 | if (!svm->vcpu.arch.interrupt_window_open && |
1660 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
c1150d8c | 1661 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1662 | else |
c1150d8c DL |
1663 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1664 | } | |
1665 | ||
cbc94022 IE |
1666 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1667 | { | |
1668 | return 0; | |
1669 | } | |
1670 | ||
6aa8b732 AK |
1671 | static void save_db_regs(unsigned long *db_regs) |
1672 | { | |
5aff458e AK |
1673 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1674 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1675 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1676 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1677 | } |
1678 | ||
1679 | static void load_db_regs(unsigned long *db_regs) | |
1680 | { | |
5aff458e AK |
1681 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1682 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1683 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1684 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1685 | } |
1686 | ||
d9e368d6 AK |
1687 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1688 | { | |
1689 | force_new_asid(vcpu); | |
1690 | } | |
1691 | ||
04d2cc77 AK |
1692 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1693 | { | |
1694 | } | |
1695 | ||
d7bf8221 JR |
1696 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
1697 | { | |
1698 | struct vcpu_svm *svm = to_svm(vcpu); | |
1699 | ||
1700 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
1701 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
1702 | kvm_lapic_set_tpr(vcpu, cr8); | |
1703 | } | |
1704 | } | |
1705 | ||
649d6864 JR |
1706 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
1707 | { | |
1708 | struct vcpu_svm *svm = to_svm(vcpu); | |
1709 | u64 cr8; | |
1710 | ||
1711 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1712 | return; | |
1713 | ||
1714 | cr8 = kvm_get_cr8(vcpu); | |
1715 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
1716 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
1717 | } | |
1718 | ||
80e31d4f AK |
1719 | #ifdef CONFIG_X86_64 |
1720 | #define R "r" | |
1721 | #else | |
1722 | #define R "e" | |
1723 | #endif | |
1724 | ||
04d2cc77 | 1725 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 1726 | { |
a2fa3e9f | 1727 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1728 | u16 fs_selector; |
1729 | u16 gs_selector; | |
1730 | u16 ldt_selector; | |
d9e368d6 | 1731 | |
5fdbf976 MT |
1732 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
1733 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
1734 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
1735 | ||
e756fc62 | 1736 | pre_svm_run(svm); |
6aa8b732 | 1737 | |
649d6864 JR |
1738 | sync_lapic_to_cr8(vcpu); |
1739 | ||
6aa8b732 | 1740 | save_host_msrs(vcpu); |
d6e88aec AK |
1741 | fs_selector = kvm_read_fs(); |
1742 | gs_selector = kvm_read_gs(); | |
1743 | ldt_selector = kvm_read_ldt(); | |
a2fa3e9f GH |
1744 | svm->host_cr2 = kvm_read_cr2(); |
1745 | svm->host_dr6 = read_dr6(); | |
1746 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1747 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
1748 | /* required for live migration with NPT */ |
1749 | if (npt_enabled) | |
1750 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 1751 | |
a2fa3e9f | 1752 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1753 | write_dr7(0); |
a2fa3e9f GH |
1754 | save_db_regs(svm->host_db_regs); |
1755 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1756 | } |
36241b8c | 1757 | |
04d2cc77 AK |
1758 | clgi(); |
1759 | ||
1760 | local_irq_enable(); | |
36241b8c | 1761 | |
6aa8b732 | 1762 | asm volatile ( |
80e31d4f AK |
1763 | "push %%"R"bp; \n\t" |
1764 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
1765 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
1766 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
1767 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
1768 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
1769 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 1770 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1771 | "mov %c[r8](%[svm]), %%r8 \n\t" |
1772 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1773 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1774 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1775 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1776 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1777 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1778 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
1779 | #endif |
1780 | ||
6aa8b732 | 1781 | /* Enter guest mode */ |
80e31d4f AK |
1782 | "push %%"R"ax \n\t" |
1783 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
1784 | __ex(SVM_VMLOAD) "\n\t" |
1785 | __ex(SVM_VMRUN) "\n\t" | |
1786 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 1787 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
1788 | |
1789 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
1790 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
1791 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
1792 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
1793 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
1794 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
1795 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 1796 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1797 | "mov %%r8, %c[r8](%[svm]) \n\t" |
1798 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1799 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1800 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1801 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1802 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1803 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1804 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1805 | #endif |
80e31d4f | 1806 | "pop %%"R"bp" |
6aa8b732 | 1807 | : |
fb3f0f51 | 1808 | : [svm]"a"(svm), |
6aa8b732 | 1809 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1810 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1811 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1812 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1813 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1814 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1815 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1816 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1817 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1818 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1819 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1820 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1821 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1822 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1823 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1824 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1825 | #endif |
54a08c04 | 1826 | : "cc", "memory" |
80e31d4f | 1827 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 1828 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
1829 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
1830 | #endif | |
1831 | ); | |
6aa8b732 | 1832 | |
a2fa3e9f GH |
1833 | if ((svm->vmcb->save.dr7 & 0xff)) |
1834 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1835 | |
ad312c7c | 1836 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5fdbf976 MT |
1837 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
1838 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
1839 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
6aa8b732 | 1840 | |
a2fa3e9f GH |
1841 | write_dr6(svm->host_dr6); |
1842 | write_dr7(svm->host_dr7); | |
1843 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 | 1844 | |
d6e88aec AK |
1845 | kvm_load_fs(fs_selector); |
1846 | kvm_load_gs(gs_selector); | |
1847 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
1848 | load_host_msrs(vcpu); |
1849 | ||
1850 | reload_tss(vcpu); | |
1851 | ||
56ba47dd AK |
1852 | local_irq_disable(); |
1853 | ||
1854 | stgi(); | |
1855 | ||
d7bf8221 JR |
1856 | sync_cr8_to_lapic(vcpu); |
1857 | ||
a2fa3e9f | 1858 | svm->next_rip = 0; |
6aa8b732 AK |
1859 | } |
1860 | ||
80e31d4f AK |
1861 | #undef R |
1862 | ||
6aa8b732 AK |
1863 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1864 | { | |
a2fa3e9f GH |
1865 | struct vcpu_svm *svm = to_svm(vcpu); |
1866 | ||
709ddebf JR |
1867 | if (npt_enabled) { |
1868 | svm->vmcb->control.nested_cr3 = root; | |
1869 | force_new_asid(vcpu); | |
1870 | return; | |
1871 | } | |
1872 | ||
a2fa3e9f | 1873 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 1874 | force_new_asid(vcpu); |
7807fa6c AL |
1875 | |
1876 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1877 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1878 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1879 | vcpu->fpu_active = 0; |
1880 | } | |
6aa8b732 AK |
1881 | } |
1882 | ||
6aa8b732 AK |
1883 | static int is_disabled(void) |
1884 | { | |
6031a61c JR |
1885 | u64 vm_cr; |
1886 | ||
1887 | rdmsrl(MSR_VM_CR, vm_cr); | |
1888 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1889 | return 1; | |
1890 | ||
6aa8b732 AK |
1891 | return 0; |
1892 | } | |
1893 | ||
102d8325 IM |
1894 | static void |
1895 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1896 | { | |
1897 | /* | |
1898 | * Patch in the VMMCALL instruction: | |
1899 | */ | |
1900 | hypercall[0] = 0x0f; | |
1901 | hypercall[1] = 0x01; | |
1902 | hypercall[2] = 0xd9; | |
102d8325 IM |
1903 | } |
1904 | ||
002c7f7c YS |
1905 | static void svm_check_processor_compat(void *rtn) |
1906 | { | |
1907 | *(int *)rtn = 0; | |
1908 | } | |
1909 | ||
774ead3a AK |
1910 | static bool svm_cpu_has_accelerated_tpr(void) |
1911 | { | |
1912 | return false; | |
1913 | } | |
1914 | ||
67253af5 SY |
1915 | static int get_npt_level(void) |
1916 | { | |
1917 | #ifdef CONFIG_X86_64 | |
1918 | return PT64_ROOT_LEVEL; | |
1919 | #else | |
1920 | return PT32E_ROOT_LEVEL; | |
1921 | #endif | |
1922 | } | |
1923 | ||
64d4d521 SY |
1924 | static int svm_get_mt_mask_shift(void) |
1925 | { | |
1926 | return 0; | |
1927 | } | |
1928 | ||
cbdd1bea | 1929 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1930 | .cpu_has_kvm_support = has_svm, |
1931 | .disabled_by_bios = is_disabled, | |
1932 | .hardware_setup = svm_hardware_setup, | |
1933 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1934 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1935 | .hardware_enable = svm_hardware_enable, |
1936 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 1937 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
1938 | |
1939 | .vcpu_create = svm_create_vcpu, | |
1940 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1941 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1942 | |
04d2cc77 | 1943 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1944 | .vcpu_load = svm_vcpu_load, |
1945 | .vcpu_put = svm_vcpu_put, | |
1946 | ||
1947 | .set_guest_debug = svm_guest_debug, | |
1948 | .get_msr = svm_get_msr, | |
1949 | .set_msr = svm_set_msr, | |
1950 | .get_segment_base = svm_get_segment_base, | |
1951 | .get_segment = svm_get_segment, | |
1952 | .set_segment = svm_set_segment, | |
2e4d2653 | 1953 | .get_cpl = svm_get_cpl, |
1747fb71 | 1954 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1955 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1956 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1957 | .set_cr3 = svm_set_cr3, |
1958 | .set_cr4 = svm_set_cr4, | |
1959 | .set_efer = svm_set_efer, | |
1960 | .get_idt = svm_get_idt, | |
1961 | .set_idt = svm_set_idt, | |
1962 | .get_gdt = svm_get_gdt, | |
1963 | .set_gdt = svm_set_gdt, | |
1964 | .get_dr = svm_get_dr, | |
1965 | .set_dr = svm_set_dr, | |
6aa8b732 AK |
1966 | .get_rflags = svm_get_rflags, |
1967 | .set_rflags = svm_set_rflags, | |
1968 | ||
6aa8b732 | 1969 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1970 | |
6aa8b732 | 1971 | .run = svm_vcpu_run, |
04d2cc77 | 1972 | .handle_exit = handle_exit, |
6aa8b732 | 1973 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1974 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1975 | .get_irq = svm_get_irq, |
1976 | .set_irq = svm_set_irq, | |
298101da AK |
1977 | .queue_exception = svm_queue_exception, |
1978 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1979 | .inject_pending_irq = svm_intr_assist, |
1980 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1981 | |
1982 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 1983 | .get_tdp_level = get_npt_level, |
64d4d521 | 1984 | .get_mt_mask_shift = svm_get_mt_mask_shift, |
6aa8b732 AK |
1985 | }; |
1986 | ||
1987 | static int __init svm_init(void) | |
1988 | { | |
cb498ea2 | 1989 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1990 | THIS_MODULE); |
6aa8b732 AK |
1991 | } |
1992 | ||
1993 | static void __exit svm_exit(void) | |
1994 | { | |
cb498ea2 | 1995 | kvm_exit(); |
6aa8b732 AK |
1996 | } |
1997 | ||
1998 | module_init(svm_init) | |
1999 | module_exit(svm_exit) |