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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
44a95dae SS |
17 | |
18 | #define pr_fmt(fmt) "SVM: " fmt | |
19 | ||
edf88417 AK |
20 | #include <linux/kvm_host.h> |
21 | ||
85f455f7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
fe4c7b19 | 25 | #include "x86.h" |
66f7b72e | 26 | #include "cpuid.h" |
25462f7f | 27 | #include "pmu.h" |
e495606d | 28 | |
6aa8b732 | 29 | #include <linux/module.h> |
ae759544 | 30 | #include <linux/mod_devicetable.h> |
9d8f549d | 31 | #include <linux/kernel.h> |
6aa8b732 AK |
32 | #include <linux/vmalloc.h> |
33 | #include <linux/highmem.h> | |
e8edc6e0 | 34 | #include <linux/sched.h> |
af658dca | 35 | #include <linux/trace_events.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
6aa8b732 | 37 | |
1018faa6 | 38 | #include <asm/perf_event.h> |
67ec6607 | 39 | #include <asm/tlbflush.h> |
e495606d | 40 | #include <asm/desc.h> |
facb0139 | 41 | #include <asm/debugreg.h> |
631bc487 | 42 | #include <asm/kvm_para.h> |
6aa8b732 | 43 | |
63d1142f | 44 | #include <asm/virtext.h> |
229456fc | 45 | #include "trace.h" |
63d1142f | 46 | |
4ecac3fd AK |
47 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
48 | ||
6aa8b732 AK |
49 | MODULE_AUTHOR("Qumranet"); |
50 | MODULE_LICENSE("GPL"); | |
51 | ||
ae759544 JT |
52 | static const struct x86_cpu_id svm_cpu_id[] = { |
53 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
54 | {} | |
55 | }; | |
56 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
57 | ||
6aa8b732 AK |
58 | #define IOPM_ALLOC_ORDER 2 |
59 | #define MSRPM_ALLOC_ORDER 1 | |
60 | ||
6aa8b732 AK |
61 | #define SEG_TYPE_LDT 2 |
62 | #define SEG_TYPE_BUSY_TSS16 3 | |
63 | ||
6bc31bdc AP |
64 | #define SVM_FEATURE_NPT (1 << 0) |
65 | #define SVM_FEATURE_LBRV (1 << 1) | |
66 | #define SVM_FEATURE_SVML (1 << 2) | |
67 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
68 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
69 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
70 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
71 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 72 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 73 | |
340d3bc3 SS |
74 | #define SVM_AVIC_DOORBELL 0xc001011b |
75 | ||
410e4d57 JR |
76 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
77 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
78 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
79 | ||
24e09cbf JR |
80 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
81 | ||
fbc0db76 | 82 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
83 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
84 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 85 | |
44a95dae SS |
86 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) || 0xFFF) |
87 | ||
88 | /* | |
89 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
90 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
91 | */ | |
92 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
93 | ||
18f40c53 SS |
94 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 |
95 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
96 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
97 | ||
67ec6607 JR |
98 | static bool erratum_383_found __read_mostly; |
99 | ||
6c8166a7 AK |
100 | static const u32 host_save_user_msrs[] = { |
101 | #ifdef CONFIG_X86_64 | |
102 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
103 | MSR_FS_BASE, | |
104 | #endif | |
105 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 106 | MSR_TSC_AUX, |
6c8166a7 AK |
107 | }; |
108 | ||
109 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
110 | ||
111 | struct kvm_vcpu; | |
112 | ||
e6aa9abd JR |
113 | struct nested_state { |
114 | struct vmcb *hsave; | |
115 | u64 hsave_msr; | |
4a810181 | 116 | u64 vm_cr_msr; |
e6aa9abd JR |
117 | u64 vmcb; |
118 | ||
119 | /* These are the merged vectors */ | |
120 | u32 *msrpm; | |
121 | ||
122 | /* gpa pointers to the real vectors */ | |
123 | u64 vmcb_msrpm; | |
ce2ac085 | 124 | u64 vmcb_iopm; |
aad42c64 | 125 | |
cd3ff653 JR |
126 | /* A VMEXIT is required but not yet emulated */ |
127 | bool exit_required; | |
128 | ||
aad42c64 | 129 | /* cache for intercepts of the guest */ |
4ee546b4 | 130 | u32 intercept_cr; |
3aed041a | 131 | u32 intercept_dr; |
aad42c64 JR |
132 | u32 intercept_exceptions; |
133 | u64 intercept; | |
134 | ||
5bd2edc3 JR |
135 | /* Nested Paging related state */ |
136 | u64 nested_cr3; | |
e6aa9abd JR |
137 | }; |
138 | ||
323c3d80 JR |
139 | #define MSRPM_OFFSETS 16 |
140 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
141 | ||
2b036c6b BO |
142 | /* |
143 | * Set osvw_len to higher value when updated Revision Guides | |
144 | * are published and we know what the new status bits are | |
145 | */ | |
146 | static uint64_t osvw_len = 4, osvw_status; | |
147 | ||
6c8166a7 AK |
148 | struct vcpu_svm { |
149 | struct kvm_vcpu vcpu; | |
150 | struct vmcb *vmcb; | |
151 | unsigned long vmcb_pa; | |
152 | struct svm_cpu_data *svm_data; | |
153 | uint64_t asid_generation; | |
154 | uint64_t sysenter_esp; | |
155 | uint64_t sysenter_eip; | |
46896c73 | 156 | uint64_t tsc_aux; |
6c8166a7 AK |
157 | |
158 | u64 next_rip; | |
159 | ||
160 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 161 | struct { |
dacccfdd AK |
162 | u16 fs; |
163 | u16 gs; | |
164 | u16 ldt; | |
afe9e66f AK |
165 | u64 gs_base; |
166 | } host; | |
6c8166a7 AK |
167 | |
168 | u32 *msrpm; | |
6c8166a7 | 169 | |
bd3d1ec3 AK |
170 | ulong nmi_iret_rip; |
171 | ||
e6aa9abd | 172 | struct nested_state nested; |
6be7d306 JK |
173 | |
174 | bool nmi_singlestep; | |
66b7138f JK |
175 | |
176 | unsigned int3_injected; | |
177 | unsigned long int3_rip; | |
631bc487 | 178 | u32 apf_reason; |
fbc0db76 | 179 | |
6092d3d3 JR |
180 | /* cached guest cpuid flags for faster access */ |
181 | bool nrips_enabled : 1; | |
44a95dae | 182 | |
18f40c53 | 183 | u32 ldr_reg; |
44a95dae SS |
184 | struct page *avic_backing_page; |
185 | u64 *avic_physical_id_cache; | |
6c8166a7 AK |
186 | }; |
187 | ||
44a95dae SS |
188 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
189 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
190 | ||
191 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
192 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
193 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
194 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
195 | ||
fbc0db76 JR |
196 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
197 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
198 | ||
455716fa JR |
199 | #define MSR_INVALID 0xffffffffU |
200 | ||
09941fbb | 201 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
202 | u32 index; /* Index of the MSR */ |
203 | bool always; /* True if intercept is always on */ | |
204 | } direct_access_msrs[] = { | |
8c06585d | 205 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
206 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
207 | #ifdef CONFIG_X86_64 | |
208 | { .index = MSR_GS_BASE, .always = true }, | |
209 | { .index = MSR_FS_BASE, .always = true }, | |
210 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
211 | { .index = MSR_LSTAR, .always = true }, | |
212 | { .index = MSR_CSTAR, .always = true }, | |
213 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
214 | #endif | |
215 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
216 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
217 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
218 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
219 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
220 | }; |
221 | ||
709ddebf JR |
222 | /* enable NPT for AMD64 and X86 with PAE */ |
223 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
224 | static bool npt_enabled = true; | |
225 | #else | |
e0231715 | 226 | static bool npt_enabled; |
709ddebf | 227 | #endif |
6c7dac72 | 228 | |
e2358851 DB |
229 | /* allow nested paging (virtualized MMU) for all guests */ |
230 | static int npt = true; | |
6c7dac72 | 231 | module_param(npt, int, S_IRUGO); |
e3da3acd | 232 | |
e2358851 DB |
233 | /* allow nested virtualization in KVM/SVM */ |
234 | static int nested = true; | |
236de055 AG |
235 | module_param(nested, int, S_IRUGO); |
236 | ||
44a95dae SS |
237 | /* enable / disable AVIC */ |
238 | static int avic; | |
239 | module_param(avic, int, S_IRUGO); | |
240 | ||
79a8059d | 241 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
44874f84 | 242 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 243 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 244 | |
410e4d57 | 245 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 246 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 247 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
248 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
249 | bool has_error_code, u32 error_code); | |
250 | ||
8d28fec4 | 251 | enum { |
116a0a23 JR |
252 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
253 | pause filter count */ | |
f56838e4 | 254 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 255 | VMCB_ASID, /* ASID */ |
decdbf6a | 256 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 257 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 258 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 259 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 260 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 261 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 262 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 263 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
264 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
265 | * AVIC PHYSICAL_TABLE pointer, | |
266 | * AVIC LOGICAL_TABLE pointer | |
267 | */ | |
8d28fec4 RJ |
268 | VMCB_DIRTY_MAX, |
269 | }; | |
270 | ||
0574dec0 JR |
271 | /* TPR and CR2 are always written before VMRUN */ |
272 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 273 | |
44a95dae SS |
274 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
275 | ||
8d28fec4 RJ |
276 | static inline void mark_all_dirty(struct vmcb *vmcb) |
277 | { | |
278 | vmcb->control.clean = 0; | |
279 | } | |
280 | ||
281 | static inline void mark_all_clean(struct vmcb *vmcb) | |
282 | { | |
283 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
284 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
285 | } | |
286 | ||
287 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
288 | { | |
289 | vmcb->control.clean &= ~(1 << bit); | |
290 | } | |
291 | ||
a2fa3e9f GH |
292 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
293 | { | |
fb3f0f51 | 294 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
295 | } |
296 | ||
44a95dae SS |
297 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
298 | { | |
299 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
300 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
301 | } | |
302 | ||
340d3bc3 SS |
303 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
304 | { | |
305 | struct vcpu_svm *svm = to_svm(vcpu); | |
306 | u64 *entry = svm->avic_physical_id_cache; | |
307 | ||
308 | if (!entry) | |
309 | return false; | |
310 | ||
311 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
312 | } | |
313 | ||
384c6368 JR |
314 | static void recalc_intercepts(struct vcpu_svm *svm) |
315 | { | |
316 | struct vmcb_control_area *c, *h; | |
317 | struct nested_state *g; | |
318 | ||
116a0a23 JR |
319 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
320 | ||
384c6368 JR |
321 | if (!is_guest_mode(&svm->vcpu)) |
322 | return; | |
323 | ||
324 | c = &svm->vmcb->control; | |
325 | h = &svm->nested.hsave->control; | |
326 | g = &svm->nested; | |
327 | ||
4ee546b4 | 328 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 329 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
330 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
331 | c->intercept = h->intercept | g->intercept; | |
332 | } | |
333 | ||
4ee546b4 RJ |
334 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
335 | { | |
336 | if (is_guest_mode(&svm->vcpu)) | |
337 | return svm->nested.hsave; | |
338 | else | |
339 | return svm->vmcb; | |
340 | } | |
341 | ||
342 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
343 | { | |
344 | struct vmcb *vmcb = get_host_vmcb(svm); | |
345 | ||
346 | vmcb->control.intercept_cr |= (1U << bit); | |
347 | ||
348 | recalc_intercepts(svm); | |
349 | } | |
350 | ||
351 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
352 | { | |
353 | struct vmcb *vmcb = get_host_vmcb(svm); | |
354 | ||
355 | vmcb->control.intercept_cr &= ~(1U << bit); | |
356 | ||
357 | recalc_intercepts(svm); | |
358 | } | |
359 | ||
360 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
361 | { | |
362 | struct vmcb *vmcb = get_host_vmcb(svm); | |
363 | ||
364 | return vmcb->control.intercept_cr & (1U << bit); | |
365 | } | |
366 | ||
5315c716 | 367 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
368 | { |
369 | struct vmcb *vmcb = get_host_vmcb(svm); | |
370 | ||
5315c716 PB |
371 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
372 | | (1 << INTERCEPT_DR1_READ) | |
373 | | (1 << INTERCEPT_DR2_READ) | |
374 | | (1 << INTERCEPT_DR3_READ) | |
375 | | (1 << INTERCEPT_DR4_READ) | |
376 | | (1 << INTERCEPT_DR5_READ) | |
377 | | (1 << INTERCEPT_DR6_READ) | |
378 | | (1 << INTERCEPT_DR7_READ) | |
379 | | (1 << INTERCEPT_DR0_WRITE) | |
380 | | (1 << INTERCEPT_DR1_WRITE) | |
381 | | (1 << INTERCEPT_DR2_WRITE) | |
382 | | (1 << INTERCEPT_DR3_WRITE) | |
383 | | (1 << INTERCEPT_DR4_WRITE) | |
384 | | (1 << INTERCEPT_DR5_WRITE) | |
385 | | (1 << INTERCEPT_DR6_WRITE) | |
386 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
387 | |
388 | recalc_intercepts(svm); | |
389 | } | |
390 | ||
5315c716 | 391 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
392 | { |
393 | struct vmcb *vmcb = get_host_vmcb(svm); | |
394 | ||
5315c716 | 395 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
396 | |
397 | recalc_intercepts(svm); | |
398 | } | |
399 | ||
18c918c5 JR |
400 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
401 | { | |
402 | struct vmcb *vmcb = get_host_vmcb(svm); | |
403 | ||
404 | vmcb->control.intercept_exceptions |= (1U << bit); | |
405 | ||
406 | recalc_intercepts(svm); | |
407 | } | |
408 | ||
409 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
410 | { | |
411 | struct vmcb *vmcb = get_host_vmcb(svm); | |
412 | ||
413 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
414 | ||
415 | recalc_intercepts(svm); | |
416 | } | |
417 | ||
8a05a1b8 JR |
418 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
419 | { | |
420 | struct vmcb *vmcb = get_host_vmcb(svm); | |
421 | ||
422 | vmcb->control.intercept |= (1ULL << bit); | |
423 | ||
424 | recalc_intercepts(svm); | |
425 | } | |
426 | ||
427 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
428 | { | |
429 | struct vmcb *vmcb = get_host_vmcb(svm); | |
430 | ||
431 | vmcb->control.intercept &= ~(1ULL << bit); | |
432 | ||
433 | recalc_intercepts(svm); | |
434 | } | |
435 | ||
2af9194d JR |
436 | static inline void enable_gif(struct vcpu_svm *svm) |
437 | { | |
438 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
439 | } | |
440 | ||
441 | static inline void disable_gif(struct vcpu_svm *svm) | |
442 | { | |
443 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
444 | } | |
445 | ||
446 | static inline bool gif_set(struct vcpu_svm *svm) | |
447 | { | |
448 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
449 | } | |
450 | ||
4866d5e3 | 451 | static unsigned long iopm_base; |
6aa8b732 AK |
452 | |
453 | struct kvm_ldttss_desc { | |
454 | u16 limit0; | |
455 | u16 base0; | |
e0231715 JR |
456 | unsigned base1:8, type:5, dpl:2, p:1; |
457 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
458 | u32 base3; |
459 | u32 zero1; | |
460 | } __attribute__((packed)); | |
461 | ||
462 | struct svm_cpu_data { | |
463 | int cpu; | |
464 | ||
5008fdf5 AK |
465 | u64 asid_generation; |
466 | u32 max_asid; | |
467 | u32 next_asid; | |
6aa8b732 AK |
468 | struct kvm_ldttss_desc *tss_desc; |
469 | ||
470 | struct page *save_area; | |
471 | }; | |
472 | ||
473 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
474 | ||
475 | struct svm_init_data { | |
476 | int cpu; | |
477 | int r; | |
478 | }; | |
479 | ||
09941fbb | 480 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 481 | |
9d8f549d | 482 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
483 | #define MSRS_RANGE_SIZE 2048 |
484 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
485 | ||
455716fa JR |
486 | static u32 svm_msrpm_offset(u32 msr) |
487 | { | |
488 | u32 offset; | |
489 | int i; | |
490 | ||
491 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
492 | if (msr < msrpm_ranges[i] || | |
493 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
494 | continue; | |
495 | ||
496 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
497 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
498 | ||
499 | /* Now we have the u8 offset - but need the u32 offset */ | |
500 | return offset / 4; | |
501 | } | |
502 | ||
503 | /* MSR not in any range */ | |
504 | return MSR_INVALID; | |
505 | } | |
506 | ||
6aa8b732 AK |
507 | #define MAX_INST_SIZE 15 |
508 | ||
6aa8b732 AK |
509 | static inline void clgi(void) |
510 | { | |
4ecac3fd | 511 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
512 | } |
513 | ||
514 | static inline void stgi(void) | |
515 | { | |
4ecac3fd | 516 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
517 | } |
518 | ||
519 | static inline void invlpga(unsigned long addr, u32 asid) | |
520 | { | |
e0231715 | 521 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
522 | } |
523 | ||
4b16184c JR |
524 | static int get_npt_level(void) |
525 | { | |
526 | #ifdef CONFIG_X86_64 | |
527 | return PT64_ROOT_LEVEL; | |
528 | #else | |
529 | return PT32E_ROOT_LEVEL; | |
530 | #endif | |
531 | } | |
532 | ||
6aa8b732 AK |
533 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
534 | { | |
6dc696d4 | 535 | vcpu->arch.efer = efer; |
709ddebf | 536 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 537 | efer &= ~EFER_LME; |
6aa8b732 | 538 | |
9962d032 | 539 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 540 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
541 | } |
542 | ||
6aa8b732 AK |
543 | static int is_external_interrupt(u32 info) |
544 | { | |
545 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
546 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
547 | } | |
548 | ||
37ccdcbe | 549 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
550 | { |
551 | struct vcpu_svm *svm = to_svm(vcpu); | |
552 | u32 ret = 0; | |
553 | ||
554 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
555 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
556 | return ret; | |
2809f5d2 GC |
557 | } |
558 | ||
559 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
560 | { | |
561 | struct vcpu_svm *svm = to_svm(vcpu); | |
562 | ||
563 | if (mask == 0) | |
564 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
565 | else | |
566 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
567 | ||
568 | } | |
569 | ||
6aa8b732 AK |
570 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
571 | { | |
a2fa3e9f GH |
572 | struct vcpu_svm *svm = to_svm(vcpu); |
573 | ||
f104765b | 574 | if (svm->vmcb->control.next_rip != 0) { |
d2922422 | 575 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 576 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 577 | } |
6bc31bdc | 578 | |
a2fa3e9f | 579 | if (!svm->next_rip) { |
51d8b661 | 580 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
581 | EMULATE_DONE) |
582 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
583 | return; |
584 | } | |
5fdbf976 MT |
585 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
586 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
587 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 588 | |
5fdbf976 | 589 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 590 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
591 | } |
592 | ||
116a4752 | 593 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
594 | bool has_error_code, u32 error_code, |
595 | bool reinject) | |
116a4752 JK |
596 | { |
597 | struct vcpu_svm *svm = to_svm(vcpu); | |
598 | ||
e0231715 JR |
599 | /* |
600 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
601 | * handle the exception | |
602 | */ | |
ce7ddec4 JR |
603 | if (!reinject && |
604 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
605 | return; |
606 | ||
2a6b20b8 | 607 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
608 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
609 | ||
610 | /* | |
611 | * For guest debugging where we have to reinject #BP if some | |
612 | * INT3 is guest-owned: | |
613 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
614 | * raises a fault that is not intercepted. Still better than | |
615 | * failing in all cases. | |
616 | */ | |
617 | skip_emulated_instruction(&svm->vcpu); | |
618 | rip = kvm_rip_read(&svm->vcpu); | |
619 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
620 | svm->int3_injected = rip - old_rip; | |
621 | } | |
622 | ||
116a4752 JK |
623 | svm->vmcb->control.event_inj = nr |
624 | | SVM_EVTINJ_VALID | |
625 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
626 | | SVM_EVTINJ_TYPE_EXEPT; | |
627 | svm->vmcb->control.event_inj_err = error_code; | |
628 | } | |
629 | ||
67ec6607 JR |
630 | static void svm_init_erratum_383(void) |
631 | { | |
632 | u32 low, high; | |
633 | int err; | |
634 | u64 val; | |
635 | ||
e6ee94d5 | 636 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
637 | return; |
638 | ||
639 | /* Use _safe variants to not break nested virtualization */ | |
640 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
641 | if (err) | |
642 | return; | |
643 | ||
644 | val |= (1ULL << 47); | |
645 | ||
646 | low = lower_32_bits(val); | |
647 | high = upper_32_bits(val); | |
648 | ||
649 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
650 | ||
651 | erratum_383_found = true; | |
652 | } | |
653 | ||
2b036c6b BO |
654 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
655 | { | |
656 | /* | |
657 | * Guests should see errata 400 and 415 as fixed (assuming that | |
658 | * HLT and IO instructions are intercepted). | |
659 | */ | |
660 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
661 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
662 | ||
663 | /* | |
664 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
665 | * all osvw.status bits inside that length, including bit 0 (which is | |
666 | * reserved for erratum 298), are valid. However, if host processor's | |
667 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
668 | * be conservative here and therefore we tell the guest that erratum 298 | |
669 | * is present (because we really don't know). | |
670 | */ | |
671 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
672 | vcpu->arch.osvw.status |= 1; | |
673 | } | |
674 | ||
6aa8b732 AK |
675 | static int has_svm(void) |
676 | { | |
63d1142f | 677 | const char *msg; |
6aa8b732 | 678 | |
63d1142f | 679 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 680 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
681 | return 0; |
682 | } | |
683 | ||
6aa8b732 AK |
684 | return 1; |
685 | } | |
686 | ||
13a34e06 | 687 | static void svm_hardware_disable(void) |
6aa8b732 | 688 | { |
fbc0db76 JR |
689 | /* Make sure we clean up behind us */ |
690 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
691 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
692 | ||
2c8dceeb | 693 | cpu_svm_disable(); |
1018faa6 JR |
694 | |
695 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
696 | } |
697 | ||
13a34e06 | 698 | static int svm_hardware_enable(void) |
6aa8b732 AK |
699 | { |
700 | ||
0fe1e009 | 701 | struct svm_cpu_data *sd; |
6aa8b732 | 702 | uint64_t efer; |
89a27f4d | 703 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
704 | struct desc_struct *gdt; |
705 | int me = raw_smp_processor_id(); | |
706 | ||
10474ae8 AG |
707 | rdmsrl(MSR_EFER, efer); |
708 | if (efer & EFER_SVME) | |
709 | return -EBUSY; | |
710 | ||
6aa8b732 | 711 | if (!has_svm()) { |
1f5b77f5 | 712 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 713 | return -EINVAL; |
6aa8b732 | 714 | } |
0fe1e009 | 715 | sd = per_cpu(svm_data, me); |
0fe1e009 | 716 | if (!sd) { |
1f5b77f5 | 717 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 718 | return -EINVAL; |
6aa8b732 AK |
719 | } |
720 | ||
0fe1e009 TH |
721 | sd->asid_generation = 1; |
722 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
723 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 724 | |
d6ab1ed4 | 725 | native_store_gdt(&gdt_descr); |
89a27f4d | 726 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 727 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 728 | |
9962d032 | 729 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 730 | |
d0316554 | 731 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 732 | |
fbc0db76 JR |
733 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
734 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 735 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
736 | } |
737 | ||
2b036c6b BO |
738 | |
739 | /* | |
740 | * Get OSVW bits. | |
741 | * | |
742 | * Note that it is possible to have a system with mixed processor | |
743 | * revisions and therefore different OSVW bits. If bits are not the same | |
744 | * on different processors then choose the worst case (i.e. if erratum | |
745 | * is present on one processor and not on another then assume that the | |
746 | * erratum is present everywhere). | |
747 | */ | |
748 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
749 | uint64_t len, status = 0; | |
750 | int err; | |
751 | ||
752 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
753 | if (!err) | |
754 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
755 | &err); | |
756 | ||
757 | if (err) | |
758 | osvw_status = osvw_len = 0; | |
759 | else { | |
760 | if (len < osvw_len) | |
761 | osvw_len = len; | |
762 | osvw_status |= status; | |
763 | osvw_status &= (1ULL << osvw_len) - 1; | |
764 | } | |
765 | } else | |
766 | osvw_status = osvw_len = 0; | |
767 | ||
67ec6607 JR |
768 | svm_init_erratum_383(); |
769 | ||
1018faa6 JR |
770 | amd_pmu_enable_virt(); |
771 | ||
10474ae8 | 772 | return 0; |
6aa8b732 AK |
773 | } |
774 | ||
0da1db75 JR |
775 | static void svm_cpu_uninit(int cpu) |
776 | { | |
0fe1e009 | 777 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 778 | |
0fe1e009 | 779 | if (!sd) |
0da1db75 JR |
780 | return; |
781 | ||
782 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
783 | __free_page(sd->save_area); |
784 | kfree(sd); | |
0da1db75 JR |
785 | } |
786 | ||
6aa8b732 AK |
787 | static int svm_cpu_init(int cpu) |
788 | { | |
0fe1e009 | 789 | struct svm_cpu_data *sd; |
6aa8b732 AK |
790 | int r; |
791 | ||
0fe1e009 TH |
792 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
793 | if (!sd) | |
6aa8b732 | 794 | return -ENOMEM; |
0fe1e009 TH |
795 | sd->cpu = cpu; |
796 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 797 | r = -ENOMEM; |
0fe1e009 | 798 | if (!sd->save_area) |
6aa8b732 AK |
799 | goto err_1; |
800 | ||
0fe1e009 | 801 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
802 | |
803 | return 0; | |
804 | ||
805 | err_1: | |
0fe1e009 | 806 | kfree(sd); |
6aa8b732 AK |
807 | return r; |
808 | ||
809 | } | |
810 | ||
ac72a9b7 JR |
811 | static bool valid_msr_intercept(u32 index) |
812 | { | |
813 | int i; | |
814 | ||
815 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
816 | if (direct_access_msrs[i].index == index) | |
817 | return true; | |
818 | ||
819 | return false; | |
820 | } | |
821 | ||
bfc733a7 RR |
822 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
823 | int read, int write) | |
6aa8b732 | 824 | { |
455716fa JR |
825 | u8 bit_read, bit_write; |
826 | unsigned long tmp; | |
827 | u32 offset; | |
6aa8b732 | 828 | |
ac72a9b7 JR |
829 | /* |
830 | * If this warning triggers extend the direct_access_msrs list at the | |
831 | * beginning of the file | |
832 | */ | |
833 | WARN_ON(!valid_msr_intercept(msr)); | |
834 | ||
455716fa JR |
835 | offset = svm_msrpm_offset(msr); |
836 | bit_read = 2 * (msr & 0x0f); | |
837 | bit_write = 2 * (msr & 0x0f) + 1; | |
838 | tmp = msrpm[offset]; | |
839 | ||
840 | BUG_ON(offset == MSR_INVALID); | |
841 | ||
842 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
843 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
844 | ||
845 | msrpm[offset] = tmp; | |
6aa8b732 AK |
846 | } |
847 | ||
f65c229c | 848 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
849 | { |
850 | int i; | |
851 | ||
f65c229c JR |
852 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
853 | ||
ac72a9b7 JR |
854 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
855 | if (!direct_access_msrs[i].always) | |
856 | continue; | |
857 | ||
858 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
859 | } | |
f65c229c JR |
860 | } |
861 | ||
323c3d80 JR |
862 | static void add_msr_offset(u32 offset) |
863 | { | |
864 | int i; | |
865 | ||
866 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
867 | ||
868 | /* Offset already in list? */ | |
869 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 870 | return; |
323c3d80 JR |
871 | |
872 | /* Slot used by another offset? */ | |
873 | if (msrpm_offsets[i] != MSR_INVALID) | |
874 | continue; | |
875 | ||
876 | /* Add offset to list */ | |
877 | msrpm_offsets[i] = offset; | |
878 | ||
879 | return; | |
6aa8b732 | 880 | } |
323c3d80 JR |
881 | |
882 | /* | |
883 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
884 | * increase MSRPM_OFFSETS in this case. | |
885 | */ | |
bfc733a7 | 886 | BUG(); |
6aa8b732 AK |
887 | } |
888 | ||
323c3d80 | 889 | static void init_msrpm_offsets(void) |
f65c229c | 890 | { |
323c3d80 | 891 | int i; |
f65c229c | 892 | |
323c3d80 JR |
893 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
894 | ||
895 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
896 | u32 offset; | |
897 | ||
898 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
899 | BUG_ON(offset == MSR_INVALID); | |
900 | ||
901 | add_msr_offset(offset); | |
902 | } | |
f65c229c JR |
903 | } |
904 | ||
24e09cbf JR |
905 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
906 | { | |
907 | u32 *msrpm = svm->msrpm; | |
908 | ||
909 | svm->vmcb->control.lbr_ctl = 1; | |
910 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
911 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
912 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
913 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
914 | } | |
915 | ||
916 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
917 | { | |
918 | u32 *msrpm = svm->msrpm; | |
919 | ||
920 | svm->vmcb->control.lbr_ctl = 0; | |
921 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
922 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
923 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
924 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
925 | } | |
926 | ||
6aa8b732 AK |
927 | static __init int svm_hardware_setup(void) |
928 | { | |
929 | int cpu; | |
930 | struct page *iopm_pages; | |
f65c229c | 931 | void *iopm_va; |
6aa8b732 AK |
932 | int r; |
933 | ||
6aa8b732 AK |
934 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
935 | ||
936 | if (!iopm_pages) | |
937 | return -ENOMEM; | |
c8681339 AL |
938 | |
939 | iopm_va = page_address(iopm_pages); | |
940 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
941 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
942 | ||
323c3d80 JR |
943 | init_msrpm_offsets(); |
944 | ||
50a37eb4 JR |
945 | if (boot_cpu_has(X86_FEATURE_NX)) |
946 | kvm_enable_efer_bits(EFER_NX); | |
947 | ||
1b2fd70c AG |
948 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
949 | kvm_enable_efer_bits(EFER_FFXSR); | |
950 | ||
92a1f12d | 951 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 952 | kvm_has_tsc_control = true; |
bc9b961b HZ |
953 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
954 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
955 | } |
956 | ||
236de055 AG |
957 | if (nested) { |
958 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 959 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
960 | } |
961 | ||
3230bb47 | 962 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
963 | r = svm_cpu_init(cpu); |
964 | if (r) | |
f65c229c | 965 | goto err; |
6aa8b732 | 966 | } |
33bd6a0b | 967 | |
2a6b20b8 | 968 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
969 | npt_enabled = false; |
970 | ||
6c7dac72 JR |
971 | if (npt_enabled && !npt) { |
972 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
973 | npt_enabled = false; | |
974 | } | |
975 | ||
18552672 | 976 | if (npt_enabled) { |
e3da3acd | 977 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 978 | kvm_enable_tdp(); |
5f4cb662 JR |
979 | } else |
980 | kvm_disable_tdp(); | |
e3da3acd | 981 | |
44a95dae SS |
982 | if (avic && (!npt_enabled || !boot_cpu_has(X86_FEATURE_AVIC))) |
983 | avic = false; | |
984 | ||
985 | if (avic) | |
986 | pr_info("AVIC enabled\n"); | |
987 | ||
6aa8b732 AK |
988 | return 0; |
989 | ||
f65c229c | 990 | err: |
6aa8b732 AK |
991 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
992 | iopm_base = 0; | |
993 | return r; | |
994 | } | |
995 | ||
996 | static __exit void svm_hardware_unsetup(void) | |
997 | { | |
0da1db75 JR |
998 | int cpu; |
999 | ||
3230bb47 | 1000 | for_each_possible_cpu(cpu) |
0da1db75 JR |
1001 | svm_cpu_uninit(cpu); |
1002 | ||
6aa8b732 | 1003 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 1004 | iopm_base = 0; |
6aa8b732 AK |
1005 | } |
1006 | ||
1007 | static void init_seg(struct vmcb_seg *seg) | |
1008 | { | |
1009 | seg->selector = 0; | |
1010 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1011 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1012 | seg->limit = 0xffff; |
1013 | seg->base = 0; | |
1014 | } | |
1015 | ||
1016 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1017 | { | |
1018 | seg->selector = 0; | |
1019 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1020 | seg->limit = 0xffff; | |
1021 | seg->base = 0; | |
1022 | } | |
1023 | ||
ba904635 WA |
1024 | static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu) |
1025 | { | |
1026 | struct vcpu_svm *svm = to_svm(vcpu); | |
1027 | ||
1028 | return svm->vmcb->control.tsc_offset; | |
1029 | } | |
1030 | ||
f4e1b3c8 ZA |
1031 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1032 | { | |
1033 | struct vcpu_svm *svm = to_svm(vcpu); | |
1034 | u64 g_tsc_offset = 0; | |
1035 | ||
2030753d | 1036 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1037 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1038 | svm->nested.hsave->control.tsc_offset; | |
1039 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
1040 | } else |
1041 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1042 | svm->vmcb->control.tsc_offset, | |
1043 | offset); | |
f4e1b3c8 ZA |
1044 | |
1045 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1046 | |
1047 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1048 | } |
1049 | ||
58ea6767 | 1050 | static void svm_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment) |
e48672fa ZA |
1051 | { |
1052 | struct vcpu_svm *svm = to_svm(vcpu); | |
1053 | ||
1054 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 1055 | if (is_guest_mode(vcpu)) |
e48672fa | 1056 | svm->nested.hsave->control.tsc_offset += adjustment; |
489223ed YY |
1057 | else |
1058 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1059 | svm->vmcb->control.tsc_offset - adjustment, | |
1060 | svm->vmcb->control.tsc_offset); | |
1061 | ||
116a0a23 | 1062 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
1063 | } |
1064 | ||
44a95dae SS |
1065 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1066 | { | |
1067 | struct vmcb *vmcb = svm->vmcb; | |
1068 | struct kvm_arch *vm_data = &svm->vcpu.kvm->arch; | |
1069 | phys_addr_t bpa = page_to_phys(svm->avic_backing_page); | |
1070 | phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page); | |
1071 | phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page); | |
1072 | ||
1073 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1074 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1075 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1076 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
1077 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
1078 | svm->vcpu.arch.apicv_active = true; | |
1079 | } | |
1080 | ||
5690891b | 1081 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1082 | { |
e6101a96 JR |
1083 | struct vmcb_control_area *control = &svm->vmcb->control; |
1084 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1085 | |
bff78274 | 1086 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 1087 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1088 | |
4ee546b4 RJ |
1089 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1090 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1091 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1092 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1093 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1094 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
1095 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1096 | |
5315c716 | 1097 | set_dr_intercepts(svm); |
6aa8b732 | 1098 | |
18c918c5 JR |
1099 | set_exception_intercept(svm, PF_VECTOR); |
1100 | set_exception_intercept(svm, UD_VECTOR); | |
1101 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1102 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1103 | set_exception_intercept(svm, DB_VECTOR); |
6aa8b732 | 1104 | |
8a05a1b8 JR |
1105 | set_intercept(svm, INTERCEPT_INTR); |
1106 | set_intercept(svm, INTERCEPT_NMI); | |
1107 | set_intercept(svm, INTERCEPT_SMI); | |
1108 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1109 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1110 | set_intercept(svm, INTERCEPT_CPUID); |
1111 | set_intercept(svm, INTERCEPT_INVD); | |
1112 | set_intercept(svm, INTERCEPT_HLT); | |
1113 | set_intercept(svm, INTERCEPT_INVLPG); | |
1114 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1115 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1116 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1117 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1118 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1119 | set_intercept(svm, INTERCEPT_VMRUN); | |
1120 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1121 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1122 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1123 | set_intercept(svm, INTERCEPT_STGI); | |
1124 | set_intercept(svm, INTERCEPT_CLGI); | |
1125 | set_intercept(svm, INTERCEPT_SKINIT); | |
1126 | set_intercept(svm, INTERCEPT_WBINVD); | |
1127 | set_intercept(svm, INTERCEPT_MONITOR); | |
1128 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 1129 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
1130 | |
1131 | control->iopm_base_pa = iopm_base; | |
f65c229c | 1132 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1133 | control->int_ctl = V_INTR_MASKING_MASK; |
1134 | ||
1135 | init_seg(&save->es); | |
1136 | init_seg(&save->ss); | |
1137 | init_seg(&save->ds); | |
1138 | init_seg(&save->fs); | |
1139 | init_seg(&save->gs); | |
1140 | ||
1141 | save->cs.selector = 0xf000; | |
04b66839 | 1142 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1143 | /* Executable/Readable Code Segment */ |
1144 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1145 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1146 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1147 | |
1148 | save->gdtr.limit = 0xffff; | |
1149 | save->idtr.limit = 0xffff; | |
1150 | ||
1151 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1152 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1153 | ||
5690891b | 1154 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1155 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1156 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1157 | save->rip = 0x0000fff0; |
5fdbf976 | 1158 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1159 | |
e0231715 | 1160 | /* |
18fa000a | 1161 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1162 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1163 | */ |
79a8059d | 1164 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1165 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1166 | |
66aee91a | 1167 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1168 | /* rdx = ?? */ |
709ddebf JR |
1169 | |
1170 | if (npt_enabled) { | |
1171 | /* Setup VMCB for Nested Paging */ | |
1172 | control->nested_ctl = 1; | |
8a05a1b8 | 1173 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1174 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1175 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1176 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1177 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1178 | save->cr3 = 0; |
1179 | save->cr4 = 0; | |
1180 | } | |
f40f6a45 | 1181 | svm->asid_generation = 0; |
1371d904 | 1182 | |
e6aa9abd | 1183 | svm->nested.vmcb = 0; |
2af9194d JR |
1184 | svm->vcpu.arch.hflags = 0; |
1185 | ||
2a6b20b8 | 1186 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1187 | control->pause_filter_count = 3000; |
8a05a1b8 | 1188 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1189 | } |
1190 | ||
44a95dae SS |
1191 | if (avic) |
1192 | avic_init_vmcb(svm); | |
1193 | ||
8d28fec4 RJ |
1194 | mark_all_dirty(svm->vmcb); |
1195 | ||
2af9194d | 1196 | enable_gif(svm); |
44a95dae SS |
1197 | |
1198 | } | |
1199 | ||
1200 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index) | |
1201 | { | |
1202 | u64 *avic_physical_id_table; | |
1203 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
1204 | ||
1205 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1206 | return NULL; | |
1207 | ||
1208 | avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page); | |
1209 | ||
1210 | return &avic_physical_id_table[index]; | |
1211 | } | |
1212 | ||
1213 | /** | |
1214 | * Note: | |
1215 | * AVIC hardware walks the nested page table to check permissions, | |
1216 | * but does not use the SPA address specified in the leaf page | |
1217 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1218 | * field of the VMCB. Therefore, we set up the | |
1219 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1220 | */ | |
1221 | static int avic_init_access_page(struct kvm_vcpu *vcpu) | |
1222 | { | |
1223 | struct kvm *kvm = vcpu->kvm; | |
1224 | int ret; | |
1225 | ||
1226 | if (kvm->arch.apic_access_page_done) | |
1227 | return 0; | |
1228 | ||
1229 | ret = x86_set_memory_region(kvm, | |
1230 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1231 | APIC_DEFAULT_PHYS_BASE, | |
1232 | PAGE_SIZE); | |
1233 | if (ret) | |
1234 | return ret; | |
1235 | ||
1236 | kvm->arch.apic_access_page_done = true; | |
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1241 | { | |
1242 | int ret; | |
1243 | u64 *entry, new_entry; | |
1244 | int id = vcpu->vcpu_id; | |
1245 | struct vcpu_svm *svm = to_svm(vcpu); | |
1246 | ||
1247 | ret = avic_init_access_page(vcpu); | |
1248 | if (ret) | |
1249 | return ret; | |
1250 | ||
1251 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1252 | return -EINVAL; | |
1253 | ||
1254 | if (!svm->vcpu.arch.apic->regs) | |
1255 | return -EINVAL; | |
1256 | ||
1257 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); | |
1258 | ||
1259 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1260 | entry = avic_get_physical_id_entry(vcpu, id); | |
1261 | if (!entry) | |
1262 | return -EINVAL; | |
1263 | ||
1264 | new_entry = READ_ONCE(*entry); | |
1265 | new_entry = (page_to_phys(svm->avic_backing_page) & | |
1266 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1267 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; | |
1268 | WRITE_ONCE(*entry, new_entry); | |
1269 | ||
1270 | svm->avic_physical_id_cache = entry; | |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static void avic_vm_destroy(struct kvm *kvm) | |
1276 | { | |
1277 | struct kvm_arch *vm_data = &kvm->arch; | |
1278 | ||
1279 | if (vm_data->avic_logical_id_table_page) | |
1280 | __free_page(vm_data->avic_logical_id_table_page); | |
1281 | if (vm_data->avic_physical_id_table_page) | |
1282 | __free_page(vm_data->avic_physical_id_table_page); | |
1283 | } | |
1284 | ||
1285 | static int avic_vm_init(struct kvm *kvm) | |
1286 | { | |
1287 | int err = -ENOMEM; | |
1288 | struct kvm_arch *vm_data = &kvm->arch; | |
1289 | struct page *p_page; | |
1290 | struct page *l_page; | |
1291 | ||
1292 | if (!avic) | |
1293 | return 0; | |
1294 | ||
1295 | /* Allocating physical APIC ID table (4KB) */ | |
1296 | p_page = alloc_page(GFP_KERNEL); | |
1297 | if (!p_page) | |
1298 | goto free_avic; | |
1299 | ||
1300 | vm_data->avic_physical_id_table_page = p_page; | |
1301 | clear_page(page_address(p_page)); | |
1302 | ||
1303 | /* Allocating logical APIC ID table (4KB) */ | |
1304 | l_page = alloc_page(GFP_KERNEL); | |
1305 | if (!l_page) | |
1306 | goto free_avic; | |
1307 | ||
1308 | vm_data->avic_logical_id_table_page = l_page; | |
1309 | clear_page(page_address(l_page)); | |
1310 | ||
1311 | return 0; | |
1312 | ||
1313 | free_avic: | |
1314 | avic_vm_destroy(kvm); | |
1315 | return err; | |
6aa8b732 AK |
1316 | } |
1317 | ||
d28bc9dd | 1318 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
1319 | { |
1320 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1321 | u32 dummy; |
1322 | u32 eax = 1; | |
04d2cc77 | 1323 | |
d28bc9dd NA |
1324 | if (!init_event) { |
1325 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
1326 | MSR_IA32_APICBASE_ENABLE; | |
1327 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
1328 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
1329 | } | |
5690891b | 1330 | init_vmcb(svm); |
70433389 | 1331 | |
66f7b72e JS |
1332 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy); |
1333 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); | |
44a95dae SS |
1334 | |
1335 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
1336 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
1337 | } |
1338 | ||
fb3f0f51 | 1339 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1340 | { |
a2fa3e9f | 1341 | struct vcpu_svm *svm; |
6aa8b732 | 1342 | struct page *page; |
f65c229c | 1343 | struct page *msrpm_pages; |
b286d5d8 | 1344 | struct page *hsave_page; |
3d6368ef | 1345 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1346 | int err; |
6aa8b732 | 1347 | |
c16f862d | 1348 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1349 | if (!svm) { |
1350 | err = -ENOMEM; | |
1351 | goto out; | |
1352 | } | |
1353 | ||
1354 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1355 | if (err) | |
1356 | goto free_svm; | |
1357 | ||
b7af4043 | 1358 | err = -ENOMEM; |
6aa8b732 | 1359 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1360 | if (!page) |
fb3f0f51 | 1361 | goto uninit; |
6aa8b732 | 1362 | |
f65c229c JR |
1363 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1364 | if (!msrpm_pages) | |
b7af4043 | 1365 | goto free_page1; |
3d6368ef AG |
1366 | |
1367 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1368 | if (!nested_msrpm_pages) | |
b7af4043 | 1369 | goto free_page2; |
f65c229c | 1370 | |
b286d5d8 AG |
1371 | hsave_page = alloc_page(GFP_KERNEL); |
1372 | if (!hsave_page) | |
b7af4043 TY |
1373 | goto free_page3; |
1374 | ||
44a95dae SS |
1375 | if (avic) { |
1376 | err = avic_init_backing_page(&svm->vcpu); | |
1377 | if (err) | |
1378 | goto free_page4; | |
1379 | } | |
1380 | ||
e6aa9abd | 1381 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1382 | |
b7af4043 TY |
1383 | svm->msrpm = page_address(msrpm_pages); |
1384 | svm_vcpu_init_msrpm(svm->msrpm); | |
1385 | ||
e6aa9abd | 1386 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1387 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1388 | |
a2fa3e9f GH |
1389 | svm->vmcb = page_address(page); |
1390 | clear_page(svm->vmcb); | |
1391 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1392 | svm->asid_generation = 0; | |
5690891b | 1393 | init_vmcb(svm); |
6aa8b732 | 1394 | |
2b036c6b BO |
1395 | svm_init_osvw(&svm->vcpu); |
1396 | ||
fb3f0f51 | 1397 | return &svm->vcpu; |
36241b8c | 1398 | |
44a95dae SS |
1399 | free_page4: |
1400 | __free_page(hsave_page); | |
b7af4043 TY |
1401 | free_page3: |
1402 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1403 | free_page2: | |
1404 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1405 | free_page1: | |
1406 | __free_page(page); | |
fb3f0f51 RR |
1407 | uninit: |
1408 | kvm_vcpu_uninit(&svm->vcpu); | |
1409 | free_svm: | |
a4770347 | 1410 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1411 | out: |
1412 | return ERR_PTR(err); | |
6aa8b732 AK |
1413 | } |
1414 | ||
1415 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1416 | { | |
a2fa3e9f GH |
1417 | struct vcpu_svm *svm = to_svm(vcpu); |
1418 | ||
fb3f0f51 | 1419 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1420 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1421 | __free_page(virt_to_page(svm->nested.hsave)); |
1422 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1423 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1424 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1425 | } |
1426 | ||
15ad7146 | 1427 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1428 | { |
a2fa3e9f | 1429 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1430 | int i; |
0cc5064d | 1431 | |
0cc5064d | 1432 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1433 | svm->asid_generation = 0; |
8d28fec4 | 1434 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1435 | } |
94dfbdb3 | 1436 | |
82ca2d10 AK |
1437 | #ifdef CONFIG_X86_64 |
1438 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1439 | #endif | |
dacccfdd AK |
1440 | savesegment(fs, svm->host.fs); |
1441 | savesegment(gs, svm->host.gs); | |
1442 | svm->host.ldt = kvm_read_ldt(); | |
1443 | ||
94dfbdb3 | 1444 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1445 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 1446 | |
ad721883 HZ |
1447 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
1448 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
1449 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
1450 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
1451 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
1452 | } | |
fbc0db76 | 1453 | } |
46896c73 PB |
1454 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
1455 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
1456 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
6aa8b732 AK |
1457 | } |
1458 | ||
1459 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1460 | { | |
a2fa3e9f | 1461 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1462 | int i; |
1463 | ||
e1beb1d3 | 1464 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1465 | kvm_load_ldt(svm->host.ldt); |
1466 | #ifdef CONFIG_X86_64 | |
1467 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1468 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1469 | load_gs_index(svm->host.gs); |
dacccfdd | 1470 | #else |
831ca609 | 1471 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1472 | loadsegment(gs, svm->host.gs); |
831ca609 | 1473 | #endif |
dacccfdd | 1474 | #endif |
94dfbdb3 | 1475 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1476 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1477 | } |
1478 | ||
6aa8b732 AK |
1479 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1480 | { | |
a2fa3e9f | 1481 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1482 | } |
1483 | ||
1484 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1485 | { | |
ae9fedc7 PB |
1486 | /* |
1487 | * Any change of EFLAGS.VM is accompained by a reload of SS | |
1488 | * (caused by either a task switch or an inter-privilege IRET), | |
1489 | * so we do not need to update the CPL here. | |
1490 | */ | |
a2fa3e9f | 1491 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1492 | } |
1493 | ||
be94f6b7 HH |
1494 | static u32 svm_get_pkru(struct kvm_vcpu *vcpu) |
1495 | { | |
1496 | return 0; | |
1497 | } | |
1498 | ||
6de4f3ad AK |
1499 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1500 | { | |
1501 | switch (reg) { | |
1502 | case VCPU_EXREG_PDPTR: | |
1503 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1504 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1505 | break; |
1506 | default: | |
1507 | BUG(); | |
1508 | } | |
1509 | } | |
1510 | ||
f0b85051 AG |
1511 | static void svm_set_vintr(struct vcpu_svm *svm) |
1512 | { | |
8a05a1b8 | 1513 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1514 | } |
1515 | ||
1516 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1517 | { | |
8a05a1b8 | 1518 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1519 | } |
1520 | ||
6aa8b732 AK |
1521 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1522 | { | |
a2fa3e9f | 1523 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1524 | |
1525 | switch (seg) { | |
1526 | case VCPU_SREG_CS: return &save->cs; | |
1527 | case VCPU_SREG_DS: return &save->ds; | |
1528 | case VCPU_SREG_ES: return &save->es; | |
1529 | case VCPU_SREG_FS: return &save->fs; | |
1530 | case VCPU_SREG_GS: return &save->gs; | |
1531 | case VCPU_SREG_SS: return &save->ss; | |
1532 | case VCPU_SREG_TR: return &save->tr; | |
1533 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1534 | } | |
1535 | BUG(); | |
8b6d44c7 | 1536 | return NULL; |
6aa8b732 AK |
1537 | } |
1538 | ||
1539 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1540 | { | |
1541 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1542 | ||
1543 | return s->base; | |
1544 | } | |
1545 | ||
1546 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1547 | struct kvm_segment *var, int seg) | |
1548 | { | |
1549 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1550 | ||
1551 | var->base = s->base; | |
1552 | var->limit = s->limit; | |
1553 | var->selector = s->selector; | |
1554 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1555 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1556 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1557 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1558 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1559 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1560 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
1561 | |
1562 | /* | |
1563 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
1564 | * However, the SVM spec states that the G bit is not observed by the | |
1565 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
1566 | * So let's synthesize a legal G bit for all segments, this helps | |
1567 | * running KVM nested. It also helps cross-vendor migration, because | |
1568 | * Intel's vmentry has a check on the 'G' bit. | |
1569 | */ | |
1570 | var->g = s->limit > 0xfffff; | |
25022acc | 1571 | |
e0231715 JR |
1572 | /* |
1573 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1574 | * for cross vendor migration purposes by "not present" |
1575 | */ | |
1576 | var->unusable = !var->present || (var->type == 0); | |
1577 | ||
1fbdc7a5 | 1578 | switch (seg) { |
1fbdc7a5 AP |
1579 | case VCPU_SREG_TR: |
1580 | /* | |
1581 | * Work around a bug where the busy flag in the tr selector | |
1582 | * isn't exposed | |
1583 | */ | |
c0d09828 | 1584 | var->type |= 0x2; |
1fbdc7a5 AP |
1585 | break; |
1586 | case VCPU_SREG_DS: | |
1587 | case VCPU_SREG_ES: | |
1588 | case VCPU_SREG_FS: | |
1589 | case VCPU_SREG_GS: | |
1590 | /* | |
1591 | * The accessed bit must always be set in the segment | |
1592 | * descriptor cache, although it can be cleared in the | |
1593 | * descriptor, the cached bit always remains at 1. Since | |
1594 | * Intel has a check on this, set it here to support | |
1595 | * cross-vendor migration. | |
1596 | */ | |
1597 | if (!var->unusable) | |
1598 | var->type |= 0x1; | |
1599 | break; | |
b586eb02 | 1600 | case VCPU_SREG_SS: |
e0231715 JR |
1601 | /* |
1602 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1603 | * descriptor is left as 1, although the whole segment has |
1604 | * been made unusable. Clear it here to pass an Intel VMX | |
1605 | * entry check when cross vendor migrating. | |
1606 | */ | |
1607 | if (var->unusable) | |
1608 | var->db = 0; | |
33b458d2 | 1609 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 1610 | break; |
1fbdc7a5 | 1611 | } |
6aa8b732 AK |
1612 | } |
1613 | ||
2e4d2653 IE |
1614 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1615 | { | |
1616 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1617 | ||
1618 | return save->cpl; | |
1619 | } | |
1620 | ||
89a27f4d | 1621 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1622 | { |
a2fa3e9f GH |
1623 | struct vcpu_svm *svm = to_svm(vcpu); |
1624 | ||
89a27f4d GN |
1625 | dt->size = svm->vmcb->save.idtr.limit; |
1626 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1627 | } |
1628 | ||
89a27f4d | 1629 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1630 | { |
a2fa3e9f GH |
1631 | struct vcpu_svm *svm = to_svm(vcpu); |
1632 | ||
89a27f4d GN |
1633 | svm->vmcb->save.idtr.limit = dt->size; |
1634 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1635 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1636 | } |
1637 | ||
89a27f4d | 1638 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1639 | { |
a2fa3e9f GH |
1640 | struct vcpu_svm *svm = to_svm(vcpu); |
1641 | ||
89a27f4d GN |
1642 | dt->size = svm->vmcb->save.gdtr.limit; |
1643 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1644 | } |
1645 | ||
89a27f4d | 1646 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1647 | { |
a2fa3e9f GH |
1648 | struct vcpu_svm *svm = to_svm(vcpu); |
1649 | ||
89a27f4d GN |
1650 | svm->vmcb->save.gdtr.limit = dt->size; |
1651 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1652 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1653 | } |
1654 | ||
e8467fda AK |
1655 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1656 | { | |
1657 | } | |
1658 | ||
aff48baa AK |
1659 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1660 | { | |
1661 | } | |
1662 | ||
25c4c276 | 1663 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1664 | { |
1665 | } | |
1666 | ||
d225157b AK |
1667 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1668 | { | |
1669 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1670 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1671 | ||
1672 | if (!svm->vcpu.fpu_active) | |
1673 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1674 | else | |
1675 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1676 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1677 | ||
dcca1a65 | 1678 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1679 | |
1680 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1681 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1682 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1683 | } else { |
4ee546b4 RJ |
1684 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1685 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1686 | } |
1687 | } | |
1688 | ||
6aa8b732 AK |
1689 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1690 | { | |
a2fa3e9f GH |
1691 | struct vcpu_svm *svm = to_svm(vcpu); |
1692 | ||
05b3e0c2 | 1693 | #ifdef CONFIG_X86_64 |
f6801dff | 1694 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1695 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1696 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1697 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1698 | } |
1699 | ||
d77c26fc | 1700 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1701 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1702 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1703 | } |
1704 | } | |
1705 | #endif | |
ad312c7c | 1706 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1707 | |
1708 | if (!npt_enabled) | |
1709 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1710 | |
1711 | if (!vcpu->fpu_active) | |
334df50a | 1712 | cr0 |= X86_CR0_TS; |
bcf166a9 PB |
1713 | /* |
1714 | * re-enable caching here because the QEMU bios | |
1715 | * does not do it - this results in some delay at | |
1716 | * reboot | |
1717 | */ | |
1718 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
1719 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1720 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1721 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1722 | update_cr0_intercept(svm); |
6aa8b732 AK |
1723 | } |
1724 | ||
5e1746d6 | 1725 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1726 | { |
1e02ce4c | 1727 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
1728 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1729 | ||
5e1746d6 NHE |
1730 | if (cr4 & X86_CR4_VMXE) |
1731 | return 1; | |
1732 | ||
e5eab0ce | 1733 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1734 | svm_flush_tlb(vcpu); |
6394b649 | 1735 | |
ec077263 JR |
1736 | vcpu->arch.cr4 = cr4; |
1737 | if (!npt_enabled) | |
1738 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1739 | cr4 |= host_cr4_mce; |
ec077263 | 1740 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1741 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1742 | return 0; |
6aa8b732 AK |
1743 | } |
1744 | ||
1745 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1746 | struct kvm_segment *var, int seg) | |
1747 | { | |
a2fa3e9f | 1748 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1749 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1750 | ||
1751 | s->base = var->base; | |
1752 | s->limit = var->limit; | |
1753 | s->selector = var->selector; | |
1754 | if (var->unusable) | |
1755 | s->attrib = 0; | |
1756 | else { | |
1757 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1758 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1759 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1760 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1761 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1762 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1763 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1764 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1765 | } | |
ae9fedc7 PB |
1766 | |
1767 | /* | |
1768 | * This is always accurate, except if SYSRET returned to a segment | |
1769 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
1770 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
1771 | * would entail passing the CPL to userspace and back. | |
1772 | */ | |
1773 | if (seg == VCPU_SREG_SS) | |
1774 | svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
6aa8b732 | 1775 | |
060d0c9a | 1776 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1777 | } |
1778 | ||
cbdb967a | 1779 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1780 | { |
d0bfb940 JK |
1781 | struct vcpu_svm *svm = to_svm(vcpu); |
1782 | ||
18c918c5 | 1783 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 1784 | |
d0bfb940 | 1785 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 1786 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1787 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1788 | } else |
1789 | vcpu->guest_debug = 0; | |
44c11430 GN |
1790 | } |
1791 | ||
0fe1e009 | 1792 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1793 | { |
0fe1e009 TH |
1794 | if (sd->next_asid > sd->max_asid) { |
1795 | ++sd->asid_generation; | |
1796 | sd->next_asid = 1; | |
a2fa3e9f | 1797 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1798 | } |
1799 | ||
0fe1e009 TH |
1800 | svm->asid_generation = sd->asid_generation; |
1801 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1802 | |
1803 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1804 | } |
1805 | ||
73aaf249 JK |
1806 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
1807 | { | |
1808 | return to_svm(vcpu)->vmcb->save.dr6; | |
1809 | } | |
1810 | ||
1811 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
1812 | { | |
1813 | struct vcpu_svm *svm = to_svm(vcpu); | |
1814 | ||
1815 | svm->vmcb->save.dr6 = value; | |
1816 | mark_dirty(svm->vmcb, VMCB_DR); | |
1817 | } | |
1818 | ||
facb0139 PB |
1819 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
1820 | { | |
1821 | struct vcpu_svm *svm = to_svm(vcpu); | |
1822 | ||
1823 | get_debugreg(vcpu->arch.db[0], 0); | |
1824 | get_debugreg(vcpu->arch.db[1], 1); | |
1825 | get_debugreg(vcpu->arch.db[2], 2); | |
1826 | get_debugreg(vcpu->arch.db[3], 3); | |
1827 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
1828 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
1829 | ||
1830 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
1831 | set_dr_intercepts(svm); | |
1832 | } | |
1833 | ||
020df079 | 1834 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1835 | { |
42dbaa5a | 1836 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1837 | |
020df079 | 1838 | svm->vmcb->save.dr7 = value; |
72214b96 | 1839 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1840 | } |
1841 | ||
851ba692 | 1842 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1843 | { |
631bc487 | 1844 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1845 | u32 error_code; |
631bc487 | 1846 | int r = 1; |
6aa8b732 | 1847 | |
631bc487 GN |
1848 | switch (svm->apf_reason) { |
1849 | default: | |
1850 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1851 | |
631bc487 GN |
1852 | trace_kvm_page_fault(fault_address, error_code); |
1853 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1854 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1855 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1856 | svm->vmcb->control.insn_bytes, | |
1857 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1858 | break; |
1859 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1860 | svm->apf_reason = 0; | |
1861 | local_irq_disable(); | |
1862 | kvm_async_pf_task_wait(fault_address); | |
1863 | local_irq_enable(); | |
1864 | break; | |
1865 | case KVM_PV_REASON_PAGE_READY: | |
1866 | svm->apf_reason = 0; | |
1867 | local_irq_disable(); | |
1868 | kvm_async_pf_task_wake(fault_address); | |
1869 | local_irq_enable(); | |
1870 | break; | |
1871 | } | |
1872 | return r; | |
6aa8b732 AK |
1873 | } |
1874 | ||
851ba692 | 1875 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1876 | { |
851ba692 AK |
1877 | struct kvm_run *kvm_run = svm->vcpu.run; |
1878 | ||
d0bfb940 | 1879 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1880 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1881 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1882 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1883 | return 1; | |
1884 | } | |
44c11430 | 1885 | |
6be7d306 JK |
1886 | if (svm->nmi_singlestep) { |
1887 | svm->nmi_singlestep = false; | |
44c11430 GN |
1888 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1889 | svm->vmcb->save.rflags &= | |
1890 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
44c11430 GN |
1891 | } |
1892 | ||
1893 | if (svm->vcpu.guest_debug & | |
e0231715 | 1894 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1895 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1896 | kvm_run->debug.arch.pc = | |
1897 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1898 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1899 | return 0; | |
1900 | } | |
1901 | ||
1902 | return 1; | |
d0bfb940 JK |
1903 | } |
1904 | ||
851ba692 | 1905 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1906 | { |
851ba692 AK |
1907 | struct kvm_run *kvm_run = svm->vcpu.run; |
1908 | ||
d0bfb940 JK |
1909 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1910 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1911 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1912 | return 0; | |
1913 | } | |
1914 | ||
851ba692 | 1915 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1916 | { |
1917 | int er; | |
1918 | ||
51d8b661 | 1919 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1920 | if (er != EMULATE_DONE) |
7ee5d940 | 1921 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1922 | return 1; |
1923 | } | |
1924 | ||
54a20552 EN |
1925 | static int ac_interception(struct vcpu_svm *svm) |
1926 | { | |
1927 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
1928 | return 1; | |
1929 | } | |
1930 | ||
6b52d186 | 1931 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1932 | { |
6b52d186 | 1933 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1934 | |
18c918c5 | 1935 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1936 | |
e756fc62 | 1937 | svm->vcpu.fpu_active = 1; |
d225157b | 1938 | update_cr0_intercept(svm); |
6b52d186 | 1939 | } |
a2fa3e9f | 1940 | |
6b52d186 AK |
1941 | static int nm_interception(struct vcpu_svm *svm) |
1942 | { | |
1943 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1944 | return 1; |
7807fa6c AL |
1945 | } |
1946 | ||
67ec6607 JR |
1947 | static bool is_erratum_383(void) |
1948 | { | |
1949 | int err, i; | |
1950 | u64 value; | |
1951 | ||
1952 | if (!erratum_383_found) | |
1953 | return false; | |
1954 | ||
1955 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1956 | if (err) | |
1957 | return false; | |
1958 | ||
1959 | /* Bit 62 may or may not be set for this mce */ | |
1960 | value &= ~(1ULL << 62); | |
1961 | ||
1962 | if (value != 0xb600000000010015ULL) | |
1963 | return false; | |
1964 | ||
1965 | /* Clear MCi_STATUS registers */ | |
1966 | for (i = 0; i < 6; ++i) | |
1967 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1968 | ||
1969 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1970 | if (!err) { | |
1971 | u32 low, high; | |
1972 | ||
1973 | value &= ~(1ULL << 2); | |
1974 | low = lower_32_bits(value); | |
1975 | high = upper_32_bits(value); | |
1976 | ||
1977 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1978 | } | |
1979 | ||
1980 | /* Flush tlb to evict multi-match entries */ | |
1981 | __flush_tlb_all(); | |
1982 | ||
1983 | return true; | |
1984 | } | |
1985 | ||
fe5913e4 | 1986 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1987 | { |
67ec6607 JR |
1988 | if (is_erratum_383()) { |
1989 | /* | |
1990 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1991 | * guest. | |
1992 | */ | |
1993 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1994 | ||
a8eeb04a | 1995 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1996 | |
1997 | return; | |
1998 | } | |
1999 | ||
53371b50 JR |
2000 | /* |
2001 | * On an #MC intercept the MCE handler is not called automatically in | |
2002 | * the host. So do it by hand here. | |
2003 | */ | |
2004 | asm volatile ( | |
2005 | "int $0x12\n"); | |
2006 | /* not sure if we ever come back to this point */ | |
2007 | ||
fe5913e4 JR |
2008 | return; |
2009 | } | |
2010 | ||
2011 | static int mc_interception(struct vcpu_svm *svm) | |
2012 | { | |
53371b50 JR |
2013 | return 1; |
2014 | } | |
2015 | ||
851ba692 | 2016 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2017 | { |
851ba692 AK |
2018 | struct kvm_run *kvm_run = svm->vcpu.run; |
2019 | ||
46fe4ddd JR |
2020 | /* |
2021 | * VMCB is undefined after a SHUTDOWN intercept | |
2022 | * so reinitialize it. | |
2023 | */ | |
a2fa3e9f | 2024 | clear_page(svm->vmcb); |
5690891b | 2025 | init_vmcb(svm); |
46fe4ddd JR |
2026 | |
2027 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2028 | return 0; | |
2029 | } | |
2030 | ||
851ba692 | 2031 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2032 | { |
cf8f70bf | 2033 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2034 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 2035 | int size, in, string; |
039576c0 | 2036 | unsigned port; |
6aa8b732 | 2037 | |
e756fc62 | 2038 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2039 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2040 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 2041 | if (string || in) |
51d8b661 | 2042 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 2043 | |
039576c0 AK |
2044 | port = io_info >> 16; |
2045 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2046 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 2047 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
2048 | |
2049 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
2050 | } |
2051 | ||
851ba692 | 2052 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2053 | { |
2054 | return 1; | |
2055 | } | |
2056 | ||
851ba692 | 2057 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2058 | { |
2059 | ++svm->vcpu.stat.irq_exits; | |
2060 | return 1; | |
2061 | } | |
2062 | ||
851ba692 | 2063 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2064 | { |
2065 | return 1; | |
2066 | } | |
2067 | ||
851ba692 | 2068 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2069 | { |
5fdbf976 | 2070 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 | 2071 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2072 | } |
2073 | ||
851ba692 | 2074 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2075 | { |
5fdbf976 | 2076 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
0d9c055e | 2077 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2078 | } |
2079 | ||
5bd2edc3 JR |
2080 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2081 | { | |
2082 | struct vcpu_svm *svm = to_svm(vcpu); | |
2083 | ||
2084 | return svm->nested.nested_cr3; | |
2085 | } | |
2086 | ||
e4e517b4 AK |
2087 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2088 | { | |
2089 | struct vcpu_svm *svm = to_svm(vcpu); | |
2090 | u64 cr3 = svm->nested.nested_cr3; | |
2091 | u64 pdpte; | |
2092 | int ret; | |
2093 | ||
54bf36aa PB |
2094 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte, |
2095 | offset_in_page(cr3) + index * 8, 8); | |
e4e517b4 AK |
2096 | if (ret) |
2097 | return 0; | |
2098 | return pdpte; | |
2099 | } | |
2100 | ||
5bd2edc3 JR |
2101 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2102 | unsigned long root) | |
2103 | { | |
2104 | struct vcpu_svm *svm = to_svm(vcpu); | |
2105 | ||
2106 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 2107 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 2108 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
2109 | } |
2110 | ||
6389ee94 AK |
2111 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2112 | struct x86_exception *fault) | |
5bd2edc3 JR |
2113 | { |
2114 | struct vcpu_svm *svm = to_svm(vcpu); | |
2115 | ||
5e352519 PB |
2116 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2117 | /* | |
2118 | * TODO: track the cause of the nested page fault, and | |
2119 | * correctly fill in the high bits of exit_info_1. | |
2120 | */ | |
2121 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2122 | svm->vmcb->control.exit_code_hi = 0; | |
2123 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
2124 | svm->vmcb->control.exit_info_2 = fault->address; | |
2125 | } | |
2126 | ||
2127 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
2128 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
2129 | ||
2130 | /* | |
2131 | * The present bit is always zero for page structure faults on real | |
2132 | * hardware. | |
2133 | */ | |
2134 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
2135 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
2136 | |
2137 | nested_svm_vmexit(svm); | |
2138 | } | |
2139 | ||
8a3c1a33 | 2140 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 2141 | { |
ad896af0 PB |
2142 | WARN_ON(mmu_is_nested(vcpu)); |
2143 | kvm_init_shadow_mmu(vcpu); | |
4b16184c JR |
2144 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; |
2145 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 2146 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
2147 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
2148 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
c258b62b | 2149 | reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu); |
4b16184c | 2150 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
2151 | } |
2152 | ||
2153 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
2154 | { | |
2155 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
2156 | } | |
2157 | ||
c0725420 AG |
2158 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
2159 | { | |
f6801dff | 2160 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
2161 | || !is_paging(&svm->vcpu)) { |
2162 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2163 | return 1; | |
2164 | } | |
2165 | ||
2166 | if (svm->vmcb->save.cpl) { | |
2167 | kvm_inject_gp(&svm->vcpu, 0); | |
2168 | return 1; | |
2169 | } | |
2170 | ||
2171 | return 0; | |
2172 | } | |
2173 | ||
cf74a78b AG |
2174 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2175 | bool has_error_code, u32 error_code) | |
2176 | { | |
b8e88bc8 JR |
2177 | int vmexit; |
2178 | ||
2030753d | 2179 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2180 | return 0; |
cf74a78b | 2181 | |
0295ad7d JR |
2182 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2183 | svm->vmcb->control.exit_code_hi = 0; | |
2184 | svm->vmcb->control.exit_info_1 = error_code; | |
2185 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
2186 | ||
b8e88bc8 JR |
2187 | vmexit = nested_svm_intercept(svm); |
2188 | if (vmexit == NESTED_EXIT_DONE) | |
2189 | svm->nested.exit_required = true; | |
2190 | ||
2191 | return vmexit; | |
cf74a78b AG |
2192 | } |
2193 | ||
8fe54654 JR |
2194 | /* This function returns true if it is save to enable the irq window */ |
2195 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2196 | { |
2030753d | 2197 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2198 | return true; |
cf74a78b | 2199 | |
26666957 | 2200 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2201 | return true; |
cf74a78b | 2202 | |
26666957 | 2203 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2204 | return false; |
cf74a78b | 2205 | |
a0a07cd2 GN |
2206 | /* |
2207 | * if vmexit was already requested (by intercepted exception | |
2208 | * for instance) do not overwrite it with "external interrupt" | |
2209 | * vmexit. | |
2210 | */ | |
2211 | if (svm->nested.exit_required) | |
2212 | return false; | |
2213 | ||
197717d5 JR |
2214 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2215 | svm->vmcb->control.exit_info_1 = 0; | |
2216 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2217 | |
cd3ff653 JR |
2218 | if (svm->nested.intercept & 1ULL) { |
2219 | /* | |
2220 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2221 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2222 | * #vmexit emulation might sleep. Only signal request for |
2223 | * the #vmexit here. | |
2224 | */ | |
2225 | svm->nested.exit_required = true; | |
236649de | 2226 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2227 | return false; |
cf74a78b AG |
2228 | } |
2229 | ||
8fe54654 | 2230 | return true; |
cf74a78b AG |
2231 | } |
2232 | ||
887f500c JR |
2233 | /* This function returns true if it is save to enable the nmi window */ |
2234 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2235 | { | |
2030753d | 2236 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2237 | return true; |
2238 | ||
2239 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2240 | return true; | |
2241 | ||
2242 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2243 | svm->nested.exit_required = true; | |
2244 | ||
2245 | return false; | |
cf74a78b AG |
2246 | } |
2247 | ||
7597f129 | 2248 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2249 | { |
2250 | struct page *page; | |
2251 | ||
6c3bd3d7 JR |
2252 | might_sleep(); |
2253 | ||
54bf36aa | 2254 | page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2255 | if (is_error_page(page)) |
2256 | goto error; | |
2257 | ||
7597f129 JR |
2258 | *_page = page; |
2259 | ||
2260 | return kmap(page); | |
34f80cfa JR |
2261 | |
2262 | error: | |
34f80cfa JR |
2263 | kvm_inject_gp(&svm->vcpu, 0); |
2264 | ||
2265 | return NULL; | |
2266 | } | |
2267 | ||
7597f129 | 2268 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2269 | { |
7597f129 | 2270 | kunmap(page); |
34f80cfa JR |
2271 | kvm_release_page_dirty(page); |
2272 | } | |
34f80cfa | 2273 | |
ce2ac085 JR |
2274 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2275 | { | |
9bf41833 JK |
2276 | unsigned port, size, iopm_len; |
2277 | u16 val, mask; | |
2278 | u8 start_bit; | |
ce2ac085 | 2279 | u64 gpa; |
34f80cfa | 2280 | |
ce2ac085 JR |
2281 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2282 | return NESTED_EXIT_HOST; | |
34f80cfa | 2283 | |
ce2ac085 | 2284 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
2285 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
2286 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 2287 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
2288 | start_bit = port % 8; |
2289 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
2290 | mask = (0xf >> (4 - size)) << start_bit; | |
2291 | val = 0; | |
ce2ac085 | 2292 | |
54bf36aa | 2293 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 2294 | return NESTED_EXIT_DONE; |
ce2ac085 | 2295 | |
9bf41833 | 2296 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
2297 | } |
2298 | ||
d2477826 | 2299 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2300 | { |
0d6b3537 JR |
2301 | u32 offset, msr, value; |
2302 | int write, mask; | |
4c2161ae | 2303 | |
3d62d9aa | 2304 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2305 | return NESTED_EXIT_HOST; |
3d62d9aa | 2306 | |
0d6b3537 JR |
2307 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2308 | offset = svm_msrpm_offset(msr); | |
2309 | write = svm->vmcb->control.exit_info_1 & 1; | |
2310 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2311 | |
0d6b3537 JR |
2312 | if (offset == MSR_INVALID) |
2313 | return NESTED_EXIT_DONE; | |
4c2161ae | 2314 | |
0d6b3537 JR |
2315 | /* Offset is in 32 bit units but need in 8 bit units */ |
2316 | offset *= 4; | |
4c2161ae | 2317 | |
54bf36aa | 2318 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 2319 | return NESTED_EXIT_DONE; |
3d62d9aa | 2320 | |
0d6b3537 | 2321 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2322 | } |
2323 | ||
410e4d57 | 2324 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2325 | { |
cf74a78b | 2326 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2327 | |
410e4d57 JR |
2328 | switch (exit_code) { |
2329 | case SVM_EXIT_INTR: | |
2330 | case SVM_EXIT_NMI: | |
ff47a49b | 2331 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2332 | return NESTED_EXIT_HOST; |
410e4d57 | 2333 | case SVM_EXIT_NPF: |
e0231715 | 2334 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2335 | if (npt_enabled) |
2336 | return NESTED_EXIT_HOST; | |
2337 | break; | |
410e4d57 | 2338 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2339 | /* When we're shadowing, trap PFs, but not async PF */ |
2340 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2341 | return NESTED_EXIT_HOST; |
2342 | break; | |
66a562f7 JR |
2343 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2344 | nm_interception(svm); | |
2345 | break; | |
410e4d57 JR |
2346 | default: |
2347 | break; | |
cf74a78b AG |
2348 | } |
2349 | ||
410e4d57 JR |
2350 | return NESTED_EXIT_CONTINUE; |
2351 | } | |
2352 | ||
2353 | /* | |
2354 | * If this function returns true, this #vmexit was already handled | |
2355 | */ | |
b8e88bc8 | 2356 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2357 | { |
2358 | u32 exit_code = svm->vmcb->control.exit_code; | |
2359 | int vmexit = NESTED_EXIT_HOST; | |
2360 | ||
cf74a78b | 2361 | switch (exit_code) { |
9c4e40b9 | 2362 | case SVM_EXIT_MSR: |
3d62d9aa | 2363 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2364 | break; |
ce2ac085 JR |
2365 | case SVM_EXIT_IOIO: |
2366 | vmexit = nested_svm_intercept_ioio(svm); | |
2367 | break; | |
4ee546b4 RJ |
2368 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2369 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2370 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2371 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2372 | break; |
2373 | } | |
3aed041a JR |
2374 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2375 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2376 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2377 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2378 | break; |
2379 | } | |
2380 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2381 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2382 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2383 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2384 | /* async page fault always cause vmexit */ |
2385 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2386 | svm->apf_reason != 0) | |
2387 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2388 | break; |
2389 | } | |
228070b1 JR |
2390 | case SVM_EXIT_ERR: { |
2391 | vmexit = NESTED_EXIT_DONE; | |
2392 | break; | |
2393 | } | |
cf74a78b AG |
2394 | default: { |
2395 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2396 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2397 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2398 | } |
2399 | } | |
2400 | ||
b8e88bc8 JR |
2401 | return vmexit; |
2402 | } | |
2403 | ||
2404 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2405 | { | |
2406 | int vmexit; | |
2407 | ||
2408 | vmexit = nested_svm_intercept(svm); | |
2409 | ||
2410 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2411 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2412 | |
2413 | return vmexit; | |
cf74a78b AG |
2414 | } |
2415 | ||
0460a979 JR |
2416 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2417 | { | |
2418 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2419 | struct vmcb_control_area *from = &from_vmcb->control; | |
2420 | ||
4ee546b4 | 2421 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2422 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2423 | dst->intercept_exceptions = from->intercept_exceptions; |
2424 | dst->intercept = from->intercept; | |
2425 | dst->iopm_base_pa = from->iopm_base_pa; | |
2426 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2427 | dst->tsc_offset = from->tsc_offset; | |
2428 | dst->asid = from->asid; | |
2429 | dst->tlb_ctl = from->tlb_ctl; | |
2430 | dst->int_ctl = from->int_ctl; | |
2431 | dst->int_vector = from->int_vector; | |
2432 | dst->int_state = from->int_state; | |
2433 | dst->exit_code = from->exit_code; | |
2434 | dst->exit_code_hi = from->exit_code_hi; | |
2435 | dst->exit_info_1 = from->exit_info_1; | |
2436 | dst->exit_info_2 = from->exit_info_2; | |
2437 | dst->exit_int_info = from->exit_int_info; | |
2438 | dst->exit_int_info_err = from->exit_int_info_err; | |
2439 | dst->nested_ctl = from->nested_ctl; | |
2440 | dst->event_inj = from->event_inj; | |
2441 | dst->event_inj_err = from->event_inj_err; | |
2442 | dst->nested_cr3 = from->nested_cr3; | |
2443 | dst->lbr_ctl = from->lbr_ctl; | |
2444 | } | |
2445 | ||
34f80cfa | 2446 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2447 | { |
34f80cfa | 2448 | struct vmcb *nested_vmcb; |
e6aa9abd | 2449 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2450 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2451 | struct page *page; |
cf74a78b | 2452 | |
17897f36 JR |
2453 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2454 | vmcb->control.exit_info_1, | |
2455 | vmcb->control.exit_info_2, | |
2456 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2457 | vmcb->control.exit_int_info_err, |
2458 | KVM_ISA_SVM); | |
17897f36 | 2459 | |
7597f129 | 2460 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2461 | if (!nested_vmcb) |
2462 | return 1; | |
2463 | ||
2030753d JR |
2464 | /* Exit Guest-Mode */ |
2465 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2466 | svm->nested.vmcb = 0; |
2467 | ||
cf74a78b | 2468 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2469 | disable_gif(svm); |
2470 | ||
2471 | nested_vmcb->save.es = vmcb->save.es; | |
2472 | nested_vmcb->save.cs = vmcb->save.cs; | |
2473 | nested_vmcb->save.ss = vmcb->save.ss; | |
2474 | nested_vmcb->save.ds = vmcb->save.ds; | |
2475 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2476 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2477 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2478 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2479 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2480 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2481 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2482 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2483 | nested_vmcb->save.rip = vmcb->save.rip; |
2484 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2485 | nested_vmcb->save.rax = vmcb->save.rax; | |
2486 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2487 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2488 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2489 | ||
2490 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2491 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2492 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2493 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2494 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2495 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2496 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2497 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2498 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
2499 | |
2500 | if (svm->nrips_enabled) | |
2501 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
2502 | |
2503 | /* | |
2504 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2505 | * to make sure that we do not lose injected events. So check event_inj | |
2506 | * here and copy it to exit_int_info if it is valid. | |
2507 | * Exit_int_info and event_inj can't be both valid because the case | |
2508 | * below only happens on a VMRUN instruction intercept which has | |
2509 | * no valid exit_int_info set. | |
2510 | */ | |
2511 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2512 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2513 | ||
2514 | nc->exit_int_info = vmcb->control.event_inj; | |
2515 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2516 | } | |
2517 | ||
33740e40 JR |
2518 | nested_vmcb->control.tlb_ctl = 0; |
2519 | nested_vmcb->control.event_inj = 0; | |
2520 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2521 | |
2522 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2523 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2524 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2525 | ||
cf74a78b | 2526 | /* Restore the original control entries */ |
0460a979 | 2527 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2528 | |
219b65dc AG |
2529 | kvm_clear_exception_queue(&svm->vcpu); |
2530 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2531 | |
4b16184c JR |
2532 | svm->nested.nested_cr3 = 0; |
2533 | ||
cf74a78b AG |
2534 | /* Restore selected save entries */ |
2535 | svm->vmcb->save.es = hsave->save.es; | |
2536 | svm->vmcb->save.cs = hsave->save.cs; | |
2537 | svm->vmcb->save.ss = hsave->save.ss; | |
2538 | svm->vmcb->save.ds = hsave->save.ds; | |
2539 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2540 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2541 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2542 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2543 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2544 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2545 | if (npt_enabled) { | |
2546 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2547 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2548 | } else { | |
2390218b | 2549 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2550 | } |
2551 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2552 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2553 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2554 | svm->vmcb->save.dr7 = 0; | |
2555 | svm->vmcb->save.cpl = 0; | |
2556 | svm->vmcb->control.exit_int_info = 0; | |
2557 | ||
8d28fec4 RJ |
2558 | mark_all_dirty(svm->vmcb); |
2559 | ||
7597f129 | 2560 | nested_svm_unmap(page); |
cf74a78b | 2561 | |
4b16184c | 2562 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2563 | kvm_mmu_reset_context(&svm->vcpu); |
2564 | kvm_mmu_load(&svm->vcpu); | |
2565 | ||
2566 | return 0; | |
2567 | } | |
3d6368ef | 2568 | |
9738b2c9 | 2569 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2570 | { |
323c3d80 JR |
2571 | /* |
2572 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2573 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2574 | * the kvm msr permission bitmap may contain zero bits |
2575 | */ | |
3d6368ef | 2576 | int i; |
9738b2c9 | 2577 | |
323c3d80 JR |
2578 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2579 | return true; | |
9738b2c9 | 2580 | |
323c3d80 JR |
2581 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2582 | u32 value, p; | |
2583 | u64 offset; | |
9738b2c9 | 2584 | |
323c3d80 JR |
2585 | if (msrpm_offsets[i] == 0xffffffff) |
2586 | break; | |
3d6368ef | 2587 | |
0d6b3537 JR |
2588 | p = msrpm_offsets[i]; |
2589 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 2590 | |
54bf36aa | 2591 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
2592 | return false; |
2593 | ||
2594 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2595 | } | |
3d6368ef | 2596 | |
323c3d80 | 2597 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2598 | |
2599 | return true; | |
3d6368ef AG |
2600 | } |
2601 | ||
52c65a30 JR |
2602 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2603 | { | |
2604 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2605 | return false; | |
2606 | ||
dbe77584 JR |
2607 | if (vmcb->control.asid == 0) |
2608 | return false; | |
2609 | ||
4b16184c JR |
2610 | if (vmcb->control.nested_ctl && !npt_enabled) |
2611 | return false; | |
2612 | ||
52c65a30 JR |
2613 | return true; |
2614 | } | |
2615 | ||
9738b2c9 | 2616 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2617 | { |
9738b2c9 | 2618 | struct vmcb *nested_vmcb; |
e6aa9abd | 2619 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2620 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2621 | struct page *page; |
06fc7772 | 2622 | u64 vmcb_gpa; |
3d6368ef | 2623 | |
06fc7772 | 2624 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2625 | |
7597f129 | 2626 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2627 | if (!nested_vmcb) |
2628 | return false; | |
2629 | ||
52c65a30 JR |
2630 | if (!nested_vmcb_checks(nested_vmcb)) { |
2631 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2632 | nested_vmcb->control.exit_code_hi = 0; | |
2633 | nested_vmcb->control.exit_info_1 = 0; | |
2634 | nested_vmcb->control.exit_info_2 = 0; | |
2635 | ||
2636 | nested_svm_unmap(page); | |
2637 | ||
2638 | return false; | |
2639 | } | |
2640 | ||
b75f4eb3 | 2641 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2642 | nested_vmcb->save.rip, |
2643 | nested_vmcb->control.int_ctl, | |
2644 | nested_vmcb->control.event_inj, | |
2645 | nested_vmcb->control.nested_ctl); | |
2646 | ||
4ee546b4 RJ |
2647 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2648 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2649 | nested_vmcb->control.intercept_exceptions, |
2650 | nested_vmcb->control.intercept); | |
2651 | ||
3d6368ef | 2652 | /* Clear internal status */ |
219b65dc AG |
2653 | kvm_clear_exception_queue(&svm->vcpu); |
2654 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2655 | |
e0231715 JR |
2656 | /* |
2657 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2658 | * restore everything when a VMEXIT occurs | |
2659 | */ | |
defbba56 JR |
2660 | hsave->save.es = vmcb->save.es; |
2661 | hsave->save.cs = vmcb->save.cs; | |
2662 | hsave->save.ss = vmcb->save.ss; | |
2663 | hsave->save.ds = vmcb->save.ds; | |
2664 | hsave->save.gdtr = vmcb->save.gdtr; | |
2665 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2666 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2667 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2668 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2669 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2670 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2671 | hsave->save.rsp = vmcb->save.rsp; |
2672 | hsave->save.rax = vmcb->save.rax; | |
2673 | if (npt_enabled) | |
2674 | hsave->save.cr3 = vmcb->save.cr3; | |
2675 | else | |
9f8fe504 | 2676 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2677 | |
0460a979 | 2678 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2679 | |
f6e78475 | 2680 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2681 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2682 | else | |
2683 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2684 | ||
4b16184c JR |
2685 | if (nested_vmcb->control.nested_ctl) { |
2686 | kvm_mmu_unload(&svm->vcpu); | |
2687 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2688 | nested_svm_init_mmu_context(&svm->vcpu); | |
2689 | } | |
2690 | ||
3d6368ef AG |
2691 | /* Load the nested guest state */ |
2692 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2693 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2694 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2695 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2696 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2697 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2698 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2699 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2700 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2701 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2702 | if (npt_enabled) { | |
2703 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2704 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2705 | } else |
2390218b | 2706 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2707 | |
2708 | /* Guest paging mode is active - reset mmu */ | |
2709 | kvm_mmu_reset_context(&svm->vcpu); | |
2710 | ||
defbba56 | 2711 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2712 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2713 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2714 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2715 | |
3d6368ef AG |
2716 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2717 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2718 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2719 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2720 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2721 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2722 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2723 | ||
f7138538 | 2724 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2725 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2726 | |
aad42c64 | 2727 | /* cache intercepts */ |
4ee546b4 | 2728 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2729 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2730 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2731 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2732 | ||
f40f6a45 | 2733 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2734 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2735 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2736 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2737 | else | |
2738 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2739 | ||
88ab24ad JR |
2740 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2741 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2742 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2743 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2744 | } |
2745 | ||
0d945bd9 | 2746 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2747 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2748 | |
88ab24ad | 2749 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2750 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2751 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2752 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2753 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2754 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2755 | ||
7597f129 | 2756 | nested_svm_unmap(page); |
9738b2c9 | 2757 | |
2030753d JR |
2758 | /* Enter Guest-Mode */ |
2759 | enter_guest_mode(&svm->vcpu); | |
2760 | ||
384c6368 JR |
2761 | /* |
2762 | * Merge guest and host intercepts - must be called with vcpu in | |
2763 | * guest-mode to take affect here | |
2764 | */ | |
2765 | recalc_intercepts(svm); | |
2766 | ||
06fc7772 | 2767 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2768 | |
2af9194d | 2769 | enable_gif(svm); |
3d6368ef | 2770 | |
8d28fec4 RJ |
2771 | mark_all_dirty(svm->vmcb); |
2772 | ||
9738b2c9 | 2773 | return true; |
3d6368ef AG |
2774 | } |
2775 | ||
9966bf68 | 2776 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2777 | { |
2778 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2779 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2780 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2781 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2782 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2783 | to_vmcb->save.star = from_vmcb->save.star; | |
2784 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2785 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2786 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2787 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2788 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2789 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2790 | } |
2791 | ||
851ba692 | 2792 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2793 | { |
9966bf68 | 2794 | struct vmcb *nested_vmcb; |
7597f129 | 2795 | struct page *page; |
9966bf68 | 2796 | |
5542675b AG |
2797 | if (nested_svm_check_permissions(svm)) |
2798 | return 1; | |
2799 | ||
7597f129 | 2800 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2801 | if (!nested_vmcb) |
2802 | return 1; | |
2803 | ||
e3e9ed3d JR |
2804 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2805 | skip_emulated_instruction(&svm->vcpu); | |
2806 | ||
9966bf68 | 2807 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 2808 | nested_svm_unmap(page); |
5542675b AG |
2809 | |
2810 | return 1; | |
2811 | } | |
2812 | ||
851ba692 | 2813 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2814 | { |
9966bf68 | 2815 | struct vmcb *nested_vmcb; |
7597f129 | 2816 | struct page *page; |
9966bf68 | 2817 | |
5542675b AG |
2818 | if (nested_svm_check_permissions(svm)) |
2819 | return 1; | |
2820 | ||
7597f129 | 2821 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2822 | if (!nested_vmcb) |
2823 | return 1; | |
2824 | ||
e3e9ed3d JR |
2825 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2826 | skip_emulated_instruction(&svm->vcpu); | |
2827 | ||
9966bf68 | 2828 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 2829 | nested_svm_unmap(page); |
5542675b AG |
2830 | |
2831 | return 1; | |
2832 | } | |
2833 | ||
851ba692 | 2834 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2835 | { |
3d6368ef AG |
2836 | if (nested_svm_check_permissions(svm)) |
2837 | return 1; | |
2838 | ||
b75f4eb3 RJ |
2839 | /* Save rip after vmrun instruction */ |
2840 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2841 | |
9738b2c9 | 2842 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2843 | return 1; |
2844 | ||
9738b2c9 | 2845 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2846 | goto failed; |
2847 | ||
2848 | return 1; | |
2849 | ||
2850 | failed: | |
2851 | ||
2852 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2853 | svm->vmcb->control.exit_code_hi = 0; | |
2854 | svm->vmcb->control.exit_info_1 = 0; | |
2855 | svm->vmcb->control.exit_info_2 = 0; | |
2856 | ||
2857 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2858 | |
2859 | return 1; | |
2860 | } | |
2861 | ||
851ba692 | 2862 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2863 | { |
2864 | if (nested_svm_check_permissions(svm)) | |
2865 | return 1; | |
2866 | ||
2867 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2868 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2869 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2870 | |
2af9194d | 2871 | enable_gif(svm); |
1371d904 AG |
2872 | |
2873 | return 1; | |
2874 | } | |
2875 | ||
851ba692 | 2876 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2877 | { |
2878 | if (nested_svm_check_permissions(svm)) | |
2879 | return 1; | |
2880 | ||
2881 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2882 | skip_emulated_instruction(&svm->vcpu); | |
2883 | ||
2af9194d | 2884 | disable_gif(svm); |
1371d904 AG |
2885 | |
2886 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
2887 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
2888 | svm_clear_vintr(svm); | |
2889 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2890 | mark_dirty(svm->vmcb, VMCB_INTR); | |
2891 | } | |
decdbf6a | 2892 | |
1371d904 AG |
2893 | return 1; |
2894 | } | |
2895 | ||
851ba692 | 2896 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2897 | { |
2898 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2899 | |
668f198f DK |
2900 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX), |
2901 | kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); | |
ec1ff790 | 2902 | |
ff092385 | 2903 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
668f198f | 2904 | kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
ff092385 AG |
2905 | |
2906 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2907 | skip_emulated_instruction(&svm->vcpu); | |
2908 | return 1; | |
2909 | } | |
2910 | ||
532a46b9 JR |
2911 | static int skinit_interception(struct vcpu_svm *svm) |
2912 | { | |
668f198f | 2913 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
532a46b9 JR |
2914 | |
2915 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2916 | return 1; | |
2917 | } | |
2918 | ||
dab429a7 DK |
2919 | static int wbinvd_interception(struct vcpu_svm *svm) |
2920 | { | |
2921 | kvm_emulate_wbinvd(&svm->vcpu); | |
2922 | return 1; | |
2923 | } | |
2924 | ||
81dd35d4 JR |
2925 | static int xsetbv_interception(struct vcpu_svm *svm) |
2926 | { | |
2927 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2928 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2929 | ||
2930 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2931 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2932 | skip_emulated_instruction(&svm->vcpu); | |
2933 | } | |
2934 | ||
2935 | return 1; | |
2936 | } | |
2937 | ||
851ba692 | 2938 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2939 | { |
37817f29 | 2940 | u16 tss_selector; |
64a7ec06 GN |
2941 | int reason; |
2942 | int int_type = svm->vmcb->control.exit_int_info & | |
2943 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2944 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2945 | uint32_t type = |
2946 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2947 | uint32_t idt_v = | |
2948 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2949 | bool has_error_code = false; |
2950 | u32 error_code = 0; | |
37817f29 IE |
2951 | |
2952 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2953 | |
37817f29 IE |
2954 | if (svm->vmcb->control.exit_info_2 & |
2955 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2956 | reason = TASK_SWITCH_IRET; |
2957 | else if (svm->vmcb->control.exit_info_2 & | |
2958 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2959 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2960 | else if (idt_v) |
64a7ec06 GN |
2961 | reason = TASK_SWITCH_GATE; |
2962 | else | |
2963 | reason = TASK_SWITCH_CALL; | |
2964 | ||
fe8e7f83 GN |
2965 | if (reason == TASK_SWITCH_GATE) { |
2966 | switch (type) { | |
2967 | case SVM_EXITINTINFO_TYPE_NMI: | |
2968 | svm->vcpu.arch.nmi_injected = false; | |
2969 | break; | |
2970 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2971 | if (svm->vmcb->control.exit_info_2 & |
2972 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2973 | has_error_code = true; | |
2974 | error_code = | |
2975 | (u32)svm->vmcb->control.exit_info_2; | |
2976 | } | |
fe8e7f83 GN |
2977 | kvm_clear_exception_queue(&svm->vcpu); |
2978 | break; | |
2979 | case SVM_EXITINTINFO_TYPE_INTR: | |
2980 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2981 | break; | |
2982 | default: | |
2983 | break; | |
2984 | } | |
2985 | } | |
64a7ec06 | 2986 | |
8317c298 GN |
2987 | if (reason != TASK_SWITCH_GATE || |
2988 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2989 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2990 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2991 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2992 | |
7f3d35fd KW |
2993 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
2994 | int_vec = -1; | |
2995 | ||
2996 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
2997 | has_error_code, error_code) == EMULATE_FAIL) { |
2998 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2999 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3000 | svm->vcpu.run->internal.ndata = 0; | |
3001 | return 0; | |
3002 | } | |
3003 | return 1; | |
6aa8b732 AK |
3004 | } |
3005 | ||
851ba692 | 3006 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3007 | { |
5fdbf976 | 3008 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3009 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 3010 | return 1; |
6aa8b732 AK |
3011 | } |
3012 | ||
851ba692 | 3013 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3014 | { |
3015 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3016 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3017 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3018 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3019 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3020 | return 1; |
3021 | } | |
3022 | ||
851ba692 | 3023 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3024 | { |
df4f3108 AP |
3025 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3026 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
3027 | ||
3028 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
3029 | skip_emulated_instruction(&svm->vcpu); | |
3030 | return 1; | |
a7052897 MT |
3031 | } |
3032 | ||
851ba692 | 3033 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3034 | { |
51d8b661 | 3035 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
3036 | } |
3037 | ||
332b56e4 AK |
3038 | static int rdpmc_interception(struct vcpu_svm *svm) |
3039 | { | |
3040 | int err; | |
3041 | ||
3042 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
3043 | return emulate_on_interception(svm); | |
3044 | ||
3045 | err = kvm_rdpmc(&svm->vcpu); | |
3046 | kvm_complete_insn_gp(&svm->vcpu, err); | |
3047 | ||
3048 | return 1; | |
3049 | } | |
3050 | ||
52eb5a6d XL |
3051 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3052 | unsigned long val) | |
628afd2a JR |
3053 | { |
3054 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3055 | bool ret = false; | |
3056 | u64 intercept; | |
3057 | ||
3058 | intercept = svm->nested.intercept; | |
3059 | ||
3060 | if (!is_guest_mode(&svm->vcpu) || | |
3061 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
3062 | return false; | |
3063 | ||
3064 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
3065 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
3066 | ||
3067 | if (cr0 ^ val) { | |
3068 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3069 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
3070 | } | |
3071 | ||
3072 | return ret; | |
3073 | } | |
3074 | ||
7ff76d58 AP |
3075 | #define CR_VALID (1ULL << 63) |
3076 | ||
3077 | static int cr_interception(struct vcpu_svm *svm) | |
3078 | { | |
3079 | int reg, cr; | |
3080 | unsigned long val; | |
3081 | int err; | |
3082 | ||
3083 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
3084 | return emulate_on_interception(svm); | |
3085 | ||
3086 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
3087 | return emulate_on_interception(svm); | |
3088 | ||
3089 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
3090 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
3091 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
3092 | else | |
3093 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
3094 | |
3095 | err = 0; | |
3096 | if (cr >= 16) { /* mov to cr */ | |
3097 | cr -= 16; | |
3098 | val = kvm_register_read(&svm->vcpu, reg); | |
3099 | switch (cr) { | |
3100 | case 0: | |
628afd2a JR |
3101 | if (!check_selective_cr0_intercepted(svm, val)) |
3102 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
3103 | else |
3104 | return 1; | |
3105 | ||
7ff76d58 AP |
3106 | break; |
3107 | case 3: | |
3108 | err = kvm_set_cr3(&svm->vcpu, val); | |
3109 | break; | |
3110 | case 4: | |
3111 | err = kvm_set_cr4(&svm->vcpu, val); | |
3112 | break; | |
3113 | case 8: | |
3114 | err = kvm_set_cr8(&svm->vcpu, val); | |
3115 | break; | |
3116 | default: | |
3117 | WARN(1, "unhandled write to CR%d", cr); | |
3118 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3119 | return 1; | |
3120 | } | |
3121 | } else { /* mov from cr */ | |
3122 | switch (cr) { | |
3123 | case 0: | |
3124 | val = kvm_read_cr0(&svm->vcpu); | |
3125 | break; | |
3126 | case 2: | |
3127 | val = svm->vcpu.arch.cr2; | |
3128 | break; | |
3129 | case 3: | |
9f8fe504 | 3130 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
3131 | break; |
3132 | case 4: | |
3133 | val = kvm_read_cr4(&svm->vcpu); | |
3134 | break; | |
3135 | case 8: | |
3136 | val = kvm_get_cr8(&svm->vcpu); | |
3137 | break; | |
3138 | default: | |
3139 | WARN(1, "unhandled read from CR%d", cr); | |
3140 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3141 | return 1; | |
3142 | } | |
3143 | kvm_register_write(&svm->vcpu, reg, val); | |
3144 | } | |
3145 | kvm_complete_insn_gp(&svm->vcpu, err); | |
3146 | ||
3147 | return 1; | |
3148 | } | |
3149 | ||
cae3797a AP |
3150 | static int dr_interception(struct vcpu_svm *svm) |
3151 | { | |
3152 | int reg, dr; | |
3153 | unsigned long val; | |
cae3797a | 3154 | |
facb0139 PB |
3155 | if (svm->vcpu.guest_debug == 0) { |
3156 | /* | |
3157 | * No more DR vmexits; force a reload of the debug registers | |
3158 | * and reenter on this instruction. The next vmexit will | |
3159 | * retrieve the full state of the debug registers. | |
3160 | */ | |
3161 | clr_dr_intercepts(svm); | |
3162 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
3163 | return 1; | |
3164 | } | |
3165 | ||
cae3797a AP |
3166 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3167 | return emulate_on_interception(svm); | |
3168 | ||
3169 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
3170 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
3171 | ||
3172 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
3173 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
3174 | return 1; | |
cae3797a AP |
3175 | val = kvm_register_read(&svm->vcpu, reg); |
3176 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
3177 | } else { | |
16f8a6f9 NA |
3178 | if (!kvm_require_dr(&svm->vcpu, dr)) |
3179 | return 1; | |
3180 | kvm_get_dr(&svm->vcpu, dr, &val); | |
3181 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
3182 | } |
3183 | ||
2c46d2ae JR |
3184 | skip_emulated_instruction(&svm->vcpu); |
3185 | ||
cae3797a AP |
3186 | return 1; |
3187 | } | |
3188 | ||
851ba692 | 3189 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 3190 | { |
851ba692 | 3191 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 3192 | int r; |
851ba692 | 3193 | |
0a5fff19 GN |
3194 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
3195 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 3196 | r = cr_interception(svm); |
35754c98 | 3197 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 3198 | return r; |
0a5fff19 | 3199 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3200 | return r; |
1d075434 JR |
3201 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3202 | return 0; | |
3203 | } | |
3204 | ||
48d89b92 | 3205 | static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d NHE |
3206 | { |
3207 | struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu)); | |
4ba76538 | 3208 | return vmcb->control.tsc_offset + host_tsc; |
d5c1785d NHE |
3209 | } |
3210 | ||
609e36d3 | 3211 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3212 | { |
a2fa3e9f GH |
3213 | struct vcpu_svm *svm = to_svm(vcpu); |
3214 | ||
609e36d3 | 3215 | switch (msr_info->index) { |
af24a4e4 | 3216 | case MSR_IA32_TSC: { |
609e36d3 | 3217 | msr_info->data = svm->vmcb->control.tsc_offset + |
35181e86 | 3218 | kvm_scale_tsc(vcpu, rdtsc()); |
fbc0db76 | 3219 | |
6aa8b732 AK |
3220 | break; |
3221 | } | |
8c06585d | 3222 | case MSR_STAR: |
609e36d3 | 3223 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 3224 | break; |
0e859cac | 3225 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3226 | case MSR_LSTAR: |
609e36d3 | 3227 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3228 | break; |
3229 | case MSR_CSTAR: | |
609e36d3 | 3230 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3231 | break; |
3232 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 3233 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3234 | break; |
3235 | case MSR_SYSCALL_MASK: | |
609e36d3 | 3236 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3237 | break; |
3238 | #endif | |
3239 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3240 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3241 | break; |
3242 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3243 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
3244 | break; |
3245 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3246 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 3247 | break; |
46896c73 PB |
3248 | case MSR_TSC_AUX: |
3249 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3250 | return 1; | |
3251 | msr_info->data = svm->tsc_aux; | |
3252 | break; | |
e0231715 JR |
3253 | /* |
3254 | * Nobody will change the following 5 values in the VMCB so we can | |
3255 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3256 | * implemented. | |
3257 | */ | |
a2938c80 | 3258 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 3259 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
3260 | break; |
3261 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 3262 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
3263 | break; |
3264 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 3265 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
3266 | break; |
3267 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 3268 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
3269 | break; |
3270 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 3271 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 3272 | break; |
b286d5d8 | 3273 | case MSR_VM_HSAVE_PA: |
609e36d3 | 3274 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 3275 | break; |
eb6f302e | 3276 | case MSR_VM_CR: |
609e36d3 | 3277 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 3278 | break; |
c8a73f18 | 3279 | case MSR_IA32_UCODE_REV: |
609e36d3 | 3280 | msr_info->data = 0x01000065; |
c8a73f18 | 3281 | break; |
ae8b7875 BP |
3282 | case MSR_F15H_IC_CFG: { |
3283 | ||
3284 | int family, model; | |
3285 | ||
3286 | family = guest_cpuid_family(vcpu); | |
3287 | model = guest_cpuid_model(vcpu); | |
3288 | ||
3289 | if (family < 0 || model < 0) | |
3290 | return kvm_get_msr_common(vcpu, msr_info); | |
3291 | ||
3292 | msr_info->data = 0; | |
3293 | ||
3294 | if (family == 0x15 && | |
3295 | (model >= 0x2 && model < 0x20)) | |
3296 | msr_info->data = 0x1E; | |
3297 | } | |
3298 | break; | |
6aa8b732 | 3299 | default: |
609e36d3 | 3300 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3301 | } |
3302 | return 0; | |
3303 | } | |
3304 | ||
851ba692 | 3305 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3306 | { |
668f198f | 3307 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
609e36d3 | 3308 | struct msr_data msr_info; |
6aa8b732 | 3309 | |
609e36d3 PB |
3310 | msr_info.index = ecx; |
3311 | msr_info.host_initiated = false; | |
3312 | if (svm_get_msr(&svm->vcpu, &msr_info)) { | |
59200273 | 3313 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3314 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3315 | } else { |
609e36d3 | 3316 | trace_kvm_msr_read(ecx, msr_info.data); |
af9ca2d7 | 3317 | |
609e36d3 PB |
3318 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, |
3319 | msr_info.data & 0xffffffff); | |
3320 | kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, | |
3321 | msr_info.data >> 32); | |
5fdbf976 | 3322 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3323 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3324 | } |
3325 | return 1; | |
3326 | } | |
3327 | ||
4a810181 JR |
3328 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3329 | { | |
3330 | struct vcpu_svm *svm = to_svm(vcpu); | |
3331 | int svm_dis, chg_mask; | |
3332 | ||
3333 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3334 | return 1; | |
3335 | ||
3336 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3337 | ||
3338 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3339 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3340 | ||
3341 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3342 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3343 | ||
3344 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3345 | ||
3346 | /* check for svm_disable while efer.svme is set */ | |
3347 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3348 | return 1; | |
3349 | ||
3350 | return 0; | |
3351 | } | |
3352 | ||
8fe8ab46 | 3353 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3354 | { |
a2fa3e9f GH |
3355 | struct vcpu_svm *svm = to_svm(vcpu); |
3356 | ||
8fe8ab46 WA |
3357 | u32 ecx = msr->index; |
3358 | u64 data = msr->data; | |
6aa8b732 | 3359 | switch (ecx) { |
f4e1b3c8 | 3360 | case MSR_IA32_TSC: |
8fe8ab46 | 3361 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3362 | break; |
8c06585d | 3363 | case MSR_STAR: |
a2fa3e9f | 3364 | svm->vmcb->save.star = data; |
6aa8b732 | 3365 | break; |
49b14f24 | 3366 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3367 | case MSR_LSTAR: |
a2fa3e9f | 3368 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3369 | break; |
3370 | case MSR_CSTAR: | |
a2fa3e9f | 3371 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3372 | break; |
3373 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3374 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3375 | break; |
3376 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3377 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3378 | break; |
3379 | #endif | |
3380 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3381 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3382 | break; |
3383 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3384 | svm->sysenter_eip = data; |
a2fa3e9f | 3385 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3386 | break; |
3387 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3388 | svm->sysenter_esp = data; |
a2fa3e9f | 3389 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3390 | break; |
46896c73 PB |
3391 | case MSR_TSC_AUX: |
3392 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3393 | return 1; | |
3394 | ||
3395 | /* | |
3396 | * This is rare, so we update the MSR here instead of using | |
3397 | * direct_access_msrs. Doing that would require a rdmsr in | |
3398 | * svm_vcpu_put. | |
3399 | */ | |
3400 | svm->tsc_aux = data; | |
3401 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
3402 | break; | |
a2938c80 | 3403 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3404 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3405 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3406 | __func__, data); | |
24e09cbf JR |
3407 | break; |
3408 | } | |
3409 | if (data & DEBUGCTL_RESERVED_BITS) | |
3410 | return 1; | |
3411 | ||
3412 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3413 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3414 | if (data & (1ULL<<0)) |
3415 | svm_enable_lbrv(svm); | |
3416 | else | |
3417 | svm_disable_lbrv(svm); | |
a2938c80 | 3418 | break; |
b286d5d8 | 3419 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3420 | svm->nested.hsave_msr = data; |
62b9abaa | 3421 | break; |
3c5d0a44 | 3422 | case MSR_VM_CR: |
4a810181 | 3423 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3424 | case MSR_VM_IGNNE: |
a737f256 | 3425 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3426 | break; |
44a95dae SS |
3427 | case MSR_IA32_APICBASE: |
3428 | if (kvm_vcpu_apicv_active(vcpu)) | |
3429 | avic_update_vapic_bar(to_svm(vcpu), data); | |
3430 | /* Follow through */ | |
6aa8b732 | 3431 | default: |
8fe8ab46 | 3432 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3433 | } |
3434 | return 0; | |
3435 | } | |
3436 | ||
851ba692 | 3437 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3438 | { |
8fe8ab46 | 3439 | struct msr_data msr; |
668f198f DK |
3440 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
3441 | u64 data = kvm_read_edx_eax(&svm->vcpu); | |
af9ca2d7 | 3442 | |
8fe8ab46 WA |
3443 | msr.data = data; |
3444 | msr.index = ecx; | |
3445 | msr.host_initiated = false; | |
af9ca2d7 | 3446 | |
5fdbf976 | 3447 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
854e8bb1 | 3448 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3449 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3450 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3451 | } else { |
3452 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3453 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3454 | } |
6aa8b732 AK |
3455 | return 1; |
3456 | } | |
3457 | ||
851ba692 | 3458 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3459 | { |
e756fc62 | 3460 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3461 | return wrmsr_interception(svm); |
6aa8b732 | 3462 | else |
851ba692 | 3463 | return rdmsr_interception(svm); |
6aa8b732 AK |
3464 | } |
3465 | ||
851ba692 | 3466 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3467 | { |
3842d135 | 3468 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3469 | svm_clear_vintr(svm); |
85f455f7 | 3470 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3471 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3472 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3473 | return 1; |
3474 | } | |
3475 | ||
565d0998 ML |
3476 | static int pause_interception(struct vcpu_svm *svm) |
3477 | { | |
3478 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3479 | return 1; | |
3480 | } | |
3481 | ||
87c00572 GS |
3482 | static int nop_interception(struct vcpu_svm *svm) |
3483 | { | |
3484 | skip_emulated_instruction(&(svm->vcpu)); | |
3485 | return 1; | |
3486 | } | |
3487 | ||
3488 | static int monitor_interception(struct vcpu_svm *svm) | |
3489 | { | |
3490 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
3491 | return nop_interception(svm); | |
3492 | } | |
3493 | ||
3494 | static int mwait_interception(struct vcpu_svm *svm) | |
3495 | { | |
3496 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
3497 | return nop_interception(svm); | |
3498 | } | |
3499 | ||
18f40c53 SS |
3500 | enum avic_ipi_failure_cause { |
3501 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
3502 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
3503 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
3504 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
3505 | }; | |
3506 | ||
3507 | static int avic_incomplete_ipi_interception(struct vcpu_svm *svm) | |
3508 | { | |
3509 | u32 icrh = svm->vmcb->control.exit_info_1 >> 32; | |
3510 | u32 icrl = svm->vmcb->control.exit_info_1; | |
3511 | u32 id = svm->vmcb->control.exit_info_2 >> 32; | |
3512 | u32 index = svm->vmcb->control.exit_info_2 && 0xFF; | |
3513 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3514 | ||
3515 | trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); | |
3516 | ||
3517 | switch (id) { | |
3518 | case AVIC_IPI_FAILURE_INVALID_INT_TYPE: | |
3519 | /* | |
3520 | * AVIC hardware handles the generation of | |
3521 | * IPIs when the specified Message Type is Fixed | |
3522 | * (also known as fixed delivery mode) and | |
3523 | * the Trigger Mode is edge-triggered. The hardware | |
3524 | * also supports self and broadcast delivery modes | |
3525 | * specified via the Destination Shorthand(DSH) | |
3526 | * field of the ICRL. Logical and physical APIC ID | |
3527 | * formats are supported. All other IPI types cause | |
3528 | * a #VMEXIT, which needs to emulated. | |
3529 | */ | |
3530 | kvm_lapic_reg_write(apic, APIC_ICR2, icrh); | |
3531 | kvm_lapic_reg_write(apic, APIC_ICR, icrl); | |
3532 | break; | |
3533 | case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { | |
3534 | int i; | |
3535 | struct kvm_vcpu *vcpu; | |
3536 | struct kvm *kvm = svm->vcpu.kvm; | |
3537 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3538 | ||
3539 | /* | |
3540 | * At this point, we expect that the AVIC HW has already | |
3541 | * set the appropriate IRR bits on the valid target | |
3542 | * vcpus. So, we just need to kick the appropriate vcpu. | |
3543 | */ | |
3544 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
3545 | bool m = kvm_apic_match_dest(vcpu, apic, | |
3546 | icrl & KVM_APIC_SHORT_MASK, | |
3547 | GET_APIC_DEST_FIELD(icrh), | |
3548 | icrl & KVM_APIC_DEST_MASK); | |
3549 | ||
3550 | if (m && !avic_vcpu_is_running(vcpu)) | |
3551 | kvm_vcpu_wake_up(vcpu); | |
3552 | } | |
3553 | break; | |
3554 | } | |
3555 | case AVIC_IPI_FAILURE_INVALID_TARGET: | |
3556 | break; | |
3557 | case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: | |
3558 | WARN_ONCE(1, "Invalid backing page\n"); | |
3559 | break; | |
3560 | default: | |
3561 | pr_err("Unknown IPI interception\n"); | |
3562 | } | |
3563 | ||
3564 | return 1; | |
3565 | } | |
3566 | ||
3567 | static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) | |
3568 | { | |
3569 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
3570 | int index; | |
3571 | u32 *logical_apic_id_table; | |
3572 | int dlid = GET_APIC_LOGICAL_ID(ldr); | |
3573 | ||
3574 | if (!dlid) | |
3575 | return NULL; | |
3576 | ||
3577 | if (flat) { /* flat */ | |
3578 | index = ffs(dlid) - 1; | |
3579 | if (index > 7) | |
3580 | return NULL; | |
3581 | } else { /* cluster */ | |
3582 | int cluster = (dlid & 0xf0) >> 4; | |
3583 | int apic = ffs(dlid & 0x0f) - 1; | |
3584 | ||
3585 | if ((apic < 0) || (apic > 7) || | |
3586 | (cluster >= 0xf)) | |
3587 | return NULL; | |
3588 | index = (cluster << 2) + apic; | |
3589 | } | |
3590 | ||
3591 | logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page); | |
3592 | ||
3593 | return &logical_apic_id_table[index]; | |
3594 | } | |
3595 | ||
3596 | static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr, | |
3597 | bool valid) | |
3598 | { | |
3599 | bool flat; | |
3600 | u32 *entry, new_entry; | |
3601 | ||
3602 | flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; | |
3603 | entry = avic_get_logical_id_entry(vcpu, ldr, flat); | |
3604 | if (!entry) | |
3605 | return -EINVAL; | |
3606 | ||
3607 | new_entry = READ_ONCE(*entry); | |
3608 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; | |
3609 | new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); | |
3610 | if (valid) | |
3611 | new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3612 | else | |
3613 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3614 | WRITE_ONCE(*entry, new_entry); | |
3615 | ||
3616 | return 0; | |
3617 | } | |
3618 | ||
3619 | static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) | |
3620 | { | |
3621 | int ret; | |
3622 | struct vcpu_svm *svm = to_svm(vcpu); | |
3623 | u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); | |
3624 | ||
3625 | if (!ldr) | |
3626 | return 1; | |
3627 | ||
3628 | ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true); | |
3629 | if (ret && svm->ldr_reg) { | |
3630 | avic_ldr_write(vcpu, 0, svm->ldr_reg, false); | |
3631 | svm->ldr_reg = 0; | |
3632 | } else { | |
3633 | svm->ldr_reg = ldr; | |
3634 | } | |
3635 | return ret; | |
3636 | } | |
3637 | ||
3638 | static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) | |
3639 | { | |
3640 | u64 *old, *new; | |
3641 | struct vcpu_svm *svm = to_svm(vcpu); | |
3642 | u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID); | |
3643 | u32 id = (apic_id_reg >> 24) & 0xff; | |
3644 | ||
3645 | if (vcpu->vcpu_id == id) | |
3646 | return 0; | |
3647 | ||
3648 | old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); | |
3649 | new = avic_get_physical_id_entry(vcpu, id); | |
3650 | if (!new || !old) | |
3651 | return 1; | |
3652 | ||
3653 | /* We need to move physical_id_entry to new offset */ | |
3654 | *new = *old; | |
3655 | *old = 0ULL; | |
3656 | to_svm(vcpu)->avic_physical_id_cache = new; | |
3657 | ||
3658 | /* | |
3659 | * Also update the guest physical APIC ID in the logical | |
3660 | * APIC ID table entry if already setup the LDR. | |
3661 | */ | |
3662 | if (svm->ldr_reg) | |
3663 | avic_handle_ldr_update(vcpu); | |
3664 | ||
3665 | return 0; | |
3666 | } | |
3667 | ||
3668 | static int avic_handle_dfr_update(struct kvm_vcpu *vcpu) | |
3669 | { | |
3670 | struct vcpu_svm *svm = to_svm(vcpu); | |
3671 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
3672 | u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); | |
3673 | u32 mod = (dfr >> 28) & 0xf; | |
3674 | ||
3675 | /* | |
3676 | * We assume that all local APICs are using the same type. | |
3677 | * If this changes, we need to flush the AVIC logical | |
3678 | * APID id table. | |
3679 | */ | |
3680 | if (vm_data->ldr_mode == mod) | |
3681 | return 0; | |
3682 | ||
3683 | clear_page(page_address(vm_data->avic_logical_id_table_page)); | |
3684 | vm_data->ldr_mode = mod; | |
3685 | ||
3686 | if (svm->ldr_reg) | |
3687 | avic_handle_ldr_update(vcpu); | |
3688 | return 0; | |
3689 | } | |
3690 | ||
3691 | static int avic_unaccel_trap_write(struct vcpu_svm *svm) | |
3692 | { | |
3693 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3694 | u32 offset = svm->vmcb->control.exit_info_1 & | |
3695 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
3696 | ||
3697 | switch (offset) { | |
3698 | case APIC_ID: | |
3699 | if (avic_handle_apic_id_update(&svm->vcpu)) | |
3700 | return 0; | |
3701 | break; | |
3702 | case APIC_LDR: | |
3703 | if (avic_handle_ldr_update(&svm->vcpu)) | |
3704 | return 0; | |
3705 | break; | |
3706 | case APIC_DFR: | |
3707 | avic_handle_dfr_update(&svm->vcpu); | |
3708 | break; | |
3709 | default: | |
3710 | break; | |
3711 | } | |
3712 | ||
3713 | kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); | |
3714 | ||
3715 | return 1; | |
3716 | } | |
3717 | ||
3718 | static bool is_avic_unaccelerated_access_trap(u32 offset) | |
3719 | { | |
3720 | bool ret = false; | |
3721 | ||
3722 | switch (offset) { | |
3723 | case APIC_ID: | |
3724 | case APIC_EOI: | |
3725 | case APIC_RRR: | |
3726 | case APIC_LDR: | |
3727 | case APIC_DFR: | |
3728 | case APIC_SPIV: | |
3729 | case APIC_ESR: | |
3730 | case APIC_ICR: | |
3731 | case APIC_LVTT: | |
3732 | case APIC_LVTTHMR: | |
3733 | case APIC_LVTPC: | |
3734 | case APIC_LVT0: | |
3735 | case APIC_LVT1: | |
3736 | case APIC_LVTERR: | |
3737 | case APIC_TMICT: | |
3738 | case APIC_TDCR: | |
3739 | ret = true; | |
3740 | break; | |
3741 | default: | |
3742 | break; | |
3743 | } | |
3744 | return ret; | |
3745 | } | |
3746 | ||
3747 | static int avic_unaccelerated_access_interception(struct vcpu_svm *svm) | |
3748 | { | |
3749 | int ret = 0; | |
3750 | u32 offset = svm->vmcb->control.exit_info_1 & | |
3751 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
3752 | u32 vector = svm->vmcb->control.exit_info_2 & | |
3753 | AVIC_UNACCEL_ACCESS_VECTOR_MASK; | |
3754 | bool write = (svm->vmcb->control.exit_info_1 >> 32) & | |
3755 | AVIC_UNACCEL_ACCESS_WRITE_MASK; | |
3756 | bool trap = is_avic_unaccelerated_access_trap(offset); | |
3757 | ||
3758 | trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, | |
3759 | trap, write, vector); | |
3760 | if (trap) { | |
3761 | /* Handling Trap */ | |
3762 | WARN_ONCE(!write, "svm: Handling trap read.\n"); | |
3763 | ret = avic_unaccel_trap_write(svm); | |
3764 | } else { | |
3765 | /* Handling Fault */ | |
3766 | ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE); | |
3767 | } | |
3768 | ||
3769 | return ret; | |
3770 | } | |
3771 | ||
09941fbb | 3772 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3773 | [SVM_EXIT_READ_CR0] = cr_interception, |
3774 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3775 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3776 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 3777 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 3778 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3779 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3780 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3781 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3782 | [SVM_EXIT_READ_DR0] = dr_interception, |
3783 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3784 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3785 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3786 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3787 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3788 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3789 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3790 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3791 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3792 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3793 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3794 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3795 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3796 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3797 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3798 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3799 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3800 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3801 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3802 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3803 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
54a20552 | 3804 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
e0231715 | 3805 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 3806 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3807 | [SVM_EXIT_SMI] = nop_on_interception, |
3808 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3809 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 3810 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 3811 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3812 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3813 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3814 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3815 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3816 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3817 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3818 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3819 | [SVM_EXIT_MSR] = msr_interception, |
3820 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3821 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3822 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3823 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3824 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3825 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3826 | [SVM_EXIT_STGI] = stgi_interception, |
3827 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3828 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 3829 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
3830 | [SVM_EXIT_MONITOR] = monitor_interception, |
3831 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 3832 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3833 | [SVM_EXIT_NPF] = pf_interception, |
64d60670 | 3834 | [SVM_EXIT_RSM] = emulate_on_interception, |
18f40c53 SS |
3835 | [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, |
3836 | [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, | |
6aa8b732 AK |
3837 | }; |
3838 | ||
ae8cc059 | 3839 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
3840 | { |
3841 | struct vcpu_svm *svm = to_svm(vcpu); | |
3842 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3843 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3844 | ||
3845 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
3846 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
3847 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
3848 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
3849 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
3850 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
3851 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
3852 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
3853 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
3854 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
3855 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
3856 | pr_err("%-20s%d\n", "asid:", control->asid); | |
3857 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
3858 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
3859 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
3860 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
3861 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
3862 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
3863 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
3864 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
3865 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
3866 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
3867 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 3868 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
3869 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
3870 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
3871 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
3872 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
44a95dae SS |
3873 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
3874 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
3875 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 3876 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
3877 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
3878 | "es:", | |
3879 | save->es.selector, save->es.attrib, | |
3880 | save->es.limit, save->es.base); | |
3881 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3882 | "cs:", | |
3883 | save->cs.selector, save->cs.attrib, | |
3884 | save->cs.limit, save->cs.base); | |
3885 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3886 | "ss:", | |
3887 | save->ss.selector, save->ss.attrib, | |
3888 | save->ss.limit, save->ss.base); | |
3889 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3890 | "ds:", | |
3891 | save->ds.selector, save->ds.attrib, | |
3892 | save->ds.limit, save->ds.base); | |
3893 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3894 | "fs:", | |
3895 | save->fs.selector, save->fs.attrib, | |
3896 | save->fs.limit, save->fs.base); | |
3897 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3898 | "gs:", | |
3899 | save->gs.selector, save->gs.attrib, | |
3900 | save->gs.limit, save->gs.base); | |
3901 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3902 | "gdtr:", | |
3903 | save->gdtr.selector, save->gdtr.attrib, | |
3904 | save->gdtr.limit, save->gdtr.base); | |
3905 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3906 | "ldtr:", | |
3907 | save->ldtr.selector, save->ldtr.attrib, | |
3908 | save->ldtr.limit, save->ldtr.base); | |
3909 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3910 | "idtr:", | |
3911 | save->idtr.selector, save->idtr.attrib, | |
3912 | save->idtr.limit, save->idtr.base); | |
3913 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3914 | "tr:", | |
3915 | save->tr.selector, save->tr.attrib, | |
3916 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
3917 | pr_err("cpl: %d efer: %016llx\n", |
3918 | save->cpl, save->efer); | |
ae8cc059 JP |
3919 | pr_err("%-15s %016llx %-13s %016llx\n", |
3920 | "cr0:", save->cr0, "cr2:", save->cr2); | |
3921 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3922 | "cr3:", save->cr3, "cr4:", save->cr4); | |
3923 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3924 | "dr6:", save->dr6, "dr7:", save->dr7); | |
3925 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3926 | "rip:", save->rip, "rflags:", save->rflags); | |
3927 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3928 | "rsp:", save->rsp, "rax:", save->rax); | |
3929 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3930 | "star:", save->star, "lstar:", save->lstar); | |
3931 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3932 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
3933 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3934 | "kernel_gs_base:", save->kernel_gs_base, | |
3935 | "sysenter_cs:", save->sysenter_cs); | |
3936 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3937 | "sysenter_esp:", save->sysenter_esp, | |
3938 | "sysenter_eip:", save->sysenter_eip); | |
3939 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3940 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
3941 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3942 | "br_from:", save->br_from, "br_to:", save->br_to); | |
3943 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3944 | "excp_from:", save->last_excp_from, | |
3945 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
3946 | } |
3947 | ||
586f9607 AK |
3948 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3949 | { | |
3950 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3951 | ||
3952 | *info1 = control->exit_info_1; | |
3953 | *info2 = control->exit_info_2; | |
3954 | } | |
3955 | ||
851ba692 | 3956 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3957 | { |
04d2cc77 | 3958 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3959 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3960 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3961 | |
8b89fe1f PB |
3962 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
3963 | ||
4ee546b4 | 3964 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3965 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3966 | if (npt_enabled) | |
3967 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3968 | |
cd3ff653 JR |
3969 | if (unlikely(svm->nested.exit_required)) { |
3970 | nested_svm_vmexit(svm); | |
3971 | svm->nested.exit_required = false; | |
3972 | ||
3973 | return 1; | |
3974 | } | |
3975 | ||
2030753d | 3976 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3977 | int vmexit; |
3978 | ||
d8cabddf JR |
3979 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3980 | svm->vmcb->control.exit_info_1, | |
3981 | svm->vmcb->control.exit_info_2, | |
3982 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
3983 | svm->vmcb->control.exit_int_info_err, |
3984 | KVM_ISA_SVM); | |
d8cabddf | 3985 | |
410e4d57 JR |
3986 | vmexit = nested_svm_exit_special(svm); |
3987 | ||
3988 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3989 | vmexit = nested_svm_exit_handled(svm); | |
3990 | ||
3991 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3992 | return 1; |
cf74a78b AG |
3993 | } |
3994 | ||
a5c3832d JR |
3995 | svm_complete_interrupts(svm); |
3996 | ||
04d2cc77 AK |
3997 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3998 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3999 | kvm_run->fail_entry.hardware_entry_failure_reason | |
4000 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
4001 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
4002 | dump_vmcb(vcpu); | |
04d2cc77 AK |
4003 | return 0; |
4004 | } | |
4005 | ||
a2fa3e9f | 4006 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 4007 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
4008 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
4009 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 4010 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 4011 | "exit_code 0x%x\n", |
b8688d51 | 4012 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
4013 | exit_code); |
4014 | ||
9d8f549d | 4015 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 4016 | || !svm_exit_handlers[exit_code]) { |
faac2458 | 4017 | WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code); |
2bc19dc3 MT |
4018 | kvm_queue_exception(vcpu, UD_VECTOR); |
4019 | return 1; | |
6aa8b732 AK |
4020 | } |
4021 | ||
851ba692 | 4022 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
4023 | } |
4024 | ||
4025 | static void reload_tss(struct kvm_vcpu *vcpu) | |
4026 | { | |
4027 | int cpu = raw_smp_processor_id(); | |
4028 | ||
0fe1e009 TH |
4029 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
4030 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
4031 | load_TR_desc(); |
4032 | } | |
4033 | ||
e756fc62 | 4034 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
4035 | { |
4036 | int cpu = raw_smp_processor_id(); | |
4037 | ||
0fe1e009 | 4038 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 4039 | |
4b656b12 | 4040 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
4041 | if (svm->asid_generation != sd->asid_generation) |
4042 | new_asid(svm, sd); | |
6aa8b732 AK |
4043 | } |
4044 | ||
95ba8273 GN |
4045 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
4046 | { | |
4047 | struct vcpu_svm *svm = to_svm(vcpu); | |
4048 | ||
4049 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
4050 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4051 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
4052 | ++vcpu->stat.nmi_injections; |
4053 | } | |
6aa8b732 | 4054 | |
85f455f7 | 4055 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
4056 | { |
4057 | struct vmcb_control_area *control; | |
4058 | ||
340d3bc3 | 4059 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 4060 | control = &svm->vmcb->control; |
85f455f7 | 4061 | control->int_vector = irq; |
6aa8b732 AK |
4062 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
4063 | control->int_ctl |= V_IRQ_MASK | | |
4064 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 4065 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
4066 | } |
4067 | ||
66fd3f7f | 4068 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
4069 | { |
4070 | struct vcpu_svm *svm = to_svm(vcpu); | |
4071 | ||
2af9194d | 4072 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 4073 | |
9fb2d2b4 GN |
4074 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
4075 | ++vcpu->stat.irq_injections; | |
4076 | ||
219b65dc AG |
4077 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
4078 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
4079 | } |
4080 | ||
95ba8273 | 4081 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
4082 | { |
4083 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 4084 | |
2030753d | 4085 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
4086 | return; |
4087 | ||
596f3142 RK |
4088 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
4089 | ||
95ba8273 | 4090 | if (irr == -1) |
aaacfc9a JR |
4091 | return; |
4092 | ||
95ba8273 | 4093 | if (tpr >= irr) |
4ee546b4 | 4094 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 4095 | } |
aaacfc9a | 4096 | |
8d14695f YZ |
4097 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
4098 | { | |
4099 | return; | |
4100 | } | |
4101 | ||
d62caabb AS |
4102 | static bool svm_get_enable_apicv(void) |
4103 | { | |
44a95dae SS |
4104 | return avic; |
4105 | } | |
4106 | ||
4107 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
4108 | { | |
4109 | } | |
4110 | ||
4111 | static void svm_hwapic_isr_update(struct kvm *kvm, int isr) | |
4112 | { | |
d62caabb AS |
4113 | } |
4114 | ||
44a95dae | 4115 | /* Note: Currently only used by Hyper-V. */ |
d62caabb | 4116 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 4117 | { |
44a95dae SS |
4118 | struct vcpu_svm *svm = to_svm(vcpu); |
4119 | struct vmcb *vmcb = svm->vmcb; | |
4120 | ||
4121 | if (!avic) | |
4122 | return; | |
4123 | ||
4124 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
4125 | mark_dirty(vmcb, VMCB_INTR); | |
c7c9c56c YZ |
4126 | } |
4127 | ||
6308630b | 4128 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
4129 | { |
4130 | return; | |
4131 | } | |
4132 | ||
a20ed54d YZ |
4133 | static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
4134 | { | |
4135 | return; | |
4136 | } | |
4137 | ||
340d3bc3 SS |
4138 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
4139 | { | |
4140 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
4141 | smp_mb__after_atomic(); | |
4142 | ||
4143 | if (avic_vcpu_is_running(vcpu)) | |
4144 | wrmsrl(SVM_AVIC_DOORBELL, | |
4145 | __default_cpu_present_to_apicid(vcpu->cpu)); | |
4146 | else | |
4147 | kvm_vcpu_wake_up(vcpu); | |
4148 | } | |
4149 | ||
95ba8273 GN |
4150 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
4151 | { | |
4152 | struct vcpu_svm *svm = to_svm(vcpu); | |
4153 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
4154 | int ret; |
4155 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
4156 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4157 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
4158 | ||
4159 | return ret; | |
aaacfc9a JR |
4160 | } |
4161 | ||
3cfc3092 JK |
4162 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
4163 | { | |
4164 | struct vcpu_svm *svm = to_svm(vcpu); | |
4165 | ||
4166 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4167 | } | |
4168 | ||
4169 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
4170 | { | |
4171 | struct vcpu_svm *svm = to_svm(vcpu); | |
4172 | ||
4173 | if (masked) { | |
4174 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4175 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4176 | } else { |
4177 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 4178 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4179 | } |
4180 | } | |
4181 | ||
78646121 GN |
4182 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
4183 | { | |
4184 | struct vcpu_svm *svm = to_svm(vcpu); | |
4185 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
4186 | int ret; |
4187 | ||
4188 | if (!gif_set(svm) || | |
4189 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
4190 | return 0; | |
4191 | ||
f6e78475 | 4192 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 4193 | |
2030753d | 4194 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
4195 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
4196 | ||
4197 | return ret; | |
78646121 GN |
4198 | } |
4199 | ||
c9a7953f | 4200 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 4201 | { |
219b65dc | 4202 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 4203 | |
340d3bc3 SS |
4204 | if (kvm_vcpu_apicv_active(vcpu)) |
4205 | return; | |
4206 | ||
e0231715 JR |
4207 | /* |
4208 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
4209 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
4210 | * get that intercept, this function will be called again though and | |
4211 | * we'll get the vintr intercept. | |
4212 | */ | |
8fe54654 | 4213 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
4214 | svm_set_vintr(svm); |
4215 | svm_inject_irq(svm, 0x0); | |
4216 | } | |
85f455f7 ED |
4217 | } |
4218 | ||
c9a7953f | 4219 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 4220 | { |
04d2cc77 | 4221 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 4222 | |
44c11430 GN |
4223 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
4224 | == HF_NMI_MASK) | |
c9a7953f | 4225 | return; /* IRET will cause a vm exit */ |
44c11430 | 4226 | |
e0231715 JR |
4227 | /* |
4228 | * Something prevents NMI from been injected. Single step over possible | |
4229 | * problem (IRET or exception injection or interrupt shadow) | |
4230 | */ | |
6be7d306 | 4231 | svm->nmi_singlestep = true; |
44c11430 | 4232 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
4233 | } |
4234 | ||
cbc94022 IE |
4235 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
4236 | { | |
4237 | return 0; | |
4238 | } | |
4239 | ||
d9e368d6 AK |
4240 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
4241 | { | |
38e5e92f JR |
4242 | struct vcpu_svm *svm = to_svm(vcpu); |
4243 | ||
4244 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
4245 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
4246 | else | |
4247 | svm->asid_generation--; | |
d9e368d6 AK |
4248 | } |
4249 | ||
04d2cc77 AK |
4250 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
4251 | { | |
4252 | } | |
4253 | ||
d7bf8221 JR |
4254 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
4255 | { | |
4256 | struct vcpu_svm *svm = to_svm(vcpu); | |
4257 | ||
2030753d | 4258 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
4259 | return; |
4260 | ||
4ee546b4 | 4261 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 4262 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 4263 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
4264 | } |
4265 | } | |
4266 | ||
649d6864 JR |
4267 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
4268 | { | |
4269 | struct vcpu_svm *svm = to_svm(vcpu); | |
4270 | u64 cr8; | |
4271 | ||
2030753d | 4272 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
4273 | return; |
4274 | ||
649d6864 JR |
4275 | cr8 = kvm_get_cr8(vcpu); |
4276 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
4277 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
4278 | } | |
4279 | ||
9222be18 GN |
4280 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
4281 | { | |
4282 | u8 vector; | |
4283 | int type; | |
4284 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
4285 | unsigned int3_injected = svm->int3_injected; |
4286 | ||
4287 | svm->int3_injected = 0; | |
9222be18 | 4288 | |
bd3d1ec3 AK |
4289 | /* |
4290 | * If we've made progress since setting HF_IRET_MASK, we've | |
4291 | * executed an IRET and can allow NMI injection. | |
4292 | */ | |
4293 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
4294 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 4295 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
4296 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4297 | } | |
44c11430 | 4298 | |
9222be18 GN |
4299 | svm->vcpu.arch.nmi_injected = false; |
4300 | kvm_clear_exception_queue(&svm->vcpu); | |
4301 | kvm_clear_interrupt_queue(&svm->vcpu); | |
4302 | ||
4303 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
4304 | return; | |
4305 | ||
3842d135 AK |
4306 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4307 | ||
9222be18 GN |
4308 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
4309 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
4310 | ||
4311 | switch (type) { | |
4312 | case SVM_EXITINTINFO_TYPE_NMI: | |
4313 | svm->vcpu.arch.nmi_injected = true; | |
4314 | break; | |
4315 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
4316 | /* |
4317 | * In case of software exceptions, do not reinject the vector, | |
4318 | * but re-execute the instruction instead. Rewind RIP first | |
4319 | * if we emulated INT3 before. | |
4320 | */ | |
4321 | if (kvm_exception_is_soft(vector)) { | |
4322 | if (vector == BP_VECTOR && int3_injected && | |
4323 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
4324 | kvm_rip_write(&svm->vcpu, | |
4325 | kvm_rip_read(&svm->vcpu) - | |
4326 | int3_injected); | |
9222be18 | 4327 | break; |
66b7138f | 4328 | } |
9222be18 GN |
4329 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
4330 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 4331 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
4332 | |
4333 | } else | |
ce7ddec4 | 4334 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
4335 | break; |
4336 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 4337 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
4338 | break; |
4339 | default: | |
4340 | break; | |
4341 | } | |
4342 | } | |
4343 | ||
b463a6f7 AK |
4344 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
4345 | { | |
4346 | struct vcpu_svm *svm = to_svm(vcpu); | |
4347 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4348 | ||
4349 | control->exit_int_info = control->event_inj; | |
4350 | control->exit_int_info_err = control->event_inj_err; | |
4351 | control->event_inj = 0; | |
4352 | svm_complete_interrupts(svm); | |
4353 | } | |
4354 | ||
851ba692 | 4355 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 4356 | { |
a2fa3e9f | 4357 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 4358 | |
2041a06a JR |
4359 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
4360 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
4361 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
4362 | ||
cd3ff653 JR |
4363 | /* |
4364 | * A vmexit emulation is required before the vcpu can be executed | |
4365 | * again. | |
4366 | */ | |
4367 | if (unlikely(svm->nested.exit_required)) | |
4368 | return; | |
4369 | ||
e756fc62 | 4370 | pre_svm_run(svm); |
6aa8b732 | 4371 | |
649d6864 JR |
4372 | sync_lapic_to_cr8(vcpu); |
4373 | ||
cda0ffdd | 4374 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 4375 | |
04d2cc77 AK |
4376 | clgi(); |
4377 | ||
4378 | local_irq_enable(); | |
36241b8c | 4379 | |
6aa8b732 | 4380 | asm volatile ( |
7454766f AK |
4381 | "push %%" _ASM_BP "; \n\t" |
4382 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
4383 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
4384 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
4385 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
4386 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
4387 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 4388 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4389 | "mov %c[r8](%[svm]), %%r8 \n\t" |
4390 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
4391 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
4392 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
4393 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
4394 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
4395 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
4396 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
4397 | #endif |
4398 | ||
6aa8b732 | 4399 | /* Enter guest mode */ |
7454766f AK |
4400 | "push %%" _ASM_AX " \n\t" |
4401 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
4402 | __ex(SVM_VMLOAD) "\n\t" |
4403 | __ex(SVM_VMRUN) "\n\t" | |
4404 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 4405 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
4406 | |
4407 | /* Save guest registers, load host registers */ | |
7454766f AK |
4408 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
4409 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
4410 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
4411 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
4412 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
4413 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 4414 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4415 | "mov %%r8, %c[r8](%[svm]) \n\t" |
4416 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
4417 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
4418 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
4419 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
4420 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
4421 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
4422 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 4423 | #endif |
7454766f | 4424 | "pop %%" _ASM_BP |
6aa8b732 | 4425 | : |
fb3f0f51 | 4426 | : [svm]"a"(svm), |
6aa8b732 | 4427 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
4428 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
4429 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
4430 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
4431 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
4432 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
4433 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 4434 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
4435 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
4436 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
4437 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
4438 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
4439 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
4440 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
4441 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
4442 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 4443 | #endif |
54a08c04 LV |
4444 | : "cc", "memory" |
4445 | #ifdef CONFIG_X86_64 | |
7454766f | 4446 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 4447 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
4448 | #else |
4449 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
4450 | #endif |
4451 | ); | |
6aa8b732 | 4452 | |
82ca2d10 AK |
4453 | #ifdef CONFIG_X86_64 |
4454 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
4455 | #else | |
dacccfdd | 4456 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
4457 | #ifndef CONFIG_X86_32_LAZY_GS |
4458 | loadsegment(gs, svm->host.gs); | |
4459 | #endif | |
9581d442 | 4460 | #endif |
6aa8b732 AK |
4461 | |
4462 | reload_tss(vcpu); | |
4463 | ||
56ba47dd AK |
4464 | local_irq_disable(); |
4465 | ||
13c34e07 AK |
4466 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
4467 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
4468 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
4469 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
4470 | ||
3781c01c JR |
4471 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
4472 | kvm_before_handle_nmi(&svm->vcpu); | |
4473 | ||
4474 | stgi(); | |
4475 | ||
4476 | /* Any pending NMI will happen here */ | |
4477 | ||
4478 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
4479 | kvm_after_handle_nmi(&svm->vcpu); | |
4480 | ||
d7bf8221 JR |
4481 | sync_cr8_to_lapic(vcpu); |
4482 | ||
a2fa3e9f | 4483 | svm->next_rip = 0; |
9222be18 | 4484 | |
38e5e92f JR |
4485 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4486 | ||
631bc487 GN |
4487 | /* if exit due to PF check for async PF */ |
4488 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
4489 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
4490 | ||
6de4f3ad AK |
4491 | if (npt_enabled) { |
4492 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
4493 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
4494 | } | |
fe5913e4 JR |
4495 | |
4496 | /* | |
4497 | * We need to handle MC intercepts here before the vcpu has a chance to | |
4498 | * change the physical cpu | |
4499 | */ | |
4500 | if (unlikely(svm->vmcb->control.exit_code == | |
4501 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
4502 | svm_handle_mce(svm); | |
8d28fec4 RJ |
4503 | |
4504 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
4505 | } |
4506 | ||
6aa8b732 AK |
4507 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
4508 | { | |
a2fa3e9f GH |
4509 | struct vcpu_svm *svm = to_svm(vcpu); |
4510 | ||
4511 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 4512 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 4513 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
4514 | } |
4515 | ||
1c97f0a0 JR |
4516 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
4517 | { | |
4518 | struct vcpu_svm *svm = to_svm(vcpu); | |
4519 | ||
4520 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 4521 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
4522 | |
4523 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 4524 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 4525 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 4526 | |
f40f6a45 | 4527 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
4528 | } |
4529 | ||
6aa8b732 AK |
4530 | static int is_disabled(void) |
4531 | { | |
6031a61c JR |
4532 | u64 vm_cr; |
4533 | ||
4534 | rdmsrl(MSR_VM_CR, vm_cr); | |
4535 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
4536 | return 1; | |
4537 | ||
6aa8b732 AK |
4538 | return 0; |
4539 | } | |
4540 | ||
102d8325 IM |
4541 | static void |
4542 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
4543 | { | |
4544 | /* | |
4545 | * Patch in the VMMCALL instruction: | |
4546 | */ | |
4547 | hypercall[0] = 0x0f; | |
4548 | hypercall[1] = 0x01; | |
4549 | hypercall[2] = 0xd9; | |
102d8325 IM |
4550 | } |
4551 | ||
002c7f7c YS |
4552 | static void svm_check_processor_compat(void *rtn) |
4553 | { | |
4554 | *(int *)rtn = 0; | |
4555 | } | |
4556 | ||
774ead3a AK |
4557 | static bool svm_cpu_has_accelerated_tpr(void) |
4558 | { | |
4559 | return false; | |
4560 | } | |
4561 | ||
6d396b55 PB |
4562 | static bool svm_has_high_real_mode_segbase(void) |
4563 | { | |
4564 | return true; | |
4565 | } | |
4566 | ||
fc07e76a PB |
4567 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
4568 | { | |
4569 | return 0; | |
4570 | } | |
4571 | ||
0e851880 SY |
4572 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
4573 | { | |
6092d3d3 | 4574 | struct vcpu_svm *svm = to_svm(vcpu); |
46781eae | 4575 | struct kvm_cpuid_entry2 *entry; |
6092d3d3 JR |
4576 | |
4577 | /* Update nrips enabled cache */ | |
4578 | svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu); | |
46781eae SS |
4579 | |
4580 | if (!kvm_vcpu_apicv_active(vcpu)) | |
4581 | return; | |
4582 | ||
4583 | entry = kvm_find_cpuid_entry(vcpu, 1, 0); | |
4584 | if (entry) | |
4585 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
0e851880 SY |
4586 | } |
4587 | ||
d4330ef2 JR |
4588 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
4589 | { | |
c2c63a49 | 4590 | switch (func) { |
46781eae SS |
4591 | case 0x1: |
4592 | if (avic) | |
4593 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
4594 | break; | |
4c62a2dc JR |
4595 | case 0x80000001: |
4596 | if (nested) | |
4597 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
4598 | break; | |
c2c63a49 JR |
4599 | case 0x8000000A: |
4600 | entry->eax = 1; /* SVM revision 1 */ | |
4601 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
4602 | ASID emulation to nested SVM */ | |
4603 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
4604 | entry->edx = 0; /* Per default do not support any |
4605 | additional features */ | |
4606 | ||
4607 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 4608 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 4609 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 4610 | |
3d4aeaad JR |
4611 | /* Support NPT for the guest if enabled */ |
4612 | if (npt_enabled) | |
4613 | entry->edx |= SVM_FEATURE_NPT; | |
4614 | ||
c2c63a49 JR |
4615 | break; |
4616 | } | |
d4330ef2 JR |
4617 | } |
4618 | ||
17cc3935 | 4619 | static int svm_get_lpage_level(void) |
344f414f | 4620 | { |
17cc3935 | 4621 | return PT_PDPE_LEVEL; |
344f414f JR |
4622 | } |
4623 | ||
4e47c7a6 SY |
4624 | static bool svm_rdtscp_supported(void) |
4625 | { | |
46896c73 | 4626 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
4627 | } |
4628 | ||
ad756a16 MJ |
4629 | static bool svm_invpcid_supported(void) |
4630 | { | |
4631 | return false; | |
4632 | } | |
4633 | ||
93c4adc7 PB |
4634 | static bool svm_mpx_supported(void) |
4635 | { | |
4636 | return false; | |
4637 | } | |
4638 | ||
55412b2e WL |
4639 | static bool svm_xsaves_supported(void) |
4640 | { | |
4641 | return false; | |
4642 | } | |
4643 | ||
f5f48ee1 SY |
4644 | static bool svm_has_wbinvd_exit(void) |
4645 | { | |
4646 | return true; | |
4647 | } | |
4648 | ||
02daab21 AK |
4649 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
4650 | { | |
4651 | struct vcpu_svm *svm = to_svm(vcpu); | |
4652 | ||
18c918c5 | 4653 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 4654 | update_cr0_intercept(svm); |
02daab21 AK |
4655 | } |
4656 | ||
8061252e | 4657 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4658 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 4659 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4660 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 4661 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 4662 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 4663 | |
09941fbb | 4664 | static const struct __x86_intercept { |
cfec82cb JR |
4665 | u32 exit_code; |
4666 | enum x86_intercept_stage stage; | |
cfec82cb JR |
4667 | } x86_intercept_map[] = { |
4668 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
4669 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4670 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4671 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4672 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
4673 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
4674 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
4675 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
4676 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
4677 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
4678 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
4679 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
4680 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
4681 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
4682 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
4683 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
4684 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
4685 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
4686 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
4687 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
4688 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
4689 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
4690 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
4691 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
4692 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
4693 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
4694 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
4695 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
4696 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
4697 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
4698 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
4699 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
4700 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
4701 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
4702 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
4703 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
4704 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
4705 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
4706 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
4707 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
4708 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
4709 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
4710 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
4711 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
4712 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
4713 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
4714 | }; |
4715 | ||
8061252e | 4716 | #undef PRE_EX |
cfec82cb | 4717 | #undef POST_EX |
d7eb8203 | 4718 | #undef POST_MEM |
cfec82cb | 4719 | |
8a76d7f2 JR |
4720 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
4721 | struct x86_instruction_info *info, | |
4722 | enum x86_intercept_stage stage) | |
4723 | { | |
cfec82cb JR |
4724 | struct vcpu_svm *svm = to_svm(vcpu); |
4725 | int vmexit, ret = X86EMUL_CONTINUE; | |
4726 | struct __x86_intercept icpt_info; | |
4727 | struct vmcb *vmcb = svm->vmcb; | |
4728 | ||
4729 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
4730 | goto out; | |
4731 | ||
4732 | icpt_info = x86_intercept_map[info->intercept]; | |
4733 | ||
40e19b51 | 4734 | if (stage != icpt_info.stage) |
cfec82cb JR |
4735 | goto out; |
4736 | ||
4737 | switch (icpt_info.exit_code) { | |
4738 | case SVM_EXIT_READ_CR0: | |
4739 | if (info->intercept == x86_intercept_cr_read) | |
4740 | icpt_info.exit_code += info->modrm_reg; | |
4741 | break; | |
4742 | case SVM_EXIT_WRITE_CR0: { | |
4743 | unsigned long cr0, val; | |
4744 | u64 intercept; | |
4745 | ||
4746 | if (info->intercept == x86_intercept_cr_write) | |
4747 | icpt_info.exit_code += info->modrm_reg; | |
4748 | ||
62baf44c JK |
4749 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
4750 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
4751 | break; |
4752 | ||
4753 | intercept = svm->nested.intercept; | |
4754 | ||
4755 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
4756 | break; | |
4757 | ||
4758 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4759 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4760 | ||
4761 | if (info->intercept == x86_intercept_lmsw) { | |
4762 | cr0 &= 0xfUL; | |
4763 | val &= 0xfUL; | |
4764 | /* lmsw can't clear PE - catch this here */ | |
4765 | if (cr0 & X86_CR0_PE) | |
4766 | val |= X86_CR0_PE; | |
4767 | } | |
4768 | ||
4769 | if (cr0 ^ val) | |
4770 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4771 | ||
4772 | break; | |
4773 | } | |
3b88e41a JR |
4774 | case SVM_EXIT_READ_DR0: |
4775 | case SVM_EXIT_WRITE_DR0: | |
4776 | icpt_info.exit_code += info->modrm_reg; | |
4777 | break; | |
8061252e JR |
4778 | case SVM_EXIT_MSR: |
4779 | if (info->intercept == x86_intercept_wrmsr) | |
4780 | vmcb->control.exit_info_1 = 1; | |
4781 | else | |
4782 | vmcb->control.exit_info_1 = 0; | |
4783 | break; | |
bf608f88 JR |
4784 | case SVM_EXIT_PAUSE: |
4785 | /* | |
4786 | * We get this for NOP only, but pause | |
4787 | * is rep not, check this here | |
4788 | */ | |
4789 | if (info->rep_prefix != REPE_PREFIX) | |
4790 | goto out; | |
f6511935 JR |
4791 | case SVM_EXIT_IOIO: { |
4792 | u64 exit_info; | |
4793 | u32 bytes; | |
4794 | ||
f6511935 JR |
4795 | if (info->intercept == x86_intercept_in || |
4796 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
4797 | exit_info = ((info->src_val & 0xffff) << 16) | |
4798 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 4799 | bytes = info->dst_bytes; |
6493f157 | 4800 | } else { |
6cbc5f5a | 4801 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 4802 | bytes = info->src_bytes; |
f6511935 JR |
4803 | } |
4804 | ||
4805 | if (info->intercept == x86_intercept_outs || | |
4806 | info->intercept == x86_intercept_ins) | |
4807 | exit_info |= SVM_IOIO_STR_MASK; | |
4808 | ||
4809 | if (info->rep_prefix) | |
4810 | exit_info |= SVM_IOIO_REP_MASK; | |
4811 | ||
4812 | bytes = min(bytes, 4u); | |
4813 | ||
4814 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4815 | ||
4816 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4817 | ||
4818 | vmcb->control.exit_info_1 = exit_info; | |
4819 | vmcb->control.exit_info_2 = info->next_rip; | |
4820 | ||
4821 | break; | |
4822 | } | |
cfec82cb JR |
4823 | default: |
4824 | break; | |
4825 | } | |
4826 | ||
f104765b BD |
4827 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
4828 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
4829 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
4830 | vmcb->control.exit_code = icpt_info.exit_code; |
4831 | vmexit = nested_svm_exit_handled(svm); | |
4832 | ||
4833 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4834 | : X86EMUL_CONTINUE; | |
4835 | ||
4836 | out: | |
4837 | return ret; | |
8a76d7f2 JR |
4838 | } |
4839 | ||
a547c6db YZ |
4840 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
4841 | { | |
4842 | local_irq_enable(); | |
4843 | } | |
4844 | ||
ae97a3b8 RK |
4845 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
4846 | { | |
4847 | } | |
4848 | ||
be8ca170 SS |
4849 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu) |
4850 | { | |
4851 | if (avic_handle_apic_id_update(vcpu) != 0) | |
4852 | return; | |
4853 | if (avic_handle_dfr_update(vcpu) != 0) | |
4854 | return; | |
4855 | avic_handle_ldr_update(vcpu); | |
4856 | } | |
4857 | ||
cbdd1bea | 4858 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4859 | .cpu_has_kvm_support = has_svm, |
4860 | .disabled_by_bios = is_disabled, | |
4861 | .hardware_setup = svm_hardware_setup, | |
4862 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4863 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4864 | .hardware_enable = svm_hardware_enable, |
4865 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4866 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6d396b55 | 4867 | .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase, |
6aa8b732 AK |
4868 | |
4869 | .vcpu_create = svm_create_vcpu, | |
4870 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4871 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4872 | |
44a95dae SS |
4873 | .vm_init = avic_vm_init, |
4874 | .vm_destroy = avic_vm_destroy, | |
4875 | ||
04d2cc77 | 4876 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4877 | .vcpu_load = svm_vcpu_load, |
4878 | .vcpu_put = svm_vcpu_put, | |
4879 | ||
a96036b8 | 4880 | .update_bp_intercept = update_bp_intercept, |
6aa8b732 AK |
4881 | .get_msr = svm_get_msr, |
4882 | .set_msr = svm_set_msr, | |
4883 | .get_segment_base = svm_get_segment_base, | |
4884 | .get_segment = svm_get_segment, | |
4885 | .set_segment = svm_set_segment, | |
2e4d2653 | 4886 | .get_cpl = svm_get_cpl, |
1747fb71 | 4887 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4888 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4889 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4890 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4891 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4892 | .set_cr3 = svm_set_cr3, |
4893 | .set_cr4 = svm_set_cr4, | |
4894 | .set_efer = svm_set_efer, | |
4895 | .get_idt = svm_get_idt, | |
4896 | .set_idt = svm_set_idt, | |
4897 | .get_gdt = svm_get_gdt, | |
4898 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
4899 | .get_dr6 = svm_get_dr6, |
4900 | .set_dr6 = svm_set_dr6, | |
020df079 | 4901 | .set_dr7 = svm_set_dr7, |
facb0139 | 4902 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 4903 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4904 | .get_rflags = svm_get_rflags, |
4905 | .set_rflags = svm_set_rflags, | |
be94f6b7 HH |
4906 | |
4907 | .get_pkru = svm_get_pkru, | |
4908 | ||
0fdd74f7 | 4909 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4910 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4911 | |
6aa8b732 | 4912 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4913 | |
6aa8b732 | 4914 | .run = svm_vcpu_run, |
04d2cc77 | 4915 | .handle_exit = handle_exit, |
6aa8b732 | 4916 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4917 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4918 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4919 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4920 | .set_irq = svm_set_irq, |
95ba8273 | 4921 | .set_nmi = svm_inject_nmi, |
298101da | 4922 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4923 | .cancel_injection = svm_cancel_injection, |
78646121 | 4924 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4925 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4926 | .get_nmi_mask = svm_get_nmi_mask, |
4927 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4928 | .enable_nmi_window = enable_nmi_window, |
4929 | .enable_irq_window = enable_irq_window, | |
4930 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 4931 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
d62caabb AS |
4932 | .get_enable_apicv = svm_get_enable_apicv, |
4933 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, | |
c7c9c56c | 4934 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
a20ed54d | 4935 | .sync_pir_to_irr = svm_sync_pir_to_irr, |
44a95dae SS |
4936 | .hwapic_irr_update = svm_hwapic_irr_update, |
4937 | .hwapic_isr_update = svm_hwapic_isr_update, | |
be8ca170 | 4938 | .apicv_post_state_restore = avic_post_state_restore, |
cbc94022 IE |
4939 | |
4940 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4941 | .get_tdp_level = get_npt_level, |
4b12f0de | 4942 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4943 | |
586f9607 | 4944 | .get_exit_info = svm_get_exit_info, |
586f9607 | 4945 | |
17cc3935 | 4946 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4947 | |
4948 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4949 | |
4950 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 4951 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 4952 | .mpx_supported = svm_mpx_supported, |
55412b2e | 4953 | .xsaves_supported = svm_xsaves_supported, |
d4330ef2 JR |
4954 | |
4955 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4956 | |
4957 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 4958 | |
ba904635 | 4959 | .read_tsc_offset = svm_read_tsc_offset, |
99e3e30a | 4960 | .write_tsc_offset = svm_write_tsc_offset, |
58ea6767 | 4961 | .adjust_tsc_offset_guest = svm_adjust_tsc_offset_guest, |
d5c1785d | 4962 | .read_l1_tsc = svm_read_l1_tsc, |
1c97f0a0 JR |
4963 | |
4964 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4965 | |
4966 | .check_intercept = svm_check_intercept, | |
a547c6db | 4967 | .handle_external_intr = svm_handle_external_intr, |
ae97a3b8 RK |
4968 | |
4969 | .sched_in = svm_sched_in, | |
25462f7f WH |
4970 | |
4971 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 4972 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
6aa8b732 AK |
4973 | }; |
4974 | ||
4975 | static int __init svm_init(void) | |
4976 | { | |
cb498ea2 | 4977 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4978 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4979 | } |
4980 | ||
4981 | static void __exit svm_exit(void) | |
4982 | { | |
cb498ea2 | 4983 | kvm_exit(); |
6aa8b732 AK |
4984 | } |
4985 | ||
4986 | module_init(svm_init) | |
4987 | module_exit(svm_exit) |