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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
85f455f7 | 18 | #include "irq.h" |
1d737c8a | 19 | #include "mmu.h" |
5fdbf976 | 20 | #include "kvm_cache_regs.h" |
fe4c7b19 | 21 | #include "x86.h" |
e495606d | 22 | |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/vmalloc.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
229456fc | 28 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
6aa8b732 | 30 | |
e495606d | 31 | #include <asm/desc.h> |
6aa8b732 | 32 | |
63d1142f | 33 | #include <asm/virtext.h> |
229456fc | 34 | #include "trace.h" |
63d1142f | 35 | |
4ecac3fd AK |
36 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
37 | ||
6aa8b732 AK |
38 | MODULE_AUTHOR("Qumranet"); |
39 | MODULE_LICENSE("GPL"); | |
40 | ||
41 | #define IOPM_ALLOC_ORDER 2 | |
42 | #define MSRPM_ALLOC_ORDER 1 | |
43 | ||
6aa8b732 AK |
44 | #define SEG_TYPE_LDT 2 |
45 | #define SEG_TYPE_BUSY_TSS16 3 | |
46 | ||
80b7706e JR |
47 | #define SVM_FEATURE_NPT (1 << 0) |
48 | #define SVM_FEATURE_LBRV (1 << 1) | |
94c935a1 | 49 | #define SVM_FEATURE_SVML (1 << 2) |
565d0998 | 50 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 51 | |
410e4d57 JR |
52 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
53 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
54 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
55 | ||
24e09cbf JR |
56 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
57 | ||
6c8166a7 AK |
58 | static const u32 host_save_user_msrs[] = { |
59 | #ifdef CONFIG_X86_64 | |
60 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
61 | MSR_FS_BASE, | |
62 | #endif | |
63 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
64 | }; | |
65 | ||
66 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
67 | ||
68 | struct kvm_vcpu; | |
69 | ||
e6aa9abd JR |
70 | struct nested_state { |
71 | struct vmcb *hsave; | |
72 | u64 hsave_msr; | |
73 | u64 vmcb; | |
74 | ||
75 | /* These are the merged vectors */ | |
76 | u32 *msrpm; | |
77 | ||
78 | /* gpa pointers to the real vectors */ | |
79 | u64 vmcb_msrpm; | |
aad42c64 | 80 | |
cd3ff653 JR |
81 | /* A VMEXIT is required but not yet emulated */ |
82 | bool exit_required; | |
83 | ||
aad42c64 JR |
84 | /* cache for intercepts of the guest */ |
85 | u16 intercept_cr_read; | |
86 | u16 intercept_cr_write; | |
87 | u16 intercept_dr_read; | |
88 | u16 intercept_dr_write; | |
89 | u32 intercept_exceptions; | |
90 | u64 intercept; | |
91 | ||
e6aa9abd JR |
92 | }; |
93 | ||
6c8166a7 AK |
94 | struct vcpu_svm { |
95 | struct kvm_vcpu vcpu; | |
96 | struct vmcb *vmcb; | |
97 | unsigned long vmcb_pa; | |
98 | struct svm_cpu_data *svm_data; | |
99 | uint64_t asid_generation; | |
100 | uint64_t sysenter_esp; | |
101 | uint64_t sysenter_eip; | |
102 | ||
103 | u64 next_rip; | |
104 | ||
105 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
106 | u64 host_gs_base; | |
6c8166a7 AK |
107 | |
108 | u32 *msrpm; | |
6c8166a7 | 109 | |
e6aa9abd | 110 | struct nested_state nested; |
6be7d306 JK |
111 | |
112 | bool nmi_singlestep; | |
6c8166a7 AK |
113 | }; |
114 | ||
709ddebf JR |
115 | /* enable NPT for AMD64 and X86 with PAE */ |
116 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
117 | static bool npt_enabled = true; | |
118 | #else | |
e3da3acd | 119 | static bool npt_enabled = false; |
709ddebf | 120 | #endif |
6c7dac72 JR |
121 | static int npt = 1; |
122 | ||
123 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 124 | |
4b6e4dca | 125 | static int nested = 1; |
236de055 AG |
126 | module_param(nested, int, S_IRUGO); |
127 | ||
44874f84 | 128 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 129 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 130 | |
410e4d57 | 131 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
cf74a78b | 132 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
133 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
134 | bool has_error_code, u32 error_code); | |
135 | ||
a2fa3e9f GH |
136 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
137 | { | |
fb3f0f51 | 138 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
139 | } |
140 | ||
3d6368ef AG |
141 | static inline bool is_nested(struct vcpu_svm *svm) |
142 | { | |
e6aa9abd | 143 | return svm->nested.vmcb; |
3d6368ef AG |
144 | } |
145 | ||
2af9194d JR |
146 | static inline void enable_gif(struct vcpu_svm *svm) |
147 | { | |
148 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
149 | } | |
150 | ||
151 | static inline void disable_gif(struct vcpu_svm *svm) | |
152 | { | |
153 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
154 | } | |
155 | ||
156 | static inline bool gif_set(struct vcpu_svm *svm) | |
157 | { | |
158 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
159 | } | |
160 | ||
4866d5e3 | 161 | static unsigned long iopm_base; |
6aa8b732 AK |
162 | |
163 | struct kvm_ldttss_desc { | |
164 | u16 limit0; | |
165 | u16 base0; | |
166 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
167 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
168 | u32 base3; | |
169 | u32 zero1; | |
170 | } __attribute__((packed)); | |
171 | ||
172 | struct svm_cpu_data { | |
173 | int cpu; | |
174 | ||
5008fdf5 AK |
175 | u64 asid_generation; |
176 | u32 max_asid; | |
177 | u32 next_asid; | |
6aa8b732 AK |
178 | struct kvm_ldttss_desc *tss_desc; |
179 | ||
180 | struct page *save_area; | |
181 | }; | |
182 | ||
183 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 184 | static uint32_t svm_features; |
6aa8b732 AK |
185 | |
186 | struct svm_init_data { | |
187 | int cpu; | |
188 | int r; | |
189 | }; | |
190 | ||
191 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
192 | ||
9d8f549d | 193 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
194 | #define MSRS_RANGE_SIZE 2048 |
195 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
196 | ||
197 | #define MAX_INST_SIZE 15 | |
198 | ||
80b7706e JR |
199 | static inline u32 svm_has(u32 feat) |
200 | { | |
201 | return svm_features & feat; | |
202 | } | |
203 | ||
6aa8b732 AK |
204 | static inline void clgi(void) |
205 | { | |
4ecac3fd | 206 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
207 | } |
208 | ||
209 | static inline void stgi(void) | |
210 | { | |
4ecac3fd | 211 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
212 | } |
213 | ||
214 | static inline void invlpga(unsigned long addr, u32 asid) | |
215 | { | |
4ecac3fd | 216 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
217 | } |
218 | ||
6aa8b732 AK |
219 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
220 | { | |
a2fa3e9f | 221 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
222 | } |
223 | ||
224 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
225 | { | |
226 | force_new_asid(vcpu); | |
227 | } | |
228 | ||
229 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
230 | { | |
709ddebf | 231 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 232 | efer &= ~EFER_LME; |
6aa8b732 | 233 | |
9962d032 | 234 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
f6801dff | 235 | vcpu->arch.efer = efer; |
6aa8b732 AK |
236 | } |
237 | ||
298101da AK |
238 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
239 | bool has_error_code, u32 error_code) | |
240 | { | |
241 | struct vcpu_svm *svm = to_svm(vcpu); | |
242 | ||
cf74a78b AG |
243 | /* If we are within a nested VM we'd better #VMEXIT and let the |
244 | guest handle the exception */ | |
245 | if (nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
246 | return; | |
247 | ||
298101da AK |
248 | svm->vmcb->control.event_inj = nr |
249 | | SVM_EVTINJ_VALID | |
250 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
251 | | SVM_EVTINJ_TYPE_EXEPT; | |
252 | svm->vmcb->control.event_inj_err = error_code; | |
253 | } | |
254 | ||
6aa8b732 AK |
255 | static int is_external_interrupt(u32 info) |
256 | { | |
257 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
258 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
259 | } | |
260 | ||
2809f5d2 GC |
261 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
262 | { | |
263 | struct vcpu_svm *svm = to_svm(vcpu); | |
264 | u32 ret = 0; | |
265 | ||
266 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
267 | ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS; | |
268 | return ret & mask; | |
269 | } | |
270 | ||
271 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
272 | { | |
273 | struct vcpu_svm *svm = to_svm(vcpu); | |
274 | ||
275 | if (mask == 0) | |
276 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
277 | else | |
278 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
279 | ||
280 | } | |
281 | ||
6aa8b732 AK |
282 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
283 | { | |
a2fa3e9f GH |
284 | struct vcpu_svm *svm = to_svm(vcpu); |
285 | ||
286 | if (!svm->next_rip) { | |
851ba692 | 287 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != |
f629cf84 GN |
288 | EMULATE_DONE) |
289 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
290 | return; |
291 | } | |
5fdbf976 MT |
292 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
293 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
294 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 295 | |
5fdbf976 | 296 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 297 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
298 | } |
299 | ||
300 | static int has_svm(void) | |
301 | { | |
63d1142f | 302 | const char *msg; |
6aa8b732 | 303 | |
63d1142f | 304 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 305 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
306 | return 0; |
307 | } | |
308 | ||
6aa8b732 AK |
309 | return 1; |
310 | } | |
311 | ||
312 | static void svm_hardware_disable(void *garbage) | |
313 | { | |
2c8dceeb | 314 | cpu_svm_disable(); |
6aa8b732 AK |
315 | } |
316 | ||
10474ae8 | 317 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
318 | { |
319 | ||
0fe1e009 | 320 | struct svm_cpu_data *sd; |
6aa8b732 | 321 | uint64_t efer; |
b792c344 | 322 | struct descriptor_table gdt_descr; |
6aa8b732 AK |
323 | struct desc_struct *gdt; |
324 | int me = raw_smp_processor_id(); | |
325 | ||
10474ae8 AG |
326 | rdmsrl(MSR_EFER, efer); |
327 | if (efer & EFER_SVME) | |
328 | return -EBUSY; | |
329 | ||
6aa8b732 | 330 | if (!has_svm()) { |
e6732a5a ZA |
331 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
332 | me); | |
10474ae8 | 333 | return -EINVAL; |
6aa8b732 | 334 | } |
0fe1e009 | 335 | sd = per_cpu(svm_data, me); |
6aa8b732 | 336 | |
0fe1e009 | 337 | if (!sd) { |
e6732a5a | 338 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 339 | me); |
10474ae8 | 340 | return -EINVAL; |
6aa8b732 AK |
341 | } |
342 | ||
0fe1e009 TH |
343 | sd->asid_generation = 1; |
344 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
345 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 346 | |
b792c344 AM |
347 | kvm_get_gdt(&gdt_descr); |
348 | gdt = (struct desc_struct *)gdt_descr.base; | |
0fe1e009 | 349 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 350 | |
9962d032 | 351 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 352 | |
d0316554 | 353 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 AG |
354 | |
355 | return 0; | |
6aa8b732 AK |
356 | } |
357 | ||
0da1db75 JR |
358 | static void svm_cpu_uninit(int cpu) |
359 | { | |
0fe1e009 | 360 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 361 | |
0fe1e009 | 362 | if (!sd) |
0da1db75 JR |
363 | return; |
364 | ||
365 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
366 | __free_page(sd->save_area); |
367 | kfree(sd); | |
0da1db75 JR |
368 | } |
369 | ||
6aa8b732 AK |
370 | static int svm_cpu_init(int cpu) |
371 | { | |
0fe1e009 | 372 | struct svm_cpu_data *sd; |
6aa8b732 AK |
373 | int r; |
374 | ||
0fe1e009 TH |
375 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
376 | if (!sd) | |
6aa8b732 | 377 | return -ENOMEM; |
0fe1e009 TH |
378 | sd->cpu = cpu; |
379 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 380 | r = -ENOMEM; |
0fe1e009 | 381 | if (!sd->save_area) |
6aa8b732 AK |
382 | goto err_1; |
383 | ||
0fe1e009 | 384 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
385 | |
386 | return 0; | |
387 | ||
388 | err_1: | |
0fe1e009 | 389 | kfree(sd); |
6aa8b732 AK |
390 | return r; |
391 | ||
392 | } | |
393 | ||
bfc733a7 RR |
394 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
395 | int read, int write) | |
6aa8b732 AK |
396 | { |
397 | int i; | |
398 | ||
399 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
400 | if (msr >= msrpm_ranges[i] && | |
401 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
402 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
403 | msrpm_ranges[i]) * 2; | |
404 | ||
405 | u32 *base = msrpm + (msr_offset / 32); | |
406 | u32 msr_shift = msr_offset % 32; | |
407 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
408 | *base = (*base & ~(0x3 << msr_shift)) | | |
409 | (mask << msr_shift); | |
bfc733a7 | 410 | return; |
6aa8b732 AK |
411 | } |
412 | } | |
bfc733a7 | 413 | BUG(); |
6aa8b732 AK |
414 | } |
415 | ||
f65c229c JR |
416 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
417 | { | |
418 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
419 | ||
420 | #ifdef CONFIG_X86_64 | |
421 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
422 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
423 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
424 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
425 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
426 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
427 | #endif | |
428 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
429 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
f65c229c JR |
430 | } |
431 | ||
24e09cbf JR |
432 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
433 | { | |
434 | u32 *msrpm = svm->msrpm; | |
435 | ||
436 | svm->vmcb->control.lbr_ctl = 1; | |
437 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
438 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
439 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
440 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
441 | } | |
442 | ||
443 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
444 | { | |
445 | u32 *msrpm = svm->msrpm; | |
446 | ||
447 | svm->vmcb->control.lbr_ctl = 0; | |
448 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
449 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
450 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
451 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
452 | } | |
453 | ||
6aa8b732 AK |
454 | static __init int svm_hardware_setup(void) |
455 | { | |
456 | int cpu; | |
457 | struct page *iopm_pages; | |
f65c229c | 458 | void *iopm_va; |
6aa8b732 AK |
459 | int r; |
460 | ||
6aa8b732 AK |
461 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
462 | ||
463 | if (!iopm_pages) | |
464 | return -ENOMEM; | |
c8681339 AL |
465 | |
466 | iopm_va = page_address(iopm_pages); | |
467 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
468 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
469 | ||
50a37eb4 JR |
470 | if (boot_cpu_has(X86_FEATURE_NX)) |
471 | kvm_enable_efer_bits(EFER_NX); | |
472 | ||
1b2fd70c AG |
473 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
474 | kvm_enable_efer_bits(EFER_FFXSR); | |
475 | ||
236de055 AG |
476 | if (nested) { |
477 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
478 | kvm_enable_efer_bits(EFER_SVME); | |
479 | } | |
480 | ||
3230bb47 | 481 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
482 | r = svm_cpu_init(cpu); |
483 | if (r) | |
f65c229c | 484 | goto err; |
6aa8b732 | 485 | } |
33bd6a0b JR |
486 | |
487 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
488 | ||
e3da3acd JR |
489 | if (!svm_has(SVM_FEATURE_NPT)) |
490 | npt_enabled = false; | |
491 | ||
6c7dac72 JR |
492 | if (npt_enabled && !npt) { |
493 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
494 | npt_enabled = false; | |
495 | } | |
496 | ||
18552672 | 497 | if (npt_enabled) { |
e3da3acd | 498 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 499 | kvm_enable_tdp(); |
5f4cb662 JR |
500 | } else |
501 | kvm_disable_tdp(); | |
e3da3acd | 502 | |
6aa8b732 AK |
503 | return 0; |
504 | ||
f65c229c | 505 | err: |
6aa8b732 AK |
506 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
507 | iopm_base = 0; | |
508 | return r; | |
509 | } | |
510 | ||
511 | static __exit void svm_hardware_unsetup(void) | |
512 | { | |
0da1db75 JR |
513 | int cpu; |
514 | ||
3230bb47 | 515 | for_each_possible_cpu(cpu) |
0da1db75 JR |
516 | svm_cpu_uninit(cpu); |
517 | ||
6aa8b732 | 518 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 519 | iopm_base = 0; |
6aa8b732 AK |
520 | } |
521 | ||
522 | static void init_seg(struct vmcb_seg *seg) | |
523 | { | |
524 | seg->selector = 0; | |
525 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
526 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
527 | seg->limit = 0xffff; | |
528 | seg->base = 0; | |
529 | } | |
530 | ||
531 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
532 | { | |
533 | seg->selector = 0; | |
534 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
535 | seg->limit = 0xffff; | |
536 | seg->base = 0; | |
537 | } | |
538 | ||
e6101a96 | 539 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 540 | { |
e6101a96 JR |
541 | struct vmcb_control_area *control = &svm->vmcb->control; |
542 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 543 | |
bff78274 AK |
544 | svm->vcpu.fpu_active = 1; |
545 | ||
6aa8b732 AK |
546 | control->intercept_cr_read = INTERCEPT_CR0_MASK | |
547 | INTERCEPT_CR3_MASK | | |
649d6864 | 548 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
549 | |
550 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
551 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
552 | INTERCEPT_CR4_MASK | |
553 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
554 | |
555 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
556 | INTERCEPT_DR1_MASK | | |
557 | INTERCEPT_DR2_MASK | | |
727f5a23 JK |
558 | INTERCEPT_DR3_MASK | |
559 | INTERCEPT_DR4_MASK | | |
560 | INTERCEPT_DR5_MASK | | |
561 | INTERCEPT_DR6_MASK | | |
562 | INTERCEPT_DR7_MASK; | |
6aa8b732 AK |
563 | |
564 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
565 | INTERCEPT_DR1_MASK | | |
566 | INTERCEPT_DR2_MASK | | |
567 | INTERCEPT_DR3_MASK | | |
727f5a23 | 568 | INTERCEPT_DR4_MASK | |
6aa8b732 | 569 | INTERCEPT_DR5_MASK | |
727f5a23 | 570 | INTERCEPT_DR6_MASK | |
6aa8b732 AK |
571 | INTERCEPT_DR7_MASK; |
572 | ||
7aa81cc0 | 573 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
574 | (1 << UD_VECTOR) | |
575 | (1 << MC_VECTOR); | |
6aa8b732 AK |
576 | |
577 | ||
578 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
579 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 580 | (1ULL << INTERCEPT_SMI) | |
d225157b | 581 | (1ULL << INTERCEPT_SELECTIVE_CR0) | |
6aa8b732 | 582 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 583 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 584 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 585 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
586 | (1ULL << INTERCEPT_INVLPGA) | |
587 | (1ULL << INTERCEPT_IOIO_PROT) | | |
588 | (1ULL << INTERCEPT_MSR_PROT) | | |
589 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 590 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
591 | (1ULL << INTERCEPT_VMRUN) | |
592 | (1ULL << INTERCEPT_VMMCALL) | | |
593 | (1ULL << INTERCEPT_VMLOAD) | | |
594 | (1ULL << INTERCEPT_VMSAVE) | | |
595 | (1ULL << INTERCEPT_STGI) | | |
596 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 597 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 598 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
599 | (1ULL << INTERCEPT_MONITOR) | |
600 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
601 | |
602 | control->iopm_base_pa = iopm_base; | |
f65c229c | 603 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 604 | control->tsc_offset = 0; |
6aa8b732 AK |
605 | control->int_ctl = V_INTR_MASKING_MASK; |
606 | ||
607 | init_seg(&save->es); | |
608 | init_seg(&save->ss); | |
609 | init_seg(&save->ds); | |
610 | init_seg(&save->fs); | |
611 | init_seg(&save->gs); | |
612 | ||
613 | save->cs.selector = 0xf000; | |
614 | /* Executable/Readable Code Segment */ | |
615 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
616 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
617 | save->cs.limit = 0xffff; | |
d92899a0 AK |
618 | /* |
619 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
620 | * be consistent with it. | |
621 | * | |
622 | * Replace when we have real mode working for vmx. | |
623 | */ | |
624 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
625 | |
626 | save->gdtr.limit = 0xffff; | |
627 | save->idtr.limit = 0xffff; | |
628 | ||
629 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
630 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
631 | ||
9962d032 | 632 | save->efer = EFER_SVME; |
d77c26fc | 633 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
634 | save->dr7 = 0x400; |
635 | save->rflags = 2; | |
636 | save->rip = 0x0000fff0; | |
5fdbf976 | 637 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 638 | |
18fa000a EH |
639 | /* This is the guest-visible cr0 value. |
640 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. | |
6aa8b732 | 641 | */ |
18fa000a EH |
642 | svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
643 | kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0); | |
644 | ||
66aee91a | 645 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 646 | /* rdx = ?? */ |
709ddebf JR |
647 | |
648 | if (npt_enabled) { | |
649 | /* Setup VMCB for Nested Paging */ | |
650 | control->nested_ctl = 1; | |
a7052897 MT |
651 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
652 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf | 653 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
888f9f3e AK |
654 | control->intercept_cr_read &= ~INTERCEPT_CR3_MASK; |
655 | control->intercept_cr_write &= ~INTERCEPT_CR3_MASK; | |
709ddebf | 656 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
657 | save->cr3 = 0; |
658 | save->cr4 = 0; | |
659 | } | |
a79d2f18 | 660 | force_new_asid(&svm->vcpu); |
1371d904 | 661 | |
e6aa9abd | 662 | svm->nested.vmcb = 0; |
2af9194d JR |
663 | svm->vcpu.arch.hflags = 0; |
664 | ||
565d0998 ML |
665 | if (svm_has(SVM_FEATURE_PAUSE_FILTER)) { |
666 | control->pause_filter_count = 3000; | |
667 | control->intercept |= (1ULL << INTERCEPT_PAUSE); | |
668 | } | |
669 | ||
2af9194d | 670 | enable_gif(svm); |
6aa8b732 AK |
671 | } |
672 | ||
e00c8cf2 | 673 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
674 | { |
675 | struct vcpu_svm *svm = to_svm(vcpu); | |
676 | ||
e6101a96 | 677 | init_vmcb(svm); |
70433389 | 678 | |
c5af89b6 | 679 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 680 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
681 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
682 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 683 | } |
5fdbf976 MT |
684 | vcpu->arch.regs_avail = ~0; |
685 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
686 | |
687 | return 0; | |
04d2cc77 AK |
688 | } |
689 | ||
fb3f0f51 | 690 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 691 | { |
a2fa3e9f | 692 | struct vcpu_svm *svm; |
6aa8b732 | 693 | struct page *page; |
f65c229c | 694 | struct page *msrpm_pages; |
b286d5d8 | 695 | struct page *hsave_page; |
3d6368ef | 696 | struct page *nested_msrpm_pages; |
fb3f0f51 | 697 | int err; |
6aa8b732 | 698 | |
c16f862d | 699 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
700 | if (!svm) { |
701 | err = -ENOMEM; | |
702 | goto out; | |
703 | } | |
704 | ||
705 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
706 | if (err) | |
707 | goto free_svm; | |
708 | ||
6aa8b732 | 709 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
710 | if (!page) { |
711 | err = -ENOMEM; | |
712 | goto uninit; | |
713 | } | |
6aa8b732 | 714 | |
f65c229c JR |
715 | err = -ENOMEM; |
716 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
717 | if (!msrpm_pages) | |
718 | goto uninit; | |
3d6368ef AG |
719 | |
720 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
721 | if (!nested_msrpm_pages) | |
722 | goto uninit; | |
723 | ||
f65c229c JR |
724 | svm->msrpm = page_address(msrpm_pages); |
725 | svm_vcpu_init_msrpm(svm->msrpm); | |
726 | ||
b286d5d8 AG |
727 | hsave_page = alloc_page(GFP_KERNEL); |
728 | if (!hsave_page) | |
729 | goto uninit; | |
e6aa9abd | 730 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 731 | |
e6aa9abd | 732 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
3d6368ef | 733 | |
a2fa3e9f GH |
734 | svm->vmcb = page_address(page); |
735 | clear_page(svm->vmcb); | |
736 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
737 | svm->asid_generation = 0; | |
e6101a96 | 738 | init_vmcb(svm); |
a2fa3e9f | 739 | |
fb3f0f51 | 740 | fx_init(&svm->vcpu); |
ad312c7c | 741 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 742 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 743 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 744 | |
fb3f0f51 | 745 | return &svm->vcpu; |
36241b8c | 746 | |
fb3f0f51 RR |
747 | uninit: |
748 | kvm_vcpu_uninit(&svm->vcpu); | |
749 | free_svm: | |
a4770347 | 750 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
751 | out: |
752 | return ERR_PTR(err); | |
6aa8b732 AK |
753 | } |
754 | ||
755 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
756 | { | |
a2fa3e9f GH |
757 | struct vcpu_svm *svm = to_svm(vcpu); |
758 | ||
fb3f0f51 | 759 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 760 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
761 | __free_page(virt_to_page(svm->nested.hsave)); |
762 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 763 | kvm_vcpu_uninit(vcpu); |
a4770347 | 764 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
765 | } |
766 | ||
15ad7146 | 767 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 768 | { |
a2fa3e9f | 769 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 770 | int i; |
0cc5064d | 771 | |
0cc5064d | 772 | if (unlikely(cpu != vcpu->cpu)) { |
e935d48e | 773 | u64 delta; |
0cc5064d | 774 | |
953899b6 JR |
775 | if (check_tsc_unstable()) { |
776 | /* | |
777 | * Make sure that the guest sees a monotonically | |
778 | * increasing TSC. | |
779 | */ | |
780 | delta = vcpu->arch.host_tsc - native_read_tsc(); | |
781 | svm->vmcb->control.tsc_offset += delta; | |
782 | if (is_nested(svm)) | |
783 | svm->nested.hsave->control.tsc_offset += delta; | |
784 | } | |
0cc5064d | 785 | vcpu->cpu = cpu; |
2f599714 | 786 | kvm_migrate_timers(vcpu); |
4b656b12 | 787 | svm->asid_generation = 0; |
0cc5064d | 788 | } |
94dfbdb3 AL |
789 | |
790 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 791 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
792 | } |
793 | ||
794 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
795 | { | |
a2fa3e9f | 796 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
797 | int i; |
798 | ||
e1beb1d3 | 799 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 800 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 801 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 802 | |
e935d48e | 803 | vcpu->arch.host_tsc = native_read_tsc(); |
6aa8b732 AK |
804 | } |
805 | ||
6aa8b732 AK |
806 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
807 | { | |
a2fa3e9f | 808 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
809 | } |
810 | ||
811 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
812 | { | |
a2fa3e9f | 813 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
814 | } |
815 | ||
6de4f3ad AK |
816 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
817 | { | |
818 | switch (reg) { | |
819 | case VCPU_EXREG_PDPTR: | |
820 | BUG_ON(!npt_enabled); | |
821 | load_pdptrs(vcpu, vcpu->arch.cr3); | |
822 | break; | |
823 | default: | |
824 | BUG(); | |
825 | } | |
826 | } | |
827 | ||
f0b85051 AG |
828 | static void svm_set_vintr(struct vcpu_svm *svm) |
829 | { | |
830 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
831 | } | |
832 | ||
833 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
834 | { | |
835 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
836 | } | |
837 | ||
6aa8b732 AK |
838 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
839 | { | |
a2fa3e9f | 840 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
841 | |
842 | switch (seg) { | |
843 | case VCPU_SREG_CS: return &save->cs; | |
844 | case VCPU_SREG_DS: return &save->ds; | |
845 | case VCPU_SREG_ES: return &save->es; | |
846 | case VCPU_SREG_FS: return &save->fs; | |
847 | case VCPU_SREG_GS: return &save->gs; | |
848 | case VCPU_SREG_SS: return &save->ss; | |
849 | case VCPU_SREG_TR: return &save->tr; | |
850 | case VCPU_SREG_LDTR: return &save->ldtr; | |
851 | } | |
852 | BUG(); | |
8b6d44c7 | 853 | return NULL; |
6aa8b732 AK |
854 | } |
855 | ||
856 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
857 | { | |
858 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
859 | ||
860 | return s->base; | |
861 | } | |
862 | ||
863 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
864 | struct kvm_segment *var, int seg) | |
865 | { | |
866 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
867 | ||
868 | var->base = s->base; | |
869 | var->limit = s->limit; | |
870 | var->selector = s->selector; | |
871 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
872 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
873 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
874 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
875 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
876 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
877 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
878 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 879 | |
19bca6ab AP |
880 | /* AMD's VMCB does not have an explicit unusable field, so emulate it |
881 | * for cross vendor migration purposes by "not present" | |
882 | */ | |
883 | var->unusable = !var->present || (var->type == 0); | |
884 | ||
1fbdc7a5 AP |
885 | switch (seg) { |
886 | case VCPU_SREG_CS: | |
887 | /* | |
888 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
889 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
890 | * Intel's VMENTRY has a check on the 'G' bit. | |
891 | */ | |
25022acc | 892 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
893 | break; |
894 | case VCPU_SREG_TR: | |
895 | /* | |
896 | * Work around a bug where the busy flag in the tr selector | |
897 | * isn't exposed | |
898 | */ | |
c0d09828 | 899 | var->type |= 0x2; |
1fbdc7a5 AP |
900 | break; |
901 | case VCPU_SREG_DS: | |
902 | case VCPU_SREG_ES: | |
903 | case VCPU_SREG_FS: | |
904 | case VCPU_SREG_GS: | |
905 | /* | |
906 | * The accessed bit must always be set in the segment | |
907 | * descriptor cache, although it can be cleared in the | |
908 | * descriptor, the cached bit always remains at 1. Since | |
909 | * Intel has a check on this, set it here to support | |
910 | * cross-vendor migration. | |
911 | */ | |
912 | if (!var->unusable) | |
913 | var->type |= 0x1; | |
914 | break; | |
b586eb02 AP |
915 | case VCPU_SREG_SS: |
916 | /* On AMD CPUs sometimes the DB bit in the segment | |
917 | * descriptor is left as 1, although the whole segment has | |
918 | * been made unusable. Clear it here to pass an Intel VMX | |
919 | * entry check when cross vendor migrating. | |
920 | */ | |
921 | if (var->unusable) | |
922 | var->db = 0; | |
923 | break; | |
1fbdc7a5 | 924 | } |
6aa8b732 AK |
925 | } |
926 | ||
2e4d2653 IE |
927 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
928 | { | |
929 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
930 | ||
931 | return save->cpl; | |
932 | } | |
933 | ||
6aa8b732 AK |
934 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
935 | { | |
a2fa3e9f GH |
936 | struct vcpu_svm *svm = to_svm(vcpu); |
937 | ||
938 | dt->limit = svm->vmcb->save.idtr.limit; | |
939 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
940 | } |
941 | ||
942 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
943 | { | |
a2fa3e9f GH |
944 | struct vcpu_svm *svm = to_svm(vcpu); |
945 | ||
946 | svm->vmcb->save.idtr.limit = dt->limit; | |
947 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
948 | } |
949 | ||
950 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
951 | { | |
a2fa3e9f GH |
952 | struct vcpu_svm *svm = to_svm(vcpu); |
953 | ||
954 | dt->limit = svm->vmcb->save.gdtr.limit; | |
955 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
956 | } |
957 | ||
958 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
959 | { | |
a2fa3e9f GH |
960 | struct vcpu_svm *svm = to_svm(vcpu); |
961 | ||
962 | svm->vmcb->save.gdtr.limit = dt->limit; | |
963 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
964 | } |
965 | ||
e8467fda AK |
966 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
967 | { | |
968 | } | |
969 | ||
25c4c276 | 970 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
971 | { |
972 | } | |
973 | ||
d225157b AK |
974 | static void update_cr0_intercept(struct vcpu_svm *svm) |
975 | { | |
976 | ulong gcr0 = svm->vcpu.arch.cr0; | |
977 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
978 | ||
979 | if (!svm->vcpu.fpu_active) | |
980 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
981 | else | |
982 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
983 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
984 | ||
985 | ||
986 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
987 | svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; | |
988 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; | |
989 | } else { | |
990 | svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK; | |
991 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK; | |
992 | } | |
993 | } | |
994 | ||
6aa8b732 AK |
995 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
996 | { | |
a2fa3e9f GH |
997 | struct vcpu_svm *svm = to_svm(vcpu); |
998 | ||
05b3e0c2 | 999 | #ifdef CONFIG_X86_64 |
f6801dff | 1000 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1001 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1002 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1003 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1004 | } |
1005 | ||
d77c26fc | 1006 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1007 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1008 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1009 | } |
1010 | } | |
1011 | #endif | |
ad312c7c | 1012 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1013 | |
1014 | if (!npt_enabled) | |
1015 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1016 | |
1017 | if (!vcpu->fpu_active) | |
334df50a | 1018 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1019 | /* |
1020 | * re-enable caching here because the QEMU bios | |
1021 | * does not do it - this results in some delay at | |
1022 | * reboot | |
1023 | */ | |
1024 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1025 | svm->vmcb->save.cr0 = cr0; |
d225157b | 1026 | update_cr0_intercept(svm); |
6aa8b732 AK |
1027 | } |
1028 | ||
1029 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1030 | { | |
6394b649 | 1031 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1032 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1033 | ||
1034 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1035 | force_new_asid(vcpu); | |
6394b649 | 1036 | |
ec077263 JR |
1037 | vcpu->arch.cr4 = cr4; |
1038 | if (!npt_enabled) | |
1039 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1040 | cr4 |= host_cr4_mce; |
ec077263 | 1041 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
1042 | } |
1043 | ||
1044 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1045 | struct kvm_segment *var, int seg) | |
1046 | { | |
a2fa3e9f | 1047 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1048 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1049 | ||
1050 | s->base = var->base; | |
1051 | s->limit = var->limit; | |
1052 | s->selector = var->selector; | |
1053 | if (var->unusable) | |
1054 | s->attrib = 0; | |
1055 | else { | |
1056 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1057 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1058 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1059 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1060 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1061 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1062 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1063 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1064 | } | |
1065 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1066 | svm->vmcb->save.cpl |
1067 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1068 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1069 | ||
1070 | } | |
1071 | ||
44c11430 | 1072 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1073 | { |
d0bfb940 JK |
1074 | struct vcpu_svm *svm = to_svm(vcpu); |
1075 | ||
d0bfb940 JK |
1076 | svm->vmcb->control.intercept_exceptions &= |
1077 | ~((1 << DB_VECTOR) | (1 << BP_VECTOR)); | |
44c11430 | 1078 | |
6be7d306 | 1079 | if (svm->nmi_singlestep) |
44c11430 GN |
1080 | svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR); |
1081 | ||
d0bfb940 JK |
1082 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1083 | if (vcpu->guest_debug & | |
1084 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
1085 | svm->vmcb->control.intercept_exceptions |= | |
1086 | 1 << DB_VECTOR; | |
1087 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
1088 | svm->vmcb->control.intercept_exceptions |= | |
1089 | 1 << BP_VECTOR; | |
1090 | } else | |
1091 | vcpu->guest_debug = 0; | |
44c11430 GN |
1092 | } |
1093 | ||
355be0b9 | 1094 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1095 | { |
44c11430 GN |
1096 | struct vcpu_svm *svm = to_svm(vcpu); |
1097 | ||
ae675ef0 JK |
1098 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1099 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1100 | else | |
1101 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1102 | ||
355be0b9 | 1103 | update_db_intercept(vcpu); |
6aa8b732 AK |
1104 | } |
1105 | ||
1106 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
1107 | { | |
94dfbdb3 | 1108 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1109 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1110 | #endif |
6aa8b732 AK |
1111 | } |
1112 | ||
1113 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
1114 | { | |
94dfbdb3 | 1115 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1116 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1117 | #endif |
6aa8b732 AK |
1118 | } |
1119 | ||
0fe1e009 | 1120 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1121 | { |
0fe1e009 TH |
1122 | if (sd->next_asid > sd->max_asid) { |
1123 | ++sd->asid_generation; | |
1124 | sd->next_asid = 1; | |
a2fa3e9f | 1125 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1126 | } |
1127 | ||
0fe1e009 TH |
1128 | svm->asid_generation = sd->asid_generation; |
1129 | svm->vmcb->control.asid = sd->next_asid++; | |
6aa8b732 AK |
1130 | } |
1131 | ||
c76de350 | 1132 | static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest) |
6aa8b732 | 1133 | { |
42dbaa5a | 1134 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a JK |
1135 | |
1136 | switch (dr) { | |
1137 | case 0 ... 3: | |
c76de350 | 1138 | *dest = vcpu->arch.db[dr]; |
42dbaa5a | 1139 | break; |
c76de350 JK |
1140 | case 4: |
1141 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
1142 | return EMULATE_FAIL; /* will re-inject UD */ | |
1143 | /* fall through */ | |
42dbaa5a JK |
1144 | case 6: |
1145 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
c76de350 | 1146 | *dest = vcpu->arch.dr6; |
42dbaa5a | 1147 | else |
c76de350 | 1148 | *dest = svm->vmcb->save.dr6; |
42dbaa5a | 1149 | break; |
c76de350 JK |
1150 | case 5: |
1151 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
1152 | return EMULATE_FAIL; /* will re-inject UD */ | |
1153 | /* fall through */ | |
42dbaa5a JK |
1154 | case 7: |
1155 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
c76de350 | 1156 | *dest = vcpu->arch.dr7; |
42dbaa5a | 1157 | else |
c76de350 | 1158 | *dest = svm->vmcb->save.dr7; |
42dbaa5a | 1159 | break; |
42dbaa5a JK |
1160 | } |
1161 | ||
c76de350 | 1162 | return EMULATE_DONE; |
6aa8b732 AK |
1163 | } |
1164 | ||
c76de350 | 1165 | static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value) |
6aa8b732 | 1166 | { |
a2fa3e9f GH |
1167 | struct vcpu_svm *svm = to_svm(vcpu); |
1168 | ||
6aa8b732 AK |
1169 | switch (dr) { |
1170 | case 0 ... 3: | |
42dbaa5a JK |
1171 | vcpu->arch.db[dr] = value; |
1172 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1173 | vcpu->arch.eff_db[dr] = value; | |
c76de350 JK |
1174 | break; |
1175 | case 4: | |
1176 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
1177 | return EMULATE_FAIL; /* will re-inject UD */ | |
1178 | /* fall through */ | |
42dbaa5a | 1179 | case 6: |
42dbaa5a | 1180 | vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1; |
c76de350 JK |
1181 | break; |
1182 | case 5: | |
1183 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
1184 | return EMULATE_FAIL; /* will re-inject UD */ | |
1185 | /* fall through */ | |
42dbaa5a | 1186 | case 7: |
42dbaa5a JK |
1187 | vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1; |
1188 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1189 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1190 | vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK); | |
1191 | } | |
c76de350 | 1192 | break; |
6aa8b732 | 1193 | } |
c76de350 JK |
1194 | |
1195 | return EMULATE_DONE; | |
6aa8b732 AK |
1196 | } |
1197 | ||
851ba692 | 1198 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1199 | { |
6aa8b732 AK |
1200 | u64 fault_address; |
1201 | u32 error_code; | |
6aa8b732 | 1202 | |
a2fa3e9f GH |
1203 | fault_address = svm->vmcb->control.exit_info_2; |
1204 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1205 | |
229456fc | 1206 | trace_kvm_page_fault(fault_address, error_code); |
52c7847d AK |
1207 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) |
1208 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
3067714c | 1209 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1210 | } |
1211 | ||
851ba692 | 1212 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1213 | { |
851ba692 AK |
1214 | struct kvm_run *kvm_run = svm->vcpu.run; |
1215 | ||
d0bfb940 | 1216 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1217 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1218 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1219 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1220 | return 1; | |
1221 | } | |
44c11430 | 1222 | |
6be7d306 JK |
1223 | if (svm->nmi_singlestep) { |
1224 | svm->nmi_singlestep = false; | |
44c11430 GN |
1225 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1226 | svm->vmcb->save.rflags &= | |
1227 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1228 | update_db_intercept(&svm->vcpu); | |
1229 | } | |
1230 | ||
1231 | if (svm->vcpu.guest_debug & | |
1232 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){ | |
1233 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1234 | kvm_run->debug.arch.pc = | |
1235 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1236 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | return 1; | |
d0bfb940 JK |
1241 | } |
1242 | ||
851ba692 | 1243 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1244 | { |
851ba692 AK |
1245 | struct kvm_run *kvm_run = svm->vcpu.run; |
1246 | ||
d0bfb940 JK |
1247 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1248 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1249 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1250 | return 0; | |
1251 | } | |
1252 | ||
851ba692 | 1253 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1254 | { |
1255 | int er; | |
1256 | ||
851ba692 | 1257 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1258 | if (er != EMULATE_DONE) |
7ee5d940 | 1259 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1260 | return 1; |
1261 | } | |
1262 | ||
6b52d186 | 1263 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1264 | { |
6b52d186 | 1265 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1266 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 1267 | svm->vcpu.fpu_active = 1; |
d225157b | 1268 | update_cr0_intercept(svm); |
6b52d186 | 1269 | } |
a2fa3e9f | 1270 | |
6b52d186 AK |
1271 | static int nm_interception(struct vcpu_svm *svm) |
1272 | { | |
1273 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1274 | return 1; |
7807fa6c AL |
1275 | } |
1276 | ||
851ba692 | 1277 | static int mc_interception(struct vcpu_svm *svm) |
53371b50 JR |
1278 | { |
1279 | /* | |
1280 | * On an #MC intercept the MCE handler is not called automatically in | |
1281 | * the host. So do it by hand here. | |
1282 | */ | |
1283 | asm volatile ( | |
1284 | "int $0x12\n"); | |
1285 | /* not sure if we ever come back to this point */ | |
1286 | ||
1287 | return 1; | |
1288 | } | |
1289 | ||
851ba692 | 1290 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1291 | { |
851ba692 AK |
1292 | struct kvm_run *kvm_run = svm->vcpu.run; |
1293 | ||
46fe4ddd JR |
1294 | /* |
1295 | * VMCB is undefined after a SHUTDOWN intercept | |
1296 | * so reinitialize it. | |
1297 | */ | |
a2fa3e9f | 1298 | clear_page(svm->vmcb); |
e6101a96 | 1299 | init_vmcb(svm); |
46fe4ddd JR |
1300 | |
1301 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1302 | return 0; | |
1303 | } | |
1304 | ||
851ba692 | 1305 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1306 | { |
d77c26fc | 1307 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1308 | int size, in, string; |
039576c0 | 1309 | unsigned port; |
6aa8b732 | 1310 | |
e756fc62 | 1311 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1312 | |
a2fa3e9f | 1313 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1314 | |
e70669ab LV |
1315 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1316 | ||
1317 | if (string) { | |
3427318f | 1318 | if (emulate_instruction(&svm->vcpu, |
851ba692 | 1319 | 0, 0, 0) == EMULATE_DO_MMIO) |
e70669ab LV |
1320 | return 0; |
1321 | return 1; | |
1322 | } | |
1323 | ||
039576c0 AK |
1324 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1325 | port = io_info >> 16; | |
1326 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
6aa8b732 | 1327 | |
e93f36bc | 1328 | skip_emulated_instruction(&svm->vcpu); |
851ba692 | 1329 | return kvm_emulate_pio(&svm->vcpu, in, size, port); |
6aa8b732 AK |
1330 | } |
1331 | ||
851ba692 | 1332 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1333 | { |
1334 | return 1; | |
1335 | } | |
1336 | ||
851ba692 | 1337 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1338 | { |
1339 | ++svm->vcpu.stat.irq_exits; | |
1340 | return 1; | |
1341 | } | |
1342 | ||
851ba692 | 1343 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1344 | { |
1345 | return 1; | |
1346 | } | |
1347 | ||
851ba692 | 1348 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1349 | { |
5fdbf976 | 1350 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1351 | skip_emulated_instruction(&svm->vcpu); |
1352 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1353 | } |
1354 | ||
851ba692 | 1355 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1356 | { |
5fdbf976 | 1357 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1358 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1359 | kvm_emulate_hypercall(&svm->vcpu); |
1360 | return 1; | |
02e235bc AK |
1361 | } |
1362 | ||
c0725420 AG |
1363 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1364 | { | |
f6801dff | 1365 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1366 | || !is_paging(&svm->vcpu)) { |
1367 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1368 | return 1; | |
1369 | } | |
1370 | ||
1371 | if (svm->vmcb->save.cpl) { | |
1372 | kvm_inject_gp(&svm->vcpu, 0); | |
1373 | return 1; | |
1374 | } | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
cf74a78b AG |
1379 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1380 | bool has_error_code, u32 error_code) | |
1381 | { | |
0295ad7d JR |
1382 | if (!is_nested(svm)) |
1383 | return 0; | |
cf74a78b | 1384 | |
0295ad7d JR |
1385 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1386 | svm->vmcb->control.exit_code_hi = 0; | |
1387 | svm->vmcb->control.exit_info_1 = error_code; | |
1388 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1389 | ||
410e4d57 | 1390 | return nested_svm_exit_handled(svm); |
cf74a78b AG |
1391 | } |
1392 | ||
1393 | static inline int nested_svm_intr(struct vcpu_svm *svm) | |
1394 | { | |
26666957 JR |
1395 | if (!is_nested(svm)) |
1396 | return 0; | |
cf74a78b | 1397 | |
26666957 JR |
1398 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
1399 | return 0; | |
cf74a78b | 1400 | |
26666957 JR |
1401 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
1402 | return 0; | |
cf74a78b | 1403 | |
26666957 JR |
1404 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1405 | ||
cd3ff653 JR |
1406 | if (svm->nested.intercept & 1ULL) { |
1407 | /* | |
1408 | * The #vmexit can't be emulated here directly because this | |
1409 | * code path runs with irqs and preemtion disabled. A | |
1410 | * #vmexit emulation might sleep. Only signal request for | |
1411 | * the #vmexit here. | |
1412 | */ | |
1413 | svm->nested.exit_required = true; | |
236649de | 1414 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
26666957 | 1415 | return 1; |
cf74a78b AG |
1416 | } |
1417 | ||
1418 | return 0; | |
1419 | } | |
1420 | ||
34f80cfa JR |
1421 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx) |
1422 | { | |
1423 | struct page *page; | |
1424 | ||
34f80cfa | 1425 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1426 | if (is_error_page(page)) |
1427 | goto error; | |
1428 | ||
1429 | return kmap_atomic(page, idx); | |
1430 | ||
1431 | error: | |
1432 | kvm_release_page_clean(page); | |
1433 | kvm_inject_gp(&svm->vcpu, 0); | |
1434 | ||
1435 | return NULL; | |
1436 | } | |
1437 | ||
1438 | static void nested_svm_unmap(void *addr, enum km_type idx) | |
1439 | { | |
1440 | struct page *page; | |
1441 | ||
1442 | if (!addr) | |
1443 | return; | |
1444 | ||
1445 | page = kmap_atomic_to_page(addr); | |
1446 | ||
1447 | kunmap_atomic(addr, idx); | |
1448 | kvm_release_page_dirty(page); | |
1449 | } | |
1450 | ||
3d62d9aa | 1451 | static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1452 | { |
4c2161ae | 1453 | u32 param = svm->vmcb->control.exit_info_1 & 1; |
3d62d9aa JR |
1454 | u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1455 | bool ret = false; | |
1456 | u32 t0, t1; | |
1457 | u8 *msrpm; | |
4c2161ae | 1458 | |
3d62d9aa JR |
1459 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
1460 | return false; | |
1461 | ||
1462 | msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0); | |
1463 | ||
1464 | if (!msrpm) | |
1465 | goto out; | |
4c2161ae JR |
1466 | |
1467 | switch (msr) { | |
1468 | case 0 ... 0x1fff: | |
1469 | t0 = (msr * 2) % 8; | |
1470 | t1 = msr / 8; | |
1471 | break; | |
1472 | case 0xc0000000 ... 0xc0001fff: | |
1473 | t0 = (8192 + msr - 0xc0000000) * 2; | |
1474 | t1 = (t0 / 8); | |
1475 | t0 %= 8; | |
1476 | break; | |
1477 | case 0xc0010000 ... 0xc0011fff: | |
1478 | t0 = (16384 + msr - 0xc0010000) * 2; | |
1479 | t1 = (t0 / 8); | |
1480 | t0 %= 8; | |
1481 | break; | |
1482 | default: | |
3d62d9aa JR |
1483 | ret = true; |
1484 | goto out; | |
4c2161ae | 1485 | } |
4c2161ae | 1486 | |
3d62d9aa JR |
1487 | ret = msrpm[t1] & ((1 << param) << t0); |
1488 | ||
1489 | out: | |
1490 | nested_svm_unmap(msrpm, KM_USER0); | |
1491 | ||
1492 | return ret; | |
4c2161ae JR |
1493 | } |
1494 | ||
410e4d57 | 1495 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1496 | { |
cf74a78b | 1497 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1498 | |
410e4d57 JR |
1499 | switch (exit_code) { |
1500 | case SVM_EXIT_INTR: | |
1501 | case SVM_EXIT_NMI: | |
1502 | return NESTED_EXIT_HOST; | |
cf74a78b | 1503 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1504 | case SVM_EXIT_NPF: |
1505 | if (npt_enabled) | |
1506 | return NESTED_EXIT_HOST; | |
1507 | break; | |
1508 | /* When we're shadowing, trap PFs */ | |
1509 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: | |
1510 | if (!npt_enabled) | |
1511 | return NESTED_EXIT_HOST; | |
1512 | break; | |
1513 | default: | |
1514 | break; | |
cf74a78b AG |
1515 | } |
1516 | ||
410e4d57 JR |
1517 | return NESTED_EXIT_CONTINUE; |
1518 | } | |
1519 | ||
1520 | /* | |
1521 | * If this function returns true, this #vmexit was already handled | |
1522 | */ | |
1523 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1524 | { | |
1525 | u32 exit_code = svm->vmcb->control.exit_code; | |
1526 | int vmexit = NESTED_EXIT_HOST; | |
1527 | ||
cf74a78b | 1528 | switch (exit_code) { |
9c4e40b9 | 1529 | case SVM_EXIT_MSR: |
3d62d9aa | 1530 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1531 | break; |
cf74a78b AG |
1532 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { |
1533 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); | |
aad42c64 | 1534 | if (svm->nested.intercept_cr_read & cr_bits) |
410e4d57 | 1535 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1536 | break; |
1537 | } | |
1538 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: { | |
1539 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0); | |
aad42c64 | 1540 | if (svm->nested.intercept_cr_write & cr_bits) |
410e4d57 | 1541 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1542 | break; |
1543 | } | |
1544 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: { | |
1545 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0); | |
aad42c64 | 1546 | if (svm->nested.intercept_dr_read & dr_bits) |
410e4d57 | 1547 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1548 | break; |
1549 | } | |
1550 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: { | |
1551 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0); | |
aad42c64 | 1552 | if (svm->nested.intercept_dr_write & dr_bits) |
410e4d57 | 1553 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1554 | break; |
1555 | } | |
1556 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1557 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1558 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1559 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1560 | break; |
1561 | } | |
1562 | default: { | |
1563 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 1564 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 1565 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1566 | } |
1567 | } | |
1568 | ||
410e4d57 | 1569 | if (vmexit == NESTED_EXIT_DONE) { |
9c4e40b9 JR |
1570 | nested_svm_vmexit(svm); |
1571 | } | |
1572 | ||
1573 | return vmexit; | |
cf74a78b AG |
1574 | } |
1575 | ||
0460a979 JR |
1576 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
1577 | { | |
1578 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
1579 | struct vmcb_control_area *from = &from_vmcb->control; | |
1580 | ||
1581 | dst->intercept_cr_read = from->intercept_cr_read; | |
1582 | dst->intercept_cr_write = from->intercept_cr_write; | |
1583 | dst->intercept_dr_read = from->intercept_dr_read; | |
1584 | dst->intercept_dr_write = from->intercept_dr_write; | |
1585 | dst->intercept_exceptions = from->intercept_exceptions; | |
1586 | dst->intercept = from->intercept; | |
1587 | dst->iopm_base_pa = from->iopm_base_pa; | |
1588 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
1589 | dst->tsc_offset = from->tsc_offset; | |
1590 | dst->asid = from->asid; | |
1591 | dst->tlb_ctl = from->tlb_ctl; | |
1592 | dst->int_ctl = from->int_ctl; | |
1593 | dst->int_vector = from->int_vector; | |
1594 | dst->int_state = from->int_state; | |
1595 | dst->exit_code = from->exit_code; | |
1596 | dst->exit_code_hi = from->exit_code_hi; | |
1597 | dst->exit_info_1 = from->exit_info_1; | |
1598 | dst->exit_info_2 = from->exit_info_2; | |
1599 | dst->exit_int_info = from->exit_int_info; | |
1600 | dst->exit_int_info_err = from->exit_int_info_err; | |
1601 | dst->nested_ctl = from->nested_ctl; | |
1602 | dst->event_inj = from->event_inj; | |
1603 | dst->event_inj_err = from->event_inj_err; | |
1604 | dst->nested_cr3 = from->nested_cr3; | |
1605 | dst->lbr_ctl = from->lbr_ctl; | |
1606 | } | |
1607 | ||
34f80cfa | 1608 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 1609 | { |
34f80cfa | 1610 | struct vmcb *nested_vmcb; |
e6aa9abd | 1611 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 1612 | struct vmcb *vmcb = svm->vmcb; |
cf74a78b | 1613 | |
17897f36 JR |
1614 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
1615 | vmcb->control.exit_info_1, | |
1616 | vmcb->control.exit_info_2, | |
1617 | vmcb->control.exit_int_info, | |
1618 | vmcb->control.exit_int_info_err); | |
1619 | ||
34f80cfa JR |
1620 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0); |
1621 | if (!nested_vmcb) | |
1622 | return 1; | |
1623 | ||
cf74a78b | 1624 | /* Give the current vmcb to the guest */ |
33740e40 JR |
1625 | disable_gif(svm); |
1626 | ||
1627 | nested_vmcb->save.es = vmcb->save.es; | |
1628 | nested_vmcb->save.cs = vmcb->save.cs; | |
1629 | nested_vmcb->save.ss = vmcb->save.ss; | |
1630 | nested_vmcb->save.ds = vmcb->save.ds; | |
1631 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
1632 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
1633 | if (npt_enabled) | |
1634 | nested_vmcb->save.cr3 = vmcb->save.cr3; | |
1635 | nested_vmcb->save.cr2 = vmcb->save.cr2; | |
1636 | nested_vmcb->save.rflags = vmcb->save.rflags; | |
1637 | nested_vmcb->save.rip = vmcb->save.rip; | |
1638 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
1639 | nested_vmcb->save.rax = vmcb->save.rax; | |
1640 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
1641 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
1642 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
1643 | ||
1644 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
1645 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
1646 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
1647 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
1648 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
1649 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
1650 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
1651 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
1652 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
8d23c466 AG |
1653 | |
1654 | /* | |
1655 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
1656 | * to make sure that we do not lose injected events. So check event_inj | |
1657 | * here and copy it to exit_int_info if it is valid. | |
1658 | * Exit_int_info and event_inj can't be both valid because the case | |
1659 | * below only happens on a VMRUN instruction intercept which has | |
1660 | * no valid exit_int_info set. | |
1661 | */ | |
1662 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
1663 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
1664 | ||
1665 | nc->exit_int_info = vmcb->control.event_inj; | |
1666 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
1667 | } | |
1668 | ||
33740e40 JR |
1669 | nested_vmcb->control.tlb_ctl = 0; |
1670 | nested_vmcb->control.event_inj = 0; | |
1671 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
1672 | |
1673 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
1674 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1675 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
1676 | ||
cf74a78b | 1677 | /* Restore the original control entries */ |
0460a979 | 1678 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 1679 | |
219b65dc AG |
1680 | kvm_clear_exception_queue(&svm->vcpu); |
1681 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b AG |
1682 | |
1683 | /* Restore selected save entries */ | |
1684 | svm->vmcb->save.es = hsave->save.es; | |
1685 | svm->vmcb->save.cs = hsave->save.cs; | |
1686 | svm->vmcb->save.ss = hsave->save.ss; | |
1687 | svm->vmcb->save.ds = hsave->save.ds; | |
1688 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
1689 | svm->vmcb->save.idtr = hsave->save.idtr; | |
1690 | svm->vmcb->save.rflags = hsave->save.rflags; | |
1691 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
1692 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
1693 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
1694 | if (npt_enabled) { | |
1695 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
1696 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
1697 | } else { | |
1698 | kvm_set_cr3(&svm->vcpu, hsave->save.cr3); | |
1699 | } | |
1700 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
1701 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
1702 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
1703 | svm->vmcb->save.dr7 = 0; | |
1704 | svm->vmcb->save.cpl = 0; | |
1705 | svm->vmcb->control.exit_int_info = 0; | |
1706 | ||
cf74a78b | 1707 | /* Exit nested SVM mode */ |
e6aa9abd | 1708 | svm->nested.vmcb = 0; |
cf74a78b | 1709 | |
34f80cfa | 1710 | nested_svm_unmap(nested_vmcb, KM_USER0); |
cf74a78b AG |
1711 | |
1712 | kvm_mmu_reset_context(&svm->vcpu); | |
1713 | kvm_mmu_load(&svm->vcpu); | |
1714 | ||
1715 | return 0; | |
1716 | } | |
3d6368ef | 1717 | |
9738b2c9 | 1718 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 1719 | { |
9738b2c9 | 1720 | u32 *nested_msrpm; |
3d6368ef | 1721 | int i; |
9738b2c9 JR |
1722 | |
1723 | nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0); | |
1724 | if (!nested_msrpm) | |
1725 | return false; | |
1726 | ||
3d6368ef | 1727 | for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++) |
e6aa9abd | 1728 | svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i]; |
9738b2c9 | 1729 | |
e6aa9abd | 1730 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
3d6368ef | 1731 | |
9738b2c9 JR |
1732 | nested_svm_unmap(nested_msrpm, KM_USER0); |
1733 | ||
1734 | return true; | |
3d6368ef AG |
1735 | } |
1736 | ||
9738b2c9 | 1737 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 1738 | { |
9738b2c9 | 1739 | struct vmcb *nested_vmcb; |
e6aa9abd | 1740 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 1741 | struct vmcb *vmcb = svm->vmcb; |
3d6368ef | 1742 | |
9738b2c9 JR |
1743 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1744 | if (!nested_vmcb) | |
1745 | return false; | |
1746 | ||
3d6368ef | 1747 | /* nested_vmcb is our indicator if nested SVM is activated */ |
e6aa9abd | 1748 | svm->nested.vmcb = svm->vmcb->save.rax; |
3d6368ef | 1749 | |
0ac406de JR |
1750 | trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb, |
1751 | nested_vmcb->save.rip, | |
1752 | nested_vmcb->control.int_ctl, | |
1753 | nested_vmcb->control.event_inj, | |
1754 | nested_vmcb->control.nested_ctl); | |
1755 | ||
3d6368ef | 1756 | /* Clear internal status */ |
219b65dc AG |
1757 | kvm_clear_exception_queue(&svm->vcpu); |
1758 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef AG |
1759 | |
1760 | /* Save the old vmcb, so we don't need to pick what we save, but | |
1761 | can restore everything when a VMEXIT occurs */ | |
defbba56 JR |
1762 | hsave->save.es = vmcb->save.es; |
1763 | hsave->save.cs = vmcb->save.cs; | |
1764 | hsave->save.ss = vmcb->save.ss; | |
1765 | hsave->save.ds = vmcb->save.ds; | |
1766 | hsave->save.gdtr = vmcb->save.gdtr; | |
1767 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 1768 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 1769 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 JR |
1770 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
1771 | hsave->save.rflags = vmcb->save.rflags; | |
1772 | hsave->save.rip = svm->next_rip; | |
1773 | hsave->save.rsp = vmcb->save.rsp; | |
1774 | hsave->save.rax = vmcb->save.rax; | |
1775 | if (npt_enabled) | |
1776 | hsave->save.cr3 = vmcb->save.cr3; | |
1777 | else | |
1778 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
1779 | ||
0460a979 | 1780 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
1781 | |
1782 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
1783 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
1784 | else | |
1785 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
1786 | ||
1787 | /* Load the nested guest state */ | |
1788 | svm->vmcb->save.es = nested_vmcb->save.es; | |
1789 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
1790 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
1791 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
1792 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
1793 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
1794 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
1795 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
1796 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
1797 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
1798 | if (npt_enabled) { | |
1799 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
1800 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
1801 | } else { | |
1802 | kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); | |
1803 | kvm_mmu_reset_context(&svm->vcpu); | |
1804 | } | |
defbba56 | 1805 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
1806 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
1807 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
1808 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
1809 | /* In case we don't even reach vcpu_run, the fields are not updated */ | |
1810 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
1811 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
1812 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
1813 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
1814 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
1815 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
1816 | ||
1817 | /* We don't want a nested guest to be more powerful than the guest, | |
1818 | so all intercepts are ORed */ | |
1819 | svm->vmcb->control.intercept_cr_read |= | |
1820 | nested_vmcb->control.intercept_cr_read; | |
1821 | svm->vmcb->control.intercept_cr_write |= | |
1822 | nested_vmcb->control.intercept_cr_write; | |
1823 | svm->vmcb->control.intercept_dr_read |= | |
1824 | nested_vmcb->control.intercept_dr_read; | |
1825 | svm->vmcb->control.intercept_dr_write |= | |
1826 | nested_vmcb->control.intercept_dr_write; | |
1827 | svm->vmcb->control.intercept_exceptions |= | |
1828 | nested_vmcb->control.intercept_exceptions; | |
1829 | ||
1830 | svm->vmcb->control.intercept |= nested_vmcb->control.intercept; | |
1831 | ||
e6aa9abd | 1832 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa; |
3d6368ef | 1833 | |
aad42c64 JR |
1834 | /* cache intercepts */ |
1835 | svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read; | |
1836 | svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write; | |
1837 | svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read; | |
1838 | svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write; | |
1839 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; | |
1840 | svm->nested.intercept = nested_vmcb->control.intercept; | |
1841 | ||
3d6368ef | 1842 | force_new_asid(&svm->vcpu); |
3d6368ef | 1843 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
1844 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
1845 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
1846 | else | |
1847 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
1848 | ||
3d6368ef AG |
1849 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
1850 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
1851 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
1852 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
1853 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
1854 | ||
9738b2c9 JR |
1855 | nested_svm_unmap(nested_vmcb, KM_USER0); |
1856 | ||
2af9194d | 1857 | enable_gif(svm); |
3d6368ef | 1858 | |
9738b2c9 | 1859 | return true; |
3d6368ef AG |
1860 | } |
1861 | ||
9966bf68 | 1862 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
1863 | { |
1864 | to_vmcb->save.fs = from_vmcb->save.fs; | |
1865 | to_vmcb->save.gs = from_vmcb->save.gs; | |
1866 | to_vmcb->save.tr = from_vmcb->save.tr; | |
1867 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
1868 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
1869 | to_vmcb->save.star = from_vmcb->save.star; | |
1870 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
1871 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
1872 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
1873 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
1874 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
1875 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
1876 | } |
1877 | ||
851ba692 | 1878 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 1879 | { |
9966bf68 JR |
1880 | struct vmcb *nested_vmcb; |
1881 | ||
5542675b AG |
1882 | if (nested_svm_check_permissions(svm)) |
1883 | return 1; | |
1884 | ||
1885 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1886 | skip_emulated_instruction(&svm->vcpu); | |
1887 | ||
9966bf68 JR |
1888 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1889 | if (!nested_vmcb) | |
1890 | return 1; | |
1891 | ||
1892 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
1893 | nested_svm_unmap(nested_vmcb, KM_USER0); | |
5542675b AG |
1894 | |
1895 | return 1; | |
1896 | } | |
1897 | ||
851ba692 | 1898 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 1899 | { |
9966bf68 JR |
1900 | struct vmcb *nested_vmcb; |
1901 | ||
5542675b AG |
1902 | if (nested_svm_check_permissions(svm)) |
1903 | return 1; | |
1904 | ||
1905 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1906 | skip_emulated_instruction(&svm->vcpu); | |
1907 | ||
9966bf68 JR |
1908 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1909 | if (!nested_vmcb) | |
1910 | return 1; | |
1911 | ||
1912 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
1913 | nested_svm_unmap(nested_vmcb, KM_USER0); | |
5542675b AG |
1914 | |
1915 | return 1; | |
1916 | } | |
1917 | ||
851ba692 | 1918 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 1919 | { |
3d6368ef AG |
1920 | if (nested_svm_check_permissions(svm)) |
1921 | return 1; | |
1922 | ||
1923 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1924 | skip_emulated_instruction(&svm->vcpu); | |
1925 | ||
9738b2c9 | 1926 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
1927 | return 1; |
1928 | ||
9738b2c9 | 1929 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
1930 | goto failed; |
1931 | ||
1932 | return 1; | |
1933 | ||
1934 | failed: | |
1935 | ||
1936 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
1937 | svm->vmcb->control.exit_code_hi = 0; | |
1938 | svm->vmcb->control.exit_info_1 = 0; | |
1939 | svm->vmcb->control.exit_info_2 = 0; | |
1940 | ||
1941 | nested_svm_vmexit(svm); | |
3d6368ef AG |
1942 | |
1943 | return 1; | |
1944 | } | |
1945 | ||
851ba692 | 1946 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
1947 | { |
1948 | if (nested_svm_check_permissions(svm)) | |
1949 | return 1; | |
1950 | ||
1951 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1952 | skip_emulated_instruction(&svm->vcpu); | |
1953 | ||
2af9194d | 1954 | enable_gif(svm); |
1371d904 AG |
1955 | |
1956 | return 1; | |
1957 | } | |
1958 | ||
851ba692 | 1959 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
1960 | { |
1961 | if (nested_svm_check_permissions(svm)) | |
1962 | return 1; | |
1963 | ||
1964 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1965 | skip_emulated_instruction(&svm->vcpu); | |
1966 | ||
2af9194d | 1967 | disable_gif(svm); |
1371d904 AG |
1968 | |
1969 | /* After a CLGI no interrupts should come */ | |
1970 | svm_clear_vintr(svm); | |
1971 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
1972 | ||
1973 | return 1; | |
1974 | } | |
1975 | ||
851ba692 | 1976 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
1977 | { |
1978 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 1979 | |
ec1ff790 JR |
1980 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
1981 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
1982 | ||
ff092385 AG |
1983 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
1984 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
1985 | ||
1986 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1987 | skip_emulated_instruction(&svm->vcpu); | |
1988 | return 1; | |
1989 | } | |
1990 | ||
532a46b9 JR |
1991 | static int skinit_interception(struct vcpu_svm *svm) |
1992 | { | |
1993 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
1994 | ||
1995 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1996 | return 1; | |
1997 | } | |
1998 | ||
851ba692 | 1999 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2000 | { |
7ee5d940 | 2001 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2002 | return 1; |
2003 | } | |
2004 | ||
851ba692 | 2005 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2006 | { |
37817f29 | 2007 | u16 tss_selector; |
64a7ec06 GN |
2008 | int reason; |
2009 | int int_type = svm->vmcb->control.exit_int_info & | |
2010 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2011 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2012 | uint32_t type = |
2013 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2014 | uint32_t idt_v = | |
2015 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
37817f29 IE |
2016 | |
2017 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2018 | |
37817f29 IE |
2019 | if (svm->vmcb->control.exit_info_2 & |
2020 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2021 | reason = TASK_SWITCH_IRET; |
2022 | else if (svm->vmcb->control.exit_info_2 & | |
2023 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2024 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2025 | else if (idt_v) |
64a7ec06 GN |
2026 | reason = TASK_SWITCH_GATE; |
2027 | else | |
2028 | reason = TASK_SWITCH_CALL; | |
2029 | ||
fe8e7f83 GN |
2030 | if (reason == TASK_SWITCH_GATE) { |
2031 | switch (type) { | |
2032 | case SVM_EXITINTINFO_TYPE_NMI: | |
2033 | svm->vcpu.arch.nmi_injected = false; | |
2034 | break; | |
2035 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
2036 | kvm_clear_exception_queue(&svm->vcpu); | |
2037 | break; | |
2038 | case SVM_EXITINTINFO_TYPE_INTR: | |
2039 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2040 | break; | |
2041 | default: | |
2042 | break; | |
2043 | } | |
2044 | } | |
64a7ec06 | 2045 | |
8317c298 GN |
2046 | if (reason != TASK_SWITCH_GATE || |
2047 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2048 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2049 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2050 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 GN |
2051 | |
2052 | return kvm_task_switch(&svm->vcpu, tss_selector, reason); | |
6aa8b732 AK |
2053 | } |
2054 | ||
851ba692 | 2055 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2056 | { |
5fdbf976 | 2057 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2058 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2059 | return 1; |
6aa8b732 AK |
2060 | } |
2061 | ||
851ba692 | 2062 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2063 | { |
2064 | ++svm->vcpu.stat.nmi_window_exits; | |
2065 | svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET); | |
44c11430 | 2066 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2067 | return 1; |
2068 | } | |
2069 | ||
851ba692 | 2070 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2071 | { |
851ba692 | 2072 | if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE) |
a7052897 MT |
2073 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
2074 | return 1; | |
2075 | } | |
2076 | ||
851ba692 | 2077 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2078 | { |
851ba692 | 2079 | if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 2080 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
2081 | return 1; |
2082 | } | |
2083 | ||
851ba692 | 2084 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2085 | { |
851ba692 AK |
2086 | struct kvm_run *kvm_run = svm->vcpu.run; |
2087 | ||
0a5fff19 GN |
2088 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2089 | /* instruction emulation calls kvm_set_cr8() */ | |
851ba692 | 2090 | emulate_instruction(&svm->vcpu, 0, 0, 0); |
95ba8273 GN |
2091 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
2092 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1d075434 | 2093 | return 1; |
95ba8273 | 2094 | } |
0a5fff19 GN |
2095 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
2096 | return 1; | |
1d075434 JR |
2097 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2098 | return 0; | |
2099 | } | |
2100 | ||
6aa8b732 AK |
2101 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2102 | { | |
a2fa3e9f GH |
2103 | struct vcpu_svm *svm = to_svm(vcpu); |
2104 | ||
6aa8b732 | 2105 | switch (ecx) { |
af24a4e4 | 2106 | case MSR_IA32_TSC: { |
20824f30 | 2107 | u64 tsc_offset; |
6aa8b732 | 2108 | |
20824f30 JR |
2109 | if (is_nested(svm)) |
2110 | tsc_offset = svm->nested.hsave->control.tsc_offset; | |
2111 | else | |
2112 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2113 | ||
2114 | *data = tsc_offset + native_read_tsc(); | |
6aa8b732 AK |
2115 | break; |
2116 | } | |
0e859cac | 2117 | case MSR_K6_STAR: |
a2fa3e9f | 2118 | *data = svm->vmcb->save.star; |
6aa8b732 | 2119 | break; |
0e859cac | 2120 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2121 | case MSR_LSTAR: |
a2fa3e9f | 2122 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2123 | break; |
2124 | case MSR_CSTAR: | |
a2fa3e9f | 2125 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2126 | break; |
2127 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2128 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2129 | break; |
2130 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2131 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2132 | break; |
2133 | #endif | |
2134 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2135 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2136 | break; |
2137 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2138 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2139 | break; |
2140 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2141 | *data = svm->sysenter_esp; |
6aa8b732 | 2142 | break; |
a2938c80 JR |
2143 | /* Nobody will change the following 5 values in the VMCB so |
2144 | we can safely return them on rdmsr. They will always be 0 | |
2145 | until LBRV is implemented. */ | |
2146 | case MSR_IA32_DEBUGCTLMSR: | |
2147 | *data = svm->vmcb->save.dbgctl; | |
2148 | break; | |
2149 | case MSR_IA32_LASTBRANCHFROMIP: | |
2150 | *data = svm->vmcb->save.br_from; | |
2151 | break; | |
2152 | case MSR_IA32_LASTBRANCHTOIP: | |
2153 | *data = svm->vmcb->save.br_to; | |
2154 | break; | |
2155 | case MSR_IA32_LASTINTFROMIP: | |
2156 | *data = svm->vmcb->save.last_excp_from; | |
2157 | break; | |
2158 | case MSR_IA32_LASTINTTOIP: | |
2159 | *data = svm->vmcb->save.last_excp_to; | |
2160 | break; | |
b286d5d8 | 2161 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2162 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2163 | break; |
eb6f302e JR |
2164 | case MSR_VM_CR: |
2165 | *data = 0; | |
2166 | break; | |
c8a73f18 AG |
2167 | case MSR_IA32_UCODE_REV: |
2168 | *data = 0x01000065; | |
2169 | break; | |
6aa8b732 | 2170 | default: |
3bab1f5d | 2171 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2172 | } |
2173 | return 0; | |
2174 | } | |
2175 | ||
851ba692 | 2176 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2177 | { |
ad312c7c | 2178 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2179 | u64 data; |
2180 | ||
59200273 AK |
2181 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2182 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2183 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2184 | } else { |
229456fc | 2185 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2186 | |
5fdbf976 | 2187 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2188 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2189 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2190 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2191 | } |
2192 | return 1; | |
2193 | } | |
2194 | ||
2195 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
2196 | { | |
a2fa3e9f GH |
2197 | struct vcpu_svm *svm = to_svm(vcpu); |
2198 | ||
6aa8b732 | 2199 | switch (ecx) { |
af24a4e4 | 2200 | case MSR_IA32_TSC: { |
20824f30 JR |
2201 | u64 tsc_offset = data - native_read_tsc(); |
2202 | u64 g_tsc_offset = 0; | |
2203 | ||
2204 | if (is_nested(svm)) { | |
2205 | g_tsc_offset = svm->vmcb->control.tsc_offset - | |
2206 | svm->nested.hsave->control.tsc_offset; | |
2207 | svm->nested.hsave->control.tsc_offset = tsc_offset; | |
2208 | } | |
2209 | ||
2210 | svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset; | |
6aa8b732 | 2211 | |
6aa8b732 AK |
2212 | break; |
2213 | } | |
0e859cac | 2214 | case MSR_K6_STAR: |
a2fa3e9f | 2215 | svm->vmcb->save.star = data; |
6aa8b732 | 2216 | break; |
49b14f24 | 2217 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2218 | case MSR_LSTAR: |
a2fa3e9f | 2219 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2220 | break; |
2221 | case MSR_CSTAR: | |
a2fa3e9f | 2222 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2223 | break; |
2224 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2225 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2226 | break; |
2227 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2228 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2229 | break; |
2230 | #endif | |
2231 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2232 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2233 | break; |
2234 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2235 | svm->sysenter_eip = data; |
a2fa3e9f | 2236 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2237 | break; |
2238 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2239 | svm->sysenter_esp = data; |
a2fa3e9f | 2240 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2241 | break; |
a2938c80 | 2242 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
2243 | if (!svm_has(SVM_FEATURE_LBRV)) { |
2244 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 2245 | __func__, data); |
24e09cbf JR |
2246 | break; |
2247 | } | |
2248 | if (data & DEBUGCTL_RESERVED_BITS) | |
2249 | return 1; | |
2250 | ||
2251 | svm->vmcb->save.dbgctl = data; | |
2252 | if (data & (1ULL<<0)) | |
2253 | svm_enable_lbrv(svm); | |
2254 | else | |
2255 | svm_disable_lbrv(svm); | |
a2938c80 | 2256 | break; |
b286d5d8 | 2257 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2258 | svm->nested.hsave_msr = data; |
62b9abaa | 2259 | break; |
3c5d0a44 AG |
2260 | case MSR_VM_CR: |
2261 | case MSR_VM_IGNNE: | |
3c5d0a44 AG |
2262 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2263 | break; | |
6aa8b732 | 2264 | default: |
3bab1f5d | 2265 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2266 | } |
2267 | return 0; | |
2268 | } | |
2269 | ||
851ba692 | 2270 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2271 | { |
ad312c7c | 2272 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2273 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2274 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2275 | |
af9ca2d7 | 2276 | |
5fdbf976 | 2277 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2278 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2279 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 2280 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
2281 | } else { |
2282 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 2283 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 2284 | } |
6aa8b732 AK |
2285 | return 1; |
2286 | } | |
2287 | ||
851ba692 | 2288 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2289 | { |
e756fc62 | 2290 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2291 | return wrmsr_interception(svm); |
6aa8b732 | 2292 | else |
851ba692 | 2293 | return rdmsr_interception(svm); |
6aa8b732 AK |
2294 | } |
2295 | ||
851ba692 | 2296 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2297 | { |
851ba692 AK |
2298 | struct kvm_run *kvm_run = svm->vcpu.run; |
2299 | ||
f0b85051 | 2300 | svm_clear_vintr(svm); |
85f455f7 | 2301 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2302 | /* |
2303 | * If the user space waits to inject interrupts, exit as soon as | |
2304 | * possible | |
2305 | */ | |
8061823a GN |
2306 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
2307 | kvm_run->request_interrupt_window && | |
2308 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 2309 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2310 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | return 1; | |
2315 | } | |
2316 | ||
565d0998 ML |
2317 | static int pause_interception(struct vcpu_svm *svm) |
2318 | { | |
2319 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
2320 | return 1; | |
2321 | } | |
2322 | ||
851ba692 | 2323 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
6aa8b732 AK |
2324 | [SVM_EXIT_READ_CR0] = emulate_on_interception, |
2325 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2326 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 2327 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
d225157b | 2328 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
6aa8b732 AK |
2329 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, |
2330 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
2331 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 2332 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
2333 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
2334 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
2335 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2336 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
727f5a23 JK |
2337 | [SVM_EXIT_READ_DR4] = emulate_on_interception, |
2338 | [SVM_EXIT_READ_DR5] = emulate_on_interception, | |
2339 | [SVM_EXIT_READ_DR6] = emulate_on_interception, | |
2340 | [SVM_EXIT_READ_DR7] = emulate_on_interception, | |
6aa8b732 AK |
2341 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, |
2342 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2343 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2344 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
727f5a23 | 2345 | [SVM_EXIT_WRITE_DR4] = emulate_on_interception, |
6aa8b732 | 2346 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, |
727f5a23 | 2347 | [SVM_EXIT_WRITE_DR6] = emulate_on_interception, |
6aa8b732 | 2348 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, |
d0bfb940 JK |
2349 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
2350 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 2351 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 2352 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 2353 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 2354 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 2355 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 2356 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2357 | [SVM_EXIT_SMI] = nop_on_interception, |
2358 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2359 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
2360 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
2361 | [SVM_EXIT_CPUID] = cpuid_interception, | |
95ba8273 | 2362 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 2363 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 2364 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 2365 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2366 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 2367 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
6aa8b732 AK |
2368 | [SVM_EXIT_IOIO] = io_interception, |
2369 | [SVM_EXIT_MSR] = msr_interception, | |
2370 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2371 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2372 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2373 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2374 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2375 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2376 | [SVM_EXIT_STGI] = stgi_interception, |
2377 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 2378 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 2379 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2380 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2381 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2382 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2383 | }; |
2384 | ||
851ba692 | 2385 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 2386 | { |
04d2cc77 | 2387 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 2388 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 2389 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 2390 | |
229456fc | 2391 | trace_kvm_exit(exit_code, svm->vmcb->save.rip); |
af9ca2d7 | 2392 | |
cd3ff653 JR |
2393 | if (unlikely(svm->nested.exit_required)) { |
2394 | nested_svm_vmexit(svm); | |
2395 | svm->nested.exit_required = false; | |
2396 | ||
2397 | return 1; | |
2398 | } | |
2399 | ||
cf74a78b | 2400 | if (is_nested(svm)) { |
410e4d57 JR |
2401 | int vmexit; |
2402 | ||
d8cabddf JR |
2403 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
2404 | svm->vmcb->control.exit_info_1, | |
2405 | svm->vmcb->control.exit_info_2, | |
2406 | svm->vmcb->control.exit_int_info, | |
2407 | svm->vmcb->control.exit_int_info_err); | |
2408 | ||
410e4d57 JR |
2409 | vmexit = nested_svm_exit_special(svm); |
2410 | ||
2411 | if (vmexit == NESTED_EXIT_CONTINUE) | |
2412 | vmexit = nested_svm_exit_handled(svm); | |
2413 | ||
2414 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 2415 | return 1; |
cf74a78b AG |
2416 | } |
2417 | ||
a5c3832d JR |
2418 | svm_complete_interrupts(svm); |
2419 | ||
888f9f3e | 2420 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK)) |
709ddebf | 2421 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
888f9f3e | 2422 | if (npt_enabled) |
709ddebf | 2423 | vcpu->arch.cr3 = svm->vmcb->save.cr3; |
04d2cc77 AK |
2424 | |
2425 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
2426 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2427 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2428 | = svm->vmcb->control.exit_code; | |
2429 | return 0; | |
2430 | } | |
2431 | ||
a2fa3e9f | 2432 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 2433 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
fe8e7f83 | 2434 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH) |
6aa8b732 AK |
2435 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
2436 | "exit_code 0x%x\n", | |
b8688d51 | 2437 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
2438 | exit_code); |
2439 | ||
9d8f549d | 2440 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 2441 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 2442 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 2443 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
2444 | return 0; |
2445 | } | |
2446 | ||
851ba692 | 2447 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
2448 | } |
2449 | ||
2450 | static void reload_tss(struct kvm_vcpu *vcpu) | |
2451 | { | |
2452 | int cpu = raw_smp_processor_id(); | |
2453 | ||
0fe1e009 TH |
2454 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
2455 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
2456 | load_TR_desc(); |
2457 | } | |
2458 | ||
e756fc62 | 2459 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
2460 | { |
2461 | int cpu = raw_smp_processor_id(); | |
2462 | ||
0fe1e009 | 2463 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 2464 | |
a2fa3e9f | 2465 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4b656b12 | 2466 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
2467 | if (svm->asid_generation != sd->asid_generation) |
2468 | new_asid(svm, sd); | |
6aa8b732 AK |
2469 | } |
2470 | ||
95ba8273 GN |
2471 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
2472 | { | |
2473 | struct vcpu_svm *svm = to_svm(vcpu); | |
2474 | ||
2475 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
2476 | vcpu->arch.hflags |= HF_NMI_MASK; | |
2477 | svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET); | |
2478 | ++vcpu->stat.nmi_injections; | |
2479 | } | |
6aa8b732 | 2480 | |
85f455f7 | 2481 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
2482 | { |
2483 | struct vmcb_control_area *control; | |
2484 | ||
229456fc | 2485 | trace_kvm_inj_virq(irq); |
af9ca2d7 | 2486 | |
fa89a817 | 2487 | ++svm->vcpu.stat.irq_injections; |
e756fc62 | 2488 | control = &svm->vmcb->control; |
85f455f7 | 2489 | control->int_vector = irq; |
6aa8b732 AK |
2490 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
2491 | control->int_ctl |= V_IRQ_MASK | | |
2492 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
2493 | } | |
2494 | ||
66fd3f7f | 2495 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
2496 | { |
2497 | struct vcpu_svm *svm = to_svm(vcpu); | |
2498 | ||
2af9194d | 2499 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 2500 | |
219b65dc AG |
2501 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
2502 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
2503 | } |
2504 | ||
95ba8273 | 2505 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
2506 | { |
2507 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 2508 | |
95ba8273 | 2509 | if (irr == -1) |
aaacfc9a JR |
2510 | return; |
2511 | ||
95ba8273 GN |
2512 | if (tpr >= irr) |
2513 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
2514 | } | |
aaacfc9a | 2515 | |
95ba8273 GN |
2516 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
2517 | { | |
2518 | struct vcpu_svm *svm = to_svm(vcpu); | |
2519 | struct vmcb *vmcb = svm->vmcb; | |
2520 | return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
2521 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
aaacfc9a JR |
2522 | } |
2523 | ||
3cfc3092 JK |
2524 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
2525 | { | |
2526 | struct vcpu_svm *svm = to_svm(vcpu); | |
2527 | ||
2528 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
2529 | } | |
2530 | ||
2531 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
2532 | { | |
2533 | struct vcpu_svm *svm = to_svm(vcpu); | |
2534 | ||
2535 | if (masked) { | |
2536 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
2537 | svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET); | |
2538 | } else { | |
2539 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
2540 | svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET); | |
2541 | } | |
2542 | } | |
2543 | ||
78646121 GN |
2544 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
2545 | { | |
2546 | struct vcpu_svm *svm = to_svm(vcpu); | |
2547 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
2548 | int ret; |
2549 | ||
2550 | if (!gif_set(svm) || | |
2551 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
2552 | return 0; | |
2553 | ||
2554 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
2555 | ||
2556 | if (is_nested(svm)) | |
2557 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); | |
2558 | ||
2559 | return ret; | |
78646121 GN |
2560 | } |
2561 | ||
9222be18 | 2562 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 2563 | { |
219b65dc | 2564 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc AG |
2565 | |
2566 | nested_svm_intr(svm); | |
2567 | ||
2568 | /* In case GIF=0 we can't rely on the CPU to tell us when | |
2569 | * GIF becomes 1, because that's a separate STGI/VMRUN intercept. | |
2570 | * The next time we get that intercept, this function will be | |
2571 | * called again though and we'll get the vintr intercept. */ | |
2af9194d | 2572 | if (gif_set(svm)) { |
219b65dc AG |
2573 | svm_set_vintr(svm); |
2574 | svm_inject_irq(svm, 0x0); | |
2575 | } | |
85f455f7 ED |
2576 | } |
2577 | ||
95ba8273 | 2578 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 2579 | { |
04d2cc77 | 2580 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 2581 | |
44c11430 GN |
2582 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
2583 | == HF_NMI_MASK) | |
2584 | return; /* IRET will cause a vm exit */ | |
2585 | ||
2586 | /* Something prevents NMI from been injected. Single step over | |
2587 | possible problem (IRET or exception injection or interrupt | |
2588 | shadow) */ | |
6be7d306 | 2589 | svm->nmi_singlestep = true; |
44c11430 GN |
2590 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
2591 | update_db_intercept(vcpu); | |
c1150d8c DL |
2592 | } |
2593 | ||
cbc94022 IE |
2594 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2595 | { | |
2596 | return 0; | |
2597 | } | |
2598 | ||
d9e368d6 AK |
2599 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
2600 | { | |
2601 | force_new_asid(vcpu); | |
2602 | } | |
2603 | ||
04d2cc77 AK |
2604 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
2605 | { | |
2606 | } | |
2607 | ||
d7bf8221 JR |
2608 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
2609 | { | |
2610 | struct vcpu_svm *svm = to_svm(vcpu); | |
2611 | ||
2612 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
2613 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
615d5193 | 2614 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
2615 | } |
2616 | } | |
2617 | ||
649d6864 JR |
2618 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
2619 | { | |
2620 | struct vcpu_svm *svm = to_svm(vcpu); | |
2621 | u64 cr8; | |
2622 | ||
649d6864 JR |
2623 | cr8 = kvm_get_cr8(vcpu); |
2624 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
2625 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
2626 | } | |
2627 | ||
9222be18 GN |
2628 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
2629 | { | |
2630 | u8 vector; | |
2631 | int type; | |
2632 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
2633 | ||
44c11430 GN |
2634 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) |
2635 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); | |
2636 | ||
9222be18 GN |
2637 | svm->vcpu.arch.nmi_injected = false; |
2638 | kvm_clear_exception_queue(&svm->vcpu); | |
2639 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2640 | ||
2641 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
2642 | return; | |
2643 | ||
2644 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; | |
2645 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
2646 | ||
2647 | switch (type) { | |
2648 | case SVM_EXITINTINFO_TYPE_NMI: | |
2649 | svm->vcpu.arch.nmi_injected = true; | |
2650 | break; | |
2651 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
2652 | /* In case of software exception do not reinject an exception | |
2653 | vector, but re-execute and instruction instead */ | |
219b65dc AG |
2654 | if (is_nested(svm)) |
2655 | break; | |
66fd3f7f | 2656 | if (kvm_exception_is_soft(vector)) |
9222be18 GN |
2657 | break; |
2658 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { | |
2659 | u32 err = svm->vmcb->control.exit_int_info_err; | |
2660 | kvm_queue_exception_e(&svm->vcpu, vector, err); | |
2661 | ||
2662 | } else | |
2663 | kvm_queue_exception(&svm->vcpu, vector); | |
2664 | break; | |
2665 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 2666 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
2667 | break; |
2668 | default: | |
2669 | break; | |
2670 | } | |
2671 | } | |
2672 | ||
80e31d4f AK |
2673 | #ifdef CONFIG_X86_64 |
2674 | #define R "r" | |
2675 | #else | |
2676 | #define R "e" | |
2677 | #endif | |
2678 | ||
851ba692 | 2679 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 2680 | { |
a2fa3e9f | 2681 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2682 | u16 fs_selector; |
2683 | u16 gs_selector; | |
2684 | u16 ldt_selector; | |
d9e368d6 | 2685 | |
cd3ff653 JR |
2686 | /* |
2687 | * A vmexit emulation is required before the vcpu can be executed | |
2688 | * again. | |
2689 | */ | |
2690 | if (unlikely(svm->nested.exit_required)) | |
2691 | return; | |
2692 | ||
5fdbf976 MT |
2693 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
2694 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
2695 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
2696 | ||
e756fc62 | 2697 | pre_svm_run(svm); |
6aa8b732 | 2698 | |
649d6864 JR |
2699 | sync_lapic_to_cr8(vcpu); |
2700 | ||
6aa8b732 | 2701 | save_host_msrs(vcpu); |
d6e88aec AK |
2702 | fs_selector = kvm_read_fs(); |
2703 | gs_selector = kvm_read_gs(); | |
2704 | ldt_selector = kvm_read_ldt(); | |
cda0ffdd | 2705 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
2706 | /* required for live migration with NPT */ |
2707 | if (npt_enabled) | |
2708 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 2709 | |
04d2cc77 AK |
2710 | clgi(); |
2711 | ||
2712 | local_irq_enable(); | |
36241b8c | 2713 | |
6aa8b732 | 2714 | asm volatile ( |
80e31d4f AK |
2715 | "push %%"R"bp; \n\t" |
2716 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
2717 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
2718 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
2719 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
2720 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
2721 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 2722 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2723 | "mov %c[r8](%[svm]), %%r8 \n\t" |
2724 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
2725 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
2726 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
2727 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
2728 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
2729 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
2730 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
2731 | #endif |
2732 | ||
6aa8b732 | 2733 | /* Enter guest mode */ |
80e31d4f AK |
2734 | "push %%"R"ax \n\t" |
2735 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
2736 | __ex(SVM_VMLOAD) "\n\t" |
2737 | __ex(SVM_VMRUN) "\n\t" | |
2738 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 2739 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
2740 | |
2741 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
2742 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
2743 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
2744 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
2745 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
2746 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
2747 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 2748 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2749 | "mov %%r8, %c[r8](%[svm]) \n\t" |
2750 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
2751 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
2752 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
2753 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
2754 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
2755 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
2756 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 2757 | #endif |
80e31d4f | 2758 | "pop %%"R"bp" |
6aa8b732 | 2759 | : |
fb3f0f51 | 2760 | : [svm]"a"(svm), |
6aa8b732 | 2761 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
2762 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
2763 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
2764 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
2765 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
2766 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
2767 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 2768 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2769 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
2770 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
2771 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
2772 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
2773 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
2774 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
2775 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
2776 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 2777 | #endif |
54a08c04 | 2778 | : "cc", "memory" |
80e31d4f | 2779 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 2780 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
2781 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
2782 | #endif | |
2783 | ); | |
6aa8b732 | 2784 | |
ad312c7c | 2785 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5fdbf976 MT |
2786 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
2787 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
2788 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
6aa8b732 | 2789 | |
d6e88aec AK |
2790 | kvm_load_fs(fs_selector); |
2791 | kvm_load_gs(gs_selector); | |
2792 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
2793 | load_host_msrs(vcpu); |
2794 | ||
2795 | reload_tss(vcpu); | |
2796 | ||
56ba47dd AK |
2797 | local_irq_disable(); |
2798 | ||
2799 | stgi(); | |
2800 | ||
d7bf8221 JR |
2801 | sync_cr8_to_lapic(vcpu); |
2802 | ||
a2fa3e9f | 2803 | svm->next_rip = 0; |
9222be18 | 2804 | |
6de4f3ad AK |
2805 | if (npt_enabled) { |
2806 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
2807 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
2808 | } | |
6aa8b732 AK |
2809 | } |
2810 | ||
80e31d4f AK |
2811 | #undef R |
2812 | ||
6aa8b732 AK |
2813 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
2814 | { | |
a2fa3e9f GH |
2815 | struct vcpu_svm *svm = to_svm(vcpu); |
2816 | ||
709ddebf JR |
2817 | if (npt_enabled) { |
2818 | svm->vmcb->control.nested_cr3 = root; | |
2819 | force_new_asid(vcpu); | |
2820 | return; | |
2821 | } | |
2822 | ||
a2fa3e9f | 2823 | svm->vmcb->save.cr3 = root; |
6aa8b732 AK |
2824 | force_new_asid(vcpu); |
2825 | } | |
2826 | ||
6aa8b732 AK |
2827 | static int is_disabled(void) |
2828 | { | |
6031a61c JR |
2829 | u64 vm_cr; |
2830 | ||
2831 | rdmsrl(MSR_VM_CR, vm_cr); | |
2832 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
2833 | return 1; | |
2834 | ||
6aa8b732 AK |
2835 | return 0; |
2836 | } | |
2837 | ||
102d8325 IM |
2838 | static void |
2839 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2840 | { | |
2841 | /* | |
2842 | * Patch in the VMMCALL instruction: | |
2843 | */ | |
2844 | hypercall[0] = 0x0f; | |
2845 | hypercall[1] = 0x01; | |
2846 | hypercall[2] = 0xd9; | |
102d8325 IM |
2847 | } |
2848 | ||
002c7f7c YS |
2849 | static void svm_check_processor_compat(void *rtn) |
2850 | { | |
2851 | *(int *)rtn = 0; | |
2852 | } | |
2853 | ||
774ead3a AK |
2854 | static bool svm_cpu_has_accelerated_tpr(void) |
2855 | { | |
2856 | return false; | |
2857 | } | |
2858 | ||
67253af5 SY |
2859 | static int get_npt_level(void) |
2860 | { | |
2861 | #ifdef CONFIG_X86_64 | |
2862 | return PT64_ROOT_LEVEL; | |
2863 | #else | |
2864 | return PT32E_ROOT_LEVEL; | |
2865 | #endif | |
2866 | } | |
2867 | ||
4b12f0de | 2868 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
2869 | { |
2870 | return 0; | |
2871 | } | |
2872 | ||
0e851880 SY |
2873 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
2874 | { | |
2875 | } | |
2876 | ||
229456fc MT |
2877 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
2878 | { SVM_EXIT_READ_CR0, "read_cr0" }, | |
2879 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
2880 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
2881 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
2882 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
2883 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
2884 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
2885 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
2886 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
2887 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
2888 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
2889 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
2890 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
2891 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
2892 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
2893 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
2894 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
2895 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
2896 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, | |
2897 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
2898 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
2899 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
2900 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
2901 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
2902 | { SVM_EXIT_INTR, "interrupt" }, | |
2903 | { SVM_EXIT_NMI, "nmi" }, | |
2904 | { SVM_EXIT_SMI, "smi" }, | |
2905 | { SVM_EXIT_INIT, "init" }, | |
2906 | { SVM_EXIT_VINTR, "vintr" }, | |
2907 | { SVM_EXIT_CPUID, "cpuid" }, | |
2908 | { SVM_EXIT_INVD, "invd" }, | |
2909 | { SVM_EXIT_HLT, "hlt" }, | |
2910 | { SVM_EXIT_INVLPG, "invlpg" }, | |
2911 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
2912 | { SVM_EXIT_IOIO, "io" }, | |
2913 | { SVM_EXIT_MSR, "msr" }, | |
2914 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
2915 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
2916 | { SVM_EXIT_VMRUN, "vmrun" }, | |
2917 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
2918 | { SVM_EXIT_VMLOAD, "vmload" }, | |
2919 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
2920 | { SVM_EXIT_STGI, "stgi" }, | |
2921 | { SVM_EXIT_CLGI, "clgi" }, | |
2922 | { SVM_EXIT_SKINIT, "skinit" }, | |
2923 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
2924 | { SVM_EXIT_MONITOR, "monitor" }, | |
2925 | { SVM_EXIT_MWAIT, "mwait" }, | |
2926 | { SVM_EXIT_NPF, "npf" }, | |
2927 | { -1, NULL } | |
2928 | }; | |
2929 | ||
17cc3935 | 2930 | static int svm_get_lpage_level(void) |
344f414f | 2931 | { |
17cc3935 | 2932 | return PT_PDPE_LEVEL; |
344f414f JR |
2933 | } |
2934 | ||
4e47c7a6 SY |
2935 | static bool svm_rdtscp_supported(void) |
2936 | { | |
2937 | return false; | |
2938 | } | |
2939 | ||
02daab21 AK |
2940 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
2941 | { | |
2942 | struct vcpu_svm *svm = to_svm(vcpu); | |
2943 | ||
d225157b | 2944 | update_cr0_intercept(svm); |
02daab21 | 2945 | svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR; |
02daab21 AK |
2946 | } |
2947 | ||
cbdd1bea | 2948 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
2949 | .cpu_has_kvm_support = has_svm, |
2950 | .disabled_by_bios = is_disabled, | |
2951 | .hardware_setup = svm_hardware_setup, | |
2952 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 2953 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
2954 | .hardware_enable = svm_hardware_enable, |
2955 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 2956 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
2957 | |
2958 | .vcpu_create = svm_create_vcpu, | |
2959 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 2960 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 2961 | |
04d2cc77 | 2962 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
2963 | .vcpu_load = svm_vcpu_load, |
2964 | .vcpu_put = svm_vcpu_put, | |
2965 | ||
2966 | .set_guest_debug = svm_guest_debug, | |
2967 | .get_msr = svm_get_msr, | |
2968 | .set_msr = svm_set_msr, | |
2969 | .get_segment_base = svm_get_segment_base, | |
2970 | .get_segment = svm_get_segment, | |
2971 | .set_segment = svm_set_segment, | |
2e4d2653 | 2972 | .get_cpl = svm_get_cpl, |
1747fb71 | 2973 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 2974 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
25c4c276 | 2975 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 2976 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
2977 | .set_cr3 = svm_set_cr3, |
2978 | .set_cr4 = svm_set_cr4, | |
2979 | .set_efer = svm_set_efer, | |
2980 | .get_idt = svm_get_idt, | |
2981 | .set_idt = svm_set_idt, | |
2982 | .get_gdt = svm_get_gdt, | |
2983 | .set_gdt = svm_set_gdt, | |
2984 | .get_dr = svm_get_dr, | |
2985 | .set_dr = svm_set_dr, | |
6de4f3ad | 2986 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
2987 | .get_rflags = svm_get_rflags, |
2988 | .set_rflags = svm_set_rflags, | |
6b52d186 | 2989 | .fpu_activate = svm_fpu_activate, |
02daab21 | 2990 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 2991 | |
6aa8b732 | 2992 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 2993 | |
6aa8b732 | 2994 | .run = svm_vcpu_run, |
04d2cc77 | 2995 | .handle_exit = handle_exit, |
6aa8b732 | 2996 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
2997 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
2998 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 2999 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 3000 | .set_irq = svm_set_irq, |
95ba8273 | 3001 | .set_nmi = svm_inject_nmi, |
298101da | 3002 | .queue_exception = svm_queue_exception, |
78646121 | 3003 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 3004 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
3005 | .get_nmi_mask = svm_get_nmi_mask, |
3006 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
3007 | .enable_nmi_window = enable_nmi_window, |
3008 | .enable_irq_window = enable_irq_window, | |
3009 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
3010 | |
3011 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 3012 | .get_tdp_level = get_npt_level, |
4b12f0de | 3013 | .get_mt_mask = svm_get_mt_mask, |
229456fc MT |
3014 | |
3015 | .exit_reasons_str = svm_exit_reasons_str, | |
17cc3935 | 3016 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
3017 | |
3018 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
3019 | |
3020 | .rdtscp_supported = svm_rdtscp_supported, | |
6aa8b732 AK |
3021 | }; |
3022 | ||
3023 | static int __init svm_init(void) | |
3024 | { | |
cb498ea2 | 3025 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 3026 | THIS_MODULE); |
6aa8b732 AK |
3027 | } |
3028 | ||
3029 | static void __exit svm_exit(void) | |
3030 | { | |
cb498ea2 | 3031 | kvm_exit(); |
6aa8b732 AK |
3032 | } |
3033 | ||
3034 | module_init(svm_init) | |
3035 | module_exit(svm_exit) |