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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
66f7b72e | 23 | #include "cpuid.h" |
25462f7f | 24 | #include "pmu.h" |
e495606d | 25 | |
6aa8b732 | 26 | #include <linux/module.h> |
ae759544 | 27 | #include <linux/mod_devicetable.h> |
9d8f549d | 28 | #include <linux/kernel.h> |
6aa8b732 AK |
29 | #include <linux/vmalloc.h> |
30 | #include <linux/highmem.h> | |
e8edc6e0 | 31 | #include <linux/sched.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
6aa8b732 | 34 | |
1018faa6 | 35 | #include <asm/perf_event.h> |
67ec6607 | 36 | #include <asm/tlbflush.h> |
e495606d | 37 | #include <asm/desc.h> |
facb0139 | 38 | #include <asm/debugreg.h> |
631bc487 | 39 | #include <asm/kvm_para.h> |
6aa8b732 | 40 | |
63d1142f | 41 | #include <asm/virtext.h> |
229456fc | 42 | #include "trace.h" |
63d1142f | 43 | |
4ecac3fd AK |
44 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
45 | ||
6aa8b732 AK |
46 | MODULE_AUTHOR("Qumranet"); |
47 | MODULE_LICENSE("GPL"); | |
48 | ||
ae759544 JT |
49 | static const struct x86_cpu_id svm_cpu_id[] = { |
50 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
51 | {} | |
52 | }; | |
53 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
54 | ||
6aa8b732 AK |
55 | #define IOPM_ALLOC_ORDER 2 |
56 | #define MSRPM_ALLOC_ORDER 1 | |
57 | ||
6aa8b732 AK |
58 | #define SEG_TYPE_LDT 2 |
59 | #define SEG_TYPE_BUSY_TSS16 3 | |
60 | ||
6bc31bdc AP |
61 | #define SVM_FEATURE_NPT (1 << 0) |
62 | #define SVM_FEATURE_LBRV (1 << 1) | |
63 | #define SVM_FEATURE_SVML (1 << 2) | |
64 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
65 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
66 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
67 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
68 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 69 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 70 | |
410e4d57 JR |
71 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
72 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
73 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
74 | ||
24e09cbf JR |
75 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
76 | ||
fbc0db76 | 77 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
78 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
79 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 80 | |
67ec6607 JR |
81 | static bool erratum_383_found __read_mostly; |
82 | ||
6c8166a7 AK |
83 | static const u32 host_save_user_msrs[] = { |
84 | #ifdef CONFIG_X86_64 | |
85 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
86 | MSR_FS_BASE, | |
87 | #endif | |
88 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
89 | }; | |
90 | ||
91 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
92 | ||
93 | struct kvm_vcpu; | |
94 | ||
e6aa9abd JR |
95 | struct nested_state { |
96 | struct vmcb *hsave; | |
97 | u64 hsave_msr; | |
4a810181 | 98 | u64 vm_cr_msr; |
e6aa9abd JR |
99 | u64 vmcb; |
100 | ||
101 | /* These are the merged vectors */ | |
102 | u32 *msrpm; | |
103 | ||
104 | /* gpa pointers to the real vectors */ | |
105 | u64 vmcb_msrpm; | |
ce2ac085 | 106 | u64 vmcb_iopm; |
aad42c64 | 107 | |
cd3ff653 JR |
108 | /* A VMEXIT is required but not yet emulated */ |
109 | bool exit_required; | |
110 | ||
aad42c64 | 111 | /* cache for intercepts of the guest */ |
4ee546b4 | 112 | u32 intercept_cr; |
3aed041a | 113 | u32 intercept_dr; |
aad42c64 JR |
114 | u32 intercept_exceptions; |
115 | u64 intercept; | |
116 | ||
5bd2edc3 JR |
117 | /* Nested Paging related state */ |
118 | u64 nested_cr3; | |
e6aa9abd JR |
119 | }; |
120 | ||
323c3d80 JR |
121 | #define MSRPM_OFFSETS 16 |
122 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
123 | ||
2b036c6b BO |
124 | /* |
125 | * Set osvw_len to higher value when updated Revision Guides | |
126 | * are published and we know what the new status bits are | |
127 | */ | |
128 | static uint64_t osvw_len = 4, osvw_status; | |
129 | ||
6c8166a7 AK |
130 | struct vcpu_svm { |
131 | struct kvm_vcpu vcpu; | |
132 | struct vmcb *vmcb; | |
133 | unsigned long vmcb_pa; | |
134 | struct svm_cpu_data *svm_data; | |
135 | uint64_t asid_generation; | |
136 | uint64_t sysenter_esp; | |
137 | uint64_t sysenter_eip; | |
138 | ||
139 | u64 next_rip; | |
140 | ||
141 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 142 | struct { |
dacccfdd AK |
143 | u16 fs; |
144 | u16 gs; | |
145 | u16 ldt; | |
afe9e66f AK |
146 | u64 gs_base; |
147 | } host; | |
6c8166a7 AK |
148 | |
149 | u32 *msrpm; | |
6c8166a7 | 150 | |
bd3d1ec3 AK |
151 | ulong nmi_iret_rip; |
152 | ||
e6aa9abd | 153 | struct nested_state nested; |
6be7d306 JK |
154 | |
155 | bool nmi_singlestep; | |
66b7138f JK |
156 | |
157 | unsigned int3_injected; | |
158 | unsigned long int3_rip; | |
631bc487 | 159 | u32 apf_reason; |
fbc0db76 | 160 | |
6092d3d3 JR |
161 | /* cached guest cpuid flags for faster access */ |
162 | bool nrips_enabled : 1; | |
6c8166a7 AK |
163 | }; |
164 | ||
fbc0db76 JR |
165 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
166 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
167 | ||
455716fa JR |
168 | #define MSR_INVALID 0xffffffffU |
169 | ||
09941fbb | 170 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
171 | u32 index; /* Index of the MSR */ |
172 | bool always; /* True if intercept is always on */ | |
173 | } direct_access_msrs[] = { | |
8c06585d | 174 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
175 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
176 | #ifdef CONFIG_X86_64 | |
177 | { .index = MSR_GS_BASE, .always = true }, | |
178 | { .index = MSR_FS_BASE, .always = true }, | |
179 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
180 | { .index = MSR_LSTAR, .always = true }, | |
181 | { .index = MSR_CSTAR, .always = true }, | |
182 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
183 | #endif | |
184 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
185 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
186 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
187 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
188 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
189 | }; |
190 | ||
709ddebf JR |
191 | /* enable NPT for AMD64 and X86 with PAE */ |
192 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
193 | static bool npt_enabled = true; | |
194 | #else | |
e0231715 | 195 | static bool npt_enabled; |
709ddebf | 196 | #endif |
6c7dac72 | 197 | |
e2358851 DB |
198 | /* allow nested paging (virtualized MMU) for all guests */ |
199 | static int npt = true; | |
6c7dac72 | 200 | module_param(npt, int, S_IRUGO); |
e3da3acd | 201 | |
e2358851 DB |
202 | /* allow nested virtualization in KVM/SVM */ |
203 | static int nested = true; | |
236de055 AG |
204 | module_param(nested, int, S_IRUGO); |
205 | ||
79a8059d | 206 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
44874f84 | 207 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 208 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 209 | |
410e4d57 | 210 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 211 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 212 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
213 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
214 | bool has_error_code, u32 error_code); | |
215 | ||
8d28fec4 | 216 | enum { |
116a0a23 JR |
217 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
218 | pause filter count */ | |
f56838e4 | 219 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 220 | VMCB_ASID, /* ASID */ |
decdbf6a | 221 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 222 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 223 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 224 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 225 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 226 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 227 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 228 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
229 | VMCB_DIRTY_MAX, |
230 | }; | |
231 | ||
0574dec0 JR |
232 | /* TPR and CR2 are always written before VMRUN */ |
233 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
234 | |
235 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
236 | { | |
237 | vmcb->control.clean = 0; | |
238 | } | |
239 | ||
240 | static inline void mark_all_clean(struct vmcb *vmcb) | |
241 | { | |
242 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
243 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
244 | } | |
245 | ||
246 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
247 | { | |
248 | vmcb->control.clean &= ~(1 << bit); | |
249 | } | |
250 | ||
a2fa3e9f GH |
251 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
252 | { | |
fb3f0f51 | 253 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
254 | } |
255 | ||
384c6368 JR |
256 | static void recalc_intercepts(struct vcpu_svm *svm) |
257 | { | |
258 | struct vmcb_control_area *c, *h; | |
259 | struct nested_state *g; | |
260 | ||
116a0a23 JR |
261 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
262 | ||
384c6368 JR |
263 | if (!is_guest_mode(&svm->vcpu)) |
264 | return; | |
265 | ||
266 | c = &svm->vmcb->control; | |
267 | h = &svm->nested.hsave->control; | |
268 | g = &svm->nested; | |
269 | ||
4ee546b4 | 270 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 271 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
272 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
273 | c->intercept = h->intercept | g->intercept; | |
274 | } | |
275 | ||
4ee546b4 RJ |
276 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
277 | { | |
278 | if (is_guest_mode(&svm->vcpu)) | |
279 | return svm->nested.hsave; | |
280 | else | |
281 | return svm->vmcb; | |
282 | } | |
283 | ||
284 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
285 | { | |
286 | struct vmcb *vmcb = get_host_vmcb(svm); | |
287 | ||
288 | vmcb->control.intercept_cr |= (1U << bit); | |
289 | ||
290 | recalc_intercepts(svm); | |
291 | } | |
292 | ||
293 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
294 | { | |
295 | struct vmcb *vmcb = get_host_vmcb(svm); | |
296 | ||
297 | vmcb->control.intercept_cr &= ~(1U << bit); | |
298 | ||
299 | recalc_intercepts(svm); | |
300 | } | |
301 | ||
302 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
303 | { | |
304 | struct vmcb *vmcb = get_host_vmcb(svm); | |
305 | ||
306 | return vmcb->control.intercept_cr & (1U << bit); | |
307 | } | |
308 | ||
5315c716 | 309 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
310 | { |
311 | struct vmcb *vmcb = get_host_vmcb(svm); | |
312 | ||
5315c716 PB |
313 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
314 | | (1 << INTERCEPT_DR1_READ) | |
315 | | (1 << INTERCEPT_DR2_READ) | |
316 | | (1 << INTERCEPT_DR3_READ) | |
317 | | (1 << INTERCEPT_DR4_READ) | |
318 | | (1 << INTERCEPT_DR5_READ) | |
319 | | (1 << INTERCEPT_DR6_READ) | |
320 | | (1 << INTERCEPT_DR7_READ) | |
321 | | (1 << INTERCEPT_DR0_WRITE) | |
322 | | (1 << INTERCEPT_DR1_WRITE) | |
323 | | (1 << INTERCEPT_DR2_WRITE) | |
324 | | (1 << INTERCEPT_DR3_WRITE) | |
325 | | (1 << INTERCEPT_DR4_WRITE) | |
326 | | (1 << INTERCEPT_DR5_WRITE) | |
327 | | (1 << INTERCEPT_DR6_WRITE) | |
328 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
329 | |
330 | recalc_intercepts(svm); | |
331 | } | |
332 | ||
5315c716 | 333 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
334 | { |
335 | struct vmcb *vmcb = get_host_vmcb(svm); | |
336 | ||
5315c716 | 337 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
338 | |
339 | recalc_intercepts(svm); | |
340 | } | |
341 | ||
18c918c5 JR |
342 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
343 | { | |
344 | struct vmcb *vmcb = get_host_vmcb(svm); | |
345 | ||
346 | vmcb->control.intercept_exceptions |= (1U << bit); | |
347 | ||
348 | recalc_intercepts(svm); | |
349 | } | |
350 | ||
351 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
352 | { | |
353 | struct vmcb *vmcb = get_host_vmcb(svm); | |
354 | ||
355 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
356 | ||
357 | recalc_intercepts(svm); | |
358 | } | |
359 | ||
8a05a1b8 JR |
360 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
361 | { | |
362 | struct vmcb *vmcb = get_host_vmcb(svm); | |
363 | ||
364 | vmcb->control.intercept |= (1ULL << bit); | |
365 | ||
366 | recalc_intercepts(svm); | |
367 | } | |
368 | ||
369 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
370 | { | |
371 | struct vmcb *vmcb = get_host_vmcb(svm); | |
372 | ||
373 | vmcb->control.intercept &= ~(1ULL << bit); | |
374 | ||
375 | recalc_intercepts(svm); | |
376 | } | |
377 | ||
2af9194d JR |
378 | static inline void enable_gif(struct vcpu_svm *svm) |
379 | { | |
380 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
381 | } | |
382 | ||
383 | static inline void disable_gif(struct vcpu_svm *svm) | |
384 | { | |
385 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
386 | } | |
387 | ||
388 | static inline bool gif_set(struct vcpu_svm *svm) | |
389 | { | |
390 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
391 | } | |
392 | ||
4866d5e3 | 393 | static unsigned long iopm_base; |
6aa8b732 AK |
394 | |
395 | struct kvm_ldttss_desc { | |
396 | u16 limit0; | |
397 | u16 base0; | |
e0231715 JR |
398 | unsigned base1:8, type:5, dpl:2, p:1; |
399 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
400 | u32 base3; |
401 | u32 zero1; | |
402 | } __attribute__((packed)); | |
403 | ||
404 | struct svm_cpu_data { | |
405 | int cpu; | |
406 | ||
5008fdf5 AK |
407 | u64 asid_generation; |
408 | u32 max_asid; | |
409 | u32 next_asid; | |
6aa8b732 AK |
410 | struct kvm_ldttss_desc *tss_desc; |
411 | ||
412 | struct page *save_area; | |
413 | }; | |
414 | ||
415 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
416 | ||
417 | struct svm_init_data { | |
418 | int cpu; | |
419 | int r; | |
420 | }; | |
421 | ||
09941fbb | 422 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 423 | |
9d8f549d | 424 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
425 | #define MSRS_RANGE_SIZE 2048 |
426 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
427 | ||
455716fa JR |
428 | static u32 svm_msrpm_offset(u32 msr) |
429 | { | |
430 | u32 offset; | |
431 | int i; | |
432 | ||
433 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
434 | if (msr < msrpm_ranges[i] || | |
435 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
436 | continue; | |
437 | ||
438 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
439 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
440 | ||
441 | /* Now we have the u8 offset - but need the u32 offset */ | |
442 | return offset / 4; | |
443 | } | |
444 | ||
445 | /* MSR not in any range */ | |
446 | return MSR_INVALID; | |
447 | } | |
448 | ||
6aa8b732 AK |
449 | #define MAX_INST_SIZE 15 |
450 | ||
6aa8b732 AK |
451 | static inline void clgi(void) |
452 | { | |
4ecac3fd | 453 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
454 | } |
455 | ||
456 | static inline void stgi(void) | |
457 | { | |
4ecac3fd | 458 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
459 | } |
460 | ||
461 | static inline void invlpga(unsigned long addr, u32 asid) | |
462 | { | |
e0231715 | 463 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
464 | } |
465 | ||
4b16184c JR |
466 | static int get_npt_level(void) |
467 | { | |
468 | #ifdef CONFIG_X86_64 | |
469 | return PT64_ROOT_LEVEL; | |
470 | #else | |
471 | return PT32E_ROOT_LEVEL; | |
472 | #endif | |
473 | } | |
474 | ||
6aa8b732 AK |
475 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
476 | { | |
6dc696d4 | 477 | vcpu->arch.efer = efer; |
709ddebf | 478 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 479 | efer &= ~EFER_LME; |
6aa8b732 | 480 | |
9962d032 | 481 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 482 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
483 | } |
484 | ||
6aa8b732 AK |
485 | static int is_external_interrupt(u32 info) |
486 | { | |
487 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
488 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
489 | } | |
490 | ||
37ccdcbe | 491 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
492 | { |
493 | struct vcpu_svm *svm = to_svm(vcpu); | |
494 | u32 ret = 0; | |
495 | ||
496 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
497 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
498 | return ret; | |
2809f5d2 GC |
499 | } |
500 | ||
501 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
502 | { | |
503 | struct vcpu_svm *svm = to_svm(vcpu); | |
504 | ||
505 | if (mask == 0) | |
506 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
507 | else | |
508 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
509 | ||
510 | } | |
511 | ||
6aa8b732 AK |
512 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
513 | { | |
a2fa3e9f GH |
514 | struct vcpu_svm *svm = to_svm(vcpu); |
515 | ||
f104765b | 516 | if (svm->vmcb->control.next_rip != 0) { |
d2922422 | 517 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 518 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 519 | } |
6bc31bdc | 520 | |
a2fa3e9f | 521 | if (!svm->next_rip) { |
51d8b661 | 522 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
523 | EMULATE_DONE) |
524 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
525 | return; |
526 | } | |
5fdbf976 MT |
527 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
528 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
529 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 530 | |
5fdbf976 | 531 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 532 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
533 | } |
534 | ||
116a4752 | 535 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
536 | bool has_error_code, u32 error_code, |
537 | bool reinject) | |
116a4752 JK |
538 | { |
539 | struct vcpu_svm *svm = to_svm(vcpu); | |
540 | ||
e0231715 JR |
541 | /* |
542 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
543 | * handle the exception | |
544 | */ | |
ce7ddec4 JR |
545 | if (!reinject && |
546 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
547 | return; |
548 | ||
2a6b20b8 | 549 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
550 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
551 | ||
552 | /* | |
553 | * For guest debugging where we have to reinject #BP if some | |
554 | * INT3 is guest-owned: | |
555 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
556 | * raises a fault that is not intercepted. Still better than | |
557 | * failing in all cases. | |
558 | */ | |
559 | skip_emulated_instruction(&svm->vcpu); | |
560 | rip = kvm_rip_read(&svm->vcpu); | |
561 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
562 | svm->int3_injected = rip - old_rip; | |
563 | } | |
564 | ||
116a4752 JK |
565 | svm->vmcb->control.event_inj = nr |
566 | | SVM_EVTINJ_VALID | |
567 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
568 | | SVM_EVTINJ_TYPE_EXEPT; | |
569 | svm->vmcb->control.event_inj_err = error_code; | |
570 | } | |
571 | ||
67ec6607 JR |
572 | static void svm_init_erratum_383(void) |
573 | { | |
574 | u32 low, high; | |
575 | int err; | |
576 | u64 val; | |
577 | ||
e6ee94d5 | 578 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
579 | return; |
580 | ||
581 | /* Use _safe variants to not break nested virtualization */ | |
582 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
583 | if (err) | |
584 | return; | |
585 | ||
586 | val |= (1ULL << 47); | |
587 | ||
588 | low = lower_32_bits(val); | |
589 | high = upper_32_bits(val); | |
590 | ||
591 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
592 | ||
593 | erratum_383_found = true; | |
594 | } | |
595 | ||
2b036c6b BO |
596 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
597 | { | |
598 | /* | |
599 | * Guests should see errata 400 and 415 as fixed (assuming that | |
600 | * HLT and IO instructions are intercepted). | |
601 | */ | |
602 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
603 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
604 | ||
605 | /* | |
606 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
607 | * all osvw.status bits inside that length, including bit 0 (which is | |
608 | * reserved for erratum 298), are valid. However, if host processor's | |
609 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
610 | * be conservative here and therefore we tell the guest that erratum 298 | |
611 | * is present (because we really don't know). | |
612 | */ | |
613 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
614 | vcpu->arch.osvw.status |= 1; | |
615 | } | |
616 | ||
6aa8b732 AK |
617 | static int has_svm(void) |
618 | { | |
63d1142f | 619 | const char *msg; |
6aa8b732 | 620 | |
63d1142f | 621 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 622 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
623 | return 0; |
624 | } | |
625 | ||
6aa8b732 AK |
626 | return 1; |
627 | } | |
628 | ||
13a34e06 | 629 | static void svm_hardware_disable(void) |
6aa8b732 | 630 | { |
fbc0db76 JR |
631 | /* Make sure we clean up behind us */ |
632 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
633 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
634 | ||
2c8dceeb | 635 | cpu_svm_disable(); |
1018faa6 JR |
636 | |
637 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
638 | } |
639 | ||
13a34e06 | 640 | static int svm_hardware_enable(void) |
6aa8b732 AK |
641 | { |
642 | ||
0fe1e009 | 643 | struct svm_cpu_data *sd; |
6aa8b732 | 644 | uint64_t efer; |
89a27f4d | 645 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
646 | struct desc_struct *gdt; |
647 | int me = raw_smp_processor_id(); | |
648 | ||
10474ae8 AG |
649 | rdmsrl(MSR_EFER, efer); |
650 | if (efer & EFER_SVME) | |
651 | return -EBUSY; | |
652 | ||
6aa8b732 | 653 | if (!has_svm()) { |
1f5b77f5 | 654 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 655 | return -EINVAL; |
6aa8b732 | 656 | } |
0fe1e009 | 657 | sd = per_cpu(svm_data, me); |
0fe1e009 | 658 | if (!sd) { |
1f5b77f5 | 659 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 660 | return -EINVAL; |
6aa8b732 AK |
661 | } |
662 | ||
0fe1e009 TH |
663 | sd->asid_generation = 1; |
664 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
665 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 666 | |
d6ab1ed4 | 667 | native_store_gdt(&gdt_descr); |
89a27f4d | 668 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 669 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 670 | |
9962d032 | 671 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 672 | |
d0316554 | 673 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 674 | |
fbc0db76 JR |
675 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
676 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 677 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
678 | } |
679 | ||
2b036c6b BO |
680 | |
681 | /* | |
682 | * Get OSVW bits. | |
683 | * | |
684 | * Note that it is possible to have a system with mixed processor | |
685 | * revisions and therefore different OSVW bits. If bits are not the same | |
686 | * on different processors then choose the worst case (i.e. if erratum | |
687 | * is present on one processor and not on another then assume that the | |
688 | * erratum is present everywhere). | |
689 | */ | |
690 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
691 | uint64_t len, status = 0; | |
692 | int err; | |
693 | ||
694 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
695 | if (!err) | |
696 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
697 | &err); | |
698 | ||
699 | if (err) | |
700 | osvw_status = osvw_len = 0; | |
701 | else { | |
702 | if (len < osvw_len) | |
703 | osvw_len = len; | |
704 | osvw_status |= status; | |
705 | osvw_status &= (1ULL << osvw_len) - 1; | |
706 | } | |
707 | } else | |
708 | osvw_status = osvw_len = 0; | |
709 | ||
67ec6607 JR |
710 | svm_init_erratum_383(); |
711 | ||
1018faa6 JR |
712 | amd_pmu_enable_virt(); |
713 | ||
10474ae8 | 714 | return 0; |
6aa8b732 AK |
715 | } |
716 | ||
0da1db75 JR |
717 | static void svm_cpu_uninit(int cpu) |
718 | { | |
0fe1e009 | 719 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 720 | |
0fe1e009 | 721 | if (!sd) |
0da1db75 JR |
722 | return; |
723 | ||
724 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
725 | __free_page(sd->save_area); |
726 | kfree(sd); | |
0da1db75 JR |
727 | } |
728 | ||
6aa8b732 AK |
729 | static int svm_cpu_init(int cpu) |
730 | { | |
0fe1e009 | 731 | struct svm_cpu_data *sd; |
6aa8b732 AK |
732 | int r; |
733 | ||
0fe1e009 TH |
734 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
735 | if (!sd) | |
6aa8b732 | 736 | return -ENOMEM; |
0fe1e009 TH |
737 | sd->cpu = cpu; |
738 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 739 | r = -ENOMEM; |
0fe1e009 | 740 | if (!sd->save_area) |
6aa8b732 AK |
741 | goto err_1; |
742 | ||
0fe1e009 | 743 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
744 | |
745 | return 0; | |
746 | ||
747 | err_1: | |
0fe1e009 | 748 | kfree(sd); |
6aa8b732 AK |
749 | return r; |
750 | ||
751 | } | |
752 | ||
ac72a9b7 JR |
753 | static bool valid_msr_intercept(u32 index) |
754 | { | |
755 | int i; | |
756 | ||
757 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
758 | if (direct_access_msrs[i].index == index) | |
759 | return true; | |
760 | ||
761 | return false; | |
762 | } | |
763 | ||
bfc733a7 RR |
764 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
765 | int read, int write) | |
6aa8b732 | 766 | { |
455716fa JR |
767 | u8 bit_read, bit_write; |
768 | unsigned long tmp; | |
769 | u32 offset; | |
6aa8b732 | 770 | |
ac72a9b7 JR |
771 | /* |
772 | * If this warning triggers extend the direct_access_msrs list at the | |
773 | * beginning of the file | |
774 | */ | |
775 | WARN_ON(!valid_msr_intercept(msr)); | |
776 | ||
455716fa JR |
777 | offset = svm_msrpm_offset(msr); |
778 | bit_read = 2 * (msr & 0x0f); | |
779 | bit_write = 2 * (msr & 0x0f) + 1; | |
780 | tmp = msrpm[offset]; | |
781 | ||
782 | BUG_ON(offset == MSR_INVALID); | |
783 | ||
784 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
785 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
786 | ||
787 | msrpm[offset] = tmp; | |
6aa8b732 AK |
788 | } |
789 | ||
f65c229c | 790 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
791 | { |
792 | int i; | |
793 | ||
f65c229c JR |
794 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
795 | ||
ac72a9b7 JR |
796 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
797 | if (!direct_access_msrs[i].always) | |
798 | continue; | |
799 | ||
800 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
801 | } | |
f65c229c JR |
802 | } |
803 | ||
323c3d80 JR |
804 | static void add_msr_offset(u32 offset) |
805 | { | |
806 | int i; | |
807 | ||
808 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
809 | ||
810 | /* Offset already in list? */ | |
811 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 812 | return; |
323c3d80 JR |
813 | |
814 | /* Slot used by another offset? */ | |
815 | if (msrpm_offsets[i] != MSR_INVALID) | |
816 | continue; | |
817 | ||
818 | /* Add offset to list */ | |
819 | msrpm_offsets[i] = offset; | |
820 | ||
821 | return; | |
6aa8b732 | 822 | } |
323c3d80 JR |
823 | |
824 | /* | |
825 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
826 | * increase MSRPM_OFFSETS in this case. | |
827 | */ | |
bfc733a7 | 828 | BUG(); |
6aa8b732 AK |
829 | } |
830 | ||
323c3d80 | 831 | static void init_msrpm_offsets(void) |
f65c229c | 832 | { |
323c3d80 | 833 | int i; |
f65c229c | 834 | |
323c3d80 JR |
835 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
836 | ||
837 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
838 | u32 offset; | |
839 | ||
840 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
841 | BUG_ON(offset == MSR_INVALID); | |
842 | ||
843 | add_msr_offset(offset); | |
844 | } | |
f65c229c JR |
845 | } |
846 | ||
24e09cbf JR |
847 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
848 | { | |
849 | u32 *msrpm = svm->msrpm; | |
850 | ||
851 | svm->vmcb->control.lbr_ctl = 1; | |
852 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
853 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
854 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
855 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
856 | } | |
857 | ||
858 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
859 | { | |
860 | u32 *msrpm = svm->msrpm; | |
861 | ||
862 | svm->vmcb->control.lbr_ctl = 0; | |
863 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
864 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
865 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
866 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
867 | } | |
868 | ||
6aa8b732 AK |
869 | static __init int svm_hardware_setup(void) |
870 | { | |
871 | int cpu; | |
872 | struct page *iopm_pages; | |
f65c229c | 873 | void *iopm_va; |
6aa8b732 AK |
874 | int r; |
875 | ||
6aa8b732 AK |
876 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
877 | ||
878 | if (!iopm_pages) | |
879 | return -ENOMEM; | |
c8681339 AL |
880 | |
881 | iopm_va = page_address(iopm_pages); | |
882 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
883 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
884 | ||
323c3d80 JR |
885 | init_msrpm_offsets(); |
886 | ||
50a37eb4 JR |
887 | if (boot_cpu_has(X86_FEATURE_NX)) |
888 | kvm_enable_efer_bits(EFER_NX); | |
889 | ||
1b2fd70c AG |
890 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
891 | kvm_enable_efer_bits(EFER_FFXSR); | |
892 | ||
92a1f12d | 893 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 894 | kvm_has_tsc_control = true; |
bc9b961b HZ |
895 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
896 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
897 | } |
898 | ||
236de055 AG |
899 | if (nested) { |
900 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 901 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
902 | } |
903 | ||
3230bb47 | 904 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
905 | r = svm_cpu_init(cpu); |
906 | if (r) | |
f65c229c | 907 | goto err; |
6aa8b732 | 908 | } |
33bd6a0b | 909 | |
2a6b20b8 | 910 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
911 | npt_enabled = false; |
912 | ||
6c7dac72 JR |
913 | if (npt_enabled && !npt) { |
914 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
915 | npt_enabled = false; | |
916 | } | |
917 | ||
18552672 | 918 | if (npt_enabled) { |
e3da3acd | 919 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 920 | kvm_enable_tdp(); |
5f4cb662 JR |
921 | } else |
922 | kvm_disable_tdp(); | |
e3da3acd | 923 | |
6aa8b732 AK |
924 | return 0; |
925 | ||
f65c229c | 926 | err: |
6aa8b732 AK |
927 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
928 | iopm_base = 0; | |
929 | return r; | |
930 | } | |
931 | ||
932 | static __exit void svm_hardware_unsetup(void) | |
933 | { | |
0da1db75 JR |
934 | int cpu; |
935 | ||
3230bb47 | 936 | for_each_possible_cpu(cpu) |
0da1db75 JR |
937 | svm_cpu_uninit(cpu); |
938 | ||
6aa8b732 | 939 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 940 | iopm_base = 0; |
6aa8b732 AK |
941 | } |
942 | ||
943 | static void init_seg(struct vmcb_seg *seg) | |
944 | { | |
945 | seg->selector = 0; | |
946 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 947 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
948 | seg->limit = 0xffff; |
949 | seg->base = 0; | |
950 | } | |
951 | ||
952 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
953 | { | |
954 | seg->selector = 0; | |
955 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
956 | seg->limit = 0xffff; | |
957 | seg->base = 0; | |
958 | } | |
959 | ||
ba904635 WA |
960 | static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu) |
961 | { | |
962 | struct vcpu_svm *svm = to_svm(vcpu); | |
963 | ||
964 | return svm->vmcb->control.tsc_offset; | |
965 | } | |
966 | ||
f4e1b3c8 ZA |
967 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
968 | { | |
969 | struct vcpu_svm *svm = to_svm(vcpu); | |
970 | u64 g_tsc_offset = 0; | |
971 | ||
2030753d | 972 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
973 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
974 | svm->nested.hsave->control.tsc_offset; | |
975 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
976 | } else |
977 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
978 | svm->vmcb->control.tsc_offset, | |
979 | offset); | |
f4e1b3c8 ZA |
980 | |
981 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
982 | |
983 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
984 | } |
985 | ||
58ea6767 | 986 | static void svm_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment) |
e48672fa ZA |
987 | { |
988 | struct vcpu_svm *svm = to_svm(vcpu); | |
989 | ||
990 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 991 | if (is_guest_mode(vcpu)) |
e48672fa | 992 | svm->nested.hsave->control.tsc_offset += adjustment; |
489223ed YY |
993 | else |
994 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
995 | svm->vmcb->control.tsc_offset - adjustment, | |
996 | svm->vmcb->control.tsc_offset); | |
997 | ||
116a0a23 | 998 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
999 | } |
1000 | ||
5690891b | 1001 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1002 | { |
e6101a96 JR |
1003 | struct vmcb_control_area *control = &svm->vmcb->control; |
1004 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1005 | |
bff78274 | 1006 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 1007 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1008 | |
4ee546b4 RJ |
1009 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1010 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1011 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1012 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1013 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1014 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
1015 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1016 | |
5315c716 | 1017 | set_dr_intercepts(svm); |
6aa8b732 | 1018 | |
18c918c5 JR |
1019 | set_exception_intercept(svm, PF_VECTOR); |
1020 | set_exception_intercept(svm, UD_VECTOR); | |
1021 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1022 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1023 | set_exception_intercept(svm, DB_VECTOR); |
6aa8b732 | 1024 | |
8a05a1b8 JR |
1025 | set_intercept(svm, INTERCEPT_INTR); |
1026 | set_intercept(svm, INTERCEPT_NMI); | |
1027 | set_intercept(svm, INTERCEPT_SMI); | |
1028 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1029 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1030 | set_intercept(svm, INTERCEPT_CPUID); |
1031 | set_intercept(svm, INTERCEPT_INVD); | |
1032 | set_intercept(svm, INTERCEPT_HLT); | |
1033 | set_intercept(svm, INTERCEPT_INVLPG); | |
1034 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1035 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1036 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1037 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1038 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1039 | set_intercept(svm, INTERCEPT_VMRUN); | |
1040 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1041 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1042 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1043 | set_intercept(svm, INTERCEPT_STGI); | |
1044 | set_intercept(svm, INTERCEPT_CLGI); | |
1045 | set_intercept(svm, INTERCEPT_SKINIT); | |
1046 | set_intercept(svm, INTERCEPT_WBINVD); | |
1047 | set_intercept(svm, INTERCEPT_MONITOR); | |
1048 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 1049 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
1050 | |
1051 | control->iopm_base_pa = iopm_base; | |
f65c229c | 1052 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1053 | control->int_ctl = V_INTR_MASKING_MASK; |
1054 | ||
1055 | init_seg(&save->es); | |
1056 | init_seg(&save->ss); | |
1057 | init_seg(&save->ds); | |
1058 | init_seg(&save->fs); | |
1059 | init_seg(&save->gs); | |
1060 | ||
1061 | save->cs.selector = 0xf000; | |
04b66839 | 1062 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1063 | /* Executable/Readable Code Segment */ |
1064 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1065 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1066 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1067 | |
1068 | save->gdtr.limit = 0xffff; | |
1069 | save->idtr.limit = 0xffff; | |
1070 | ||
1071 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1072 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1073 | ||
5690891b | 1074 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1075 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1076 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1077 | save->rip = 0x0000fff0; |
5fdbf976 | 1078 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1079 | |
e0231715 | 1080 | /* |
18fa000a | 1081 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1082 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1083 | */ |
79a8059d | 1084 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1085 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1086 | |
66aee91a | 1087 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1088 | /* rdx = ?? */ |
709ddebf JR |
1089 | |
1090 | if (npt_enabled) { | |
1091 | /* Setup VMCB for Nested Paging */ | |
1092 | control->nested_ctl = 1; | |
8a05a1b8 | 1093 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1094 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1095 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1096 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1097 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1098 | save->cr3 = 0; |
1099 | save->cr4 = 0; | |
1100 | } | |
f40f6a45 | 1101 | svm->asid_generation = 0; |
1371d904 | 1102 | |
e6aa9abd | 1103 | svm->nested.vmcb = 0; |
2af9194d JR |
1104 | svm->vcpu.arch.hflags = 0; |
1105 | ||
2a6b20b8 | 1106 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1107 | control->pause_filter_count = 3000; |
8a05a1b8 | 1108 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1109 | } |
1110 | ||
8d28fec4 RJ |
1111 | mark_all_dirty(svm->vmcb); |
1112 | ||
2af9194d | 1113 | enable_gif(svm); |
6aa8b732 AK |
1114 | } |
1115 | ||
d28bc9dd | 1116 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
1117 | { |
1118 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1119 | u32 dummy; |
1120 | u32 eax = 1; | |
04d2cc77 | 1121 | |
d28bc9dd NA |
1122 | if (!init_event) { |
1123 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
1124 | MSR_IA32_APICBASE_ENABLE; | |
1125 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
1126 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
1127 | } | |
5690891b | 1128 | init_vmcb(svm); |
70433389 | 1129 | |
66f7b72e JS |
1130 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy); |
1131 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); | |
04d2cc77 AK |
1132 | } |
1133 | ||
fb3f0f51 | 1134 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1135 | { |
a2fa3e9f | 1136 | struct vcpu_svm *svm; |
6aa8b732 | 1137 | struct page *page; |
f65c229c | 1138 | struct page *msrpm_pages; |
b286d5d8 | 1139 | struct page *hsave_page; |
3d6368ef | 1140 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1141 | int err; |
6aa8b732 | 1142 | |
c16f862d | 1143 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1144 | if (!svm) { |
1145 | err = -ENOMEM; | |
1146 | goto out; | |
1147 | } | |
1148 | ||
1149 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1150 | if (err) | |
1151 | goto free_svm; | |
1152 | ||
b7af4043 | 1153 | err = -ENOMEM; |
6aa8b732 | 1154 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1155 | if (!page) |
fb3f0f51 | 1156 | goto uninit; |
6aa8b732 | 1157 | |
f65c229c JR |
1158 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1159 | if (!msrpm_pages) | |
b7af4043 | 1160 | goto free_page1; |
3d6368ef AG |
1161 | |
1162 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1163 | if (!nested_msrpm_pages) | |
b7af4043 | 1164 | goto free_page2; |
f65c229c | 1165 | |
b286d5d8 AG |
1166 | hsave_page = alloc_page(GFP_KERNEL); |
1167 | if (!hsave_page) | |
b7af4043 TY |
1168 | goto free_page3; |
1169 | ||
e6aa9abd | 1170 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1171 | |
b7af4043 TY |
1172 | svm->msrpm = page_address(msrpm_pages); |
1173 | svm_vcpu_init_msrpm(svm->msrpm); | |
1174 | ||
e6aa9abd | 1175 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1176 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1177 | |
a2fa3e9f GH |
1178 | svm->vmcb = page_address(page); |
1179 | clear_page(svm->vmcb); | |
1180 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1181 | svm->asid_generation = 0; | |
5690891b | 1182 | init_vmcb(svm); |
6aa8b732 | 1183 | |
2b036c6b BO |
1184 | svm_init_osvw(&svm->vcpu); |
1185 | ||
fb3f0f51 | 1186 | return &svm->vcpu; |
36241b8c | 1187 | |
b7af4043 TY |
1188 | free_page3: |
1189 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1190 | free_page2: | |
1191 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1192 | free_page1: | |
1193 | __free_page(page); | |
fb3f0f51 RR |
1194 | uninit: |
1195 | kvm_vcpu_uninit(&svm->vcpu); | |
1196 | free_svm: | |
a4770347 | 1197 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1198 | out: |
1199 | return ERR_PTR(err); | |
6aa8b732 AK |
1200 | } |
1201 | ||
1202 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1203 | { | |
a2fa3e9f GH |
1204 | struct vcpu_svm *svm = to_svm(vcpu); |
1205 | ||
fb3f0f51 | 1206 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1207 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1208 | __free_page(virt_to_page(svm->nested.hsave)); |
1209 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1210 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1211 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1212 | } |
1213 | ||
15ad7146 | 1214 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1215 | { |
a2fa3e9f | 1216 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1217 | int i; |
0cc5064d | 1218 | |
0cc5064d | 1219 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1220 | svm->asid_generation = 0; |
8d28fec4 | 1221 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1222 | } |
94dfbdb3 | 1223 | |
82ca2d10 AK |
1224 | #ifdef CONFIG_X86_64 |
1225 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1226 | #endif | |
dacccfdd AK |
1227 | savesegment(fs, svm->host.fs); |
1228 | savesegment(gs, svm->host.gs); | |
1229 | svm->host.ldt = kvm_read_ldt(); | |
1230 | ||
94dfbdb3 | 1231 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1232 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 1233 | |
ad721883 HZ |
1234 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
1235 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
1236 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
1237 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
1238 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
1239 | } | |
fbc0db76 | 1240 | } |
6aa8b732 AK |
1241 | } |
1242 | ||
1243 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1244 | { | |
a2fa3e9f | 1245 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1246 | int i; |
1247 | ||
e1beb1d3 | 1248 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1249 | kvm_load_ldt(svm->host.ldt); |
1250 | #ifdef CONFIG_X86_64 | |
1251 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1252 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1253 | load_gs_index(svm->host.gs); |
dacccfdd | 1254 | #else |
831ca609 | 1255 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1256 | loadsegment(gs, svm->host.gs); |
831ca609 | 1257 | #endif |
dacccfdd | 1258 | #endif |
94dfbdb3 | 1259 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1260 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1261 | } |
1262 | ||
6aa8b732 AK |
1263 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1264 | { | |
a2fa3e9f | 1265 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1266 | } |
1267 | ||
1268 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1269 | { | |
ae9fedc7 PB |
1270 | /* |
1271 | * Any change of EFLAGS.VM is accompained by a reload of SS | |
1272 | * (caused by either a task switch or an inter-privilege IRET), | |
1273 | * so we do not need to update the CPL here. | |
1274 | */ | |
a2fa3e9f | 1275 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1276 | } |
1277 | ||
6de4f3ad AK |
1278 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1279 | { | |
1280 | switch (reg) { | |
1281 | case VCPU_EXREG_PDPTR: | |
1282 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1283 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1284 | break; |
1285 | default: | |
1286 | BUG(); | |
1287 | } | |
1288 | } | |
1289 | ||
f0b85051 AG |
1290 | static void svm_set_vintr(struct vcpu_svm *svm) |
1291 | { | |
8a05a1b8 | 1292 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1293 | } |
1294 | ||
1295 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1296 | { | |
8a05a1b8 | 1297 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1298 | } |
1299 | ||
6aa8b732 AK |
1300 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1301 | { | |
a2fa3e9f | 1302 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1303 | |
1304 | switch (seg) { | |
1305 | case VCPU_SREG_CS: return &save->cs; | |
1306 | case VCPU_SREG_DS: return &save->ds; | |
1307 | case VCPU_SREG_ES: return &save->es; | |
1308 | case VCPU_SREG_FS: return &save->fs; | |
1309 | case VCPU_SREG_GS: return &save->gs; | |
1310 | case VCPU_SREG_SS: return &save->ss; | |
1311 | case VCPU_SREG_TR: return &save->tr; | |
1312 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1313 | } | |
1314 | BUG(); | |
8b6d44c7 | 1315 | return NULL; |
6aa8b732 AK |
1316 | } |
1317 | ||
1318 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1319 | { | |
1320 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1321 | ||
1322 | return s->base; | |
1323 | } | |
1324 | ||
1325 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1326 | struct kvm_segment *var, int seg) | |
1327 | { | |
1328 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1329 | ||
1330 | var->base = s->base; | |
1331 | var->limit = s->limit; | |
1332 | var->selector = s->selector; | |
1333 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1334 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1335 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1336 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1337 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1338 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1339 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
1340 | |
1341 | /* | |
1342 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
1343 | * However, the SVM spec states that the G bit is not observed by the | |
1344 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
1345 | * So let's synthesize a legal G bit for all segments, this helps | |
1346 | * running KVM nested. It also helps cross-vendor migration, because | |
1347 | * Intel's vmentry has a check on the 'G' bit. | |
1348 | */ | |
1349 | var->g = s->limit > 0xfffff; | |
25022acc | 1350 | |
e0231715 JR |
1351 | /* |
1352 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1353 | * for cross vendor migration purposes by "not present" |
1354 | */ | |
1355 | var->unusable = !var->present || (var->type == 0); | |
1356 | ||
1fbdc7a5 | 1357 | switch (seg) { |
1fbdc7a5 AP |
1358 | case VCPU_SREG_TR: |
1359 | /* | |
1360 | * Work around a bug where the busy flag in the tr selector | |
1361 | * isn't exposed | |
1362 | */ | |
c0d09828 | 1363 | var->type |= 0x2; |
1fbdc7a5 AP |
1364 | break; |
1365 | case VCPU_SREG_DS: | |
1366 | case VCPU_SREG_ES: | |
1367 | case VCPU_SREG_FS: | |
1368 | case VCPU_SREG_GS: | |
1369 | /* | |
1370 | * The accessed bit must always be set in the segment | |
1371 | * descriptor cache, although it can be cleared in the | |
1372 | * descriptor, the cached bit always remains at 1. Since | |
1373 | * Intel has a check on this, set it here to support | |
1374 | * cross-vendor migration. | |
1375 | */ | |
1376 | if (!var->unusable) | |
1377 | var->type |= 0x1; | |
1378 | break; | |
b586eb02 | 1379 | case VCPU_SREG_SS: |
e0231715 JR |
1380 | /* |
1381 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1382 | * descriptor is left as 1, although the whole segment has |
1383 | * been made unusable. Clear it here to pass an Intel VMX | |
1384 | * entry check when cross vendor migrating. | |
1385 | */ | |
1386 | if (var->unusable) | |
1387 | var->db = 0; | |
33b458d2 | 1388 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 1389 | break; |
1fbdc7a5 | 1390 | } |
6aa8b732 AK |
1391 | } |
1392 | ||
2e4d2653 IE |
1393 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1394 | { | |
1395 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1396 | ||
1397 | return save->cpl; | |
1398 | } | |
1399 | ||
89a27f4d | 1400 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1401 | { |
a2fa3e9f GH |
1402 | struct vcpu_svm *svm = to_svm(vcpu); |
1403 | ||
89a27f4d GN |
1404 | dt->size = svm->vmcb->save.idtr.limit; |
1405 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1406 | } |
1407 | ||
89a27f4d | 1408 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1409 | { |
a2fa3e9f GH |
1410 | struct vcpu_svm *svm = to_svm(vcpu); |
1411 | ||
89a27f4d GN |
1412 | svm->vmcb->save.idtr.limit = dt->size; |
1413 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1414 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1415 | } |
1416 | ||
89a27f4d | 1417 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1418 | { |
a2fa3e9f GH |
1419 | struct vcpu_svm *svm = to_svm(vcpu); |
1420 | ||
89a27f4d GN |
1421 | dt->size = svm->vmcb->save.gdtr.limit; |
1422 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1423 | } |
1424 | ||
89a27f4d | 1425 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1426 | { |
a2fa3e9f GH |
1427 | struct vcpu_svm *svm = to_svm(vcpu); |
1428 | ||
89a27f4d GN |
1429 | svm->vmcb->save.gdtr.limit = dt->size; |
1430 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1431 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1432 | } |
1433 | ||
e8467fda AK |
1434 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1435 | { | |
1436 | } | |
1437 | ||
aff48baa AK |
1438 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1439 | { | |
1440 | } | |
1441 | ||
25c4c276 | 1442 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1443 | { |
1444 | } | |
1445 | ||
d225157b AK |
1446 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1447 | { | |
1448 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1449 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1450 | ||
1451 | if (!svm->vcpu.fpu_active) | |
1452 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1453 | else | |
1454 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1455 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1456 | ||
dcca1a65 | 1457 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1458 | |
1459 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1460 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1461 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1462 | } else { |
4ee546b4 RJ |
1463 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1464 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1465 | } |
1466 | } | |
1467 | ||
6aa8b732 AK |
1468 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1469 | { | |
a2fa3e9f GH |
1470 | struct vcpu_svm *svm = to_svm(vcpu); |
1471 | ||
05b3e0c2 | 1472 | #ifdef CONFIG_X86_64 |
f6801dff | 1473 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1474 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1475 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1476 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1477 | } |
1478 | ||
d77c26fc | 1479 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1480 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1481 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1482 | } |
1483 | } | |
1484 | #endif | |
ad312c7c | 1485 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1486 | |
1487 | if (!npt_enabled) | |
1488 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1489 | |
1490 | if (!vcpu->fpu_active) | |
334df50a | 1491 | cr0 |= X86_CR0_TS; |
bcf166a9 PB |
1492 | /* |
1493 | * re-enable caching here because the QEMU bios | |
1494 | * does not do it - this results in some delay at | |
1495 | * reboot | |
1496 | */ | |
1497 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
1498 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1499 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1500 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1501 | update_cr0_intercept(svm); |
6aa8b732 AK |
1502 | } |
1503 | ||
5e1746d6 | 1504 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1505 | { |
1e02ce4c | 1506 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
1507 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1508 | ||
5e1746d6 NHE |
1509 | if (cr4 & X86_CR4_VMXE) |
1510 | return 1; | |
1511 | ||
e5eab0ce | 1512 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1513 | svm_flush_tlb(vcpu); |
6394b649 | 1514 | |
ec077263 JR |
1515 | vcpu->arch.cr4 = cr4; |
1516 | if (!npt_enabled) | |
1517 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1518 | cr4 |= host_cr4_mce; |
ec077263 | 1519 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1520 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1521 | return 0; |
6aa8b732 AK |
1522 | } |
1523 | ||
1524 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1525 | struct kvm_segment *var, int seg) | |
1526 | { | |
a2fa3e9f | 1527 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1528 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1529 | ||
1530 | s->base = var->base; | |
1531 | s->limit = var->limit; | |
1532 | s->selector = var->selector; | |
1533 | if (var->unusable) | |
1534 | s->attrib = 0; | |
1535 | else { | |
1536 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1537 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1538 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1539 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1540 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1541 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1542 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1543 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1544 | } | |
ae9fedc7 PB |
1545 | |
1546 | /* | |
1547 | * This is always accurate, except if SYSRET returned to a segment | |
1548 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
1549 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
1550 | * would entail passing the CPL to userspace and back. | |
1551 | */ | |
1552 | if (seg == VCPU_SREG_SS) | |
1553 | svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
6aa8b732 | 1554 | |
060d0c9a | 1555 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1556 | } |
1557 | ||
cbdb967a | 1558 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1559 | { |
d0bfb940 JK |
1560 | struct vcpu_svm *svm = to_svm(vcpu); |
1561 | ||
18c918c5 | 1562 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 1563 | |
d0bfb940 | 1564 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 1565 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1566 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1567 | } else |
1568 | vcpu->guest_debug = 0; | |
44c11430 GN |
1569 | } |
1570 | ||
0fe1e009 | 1571 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1572 | { |
0fe1e009 TH |
1573 | if (sd->next_asid > sd->max_asid) { |
1574 | ++sd->asid_generation; | |
1575 | sd->next_asid = 1; | |
a2fa3e9f | 1576 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1577 | } |
1578 | ||
0fe1e009 TH |
1579 | svm->asid_generation = sd->asid_generation; |
1580 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1581 | |
1582 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1583 | } |
1584 | ||
73aaf249 JK |
1585 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
1586 | { | |
1587 | return to_svm(vcpu)->vmcb->save.dr6; | |
1588 | } | |
1589 | ||
1590 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
1591 | { | |
1592 | struct vcpu_svm *svm = to_svm(vcpu); | |
1593 | ||
1594 | svm->vmcb->save.dr6 = value; | |
1595 | mark_dirty(svm->vmcb, VMCB_DR); | |
1596 | } | |
1597 | ||
facb0139 PB |
1598 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
1599 | { | |
1600 | struct vcpu_svm *svm = to_svm(vcpu); | |
1601 | ||
1602 | get_debugreg(vcpu->arch.db[0], 0); | |
1603 | get_debugreg(vcpu->arch.db[1], 1); | |
1604 | get_debugreg(vcpu->arch.db[2], 2); | |
1605 | get_debugreg(vcpu->arch.db[3], 3); | |
1606 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
1607 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
1608 | ||
1609 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
1610 | set_dr_intercepts(svm); | |
1611 | } | |
1612 | ||
020df079 | 1613 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1614 | { |
42dbaa5a | 1615 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1616 | |
020df079 | 1617 | svm->vmcb->save.dr7 = value; |
72214b96 | 1618 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1619 | } |
1620 | ||
851ba692 | 1621 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1622 | { |
631bc487 | 1623 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1624 | u32 error_code; |
631bc487 | 1625 | int r = 1; |
6aa8b732 | 1626 | |
631bc487 GN |
1627 | switch (svm->apf_reason) { |
1628 | default: | |
1629 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1630 | |
631bc487 GN |
1631 | trace_kvm_page_fault(fault_address, error_code); |
1632 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1633 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1634 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1635 | svm->vmcb->control.insn_bytes, | |
1636 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1637 | break; |
1638 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1639 | svm->apf_reason = 0; | |
1640 | local_irq_disable(); | |
1641 | kvm_async_pf_task_wait(fault_address); | |
1642 | local_irq_enable(); | |
1643 | break; | |
1644 | case KVM_PV_REASON_PAGE_READY: | |
1645 | svm->apf_reason = 0; | |
1646 | local_irq_disable(); | |
1647 | kvm_async_pf_task_wake(fault_address); | |
1648 | local_irq_enable(); | |
1649 | break; | |
1650 | } | |
1651 | return r; | |
6aa8b732 AK |
1652 | } |
1653 | ||
851ba692 | 1654 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1655 | { |
851ba692 AK |
1656 | struct kvm_run *kvm_run = svm->vcpu.run; |
1657 | ||
d0bfb940 | 1658 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1659 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1660 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1661 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1662 | return 1; | |
1663 | } | |
44c11430 | 1664 | |
6be7d306 JK |
1665 | if (svm->nmi_singlestep) { |
1666 | svm->nmi_singlestep = false; | |
44c11430 GN |
1667 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1668 | svm->vmcb->save.rflags &= | |
1669 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
44c11430 GN |
1670 | } |
1671 | ||
1672 | if (svm->vcpu.guest_debug & | |
e0231715 | 1673 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1674 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1675 | kvm_run->debug.arch.pc = | |
1676 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1677 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1678 | return 0; | |
1679 | } | |
1680 | ||
1681 | return 1; | |
d0bfb940 JK |
1682 | } |
1683 | ||
851ba692 | 1684 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1685 | { |
851ba692 AK |
1686 | struct kvm_run *kvm_run = svm->vcpu.run; |
1687 | ||
d0bfb940 JK |
1688 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1689 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1690 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1691 | return 0; | |
1692 | } | |
1693 | ||
851ba692 | 1694 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1695 | { |
1696 | int er; | |
1697 | ||
51d8b661 | 1698 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1699 | if (er != EMULATE_DONE) |
7ee5d940 | 1700 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1701 | return 1; |
1702 | } | |
1703 | ||
54a20552 EN |
1704 | static int ac_interception(struct vcpu_svm *svm) |
1705 | { | |
1706 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
1707 | return 1; | |
1708 | } | |
1709 | ||
6b52d186 | 1710 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1711 | { |
6b52d186 | 1712 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1713 | |
18c918c5 | 1714 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1715 | |
e756fc62 | 1716 | svm->vcpu.fpu_active = 1; |
d225157b | 1717 | update_cr0_intercept(svm); |
6b52d186 | 1718 | } |
a2fa3e9f | 1719 | |
6b52d186 AK |
1720 | static int nm_interception(struct vcpu_svm *svm) |
1721 | { | |
1722 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1723 | return 1; |
7807fa6c AL |
1724 | } |
1725 | ||
67ec6607 JR |
1726 | static bool is_erratum_383(void) |
1727 | { | |
1728 | int err, i; | |
1729 | u64 value; | |
1730 | ||
1731 | if (!erratum_383_found) | |
1732 | return false; | |
1733 | ||
1734 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1735 | if (err) | |
1736 | return false; | |
1737 | ||
1738 | /* Bit 62 may or may not be set for this mce */ | |
1739 | value &= ~(1ULL << 62); | |
1740 | ||
1741 | if (value != 0xb600000000010015ULL) | |
1742 | return false; | |
1743 | ||
1744 | /* Clear MCi_STATUS registers */ | |
1745 | for (i = 0; i < 6; ++i) | |
1746 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1747 | ||
1748 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1749 | if (!err) { | |
1750 | u32 low, high; | |
1751 | ||
1752 | value &= ~(1ULL << 2); | |
1753 | low = lower_32_bits(value); | |
1754 | high = upper_32_bits(value); | |
1755 | ||
1756 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1757 | } | |
1758 | ||
1759 | /* Flush tlb to evict multi-match entries */ | |
1760 | __flush_tlb_all(); | |
1761 | ||
1762 | return true; | |
1763 | } | |
1764 | ||
fe5913e4 | 1765 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1766 | { |
67ec6607 JR |
1767 | if (is_erratum_383()) { |
1768 | /* | |
1769 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1770 | * guest. | |
1771 | */ | |
1772 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1773 | ||
a8eeb04a | 1774 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1775 | |
1776 | return; | |
1777 | } | |
1778 | ||
53371b50 JR |
1779 | /* |
1780 | * On an #MC intercept the MCE handler is not called automatically in | |
1781 | * the host. So do it by hand here. | |
1782 | */ | |
1783 | asm volatile ( | |
1784 | "int $0x12\n"); | |
1785 | /* not sure if we ever come back to this point */ | |
1786 | ||
fe5913e4 JR |
1787 | return; |
1788 | } | |
1789 | ||
1790 | static int mc_interception(struct vcpu_svm *svm) | |
1791 | { | |
53371b50 JR |
1792 | return 1; |
1793 | } | |
1794 | ||
851ba692 | 1795 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1796 | { |
851ba692 AK |
1797 | struct kvm_run *kvm_run = svm->vcpu.run; |
1798 | ||
46fe4ddd JR |
1799 | /* |
1800 | * VMCB is undefined after a SHUTDOWN intercept | |
1801 | * so reinitialize it. | |
1802 | */ | |
a2fa3e9f | 1803 | clear_page(svm->vmcb); |
5690891b | 1804 | init_vmcb(svm); |
46fe4ddd JR |
1805 | |
1806 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1807 | return 0; | |
1808 | } | |
1809 | ||
851ba692 | 1810 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1811 | { |
cf8f70bf | 1812 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1813 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1814 | int size, in, string; |
039576c0 | 1815 | unsigned port; |
6aa8b732 | 1816 | |
e756fc62 | 1817 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1818 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1819 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1820 | if (string || in) |
51d8b661 | 1821 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1822 | |
039576c0 AK |
1823 | port = io_info >> 16; |
1824 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1825 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1826 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1827 | |
1828 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1829 | } |
1830 | ||
851ba692 | 1831 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1832 | { |
1833 | return 1; | |
1834 | } | |
1835 | ||
851ba692 | 1836 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1837 | { |
1838 | ++svm->vcpu.stat.irq_exits; | |
1839 | return 1; | |
1840 | } | |
1841 | ||
851ba692 | 1842 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1843 | { |
1844 | return 1; | |
1845 | } | |
1846 | ||
851ba692 | 1847 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1848 | { |
5fdbf976 | 1849 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 | 1850 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
1851 | } |
1852 | ||
851ba692 | 1853 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1854 | { |
5fdbf976 | 1855 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
7aa81cc0 AL |
1856 | kvm_emulate_hypercall(&svm->vcpu); |
1857 | return 1; | |
02e235bc AK |
1858 | } |
1859 | ||
5bd2edc3 JR |
1860 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1861 | { | |
1862 | struct vcpu_svm *svm = to_svm(vcpu); | |
1863 | ||
1864 | return svm->nested.nested_cr3; | |
1865 | } | |
1866 | ||
e4e517b4 AK |
1867 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
1868 | { | |
1869 | struct vcpu_svm *svm = to_svm(vcpu); | |
1870 | u64 cr3 = svm->nested.nested_cr3; | |
1871 | u64 pdpte; | |
1872 | int ret; | |
1873 | ||
54bf36aa PB |
1874 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte, |
1875 | offset_in_page(cr3) + index * 8, 8); | |
e4e517b4 AK |
1876 | if (ret) |
1877 | return 0; | |
1878 | return pdpte; | |
1879 | } | |
1880 | ||
5bd2edc3 JR |
1881 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
1882 | unsigned long root) | |
1883 | { | |
1884 | struct vcpu_svm *svm = to_svm(vcpu); | |
1885 | ||
1886 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1887 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1888 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1889 | } |
1890 | ||
6389ee94 AK |
1891 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1892 | struct x86_exception *fault) | |
5bd2edc3 JR |
1893 | { |
1894 | struct vcpu_svm *svm = to_svm(vcpu); | |
1895 | ||
5e352519 PB |
1896 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
1897 | /* | |
1898 | * TODO: track the cause of the nested page fault, and | |
1899 | * correctly fill in the high bits of exit_info_1. | |
1900 | */ | |
1901 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1902 | svm->vmcb->control.exit_code_hi = 0; | |
1903 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
1904 | svm->vmcb->control.exit_info_2 = fault->address; | |
1905 | } | |
1906 | ||
1907 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
1908 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
1909 | ||
1910 | /* | |
1911 | * The present bit is always zero for page structure faults on real | |
1912 | * hardware. | |
1913 | */ | |
1914 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
1915 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
1916 | |
1917 | nested_svm_vmexit(svm); | |
1918 | } | |
1919 | ||
8a3c1a33 | 1920 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 1921 | { |
ad896af0 PB |
1922 | WARN_ON(mmu_is_nested(vcpu)); |
1923 | kvm_init_shadow_mmu(vcpu); | |
4b16184c JR |
1924 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; |
1925 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 1926 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
1927 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
1928 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
c258b62b | 1929 | reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu); |
4b16184c | 1930 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
1931 | } |
1932 | ||
1933 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1934 | { | |
1935 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1936 | } | |
1937 | ||
c0725420 AG |
1938 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1939 | { | |
f6801dff | 1940 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1941 | || !is_paging(&svm->vcpu)) { |
1942 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1943 | return 1; | |
1944 | } | |
1945 | ||
1946 | if (svm->vmcb->save.cpl) { | |
1947 | kvm_inject_gp(&svm->vcpu, 0); | |
1948 | return 1; | |
1949 | } | |
1950 | ||
1951 | return 0; | |
1952 | } | |
1953 | ||
cf74a78b AG |
1954 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1955 | bool has_error_code, u32 error_code) | |
1956 | { | |
b8e88bc8 JR |
1957 | int vmexit; |
1958 | ||
2030753d | 1959 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1960 | return 0; |
cf74a78b | 1961 | |
0295ad7d JR |
1962 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1963 | svm->vmcb->control.exit_code_hi = 0; | |
1964 | svm->vmcb->control.exit_info_1 = error_code; | |
1965 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1966 | ||
b8e88bc8 JR |
1967 | vmexit = nested_svm_intercept(svm); |
1968 | if (vmexit == NESTED_EXIT_DONE) | |
1969 | svm->nested.exit_required = true; | |
1970 | ||
1971 | return vmexit; | |
cf74a78b AG |
1972 | } |
1973 | ||
8fe54654 JR |
1974 | /* This function returns true if it is save to enable the irq window */ |
1975 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1976 | { |
2030753d | 1977 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 1978 | return true; |
cf74a78b | 1979 | |
26666957 | 1980 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1981 | return true; |
cf74a78b | 1982 | |
26666957 | 1983 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1984 | return false; |
cf74a78b | 1985 | |
a0a07cd2 GN |
1986 | /* |
1987 | * if vmexit was already requested (by intercepted exception | |
1988 | * for instance) do not overwrite it with "external interrupt" | |
1989 | * vmexit. | |
1990 | */ | |
1991 | if (svm->nested.exit_required) | |
1992 | return false; | |
1993 | ||
197717d5 JR |
1994 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1995 | svm->vmcb->control.exit_info_1 = 0; | |
1996 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1997 | |
cd3ff653 JR |
1998 | if (svm->nested.intercept & 1ULL) { |
1999 | /* | |
2000 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2001 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2002 | * #vmexit emulation might sleep. Only signal request for |
2003 | * the #vmexit here. | |
2004 | */ | |
2005 | svm->nested.exit_required = true; | |
236649de | 2006 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2007 | return false; |
cf74a78b AG |
2008 | } |
2009 | ||
8fe54654 | 2010 | return true; |
cf74a78b AG |
2011 | } |
2012 | ||
887f500c JR |
2013 | /* This function returns true if it is save to enable the nmi window */ |
2014 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2015 | { | |
2030753d | 2016 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2017 | return true; |
2018 | ||
2019 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2020 | return true; | |
2021 | ||
2022 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2023 | svm->nested.exit_required = true; | |
2024 | ||
2025 | return false; | |
cf74a78b AG |
2026 | } |
2027 | ||
7597f129 | 2028 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2029 | { |
2030 | struct page *page; | |
2031 | ||
6c3bd3d7 JR |
2032 | might_sleep(); |
2033 | ||
54bf36aa | 2034 | page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2035 | if (is_error_page(page)) |
2036 | goto error; | |
2037 | ||
7597f129 JR |
2038 | *_page = page; |
2039 | ||
2040 | return kmap(page); | |
34f80cfa JR |
2041 | |
2042 | error: | |
34f80cfa JR |
2043 | kvm_inject_gp(&svm->vcpu, 0); |
2044 | ||
2045 | return NULL; | |
2046 | } | |
2047 | ||
7597f129 | 2048 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2049 | { |
7597f129 | 2050 | kunmap(page); |
34f80cfa JR |
2051 | kvm_release_page_dirty(page); |
2052 | } | |
34f80cfa | 2053 | |
ce2ac085 JR |
2054 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2055 | { | |
9bf41833 JK |
2056 | unsigned port, size, iopm_len; |
2057 | u16 val, mask; | |
2058 | u8 start_bit; | |
ce2ac085 | 2059 | u64 gpa; |
34f80cfa | 2060 | |
ce2ac085 JR |
2061 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2062 | return NESTED_EXIT_HOST; | |
34f80cfa | 2063 | |
ce2ac085 | 2064 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
2065 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
2066 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 2067 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
2068 | start_bit = port % 8; |
2069 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
2070 | mask = (0xf >> (4 - size)) << start_bit; | |
2071 | val = 0; | |
ce2ac085 | 2072 | |
54bf36aa | 2073 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 2074 | return NESTED_EXIT_DONE; |
ce2ac085 | 2075 | |
9bf41833 | 2076 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
2077 | } |
2078 | ||
d2477826 | 2079 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2080 | { |
0d6b3537 JR |
2081 | u32 offset, msr, value; |
2082 | int write, mask; | |
4c2161ae | 2083 | |
3d62d9aa | 2084 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2085 | return NESTED_EXIT_HOST; |
3d62d9aa | 2086 | |
0d6b3537 JR |
2087 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2088 | offset = svm_msrpm_offset(msr); | |
2089 | write = svm->vmcb->control.exit_info_1 & 1; | |
2090 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2091 | |
0d6b3537 JR |
2092 | if (offset == MSR_INVALID) |
2093 | return NESTED_EXIT_DONE; | |
4c2161ae | 2094 | |
0d6b3537 JR |
2095 | /* Offset is in 32 bit units but need in 8 bit units */ |
2096 | offset *= 4; | |
4c2161ae | 2097 | |
54bf36aa | 2098 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 2099 | return NESTED_EXIT_DONE; |
3d62d9aa | 2100 | |
0d6b3537 | 2101 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2102 | } |
2103 | ||
410e4d57 | 2104 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2105 | { |
cf74a78b | 2106 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2107 | |
410e4d57 JR |
2108 | switch (exit_code) { |
2109 | case SVM_EXIT_INTR: | |
2110 | case SVM_EXIT_NMI: | |
ff47a49b | 2111 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2112 | return NESTED_EXIT_HOST; |
410e4d57 | 2113 | case SVM_EXIT_NPF: |
e0231715 | 2114 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2115 | if (npt_enabled) |
2116 | return NESTED_EXIT_HOST; | |
2117 | break; | |
410e4d57 | 2118 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2119 | /* When we're shadowing, trap PFs, but not async PF */ |
2120 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2121 | return NESTED_EXIT_HOST; |
2122 | break; | |
66a562f7 JR |
2123 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2124 | nm_interception(svm); | |
2125 | break; | |
410e4d57 JR |
2126 | default: |
2127 | break; | |
cf74a78b AG |
2128 | } |
2129 | ||
410e4d57 JR |
2130 | return NESTED_EXIT_CONTINUE; |
2131 | } | |
2132 | ||
2133 | /* | |
2134 | * If this function returns true, this #vmexit was already handled | |
2135 | */ | |
b8e88bc8 | 2136 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2137 | { |
2138 | u32 exit_code = svm->vmcb->control.exit_code; | |
2139 | int vmexit = NESTED_EXIT_HOST; | |
2140 | ||
cf74a78b | 2141 | switch (exit_code) { |
9c4e40b9 | 2142 | case SVM_EXIT_MSR: |
3d62d9aa | 2143 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2144 | break; |
ce2ac085 JR |
2145 | case SVM_EXIT_IOIO: |
2146 | vmexit = nested_svm_intercept_ioio(svm); | |
2147 | break; | |
4ee546b4 RJ |
2148 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2149 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2150 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2151 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2152 | break; |
2153 | } | |
3aed041a JR |
2154 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2155 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2156 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2157 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2158 | break; |
2159 | } | |
2160 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2161 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2162 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2163 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2164 | /* async page fault always cause vmexit */ |
2165 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2166 | svm->apf_reason != 0) | |
2167 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2168 | break; |
2169 | } | |
228070b1 JR |
2170 | case SVM_EXIT_ERR: { |
2171 | vmexit = NESTED_EXIT_DONE; | |
2172 | break; | |
2173 | } | |
cf74a78b AG |
2174 | default: { |
2175 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2176 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2177 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2178 | } |
2179 | } | |
2180 | ||
b8e88bc8 JR |
2181 | return vmexit; |
2182 | } | |
2183 | ||
2184 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2185 | { | |
2186 | int vmexit; | |
2187 | ||
2188 | vmexit = nested_svm_intercept(svm); | |
2189 | ||
2190 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2191 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2192 | |
2193 | return vmexit; | |
cf74a78b AG |
2194 | } |
2195 | ||
0460a979 JR |
2196 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2197 | { | |
2198 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2199 | struct vmcb_control_area *from = &from_vmcb->control; | |
2200 | ||
4ee546b4 | 2201 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2202 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2203 | dst->intercept_exceptions = from->intercept_exceptions; |
2204 | dst->intercept = from->intercept; | |
2205 | dst->iopm_base_pa = from->iopm_base_pa; | |
2206 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2207 | dst->tsc_offset = from->tsc_offset; | |
2208 | dst->asid = from->asid; | |
2209 | dst->tlb_ctl = from->tlb_ctl; | |
2210 | dst->int_ctl = from->int_ctl; | |
2211 | dst->int_vector = from->int_vector; | |
2212 | dst->int_state = from->int_state; | |
2213 | dst->exit_code = from->exit_code; | |
2214 | dst->exit_code_hi = from->exit_code_hi; | |
2215 | dst->exit_info_1 = from->exit_info_1; | |
2216 | dst->exit_info_2 = from->exit_info_2; | |
2217 | dst->exit_int_info = from->exit_int_info; | |
2218 | dst->exit_int_info_err = from->exit_int_info_err; | |
2219 | dst->nested_ctl = from->nested_ctl; | |
2220 | dst->event_inj = from->event_inj; | |
2221 | dst->event_inj_err = from->event_inj_err; | |
2222 | dst->nested_cr3 = from->nested_cr3; | |
2223 | dst->lbr_ctl = from->lbr_ctl; | |
2224 | } | |
2225 | ||
34f80cfa | 2226 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2227 | { |
34f80cfa | 2228 | struct vmcb *nested_vmcb; |
e6aa9abd | 2229 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2230 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2231 | struct page *page; |
cf74a78b | 2232 | |
17897f36 JR |
2233 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2234 | vmcb->control.exit_info_1, | |
2235 | vmcb->control.exit_info_2, | |
2236 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2237 | vmcb->control.exit_int_info_err, |
2238 | KVM_ISA_SVM); | |
17897f36 | 2239 | |
7597f129 | 2240 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2241 | if (!nested_vmcb) |
2242 | return 1; | |
2243 | ||
2030753d JR |
2244 | /* Exit Guest-Mode */ |
2245 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2246 | svm->nested.vmcb = 0; |
2247 | ||
cf74a78b | 2248 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2249 | disable_gif(svm); |
2250 | ||
2251 | nested_vmcb->save.es = vmcb->save.es; | |
2252 | nested_vmcb->save.cs = vmcb->save.cs; | |
2253 | nested_vmcb->save.ss = vmcb->save.ss; | |
2254 | nested_vmcb->save.ds = vmcb->save.ds; | |
2255 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2256 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2257 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2258 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2259 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2260 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2261 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2262 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2263 | nested_vmcb->save.rip = vmcb->save.rip; |
2264 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2265 | nested_vmcb->save.rax = vmcb->save.rax; | |
2266 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2267 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2268 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2269 | ||
2270 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2271 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2272 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2273 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2274 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2275 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2276 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2277 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2278 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
2279 | |
2280 | if (svm->nrips_enabled) | |
2281 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
2282 | |
2283 | /* | |
2284 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2285 | * to make sure that we do not lose injected events. So check event_inj | |
2286 | * here and copy it to exit_int_info if it is valid. | |
2287 | * Exit_int_info and event_inj can't be both valid because the case | |
2288 | * below only happens on a VMRUN instruction intercept which has | |
2289 | * no valid exit_int_info set. | |
2290 | */ | |
2291 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2292 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2293 | ||
2294 | nc->exit_int_info = vmcb->control.event_inj; | |
2295 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2296 | } | |
2297 | ||
33740e40 JR |
2298 | nested_vmcb->control.tlb_ctl = 0; |
2299 | nested_vmcb->control.event_inj = 0; | |
2300 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2301 | |
2302 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2303 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2304 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2305 | ||
cf74a78b | 2306 | /* Restore the original control entries */ |
0460a979 | 2307 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2308 | |
219b65dc AG |
2309 | kvm_clear_exception_queue(&svm->vcpu); |
2310 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2311 | |
4b16184c JR |
2312 | svm->nested.nested_cr3 = 0; |
2313 | ||
cf74a78b AG |
2314 | /* Restore selected save entries */ |
2315 | svm->vmcb->save.es = hsave->save.es; | |
2316 | svm->vmcb->save.cs = hsave->save.cs; | |
2317 | svm->vmcb->save.ss = hsave->save.ss; | |
2318 | svm->vmcb->save.ds = hsave->save.ds; | |
2319 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2320 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2321 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2322 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2323 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2324 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2325 | if (npt_enabled) { | |
2326 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2327 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2328 | } else { | |
2390218b | 2329 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2330 | } |
2331 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2332 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2333 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2334 | svm->vmcb->save.dr7 = 0; | |
2335 | svm->vmcb->save.cpl = 0; | |
2336 | svm->vmcb->control.exit_int_info = 0; | |
2337 | ||
8d28fec4 RJ |
2338 | mark_all_dirty(svm->vmcb); |
2339 | ||
7597f129 | 2340 | nested_svm_unmap(page); |
cf74a78b | 2341 | |
4b16184c | 2342 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2343 | kvm_mmu_reset_context(&svm->vcpu); |
2344 | kvm_mmu_load(&svm->vcpu); | |
2345 | ||
2346 | return 0; | |
2347 | } | |
3d6368ef | 2348 | |
9738b2c9 | 2349 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2350 | { |
323c3d80 JR |
2351 | /* |
2352 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2353 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2354 | * the kvm msr permission bitmap may contain zero bits |
2355 | */ | |
3d6368ef | 2356 | int i; |
9738b2c9 | 2357 | |
323c3d80 JR |
2358 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2359 | return true; | |
9738b2c9 | 2360 | |
323c3d80 JR |
2361 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2362 | u32 value, p; | |
2363 | u64 offset; | |
9738b2c9 | 2364 | |
323c3d80 JR |
2365 | if (msrpm_offsets[i] == 0xffffffff) |
2366 | break; | |
3d6368ef | 2367 | |
0d6b3537 JR |
2368 | p = msrpm_offsets[i]; |
2369 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 2370 | |
54bf36aa | 2371 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
2372 | return false; |
2373 | ||
2374 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2375 | } | |
3d6368ef | 2376 | |
323c3d80 | 2377 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2378 | |
2379 | return true; | |
3d6368ef AG |
2380 | } |
2381 | ||
52c65a30 JR |
2382 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2383 | { | |
2384 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2385 | return false; | |
2386 | ||
dbe77584 JR |
2387 | if (vmcb->control.asid == 0) |
2388 | return false; | |
2389 | ||
4b16184c JR |
2390 | if (vmcb->control.nested_ctl && !npt_enabled) |
2391 | return false; | |
2392 | ||
52c65a30 JR |
2393 | return true; |
2394 | } | |
2395 | ||
9738b2c9 | 2396 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2397 | { |
9738b2c9 | 2398 | struct vmcb *nested_vmcb; |
e6aa9abd | 2399 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2400 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2401 | struct page *page; |
06fc7772 | 2402 | u64 vmcb_gpa; |
3d6368ef | 2403 | |
06fc7772 | 2404 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2405 | |
7597f129 | 2406 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2407 | if (!nested_vmcb) |
2408 | return false; | |
2409 | ||
52c65a30 JR |
2410 | if (!nested_vmcb_checks(nested_vmcb)) { |
2411 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2412 | nested_vmcb->control.exit_code_hi = 0; | |
2413 | nested_vmcb->control.exit_info_1 = 0; | |
2414 | nested_vmcb->control.exit_info_2 = 0; | |
2415 | ||
2416 | nested_svm_unmap(page); | |
2417 | ||
2418 | return false; | |
2419 | } | |
2420 | ||
b75f4eb3 | 2421 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2422 | nested_vmcb->save.rip, |
2423 | nested_vmcb->control.int_ctl, | |
2424 | nested_vmcb->control.event_inj, | |
2425 | nested_vmcb->control.nested_ctl); | |
2426 | ||
4ee546b4 RJ |
2427 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2428 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2429 | nested_vmcb->control.intercept_exceptions, |
2430 | nested_vmcb->control.intercept); | |
2431 | ||
3d6368ef | 2432 | /* Clear internal status */ |
219b65dc AG |
2433 | kvm_clear_exception_queue(&svm->vcpu); |
2434 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2435 | |
e0231715 JR |
2436 | /* |
2437 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2438 | * restore everything when a VMEXIT occurs | |
2439 | */ | |
defbba56 JR |
2440 | hsave->save.es = vmcb->save.es; |
2441 | hsave->save.cs = vmcb->save.cs; | |
2442 | hsave->save.ss = vmcb->save.ss; | |
2443 | hsave->save.ds = vmcb->save.ds; | |
2444 | hsave->save.gdtr = vmcb->save.gdtr; | |
2445 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2446 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2447 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2448 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2449 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2450 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2451 | hsave->save.rsp = vmcb->save.rsp; |
2452 | hsave->save.rax = vmcb->save.rax; | |
2453 | if (npt_enabled) | |
2454 | hsave->save.cr3 = vmcb->save.cr3; | |
2455 | else | |
9f8fe504 | 2456 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2457 | |
0460a979 | 2458 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2459 | |
f6e78475 | 2460 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2461 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2462 | else | |
2463 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2464 | ||
4b16184c JR |
2465 | if (nested_vmcb->control.nested_ctl) { |
2466 | kvm_mmu_unload(&svm->vcpu); | |
2467 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2468 | nested_svm_init_mmu_context(&svm->vcpu); | |
2469 | } | |
2470 | ||
3d6368ef AG |
2471 | /* Load the nested guest state */ |
2472 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2473 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2474 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2475 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2476 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2477 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2478 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2479 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2480 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2481 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2482 | if (npt_enabled) { | |
2483 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2484 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2485 | } else |
2390218b | 2486 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2487 | |
2488 | /* Guest paging mode is active - reset mmu */ | |
2489 | kvm_mmu_reset_context(&svm->vcpu); | |
2490 | ||
defbba56 | 2491 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2492 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2493 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2494 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2495 | |
3d6368ef AG |
2496 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2497 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2498 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2499 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2500 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2501 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2502 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2503 | ||
f7138538 | 2504 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2505 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2506 | |
aad42c64 | 2507 | /* cache intercepts */ |
4ee546b4 | 2508 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2509 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2510 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2511 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2512 | ||
f40f6a45 | 2513 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2514 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2515 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2516 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2517 | else | |
2518 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2519 | ||
88ab24ad JR |
2520 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2521 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2522 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2523 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2524 | } |
2525 | ||
0d945bd9 | 2526 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2527 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2528 | |
88ab24ad | 2529 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2530 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2531 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2532 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2533 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2534 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2535 | ||
7597f129 | 2536 | nested_svm_unmap(page); |
9738b2c9 | 2537 | |
2030753d JR |
2538 | /* Enter Guest-Mode */ |
2539 | enter_guest_mode(&svm->vcpu); | |
2540 | ||
384c6368 JR |
2541 | /* |
2542 | * Merge guest and host intercepts - must be called with vcpu in | |
2543 | * guest-mode to take affect here | |
2544 | */ | |
2545 | recalc_intercepts(svm); | |
2546 | ||
06fc7772 | 2547 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2548 | |
2af9194d | 2549 | enable_gif(svm); |
3d6368ef | 2550 | |
8d28fec4 RJ |
2551 | mark_all_dirty(svm->vmcb); |
2552 | ||
9738b2c9 | 2553 | return true; |
3d6368ef AG |
2554 | } |
2555 | ||
9966bf68 | 2556 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2557 | { |
2558 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2559 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2560 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2561 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2562 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2563 | to_vmcb->save.star = from_vmcb->save.star; | |
2564 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2565 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2566 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2567 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2568 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2569 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2570 | } |
2571 | ||
851ba692 | 2572 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2573 | { |
9966bf68 | 2574 | struct vmcb *nested_vmcb; |
7597f129 | 2575 | struct page *page; |
9966bf68 | 2576 | |
5542675b AG |
2577 | if (nested_svm_check_permissions(svm)) |
2578 | return 1; | |
2579 | ||
7597f129 | 2580 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2581 | if (!nested_vmcb) |
2582 | return 1; | |
2583 | ||
e3e9ed3d JR |
2584 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2585 | skip_emulated_instruction(&svm->vcpu); | |
2586 | ||
9966bf68 | 2587 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 2588 | nested_svm_unmap(page); |
5542675b AG |
2589 | |
2590 | return 1; | |
2591 | } | |
2592 | ||
851ba692 | 2593 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2594 | { |
9966bf68 | 2595 | struct vmcb *nested_vmcb; |
7597f129 | 2596 | struct page *page; |
9966bf68 | 2597 | |
5542675b AG |
2598 | if (nested_svm_check_permissions(svm)) |
2599 | return 1; | |
2600 | ||
7597f129 | 2601 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2602 | if (!nested_vmcb) |
2603 | return 1; | |
2604 | ||
e3e9ed3d JR |
2605 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2606 | skip_emulated_instruction(&svm->vcpu); | |
2607 | ||
9966bf68 | 2608 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 2609 | nested_svm_unmap(page); |
5542675b AG |
2610 | |
2611 | return 1; | |
2612 | } | |
2613 | ||
851ba692 | 2614 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2615 | { |
3d6368ef AG |
2616 | if (nested_svm_check_permissions(svm)) |
2617 | return 1; | |
2618 | ||
b75f4eb3 RJ |
2619 | /* Save rip after vmrun instruction */ |
2620 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2621 | |
9738b2c9 | 2622 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2623 | return 1; |
2624 | ||
9738b2c9 | 2625 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2626 | goto failed; |
2627 | ||
2628 | return 1; | |
2629 | ||
2630 | failed: | |
2631 | ||
2632 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2633 | svm->vmcb->control.exit_code_hi = 0; | |
2634 | svm->vmcb->control.exit_info_1 = 0; | |
2635 | svm->vmcb->control.exit_info_2 = 0; | |
2636 | ||
2637 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2638 | |
2639 | return 1; | |
2640 | } | |
2641 | ||
851ba692 | 2642 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2643 | { |
2644 | if (nested_svm_check_permissions(svm)) | |
2645 | return 1; | |
2646 | ||
2647 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2648 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2649 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2650 | |
2af9194d | 2651 | enable_gif(svm); |
1371d904 AG |
2652 | |
2653 | return 1; | |
2654 | } | |
2655 | ||
851ba692 | 2656 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2657 | { |
2658 | if (nested_svm_check_permissions(svm)) | |
2659 | return 1; | |
2660 | ||
2661 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2662 | skip_emulated_instruction(&svm->vcpu); | |
2663 | ||
2af9194d | 2664 | disable_gif(svm); |
1371d904 AG |
2665 | |
2666 | /* After a CLGI no interrupts should come */ | |
2667 | svm_clear_vintr(svm); | |
2668 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2669 | ||
decdbf6a JR |
2670 | mark_dirty(svm->vmcb, VMCB_INTR); |
2671 | ||
1371d904 AG |
2672 | return 1; |
2673 | } | |
2674 | ||
851ba692 | 2675 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2676 | { |
2677 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2678 | |
668f198f DK |
2679 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX), |
2680 | kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); | |
ec1ff790 | 2681 | |
ff092385 | 2682 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
668f198f | 2683 | kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
ff092385 AG |
2684 | |
2685 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2686 | skip_emulated_instruction(&svm->vcpu); | |
2687 | return 1; | |
2688 | } | |
2689 | ||
532a46b9 JR |
2690 | static int skinit_interception(struct vcpu_svm *svm) |
2691 | { | |
668f198f | 2692 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
532a46b9 JR |
2693 | |
2694 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2695 | return 1; | |
2696 | } | |
2697 | ||
dab429a7 DK |
2698 | static int wbinvd_interception(struct vcpu_svm *svm) |
2699 | { | |
2700 | kvm_emulate_wbinvd(&svm->vcpu); | |
2701 | return 1; | |
2702 | } | |
2703 | ||
81dd35d4 JR |
2704 | static int xsetbv_interception(struct vcpu_svm *svm) |
2705 | { | |
2706 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2707 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2708 | ||
2709 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2710 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2711 | skip_emulated_instruction(&svm->vcpu); | |
2712 | } | |
2713 | ||
2714 | return 1; | |
2715 | } | |
2716 | ||
851ba692 | 2717 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2718 | { |
37817f29 | 2719 | u16 tss_selector; |
64a7ec06 GN |
2720 | int reason; |
2721 | int int_type = svm->vmcb->control.exit_int_info & | |
2722 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2723 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2724 | uint32_t type = |
2725 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2726 | uint32_t idt_v = | |
2727 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2728 | bool has_error_code = false; |
2729 | u32 error_code = 0; | |
37817f29 IE |
2730 | |
2731 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2732 | |
37817f29 IE |
2733 | if (svm->vmcb->control.exit_info_2 & |
2734 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2735 | reason = TASK_SWITCH_IRET; |
2736 | else if (svm->vmcb->control.exit_info_2 & | |
2737 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2738 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2739 | else if (idt_v) |
64a7ec06 GN |
2740 | reason = TASK_SWITCH_GATE; |
2741 | else | |
2742 | reason = TASK_SWITCH_CALL; | |
2743 | ||
fe8e7f83 GN |
2744 | if (reason == TASK_SWITCH_GATE) { |
2745 | switch (type) { | |
2746 | case SVM_EXITINTINFO_TYPE_NMI: | |
2747 | svm->vcpu.arch.nmi_injected = false; | |
2748 | break; | |
2749 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2750 | if (svm->vmcb->control.exit_info_2 & |
2751 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2752 | has_error_code = true; | |
2753 | error_code = | |
2754 | (u32)svm->vmcb->control.exit_info_2; | |
2755 | } | |
fe8e7f83 GN |
2756 | kvm_clear_exception_queue(&svm->vcpu); |
2757 | break; | |
2758 | case SVM_EXITINTINFO_TYPE_INTR: | |
2759 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2760 | break; | |
2761 | default: | |
2762 | break; | |
2763 | } | |
2764 | } | |
64a7ec06 | 2765 | |
8317c298 GN |
2766 | if (reason != TASK_SWITCH_GATE || |
2767 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2768 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2769 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2770 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2771 | |
7f3d35fd KW |
2772 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
2773 | int_vec = -1; | |
2774 | ||
2775 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
2776 | has_error_code, error_code) == EMULATE_FAIL) { |
2777 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2778 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2779 | svm->vcpu.run->internal.ndata = 0; | |
2780 | return 0; | |
2781 | } | |
2782 | return 1; | |
6aa8b732 AK |
2783 | } |
2784 | ||
851ba692 | 2785 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2786 | { |
5fdbf976 | 2787 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2788 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2789 | return 1; |
6aa8b732 AK |
2790 | } |
2791 | ||
851ba692 | 2792 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2793 | { |
2794 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2795 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2796 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2797 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 2798 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
2799 | return 1; |
2800 | } | |
2801 | ||
851ba692 | 2802 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2803 | { |
df4f3108 AP |
2804 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2805 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2806 | ||
2807 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2808 | skip_emulated_instruction(&svm->vcpu); | |
2809 | return 1; | |
a7052897 MT |
2810 | } |
2811 | ||
851ba692 | 2812 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2813 | { |
51d8b661 | 2814 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2815 | } |
2816 | ||
332b56e4 AK |
2817 | static int rdpmc_interception(struct vcpu_svm *svm) |
2818 | { | |
2819 | int err; | |
2820 | ||
2821 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
2822 | return emulate_on_interception(svm); | |
2823 | ||
2824 | err = kvm_rdpmc(&svm->vcpu); | |
2825 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2826 | ||
2827 | return 1; | |
2828 | } | |
2829 | ||
52eb5a6d XL |
2830 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
2831 | unsigned long val) | |
628afd2a JR |
2832 | { |
2833 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
2834 | bool ret = false; | |
2835 | u64 intercept; | |
2836 | ||
2837 | intercept = svm->nested.intercept; | |
2838 | ||
2839 | if (!is_guest_mode(&svm->vcpu) || | |
2840 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
2841 | return false; | |
2842 | ||
2843 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
2844 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
2845 | ||
2846 | if (cr0 ^ val) { | |
2847 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
2848 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
2849 | } | |
2850 | ||
2851 | return ret; | |
2852 | } | |
2853 | ||
7ff76d58 AP |
2854 | #define CR_VALID (1ULL << 63) |
2855 | ||
2856 | static int cr_interception(struct vcpu_svm *svm) | |
2857 | { | |
2858 | int reg, cr; | |
2859 | unsigned long val; | |
2860 | int err; | |
2861 | ||
2862 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2863 | return emulate_on_interception(svm); | |
2864 | ||
2865 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2866 | return emulate_on_interception(svm); | |
2867 | ||
2868 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
2869 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
2870 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
2871 | else | |
2872 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
2873 | |
2874 | err = 0; | |
2875 | if (cr >= 16) { /* mov to cr */ | |
2876 | cr -= 16; | |
2877 | val = kvm_register_read(&svm->vcpu, reg); | |
2878 | switch (cr) { | |
2879 | case 0: | |
628afd2a JR |
2880 | if (!check_selective_cr0_intercepted(svm, val)) |
2881 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
2882 | else |
2883 | return 1; | |
2884 | ||
7ff76d58 AP |
2885 | break; |
2886 | case 3: | |
2887 | err = kvm_set_cr3(&svm->vcpu, val); | |
2888 | break; | |
2889 | case 4: | |
2890 | err = kvm_set_cr4(&svm->vcpu, val); | |
2891 | break; | |
2892 | case 8: | |
2893 | err = kvm_set_cr8(&svm->vcpu, val); | |
2894 | break; | |
2895 | default: | |
2896 | WARN(1, "unhandled write to CR%d", cr); | |
2897 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2898 | return 1; | |
2899 | } | |
2900 | } else { /* mov from cr */ | |
2901 | switch (cr) { | |
2902 | case 0: | |
2903 | val = kvm_read_cr0(&svm->vcpu); | |
2904 | break; | |
2905 | case 2: | |
2906 | val = svm->vcpu.arch.cr2; | |
2907 | break; | |
2908 | case 3: | |
9f8fe504 | 2909 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2910 | break; |
2911 | case 4: | |
2912 | val = kvm_read_cr4(&svm->vcpu); | |
2913 | break; | |
2914 | case 8: | |
2915 | val = kvm_get_cr8(&svm->vcpu); | |
2916 | break; | |
2917 | default: | |
2918 | WARN(1, "unhandled read from CR%d", cr); | |
2919 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2920 | return 1; | |
2921 | } | |
2922 | kvm_register_write(&svm->vcpu, reg, val); | |
2923 | } | |
2924 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2925 | ||
2926 | return 1; | |
2927 | } | |
2928 | ||
cae3797a AP |
2929 | static int dr_interception(struct vcpu_svm *svm) |
2930 | { | |
2931 | int reg, dr; | |
2932 | unsigned long val; | |
cae3797a | 2933 | |
facb0139 PB |
2934 | if (svm->vcpu.guest_debug == 0) { |
2935 | /* | |
2936 | * No more DR vmexits; force a reload of the debug registers | |
2937 | * and reenter on this instruction. The next vmexit will | |
2938 | * retrieve the full state of the debug registers. | |
2939 | */ | |
2940 | clr_dr_intercepts(svm); | |
2941 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
2942 | return 1; | |
2943 | } | |
2944 | ||
cae3797a AP |
2945 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2946 | return emulate_on_interception(svm); | |
2947 | ||
2948 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2949 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2950 | ||
2951 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
2952 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
2953 | return 1; | |
cae3797a AP |
2954 | val = kvm_register_read(&svm->vcpu, reg); |
2955 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2956 | } else { | |
16f8a6f9 NA |
2957 | if (!kvm_require_dr(&svm->vcpu, dr)) |
2958 | return 1; | |
2959 | kvm_get_dr(&svm->vcpu, dr, &val); | |
2960 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
2961 | } |
2962 | ||
2c46d2ae JR |
2963 | skip_emulated_instruction(&svm->vcpu); |
2964 | ||
cae3797a AP |
2965 | return 1; |
2966 | } | |
2967 | ||
851ba692 | 2968 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2969 | { |
851ba692 | 2970 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2971 | int r; |
851ba692 | 2972 | |
0a5fff19 GN |
2973 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2974 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2975 | r = cr_interception(svm); |
35754c98 | 2976 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 2977 | return r; |
0a5fff19 | 2978 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 2979 | return r; |
1d075434 JR |
2980 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2981 | return 0; | |
2982 | } | |
2983 | ||
48d89b92 | 2984 | static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d NHE |
2985 | { |
2986 | struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu)); | |
4ba76538 | 2987 | return vmcb->control.tsc_offset + host_tsc; |
d5c1785d NHE |
2988 | } |
2989 | ||
609e36d3 | 2990 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 2991 | { |
a2fa3e9f GH |
2992 | struct vcpu_svm *svm = to_svm(vcpu); |
2993 | ||
609e36d3 | 2994 | switch (msr_info->index) { |
af24a4e4 | 2995 | case MSR_IA32_TSC: { |
609e36d3 | 2996 | msr_info->data = svm->vmcb->control.tsc_offset + |
35181e86 | 2997 | kvm_scale_tsc(vcpu, rdtsc()); |
fbc0db76 | 2998 | |
6aa8b732 AK |
2999 | break; |
3000 | } | |
8c06585d | 3001 | case MSR_STAR: |
609e36d3 | 3002 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 3003 | break; |
0e859cac | 3004 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3005 | case MSR_LSTAR: |
609e36d3 | 3006 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3007 | break; |
3008 | case MSR_CSTAR: | |
609e36d3 | 3009 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3010 | break; |
3011 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 3012 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3013 | break; |
3014 | case MSR_SYSCALL_MASK: | |
609e36d3 | 3015 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3016 | break; |
3017 | #endif | |
3018 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3019 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3020 | break; |
3021 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3022 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
3023 | break; |
3024 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3025 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 3026 | break; |
e0231715 JR |
3027 | /* |
3028 | * Nobody will change the following 5 values in the VMCB so we can | |
3029 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3030 | * implemented. | |
3031 | */ | |
a2938c80 | 3032 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 3033 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
3034 | break; |
3035 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 3036 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
3037 | break; |
3038 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 3039 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
3040 | break; |
3041 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 3042 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
3043 | break; |
3044 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 3045 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 3046 | break; |
b286d5d8 | 3047 | case MSR_VM_HSAVE_PA: |
609e36d3 | 3048 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 3049 | break; |
eb6f302e | 3050 | case MSR_VM_CR: |
609e36d3 | 3051 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 3052 | break; |
c8a73f18 | 3053 | case MSR_IA32_UCODE_REV: |
609e36d3 | 3054 | msr_info->data = 0x01000065; |
c8a73f18 | 3055 | break; |
6aa8b732 | 3056 | default: |
609e36d3 | 3057 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3058 | } |
3059 | return 0; | |
3060 | } | |
3061 | ||
851ba692 | 3062 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3063 | { |
668f198f | 3064 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
609e36d3 | 3065 | struct msr_data msr_info; |
6aa8b732 | 3066 | |
609e36d3 PB |
3067 | msr_info.index = ecx; |
3068 | msr_info.host_initiated = false; | |
3069 | if (svm_get_msr(&svm->vcpu, &msr_info)) { | |
59200273 | 3070 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3071 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3072 | } else { |
609e36d3 | 3073 | trace_kvm_msr_read(ecx, msr_info.data); |
af9ca2d7 | 3074 | |
609e36d3 PB |
3075 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, |
3076 | msr_info.data & 0xffffffff); | |
3077 | kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, | |
3078 | msr_info.data >> 32); | |
5fdbf976 | 3079 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3080 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3081 | } |
3082 | return 1; | |
3083 | } | |
3084 | ||
4a810181 JR |
3085 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3086 | { | |
3087 | struct vcpu_svm *svm = to_svm(vcpu); | |
3088 | int svm_dis, chg_mask; | |
3089 | ||
3090 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3091 | return 1; | |
3092 | ||
3093 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3094 | ||
3095 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3096 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3097 | ||
3098 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3099 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3100 | ||
3101 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3102 | ||
3103 | /* check for svm_disable while efer.svme is set */ | |
3104 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3105 | return 1; | |
3106 | ||
3107 | return 0; | |
3108 | } | |
3109 | ||
8fe8ab46 | 3110 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3111 | { |
a2fa3e9f GH |
3112 | struct vcpu_svm *svm = to_svm(vcpu); |
3113 | ||
8fe8ab46 WA |
3114 | u32 ecx = msr->index; |
3115 | u64 data = msr->data; | |
6aa8b732 | 3116 | switch (ecx) { |
f4e1b3c8 | 3117 | case MSR_IA32_TSC: |
8fe8ab46 | 3118 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3119 | break; |
8c06585d | 3120 | case MSR_STAR: |
a2fa3e9f | 3121 | svm->vmcb->save.star = data; |
6aa8b732 | 3122 | break; |
49b14f24 | 3123 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3124 | case MSR_LSTAR: |
a2fa3e9f | 3125 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3126 | break; |
3127 | case MSR_CSTAR: | |
a2fa3e9f | 3128 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3129 | break; |
3130 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3131 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3132 | break; |
3133 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3134 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3135 | break; |
3136 | #endif | |
3137 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3138 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3139 | break; |
3140 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3141 | svm->sysenter_eip = data; |
a2fa3e9f | 3142 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3143 | break; |
3144 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3145 | svm->sysenter_esp = data; |
a2fa3e9f | 3146 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3147 | break; |
a2938c80 | 3148 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3149 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3150 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3151 | __func__, data); | |
24e09cbf JR |
3152 | break; |
3153 | } | |
3154 | if (data & DEBUGCTL_RESERVED_BITS) | |
3155 | return 1; | |
3156 | ||
3157 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3158 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3159 | if (data & (1ULL<<0)) |
3160 | svm_enable_lbrv(svm); | |
3161 | else | |
3162 | svm_disable_lbrv(svm); | |
a2938c80 | 3163 | break; |
b286d5d8 | 3164 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3165 | svm->nested.hsave_msr = data; |
62b9abaa | 3166 | break; |
3c5d0a44 | 3167 | case MSR_VM_CR: |
4a810181 | 3168 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3169 | case MSR_VM_IGNNE: |
a737f256 | 3170 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3171 | break; |
6aa8b732 | 3172 | default: |
8fe8ab46 | 3173 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3174 | } |
3175 | return 0; | |
3176 | } | |
3177 | ||
851ba692 | 3178 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3179 | { |
8fe8ab46 | 3180 | struct msr_data msr; |
668f198f DK |
3181 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
3182 | u64 data = kvm_read_edx_eax(&svm->vcpu); | |
af9ca2d7 | 3183 | |
8fe8ab46 WA |
3184 | msr.data = data; |
3185 | msr.index = ecx; | |
3186 | msr.host_initiated = false; | |
af9ca2d7 | 3187 | |
5fdbf976 | 3188 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
854e8bb1 | 3189 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3190 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3191 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3192 | } else { |
3193 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3194 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3195 | } |
6aa8b732 AK |
3196 | return 1; |
3197 | } | |
3198 | ||
851ba692 | 3199 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3200 | { |
e756fc62 | 3201 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3202 | return wrmsr_interception(svm); |
6aa8b732 | 3203 | else |
851ba692 | 3204 | return rdmsr_interception(svm); |
6aa8b732 AK |
3205 | } |
3206 | ||
851ba692 | 3207 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3208 | { |
3842d135 | 3209 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3210 | svm_clear_vintr(svm); |
85f455f7 | 3211 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3212 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3213 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3214 | return 1; |
3215 | } | |
3216 | ||
565d0998 ML |
3217 | static int pause_interception(struct vcpu_svm *svm) |
3218 | { | |
3219 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3220 | return 1; | |
3221 | } | |
3222 | ||
87c00572 GS |
3223 | static int nop_interception(struct vcpu_svm *svm) |
3224 | { | |
3225 | skip_emulated_instruction(&(svm->vcpu)); | |
3226 | return 1; | |
3227 | } | |
3228 | ||
3229 | static int monitor_interception(struct vcpu_svm *svm) | |
3230 | { | |
3231 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
3232 | return nop_interception(svm); | |
3233 | } | |
3234 | ||
3235 | static int mwait_interception(struct vcpu_svm *svm) | |
3236 | { | |
3237 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
3238 | return nop_interception(svm); | |
3239 | } | |
3240 | ||
09941fbb | 3241 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3242 | [SVM_EXIT_READ_CR0] = cr_interception, |
3243 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3244 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3245 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 3246 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 3247 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3248 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3249 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3250 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3251 | [SVM_EXIT_READ_DR0] = dr_interception, |
3252 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3253 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3254 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3255 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3256 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3257 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3258 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3259 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3260 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3261 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3262 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3263 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3264 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3265 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3266 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3267 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3268 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3269 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3270 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3271 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3272 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
54a20552 | 3273 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
e0231715 | 3274 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 3275 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3276 | [SVM_EXIT_SMI] = nop_on_interception, |
3277 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3278 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 3279 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 3280 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3281 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3282 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3283 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3284 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3285 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3286 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3287 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3288 | [SVM_EXIT_MSR] = msr_interception, |
3289 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3290 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3291 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3292 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3293 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3294 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3295 | [SVM_EXIT_STGI] = stgi_interception, |
3296 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3297 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 3298 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
3299 | [SVM_EXIT_MONITOR] = monitor_interception, |
3300 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 3301 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3302 | [SVM_EXIT_NPF] = pf_interception, |
64d60670 | 3303 | [SVM_EXIT_RSM] = emulate_on_interception, |
6aa8b732 AK |
3304 | }; |
3305 | ||
ae8cc059 | 3306 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
3307 | { |
3308 | struct vcpu_svm *svm = to_svm(vcpu); | |
3309 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3310 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3311 | ||
3312 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
3313 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
3314 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
3315 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
3316 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
3317 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
3318 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
3319 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
3320 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
3321 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
3322 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
3323 | pr_err("%-20s%d\n", "asid:", control->asid); | |
3324 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
3325 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
3326 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
3327 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
3328 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
3329 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
3330 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
3331 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
3332 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
3333 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
3334 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
3335 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); | |
3336 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
3337 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
3338 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
3f10c846 | 3339 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
3340 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
3341 | "es:", | |
3342 | save->es.selector, save->es.attrib, | |
3343 | save->es.limit, save->es.base); | |
3344 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3345 | "cs:", | |
3346 | save->cs.selector, save->cs.attrib, | |
3347 | save->cs.limit, save->cs.base); | |
3348 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3349 | "ss:", | |
3350 | save->ss.selector, save->ss.attrib, | |
3351 | save->ss.limit, save->ss.base); | |
3352 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3353 | "ds:", | |
3354 | save->ds.selector, save->ds.attrib, | |
3355 | save->ds.limit, save->ds.base); | |
3356 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3357 | "fs:", | |
3358 | save->fs.selector, save->fs.attrib, | |
3359 | save->fs.limit, save->fs.base); | |
3360 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3361 | "gs:", | |
3362 | save->gs.selector, save->gs.attrib, | |
3363 | save->gs.limit, save->gs.base); | |
3364 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3365 | "gdtr:", | |
3366 | save->gdtr.selector, save->gdtr.attrib, | |
3367 | save->gdtr.limit, save->gdtr.base); | |
3368 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3369 | "ldtr:", | |
3370 | save->ldtr.selector, save->ldtr.attrib, | |
3371 | save->ldtr.limit, save->ldtr.base); | |
3372 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3373 | "idtr:", | |
3374 | save->idtr.selector, save->idtr.attrib, | |
3375 | save->idtr.limit, save->idtr.base); | |
3376 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3377 | "tr:", | |
3378 | save->tr.selector, save->tr.attrib, | |
3379 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
3380 | pr_err("cpl: %d efer: %016llx\n", |
3381 | save->cpl, save->efer); | |
ae8cc059 JP |
3382 | pr_err("%-15s %016llx %-13s %016llx\n", |
3383 | "cr0:", save->cr0, "cr2:", save->cr2); | |
3384 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3385 | "cr3:", save->cr3, "cr4:", save->cr4); | |
3386 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3387 | "dr6:", save->dr6, "dr7:", save->dr7); | |
3388 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3389 | "rip:", save->rip, "rflags:", save->rflags); | |
3390 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3391 | "rsp:", save->rsp, "rax:", save->rax); | |
3392 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3393 | "star:", save->star, "lstar:", save->lstar); | |
3394 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3395 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
3396 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3397 | "kernel_gs_base:", save->kernel_gs_base, | |
3398 | "sysenter_cs:", save->sysenter_cs); | |
3399 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3400 | "sysenter_esp:", save->sysenter_esp, | |
3401 | "sysenter_eip:", save->sysenter_eip); | |
3402 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3403 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
3404 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3405 | "br_from:", save->br_from, "br_to:", save->br_to); | |
3406 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3407 | "excp_from:", save->last_excp_from, | |
3408 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
3409 | } |
3410 | ||
586f9607 AK |
3411 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3412 | { | |
3413 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3414 | ||
3415 | *info1 = control->exit_info_1; | |
3416 | *info2 = control->exit_info_2; | |
3417 | } | |
3418 | ||
851ba692 | 3419 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3420 | { |
04d2cc77 | 3421 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3422 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3423 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3424 | |
4ee546b4 | 3425 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3426 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3427 | if (npt_enabled) | |
3428 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3429 | |
cd3ff653 JR |
3430 | if (unlikely(svm->nested.exit_required)) { |
3431 | nested_svm_vmexit(svm); | |
3432 | svm->nested.exit_required = false; | |
3433 | ||
3434 | return 1; | |
3435 | } | |
3436 | ||
2030753d | 3437 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3438 | int vmexit; |
3439 | ||
d8cabddf JR |
3440 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3441 | svm->vmcb->control.exit_info_1, | |
3442 | svm->vmcb->control.exit_info_2, | |
3443 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
3444 | svm->vmcb->control.exit_int_info_err, |
3445 | KVM_ISA_SVM); | |
d8cabddf | 3446 | |
410e4d57 JR |
3447 | vmexit = nested_svm_exit_special(svm); |
3448 | ||
3449 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3450 | vmexit = nested_svm_exit_handled(svm); | |
3451 | ||
3452 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3453 | return 1; |
cf74a78b AG |
3454 | } |
3455 | ||
a5c3832d JR |
3456 | svm_complete_interrupts(svm); |
3457 | ||
04d2cc77 AK |
3458 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3459 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3460 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3461 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3462 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3463 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3464 | return 0; |
3465 | } | |
3466 | ||
a2fa3e9f | 3467 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3468 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3469 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3470 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 3471 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 3472 | "exit_code 0x%x\n", |
b8688d51 | 3473 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3474 | exit_code); |
3475 | ||
9d8f549d | 3476 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3477 | || !svm_exit_handlers[exit_code]) { |
faac2458 | 3478 | WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code); |
2bc19dc3 MT |
3479 | kvm_queue_exception(vcpu, UD_VECTOR); |
3480 | return 1; | |
6aa8b732 AK |
3481 | } |
3482 | ||
851ba692 | 3483 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3484 | } |
3485 | ||
3486 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3487 | { | |
3488 | int cpu = raw_smp_processor_id(); | |
3489 | ||
0fe1e009 TH |
3490 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3491 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3492 | load_TR_desc(); |
3493 | } | |
3494 | ||
e756fc62 | 3495 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3496 | { |
3497 | int cpu = raw_smp_processor_id(); | |
3498 | ||
0fe1e009 | 3499 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3500 | |
4b656b12 | 3501 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3502 | if (svm->asid_generation != sd->asid_generation) |
3503 | new_asid(svm, sd); | |
6aa8b732 AK |
3504 | } |
3505 | ||
95ba8273 GN |
3506 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3507 | { | |
3508 | struct vcpu_svm *svm = to_svm(vcpu); | |
3509 | ||
3510 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3511 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3512 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3513 | ++vcpu->stat.nmi_injections; |
3514 | } | |
6aa8b732 | 3515 | |
85f455f7 | 3516 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3517 | { |
3518 | struct vmcb_control_area *control; | |
3519 | ||
e756fc62 | 3520 | control = &svm->vmcb->control; |
85f455f7 | 3521 | control->int_vector = irq; |
6aa8b732 AK |
3522 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3523 | control->int_ctl |= V_IRQ_MASK | | |
3524 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3525 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3526 | } |
3527 | ||
66fd3f7f | 3528 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3529 | { |
3530 | struct vcpu_svm *svm = to_svm(vcpu); | |
3531 | ||
2af9194d | 3532 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3533 | |
9fb2d2b4 GN |
3534 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3535 | ++vcpu->stat.irq_injections; | |
3536 | ||
219b65dc AG |
3537 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3538 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3539 | } |
3540 | ||
95ba8273 | 3541 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3542 | { |
3543 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3544 | |
2030753d | 3545 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3546 | return; |
3547 | ||
596f3142 RK |
3548 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
3549 | ||
95ba8273 | 3550 | if (irr == -1) |
aaacfc9a JR |
3551 | return; |
3552 | ||
95ba8273 | 3553 | if (tpr >= irr) |
4ee546b4 | 3554 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3555 | } |
aaacfc9a | 3556 | |
8d14695f YZ |
3557 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
3558 | { | |
3559 | return; | |
3560 | } | |
3561 | ||
d50ab6c1 | 3562 | static int svm_cpu_uses_apicv(struct kvm_vcpu *vcpu) |
c7c9c56c YZ |
3563 | { |
3564 | return 0; | |
3565 | } | |
3566 | ||
6308630b | 3567 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
3568 | { |
3569 | return; | |
3570 | } | |
3571 | ||
a20ed54d YZ |
3572 | static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
3573 | { | |
3574 | return; | |
3575 | } | |
3576 | ||
95ba8273 GN |
3577 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3578 | { | |
3579 | struct vcpu_svm *svm = to_svm(vcpu); | |
3580 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3581 | int ret; |
3582 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3583 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3584 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3585 | ||
3586 | return ret; | |
aaacfc9a JR |
3587 | } |
3588 | ||
3cfc3092 JK |
3589 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3590 | { | |
3591 | struct vcpu_svm *svm = to_svm(vcpu); | |
3592 | ||
3593 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3594 | } | |
3595 | ||
3596 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3597 | { | |
3598 | struct vcpu_svm *svm = to_svm(vcpu); | |
3599 | ||
3600 | if (masked) { | |
3601 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3602 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3603 | } else { |
3604 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3605 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3606 | } |
3607 | } | |
3608 | ||
78646121 GN |
3609 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3610 | { | |
3611 | struct vcpu_svm *svm = to_svm(vcpu); | |
3612 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3613 | int ret; |
3614 | ||
3615 | if (!gif_set(svm) || | |
3616 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3617 | return 0; | |
3618 | ||
f6e78475 | 3619 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3620 | |
2030753d | 3621 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3622 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3623 | ||
3624 | return ret; | |
78646121 GN |
3625 | } |
3626 | ||
c9a7953f | 3627 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3628 | { |
219b65dc | 3629 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3630 | |
e0231715 JR |
3631 | /* |
3632 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3633 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3634 | * get that intercept, this function will be called again though and | |
3635 | * we'll get the vintr intercept. | |
3636 | */ | |
8fe54654 | 3637 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3638 | svm_set_vintr(svm); |
3639 | svm_inject_irq(svm, 0x0); | |
3640 | } | |
85f455f7 ED |
3641 | } |
3642 | ||
c9a7953f | 3643 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3644 | { |
04d2cc77 | 3645 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3646 | |
44c11430 GN |
3647 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3648 | == HF_NMI_MASK) | |
c9a7953f | 3649 | return; /* IRET will cause a vm exit */ |
44c11430 | 3650 | |
e0231715 JR |
3651 | /* |
3652 | * Something prevents NMI from been injected. Single step over possible | |
3653 | * problem (IRET or exception injection or interrupt shadow) | |
3654 | */ | |
6be7d306 | 3655 | svm->nmi_singlestep = true; |
44c11430 | 3656 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
3657 | } |
3658 | ||
cbc94022 IE |
3659 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3660 | { | |
3661 | return 0; | |
3662 | } | |
3663 | ||
d9e368d6 AK |
3664 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3665 | { | |
38e5e92f JR |
3666 | struct vcpu_svm *svm = to_svm(vcpu); |
3667 | ||
3668 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3669 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3670 | else | |
3671 | svm->asid_generation--; | |
d9e368d6 AK |
3672 | } |
3673 | ||
04d2cc77 AK |
3674 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3675 | { | |
3676 | } | |
3677 | ||
d7bf8221 JR |
3678 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3679 | { | |
3680 | struct vcpu_svm *svm = to_svm(vcpu); | |
3681 | ||
2030753d | 3682 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3683 | return; |
3684 | ||
4ee546b4 | 3685 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3686 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3687 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3688 | } |
3689 | } | |
3690 | ||
649d6864 JR |
3691 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3692 | { | |
3693 | struct vcpu_svm *svm = to_svm(vcpu); | |
3694 | u64 cr8; | |
3695 | ||
2030753d | 3696 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3697 | return; |
3698 | ||
649d6864 JR |
3699 | cr8 = kvm_get_cr8(vcpu); |
3700 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3701 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3702 | } | |
3703 | ||
9222be18 GN |
3704 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3705 | { | |
3706 | u8 vector; | |
3707 | int type; | |
3708 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3709 | unsigned int3_injected = svm->int3_injected; |
3710 | ||
3711 | svm->int3_injected = 0; | |
9222be18 | 3712 | |
bd3d1ec3 AK |
3713 | /* |
3714 | * If we've made progress since setting HF_IRET_MASK, we've | |
3715 | * executed an IRET and can allow NMI injection. | |
3716 | */ | |
3717 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3718 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3719 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3720 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3721 | } | |
44c11430 | 3722 | |
9222be18 GN |
3723 | svm->vcpu.arch.nmi_injected = false; |
3724 | kvm_clear_exception_queue(&svm->vcpu); | |
3725 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3726 | ||
3727 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3728 | return; | |
3729 | ||
3842d135 AK |
3730 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3731 | ||
9222be18 GN |
3732 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3733 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3734 | ||
3735 | switch (type) { | |
3736 | case SVM_EXITINTINFO_TYPE_NMI: | |
3737 | svm->vcpu.arch.nmi_injected = true; | |
3738 | break; | |
3739 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3740 | /* |
3741 | * In case of software exceptions, do not reinject the vector, | |
3742 | * but re-execute the instruction instead. Rewind RIP first | |
3743 | * if we emulated INT3 before. | |
3744 | */ | |
3745 | if (kvm_exception_is_soft(vector)) { | |
3746 | if (vector == BP_VECTOR && int3_injected && | |
3747 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3748 | kvm_rip_write(&svm->vcpu, | |
3749 | kvm_rip_read(&svm->vcpu) - | |
3750 | int3_injected); | |
9222be18 | 3751 | break; |
66b7138f | 3752 | } |
9222be18 GN |
3753 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3754 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3755 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3756 | |
3757 | } else | |
ce7ddec4 | 3758 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3759 | break; |
3760 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3761 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3762 | break; |
3763 | default: | |
3764 | break; | |
3765 | } | |
3766 | } | |
3767 | ||
b463a6f7 AK |
3768 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3769 | { | |
3770 | struct vcpu_svm *svm = to_svm(vcpu); | |
3771 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3772 | ||
3773 | control->exit_int_info = control->event_inj; | |
3774 | control->exit_int_info_err = control->event_inj_err; | |
3775 | control->event_inj = 0; | |
3776 | svm_complete_interrupts(svm); | |
3777 | } | |
3778 | ||
851ba692 | 3779 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3780 | { |
a2fa3e9f | 3781 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3782 | |
2041a06a JR |
3783 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3784 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3785 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3786 | ||
cd3ff653 JR |
3787 | /* |
3788 | * A vmexit emulation is required before the vcpu can be executed | |
3789 | * again. | |
3790 | */ | |
3791 | if (unlikely(svm->nested.exit_required)) | |
3792 | return; | |
3793 | ||
e756fc62 | 3794 | pre_svm_run(svm); |
6aa8b732 | 3795 | |
649d6864 JR |
3796 | sync_lapic_to_cr8(vcpu); |
3797 | ||
cda0ffdd | 3798 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3799 | |
04d2cc77 AK |
3800 | clgi(); |
3801 | ||
3802 | local_irq_enable(); | |
36241b8c | 3803 | |
6aa8b732 | 3804 | asm volatile ( |
7454766f AK |
3805 | "push %%" _ASM_BP "; \n\t" |
3806 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
3807 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
3808 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
3809 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
3810 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
3811 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 3812 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3813 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3814 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3815 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3816 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3817 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3818 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3819 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3820 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3821 | #endif |
3822 | ||
6aa8b732 | 3823 | /* Enter guest mode */ |
7454766f AK |
3824 | "push %%" _ASM_AX " \n\t" |
3825 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
3826 | __ex(SVM_VMLOAD) "\n\t" |
3827 | __ex(SVM_VMRUN) "\n\t" | |
3828 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 3829 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
3830 | |
3831 | /* Save guest registers, load host registers */ | |
7454766f AK |
3832 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
3833 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
3834 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
3835 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
3836 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
3837 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3838 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3839 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3840 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3841 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3842 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3843 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3844 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3845 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3846 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3847 | #endif |
7454766f | 3848 | "pop %%" _ASM_BP |
6aa8b732 | 3849 | : |
fb3f0f51 | 3850 | : [svm]"a"(svm), |
6aa8b732 | 3851 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3852 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3853 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3854 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3855 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3856 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3857 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3858 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3859 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3860 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3861 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3862 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3863 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3864 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3865 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3866 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3867 | #endif |
54a08c04 LV |
3868 | : "cc", "memory" |
3869 | #ifdef CONFIG_X86_64 | |
7454766f | 3870 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 3871 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
3872 | #else |
3873 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
3874 | #endif |
3875 | ); | |
6aa8b732 | 3876 | |
82ca2d10 AK |
3877 | #ifdef CONFIG_X86_64 |
3878 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3879 | #else | |
dacccfdd | 3880 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3881 | #ifndef CONFIG_X86_32_LAZY_GS |
3882 | loadsegment(gs, svm->host.gs); | |
3883 | #endif | |
9581d442 | 3884 | #endif |
6aa8b732 AK |
3885 | |
3886 | reload_tss(vcpu); | |
3887 | ||
56ba47dd AK |
3888 | local_irq_disable(); |
3889 | ||
13c34e07 AK |
3890 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3891 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3892 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3893 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3894 | ||
1e2b1dd7 JK |
3895 | trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM); |
3896 | ||
3781c01c JR |
3897 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3898 | kvm_before_handle_nmi(&svm->vcpu); | |
3899 | ||
3900 | stgi(); | |
3901 | ||
3902 | /* Any pending NMI will happen here */ | |
3903 | ||
3904 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3905 | kvm_after_handle_nmi(&svm->vcpu); | |
3906 | ||
d7bf8221 JR |
3907 | sync_cr8_to_lapic(vcpu); |
3908 | ||
a2fa3e9f | 3909 | svm->next_rip = 0; |
9222be18 | 3910 | |
38e5e92f JR |
3911 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3912 | ||
631bc487 GN |
3913 | /* if exit due to PF check for async PF */ |
3914 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3915 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3916 | ||
6de4f3ad AK |
3917 | if (npt_enabled) { |
3918 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3919 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3920 | } | |
fe5913e4 JR |
3921 | |
3922 | /* | |
3923 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3924 | * change the physical cpu | |
3925 | */ | |
3926 | if (unlikely(svm->vmcb->control.exit_code == | |
3927 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3928 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3929 | |
3930 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3931 | } |
3932 | ||
6aa8b732 AK |
3933 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3934 | { | |
a2fa3e9f GH |
3935 | struct vcpu_svm *svm = to_svm(vcpu); |
3936 | ||
3937 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3938 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3939 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3940 | } |
3941 | ||
1c97f0a0 JR |
3942 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3943 | { | |
3944 | struct vcpu_svm *svm = to_svm(vcpu); | |
3945 | ||
3946 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3947 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3948 | |
3949 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3950 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3951 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3952 | |
f40f6a45 | 3953 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3954 | } |
3955 | ||
6aa8b732 AK |
3956 | static int is_disabled(void) |
3957 | { | |
6031a61c JR |
3958 | u64 vm_cr; |
3959 | ||
3960 | rdmsrl(MSR_VM_CR, vm_cr); | |
3961 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3962 | return 1; | |
3963 | ||
6aa8b732 AK |
3964 | return 0; |
3965 | } | |
3966 | ||
102d8325 IM |
3967 | static void |
3968 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3969 | { | |
3970 | /* | |
3971 | * Patch in the VMMCALL instruction: | |
3972 | */ | |
3973 | hypercall[0] = 0x0f; | |
3974 | hypercall[1] = 0x01; | |
3975 | hypercall[2] = 0xd9; | |
102d8325 IM |
3976 | } |
3977 | ||
002c7f7c YS |
3978 | static void svm_check_processor_compat(void *rtn) |
3979 | { | |
3980 | *(int *)rtn = 0; | |
3981 | } | |
3982 | ||
774ead3a AK |
3983 | static bool svm_cpu_has_accelerated_tpr(void) |
3984 | { | |
3985 | return false; | |
3986 | } | |
3987 | ||
6d396b55 PB |
3988 | static bool svm_has_high_real_mode_segbase(void) |
3989 | { | |
3990 | return true; | |
3991 | } | |
3992 | ||
fc07e76a PB |
3993 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
3994 | { | |
3995 | return 0; | |
3996 | } | |
3997 | ||
0e851880 SY |
3998 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3999 | { | |
6092d3d3 JR |
4000 | struct vcpu_svm *svm = to_svm(vcpu); |
4001 | ||
4002 | /* Update nrips enabled cache */ | |
4003 | svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu); | |
0e851880 SY |
4004 | } |
4005 | ||
d4330ef2 JR |
4006 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
4007 | { | |
c2c63a49 | 4008 | switch (func) { |
4c62a2dc JR |
4009 | case 0x80000001: |
4010 | if (nested) | |
4011 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
4012 | break; | |
c2c63a49 JR |
4013 | case 0x8000000A: |
4014 | entry->eax = 1; /* SVM revision 1 */ | |
4015 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
4016 | ASID emulation to nested SVM */ | |
4017 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
4018 | entry->edx = 0; /* Per default do not support any |
4019 | additional features */ | |
4020 | ||
4021 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 4022 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 4023 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 4024 | |
3d4aeaad JR |
4025 | /* Support NPT for the guest if enabled */ |
4026 | if (npt_enabled) | |
4027 | entry->edx |= SVM_FEATURE_NPT; | |
4028 | ||
c2c63a49 JR |
4029 | break; |
4030 | } | |
d4330ef2 JR |
4031 | } |
4032 | ||
17cc3935 | 4033 | static int svm_get_lpage_level(void) |
344f414f | 4034 | { |
17cc3935 | 4035 | return PT_PDPE_LEVEL; |
344f414f JR |
4036 | } |
4037 | ||
4e47c7a6 SY |
4038 | static bool svm_rdtscp_supported(void) |
4039 | { | |
4040 | return false; | |
4041 | } | |
4042 | ||
ad756a16 MJ |
4043 | static bool svm_invpcid_supported(void) |
4044 | { | |
4045 | return false; | |
4046 | } | |
4047 | ||
93c4adc7 PB |
4048 | static bool svm_mpx_supported(void) |
4049 | { | |
4050 | return false; | |
4051 | } | |
4052 | ||
55412b2e WL |
4053 | static bool svm_xsaves_supported(void) |
4054 | { | |
4055 | return false; | |
4056 | } | |
4057 | ||
f5f48ee1 SY |
4058 | static bool svm_has_wbinvd_exit(void) |
4059 | { | |
4060 | return true; | |
4061 | } | |
4062 | ||
02daab21 AK |
4063 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
4064 | { | |
4065 | struct vcpu_svm *svm = to_svm(vcpu); | |
4066 | ||
18c918c5 | 4067 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 4068 | update_cr0_intercept(svm); |
02daab21 AK |
4069 | } |
4070 | ||
8061252e | 4071 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4072 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 4073 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4074 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 4075 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 4076 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 4077 | |
09941fbb | 4078 | static const struct __x86_intercept { |
cfec82cb JR |
4079 | u32 exit_code; |
4080 | enum x86_intercept_stage stage; | |
cfec82cb JR |
4081 | } x86_intercept_map[] = { |
4082 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
4083 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4084 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4085 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4086 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
4087 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
4088 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
4089 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
4090 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
4091 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
4092 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
4093 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
4094 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
4095 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
4096 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
4097 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
4098 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
4099 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
4100 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
4101 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
4102 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
4103 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
4104 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
4105 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
4106 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
4107 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
4108 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
4109 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
4110 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
4111 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
4112 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
4113 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
4114 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
4115 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
4116 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
4117 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
4118 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
4119 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
4120 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
4121 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
4122 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
4123 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
4124 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
4125 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
4126 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
4127 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
4128 | }; |
4129 | ||
8061252e | 4130 | #undef PRE_EX |
cfec82cb | 4131 | #undef POST_EX |
d7eb8203 | 4132 | #undef POST_MEM |
cfec82cb | 4133 | |
8a76d7f2 JR |
4134 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
4135 | struct x86_instruction_info *info, | |
4136 | enum x86_intercept_stage stage) | |
4137 | { | |
cfec82cb JR |
4138 | struct vcpu_svm *svm = to_svm(vcpu); |
4139 | int vmexit, ret = X86EMUL_CONTINUE; | |
4140 | struct __x86_intercept icpt_info; | |
4141 | struct vmcb *vmcb = svm->vmcb; | |
4142 | ||
4143 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
4144 | goto out; | |
4145 | ||
4146 | icpt_info = x86_intercept_map[info->intercept]; | |
4147 | ||
40e19b51 | 4148 | if (stage != icpt_info.stage) |
cfec82cb JR |
4149 | goto out; |
4150 | ||
4151 | switch (icpt_info.exit_code) { | |
4152 | case SVM_EXIT_READ_CR0: | |
4153 | if (info->intercept == x86_intercept_cr_read) | |
4154 | icpt_info.exit_code += info->modrm_reg; | |
4155 | break; | |
4156 | case SVM_EXIT_WRITE_CR0: { | |
4157 | unsigned long cr0, val; | |
4158 | u64 intercept; | |
4159 | ||
4160 | if (info->intercept == x86_intercept_cr_write) | |
4161 | icpt_info.exit_code += info->modrm_reg; | |
4162 | ||
62baf44c JK |
4163 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
4164 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
4165 | break; |
4166 | ||
4167 | intercept = svm->nested.intercept; | |
4168 | ||
4169 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
4170 | break; | |
4171 | ||
4172 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4173 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4174 | ||
4175 | if (info->intercept == x86_intercept_lmsw) { | |
4176 | cr0 &= 0xfUL; | |
4177 | val &= 0xfUL; | |
4178 | /* lmsw can't clear PE - catch this here */ | |
4179 | if (cr0 & X86_CR0_PE) | |
4180 | val |= X86_CR0_PE; | |
4181 | } | |
4182 | ||
4183 | if (cr0 ^ val) | |
4184 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4185 | ||
4186 | break; | |
4187 | } | |
3b88e41a JR |
4188 | case SVM_EXIT_READ_DR0: |
4189 | case SVM_EXIT_WRITE_DR0: | |
4190 | icpt_info.exit_code += info->modrm_reg; | |
4191 | break; | |
8061252e JR |
4192 | case SVM_EXIT_MSR: |
4193 | if (info->intercept == x86_intercept_wrmsr) | |
4194 | vmcb->control.exit_info_1 = 1; | |
4195 | else | |
4196 | vmcb->control.exit_info_1 = 0; | |
4197 | break; | |
bf608f88 JR |
4198 | case SVM_EXIT_PAUSE: |
4199 | /* | |
4200 | * We get this for NOP only, but pause | |
4201 | * is rep not, check this here | |
4202 | */ | |
4203 | if (info->rep_prefix != REPE_PREFIX) | |
4204 | goto out; | |
f6511935 JR |
4205 | case SVM_EXIT_IOIO: { |
4206 | u64 exit_info; | |
4207 | u32 bytes; | |
4208 | ||
f6511935 JR |
4209 | if (info->intercept == x86_intercept_in || |
4210 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
4211 | exit_info = ((info->src_val & 0xffff) << 16) | |
4212 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 4213 | bytes = info->dst_bytes; |
6493f157 | 4214 | } else { |
6cbc5f5a | 4215 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 4216 | bytes = info->src_bytes; |
f6511935 JR |
4217 | } |
4218 | ||
4219 | if (info->intercept == x86_intercept_outs || | |
4220 | info->intercept == x86_intercept_ins) | |
4221 | exit_info |= SVM_IOIO_STR_MASK; | |
4222 | ||
4223 | if (info->rep_prefix) | |
4224 | exit_info |= SVM_IOIO_REP_MASK; | |
4225 | ||
4226 | bytes = min(bytes, 4u); | |
4227 | ||
4228 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4229 | ||
4230 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4231 | ||
4232 | vmcb->control.exit_info_1 = exit_info; | |
4233 | vmcb->control.exit_info_2 = info->next_rip; | |
4234 | ||
4235 | break; | |
4236 | } | |
cfec82cb JR |
4237 | default: |
4238 | break; | |
4239 | } | |
4240 | ||
f104765b BD |
4241 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
4242 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
4243 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
4244 | vmcb->control.exit_code = icpt_info.exit_code; |
4245 | vmexit = nested_svm_exit_handled(svm); | |
4246 | ||
4247 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4248 | : X86EMUL_CONTINUE; | |
4249 | ||
4250 | out: | |
4251 | return ret; | |
8a76d7f2 JR |
4252 | } |
4253 | ||
a547c6db YZ |
4254 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
4255 | { | |
4256 | local_irq_enable(); | |
4257 | } | |
4258 | ||
ae97a3b8 RK |
4259 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
4260 | { | |
4261 | } | |
4262 | ||
cbdd1bea | 4263 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4264 | .cpu_has_kvm_support = has_svm, |
4265 | .disabled_by_bios = is_disabled, | |
4266 | .hardware_setup = svm_hardware_setup, | |
4267 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4268 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4269 | .hardware_enable = svm_hardware_enable, |
4270 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4271 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6d396b55 | 4272 | .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase, |
6aa8b732 AK |
4273 | |
4274 | .vcpu_create = svm_create_vcpu, | |
4275 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4276 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4277 | |
04d2cc77 | 4278 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4279 | .vcpu_load = svm_vcpu_load, |
4280 | .vcpu_put = svm_vcpu_put, | |
4281 | ||
a96036b8 | 4282 | .update_bp_intercept = update_bp_intercept, |
6aa8b732 AK |
4283 | .get_msr = svm_get_msr, |
4284 | .set_msr = svm_set_msr, | |
4285 | .get_segment_base = svm_get_segment_base, | |
4286 | .get_segment = svm_get_segment, | |
4287 | .set_segment = svm_set_segment, | |
2e4d2653 | 4288 | .get_cpl = svm_get_cpl, |
1747fb71 | 4289 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4290 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4291 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4292 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4293 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4294 | .set_cr3 = svm_set_cr3, |
4295 | .set_cr4 = svm_set_cr4, | |
4296 | .set_efer = svm_set_efer, | |
4297 | .get_idt = svm_get_idt, | |
4298 | .set_idt = svm_set_idt, | |
4299 | .get_gdt = svm_get_gdt, | |
4300 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
4301 | .get_dr6 = svm_get_dr6, |
4302 | .set_dr6 = svm_set_dr6, | |
020df079 | 4303 | .set_dr7 = svm_set_dr7, |
facb0139 | 4304 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 4305 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4306 | .get_rflags = svm_get_rflags, |
4307 | .set_rflags = svm_set_rflags, | |
0fdd74f7 | 4308 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4309 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4310 | |
6aa8b732 | 4311 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4312 | |
6aa8b732 | 4313 | .run = svm_vcpu_run, |
04d2cc77 | 4314 | .handle_exit = handle_exit, |
6aa8b732 | 4315 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4316 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4317 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4318 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4319 | .set_irq = svm_set_irq, |
95ba8273 | 4320 | .set_nmi = svm_inject_nmi, |
298101da | 4321 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4322 | .cancel_injection = svm_cancel_injection, |
78646121 | 4323 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4324 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4325 | .get_nmi_mask = svm_get_nmi_mask, |
4326 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4327 | .enable_nmi_window = enable_nmi_window, |
4328 | .enable_irq_window = enable_irq_window, | |
4329 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 4330 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
d50ab6c1 | 4331 | .cpu_uses_apicv = svm_cpu_uses_apicv, |
c7c9c56c | 4332 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
a20ed54d | 4333 | .sync_pir_to_irr = svm_sync_pir_to_irr, |
cbc94022 IE |
4334 | |
4335 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4336 | .get_tdp_level = get_npt_level, |
4b12f0de | 4337 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4338 | |
586f9607 | 4339 | .get_exit_info = svm_get_exit_info, |
586f9607 | 4340 | |
17cc3935 | 4341 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4342 | |
4343 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4344 | |
4345 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 4346 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 4347 | .mpx_supported = svm_mpx_supported, |
55412b2e | 4348 | .xsaves_supported = svm_xsaves_supported, |
d4330ef2 JR |
4349 | |
4350 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4351 | |
4352 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 4353 | |
ba904635 | 4354 | .read_tsc_offset = svm_read_tsc_offset, |
99e3e30a | 4355 | .write_tsc_offset = svm_write_tsc_offset, |
58ea6767 | 4356 | .adjust_tsc_offset_guest = svm_adjust_tsc_offset_guest, |
d5c1785d | 4357 | .read_l1_tsc = svm_read_l1_tsc, |
1c97f0a0 JR |
4358 | |
4359 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4360 | |
4361 | .check_intercept = svm_check_intercept, | |
a547c6db | 4362 | .handle_external_intr = svm_handle_external_intr, |
ae97a3b8 RK |
4363 | |
4364 | .sched_in = svm_sched_in, | |
25462f7f WH |
4365 | |
4366 | .pmu_ops = &amd_pmu_ops, | |
6aa8b732 AK |
4367 | }; |
4368 | ||
4369 | static int __init svm_init(void) | |
4370 | { | |
cb498ea2 | 4371 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4372 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4373 | } |
4374 | ||
4375 | static void __exit svm_exit(void) | |
4376 | { | |
cb498ea2 | 4377 | kvm_exit(); |
6aa8b732 AK |
4378 | } |
4379 | ||
4380 | module_init(svm_init) | |
4381 | module_exit(svm_exit) |