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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
631bc487 | 34 | #include <asm/kvm_para.h> |
6aa8b732 | 35 | |
63d1142f | 36 | #include <asm/virtext.h> |
229456fc | 37 | #include "trace.h" |
63d1142f | 38 | |
4ecac3fd AK |
39 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
40 | ||
6aa8b732 AK |
41 | MODULE_AUTHOR("Qumranet"); |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | #define IOPM_ALLOC_ORDER 2 | |
45 | #define MSRPM_ALLOC_ORDER 1 | |
46 | ||
6aa8b732 AK |
47 | #define SEG_TYPE_LDT 2 |
48 | #define SEG_TYPE_BUSY_TSS16 3 | |
49 | ||
6bc31bdc AP |
50 | #define SVM_FEATURE_NPT (1 << 0) |
51 | #define SVM_FEATURE_LBRV (1 << 1) | |
52 | #define SVM_FEATURE_SVML (1 << 2) | |
53 | #define SVM_FEATURE_NRIP (1 << 3) | |
54 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) | |
80b7706e | 55 | |
410e4d57 JR |
56 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
57 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
58 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
59 | ||
24e09cbf JR |
60 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
61 | ||
67ec6607 JR |
62 | static bool erratum_383_found __read_mostly; |
63 | ||
6c8166a7 AK |
64 | static const u32 host_save_user_msrs[] = { |
65 | #ifdef CONFIG_X86_64 | |
66 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
67 | MSR_FS_BASE, | |
68 | #endif | |
69 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
70 | }; | |
71 | ||
72 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
73 | ||
74 | struct kvm_vcpu; | |
75 | ||
e6aa9abd JR |
76 | struct nested_state { |
77 | struct vmcb *hsave; | |
78 | u64 hsave_msr; | |
4a810181 | 79 | u64 vm_cr_msr; |
e6aa9abd JR |
80 | u64 vmcb; |
81 | ||
82 | /* These are the merged vectors */ | |
83 | u32 *msrpm; | |
84 | ||
85 | /* gpa pointers to the real vectors */ | |
86 | u64 vmcb_msrpm; | |
ce2ac085 | 87 | u64 vmcb_iopm; |
aad42c64 | 88 | |
cd3ff653 JR |
89 | /* A VMEXIT is required but not yet emulated */ |
90 | bool exit_required; | |
91 | ||
cda00082 JR |
92 | /* |
93 | * If we vmexit during an instruction emulation we need this to restore | |
94 | * the l1 guest rip after the emulation | |
95 | */ | |
96 | unsigned long vmexit_rip; | |
97 | unsigned long vmexit_rsp; | |
98 | unsigned long vmexit_rax; | |
99 | ||
aad42c64 | 100 | /* cache for intercepts of the guest */ |
4ee546b4 | 101 | u32 intercept_cr; |
3aed041a | 102 | u32 intercept_dr; |
aad42c64 JR |
103 | u32 intercept_exceptions; |
104 | u64 intercept; | |
105 | ||
5bd2edc3 JR |
106 | /* Nested Paging related state */ |
107 | u64 nested_cr3; | |
e6aa9abd JR |
108 | }; |
109 | ||
323c3d80 JR |
110 | #define MSRPM_OFFSETS 16 |
111 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
112 | ||
6c8166a7 AK |
113 | struct vcpu_svm { |
114 | struct kvm_vcpu vcpu; | |
115 | struct vmcb *vmcb; | |
116 | unsigned long vmcb_pa; | |
117 | struct svm_cpu_data *svm_data; | |
118 | uint64_t asid_generation; | |
119 | uint64_t sysenter_esp; | |
120 | uint64_t sysenter_eip; | |
121 | ||
122 | u64 next_rip; | |
123 | ||
124 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 125 | struct { |
dacccfdd AK |
126 | u16 fs; |
127 | u16 gs; | |
128 | u16 ldt; | |
afe9e66f AK |
129 | u64 gs_base; |
130 | } host; | |
6c8166a7 AK |
131 | |
132 | u32 *msrpm; | |
6c8166a7 | 133 | |
e6aa9abd | 134 | struct nested_state nested; |
6be7d306 JK |
135 | |
136 | bool nmi_singlestep; | |
66b7138f JK |
137 | |
138 | unsigned int3_injected; | |
139 | unsigned long int3_rip; | |
631bc487 | 140 | u32 apf_reason; |
6c8166a7 AK |
141 | }; |
142 | ||
455716fa JR |
143 | #define MSR_INVALID 0xffffffffU |
144 | ||
ac72a9b7 JR |
145 | static struct svm_direct_access_msrs { |
146 | u32 index; /* Index of the MSR */ | |
147 | bool always; /* True if intercept is always on */ | |
148 | } direct_access_msrs[] = { | |
8c06585d | 149 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
150 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
151 | #ifdef CONFIG_X86_64 | |
152 | { .index = MSR_GS_BASE, .always = true }, | |
153 | { .index = MSR_FS_BASE, .always = true }, | |
154 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
155 | { .index = MSR_LSTAR, .always = true }, | |
156 | { .index = MSR_CSTAR, .always = true }, | |
157 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
158 | #endif | |
159 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
160 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
161 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
162 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
163 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
164 | }; |
165 | ||
709ddebf JR |
166 | /* enable NPT for AMD64 and X86 with PAE */ |
167 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
168 | static bool npt_enabled = true; | |
169 | #else | |
e0231715 | 170 | static bool npt_enabled; |
709ddebf | 171 | #endif |
6c7dac72 JR |
172 | static int npt = 1; |
173 | ||
174 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 175 | |
4b6e4dca | 176 | static int nested = 1; |
236de055 AG |
177 | module_param(nested, int, S_IRUGO); |
178 | ||
44874f84 | 179 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 180 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 181 | |
410e4d57 | 182 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 183 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 184 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
185 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
186 | bool has_error_code, u32 error_code); | |
187 | ||
a2fa3e9f GH |
188 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
189 | { | |
fb3f0f51 | 190 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
191 | } |
192 | ||
384c6368 JR |
193 | static void recalc_intercepts(struct vcpu_svm *svm) |
194 | { | |
195 | struct vmcb_control_area *c, *h; | |
196 | struct nested_state *g; | |
197 | ||
198 | if (!is_guest_mode(&svm->vcpu)) | |
199 | return; | |
200 | ||
201 | c = &svm->vmcb->control; | |
202 | h = &svm->nested.hsave->control; | |
203 | g = &svm->nested; | |
204 | ||
4ee546b4 | 205 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 206 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
207 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
208 | c->intercept = h->intercept | g->intercept; | |
209 | } | |
210 | ||
4ee546b4 RJ |
211 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
212 | { | |
213 | if (is_guest_mode(&svm->vcpu)) | |
214 | return svm->nested.hsave; | |
215 | else | |
216 | return svm->vmcb; | |
217 | } | |
218 | ||
219 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
220 | { | |
221 | struct vmcb *vmcb = get_host_vmcb(svm); | |
222 | ||
223 | vmcb->control.intercept_cr |= (1U << bit); | |
224 | ||
225 | recalc_intercepts(svm); | |
226 | } | |
227 | ||
228 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
229 | { | |
230 | struct vmcb *vmcb = get_host_vmcb(svm); | |
231 | ||
232 | vmcb->control.intercept_cr &= ~(1U << bit); | |
233 | ||
234 | recalc_intercepts(svm); | |
235 | } | |
236 | ||
237 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
238 | { | |
239 | struct vmcb *vmcb = get_host_vmcb(svm); | |
240 | ||
241 | return vmcb->control.intercept_cr & (1U << bit); | |
242 | } | |
243 | ||
3aed041a JR |
244 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
245 | { | |
246 | struct vmcb *vmcb = get_host_vmcb(svm); | |
247 | ||
248 | vmcb->control.intercept_dr |= (1U << bit); | |
249 | ||
250 | recalc_intercepts(svm); | |
251 | } | |
252 | ||
253 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
254 | { | |
255 | struct vmcb *vmcb = get_host_vmcb(svm); | |
256 | ||
257 | vmcb->control.intercept_dr &= ~(1U << bit); | |
258 | ||
259 | recalc_intercepts(svm); | |
260 | } | |
261 | ||
18c918c5 JR |
262 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
263 | { | |
264 | struct vmcb *vmcb = get_host_vmcb(svm); | |
265 | ||
266 | vmcb->control.intercept_exceptions |= (1U << bit); | |
267 | ||
268 | recalc_intercepts(svm); | |
269 | } | |
270 | ||
271 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
272 | { | |
273 | struct vmcb *vmcb = get_host_vmcb(svm); | |
274 | ||
275 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
276 | ||
277 | recalc_intercepts(svm); | |
278 | } | |
279 | ||
8a05a1b8 JR |
280 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
281 | { | |
282 | struct vmcb *vmcb = get_host_vmcb(svm); | |
283 | ||
284 | vmcb->control.intercept |= (1ULL << bit); | |
285 | ||
286 | recalc_intercepts(svm); | |
287 | } | |
288 | ||
289 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
290 | { | |
291 | struct vmcb *vmcb = get_host_vmcb(svm); | |
292 | ||
293 | vmcb->control.intercept &= ~(1ULL << bit); | |
294 | ||
295 | recalc_intercepts(svm); | |
296 | } | |
297 | ||
2af9194d JR |
298 | static inline void enable_gif(struct vcpu_svm *svm) |
299 | { | |
300 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
301 | } | |
302 | ||
303 | static inline void disable_gif(struct vcpu_svm *svm) | |
304 | { | |
305 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
306 | } | |
307 | ||
308 | static inline bool gif_set(struct vcpu_svm *svm) | |
309 | { | |
310 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
311 | } | |
312 | ||
4866d5e3 | 313 | static unsigned long iopm_base; |
6aa8b732 AK |
314 | |
315 | struct kvm_ldttss_desc { | |
316 | u16 limit0; | |
317 | u16 base0; | |
e0231715 JR |
318 | unsigned base1:8, type:5, dpl:2, p:1; |
319 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
320 | u32 base3; |
321 | u32 zero1; | |
322 | } __attribute__((packed)); | |
323 | ||
324 | struct svm_cpu_data { | |
325 | int cpu; | |
326 | ||
5008fdf5 AK |
327 | u64 asid_generation; |
328 | u32 max_asid; | |
329 | u32 next_asid; | |
6aa8b732 AK |
330 | struct kvm_ldttss_desc *tss_desc; |
331 | ||
332 | struct page *save_area; | |
333 | }; | |
334 | ||
335 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 336 | static uint32_t svm_features; |
6aa8b732 AK |
337 | |
338 | struct svm_init_data { | |
339 | int cpu; | |
340 | int r; | |
341 | }; | |
342 | ||
343 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
344 | ||
9d8f549d | 345 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
346 | #define MSRS_RANGE_SIZE 2048 |
347 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
348 | ||
455716fa JR |
349 | static u32 svm_msrpm_offset(u32 msr) |
350 | { | |
351 | u32 offset; | |
352 | int i; | |
353 | ||
354 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
355 | if (msr < msrpm_ranges[i] || | |
356 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
357 | continue; | |
358 | ||
359 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
360 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
361 | ||
362 | /* Now we have the u8 offset - but need the u32 offset */ | |
363 | return offset / 4; | |
364 | } | |
365 | ||
366 | /* MSR not in any range */ | |
367 | return MSR_INVALID; | |
368 | } | |
369 | ||
6aa8b732 AK |
370 | #define MAX_INST_SIZE 15 |
371 | ||
6aa8b732 AK |
372 | static inline void clgi(void) |
373 | { | |
4ecac3fd | 374 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
375 | } |
376 | ||
377 | static inline void stgi(void) | |
378 | { | |
4ecac3fd | 379 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
380 | } |
381 | ||
382 | static inline void invlpga(unsigned long addr, u32 asid) | |
383 | { | |
e0231715 | 384 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
385 | } |
386 | ||
6aa8b732 AK |
387 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
388 | { | |
a2fa3e9f | 389 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
390 | } |
391 | ||
392 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
393 | { | |
394 | force_new_asid(vcpu); | |
395 | } | |
396 | ||
4b16184c JR |
397 | static int get_npt_level(void) |
398 | { | |
399 | #ifdef CONFIG_X86_64 | |
400 | return PT64_ROOT_LEVEL; | |
401 | #else | |
402 | return PT32E_ROOT_LEVEL; | |
403 | #endif | |
404 | } | |
405 | ||
6aa8b732 AK |
406 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
407 | { | |
6dc696d4 | 408 | vcpu->arch.efer = efer; |
709ddebf | 409 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 410 | efer &= ~EFER_LME; |
6aa8b732 | 411 | |
9962d032 | 412 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
6aa8b732 AK |
413 | } |
414 | ||
6aa8b732 AK |
415 | static int is_external_interrupt(u32 info) |
416 | { | |
417 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
418 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
419 | } | |
420 | ||
2809f5d2 GC |
421 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
422 | { | |
423 | struct vcpu_svm *svm = to_svm(vcpu); | |
424 | u32 ret = 0; | |
425 | ||
426 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 427 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
428 | return ret & mask; |
429 | } | |
430 | ||
431 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
432 | { | |
433 | struct vcpu_svm *svm = to_svm(vcpu); | |
434 | ||
435 | if (mask == 0) | |
436 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
437 | else | |
438 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
439 | ||
440 | } | |
441 | ||
6aa8b732 AK |
442 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
443 | { | |
a2fa3e9f GH |
444 | struct vcpu_svm *svm = to_svm(vcpu); |
445 | ||
6bc31bdc AP |
446 | if (svm->vmcb->control.next_rip != 0) |
447 | svm->next_rip = svm->vmcb->control.next_rip; | |
448 | ||
a2fa3e9f | 449 | if (!svm->next_rip) { |
851ba692 | 450 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != |
f629cf84 GN |
451 | EMULATE_DONE) |
452 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
453 | return; |
454 | } | |
5fdbf976 MT |
455 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
456 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
457 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 458 | |
5fdbf976 | 459 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 460 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
461 | } |
462 | ||
116a4752 | 463 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
464 | bool has_error_code, u32 error_code, |
465 | bool reinject) | |
116a4752 JK |
466 | { |
467 | struct vcpu_svm *svm = to_svm(vcpu); | |
468 | ||
e0231715 JR |
469 | /* |
470 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
471 | * handle the exception | |
472 | */ | |
ce7ddec4 JR |
473 | if (!reinject && |
474 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
475 | return; |
476 | ||
2a6b20b8 | 477 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
478 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
479 | ||
480 | /* | |
481 | * For guest debugging where we have to reinject #BP if some | |
482 | * INT3 is guest-owned: | |
483 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
484 | * raises a fault that is not intercepted. Still better than | |
485 | * failing in all cases. | |
486 | */ | |
487 | skip_emulated_instruction(&svm->vcpu); | |
488 | rip = kvm_rip_read(&svm->vcpu); | |
489 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
490 | svm->int3_injected = rip - old_rip; | |
491 | } | |
492 | ||
116a4752 JK |
493 | svm->vmcb->control.event_inj = nr |
494 | | SVM_EVTINJ_VALID | |
495 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
496 | | SVM_EVTINJ_TYPE_EXEPT; | |
497 | svm->vmcb->control.event_inj_err = error_code; | |
498 | } | |
499 | ||
67ec6607 JR |
500 | static void svm_init_erratum_383(void) |
501 | { | |
502 | u32 low, high; | |
503 | int err; | |
504 | u64 val; | |
505 | ||
1be85a6d | 506 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
507 | return; |
508 | ||
509 | /* Use _safe variants to not break nested virtualization */ | |
510 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
511 | if (err) | |
512 | return; | |
513 | ||
514 | val |= (1ULL << 47); | |
515 | ||
516 | low = lower_32_bits(val); | |
517 | high = upper_32_bits(val); | |
518 | ||
519 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
520 | ||
521 | erratum_383_found = true; | |
522 | } | |
523 | ||
6aa8b732 AK |
524 | static int has_svm(void) |
525 | { | |
63d1142f | 526 | const char *msg; |
6aa8b732 | 527 | |
63d1142f | 528 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 529 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
530 | return 0; |
531 | } | |
532 | ||
6aa8b732 AK |
533 | return 1; |
534 | } | |
535 | ||
536 | static void svm_hardware_disable(void *garbage) | |
537 | { | |
2c8dceeb | 538 | cpu_svm_disable(); |
6aa8b732 AK |
539 | } |
540 | ||
10474ae8 | 541 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
542 | { |
543 | ||
0fe1e009 | 544 | struct svm_cpu_data *sd; |
6aa8b732 | 545 | uint64_t efer; |
89a27f4d | 546 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
547 | struct desc_struct *gdt; |
548 | int me = raw_smp_processor_id(); | |
549 | ||
10474ae8 AG |
550 | rdmsrl(MSR_EFER, efer); |
551 | if (efer & EFER_SVME) | |
552 | return -EBUSY; | |
553 | ||
6aa8b732 | 554 | if (!has_svm()) { |
e6732a5a ZA |
555 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
556 | me); | |
10474ae8 | 557 | return -EINVAL; |
6aa8b732 | 558 | } |
0fe1e009 | 559 | sd = per_cpu(svm_data, me); |
6aa8b732 | 560 | |
0fe1e009 | 561 | if (!sd) { |
e6732a5a | 562 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 563 | me); |
10474ae8 | 564 | return -EINVAL; |
6aa8b732 AK |
565 | } |
566 | ||
0fe1e009 TH |
567 | sd->asid_generation = 1; |
568 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
569 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 570 | |
d6ab1ed4 | 571 | native_store_gdt(&gdt_descr); |
89a27f4d | 572 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 573 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 574 | |
9962d032 | 575 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 576 | |
d0316554 | 577 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 578 | |
67ec6607 JR |
579 | svm_init_erratum_383(); |
580 | ||
10474ae8 | 581 | return 0; |
6aa8b732 AK |
582 | } |
583 | ||
0da1db75 JR |
584 | static void svm_cpu_uninit(int cpu) |
585 | { | |
0fe1e009 | 586 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 587 | |
0fe1e009 | 588 | if (!sd) |
0da1db75 JR |
589 | return; |
590 | ||
591 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
592 | __free_page(sd->save_area); |
593 | kfree(sd); | |
0da1db75 JR |
594 | } |
595 | ||
6aa8b732 AK |
596 | static int svm_cpu_init(int cpu) |
597 | { | |
0fe1e009 | 598 | struct svm_cpu_data *sd; |
6aa8b732 AK |
599 | int r; |
600 | ||
0fe1e009 TH |
601 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
602 | if (!sd) | |
6aa8b732 | 603 | return -ENOMEM; |
0fe1e009 TH |
604 | sd->cpu = cpu; |
605 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 606 | r = -ENOMEM; |
0fe1e009 | 607 | if (!sd->save_area) |
6aa8b732 AK |
608 | goto err_1; |
609 | ||
0fe1e009 | 610 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
611 | |
612 | return 0; | |
613 | ||
614 | err_1: | |
0fe1e009 | 615 | kfree(sd); |
6aa8b732 AK |
616 | return r; |
617 | ||
618 | } | |
619 | ||
ac72a9b7 JR |
620 | static bool valid_msr_intercept(u32 index) |
621 | { | |
622 | int i; | |
623 | ||
624 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
625 | if (direct_access_msrs[i].index == index) | |
626 | return true; | |
627 | ||
628 | return false; | |
629 | } | |
630 | ||
bfc733a7 RR |
631 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
632 | int read, int write) | |
6aa8b732 | 633 | { |
455716fa JR |
634 | u8 bit_read, bit_write; |
635 | unsigned long tmp; | |
636 | u32 offset; | |
6aa8b732 | 637 | |
ac72a9b7 JR |
638 | /* |
639 | * If this warning triggers extend the direct_access_msrs list at the | |
640 | * beginning of the file | |
641 | */ | |
642 | WARN_ON(!valid_msr_intercept(msr)); | |
643 | ||
455716fa JR |
644 | offset = svm_msrpm_offset(msr); |
645 | bit_read = 2 * (msr & 0x0f); | |
646 | bit_write = 2 * (msr & 0x0f) + 1; | |
647 | tmp = msrpm[offset]; | |
648 | ||
649 | BUG_ON(offset == MSR_INVALID); | |
650 | ||
651 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
652 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
653 | ||
654 | msrpm[offset] = tmp; | |
6aa8b732 AK |
655 | } |
656 | ||
f65c229c | 657 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
658 | { |
659 | int i; | |
660 | ||
f65c229c JR |
661 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
662 | ||
ac72a9b7 JR |
663 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
664 | if (!direct_access_msrs[i].always) | |
665 | continue; | |
666 | ||
667 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
668 | } | |
f65c229c JR |
669 | } |
670 | ||
323c3d80 JR |
671 | static void add_msr_offset(u32 offset) |
672 | { | |
673 | int i; | |
674 | ||
675 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
676 | ||
677 | /* Offset already in list? */ | |
678 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 679 | return; |
323c3d80 JR |
680 | |
681 | /* Slot used by another offset? */ | |
682 | if (msrpm_offsets[i] != MSR_INVALID) | |
683 | continue; | |
684 | ||
685 | /* Add offset to list */ | |
686 | msrpm_offsets[i] = offset; | |
687 | ||
688 | return; | |
6aa8b732 | 689 | } |
323c3d80 JR |
690 | |
691 | /* | |
692 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
693 | * increase MSRPM_OFFSETS in this case. | |
694 | */ | |
bfc733a7 | 695 | BUG(); |
6aa8b732 AK |
696 | } |
697 | ||
323c3d80 | 698 | static void init_msrpm_offsets(void) |
f65c229c | 699 | { |
323c3d80 | 700 | int i; |
f65c229c | 701 | |
323c3d80 JR |
702 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
703 | ||
704 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
705 | u32 offset; | |
706 | ||
707 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
708 | BUG_ON(offset == MSR_INVALID); | |
709 | ||
710 | add_msr_offset(offset); | |
711 | } | |
f65c229c JR |
712 | } |
713 | ||
24e09cbf JR |
714 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
715 | { | |
716 | u32 *msrpm = svm->msrpm; | |
717 | ||
718 | svm->vmcb->control.lbr_ctl = 1; | |
719 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
720 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
721 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
722 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
723 | } | |
724 | ||
725 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
726 | { | |
727 | u32 *msrpm = svm->msrpm; | |
728 | ||
729 | svm->vmcb->control.lbr_ctl = 0; | |
730 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
731 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
732 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
733 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
734 | } | |
735 | ||
6aa8b732 AK |
736 | static __init int svm_hardware_setup(void) |
737 | { | |
738 | int cpu; | |
739 | struct page *iopm_pages; | |
f65c229c | 740 | void *iopm_va; |
6aa8b732 AK |
741 | int r; |
742 | ||
6aa8b732 AK |
743 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
744 | ||
745 | if (!iopm_pages) | |
746 | return -ENOMEM; | |
c8681339 AL |
747 | |
748 | iopm_va = page_address(iopm_pages); | |
749 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
750 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
751 | ||
323c3d80 JR |
752 | init_msrpm_offsets(); |
753 | ||
50a37eb4 JR |
754 | if (boot_cpu_has(X86_FEATURE_NX)) |
755 | kvm_enable_efer_bits(EFER_NX); | |
756 | ||
1b2fd70c AG |
757 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
758 | kvm_enable_efer_bits(EFER_FFXSR); | |
759 | ||
236de055 AG |
760 | if (nested) { |
761 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 762 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
763 | } |
764 | ||
3230bb47 | 765 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
766 | r = svm_cpu_init(cpu); |
767 | if (r) | |
f65c229c | 768 | goto err; |
6aa8b732 | 769 | } |
33bd6a0b JR |
770 | |
771 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
772 | ||
2a6b20b8 | 773 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
774 | npt_enabled = false; |
775 | ||
6c7dac72 JR |
776 | if (npt_enabled && !npt) { |
777 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
778 | npt_enabled = false; | |
779 | } | |
780 | ||
18552672 | 781 | if (npt_enabled) { |
e3da3acd | 782 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 783 | kvm_enable_tdp(); |
5f4cb662 JR |
784 | } else |
785 | kvm_disable_tdp(); | |
e3da3acd | 786 | |
6aa8b732 AK |
787 | return 0; |
788 | ||
f65c229c | 789 | err: |
6aa8b732 AK |
790 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
791 | iopm_base = 0; | |
792 | return r; | |
793 | } | |
794 | ||
795 | static __exit void svm_hardware_unsetup(void) | |
796 | { | |
0da1db75 JR |
797 | int cpu; |
798 | ||
3230bb47 | 799 | for_each_possible_cpu(cpu) |
0da1db75 JR |
800 | svm_cpu_uninit(cpu); |
801 | ||
6aa8b732 | 802 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 803 | iopm_base = 0; |
6aa8b732 AK |
804 | } |
805 | ||
806 | static void init_seg(struct vmcb_seg *seg) | |
807 | { | |
808 | seg->selector = 0; | |
809 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 810 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
811 | seg->limit = 0xffff; |
812 | seg->base = 0; | |
813 | } | |
814 | ||
815 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
816 | { | |
817 | seg->selector = 0; | |
818 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
819 | seg->limit = 0xffff; | |
820 | seg->base = 0; | |
821 | } | |
822 | ||
f4e1b3c8 ZA |
823 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
824 | { | |
825 | struct vcpu_svm *svm = to_svm(vcpu); | |
826 | u64 g_tsc_offset = 0; | |
827 | ||
2030753d | 828 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
829 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
830 | svm->nested.hsave->control.tsc_offset; | |
831 | svm->nested.hsave->control.tsc_offset = offset; | |
832 | } | |
833 | ||
834 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
835 | } | |
836 | ||
e48672fa ZA |
837 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
838 | { | |
839 | struct vcpu_svm *svm = to_svm(vcpu); | |
840 | ||
841 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 842 | if (is_guest_mode(vcpu)) |
e48672fa ZA |
843 | svm->nested.hsave->control.tsc_offset += adjustment; |
844 | } | |
845 | ||
e6101a96 | 846 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 847 | { |
e6101a96 JR |
848 | struct vmcb_control_area *control = &svm->vmcb->control; |
849 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 850 | |
bff78274 | 851 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 852 | svm->vcpu.arch.hflags = 0; |
bff78274 | 853 | |
4ee546b4 RJ |
854 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
855 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
856 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
857 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
858 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
859 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
860 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 861 | |
3aed041a JR |
862 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
863 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
864 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
865 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
866 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
867 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
868 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
869 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
870 | ||
871 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
872 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
873 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
874 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
875 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
876 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
877 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
878 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 879 | |
18c918c5 JR |
880 | set_exception_intercept(svm, PF_VECTOR); |
881 | set_exception_intercept(svm, UD_VECTOR); | |
882 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 883 | |
8a05a1b8 JR |
884 | set_intercept(svm, INTERCEPT_INTR); |
885 | set_intercept(svm, INTERCEPT_NMI); | |
886 | set_intercept(svm, INTERCEPT_SMI); | |
887 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
888 | set_intercept(svm, INTERCEPT_CPUID); | |
889 | set_intercept(svm, INTERCEPT_INVD); | |
890 | set_intercept(svm, INTERCEPT_HLT); | |
891 | set_intercept(svm, INTERCEPT_INVLPG); | |
892 | set_intercept(svm, INTERCEPT_INVLPGA); | |
893 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
894 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
895 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
896 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
897 | set_intercept(svm, INTERCEPT_VMRUN); | |
898 | set_intercept(svm, INTERCEPT_VMMCALL); | |
899 | set_intercept(svm, INTERCEPT_VMLOAD); | |
900 | set_intercept(svm, INTERCEPT_VMSAVE); | |
901 | set_intercept(svm, INTERCEPT_STGI); | |
902 | set_intercept(svm, INTERCEPT_CLGI); | |
903 | set_intercept(svm, INTERCEPT_SKINIT); | |
904 | set_intercept(svm, INTERCEPT_WBINVD); | |
905 | set_intercept(svm, INTERCEPT_MONITOR); | |
906 | set_intercept(svm, INTERCEPT_MWAIT); | |
6aa8b732 AK |
907 | |
908 | control->iopm_base_pa = iopm_base; | |
f65c229c | 909 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
910 | control->int_ctl = V_INTR_MASKING_MASK; |
911 | ||
912 | init_seg(&save->es); | |
913 | init_seg(&save->ss); | |
914 | init_seg(&save->ds); | |
915 | init_seg(&save->fs); | |
916 | init_seg(&save->gs); | |
917 | ||
918 | save->cs.selector = 0xf000; | |
919 | /* Executable/Readable Code Segment */ | |
920 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
921 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
922 | save->cs.limit = 0xffff; | |
d92899a0 AK |
923 | /* |
924 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
925 | * be consistent with it. | |
926 | * | |
927 | * Replace when we have real mode working for vmx. | |
928 | */ | |
929 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
930 | |
931 | save->gdtr.limit = 0xffff; | |
932 | save->idtr.limit = 0xffff; | |
933 | ||
934 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
935 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
936 | ||
eaa48512 | 937 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 938 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
939 | save->dr7 = 0x400; |
940 | save->rflags = 2; | |
941 | save->rip = 0x0000fff0; | |
5fdbf976 | 942 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 943 | |
e0231715 JR |
944 | /* |
945 | * This is the guest-visible cr0 value. | |
18fa000a | 946 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 947 | */ |
678041ad MT |
948 | svm->vcpu.arch.cr0 = 0; |
949 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 950 | |
66aee91a | 951 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 952 | /* rdx = ?? */ |
709ddebf JR |
953 | |
954 | if (npt_enabled) { | |
955 | /* Setup VMCB for Nested Paging */ | |
956 | control->nested_ctl = 1; | |
8a05a1b8 JR |
957 | clr_intercept(svm, INTERCEPT_TASK_SWITCH); |
958 | clr_intercept(svm, INTERCEPT_INVLPG); | |
18c918c5 | 959 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
960 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
961 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 962 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
963 | save->cr3 = 0; |
964 | save->cr4 = 0; | |
965 | } | |
a79d2f18 | 966 | force_new_asid(&svm->vcpu); |
1371d904 | 967 | |
e6aa9abd | 968 | svm->nested.vmcb = 0; |
2af9194d JR |
969 | svm->vcpu.arch.hflags = 0; |
970 | ||
2a6b20b8 | 971 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 972 | control->pause_filter_count = 3000; |
8a05a1b8 | 973 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
974 | } |
975 | ||
2af9194d | 976 | enable_gif(svm); |
6aa8b732 AK |
977 | } |
978 | ||
e00c8cf2 | 979 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
980 | { |
981 | struct vcpu_svm *svm = to_svm(vcpu); | |
982 | ||
e6101a96 | 983 | init_vmcb(svm); |
70433389 | 984 | |
c5af89b6 | 985 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 986 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
987 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
988 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 989 | } |
5fdbf976 MT |
990 | vcpu->arch.regs_avail = ~0; |
991 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
992 | |
993 | return 0; | |
04d2cc77 AK |
994 | } |
995 | ||
fb3f0f51 | 996 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 997 | { |
a2fa3e9f | 998 | struct vcpu_svm *svm; |
6aa8b732 | 999 | struct page *page; |
f65c229c | 1000 | struct page *msrpm_pages; |
b286d5d8 | 1001 | struct page *hsave_page; |
3d6368ef | 1002 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1003 | int err; |
6aa8b732 | 1004 | |
c16f862d | 1005 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1006 | if (!svm) { |
1007 | err = -ENOMEM; | |
1008 | goto out; | |
1009 | } | |
1010 | ||
1011 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1012 | if (err) | |
1013 | goto free_svm; | |
1014 | ||
b7af4043 | 1015 | err = -ENOMEM; |
6aa8b732 | 1016 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1017 | if (!page) |
fb3f0f51 | 1018 | goto uninit; |
6aa8b732 | 1019 | |
f65c229c JR |
1020 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1021 | if (!msrpm_pages) | |
b7af4043 | 1022 | goto free_page1; |
3d6368ef AG |
1023 | |
1024 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1025 | if (!nested_msrpm_pages) | |
b7af4043 | 1026 | goto free_page2; |
f65c229c | 1027 | |
b286d5d8 AG |
1028 | hsave_page = alloc_page(GFP_KERNEL); |
1029 | if (!hsave_page) | |
b7af4043 TY |
1030 | goto free_page3; |
1031 | ||
e6aa9abd | 1032 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1033 | |
b7af4043 TY |
1034 | svm->msrpm = page_address(msrpm_pages); |
1035 | svm_vcpu_init_msrpm(svm->msrpm); | |
1036 | ||
e6aa9abd | 1037 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1038 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1039 | |
a2fa3e9f GH |
1040 | svm->vmcb = page_address(page); |
1041 | clear_page(svm->vmcb); | |
1042 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1043 | svm->asid_generation = 0; | |
e6101a96 | 1044 | init_vmcb(svm); |
99e3e30a | 1045 | kvm_write_tsc(&svm->vcpu, 0); |
a2fa3e9f | 1046 | |
10ab25cd JK |
1047 | err = fx_init(&svm->vcpu); |
1048 | if (err) | |
1049 | goto free_page4; | |
1050 | ||
ad312c7c | 1051 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1052 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1053 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1054 | |
fb3f0f51 | 1055 | return &svm->vcpu; |
36241b8c | 1056 | |
10ab25cd JK |
1057 | free_page4: |
1058 | __free_page(hsave_page); | |
b7af4043 TY |
1059 | free_page3: |
1060 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1061 | free_page2: | |
1062 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1063 | free_page1: | |
1064 | __free_page(page); | |
fb3f0f51 RR |
1065 | uninit: |
1066 | kvm_vcpu_uninit(&svm->vcpu); | |
1067 | free_svm: | |
a4770347 | 1068 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1069 | out: |
1070 | return ERR_PTR(err); | |
6aa8b732 AK |
1071 | } |
1072 | ||
1073 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1074 | { | |
a2fa3e9f GH |
1075 | struct vcpu_svm *svm = to_svm(vcpu); |
1076 | ||
fb3f0f51 | 1077 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1078 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1079 | __free_page(virt_to_page(svm->nested.hsave)); |
1080 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1081 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1082 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1083 | } |
1084 | ||
15ad7146 | 1085 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1086 | { |
a2fa3e9f | 1087 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1088 | int i; |
0cc5064d | 1089 | |
0cc5064d | 1090 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1091 | svm->asid_generation = 0; |
0cc5064d | 1092 | } |
94dfbdb3 | 1093 | |
82ca2d10 AK |
1094 | #ifdef CONFIG_X86_64 |
1095 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1096 | #endif | |
dacccfdd AK |
1097 | savesegment(fs, svm->host.fs); |
1098 | savesegment(gs, svm->host.gs); | |
1099 | svm->host.ldt = kvm_read_ldt(); | |
1100 | ||
94dfbdb3 | 1101 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1102 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1103 | } |
1104 | ||
1105 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1106 | { | |
a2fa3e9f | 1107 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1108 | int i; |
1109 | ||
e1beb1d3 | 1110 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1111 | kvm_load_ldt(svm->host.ldt); |
1112 | #ifdef CONFIG_X86_64 | |
1113 | loadsegment(fs, svm->host.fs); | |
1114 | load_gs_index(svm->host.gs); | |
1115 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); | |
1116 | #else | |
1117 | loadsegment(gs, svm->host.gs); | |
1118 | #endif | |
94dfbdb3 | 1119 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1120 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1121 | } |
1122 | ||
6aa8b732 AK |
1123 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1124 | { | |
a2fa3e9f | 1125 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1126 | } |
1127 | ||
1128 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1129 | { | |
a2fa3e9f | 1130 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1131 | } |
1132 | ||
6de4f3ad AK |
1133 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1134 | { | |
1135 | switch (reg) { | |
1136 | case VCPU_EXREG_PDPTR: | |
1137 | BUG_ON(!npt_enabled); | |
ff03a073 | 1138 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3); |
6de4f3ad AK |
1139 | break; |
1140 | default: | |
1141 | BUG(); | |
1142 | } | |
1143 | } | |
1144 | ||
f0b85051 AG |
1145 | static void svm_set_vintr(struct vcpu_svm *svm) |
1146 | { | |
8a05a1b8 | 1147 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1148 | } |
1149 | ||
1150 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1151 | { | |
8a05a1b8 | 1152 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1153 | } |
1154 | ||
6aa8b732 AK |
1155 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1156 | { | |
a2fa3e9f | 1157 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1158 | |
1159 | switch (seg) { | |
1160 | case VCPU_SREG_CS: return &save->cs; | |
1161 | case VCPU_SREG_DS: return &save->ds; | |
1162 | case VCPU_SREG_ES: return &save->es; | |
1163 | case VCPU_SREG_FS: return &save->fs; | |
1164 | case VCPU_SREG_GS: return &save->gs; | |
1165 | case VCPU_SREG_SS: return &save->ss; | |
1166 | case VCPU_SREG_TR: return &save->tr; | |
1167 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1168 | } | |
1169 | BUG(); | |
8b6d44c7 | 1170 | return NULL; |
6aa8b732 AK |
1171 | } |
1172 | ||
1173 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1174 | { | |
1175 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1176 | ||
1177 | return s->base; | |
1178 | } | |
1179 | ||
1180 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1181 | struct kvm_segment *var, int seg) | |
1182 | { | |
1183 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1184 | ||
1185 | var->base = s->base; | |
1186 | var->limit = s->limit; | |
1187 | var->selector = s->selector; | |
1188 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1189 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1190 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1191 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1192 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1193 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1194 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1195 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1196 | |
e0231715 JR |
1197 | /* |
1198 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1199 | * for cross vendor migration purposes by "not present" |
1200 | */ | |
1201 | var->unusable = !var->present || (var->type == 0); | |
1202 | ||
1fbdc7a5 AP |
1203 | switch (seg) { |
1204 | case VCPU_SREG_CS: | |
1205 | /* | |
1206 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1207 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1208 | * Intel's VMENTRY has a check on the 'G' bit. | |
1209 | */ | |
25022acc | 1210 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1211 | break; |
1212 | case VCPU_SREG_TR: | |
1213 | /* | |
1214 | * Work around a bug where the busy flag in the tr selector | |
1215 | * isn't exposed | |
1216 | */ | |
c0d09828 | 1217 | var->type |= 0x2; |
1fbdc7a5 AP |
1218 | break; |
1219 | case VCPU_SREG_DS: | |
1220 | case VCPU_SREG_ES: | |
1221 | case VCPU_SREG_FS: | |
1222 | case VCPU_SREG_GS: | |
1223 | /* | |
1224 | * The accessed bit must always be set in the segment | |
1225 | * descriptor cache, although it can be cleared in the | |
1226 | * descriptor, the cached bit always remains at 1. Since | |
1227 | * Intel has a check on this, set it here to support | |
1228 | * cross-vendor migration. | |
1229 | */ | |
1230 | if (!var->unusable) | |
1231 | var->type |= 0x1; | |
1232 | break; | |
b586eb02 | 1233 | case VCPU_SREG_SS: |
e0231715 JR |
1234 | /* |
1235 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1236 | * descriptor is left as 1, although the whole segment has |
1237 | * been made unusable. Clear it here to pass an Intel VMX | |
1238 | * entry check when cross vendor migrating. | |
1239 | */ | |
1240 | if (var->unusable) | |
1241 | var->db = 0; | |
1242 | break; | |
1fbdc7a5 | 1243 | } |
6aa8b732 AK |
1244 | } |
1245 | ||
2e4d2653 IE |
1246 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1247 | { | |
1248 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1249 | ||
1250 | return save->cpl; | |
1251 | } | |
1252 | ||
89a27f4d | 1253 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1254 | { |
a2fa3e9f GH |
1255 | struct vcpu_svm *svm = to_svm(vcpu); |
1256 | ||
89a27f4d GN |
1257 | dt->size = svm->vmcb->save.idtr.limit; |
1258 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1259 | } |
1260 | ||
89a27f4d | 1261 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1262 | { |
a2fa3e9f GH |
1263 | struct vcpu_svm *svm = to_svm(vcpu); |
1264 | ||
89a27f4d GN |
1265 | svm->vmcb->save.idtr.limit = dt->size; |
1266 | svm->vmcb->save.idtr.base = dt->address ; | |
6aa8b732 AK |
1267 | } |
1268 | ||
89a27f4d | 1269 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1270 | { |
a2fa3e9f GH |
1271 | struct vcpu_svm *svm = to_svm(vcpu); |
1272 | ||
89a27f4d GN |
1273 | dt->size = svm->vmcb->save.gdtr.limit; |
1274 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1275 | } |
1276 | ||
89a27f4d | 1277 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1278 | { |
a2fa3e9f GH |
1279 | struct vcpu_svm *svm = to_svm(vcpu); |
1280 | ||
89a27f4d GN |
1281 | svm->vmcb->save.gdtr.limit = dt->size; |
1282 | svm->vmcb->save.gdtr.base = dt->address ; | |
6aa8b732 AK |
1283 | } |
1284 | ||
e8467fda AK |
1285 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1286 | { | |
1287 | } | |
1288 | ||
25c4c276 | 1289 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1290 | { |
1291 | } | |
1292 | ||
d225157b AK |
1293 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1294 | { | |
1295 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1296 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1297 | ||
1298 | if (!svm->vcpu.fpu_active) | |
1299 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1300 | else | |
1301 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1302 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1303 | ||
1304 | ||
1305 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1306 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1307 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1308 | } else { |
4ee546b4 RJ |
1309 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1310 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1311 | } |
1312 | } | |
1313 | ||
6aa8b732 AK |
1314 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1315 | { | |
a2fa3e9f GH |
1316 | struct vcpu_svm *svm = to_svm(vcpu); |
1317 | ||
2030753d | 1318 | if (is_guest_mode(vcpu)) { |
7f5d8b56 JR |
1319 | /* |
1320 | * We are here because we run in nested mode, the host kvm | |
1321 | * intercepts cr0 writes but the l1 hypervisor does not. | |
1322 | * But the L1 hypervisor may intercept selective cr0 writes. | |
1323 | * This needs to be checked here. | |
1324 | */ | |
1325 | unsigned long old, new; | |
1326 | ||
1327 | /* Remove bits that would trigger a real cr0 write intercept */ | |
1328 | old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK; | |
1329 | new = cr0 & SVM_CR0_SELECTIVE_MASK; | |
1330 | ||
1331 | if (old == new) { | |
1332 | /* cr0 write with ts and mp unchanged */ | |
1333 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
cda00082 JR |
1334 | if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) { |
1335 | svm->nested.vmexit_rip = kvm_rip_read(vcpu); | |
1336 | svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
1337 | svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
7f5d8b56 | 1338 | return; |
cda00082 | 1339 | } |
7f5d8b56 JR |
1340 | } |
1341 | } | |
1342 | ||
05b3e0c2 | 1343 | #ifdef CONFIG_X86_64 |
f6801dff | 1344 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1345 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1346 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1347 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1348 | } |
1349 | ||
d77c26fc | 1350 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1351 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1352 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1353 | } |
1354 | } | |
1355 | #endif | |
ad312c7c | 1356 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1357 | |
1358 | if (!npt_enabled) | |
1359 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1360 | |
1361 | if (!vcpu->fpu_active) | |
334df50a | 1362 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1363 | /* |
1364 | * re-enable caching here because the QEMU bios | |
1365 | * does not do it - this results in some delay at | |
1366 | * reboot | |
1367 | */ | |
1368 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1369 | svm->vmcb->save.cr0 = cr0; |
d225157b | 1370 | update_cr0_intercept(svm); |
6aa8b732 AK |
1371 | } |
1372 | ||
1373 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1374 | { | |
6394b649 | 1375 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1376 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1377 | ||
1378 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1379 | force_new_asid(vcpu); | |
6394b649 | 1380 | |
ec077263 JR |
1381 | vcpu->arch.cr4 = cr4; |
1382 | if (!npt_enabled) | |
1383 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1384 | cr4 |= host_cr4_mce; |
ec077263 | 1385 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
1386 | } |
1387 | ||
1388 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1389 | struct kvm_segment *var, int seg) | |
1390 | { | |
a2fa3e9f | 1391 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1392 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1393 | ||
1394 | s->base = var->base; | |
1395 | s->limit = var->limit; | |
1396 | s->selector = var->selector; | |
1397 | if (var->unusable) | |
1398 | s->attrib = 0; | |
1399 | else { | |
1400 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1401 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1402 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1403 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1404 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1405 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1406 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1407 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1408 | } | |
1409 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1410 | svm->vmcb->save.cpl |
1411 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1412 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1413 | ||
1414 | } | |
1415 | ||
44c11430 | 1416 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1417 | { |
d0bfb940 JK |
1418 | struct vcpu_svm *svm = to_svm(vcpu); |
1419 | ||
18c918c5 JR |
1420 | clr_exception_intercept(svm, DB_VECTOR); |
1421 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1422 | |
6be7d306 | 1423 | if (svm->nmi_singlestep) |
18c918c5 | 1424 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1425 | |
d0bfb940 JK |
1426 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1427 | if (vcpu->guest_debug & | |
1428 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1429 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1430 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1431 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1432 | } else |
1433 | vcpu->guest_debug = 0; | |
44c11430 GN |
1434 | } |
1435 | ||
355be0b9 | 1436 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1437 | { |
44c11430 GN |
1438 | struct vcpu_svm *svm = to_svm(vcpu); |
1439 | ||
ae675ef0 JK |
1440 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1441 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1442 | else | |
1443 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1444 | ||
355be0b9 | 1445 | update_db_intercept(vcpu); |
6aa8b732 AK |
1446 | } |
1447 | ||
0fe1e009 | 1448 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1449 | { |
0fe1e009 TH |
1450 | if (sd->next_asid > sd->max_asid) { |
1451 | ++sd->asid_generation; | |
1452 | sd->next_asid = 1; | |
a2fa3e9f | 1453 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1454 | } |
1455 | ||
0fe1e009 TH |
1456 | svm->asid_generation = sd->asid_generation; |
1457 | svm->vmcb->control.asid = sd->next_asid++; | |
6aa8b732 AK |
1458 | } |
1459 | ||
020df079 | 1460 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1461 | { |
42dbaa5a | 1462 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1463 | |
020df079 | 1464 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
1465 | } |
1466 | ||
851ba692 | 1467 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1468 | { |
631bc487 | 1469 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1470 | u32 error_code; |
631bc487 | 1471 | int r = 1; |
6aa8b732 | 1472 | |
631bc487 GN |
1473 | switch (svm->apf_reason) { |
1474 | default: | |
1475 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1476 | |
631bc487 GN |
1477 | trace_kvm_page_fault(fault_address, error_code); |
1478 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1479 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
1480 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); | |
1481 | break; | |
1482 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1483 | svm->apf_reason = 0; | |
1484 | local_irq_disable(); | |
1485 | kvm_async_pf_task_wait(fault_address); | |
1486 | local_irq_enable(); | |
1487 | break; | |
1488 | case KVM_PV_REASON_PAGE_READY: | |
1489 | svm->apf_reason = 0; | |
1490 | local_irq_disable(); | |
1491 | kvm_async_pf_task_wake(fault_address); | |
1492 | local_irq_enable(); | |
1493 | break; | |
1494 | } | |
1495 | return r; | |
6aa8b732 AK |
1496 | } |
1497 | ||
851ba692 | 1498 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1499 | { |
851ba692 AK |
1500 | struct kvm_run *kvm_run = svm->vcpu.run; |
1501 | ||
d0bfb940 | 1502 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1503 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1504 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1505 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1506 | return 1; | |
1507 | } | |
44c11430 | 1508 | |
6be7d306 JK |
1509 | if (svm->nmi_singlestep) { |
1510 | svm->nmi_singlestep = false; | |
44c11430 GN |
1511 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1512 | svm->vmcb->save.rflags &= | |
1513 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1514 | update_db_intercept(&svm->vcpu); | |
1515 | } | |
1516 | ||
1517 | if (svm->vcpu.guest_debug & | |
e0231715 | 1518 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1519 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1520 | kvm_run->debug.arch.pc = | |
1521 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1522 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | return 1; | |
d0bfb940 JK |
1527 | } |
1528 | ||
851ba692 | 1529 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1530 | { |
851ba692 AK |
1531 | struct kvm_run *kvm_run = svm->vcpu.run; |
1532 | ||
d0bfb940 JK |
1533 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1534 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1535 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1536 | return 0; | |
1537 | } | |
1538 | ||
851ba692 | 1539 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1540 | { |
1541 | int er; | |
1542 | ||
851ba692 | 1543 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1544 | if (er != EMULATE_DONE) |
7ee5d940 | 1545 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1546 | return 1; |
1547 | } | |
1548 | ||
6b52d186 | 1549 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1550 | { |
6b52d186 | 1551 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1552 | |
18c918c5 | 1553 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1554 | |
e756fc62 | 1555 | svm->vcpu.fpu_active = 1; |
d225157b | 1556 | update_cr0_intercept(svm); |
6b52d186 | 1557 | } |
a2fa3e9f | 1558 | |
6b52d186 AK |
1559 | static int nm_interception(struct vcpu_svm *svm) |
1560 | { | |
1561 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1562 | return 1; |
7807fa6c AL |
1563 | } |
1564 | ||
67ec6607 JR |
1565 | static bool is_erratum_383(void) |
1566 | { | |
1567 | int err, i; | |
1568 | u64 value; | |
1569 | ||
1570 | if (!erratum_383_found) | |
1571 | return false; | |
1572 | ||
1573 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1574 | if (err) | |
1575 | return false; | |
1576 | ||
1577 | /* Bit 62 may or may not be set for this mce */ | |
1578 | value &= ~(1ULL << 62); | |
1579 | ||
1580 | if (value != 0xb600000000010015ULL) | |
1581 | return false; | |
1582 | ||
1583 | /* Clear MCi_STATUS registers */ | |
1584 | for (i = 0; i < 6; ++i) | |
1585 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1586 | ||
1587 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1588 | if (!err) { | |
1589 | u32 low, high; | |
1590 | ||
1591 | value &= ~(1ULL << 2); | |
1592 | low = lower_32_bits(value); | |
1593 | high = upper_32_bits(value); | |
1594 | ||
1595 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1596 | } | |
1597 | ||
1598 | /* Flush tlb to evict multi-match entries */ | |
1599 | __flush_tlb_all(); | |
1600 | ||
1601 | return true; | |
1602 | } | |
1603 | ||
fe5913e4 | 1604 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1605 | { |
67ec6607 JR |
1606 | if (is_erratum_383()) { |
1607 | /* | |
1608 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1609 | * guest. | |
1610 | */ | |
1611 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1612 | ||
a8eeb04a | 1613 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1614 | |
1615 | return; | |
1616 | } | |
1617 | ||
53371b50 JR |
1618 | /* |
1619 | * On an #MC intercept the MCE handler is not called automatically in | |
1620 | * the host. So do it by hand here. | |
1621 | */ | |
1622 | asm volatile ( | |
1623 | "int $0x12\n"); | |
1624 | /* not sure if we ever come back to this point */ | |
1625 | ||
fe5913e4 JR |
1626 | return; |
1627 | } | |
1628 | ||
1629 | static int mc_interception(struct vcpu_svm *svm) | |
1630 | { | |
53371b50 JR |
1631 | return 1; |
1632 | } | |
1633 | ||
851ba692 | 1634 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1635 | { |
851ba692 AK |
1636 | struct kvm_run *kvm_run = svm->vcpu.run; |
1637 | ||
46fe4ddd JR |
1638 | /* |
1639 | * VMCB is undefined after a SHUTDOWN intercept | |
1640 | * so reinitialize it. | |
1641 | */ | |
a2fa3e9f | 1642 | clear_page(svm->vmcb); |
e6101a96 | 1643 | init_vmcb(svm); |
46fe4ddd JR |
1644 | |
1645 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1646 | return 0; | |
1647 | } | |
1648 | ||
851ba692 | 1649 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1650 | { |
cf8f70bf | 1651 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1652 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1653 | int size, in, string; |
039576c0 | 1654 | unsigned port; |
6aa8b732 | 1655 | |
e756fc62 | 1656 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1657 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1658 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1659 | if (string || in) |
6d77dbfc | 1660 | return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE; |
cf8f70bf | 1661 | |
039576c0 AK |
1662 | port = io_info >> 16; |
1663 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1664 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1665 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1666 | |
1667 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1668 | } |
1669 | ||
851ba692 | 1670 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1671 | { |
1672 | return 1; | |
1673 | } | |
1674 | ||
851ba692 | 1675 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1676 | { |
1677 | ++svm->vcpu.stat.irq_exits; | |
1678 | return 1; | |
1679 | } | |
1680 | ||
851ba692 | 1681 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1682 | { |
1683 | return 1; | |
1684 | } | |
1685 | ||
851ba692 | 1686 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1687 | { |
5fdbf976 | 1688 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1689 | skip_emulated_instruction(&svm->vcpu); |
1690 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1691 | } |
1692 | ||
851ba692 | 1693 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1694 | { |
5fdbf976 | 1695 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1696 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1697 | kvm_emulate_hypercall(&svm->vcpu); |
1698 | return 1; | |
02e235bc AK |
1699 | } |
1700 | ||
5bd2edc3 JR |
1701 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1702 | { | |
1703 | struct vcpu_svm *svm = to_svm(vcpu); | |
1704 | ||
1705 | return svm->nested.nested_cr3; | |
1706 | } | |
1707 | ||
1708 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, | |
1709 | unsigned long root) | |
1710 | { | |
1711 | struct vcpu_svm *svm = to_svm(vcpu); | |
1712 | ||
1713 | svm->vmcb->control.nested_cr3 = root; | |
1714 | force_new_asid(vcpu); | |
1715 | } | |
1716 | ||
6389ee94 AK |
1717 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1718 | struct x86_exception *fault) | |
5bd2edc3 JR |
1719 | { |
1720 | struct vcpu_svm *svm = to_svm(vcpu); | |
1721 | ||
1722 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1723 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1724 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1725 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1726 | |
1727 | nested_svm_vmexit(svm); | |
1728 | } | |
1729 | ||
4b16184c JR |
1730 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1731 | { | |
1732 | int r; | |
1733 | ||
1734 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1735 | ||
1736 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1737 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
1738 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; | |
1739 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1740 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1741 | ||
1742 | return r; | |
1743 | } | |
1744 | ||
1745 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1746 | { | |
1747 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1748 | } | |
1749 | ||
c0725420 AG |
1750 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1751 | { | |
f6801dff | 1752 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1753 | || !is_paging(&svm->vcpu)) { |
1754 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1755 | return 1; | |
1756 | } | |
1757 | ||
1758 | if (svm->vmcb->save.cpl) { | |
1759 | kvm_inject_gp(&svm->vcpu, 0); | |
1760 | return 1; | |
1761 | } | |
1762 | ||
1763 | return 0; | |
1764 | } | |
1765 | ||
cf74a78b AG |
1766 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1767 | bool has_error_code, u32 error_code) | |
1768 | { | |
b8e88bc8 JR |
1769 | int vmexit; |
1770 | ||
2030753d | 1771 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1772 | return 0; |
cf74a78b | 1773 | |
0295ad7d JR |
1774 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1775 | svm->vmcb->control.exit_code_hi = 0; | |
1776 | svm->vmcb->control.exit_info_1 = error_code; | |
1777 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1778 | ||
b8e88bc8 JR |
1779 | vmexit = nested_svm_intercept(svm); |
1780 | if (vmexit == NESTED_EXIT_DONE) | |
1781 | svm->nested.exit_required = true; | |
1782 | ||
1783 | return vmexit; | |
cf74a78b AG |
1784 | } |
1785 | ||
8fe54654 JR |
1786 | /* This function returns true if it is save to enable the irq window */ |
1787 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1788 | { |
2030753d | 1789 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 1790 | return true; |
cf74a78b | 1791 | |
26666957 | 1792 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1793 | return true; |
cf74a78b | 1794 | |
26666957 | 1795 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1796 | return false; |
cf74a78b | 1797 | |
a0a07cd2 GN |
1798 | /* |
1799 | * if vmexit was already requested (by intercepted exception | |
1800 | * for instance) do not overwrite it with "external interrupt" | |
1801 | * vmexit. | |
1802 | */ | |
1803 | if (svm->nested.exit_required) | |
1804 | return false; | |
1805 | ||
197717d5 JR |
1806 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1807 | svm->vmcb->control.exit_info_1 = 0; | |
1808 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1809 | |
cd3ff653 JR |
1810 | if (svm->nested.intercept & 1ULL) { |
1811 | /* | |
1812 | * The #vmexit can't be emulated here directly because this | |
1813 | * code path runs with irqs and preemtion disabled. A | |
1814 | * #vmexit emulation might sleep. Only signal request for | |
1815 | * the #vmexit here. | |
1816 | */ | |
1817 | svm->nested.exit_required = true; | |
236649de | 1818 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 1819 | return false; |
cf74a78b AG |
1820 | } |
1821 | ||
8fe54654 | 1822 | return true; |
cf74a78b AG |
1823 | } |
1824 | ||
887f500c JR |
1825 | /* This function returns true if it is save to enable the nmi window */ |
1826 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1827 | { | |
2030753d | 1828 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
1829 | return true; |
1830 | ||
1831 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1832 | return true; | |
1833 | ||
1834 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1835 | svm->nested.exit_required = true; | |
1836 | ||
1837 | return false; | |
cf74a78b AG |
1838 | } |
1839 | ||
7597f129 | 1840 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1841 | { |
1842 | struct page *page; | |
1843 | ||
6c3bd3d7 JR |
1844 | might_sleep(); |
1845 | ||
34f80cfa | 1846 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1847 | if (is_error_page(page)) |
1848 | goto error; | |
1849 | ||
7597f129 JR |
1850 | *_page = page; |
1851 | ||
1852 | return kmap(page); | |
34f80cfa JR |
1853 | |
1854 | error: | |
1855 | kvm_release_page_clean(page); | |
1856 | kvm_inject_gp(&svm->vcpu, 0); | |
1857 | ||
1858 | return NULL; | |
1859 | } | |
1860 | ||
7597f129 | 1861 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1862 | { |
7597f129 | 1863 | kunmap(page); |
34f80cfa JR |
1864 | kvm_release_page_dirty(page); |
1865 | } | |
34f80cfa | 1866 | |
ce2ac085 JR |
1867 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
1868 | { | |
1869 | unsigned port; | |
1870 | u8 val, bit; | |
1871 | u64 gpa; | |
34f80cfa | 1872 | |
ce2ac085 JR |
1873 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
1874 | return NESTED_EXIT_HOST; | |
34f80cfa | 1875 | |
ce2ac085 JR |
1876 | port = svm->vmcb->control.exit_info_1 >> 16; |
1877 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1878 | bit = port % 8; | |
1879 | val = 0; | |
1880 | ||
1881 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1882 | val &= (1 << bit); | |
1883 | ||
1884 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
1885 | } |
1886 | ||
d2477826 | 1887 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1888 | { |
0d6b3537 JR |
1889 | u32 offset, msr, value; |
1890 | int write, mask; | |
4c2161ae | 1891 | |
3d62d9aa | 1892 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 1893 | return NESTED_EXIT_HOST; |
3d62d9aa | 1894 | |
0d6b3537 JR |
1895 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1896 | offset = svm_msrpm_offset(msr); | |
1897 | write = svm->vmcb->control.exit_info_1 & 1; | |
1898 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 1899 | |
0d6b3537 JR |
1900 | if (offset == MSR_INVALID) |
1901 | return NESTED_EXIT_DONE; | |
4c2161ae | 1902 | |
0d6b3537 JR |
1903 | /* Offset is in 32 bit units but need in 8 bit units */ |
1904 | offset *= 4; | |
4c2161ae | 1905 | |
0d6b3537 JR |
1906 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
1907 | return NESTED_EXIT_DONE; | |
3d62d9aa | 1908 | |
0d6b3537 | 1909 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
1910 | } |
1911 | ||
410e4d57 | 1912 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1913 | { |
cf74a78b | 1914 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1915 | |
410e4d57 JR |
1916 | switch (exit_code) { |
1917 | case SVM_EXIT_INTR: | |
1918 | case SVM_EXIT_NMI: | |
ff47a49b | 1919 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 1920 | return NESTED_EXIT_HOST; |
410e4d57 | 1921 | case SVM_EXIT_NPF: |
e0231715 | 1922 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1923 | if (npt_enabled) |
1924 | return NESTED_EXIT_HOST; | |
1925 | break; | |
410e4d57 | 1926 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
1927 | /* When we're shadowing, trap PFs, but not async PF */ |
1928 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
1929 | return NESTED_EXIT_HOST; |
1930 | break; | |
66a562f7 JR |
1931 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
1932 | nm_interception(svm); | |
1933 | break; | |
410e4d57 JR |
1934 | default: |
1935 | break; | |
cf74a78b AG |
1936 | } |
1937 | ||
410e4d57 JR |
1938 | return NESTED_EXIT_CONTINUE; |
1939 | } | |
1940 | ||
1941 | /* | |
1942 | * If this function returns true, this #vmexit was already handled | |
1943 | */ | |
b8e88bc8 | 1944 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
1945 | { |
1946 | u32 exit_code = svm->vmcb->control.exit_code; | |
1947 | int vmexit = NESTED_EXIT_HOST; | |
1948 | ||
cf74a78b | 1949 | switch (exit_code) { |
9c4e40b9 | 1950 | case SVM_EXIT_MSR: |
3d62d9aa | 1951 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1952 | break; |
ce2ac085 JR |
1953 | case SVM_EXIT_IOIO: |
1954 | vmexit = nested_svm_intercept_ioio(svm); | |
1955 | break; | |
4ee546b4 RJ |
1956 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
1957 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
1958 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 1959 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1960 | break; |
1961 | } | |
3aed041a JR |
1962 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
1963 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
1964 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 1965 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1966 | break; |
1967 | } | |
1968 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1969 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1970 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1971 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
1972 | /* async page fault always cause vmexit */ |
1973 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
1974 | svm->apf_reason != 0) | |
1975 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
1976 | break; |
1977 | } | |
228070b1 JR |
1978 | case SVM_EXIT_ERR: { |
1979 | vmexit = NESTED_EXIT_DONE; | |
1980 | break; | |
1981 | } | |
cf74a78b AG |
1982 | default: { |
1983 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 1984 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 1985 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1986 | } |
1987 | } | |
1988 | ||
b8e88bc8 JR |
1989 | return vmexit; |
1990 | } | |
1991 | ||
1992 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1993 | { | |
1994 | int vmexit; | |
1995 | ||
1996 | vmexit = nested_svm_intercept(svm); | |
1997 | ||
1998 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 1999 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2000 | |
2001 | return vmexit; | |
cf74a78b AG |
2002 | } |
2003 | ||
0460a979 JR |
2004 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2005 | { | |
2006 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2007 | struct vmcb_control_area *from = &from_vmcb->control; | |
2008 | ||
4ee546b4 | 2009 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2010 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2011 | dst->intercept_exceptions = from->intercept_exceptions; |
2012 | dst->intercept = from->intercept; | |
2013 | dst->iopm_base_pa = from->iopm_base_pa; | |
2014 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2015 | dst->tsc_offset = from->tsc_offset; | |
2016 | dst->asid = from->asid; | |
2017 | dst->tlb_ctl = from->tlb_ctl; | |
2018 | dst->int_ctl = from->int_ctl; | |
2019 | dst->int_vector = from->int_vector; | |
2020 | dst->int_state = from->int_state; | |
2021 | dst->exit_code = from->exit_code; | |
2022 | dst->exit_code_hi = from->exit_code_hi; | |
2023 | dst->exit_info_1 = from->exit_info_1; | |
2024 | dst->exit_info_2 = from->exit_info_2; | |
2025 | dst->exit_int_info = from->exit_int_info; | |
2026 | dst->exit_int_info_err = from->exit_int_info_err; | |
2027 | dst->nested_ctl = from->nested_ctl; | |
2028 | dst->event_inj = from->event_inj; | |
2029 | dst->event_inj_err = from->event_inj_err; | |
2030 | dst->nested_cr3 = from->nested_cr3; | |
2031 | dst->lbr_ctl = from->lbr_ctl; | |
2032 | } | |
2033 | ||
34f80cfa | 2034 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2035 | { |
34f80cfa | 2036 | struct vmcb *nested_vmcb; |
e6aa9abd | 2037 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2038 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2039 | struct page *page; |
cf74a78b | 2040 | |
17897f36 JR |
2041 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2042 | vmcb->control.exit_info_1, | |
2043 | vmcb->control.exit_info_2, | |
2044 | vmcb->control.exit_int_info, | |
2045 | vmcb->control.exit_int_info_err); | |
2046 | ||
7597f129 | 2047 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2048 | if (!nested_vmcb) |
2049 | return 1; | |
2050 | ||
2030753d JR |
2051 | /* Exit Guest-Mode */ |
2052 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2053 | svm->nested.vmcb = 0; |
2054 | ||
cf74a78b | 2055 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2056 | disable_gif(svm); |
2057 | ||
2058 | nested_vmcb->save.es = vmcb->save.es; | |
2059 | nested_vmcb->save.cs = vmcb->save.cs; | |
2060 | nested_vmcb->save.ss = vmcb->save.ss; | |
2061 | nested_vmcb->save.ds = vmcb->save.ds; | |
2062 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2063 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2064 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2065 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
2be4fc7a | 2066 | nested_vmcb->save.cr3 = svm->vcpu.arch.cr3; |
33740e40 | 2067 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2068 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
33740e40 JR |
2069 | nested_vmcb->save.rflags = vmcb->save.rflags; |
2070 | nested_vmcb->save.rip = vmcb->save.rip; | |
2071 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2072 | nested_vmcb->save.rax = vmcb->save.rax; | |
2073 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2074 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2075 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2076 | ||
2077 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2078 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2079 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2080 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2081 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2082 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2083 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2084 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2085 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2086 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2087 | |
2088 | /* | |
2089 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2090 | * to make sure that we do not lose injected events. So check event_inj | |
2091 | * here and copy it to exit_int_info if it is valid. | |
2092 | * Exit_int_info and event_inj can't be both valid because the case | |
2093 | * below only happens on a VMRUN instruction intercept which has | |
2094 | * no valid exit_int_info set. | |
2095 | */ | |
2096 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2097 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2098 | ||
2099 | nc->exit_int_info = vmcb->control.event_inj; | |
2100 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2101 | } | |
2102 | ||
33740e40 JR |
2103 | nested_vmcb->control.tlb_ctl = 0; |
2104 | nested_vmcb->control.event_inj = 0; | |
2105 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2106 | |
2107 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2108 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2109 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2110 | ||
cf74a78b | 2111 | /* Restore the original control entries */ |
0460a979 | 2112 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2113 | |
219b65dc AG |
2114 | kvm_clear_exception_queue(&svm->vcpu); |
2115 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2116 | |
4b16184c JR |
2117 | svm->nested.nested_cr3 = 0; |
2118 | ||
cf74a78b AG |
2119 | /* Restore selected save entries */ |
2120 | svm->vmcb->save.es = hsave->save.es; | |
2121 | svm->vmcb->save.cs = hsave->save.cs; | |
2122 | svm->vmcb->save.ss = hsave->save.ss; | |
2123 | svm->vmcb->save.ds = hsave->save.ds; | |
2124 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2125 | svm->vmcb->save.idtr = hsave->save.idtr; | |
2126 | svm->vmcb->save.rflags = hsave->save.rflags; | |
2127 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
2128 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2129 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2130 | if (npt_enabled) { | |
2131 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2132 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2133 | } else { | |
2390218b | 2134 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2135 | } |
2136 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2137 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2138 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2139 | svm->vmcb->save.dr7 = 0; | |
2140 | svm->vmcb->save.cpl = 0; | |
2141 | svm->vmcb->control.exit_int_info = 0; | |
2142 | ||
7597f129 | 2143 | nested_svm_unmap(page); |
cf74a78b | 2144 | |
4b16184c | 2145 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2146 | kvm_mmu_reset_context(&svm->vcpu); |
2147 | kvm_mmu_load(&svm->vcpu); | |
2148 | ||
2149 | return 0; | |
2150 | } | |
3d6368ef | 2151 | |
9738b2c9 | 2152 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2153 | { |
323c3d80 JR |
2154 | /* |
2155 | * This function merges the msr permission bitmaps of kvm and the | |
2156 | * nested vmcb. It is omptimized in that it only merges the parts where | |
2157 | * the kvm msr permission bitmap may contain zero bits | |
2158 | */ | |
3d6368ef | 2159 | int i; |
9738b2c9 | 2160 | |
323c3d80 JR |
2161 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2162 | return true; | |
9738b2c9 | 2163 | |
323c3d80 JR |
2164 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2165 | u32 value, p; | |
2166 | u64 offset; | |
9738b2c9 | 2167 | |
323c3d80 JR |
2168 | if (msrpm_offsets[i] == 0xffffffff) |
2169 | break; | |
3d6368ef | 2170 | |
0d6b3537 JR |
2171 | p = msrpm_offsets[i]; |
2172 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2173 | |
2174 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2175 | return false; | |
2176 | ||
2177 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2178 | } | |
3d6368ef | 2179 | |
323c3d80 | 2180 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2181 | |
2182 | return true; | |
3d6368ef AG |
2183 | } |
2184 | ||
52c65a30 JR |
2185 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2186 | { | |
2187 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2188 | return false; | |
2189 | ||
dbe77584 JR |
2190 | if (vmcb->control.asid == 0) |
2191 | return false; | |
2192 | ||
4b16184c JR |
2193 | if (vmcb->control.nested_ctl && !npt_enabled) |
2194 | return false; | |
2195 | ||
52c65a30 JR |
2196 | return true; |
2197 | } | |
2198 | ||
9738b2c9 | 2199 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2200 | { |
9738b2c9 | 2201 | struct vmcb *nested_vmcb; |
e6aa9abd | 2202 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2203 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2204 | struct page *page; |
06fc7772 | 2205 | u64 vmcb_gpa; |
3d6368ef | 2206 | |
06fc7772 | 2207 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2208 | |
7597f129 | 2209 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2210 | if (!nested_vmcb) |
2211 | return false; | |
2212 | ||
52c65a30 JR |
2213 | if (!nested_vmcb_checks(nested_vmcb)) { |
2214 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2215 | nested_vmcb->control.exit_code_hi = 0; | |
2216 | nested_vmcb->control.exit_info_1 = 0; | |
2217 | nested_vmcb->control.exit_info_2 = 0; | |
2218 | ||
2219 | nested_svm_unmap(page); | |
2220 | ||
2221 | return false; | |
2222 | } | |
2223 | ||
b75f4eb3 | 2224 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2225 | nested_vmcb->save.rip, |
2226 | nested_vmcb->control.int_ctl, | |
2227 | nested_vmcb->control.event_inj, | |
2228 | nested_vmcb->control.nested_ctl); | |
2229 | ||
4ee546b4 RJ |
2230 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2231 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2232 | nested_vmcb->control.intercept_exceptions, |
2233 | nested_vmcb->control.intercept); | |
2234 | ||
3d6368ef | 2235 | /* Clear internal status */ |
219b65dc AG |
2236 | kvm_clear_exception_queue(&svm->vcpu); |
2237 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2238 | |
e0231715 JR |
2239 | /* |
2240 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2241 | * restore everything when a VMEXIT occurs | |
2242 | */ | |
defbba56 JR |
2243 | hsave->save.es = vmcb->save.es; |
2244 | hsave->save.cs = vmcb->save.cs; | |
2245 | hsave->save.ss = vmcb->save.ss; | |
2246 | hsave->save.ds = vmcb->save.ds; | |
2247 | hsave->save.gdtr = vmcb->save.gdtr; | |
2248 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2249 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2250 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 JR |
2251 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
2252 | hsave->save.rflags = vmcb->save.rflags; | |
b75f4eb3 | 2253 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2254 | hsave->save.rsp = vmcb->save.rsp; |
2255 | hsave->save.rax = vmcb->save.rax; | |
2256 | if (npt_enabled) | |
2257 | hsave->save.cr3 = vmcb->save.cr3; | |
2258 | else | |
2259 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
2260 | ||
0460a979 | 2261 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
2262 | |
2263 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
2264 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
2265 | else | |
2266 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2267 | ||
4b16184c JR |
2268 | if (nested_vmcb->control.nested_ctl) { |
2269 | kvm_mmu_unload(&svm->vcpu); | |
2270 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2271 | nested_svm_init_mmu_context(&svm->vcpu); | |
2272 | } | |
2273 | ||
3d6368ef AG |
2274 | /* Load the nested guest state */ |
2275 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2276 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2277 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2278 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2279 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2280 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
2281 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
2282 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
2283 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2284 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2285 | if (npt_enabled) { | |
2286 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2287 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2288 | } else |
2390218b | 2289 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2290 | |
2291 | /* Guest paging mode is active - reset mmu */ | |
2292 | kvm_mmu_reset_context(&svm->vcpu); | |
2293 | ||
defbba56 | 2294 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2295 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2296 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2297 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2298 | |
3d6368ef AG |
2299 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2300 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2301 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2302 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2303 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2304 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2305 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2306 | ||
f7138538 | 2307 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2308 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2309 | |
aad42c64 | 2310 | /* cache intercepts */ |
4ee546b4 | 2311 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2312 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2313 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2314 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2315 | ||
3d6368ef | 2316 | force_new_asid(&svm->vcpu); |
3d6368ef | 2317 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2318 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2319 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2320 | else | |
2321 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2322 | ||
88ab24ad JR |
2323 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2324 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2325 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2326 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2327 | } |
2328 | ||
0d945bd9 | 2329 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2330 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2331 | |
88ab24ad | 2332 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2333 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2334 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2335 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2336 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2337 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2338 | ||
7597f129 | 2339 | nested_svm_unmap(page); |
9738b2c9 | 2340 | |
2030753d JR |
2341 | /* Enter Guest-Mode */ |
2342 | enter_guest_mode(&svm->vcpu); | |
2343 | ||
384c6368 JR |
2344 | /* |
2345 | * Merge guest and host intercepts - must be called with vcpu in | |
2346 | * guest-mode to take affect here | |
2347 | */ | |
2348 | recalc_intercepts(svm); | |
2349 | ||
06fc7772 | 2350 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2351 | |
2af9194d | 2352 | enable_gif(svm); |
3d6368ef | 2353 | |
9738b2c9 | 2354 | return true; |
3d6368ef AG |
2355 | } |
2356 | ||
9966bf68 | 2357 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2358 | { |
2359 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2360 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2361 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2362 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2363 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2364 | to_vmcb->save.star = from_vmcb->save.star; | |
2365 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2366 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2367 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2368 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2369 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2370 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2371 | } |
2372 | ||
851ba692 | 2373 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2374 | { |
9966bf68 | 2375 | struct vmcb *nested_vmcb; |
7597f129 | 2376 | struct page *page; |
9966bf68 | 2377 | |
5542675b AG |
2378 | if (nested_svm_check_permissions(svm)) |
2379 | return 1; | |
2380 | ||
2381 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2382 | skip_emulated_instruction(&svm->vcpu); | |
2383 | ||
7597f129 | 2384 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2385 | if (!nested_vmcb) |
2386 | return 1; | |
2387 | ||
2388 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 2389 | nested_svm_unmap(page); |
5542675b AG |
2390 | |
2391 | return 1; | |
2392 | } | |
2393 | ||
851ba692 | 2394 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2395 | { |
9966bf68 | 2396 | struct vmcb *nested_vmcb; |
7597f129 | 2397 | struct page *page; |
9966bf68 | 2398 | |
5542675b AG |
2399 | if (nested_svm_check_permissions(svm)) |
2400 | return 1; | |
2401 | ||
2402 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2403 | skip_emulated_instruction(&svm->vcpu); | |
2404 | ||
7597f129 | 2405 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2406 | if (!nested_vmcb) |
2407 | return 1; | |
2408 | ||
2409 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 2410 | nested_svm_unmap(page); |
5542675b AG |
2411 | |
2412 | return 1; | |
2413 | } | |
2414 | ||
851ba692 | 2415 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2416 | { |
3d6368ef AG |
2417 | if (nested_svm_check_permissions(svm)) |
2418 | return 1; | |
2419 | ||
b75f4eb3 RJ |
2420 | /* Save rip after vmrun instruction */ |
2421 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2422 | |
9738b2c9 | 2423 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2424 | return 1; |
2425 | ||
9738b2c9 | 2426 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2427 | goto failed; |
2428 | ||
2429 | return 1; | |
2430 | ||
2431 | failed: | |
2432 | ||
2433 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2434 | svm->vmcb->control.exit_code_hi = 0; | |
2435 | svm->vmcb->control.exit_info_1 = 0; | |
2436 | svm->vmcb->control.exit_info_2 = 0; | |
2437 | ||
2438 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2439 | |
2440 | return 1; | |
2441 | } | |
2442 | ||
851ba692 | 2443 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2444 | { |
2445 | if (nested_svm_check_permissions(svm)) | |
2446 | return 1; | |
2447 | ||
2448 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2449 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2450 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2451 | |
2af9194d | 2452 | enable_gif(svm); |
1371d904 AG |
2453 | |
2454 | return 1; | |
2455 | } | |
2456 | ||
851ba692 | 2457 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2458 | { |
2459 | if (nested_svm_check_permissions(svm)) | |
2460 | return 1; | |
2461 | ||
2462 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2463 | skip_emulated_instruction(&svm->vcpu); | |
2464 | ||
2af9194d | 2465 | disable_gif(svm); |
1371d904 AG |
2466 | |
2467 | /* After a CLGI no interrupts should come */ | |
2468 | svm_clear_vintr(svm); | |
2469 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2470 | ||
2471 | return 1; | |
2472 | } | |
2473 | ||
851ba692 | 2474 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2475 | { |
2476 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2477 | |
ec1ff790 JR |
2478 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2479 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2480 | ||
ff092385 AG |
2481 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2482 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2483 | ||
2484 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2485 | skip_emulated_instruction(&svm->vcpu); | |
2486 | return 1; | |
2487 | } | |
2488 | ||
532a46b9 JR |
2489 | static int skinit_interception(struct vcpu_svm *svm) |
2490 | { | |
2491 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2492 | ||
2493 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2494 | return 1; | |
2495 | } | |
2496 | ||
851ba692 | 2497 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2498 | { |
7ee5d940 | 2499 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2500 | return 1; |
2501 | } | |
2502 | ||
851ba692 | 2503 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2504 | { |
37817f29 | 2505 | u16 tss_selector; |
64a7ec06 GN |
2506 | int reason; |
2507 | int int_type = svm->vmcb->control.exit_int_info & | |
2508 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2509 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2510 | uint32_t type = |
2511 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2512 | uint32_t idt_v = | |
2513 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2514 | bool has_error_code = false; |
2515 | u32 error_code = 0; | |
37817f29 IE |
2516 | |
2517 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2518 | |
37817f29 IE |
2519 | if (svm->vmcb->control.exit_info_2 & |
2520 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2521 | reason = TASK_SWITCH_IRET; |
2522 | else if (svm->vmcb->control.exit_info_2 & | |
2523 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2524 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2525 | else if (idt_v) |
64a7ec06 GN |
2526 | reason = TASK_SWITCH_GATE; |
2527 | else | |
2528 | reason = TASK_SWITCH_CALL; | |
2529 | ||
fe8e7f83 GN |
2530 | if (reason == TASK_SWITCH_GATE) { |
2531 | switch (type) { | |
2532 | case SVM_EXITINTINFO_TYPE_NMI: | |
2533 | svm->vcpu.arch.nmi_injected = false; | |
2534 | break; | |
2535 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2536 | if (svm->vmcb->control.exit_info_2 & |
2537 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2538 | has_error_code = true; | |
2539 | error_code = | |
2540 | (u32)svm->vmcb->control.exit_info_2; | |
2541 | } | |
fe8e7f83 GN |
2542 | kvm_clear_exception_queue(&svm->vcpu); |
2543 | break; | |
2544 | case SVM_EXITINTINFO_TYPE_INTR: | |
2545 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2546 | break; | |
2547 | default: | |
2548 | break; | |
2549 | } | |
2550 | } | |
64a7ec06 | 2551 | |
8317c298 GN |
2552 | if (reason != TASK_SWITCH_GATE || |
2553 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2554 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2555 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2556 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2557 | |
acb54517 GN |
2558 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2559 | has_error_code, error_code) == EMULATE_FAIL) { | |
2560 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2561 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2562 | svm->vcpu.run->internal.ndata = 0; | |
2563 | return 0; | |
2564 | } | |
2565 | return 1; | |
6aa8b732 AK |
2566 | } |
2567 | ||
851ba692 | 2568 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2569 | { |
5fdbf976 | 2570 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2571 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2572 | return 1; |
6aa8b732 AK |
2573 | } |
2574 | ||
851ba692 | 2575 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2576 | { |
2577 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2578 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2579 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2580 | return 1; |
2581 | } | |
2582 | ||
851ba692 | 2583 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2584 | { |
6d77dbfc | 2585 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; |
a7052897 MT |
2586 | } |
2587 | ||
851ba692 | 2588 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2589 | { |
6d77dbfc | 2590 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; |
6aa8b732 AK |
2591 | } |
2592 | ||
cda00082 JR |
2593 | static int cr0_write_interception(struct vcpu_svm *svm) |
2594 | { | |
2595 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
2596 | int r; | |
2597 | ||
2598 | r = emulate_instruction(&svm->vcpu, 0, 0, 0); | |
2599 | ||
2600 | if (svm->nested.vmexit_rip) { | |
2601 | kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip); | |
2602 | kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp); | |
2603 | kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax); | |
2604 | svm->nested.vmexit_rip = 0; | |
2605 | } | |
2606 | ||
2607 | return r == EMULATE_DONE; | |
2608 | } | |
2609 | ||
851ba692 | 2610 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2611 | { |
851ba692 AK |
2612 | struct kvm_run *kvm_run = svm->vcpu.run; |
2613 | ||
0a5fff19 GN |
2614 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2615 | /* instruction emulation calls kvm_set_cr8() */ | |
851ba692 | 2616 | emulate_instruction(&svm->vcpu, 0, 0, 0); |
95ba8273 | 2617 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2618 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
1d075434 | 2619 | return 1; |
95ba8273 | 2620 | } |
0a5fff19 GN |
2621 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
2622 | return 1; | |
1d075434 JR |
2623 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2624 | return 0; | |
2625 | } | |
2626 | ||
6aa8b732 AK |
2627 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2628 | { | |
a2fa3e9f GH |
2629 | struct vcpu_svm *svm = to_svm(vcpu); |
2630 | ||
6aa8b732 | 2631 | switch (ecx) { |
af24a4e4 | 2632 | case MSR_IA32_TSC: { |
20824f30 | 2633 | u64 tsc_offset; |
6aa8b732 | 2634 | |
2030753d | 2635 | if (is_guest_mode(vcpu)) |
20824f30 JR |
2636 | tsc_offset = svm->nested.hsave->control.tsc_offset; |
2637 | else | |
2638 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2639 | ||
2640 | *data = tsc_offset + native_read_tsc(); | |
6aa8b732 AK |
2641 | break; |
2642 | } | |
8c06585d | 2643 | case MSR_STAR: |
a2fa3e9f | 2644 | *data = svm->vmcb->save.star; |
6aa8b732 | 2645 | break; |
0e859cac | 2646 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2647 | case MSR_LSTAR: |
a2fa3e9f | 2648 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2649 | break; |
2650 | case MSR_CSTAR: | |
a2fa3e9f | 2651 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2652 | break; |
2653 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2654 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2655 | break; |
2656 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2657 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2658 | break; |
2659 | #endif | |
2660 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2661 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2662 | break; |
2663 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2664 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2665 | break; |
2666 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2667 | *data = svm->sysenter_esp; |
6aa8b732 | 2668 | break; |
e0231715 JR |
2669 | /* |
2670 | * Nobody will change the following 5 values in the VMCB so we can | |
2671 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2672 | * implemented. | |
2673 | */ | |
a2938c80 JR |
2674 | case MSR_IA32_DEBUGCTLMSR: |
2675 | *data = svm->vmcb->save.dbgctl; | |
2676 | break; | |
2677 | case MSR_IA32_LASTBRANCHFROMIP: | |
2678 | *data = svm->vmcb->save.br_from; | |
2679 | break; | |
2680 | case MSR_IA32_LASTBRANCHTOIP: | |
2681 | *data = svm->vmcb->save.br_to; | |
2682 | break; | |
2683 | case MSR_IA32_LASTINTFROMIP: | |
2684 | *data = svm->vmcb->save.last_excp_from; | |
2685 | break; | |
2686 | case MSR_IA32_LASTINTTOIP: | |
2687 | *data = svm->vmcb->save.last_excp_to; | |
2688 | break; | |
b286d5d8 | 2689 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2690 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2691 | break; |
eb6f302e | 2692 | case MSR_VM_CR: |
4a810181 | 2693 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 2694 | break; |
c8a73f18 AG |
2695 | case MSR_IA32_UCODE_REV: |
2696 | *data = 0x01000065; | |
2697 | break; | |
6aa8b732 | 2698 | default: |
3bab1f5d | 2699 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2700 | } |
2701 | return 0; | |
2702 | } | |
2703 | ||
851ba692 | 2704 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2705 | { |
ad312c7c | 2706 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2707 | u64 data; |
2708 | ||
59200273 AK |
2709 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2710 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2711 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2712 | } else { |
229456fc | 2713 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2714 | |
5fdbf976 | 2715 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2716 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2717 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2718 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2719 | } |
2720 | return 1; | |
2721 | } | |
2722 | ||
4a810181 JR |
2723 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
2724 | { | |
2725 | struct vcpu_svm *svm = to_svm(vcpu); | |
2726 | int svm_dis, chg_mask; | |
2727 | ||
2728 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2729 | return 1; | |
2730 | ||
2731 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2732 | ||
2733 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2734 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2735 | ||
2736 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2737 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2738 | ||
2739 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2740 | ||
2741 | /* check for svm_disable while efer.svme is set */ | |
2742 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2743 | return 1; | |
2744 | ||
2745 | return 0; | |
2746 | } | |
2747 | ||
6aa8b732 AK |
2748 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
2749 | { | |
a2fa3e9f GH |
2750 | struct vcpu_svm *svm = to_svm(vcpu); |
2751 | ||
6aa8b732 | 2752 | switch (ecx) { |
f4e1b3c8 | 2753 | case MSR_IA32_TSC: |
99e3e30a | 2754 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 2755 | break; |
8c06585d | 2756 | case MSR_STAR: |
a2fa3e9f | 2757 | svm->vmcb->save.star = data; |
6aa8b732 | 2758 | break; |
49b14f24 | 2759 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2760 | case MSR_LSTAR: |
a2fa3e9f | 2761 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2762 | break; |
2763 | case MSR_CSTAR: | |
a2fa3e9f | 2764 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2765 | break; |
2766 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2767 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2768 | break; |
2769 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2770 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2771 | break; |
2772 | #endif | |
2773 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2774 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2775 | break; |
2776 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2777 | svm->sysenter_eip = data; |
a2fa3e9f | 2778 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2779 | break; |
2780 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2781 | svm->sysenter_esp = data; |
a2fa3e9f | 2782 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2783 | break; |
a2938c80 | 2784 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 2785 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
24e09cbf | 2786 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
b8688d51 | 2787 | __func__, data); |
24e09cbf JR |
2788 | break; |
2789 | } | |
2790 | if (data & DEBUGCTL_RESERVED_BITS) | |
2791 | return 1; | |
2792 | ||
2793 | svm->vmcb->save.dbgctl = data; | |
2794 | if (data & (1ULL<<0)) | |
2795 | svm_enable_lbrv(svm); | |
2796 | else | |
2797 | svm_disable_lbrv(svm); | |
a2938c80 | 2798 | break; |
b286d5d8 | 2799 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2800 | svm->nested.hsave_msr = data; |
62b9abaa | 2801 | break; |
3c5d0a44 | 2802 | case MSR_VM_CR: |
4a810181 | 2803 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 2804 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
2805 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2806 | break; | |
6aa8b732 | 2807 | default: |
3bab1f5d | 2808 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2809 | } |
2810 | return 0; | |
2811 | } | |
2812 | ||
851ba692 | 2813 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2814 | { |
ad312c7c | 2815 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2816 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2817 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2818 | |
af9ca2d7 | 2819 | |
5fdbf976 | 2820 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2821 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2822 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 2823 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
2824 | } else { |
2825 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 2826 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 2827 | } |
6aa8b732 AK |
2828 | return 1; |
2829 | } | |
2830 | ||
851ba692 | 2831 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2832 | { |
e756fc62 | 2833 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2834 | return wrmsr_interception(svm); |
6aa8b732 | 2835 | else |
851ba692 | 2836 | return rdmsr_interception(svm); |
6aa8b732 AK |
2837 | } |
2838 | ||
851ba692 | 2839 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2840 | { |
851ba692 AK |
2841 | struct kvm_run *kvm_run = svm->vcpu.run; |
2842 | ||
3842d135 | 2843 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 2844 | svm_clear_vintr(svm); |
85f455f7 | 2845 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2846 | /* |
2847 | * If the user space waits to inject interrupts, exit as soon as | |
2848 | * possible | |
2849 | */ | |
8061823a GN |
2850 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
2851 | kvm_run->request_interrupt_window && | |
2852 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 2853 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2854 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2855 | return 0; | |
2856 | } | |
2857 | ||
2858 | return 1; | |
2859 | } | |
2860 | ||
565d0998 ML |
2861 | static int pause_interception(struct vcpu_svm *svm) |
2862 | { | |
2863 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
2864 | return 1; | |
2865 | } | |
2866 | ||
851ba692 | 2867 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
e0231715 JR |
2868 | [SVM_EXIT_READ_CR0] = emulate_on_interception, |
2869 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2870 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
2871 | [SVM_EXIT_READ_CR8] = emulate_on_interception, | |
d225157b | 2872 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
cda00082 | 2873 | [SVM_EXIT_WRITE_CR0] = cr0_write_interception, |
e0231715 JR |
2874 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, |
2875 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
2876 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, | |
2877 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
6aa8b732 AK |
2878 | [SVM_EXIT_READ_DR1] = emulate_on_interception, |
2879 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2880 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
727f5a23 JK |
2881 | [SVM_EXIT_READ_DR4] = emulate_on_interception, |
2882 | [SVM_EXIT_READ_DR5] = emulate_on_interception, | |
2883 | [SVM_EXIT_READ_DR6] = emulate_on_interception, | |
2884 | [SVM_EXIT_READ_DR7] = emulate_on_interception, | |
6aa8b732 AK |
2885 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, |
2886 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2887 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2888 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
727f5a23 | 2889 | [SVM_EXIT_WRITE_DR4] = emulate_on_interception, |
6aa8b732 | 2890 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, |
727f5a23 | 2891 | [SVM_EXIT_WRITE_DR6] = emulate_on_interception, |
6aa8b732 | 2892 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, |
d0bfb940 JK |
2893 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
2894 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 2895 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
2896 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
2897 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
2898 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
2899 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 2900 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2901 | [SVM_EXIT_SMI] = nop_on_interception, |
2902 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2903 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 | 2904 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 2905 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 2906 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 2907 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 2908 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2909 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 2910 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 2911 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
2912 | [SVM_EXIT_MSR] = msr_interception, |
2913 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2914 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2915 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2916 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2917 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2918 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2919 | [SVM_EXIT_STGI] = stgi_interception, |
2920 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 2921 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 2922 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2923 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2924 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2925 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2926 | }; |
2927 | ||
3f10c846 JR |
2928 | void dump_vmcb(struct kvm_vcpu *vcpu) |
2929 | { | |
2930 | struct vcpu_svm *svm = to_svm(vcpu); | |
2931 | struct vmcb_control_area *control = &svm->vmcb->control; | |
2932 | struct vmcb_save_area *save = &svm->vmcb->save; | |
2933 | ||
2934 | pr_err("VMCB Control Area:\n"); | |
4ee546b4 RJ |
2935 | pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff); |
2936 | pr_err("cr_write: %04x\n", control->intercept_cr >> 16); | |
3aed041a JR |
2937 | pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff); |
2938 | pr_err("dr_write: %04x\n", control->intercept_dr >> 16); | |
3f10c846 JR |
2939 | pr_err("exceptions: %08x\n", control->intercept_exceptions); |
2940 | pr_err("intercepts: %016llx\n", control->intercept); | |
2941 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
2942 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
2943 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
2944 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
2945 | pr_err("asid: %d\n", control->asid); | |
2946 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
2947 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
2948 | pr_err("int_vector: %08x\n", control->int_vector); | |
2949 | pr_err("int_state: %08x\n", control->int_state); | |
2950 | pr_err("exit_code: %08x\n", control->exit_code); | |
2951 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
2952 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
2953 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
2954 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
2955 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
2956 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
2957 | pr_err("event_inj: %08x\n", control->event_inj); | |
2958 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
2959 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
2960 | pr_err("next_rip: %016llx\n", control->next_rip); | |
2961 | pr_err("VMCB State Save Area:\n"); | |
2962 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
2963 | save->es.selector, save->es.attrib, | |
2964 | save->es.limit, save->es.base); | |
2965 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2966 | save->cs.selector, save->cs.attrib, | |
2967 | save->cs.limit, save->cs.base); | |
2968 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
2969 | save->ss.selector, save->ss.attrib, | |
2970 | save->ss.limit, save->ss.base); | |
2971 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
2972 | save->ds.selector, save->ds.attrib, | |
2973 | save->ds.limit, save->ds.base); | |
2974 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2975 | save->fs.selector, save->fs.attrib, | |
2976 | save->fs.limit, save->fs.base); | |
2977 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2978 | save->gs.selector, save->gs.attrib, | |
2979 | save->gs.limit, save->gs.base); | |
2980 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2981 | save->gdtr.selector, save->gdtr.attrib, | |
2982 | save->gdtr.limit, save->gdtr.base); | |
2983 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2984 | save->ldtr.selector, save->ldtr.attrib, | |
2985 | save->ldtr.limit, save->ldtr.base); | |
2986 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2987 | save->idtr.selector, save->idtr.attrib, | |
2988 | save->idtr.limit, save->idtr.base); | |
2989 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2990 | save->tr.selector, save->tr.attrib, | |
2991 | save->tr.limit, save->tr.base); | |
2992 | pr_err("cpl: %d efer: %016llx\n", | |
2993 | save->cpl, save->efer); | |
2994 | pr_err("cr0: %016llx cr2: %016llx\n", | |
2995 | save->cr0, save->cr2); | |
2996 | pr_err("cr3: %016llx cr4: %016llx\n", | |
2997 | save->cr3, save->cr4); | |
2998 | pr_err("dr6: %016llx dr7: %016llx\n", | |
2999 | save->dr6, save->dr7); | |
3000 | pr_err("rip: %016llx rflags: %016llx\n", | |
3001 | save->rip, save->rflags); | |
3002 | pr_err("rsp: %016llx rax: %016llx\n", | |
3003 | save->rsp, save->rax); | |
3004 | pr_err("star: %016llx lstar: %016llx\n", | |
3005 | save->star, save->lstar); | |
3006 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
3007 | save->cstar, save->sfmask); | |
3008 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
3009 | save->kernel_gs_base, save->sysenter_cs); | |
3010 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
3011 | save->sysenter_esp, save->sysenter_eip); | |
3012 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
3013 | save->g_pat, save->dbgctl); | |
3014 | pr_err("br_from: %016llx br_to: %016llx\n", | |
3015 | save->br_from, save->br_to); | |
3016 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
3017 | save->last_excp_from, save->last_excp_to); | |
3018 | ||
3019 | } | |
3020 | ||
586f9607 AK |
3021 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3022 | { | |
3023 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3024 | ||
3025 | *info1 = control->exit_info_1; | |
3026 | *info2 = control->exit_info_2; | |
3027 | } | |
3028 | ||
851ba692 | 3029 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3030 | { |
04d2cc77 | 3031 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3032 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3033 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3034 | |
aa17911e | 3035 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
af9ca2d7 | 3036 | |
4ee546b4 | 3037 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3038 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3039 | if (npt_enabled) | |
3040 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3041 | |
cd3ff653 JR |
3042 | if (unlikely(svm->nested.exit_required)) { |
3043 | nested_svm_vmexit(svm); | |
3044 | svm->nested.exit_required = false; | |
3045 | ||
3046 | return 1; | |
3047 | } | |
3048 | ||
2030753d | 3049 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3050 | int vmexit; |
3051 | ||
d8cabddf JR |
3052 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3053 | svm->vmcb->control.exit_info_1, | |
3054 | svm->vmcb->control.exit_info_2, | |
3055 | svm->vmcb->control.exit_int_info, | |
3056 | svm->vmcb->control.exit_int_info_err); | |
3057 | ||
410e4d57 JR |
3058 | vmexit = nested_svm_exit_special(svm); |
3059 | ||
3060 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3061 | vmexit = nested_svm_exit_handled(svm); | |
3062 | ||
3063 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3064 | return 1; |
cf74a78b AG |
3065 | } |
3066 | ||
a5c3832d JR |
3067 | svm_complete_interrupts(svm); |
3068 | ||
04d2cc77 AK |
3069 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3070 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3071 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3072 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3073 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3074 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3075 | return 0; |
3076 | } | |
3077 | ||
a2fa3e9f | 3078 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3079 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3080 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3081 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3082 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3083 | "exit_code 0x%x\n", | |
b8688d51 | 3084 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3085 | exit_code); |
3086 | ||
9d8f549d | 3087 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3088 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3089 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3090 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3091 | return 0; |
3092 | } | |
3093 | ||
851ba692 | 3094 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3095 | } |
3096 | ||
3097 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3098 | { | |
3099 | int cpu = raw_smp_processor_id(); | |
3100 | ||
0fe1e009 TH |
3101 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3102 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3103 | load_TR_desc(); |
3104 | } | |
3105 | ||
e756fc62 | 3106 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3107 | { |
3108 | int cpu = raw_smp_processor_id(); | |
3109 | ||
0fe1e009 | 3110 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3111 | |
a2fa3e9f | 3112 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4b656b12 | 3113 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3114 | if (svm->asid_generation != sd->asid_generation) |
3115 | new_asid(svm, sd); | |
6aa8b732 AK |
3116 | } |
3117 | ||
95ba8273 GN |
3118 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3119 | { | |
3120 | struct vcpu_svm *svm = to_svm(vcpu); | |
3121 | ||
3122 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3123 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3124 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3125 | ++vcpu->stat.nmi_injections; |
3126 | } | |
6aa8b732 | 3127 | |
85f455f7 | 3128 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3129 | { |
3130 | struct vmcb_control_area *control; | |
3131 | ||
e756fc62 | 3132 | control = &svm->vmcb->control; |
85f455f7 | 3133 | control->int_vector = irq; |
6aa8b732 AK |
3134 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3135 | control->int_ctl |= V_IRQ_MASK | | |
3136 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
3137 | } | |
3138 | ||
66fd3f7f | 3139 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3140 | { |
3141 | struct vcpu_svm *svm = to_svm(vcpu); | |
3142 | ||
2af9194d | 3143 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3144 | |
9fb2d2b4 GN |
3145 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3146 | ++vcpu->stat.irq_injections; | |
3147 | ||
219b65dc AG |
3148 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3149 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3150 | } |
3151 | ||
95ba8273 | 3152 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3153 | { |
3154 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3155 | |
2030753d | 3156 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3157 | return; |
3158 | ||
95ba8273 | 3159 | if (irr == -1) |
aaacfc9a JR |
3160 | return; |
3161 | ||
95ba8273 | 3162 | if (tpr >= irr) |
4ee546b4 | 3163 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3164 | } |
aaacfc9a | 3165 | |
95ba8273 GN |
3166 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3167 | { | |
3168 | struct vcpu_svm *svm = to_svm(vcpu); | |
3169 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3170 | int ret; |
3171 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3172 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3173 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3174 | ||
3175 | return ret; | |
aaacfc9a JR |
3176 | } |
3177 | ||
3cfc3092 JK |
3178 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3179 | { | |
3180 | struct vcpu_svm *svm = to_svm(vcpu); | |
3181 | ||
3182 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3183 | } | |
3184 | ||
3185 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3186 | { | |
3187 | struct vcpu_svm *svm = to_svm(vcpu); | |
3188 | ||
3189 | if (masked) { | |
3190 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3191 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3192 | } else { |
3193 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3194 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3195 | } |
3196 | } | |
3197 | ||
78646121 GN |
3198 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3199 | { | |
3200 | struct vcpu_svm *svm = to_svm(vcpu); | |
3201 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3202 | int ret; |
3203 | ||
3204 | if (!gif_set(svm) || | |
3205 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3206 | return 0; | |
3207 | ||
3208 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
3209 | ||
2030753d | 3210 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3211 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3212 | ||
3213 | return ret; | |
78646121 GN |
3214 | } |
3215 | ||
9222be18 | 3216 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3217 | { |
219b65dc | 3218 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3219 | |
e0231715 JR |
3220 | /* |
3221 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3222 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3223 | * get that intercept, this function will be called again though and | |
3224 | * we'll get the vintr intercept. | |
3225 | */ | |
8fe54654 | 3226 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3227 | svm_set_vintr(svm); |
3228 | svm_inject_irq(svm, 0x0); | |
3229 | } | |
85f455f7 ED |
3230 | } |
3231 | ||
95ba8273 | 3232 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3233 | { |
04d2cc77 | 3234 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3235 | |
44c11430 GN |
3236 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3237 | == HF_NMI_MASK) | |
3238 | return; /* IRET will cause a vm exit */ | |
3239 | ||
e0231715 JR |
3240 | /* |
3241 | * Something prevents NMI from been injected. Single step over possible | |
3242 | * problem (IRET or exception injection or interrupt shadow) | |
3243 | */ | |
6be7d306 | 3244 | svm->nmi_singlestep = true; |
44c11430 GN |
3245 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3246 | update_db_intercept(vcpu); | |
c1150d8c DL |
3247 | } |
3248 | ||
cbc94022 IE |
3249 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3250 | { | |
3251 | return 0; | |
3252 | } | |
3253 | ||
d9e368d6 AK |
3254 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3255 | { | |
3256 | force_new_asid(vcpu); | |
3257 | } | |
3258 | ||
04d2cc77 AK |
3259 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3260 | { | |
3261 | } | |
3262 | ||
d7bf8221 JR |
3263 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3264 | { | |
3265 | struct vcpu_svm *svm = to_svm(vcpu); | |
3266 | ||
2030753d | 3267 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3268 | return; |
3269 | ||
4ee546b4 | 3270 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3271 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3272 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3273 | } |
3274 | } | |
3275 | ||
649d6864 JR |
3276 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3277 | { | |
3278 | struct vcpu_svm *svm = to_svm(vcpu); | |
3279 | u64 cr8; | |
3280 | ||
2030753d | 3281 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3282 | return; |
3283 | ||
649d6864 JR |
3284 | cr8 = kvm_get_cr8(vcpu); |
3285 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3286 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3287 | } | |
3288 | ||
9222be18 GN |
3289 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3290 | { | |
3291 | u8 vector; | |
3292 | int type; | |
3293 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3294 | unsigned int3_injected = svm->int3_injected; |
3295 | ||
3296 | svm->int3_injected = 0; | |
9222be18 | 3297 | |
3842d135 | 3298 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) { |
44c11430 | 3299 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3300 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3301 | } | |
44c11430 | 3302 | |
9222be18 GN |
3303 | svm->vcpu.arch.nmi_injected = false; |
3304 | kvm_clear_exception_queue(&svm->vcpu); | |
3305 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3306 | ||
3307 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3308 | return; | |
3309 | ||
3842d135 AK |
3310 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3311 | ||
9222be18 GN |
3312 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3313 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3314 | ||
3315 | switch (type) { | |
3316 | case SVM_EXITINTINFO_TYPE_NMI: | |
3317 | svm->vcpu.arch.nmi_injected = true; | |
3318 | break; | |
3319 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3320 | /* |
3321 | * In case of software exceptions, do not reinject the vector, | |
3322 | * but re-execute the instruction instead. Rewind RIP first | |
3323 | * if we emulated INT3 before. | |
3324 | */ | |
3325 | if (kvm_exception_is_soft(vector)) { | |
3326 | if (vector == BP_VECTOR && int3_injected && | |
3327 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3328 | kvm_rip_write(&svm->vcpu, | |
3329 | kvm_rip_read(&svm->vcpu) - | |
3330 | int3_injected); | |
9222be18 | 3331 | break; |
66b7138f | 3332 | } |
9222be18 GN |
3333 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3334 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3335 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3336 | |
3337 | } else | |
ce7ddec4 | 3338 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3339 | break; |
3340 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3341 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3342 | break; |
3343 | default: | |
3344 | break; | |
3345 | } | |
3346 | } | |
3347 | ||
b463a6f7 AK |
3348 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3349 | { | |
3350 | struct vcpu_svm *svm = to_svm(vcpu); | |
3351 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3352 | ||
3353 | control->exit_int_info = control->event_inj; | |
3354 | control->exit_int_info_err = control->event_inj_err; | |
3355 | control->event_inj = 0; | |
3356 | svm_complete_interrupts(svm); | |
3357 | } | |
3358 | ||
80e31d4f AK |
3359 | #ifdef CONFIG_X86_64 |
3360 | #define R "r" | |
3361 | #else | |
3362 | #define R "e" | |
3363 | #endif | |
3364 | ||
851ba692 | 3365 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3366 | { |
a2fa3e9f | 3367 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3368 | |
2041a06a JR |
3369 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3370 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3371 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3372 | ||
cd3ff653 JR |
3373 | /* |
3374 | * A vmexit emulation is required before the vcpu can be executed | |
3375 | * again. | |
3376 | */ | |
3377 | if (unlikely(svm->nested.exit_required)) | |
3378 | return; | |
3379 | ||
e756fc62 | 3380 | pre_svm_run(svm); |
6aa8b732 | 3381 | |
649d6864 JR |
3382 | sync_lapic_to_cr8(vcpu); |
3383 | ||
cda0ffdd | 3384 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3385 | |
04d2cc77 AK |
3386 | clgi(); |
3387 | ||
3388 | local_irq_enable(); | |
36241b8c | 3389 | |
6aa8b732 | 3390 | asm volatile ( |
80e31d4f AK |
3391 | "push %%"R"bp; \n\t" |
3392 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3393 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3394 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3395 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3396 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3397 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3398 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3399 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3400 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3401 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3402 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3403 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3404 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3405 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3406 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3407 | #endif |
3408 | ||
6aa8b732 | 3409 | /* Enter guest mode */ |
80e31d4f AK |
3410 | "push %%"R"ax \n\t" |
3411 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3412 | __ex(SVM_VMLOAD) "\n\t" |
3413 | __ex(SVM_VMRUN) "\n\t" | |
3414 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3415 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3416 | |
3417 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3418 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3419 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3420 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3421 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3422 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3423 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3424 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3425 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3426 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3427 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3428 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3429 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3430 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3431 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3432 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3433 | #endif |
80e31d4f | 3434 | "pop %%"R"bp" |
6aa8b732 | 3435 | : |
fb3f0f51 | 3436 | : [svm]"a"(svm), |
6aa8b732 | 3437 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3438 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3439 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3440 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3441 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3442 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3443 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3444 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3445 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3446 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3447 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3448 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3449 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3450 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3451 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3452 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3453 | #endif |
54a08c04 | 3454 | : "cc", "memory" |
80e31d4f | 3455 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3456 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3457 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3458 | #endif | |
3459 | ); | |
6aa8b732 | 3460 | |
82ca2d10 AK |
3461 | #ifdef CONFIG_X86_64 |
3462 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3463 | #else | |
dacccfdd | 3464 | loadsegment(fs, svm->host.fs); |
9581d442 | 3465 | #endif |
6aa8b732 AK |
3466 | |
3467 | reload_tss(vcpu); | |
3468 | ||
56ba47dd AK |
3469 | local_irq_disable(); |
3470 | ||
3471 | stgi(); | |
3472 | ||
13c34e07 AK |
3473 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3474 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3475 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3476 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3477 | ||
d7bf8221 JR |
3478 | sync_cr8_to_lapic(vcpu); |
3479 | ||
a2fa3e9f | 3480 | svm->next_rip = 0; |
9222be18 | 3481 | |
631bc487 GN |
3482 | /* if exit due to PF check for async PF */ |
3483 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3484 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3485 | ||
6de4f3ad AK |
3486 | if (npt_enabled) { |
3487 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3488 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3489 | } | |
fe5913e4 JR |
3490 | |
3491 | /* | |
3492 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3493 | * change the physical cpu | |
3494 | */ | |
3495 | if (unlikely(svm->vmcb->control.exit_code == | |
3496 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3497 | svm_handle_mce(svm); | |
6aa8b732 AK |
3498 | } |
3499 | ||
80e31d4f AK |
3500 | #undef R |
3501 | ||
6aa8b732 AK |
3502 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3503 | { | |
a2fa3e9f GH |
3504 | struct vcpu_svm *svm = to_svm(vcpu); |
3505 | ||
3506 | svm->vmcb->save.cr3 = root; | |
6aa8b732 AK |
3507 | force_new_asid(vcpu); |
3508 | } | |
3509 | ||
1c97f0a0 JR |
3510 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3511 | { | |
3512 | struct vcpu_svm *svm = to_svm(vcpu); | |
3513 | ||
3514 | svm->vmcb->control.nested_cr3 = root; | |
3515 | ||
3516 | /* Also sync guest cr3 here in case we live migrate */ | |
3517 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
3518 | ||
3519 | force_new_asid(vcpu); | |
3520 | } | |
3521 | ||
6aa8b732 AK |
3522 | static int is_disabled(void) |
3523 | { | |
6031a61c JR |
3524 | u64 vm_cr; |
3525 | ||
3526 | rdmsrl(MSR_VM_CR, vm_cr); | |
3527 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3528 | return 1; | |
3529 | ||
6aa8b732 AK |
3530 | return 0; |
3531 | } | |
3532 | ||
102d8325 IM |
3533 | static void |
3534 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3535 | { | |
3536 | /* | |
3537 | * Patch in the VMMCALL instruction: | |
3538 | */ | |
3539 | hypercall[0] = 0x0f; | |
3540 | hypercall[1] = 0x01; | |
3541 | hypercall[2] = 0xd9; | |
102d8325 IM |
3542 | } |
3543 | ||
002c7f7c YS |
3544 | static void svm_check_processor_compat(void *rtn) |
3545 | { | |
3546 | *(int *)rtn = 0; | |
3547 | } | |
3548 | ||
774ead3a AK |
3549 | static bool svm_cpu_has_accelerated_tpr(void) |
3550 | { | |
3551 | return false; | |
3552 | } | |
3553 | ||
4b12f0de | 3554 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3555 | { |
3556 | return 0; | |
3557 | } | |
3558 | ||
0e851880 SY |
3559 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3560 | { | |
3561 | } | |
3562 | ||
d4330ef2 JR |
3563 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3564 | { | |
c2c63a49 | 3565 | switch (func) { |
24d1b15f JR |
3566 | case 0x00000001: |
3567 | /* Mask out xsave bit as long as it is not supported by SVM */ | |
3568 | entry->ecx &= ~(bit(X86_FEATURE_XSAVE)); | |
3569 | break; | |
4c62a2dc JR |
3570 | case 0x80000001: |
3571 | if (nested) | |
3572 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3573 | break; | |
c2c63a49 JR |
3574 | case 0x8000000A: |
3575 | entry->eax = 1; /* SVM revision 1 */ | |
3576 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3577 | ASID emulation to nested SVM */ | |
3578 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
3579 | entry->edx = 0; /* Per default do not support any |
3580 | additional features */ | |
3581 | ||
3582 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 3583 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 3584 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 3585 | |
3d4aeaad JR |
3586 | /* Support NPT for the guest if enabled */ |
3587 | if (npt_enabled) | |
3588 | entry->edx |= SVM_FEATURE_NPT; | |
3589 | ||
c2c63a49 JR |
3590 | break; |
3591 | } | |
d4330ef2 JR |
3592 | } |
3593 | ||
229456fc | 3594 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
e0231715 JR |
3595 | { SVM_EXIT_READ_CR0, "read_cr0" }, |
3596 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3597 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3598 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3599 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3600 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3601 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3602 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3603 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3604 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3605 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3606 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3607 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3608 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3609 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3610 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3611 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3612 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
229456fc MT |
3613 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, |
3614 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3615 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3616 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3617 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3618 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3619 | { SVM_EXIT_INTR, "interrupt" }, | |
3620 | { SVM_EXIT_NMI, "nmi" }, | |
3621 | { SVM_EXIT_SMI, "smi" }, | |
3622 | { SVM_EXIT_INIT, "init" }, | |
3623 | { SVM_EXIT_VINTR, "vintr" }, | |
3624 | { SVM_EXIT_CPUID, "cpuid" }, | |
3625 | { SVM_EXIT_INVD, "invd" }, | |
3626 | { SVM_EXIT_HLT, "hlt" }, | |
3627 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3628 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3629 | { SVM_EXIT_IOIO, "io" }, | |
3630 | { SVM_EXIT_MSR, "msr" }, | |
3631 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3632 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3633 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3634 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3635 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3636 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3637 | { SVM_EXIT_STGI, "stgi" }, | |
3638 | { SVM_EXIT_CLGI, "clgi" }, | |
3639 | { SVM_EXIT_SKINIT, "skinit" }, | |
3640 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3641 | { SVM_EXIT_MONITOR, "monitor" }, | |
3642 | { SVM_EXIT_MWAIT, "mwait" }, | |
3643 | { SVM_EXIT_NPF, "npf" }, | |
3644 | { -1, NULL } | |
3645 | }; | |
3646 | ||
17cc3935 | 3647 | static int svm_get_lpage_level(void) |
344f414f | 3648 | { |
17cc3935 | 3649 | return PT_PDPE_LEVEL; |
344f414f JR |
3650 | } |
3651 | ||
4e47c7a6 SY |
3652 | static bool svm_rdtscp_supported(void) |
3653 | { | |
3654 | return false; | |
3655 | } | |
3656 | ||
f5f48ee1 SY |
3657 | static bool svm_has_wbinvd_exit(void) |
3658 | { | |
3659 | return true; | |
3660 | } | |
3661 | ||
02daab21 AK |
3662 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
3663 | { | |
3664 | struct vcpu_svm *svm = to_svm(vcpu); | |
3665 | ||
18c918c5 | 3666 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 3667 | update_cr0_intercept(svm); |
02daab21 AK |
3668 | } |
3669 | ||
cbdd1bea | 3670 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
3671 | .cpu_has_kvm_support = has_svm, |
3672 | .disabled_by_bios = is_disabled, | |
3673 | .hardware_setup = svm_hardware_setup, | |
3674 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 3675 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
3676 | .hardware_enable = svm_hardware_enable, |
3677 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 3678 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
3679 | |
3680 | .vcpu_create = svm_create_vcpu, | |
3681 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 3682 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 3683 | |
04d2cc77 | 3684 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
3685 | .vcpu_load = svm_vcpu_load, |
3686 | .vcpu_put = svm_vcpu_put, | |
3687 | ||
3688 | .set_guest_debug = svm_guest_debug, | |
3689 | .get_msr = svm_get_msr, | |
3690 | .set_msr = svm_set_msr, | |
3691 | .get_segment_base = svm_get_segment_base, | |
3692 | .get_segment = svm_get_segment, | |
3693 | .set_segment = svm_set_segment, | |
2e4d2653 | 3694 | .get_cpl = svm_get_cpl, |
1747fb71 | 3695 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 3696 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
25c4c276 | 3697 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 3698 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
3699 | .set_cr3 = svm_set_cr3, |
3700 | .set_cr4 = svm_set_cr4, | |
3701 | .set_efer = svm_set_efer, | |
3702 | .get_idt = svm_get_idt, | |
3703 | .set_idt = svm_set_idt, | |
3704 | .get_gdt = svm_get_gdt, | |
3705 | .set_gdt = svm_set_gdt, | |
020df079 | 3706 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 3707 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
3708 | .get_rflags = svm_get_rflags, |
3709 | .set_rflags = svm_set_rflags, | |
6b52d186 | 3710 | .fpu_activate = svm_fpu_activate, |
02daab21 | 3711 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 3712 | |
6aa8b732 | 3713 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 3714 | |
6aa8b732 | 3715 | .run = svm_vcpu_run, |
04d2cc77 | 3716 | .handle_exit = handle_exit, |
6aa8b732 | 3717 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
3718 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
3719 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 3720 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 3721 | .set_irq = svm_set_irq, |
95ba8273 | 3722 | .set_nmi = svm_inject_nmi, |
298101da | 3723 | .queue_exception = svm_queue_exception, |
b463a6f7 | 3724 | .cancel_injection = svm_cancel_injection, |
78646121 | 3725 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 3726 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
3727 | .get_nmi_mask = svm_get_nmi_mask, |
3728 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
3729 | .enable_nmi_window = enable_nmi_window, |
3730 | .enable_irq_window = enable_irq_window, | |
3731 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
3732 | |
3733 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 3734 | .get_tdp_level = get_npt_level, |
4b12f0de | 3735 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 3736 | |
586f9607 | 3737 | .get_exit_info = svm_get_exit_info, |
229456fc | 3738 | .exit_reasons_str = svm_exit_reasons_str, |
586f9607 | 3739 | |
17cc3935 | 3740 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
3741 | |
3742 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
3743 | |
3744 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
3745 | |
3746 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
3747 | |
3748 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
3749 | |
3750 | .write_tsc_offset = svm_write_tsc_offset, | |
e48672fa | 3751 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
1c97f0a0 JR |
3752 | |
3753 | .set_tdp_cr3 = set_tdp_cr3, | |
6aa8b732 AK |
3754 | }; |
3755 | ||
3756 | static int __init svm_init(void) | |
3757 | { | |
cb498ea2 | 3758 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 3759 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
3760 | } |
3761 | ||
3762 | static void __exit svm_exit(void) | |
3763 | { | |
cb498ea2 | 3764 | kvm_exit(); |
6aa8b732 AK |
3765 | } |
3766 | ||
3767 | module_init(svm_init) | |
3768 | module_exit(svm_exit) |