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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
631bc487 | 34 | #include <asm/kvm_para.h> |
6aa8b732 | 35 | |
63d1142f | 36 | #include <asm/virtext.h> |
229456fc | 37 | #include "trace.h" |
63d1142f | 38 | |
4ecac3fd AK |
39 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
40 | ||
6aa8b732 AK |
41 | MODULE_AUTHOR("Qumranet"); |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | #define IOPM_ALLOC_ORDER 2 | |
45 | #define MSRPM_ALLOC_ORDER 1 | |
46 | ||
6aa8b732 AK |
47 | #define SEG_TYPE_LDT 2 |
48 | #define SEG_TYPE_BUSY_TSS16 3 | |
49 | ||
6bc31bdc AP |
50 | #define SVM_FEATURE_NPT (1 << 0) |
51 | #define SVM_FEATURE_LBRV (1 << 1) | |
52 | #define SVM_FEATURE_SVML (1 << 2) | |
53 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
54 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
55 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
56 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
57 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 58 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 59 | |
410e4d57 JR |
60 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
61 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
62 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
63 | ||
24e09cbf JR |
64 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
65 | ||
fbc0db76 JR |
66 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
67 | ||
67ec6607 JR |
68 | static bool erratum_383_found __read_mostly; |
69 | ||
6c8166a7 AK |
70 | static const u32 host_save_user_msrs[] = { |
71 | #ifdef CONFIG_X86_64 | |
72 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
73 | MSR_FS_BASE, | |
74 | #endif | |
75 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
76 | }; | |
77 | ||
78 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
79 | ||
80 | struct kvm_vcpu; | |
81 | ||
e6aa9abd JR |
82 | struct nested_state { |
83 | struct vmcb *hsave; | |
84 | u64 hsave_msr; | |
4a810181 | 85 | u64 vm_cr_msr; |
e6aa9abd JR |
86 | u64 vmcb; |
87 | ||
88 | /* These are the merged vectors */ | |
89 | u32 *msrpm; | |
90 | ||
91 | /* gpa pointers to the real vectors */ | |
92 | u64 vmcb_msrpm; | |
ce2ac085 | 93 | u64 vmcb_iopm; |
aad42c64 | 94 | |
cd3ff653 JR |
95 | /* A VMEXIT is required but not yet emulated */ |
96 | bool exit_required; | |
97 | ||
aad42c64 | 98 | /* cache for intercepts of the guest */ |
4ee546b4 | 99 | u32 intercept_cr; |
3aed041a | 100 | u32 intercept_dr; |
aad42c64 JR |
101 | u32 intercept_exceptions; |
102 | u64 intercept; | |
103 | ||
5bd2edc3 JR |
104 | /* Nested Paging related state */ |
105 | u64 nested_cr3; | |
e6aa9abd JR |
106 | }; |
107 | ||
323c3d80 JR |
108 | #define MSRPM_OFFSETS 16 |
109 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
110 | ||
6c8166a7 AK |
111 | struct vcpu_svm { |
112 | struct kvm_vcpu vcpu; | |
113 | struct vmcb *vmcb; | |
114 | unsigned long vmcb_pa; | |
115 | struct svm_cpu_data *svm_data; | |
116 | uint64_t asid_generation; | |
117 | uint64_t sysenter_esp; | |
118 | uint64_t sysenter_eip; | |
119 | ||
120 | u64 next_rip; | |
121 | ||
122 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 123 | struct { |
dacccfdd AK |
124 | u16 fs; |
125 | u16 gs; | |
126 | u16 ldt; | |
afe9e66f AK |
127 | u64 gs_base; |
128 | } host; | |
6c8166a7 AK |
129 | |
130 | u32 *msrpm; | |
6c8166a7 | 131 | |
bd3d1ec3 AK |
132 | ulong nmi_iret_rip; |
133 | ||
e6aa9abd | 134 | struct nested_state nested; |
6be7d306 JK |
135 | |
136 | bool nmi_singlestep; | |
66b7138f JK |
137 | |
138 | unsigned int3_injected; | |
139 | unsigned long int3_rip; | |
631bc487 | 140 | u32 apf_reason; |
fbc0db76 JR |
141 | |
142 | u64 tsc_ratio; | |
6c8166a7 AK |
143 | }; |
144 | ||
fbc0db76 JR |
145 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
146 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
147 | ||
455716fa JR |
148 | #define MSR_INVALID 0xffffffffU |
149 | ||
ac72a9b7 JR |
150 | static struct svm_direct_access_msrs { |
151 | u32 index; /* Index of the MSR */ | |
152 | bool always; /* True if intercept is always on */ | |
153 | } direct_access_msrs[] = { | |
8c06585d | 154 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
155 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
156 | #ifdef CONFIG_X86_64 | |
157 | { .index = MSR_GS_BASE, .always = true }, | |
158 | { .index = MSR_FS_BASE, .always = true }, | |
159 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
160 | { .index = MSR_LSTAR, .always = true }, | |
161 | { .index = MSR_CSTAR, .always = true }, | |
162 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
163 | #endif | |
164 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
165 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
166 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
167 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
168 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
169 | }; |
170 | ||
709ddebf JR |
171 | /* enable NPT for AMD64 and X86 with PAE */ |
172 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
173 | static bool npt_enabled = true; | |
174 | #else | |
e0231715 | 175 | static bool npt_enabled; |
709ddebf | 176 | #endif |
6c7dac72 JR |
177 | static int npt = 1; |
178 | ||
179 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 180 | |
4b6e4dca | 181 | static int nested = 1; |
236de055 AG |
182 | module_param(nested, int, S_IRUGO); |
183 | ||
44874f84 | 184 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 185 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 186 | |
410e4d57 | 187 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 188 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 189 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
190 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
191 | bool has_error_code, u32 error_code); | |
192 | ||
8d28fec4 | 193 | enum { |
116a0a23 JR |
194 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
195 | pause filter count */ | |
f56838e4 | 196 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 197 | VMCB_ASID, /* ASID */ |
decdbf6a | 198 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 199 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 200 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 201 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 202 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 203 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 204 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 205 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
206 | VMCB_DIRTY_MAX, |
207 | }; | |
208 | ||
0574dec0 JR |
209 | /* TPR and CR2 are always written before VMRUN */ |
210 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
211 | |
212 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
213 | { | |
214 | vmcb->control.clean = 0; | |
215 | } | |
216 | ||
217 | static inline void mark_all_clean(struct vmcb *vmcb) | |
218 | { | |
219 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
220 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
221 | } | |
222 | ||
223 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
224 | { | |
225 | vmcb->control.clean &= ~(1 << bit); | |
226 | } | |
227 | ||
a2fa3e9f GH |
228 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
229 | { | |
fb3f0f51 | 230 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
231 | } |
232 | ||
384c6368 JR |
233 | static void recalc_intercepts(struct vcpu_svm *svm) |
234 | { | |
235 | struct vmcb_control_area *c, *h; | |
236 | struct nested_state *g; | |
237 | ||
116a0a23 JR |
238 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
239 | ||
384c6368 JR |
240 | if (!is_guest_mode(&svm->vcpu)) |
241 | return; | |
242 | ||
243 | c = &svm->vmcb->control; | |
244 | h = &svm->nested.hsave->control; | |
245 | g = &svm->nested; | |
246 | ||
4ee546b4 | 247 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 248 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
249 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
250 | c->intercept = h->intercept | g->intercept; | |
251 | } | |
252 | ||
4ee546b4 RJ |
253 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
254 | { | |
255 | if (is_guest_mode(&svm->vcpu)) | |
256 | return svm->nested.hsave; | |
257 | else | |
258 | return svm->vmcb; | |
259 | } | |
260 | ||
261 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
262 | { | |
263 | struct vmcb *vmcb = get_host_vmcb(svm); | |
264 | ||
265 | vmcb->control.intercept_cr |= (1U << bit); | |
266 | ||
267 | recalc_intercepts(svm); | |
268 | } | |
269 | ||
270 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
271 | { | |
272 | struct vmcb *vmcb = get_host_vmcb(svm); | |
273 | ||
274 | vmcb->control.intercept_cr &= ~(1U << bit); | |
275 | ||
276 | recalc_intercepts(svm); | |
277 | } | |
278 | ||
279 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
280 | { | |
281 | struct vmcb *vmcb = get_host_vmcb(svm); | |
282 | ||
283 | return vmcb->control.intercept_cr & (1U << bit); | |
284 | } | |
285 | ||
3aed041a JR |
286 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
287 | { | |
288 | struct vmcb *vmcb = get_host_vmcb(svm); | |
289 | ||
290 | vmcb->control.intercept_dr |= (1U << bit); | |
291 | ||
292 | recalc_intercepts(svm); | |
293 | } | |
294 | ||
295 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
296 | { | |
297 | struct vmcb *vmcb = get_host_vmcb(svm); | |
298 | ||
299 | vmcb->control.intercept_dr &= ~(1U << bit); | |
300 | ||
301 | recalc_intercepts(svm); | |
302 | } | |
303 | ||
18c918c5 JR |
304 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
305 | { | |
306 | struct vmcb *vmcb = get_host_vmcb(svm); | |
307 | ||
308 | vmcb->control.intercept_exceptions |= (1U << bit); | |
309 | ||
310 | recalc_intercepts(svm); | |
311 | } | |
312 | ||
313 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
314 | { | |
315 | struct vmcb *vmcb = get_host_vmcb(svm); | |
316 | ||
317 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
318 | ||
319 | recalc_intercepts(svm); | |
320 | } | |
321 | ||
8a05a1b8 JR |
322 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
323 | { | |
324 | struct vmcb *vmcb = get_host_vmcb(svm); | |
325 | ||
326 | vmcb->control.intercept |= (1ULL << bit); | |
327 | ||
328 | recalc_intercepts(svm); | |
329 | } | |
330 | ||
331 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
332 | { | |
333 | struct vmcb *vmcb = get_host_vmcb(svm); | |
334 | ||
335 | vmcb->control.intercept &= ~(1ULL << bit); | |
336 | ||
337 | recalc_intercepts(svm); | |
338 | } | |
339 | ||
2af9194d JR |
340 | static inline void enable_gif(struct vcpu_svm *svm) |
341 | { | |
342 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
343 | } | |
344 | ||
345 | static inline void disable_gif(struct vcpu_svm *svm) | |
346 | { | |
347 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
348 | } | |
349 | ||
350 | static inline bool gif_set(struct vcpu_svm *svm) | |
351 | { | |
352 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
353 | } | |
354 | ||
4866d5e3 | 355 | static unsigned long iopm_base; |
6aa8b732 AK |
356 | |
357 | struct kvm_ldttss_desc { | |
358 | u16 limit0; | |
359 | u16 base0; | |
e0231715 JR |
360 | unsigned base1:8, type:5, dpl:2, p:1; |
361 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
362 | u32 base3; |
363 | u32 zero1; | |
364 | } __attribute__((packed)); | |
365 | ||
366 | struct svm_cpu_data { | |
367 | int cpu; | |
368 | ||
5008fdf5 AK |
369 | u64 asid_generation; |
370 | u32 max_asid; | |
371 | u32 next_asid; | |
6aa8b732 AK |
372 | struct kvm_ldttss_desc *tss_desc; |
373 | ||
374 | struct page *save_area; | |
375 | }; | |
376 | ||
377 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
378 | ||
379 | struct svm_init_data { | |
380 | int cpu; | |
381 | int r; | |
382 | }; | |
383 | ||
384 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
385 | ||
9d8f549d | 386 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
387 | #define MSRS_RANGE_SIZE 2048 |
388 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
389 | ||
455716fa JR |
390 | static u32 svm_msrpm_offset(u32 msr) |
391 | { | |
392 | u32 offset; | |
393 | int i; | |
394 | ||
395 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
396 | if (msr < msrpm_ranges[i] || | |
397 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
398 | continue; | |
399 | ||
400 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
401 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
402 | ||
403 | /* Now we have the u8 offset - but need the u32 offset */ | |
404 | return offset / 4; | |
405 | } | |
406 | ||
407 | /* MSR not in any range */ | |
408 | return MSR_INVALID; | |
409 | } | |
410 | ||
6aa8b732 AK |
411 | #define MAX_INST_SIZE 15 |
412 | ||
6aa8b732 AK |
413 | static inline void clgi(void) |
414 | { | |
4ecac3fd | 415 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
416 | } |
417 | ||
418 | static inline void stgi(void) | |
419 | { | |
4ecac3fd | 420 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
421 | } |
422 | ||
423 | static inline void invlpga(unsigned long addr, u32 asid) | |
424 | { | |
e0231715 | 425 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
426 | } |
427 | ||
4b16184c JR |
428 | static int get_npt_level(void) |
429 | { | |
430 | #ifdef CONFIG_X86_64 | |
431 | return PT64_ROOT_LEVEL; | |
432 | #else | |
433 | return PT32E_ROOT_LEVEL; | |
434 | #endif | |
435 | } | |
436 | ||
6aa8b732 AK |
437 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
438 | { | |
6dc696d4 | 439 | vcpu->arch.efer = efer; |
709ddebf | 440 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 441 | efer &= ~EFER_LME; |
6aa8b732 | 442 | |
9962d032 | 443 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 444 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
445 | } |
446 | ||
6aa8b732 AK |
447 | static int is_external_interrupt(u32 info) |
448 | { | |
449 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
450 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
451 | } | |
452 | ||
2809f5d2 GC |
453 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
454 | { | |
455 | struct vcpu_svm *svm = to_svm(vcpu); | |
456 | u32 ret = 0; | |
457 | ||
458 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 459 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
460 | return ret & mask; |
461 | } | |
462 | ||
463 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
464 | { | |
465 | struct vcpu_svm *svm = to_svm(vcpu); | |
466 | ||
467 | if (mask == 0) | |
468 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
469 | else | |
470 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
471 | ||
472 | } | |
473 | ||
6aa8b732 AK |
474 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
475 | { | |
a2fa3e9f GH |
476 | struct vcpu_svm *svm = to_svm(vcpu); |
477 | ||
6bc31bdc AP |
478 | if (svm->vmcb->control.next_rip != 0) |
479 | svm->next_rip = svm->vmcb->control.next_rip; | |
480 | ||
a2fa3e9f | 481 | if (!svm->next_rip) { |
51d8b661 | 482 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
483 | EMULATE_DONE) |
484 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
485 | return; |
486 | } | |
5fdbf976 MT |
487 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
488 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
489 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 490 | |
5fdbf976 | 491 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 492 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
493 | } |
494 | ||
116a4752 | 495 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
496 | bool has_error_code, u32 error_code, |
497 | bool reinject) | |
116a4752 JK |
498 | { |
499 | struct vcpu_svm *svm = to_svm(vcpu); | |
500 | ||
e0231715 JR |
501 | /* |
502 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
503 | * handle the exception | |
504 | */ | |
ce7ddec4 JR |
505 | if (!reinject && |
506 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
507 | return; |
508 | ||
2a6b20b8 | 509 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
510 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
511 | ||
512 | /* | |
513 | * For guest debugging where we have to reinject #BP if some | |
514 | * INT3 is guest-owned: | |
515 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
516 | * raises a fault that is not intercepted. Still better than | |
517 | * failing in all cases. | |
518 | */ | |
519 | skip_emulated_instruction(&svm->vcpu); | |
520 | rip = kvm_rip_read(&svm->vcpu); | |
521 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
522 | svm->int3_injected = rip - old_rip; | |
523 | } | |
524 | ||
116a4752 JK |
525 | svm->vmcb->control.event_inj = nr |
526 | | SVM_EVTINJ_VALID | |
527 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
528 | | SVM_EVTINJ_TYPE_EXEPT; | |
529 | svm->vmcb->control.event_inj_err = error_code; | |
530 | } | |
531 | ||
67ec6607 JR |
532 | static void svm_init_erratum_383(void) |
533 | { | |
534 | u32 low, high; | |
535 | int err; | |
536 | u64 val; | |
537 | ||
1be85a6d | 538 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
539 | return; |
540 | ||
541 | /* Use _safe variants to not break nested virtualization */ | |
542 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
543 | if (err) | |
544 | return; | |
545 | ||
546 | val |= (1ULL << 47); | |
547 | ||
548 | low = lower_32_bits(val); | |
549 | high = upper_32_bits(val); | |
550 | ||
551 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
552 | ||
553 | erratum_383_found = true; | |
554 | } | |
555 | ||
6aa8b732 AK |
556 | static int has_svm(void) |
557 | { | |
63d1142f | 558 | const char *msg; |
6aa8b732 | 559 | |
63d1142f | 560 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 561 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
562 | return 0; |
563 | } | |
564 | ||
6aa8b732 AK |
565 | return 1; |
566 | } | |
567 | ||
568 | static void svm_hardware_disable(void *garbage) | |
569 | { | |
fbc0db76 JR |
570 | /* Make sure we clean up behind us */ |
571 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
572 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
573 | ||
2c8dceeb | 574 | cpu_svm_disable(); |
6aa8b732 AK |
575 | } |
576 | ||
10474ae8 | 577 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
578 | { |
579 | ||
0fe1e009 | 580 | struct svm_cpu_data *sd; |
6aa8b732 | 581 | uint64_t efer; |
89a27f4d | 582 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
583 | struct desc_struct *gdt; |
584 | int me = raw_smp_processor_id(); | |
585 | ||
10474ae8 AG |
586 | rdmsrl(MSR_EFER, efer); |
587 | if (efer & EFER_SVME) | |
588 | return -EBUSY; | |
589 | ||
6aa8b732 | 590 | if (!has_svm()) { |
e6732a5a ZA |
591 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
592 | me); | |
10474ae8 | 593 | return -EINVAL; |
6aa8b732 | 594 | } |
0fe1e009 | 595 | sd = per_cpu(svm_data, me); |
6aa8b732 | 596 | |
0fe1e009 | 597 | if (!sd) { |
e6732a5a | 598 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 599 | me); |
10474ae8 | 600 | return -EINVAL; |
6aa8b732 AK |
601 | } |
602 | ||
0fe1e009 TH |
603 | sd->asid_generation = 1; |
604 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
605 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 606 | |
d6ab1ed4 | 607 | native_store_gdt(&gdt_descr); |
89a27f4d | 608 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 609 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 610 | |
9962d032 | 611 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 612 | |
d0316554 | 613 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 614 | |
fbc0db76 JR |
615 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
616 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
617 | __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT; | |
618 | } | |
619 | ||
67ec6607 JR |
620 | svm_init_erratum_383(); |
621 | ||
10474ae8 | 622 | return 0; |
6aa8b732 AK |
623 | } |
624 | ||
0da1db75 JR |
625 | static void svm_cpu_uninit(int cpu) |
626 | { | |
0fe1e009 | 627 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 628 | |
0fe1e009 | 629 | if (!sd) |
0da1db75 JR |
630 | return; |
631 | ||
632 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
633 | __free_page(sd->save_area); |
634 | kfree(sd); | |
0da1db75 JR |
635 | } |
636 | ||
6aa8b732 AK |
637 | static int svm_cpu_init(int cpu) |
638 | { | |
0fe1e009 | 639 | struct svm_cpu_data *sd; |
6aa8b732 AK |
640 | int r; |
641 | ||
0fe1e009 TH |
642 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
643 | if (!sd) | |
6aa8b732 | 644 | return -ENOMEM; |
0fe1e009 TH |
645 | sd->cpu = cpu; |
646 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 647 | r = -ENOMEM; |
0fe1e009 | 648 | if (!sd->save_area) |
6aa8b732 AK |
649 | goto err_1; |
650 | ||
0fe1e009 | 651 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
652 | |
653 | return 0; | |
654 | ||
655 | err_1: | |
0fe1e009 | 656 | kfree(sd); |
6aa8b732 AK |
657 | return r; |
658 | ||
659 | } | |
660 | ||
ac72a9b7 JR |
661 | static bool valid_msr_intercept(u32 index) |
662 | { | |
663 | int i; | |
664 | ||
665 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
666 | if (direct_access_msrs[i].index == index) | |
667 | return true; | |
668 | ||
669 | return false; | |
670 | } | |
671 | ||
bfc733a7 RR |
672 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
673 | int read, int write) | |
6aa8b732 | 674 | { |
455716fa JR |
675 | u8 bit_read, bit_write; |
676 | unsigned long tmp; | |
677 | u32 offset; | |
6aa8b732 | 678 | |
ac72a9b7 JR |
679 | /* |
680 | * If this warning triggers extend the direct_access_msrs list at the | |
681 | * beginning of the file | |
682 | */ | |
683 | WARN_ON(!valid_msr_intercept(msr)); | |
684 | ||
455716fa JR |
685 | offset = svm_msrpm_offset(msr); |
686 | bit_read = 2 * (msr & 0x0f); | |
687 | bit_write = 2 * (msr & 0x0f) + 1; | |
688 | tmp = msrpm[offset]; | |
689 | ||
690 | BUG_ON(offset == MSR_INVALID); | |
691 | ||
692 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
693 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
694 | ||
695 | msrpm[offset] = tmp; | |
6aa8b732 AK |
696 | } |
697 | ||
f65c229c | 698 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
699 | { |
700 | int i; | |
701 | ||
f65c229c JR |
702 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
703 | ||
ac72a9b7 JR |
704 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
705 | if (!direct_access_msrs[i].always) | |
706 | continue; | |
707 | ||
708 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
709 | } | |
f65c229c JR |
710 | } |
711 | ||
323c3d80 JR |
712 | static void add_msr_offset(u32 offset) |
713 | { | |
714 | int i; | |
715 | ||
716 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
717 | ||
718 | /* Offset already in list? */ | |
719 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 720 | return; |
323c3d80 JR |
721 | |
722 | /* Slot used by another offset? */ | |
723 | if (msrpm_offsets[i] != MSR_INVALID) | |
724 | continue; | |
725 | ||
726 | /* Add offset to list */ | |
727 | msrpm_offsets[i] = offset; | |
728 | ||
729 | return; | |
6aa8b732 | 730 | } |
323c3d80 JR |
731 | |
732 | /* | |
733 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
734 | * increase MSRPM_OFFSETS in this case. | |
735 | */ | |
bfc733a7 | 736 | BUG(); |
6aa8b732 AK |
737 | } |
738 | ||
323c3d80 | 739 | static void init_msrpm_offsets(void) |
f65c229c | 740 | { |
323c3d80 | 741 | int i; |
f65c229c | 742 | |
323c3d80 JR |
743 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
744 | ||
745 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
746 | u32 offset; | |
747 | ||
748 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
749 | BUG_ON(offset == MSR_INVALID); | |
750 | ||
751 | add_msr_offset(offset); | |
752 | } | |
f65c229c JR |
753 | } |
754 | ||
24e09cbf JR |
755 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
756 | { | |
757 | u32 *msrpm = svm->msrpm; | |
758 | ||
759 | svm->vmcb->control.lbr_ctl = 1; | |
760 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
761 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
762 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
763 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
764 | } | |
765 | ||
766 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
767 | { | |
768 | u32 *msrpm = svm->msrpm; | |
769 | ||
770 | svm->vmcb->control.lbr_ctl = 0; | |
771 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
772 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
773 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
774 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
775 | } | |
776 | ||
6aa8b732 AK |
777 | static __init int svm_hardware_setup(void) |
778 | { | |
779 | int cpu; | |
780 | struct page *iopm_pages; | |
f65c229c | 781 | void *iopm_va; |
6aa8b732 AK |
782 | int r; |
783 | ||
6aa8b732 AK |
784 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
785 | ||
786 | if (!iopm_pages) | |
787 | return -ENOMEM; | |
c8681339 AL |
788 | |
789 | iopm_va = page_address(iopm_pages); | |
790 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
791 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
792 | ||
323c3d80 JR |
793 | init_msrpm_offsets(); |
794 | ||
50a37eb4 JR |
795 | if (boot_cpu_has(X86_FEATURE_NX)) |
796 | kvm_enable_efer_bits(EFER_NX); | |
797 | ||
1b2fd70c AG |
798 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
799 | kvm_enable_efer_bits(EFER_FFXSR); | |
800 | ||
236de055 AG |
801 | if (nested) { |
802 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 803 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
804 | } |
805 | ||
3230bb47 | 806 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
807 | r = svm_cpu_init(cpu); |
808 | if (r) | |
f65c229c | 809 | goto err; |
6aa8b732 | 810 | } |
33bd6a0b | 811 | |
2a6b20b8 | 812 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
813 | npt_enabled = false; |
814 | ||
6c7dac72 JR |
815 | if (npt_enabled && !npt) { |
816 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
817 | npt_enabled = false; | |
818 | } | |
819 | ||
18552672 | 820 | if (npt_enabled) { |
e3da3acd | 821 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 822 | kvm_enable_tdp(); |
5f4cb662 JR |
823 | } else |
824 | kvm_disable_tdp(); | |
e3da3acd | 825 | |
6aa8b732 AK |
826 | return 0; |
827 | ||
f65c229c | 828 | err: |
6aa8b732 AK |
829 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
830 | iopm_base = 0; | |
831 | return r; | |
832 | } | |
833 | ||
834 | static __exit void svm_hardware_unsetup(void) | |
835 | { | |
0da1db75 JR |
836 | int cpu; |
837 | ||
3230bb47 | 838 | for_each_possible_cpu(cpu) |
0da1db75 JR |
839 | svm_cpu_uninit(cpu); |
840 | ||
6aa8b732 | 841 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 842 | iopm_base = 0; |
6aa8b732 AK |
843 | } |
844 | ||
845 | static void init_seg(struct vmcb_seg *seg) | |
846 | { | |
847 | seg->selector = 0; | |
848 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 849 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
850 | seg->limit = 0xffff; |
851 | seg->base = 0; | |
852 | } | |
853 | ||
854 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
855 | { | |
856 | seg->selector = 0; | |
857 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
858 | seg->limit = 0xffff; | |
859 | seg->base = 0; | |
860 | } | |
861 | ||
fbc0db76 JR |
862 | static u64 __scale_tsc(u64 ratio, u64 tsc) |
863 | { | |
864 | u64 mult, frac, _tsc; | |
865 | ||
866 | mult = ratio >> 32; | |
867 | frac = ratio & ((1ULL << 32) - 1); | |
868 | ||
869 | _tsc = tsc; | |
870 | _tsc *= mult; | |
871 | _tsc += (tsc >> 32) * frac; | |
872 | _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32; | |
873 | ||
874 | return _tsc; | |
875 | } | |
876 | ||
877 | static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
878 | { | |
879 | struct vcpu_svm *svm = to_svm(vcpu); | |
880 | u64 _tsc = tsc; | |
881 | ||
882 | if (svm->tsc_ratio != TSC_RATIO_DEFAULT) | |
883 | _tsc = __scale_tsc(svm->tsc_ratio, tsc); | |
884 | ||
885 | return _tsc; | |
886 | } | |
887 | ||
f4e1b3c8 ZA |
888 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
889 | { | |
890 | struct vcpu_svm *svm = to_svm(vcpu); | |
891 | u64 g_tsc_offset = 0; | |
892 | ||
2030753d | 893 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
894 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
895 | svm->nested.hsave->control.tsc_offset; | |
896 | svm->nested.hsave->control.tsc_offset = offset; | |
897 | } | |
898 | ||
899 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
900 | |
901 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
902 | } |
903 | ||
e48672fa ZA |
904 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
905 | { | |
906 | struct vcpu_svm *svm = to_svm(vcpu); | |
907 | ||
908 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 909 | if (is_guest_mode(vcpu)) |
e48672fa | 910 | svm->nested.hsave->control.tsc_offset += adjustment; |
116a0a23 | 911 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
912 | } |
913 | ||
e6101a96 | 914 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 915 | { |
e6101a96 JR |
916 | struct vmcb_control_area *control = &svm->vmcb->control; |
917 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 918 | |
bff78274 | 919 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 920 | svm->vcpu.arch.hflags = 0; |
bff78274 | 921 | |
4ee546b4 RJ |
922 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
923 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
924 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
925 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
926 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
927 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
928 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 929 | |
3aed041a JR |
930 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
931 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
932 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
933 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
934 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
935 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
936 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
937 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
938 | ||
939 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
940 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
941 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
942 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
943 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
944 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
945 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
946 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 947 | |
18c918c5 JR |
948 | set_exception_intercept(svm, PF_VECTOR); |
949 | set_exception_intercept(svm, UD_VECTOR); | |
950 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 951 | |
8a05a1b8 JR |
952 | set_intercept(svm, INTERCEPT_INTR); |
953 | set_intercept(svm, INTERCEPT_NMI); | |
954 | set_intercept(svm, INTERCEPT_SMI); | |
955 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
956 | set_intercept(svm, INTERCEPT_CPUID); | |
957 | set_intercept(svm, INTERCEPT_INVD); | |
958 | set_intercept(svm, INTERCEPT_HLT); | |
959 | set_intercept(svm, INTERCEPT_INVLPG); | |
960 | set_intercept(svm, INTERCEPT_INVLPGA); | |
961 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
962 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
963 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
964 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
965 | set_intercept(svm, INTERCEPT_VMRUN); | |
966 | set_intercept(svm, INTERCEPT_VMMCALL); | |
967 | set_intercept(svm, INTERCEPT_VMLOAD); | |
968 | set_intercept(svm, INTERCEPT_VMSAVE); | |
969 | set_intercept(svm, INTERCEPT_STGI); | |
970 | set_intercept(svm, INTERCEPT_CLGI); | |
971 | set_intercept(svm, INTERCEPT_SKINIT); | |
972 | set_intercept(svm, INTERCEPT_WBINVD); | |
973 | set_intercept(svm, INTERCEPT_MONITOR); | |
974 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 975 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
976 | |
977 | control->iopm_base_pa = iopm_base; | |
f65c229c | 978 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
979 | control->int_ctl = V_INTR_MASKING_MASK; |
980 | ||
981 | init_seg(&save->es); | |
982 | init_seg(&save->ss); | |
983 | init_seg(&save->ds); | |
984 | init_seg(&save->fs); | |
985 | init_seg(&save->gs); | |
986 | ||
987 | save->cs.selector = 0xf000; | |
988 | /* Executable/Readable Code Segment */ | |
989 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
990 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
991 | save->cs.limit = 0xffff; | |
d92899a0 AK |
992 | /* |
993 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
994 | * be consistent with it. | |
995 | * | |
996 | * Replace when we have real mode working for vmx. | |
997 | */ | |
998 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
999 | |
1000 | save->gdtr.limit = 0xffff; | |
1001 | save->idtr.limit = 0xffff; | |
1002 | ||
1003 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1004 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1005 | ||
eaa48512 | 1006 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1007 | save->dr6 = 0xffff0ff0; |
6aa8b732 | 1008 | save->dr7 = 0x400; |
f6e78475 | 1009 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1010 | save->rip = 0x0000fff0; |
5fdbf976 | 1011 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1012 | |
e0231715 JR |
1013 | /* |
1014 | * This is the guest-visible cr0 value. | |
18fa000a | 1015 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 1016 | */ |
678041ad MT |
1017 | svm->vcpu.arch.cr0 = 0; |
1018 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 1019 | |
66aee91a | 1020 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1021 | /* rdx = ?? */ |
709ddebf JR |
1022 | |
1023 | if (npt_enabled) { | |
1024 | /* Setup VMCB for Nested Paging */ | |
1025 | control->nested_ctl = 1; | |
8a05a1b8 JR |
1026 | clr_intercept(svm, INTERCEPT_TASK_SWITCH); |
1027 | clr_intercept(svm, INTERCEPT_INVLPG); | |
18c918c5 | 1028 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1029 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1030 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 1031 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
1032 | save->cr3 = 0; |
1033 | save->cr4 = 0; | |
1034 | } | |
f40f6a45 | 1035 | svm->asid_generation = 0; |
1371d904 | 1036 | |
e6aa9abd | 1037 | svm->nested.vmcb = 0; |
2af9194d JR |
1038 | svm->vcpu.arch.hflags = 0; |
1039 | ||
2a6b20b8 | 1040 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1041 | control->pause_filter_count = 3000; |
8a05a1b8 | 1042 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1043 | } |
1044 | ||
8d28fec4 RJ |
1045 | mark_all_dirty(svm->vmcb); |
1046 | ||
2af9194d | 1047 | enable_gif(svm); |
6aa8b732 AK |
1048 | } |
1049 | ||
e00c8cf2 | 1050 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1051 | { |
1052 | struct vcpu_svm *svm = to_svm(vcpu); | |
1053 | ||
e6101a96 | 1054 | init_vmcb(svm); |
70433389 | 1055 | |
c5af89b6 | 1056 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 1057 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
1058 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
1059 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 1060 | } |
5fdbf976 MT |
1061 | vcpu->arch.regs_avail = ~0; |
1062 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
1063 | |
1064 | return 0; | |
04d2cc77 AK |
1065 | } |
1066 | ||
fb3f0f51 | 1067 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1068 | { |
a2fa3e9f | 1069 | struct vcpu_svm *svm; |
6aa8b732 | 1070 | struct page *page; |
f65c229c | 1071 | struct page *msrpm_pages; |
b286d5d8 | 1072 | struct page *hsave_page; |
3d6368ef | 1073 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1074 | int err; |
6aa8b732 | 1075 | |
c16f862d | 1076 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1077 | if (!svm) { |
1078 | err = -ENOMEM; | |
1079 | goto out; | |
1080 | } | |
1081 | ||
fbc0db76 JR |
1082 | svm->tsc_ratio = TSC_RATIO_DEFAULT; |
1083 | ||
fb3f0f51 RR |
1084 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); |
1085 | if (err) | |
1086 | goto free_svm; | |
1087 | ||
b7af4043 | 1088 | err = -ENOMEM; |
6aa8b732 | 1089 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1090 | if (!page) |
fb3f0f51 | 1091 | goto uninit; |
6aa8b732 | 1092 | |
f65c229c JR |
1093 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1094 | if (!msrpm_pages) | |
b7af4043 | 1095 | goto free_page1; |
3d6368ef AG |
1096 | |
1097 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1098 | if (!nested_msrpm_pages) | |
b7af4043 | 1099 | goto free_page2; |
f65c229c | 1100 | |
b286d5d8 AG |
1101 | hsave_page = alloc_page(GFP_KERNEL); |
1102 | if (!hsave_page) | |
b7af4043 TY |
1103 | goto free_page3; |
1104 | ||
e6aa9abd | 1105 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1106 | |
b7af4043 TY |
1107 | svm->msrpm = page_address(msrpm_pages); |
1108 | svm_vcpu_init_msrpm(svm->msrpm); | |
1109 | ||
e6aa9abd | 1110 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1111 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1112 | |
a2fa3e9f GH |
1113 | svm->vmcb = page_address(page); |
1114 | clear_page(svm->vmcb); | |
1115 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1116 | svm->asid_generation = 0; | |
e6101a96 | 1117 | init_vmcb(svm); |
99e3e30a | 1118 | kvm_write_tsc(&svm->vcpu, 0); |
a2fa3e9f | 1119 | |
10ab25cd JK |
1120 | err = fx_init(&svm->vcpu); |
1121 | if (err) | |
1122 | goto free_page4; | |
1123 | ||
ad312c7c | 1124 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1125 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1126 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1127 | |
fb3f0f51 | 1128 | return &svm->vcpu; |
36241b8c | 1129 | |
10ab25cd JK |
1130 | free_page4: |
1131 | __free_page(hsave_page); | |
b7af4043 TY |
1132 | free_page3: |
1133 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1134 | free_page2: | |
1135 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1136 | free_page1: | |
1137 | __free_page(page); | |
fb3f0f51 RR |
1138 | uninit: |
1139 | kvm_vcpu_uninit(&svm->vcpu); | |
1140 | free_svm: | |
a4770347 | 1141 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1142 | out: |
1143 | return ERR_PTR(err); | |
6aa8b732 AK |
1144 | } |
1145 | ||
1146 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1147 | { | |
a2fa3e9f GH |
1148 | struct vcpu_svm *svm = to_svm(vcpu); |
1149 | ||
fb3f0f51 | 1150 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1151 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1152 | __free_page(virt_to_page(svm->nested.hsave)); |
1153 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1154 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1155 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1156 | } |
1157 | ||
15ad7146 | 1158 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1159 | { |
a2fa3e9f | 1160 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1161 | int i; |
0cc5064d | 1162 | |
0cc5064d | 1163 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1164 | svm->asid_generation = 0; |
8d28fec4 | 1165 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1166 | } |
94dfbdb3 | 1167 | |
82ca2d10 AK |
1168 | #ifdef CONFIG_X86_64 |
1169 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1170 | #endif | |
dacccfdd AK |
1171 | savesegment(fs, svm->host.fs); |
1172 | savesegment(gs, svm->host.gs); | |
1173 | svm->host.ldt = kvm_read_ldt(); | |
1174 | ||
94dfbdb3 | 1175 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1176 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 JR |
1177 | |
1178 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR) && | |
1179 | svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) { | |
1180 | __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio; | |
1181 | wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio); | |
1182 | } | |
6aa8b732 AK |
1183 | } |
1184 | ||
1185 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1186 | { | |
a2fa3e9f | 1187 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1188 | int i; |
1189 | ||
e1beb1d3 | 1190 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1191 | kvm_load_ldt(svm->host.ldt); |
1192 | #ifdef CONFIG_X86_64 | |
1193 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1194 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1195 | load_gs_index(svm->host.gs); |
dacccfdd | 1196 | #else |
831ca609 | 1197 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1198 | loadsegment(gs, svm->host.gs); |
831ca609 | 1199 | #endif |
dacccfdd | 1200 | #endif |
94dfbdb3 | 1201 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1202 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1203 | } |
1204 | ||
6aa8b732 AK |
1205 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1206 | { | |
a2fa3e9f | 1207 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1208 | } |
1209 | ||
1210 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1211 | { | |
a2fa3e9f | 1212 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1213 | } |
1214 | ||
6de4f3ad AK |
1215 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1216 | { | |
1217 | switch (reg) { | |
1218 | case VCPU_EXREG_PDPTR: | |
1219 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1220 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1221 | break; |
1222 | default: | |
1223 | BUG(); | |
1224 | } | |
1225 | } | |
1226 | ||
f0b85051 AG |
1227 | static void svm_set_vintr(struct vcpu_svm *svm) |
1228 | { | |
8a05a1b8 | 1229 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1230 | } |
1231 | ||
1232 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1233 | { | |
8a05a1b8 | 1234 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1235 | } |
1236 | ||
6aa8b732 AK |
1237 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1238 | { | |
a2fa3e9f | 1239 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1240 | |
1241 | switch (seg) { | |
1242 | case VCPU_SREG_CS: return &save->cs; | |
1243 | case VCPU_SREG_DS: return &save->ds; | |
1244 | case VCPU_SREG_ES: return &save->es; | |
1245 | case VCPU_SREG_FS: return &save->fs; | |
1246 | case VCPU_SREG_GS: return &save->gs; | |
1247 | case VCPU_SREG_SS: return &save->ss; | |
1248 | case VCPU_SREG_TR: return &save->tr; | |
1249 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1250 | } | |
1251 | BUG(); | |
8b6d44c7 | 1252 | return NULL; |
6aa8b732 AK |
1253 | } |
1254 | ||
1255 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1256 | { | |
1257 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1258 | ||
1259 | return s->base; | |
1260 | } | |
1261 | ||
1262 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1263 | struct kvm_segment *var, int seg) | |
1264 | { | |
1265 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1266 | ||
1267 | var->base = s->base; | |
1268 | var->limit = s->limit; | |
1269 | var->selector = s->selector; | |
1270 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1271 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1272 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1273 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1274 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1275 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1276 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1277 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1278 | |
e0231715 JR |
1279 | /* |
1280 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1281 | * for cross vendor migration purposes by "not present" |
1282 | */ | |
1283 | var->unusable = !var->present || (var->type == 0); | |
1284 | ||
1fbdc7a5 AP |
1285 | switch (seg) { |
1286 | case VCPU_SREG_CS: | |
1287 | /* | |
1288 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1289 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1290 | * Intel's VMENTRY has a check on the 'G' bit. | |
1291 | */ | |
25022acc | 1292 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1293 | break; |
1294 | case VCPU_SREG_TR: | |
1295 | /* | |
1296 | * Work around a bug where the busy flag in the tr selector | |
1297 | * isn't exposed | |
1298 | */ | |
c0d09828 | 1299 | var->type |= 0x2; |
1fbdc7a5 AP |
1300 | break; |
1301 | case VCPU_SREG_DS: | |
1302 | case VCPU_SREG_ES: | |
1303 | case VCPU_SREG_FS: | |
1304 | case VCPU_SREG_GS: | |
1305 | /* | |
1306 | * The accessed bit must always be set in the segment | |
1307 | * descriptor cache, although it can be cleared in the | |
1308 | * descriptor, the cached bit always remains at 1. Since | |
1309 | * Intel has a check on this, set it here to support | |
1310 | * cross-vendor migration. | |
1311 | */ | |
1312 | if (!var->unusable) | |
1313 | var->type |= 0x1; | |
1314 | break; | |
b586eb02 | 1315 | case VCPU_SREG_SS: |
e0231715 JR |
1316 | /* |
1317 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1318 | * descriptor is left as 1, although the whole segment has |
1319 | * been made unusable. Clear it here to pass an Intel VMX | |
1320 | * entry check when cross vendor migrating. | |
1321 | */ | |
1322 | if (var->unusable) | |
1323 | var->db = 0; | |
1324 | break; | |
1fbdc7a5 | 1325 | } |
6aa8b732 AK |
1326 | } |
1327 | ||
2e4d2653 IE |
1328 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1329 | { | |
1330 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1331 | ||
1332 | return save->cpl; | |
1333 | } | |
1334 | ||
89a27f4d | 1335 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1336 | { |
a2fa3e9f GH |
1337 | struct vcpu_svm *svm = to_svm(vcpu); |
1338 | ||
89a27f4d GN |
1339 | dt->size = svm->vmcb->save.idtr.limit; |
1340 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1341 | } |
1342 | ||
89a27f4d | 1343 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1344 | { |
a2fa3e9f GH |
1345 | struct vcpu_svm *svm = to_svm(vcpu); |
1346 | ||
89a27f4d GN |
1347 | svm->vmcb->save.idtr.limit = dt->size; |
1348 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1349 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1350 | } |
1351 | ||
89a27f4d | 1352 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1353 | { |
a2fa3e9f GH |
1354 | struct vcpu_svm *svm = to_svm(vcpu); |
1355 | ||
89a27f4d GN |
1356 | dt->size = svm->vmcb->save.gdtr.limit; |
1357 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1358 | } |
1359 | ||
89a27f4d | 1360 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1361 | { |
a2fa3e9f GH |
1362 | struct vcpu_svm *svm = to_svm(vcpu); |
1363 | ||
89a27f4d GN |
1364 | svm->vmcb->save.gdtr.limit = dt->size; |
1365 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1366 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1367 | } |
1368 | ||
e8467fda AK |
1369 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1370 | { | |
1371 | } | |
1372 | ||
aff48baa AK |
1373 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1374 | { | |
1375 | } | |
1376 | ||
25c4c276 | 1377 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1378 | { |
1379 | } | |
1380 | ||
d225157b AK |
1381 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1382 | { | |
1383 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1384 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1385 | ||
1386 | if (!svm->vcpu.fpu_active) | |
1387 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1388 | else | |
1389 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1390 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1391 | ||
dcca1a65 | 1392 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1393 | |
1394 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1395 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1396 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1397 | } else { |
4ee546b4 RJ |
1398 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1399 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1400 | } |
1401 | } | |
1402 | ||
6aa8b732 AK |
1403 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1404 | { | |
a2fa3e9f GH |
1405 | struct vcpu_svm *svm = to_svm(vcpu); |
1406 | ||
05b3e0c2 | 1407 | #ifdef CONFIG_X86_64 |
f6801dff | 1408 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1409 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1410 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1411 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1412 | } |
1413 | ||
d77c26fc | 1414 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1415 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1416 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1417 | } |
1418 | } | |
1419 | #endif | |
ad312c7c | 1420 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1421 | |
1422 | if (!npt_enabled) | |
1423 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1424 | |
1425 | if (!vcpu->fpu_active) | |
334df50a | 1426 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1427 | /* |
1428 | * re-enable caching here because the QEMU bios | |
1429 | * does not do it - this results in some delay at | |
1430 | * reboot | |
1431 | */ | |
1432 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1433 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1434 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1435 | update_cr0_intercept(svm); |
6aa8b732 AK |
1436 | } |
1437 | ||
1438 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1439 | { | |
6394b649 | 1440 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1441 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1442 | ||
1443 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
f40f6a45 | 1444 | svm_flush_tlb(vcpu); |
6394b649 | 1445 | |
ec077263 JR |
1446 | vcpu->arch.cr4 = cr4; |
1447 | if (!npt_enabled) | |
1448 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1449 | cr4 |= host_cr4_mce; |
ec077263 | 1450 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1451 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
1452 | } |
1453 | ||
1454 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1455 | struct kvm_segment *var, int seg) | |
1456 | { | |
a2fa3e9f | 1457 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1458 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1459 | ||
1460 | s->base = var->base; | |
1461 | s->limit = var->limit; | |
1462 | s->selector = var->selector; | |
1463 | if (var->unusable) | |
1464 | s->attrib = 0; | |
1465 | else { | |
1466 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1467 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1468 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1469 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1470 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1471 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1472 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1473 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1474 | } | |
1475 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1476 | svm->vmcb->save.cpl |
1477 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1478 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1479 | ||
060d0c9a | 1480 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1481 | } |
1482 | ||
44c11430 | 1483 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1484 | { |
d0bfb940 JK |
1485 | struct vcpu_svm *svm = to_svm(vcpu); |
1486 | ||
18c918c5 JR |
1487 | clr_exception_intercept(svm, DB_VECTOR); |
1488 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1489 | |
6be7d306 | 1490 | if (svm->nmi_singlestep) |
18c918c5 | 1491 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1492 | |
d0bfb940 JK |
1493 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1494 | if (vcpu->guest_debug & | |
1495 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1496 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1497 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1498 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1499 | } else |
1500 | vcpu->guest_debug = 0; | |
44c11430 GN |
1501 | } |
1502 | ||
355be0b9 | 1503 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1504 | { |
44c11430 GN |
1505 | struct vcpu_svm *svm = to_svm(vcpu); |
1506 | ||
ae675ef0 JK |
1507 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1508 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1509 | else | |
1510 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1511 | ||
72214b96 JR |
1512 | mark_dirty(svm->vmcb, VMCB_DR); |
1513 | ||
355be0b9 | 1514 | update_db_intercept(vcpu); |
6aa8b732 AK |
1515 | } |
1516 | ||
0fe1e009 | 1517 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1518 | { |
0fe1e009 TH |
1519 | if (sd->next_asid > sd->max_asid) { |
1520 | ++sd->asid_generation; | |
1521 | sd->next_asid = 1; | |
a2fa3e9f | 1522 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1523 | } |
1524 | ||
0fe1e009 TH |
1525 | svm->asid_generation = sd->asid_generation; |
1526 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1527 | |
1528 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1529 | } |
1530 | ||
020df079 | 1531 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1532 | { |
42dbaa5a | 1533 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1534 | |
020df079 | 1535 | svm->vmcb->save.dr7 = value; |
72214b96 | 1536 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1537 | } |
1538 | ||
851ba692 | 1539 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1540 | { |
631bc487 | 1541 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1542 | u32 error_code; |
631bc487 | 1543 | int r = 1; |
6aa8b732 | 1544 | |
631bc487 GN |
1545 | switch (svm->apf_reason) { |
1546 | default: | |
1547 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1548 | |
631bc487 GN |
1549 | trace_kvm_page_fault(fault_address, error_code); |
1550 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1551 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1552 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1553 | svm->vmcb->control.insn_bytes, | |
1554 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1555 | break; |
1556 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1557 | svm->apf_reason = 0; | |
1558 | local_irq_disable(); | |
1559 | kvm_async_pf_task_wait(fault_address); | |
1560 | local_irq_enable(); | |
1561 | break; | |
1562 | case KVM_PV_REASON_PAGE_READY: | |
1563 | svm->apf_reason = 0; | |
1564 | local_irq_disable(); | |
1565 | kvm_async_pf_task_wake(fault_address); | |
1566 | local_irq_enable(); | |
1567 | break; | |
1568 | } | |
1569 | return r; | |
6aa8b732 AK |
1570 | } |
1571 | ||
851ba692 | 1572 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1573 | { |
851ba692 AK |
1574 | struct kvm_run *kvm_run = svm->vcpu.run; |
1575 | ||
d0bfb940 | 1576 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1577 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1578 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1579 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1580 | return 1; | |
1581 | } | |
44c11430 | 1582 | |
6be7d306 JK |
1583 | if (svm->nmi_singlestep) { |
1584 | svm->nmi_singlestep = false; | |
44c11430 GN |
1585 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1586 | svm->vmcb->save.rflags &= | |
1587 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1588 | update_db_intercept(&svm->vcpu); | |
1589 | } | |
1590 | ||
1591 | if (svm->vcpu.guest_debug & | |
e0231715 | 1592 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1593 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1594 | kvm_run->debug.arch.pc = | |
1595 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1596 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | return 1; | |
d0bfb940 JK |
1601 | } |
1602 | ||
851ba692 | 1603 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1604 | { |
851ba692 AK |
1605 | struct kvm_run *kvm_run = svm->vcpu.run; |
1606 | ||
d0bfb940 JK |
1607 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1608 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1609 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1610 | return 0; | |
1611 | } | |
1612 | ||
851ba692 | 1613 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1614 | { |
1615 | int er; | |
1616 | ||
51d8b661 | 1617 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1618 | if (er != EMULATE_DONE) |
7ee5d940 | 1619 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1620 | return 1; |
1621 | } | |
1622 | ||
6b52d186 | 1623 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1624 | { |
6b52d186 | 1625 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1626 | |
18c918c5 | 1627 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1628 | |
e756fc62 | 1629 | svm->vcpu.fpu_active = 1; |
d225157b | 1630 | update_cr0_intercept(svm); |
6b52d186 | 1631 | } |
a2fa3e9f | 1632 | |
6b52d186 AK |
1633 | static int nm_interception(struct vcpu_svm *svm) |
1634 | { | |
1635 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1636 | return 1; |
7807fa6c AL |
1637 | } |
1638 | ||
67ec6607 JR |
1639 | static bool is_erratum_383(void) |
1640 | { | |
1641 | int err, i; | |
1642 | u64 value; | |
1643 | ||
1644 | if (!erratum_383_found) | |
1645 | return false; | |
1646 | ||
1647 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1648 | if (err) | |
1649 | return false; | |
1650 | ||
1651 | /* Bit 62 may or may not be set for this mce */ | |
1652 | value &= ~(1ULL << 62); | |
1653 | ||
1654 | if (value != 0xb600000000010015ULL) | |
1655 | return false; | |
1656 | ||
1657 | /* Clear MCi_STATUS registers */ | |
1658 | for (i = 0; i < 6; ++i) | |
1659 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1660 | ||
1661 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1662 | if (!err) { | |
1663 | u32 low, high; | |
1664 | ||
1665 | value &= ~(1ULL << 2); | |
1666 | low = lower_32_bits(value); | |
1667 | high = upper_32_bits(value); | |
1668 | ||
1669 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1670 | } | |
1671 | ||
1672 | /* Flush tlb to evict multi-match entries */ | |
1673 | __flush_tlb_all(); | |
1674 | ||
1675 | return true; | |
1676 | } | |
1677 | ||
fe5913e4 | 1678 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1679 | { |
67ec6607 JR |
1680 | if (is_erratum_383()) { |
1681 | /* | |
1682 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1683 | * guest. | |
1684 | */ | |
1685 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1686 | ||
a8eeb04a | 1687 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1688 | |
1689 | return; | |
1690 | } | |
1691 | ||
53371b50 JR |
1692 | /* |
1693 | * On an #MC intercept the MCE handler is not called automatically in | |
1694 | * the host. So do it by hand here. | |
1695 | */ | |
1696 | asm volatile ( | |
1697 | "int $0x12\n"); | |
1698 | /* not sure if we ever come back to this point */ | |
1699 | ||
fe5913e4 JR |
1700 | return; |
1701 | } | |
1702 | ||
1703 | static int mc_interception(struct vcpu_svm *svm) | |
1704 | { | |
53371b50 JR |
1705 | return 1; |
1706 | } | |
1707 | ||
851ba692 | 1708 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1709 | { |
851ba692 AK |
1710 | struct kvm_run *kvm_run = svm->vcpu.run; |
1711 | ||
46fe4ddd JR |
1712 | /* |
1713 | * VMCB is undefined after a SHUTDOWN intercept | |
1714 | * so reinitialize it. | |
1715 | */ | |
a2fa3e9f | 1716 | clear_page(svm->vmcb); |
e6101a96 | 1717 | init_vmcb(svm); |
46fe4ddd JR |
1718 | |
1719 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1720 | return 0; | |
1721 | } | |
1722 | ||
851ba692 | 1723 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1724 | { |
cf8f70bf | 1725 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1726 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1727 | int size, in, string; |
039576c0 | 1728 | unsigned port; |
6aa8b732 | 1729 | |
e756fc62 | 1730 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1731 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1732 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1733 | if (string || in) |
51d8b661 | 1734 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1735 | |
039576c0 AK |
1736 | port = io_info >> 16; |
1737 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1738 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1739 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1740 | |
1741 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1742 | } |
1743 | ||
851ba692 | 1744 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1745 | { |
1746 | return 1; | |
1747 | } | |
1748 | ||
851ba692 | 1749 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1750 | { |
1751 | ++svm->vcpu.stat.irq_exits; | |
1752 | return 1; | |
1753 | } | |
1754 | ||
851ba692 | 1755 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1756 | { |
1757 | return 1; | |
1758 | } | |
1759 | ||
851ba692 | 1760 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1761 | { |
5fdbf976 | 1762 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1763 | skip_emulated_instruction(&svm->vcpu); |
1764 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1765 | } |
1766 | ||
851ba692 | 1767 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1768 | { |
5fdbf976 | 1769 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1770 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1771 | kvm_emulate_hypercall(&svm->vcpu); |
1772 | return 1; | |
02e235bc AK |
1773 | } |
1774 | ||
5bd2edc3 JR |
1775 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1776 | { | |
1777 | struct vcpu_svm *svm = to_svm(vcpu); | |
1778 | ||
1779 | return svm->nested.nested_cr3; | |
1780 | } | |
1781 | ||
1782 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, | |
1783 | unsigned long root) | |
1784 | { | |
1785 | struct vcpu_svm *svm = to_svm(vcpu); | |
1786 | ||
1787 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1788 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1789 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1790 | } |
1791 | ||
6389ee94 AK |
1792 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1793 | struct x86_exception *fault) | |
5bd2edc3 JR |
1794 | { |
1795 | struct vcpu_svm *svm = to_svm(vcpu); | |
1796 | ||
1797 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1798 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1799 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1800 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1801 | |
1802 | nested_svm_vmexit(svm); | |
1803 | } | |
1804 | ||
4b16184c JR |
1805 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1806 | { | |
1807 | int r; | |
1808 | ||
1809 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1810 | ||
1811 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1812 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
1813 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; | |
1814 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1815 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1816 | ||
1817 | return r; | |
1818 | } | |
1819 | ||
1820 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1821 | { | |
1822 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1823 | } | |
1824 | ||
c0725420 AG |
1825 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1826 | { | |
f6801dff | 1827 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1828 | || !is_paging(&svm->vcpu)) { |
1829 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1830 | return 1; | |
1831 | } | |
1832 | ||
1833 | if (svm->vmcb->save.cpl) { | |
1834 | kvm_inject_gp(&svm->vcpu, 0); | |
1835 | return 1; | |
1836 | } | |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | ||
cf74a78b AG |
1841 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1842 | bool has_error_code, u32 error_code) | |
1843 | { | |
b8e88bc8 JR |
1844 | int vmexit; |
1845 | ||
2030753d | 1846 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1847 | return 0; |
cf74a78b | 1848 | |
0295ad7d JR |
1849 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1850 | svm->vmcb->control.exit_code_hi = 0; | |
1851 | svm->vmcb->control.exit_info_1 = error_code; | |
1852 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1853 | ||
b8e88bc8 JR |
1854 | vmexit = nested_svm_intercept(svm); |
1855 | if (vmexit == NESTED_EXIT_DONE) | |
1856 | svm->nested.exit_required = true; | |
1857 | ||
1858 | return vmexit; | |
cf74a78b AG |
1859 | } |
1860 | ||
8fe54654 JR |
1861 | /* This function returns true if it is save to enable the irq window */ |
1862 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1863 | { |
2030753d | 1864 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 1865 | return true; |
cf74a78b | 1866 | |
26666957 | 1867 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1868 | return true; |
cf74a78b | 1869 | |
26666957 | 1870 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1871 | return false; |
cf74a78b | 1872 | |
a0a07cd2 GN |
1873 | /* |
1874 | * if vmexit was already requested (by intercepted exception | |
1875 | * for instance) do not overwrite it with "external interrupt" | |
1876 | * vmexit. | |
1877 | */ | |
1878 | if (svm->nested.exit_required) | |
1879 | return false; | |
1880 | ||
197717d5 JR |
1881 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1882 | svm->vmcb->control.exit_info_1 = 0; | |
1883 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1884 | |
cd3ff653 JR |
1885 | if (svm->nested.intercept & 1ULL) { |
1886 | /* | |
1887 | * The #vmexit can't be emulated here directly because this | |
1888 | * code path runs with irqs and preemtion disabled. A | |
1889 | * #vmexit emulation might sleep. Only signal request for | |
1890 | * the #vmexit here. | |
1891 | */ | |
1892 | svm->nested.exit_required = true; | |
236649de | 1893 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 1894 | return false; |
cf74a78b AG |
1895 | } |
1896 | ||
8fe54654 | 1897 | return true; |
cf74a78b AG |
1898 | } |
1899 | ||
887f500c JR |
1900 | /* This function returns true if it is save to enable the nmi window */ |
1901 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1902 | { | |
2030753d | 1903 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
1904 | return true; |
1905 | ||
1906 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1907 | return true; | |
1908 | ||
1909 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1910 | svm->nested.exit_required = true; | |
1911 | ||
1912 | return false; | |
cf74a78b AG |
1913 | } |
1914 | ||
7597f129 | 1915 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1916 | { |
1917 | struct page *page; | |
1918 | ||
6c3bd3d7 JR |
1919 | might_sleep(); |
1920 | ||
34f80cfa | 1921 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1922 | if (is_error_page(page)) |
1923 | goto error; | |
1924 | ||
7597f129 JR |
1925 | *_page = page; |
1926 | ||
1927 | return kmap(page); | |
34f80cfa JR |
1928 | |
1929 | error: | |
1930 | kvm_release_page_clean(page); | |
1931 | kvm_inject_gp(&svm->vcpu, 0); | |
1932 | ||
1933 | return NULL; | |
1934 | } | |
1935 | ||
7597f129 | 1936 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1937 | { |
7597f129 | 1938 | kunmap(page); |
34f80cfa JR |
1939 | kvm_release_page_dirty(page); |
1940 | } | |
34f80cfa | 1941 | |
ce2ac085 JR |
1942 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
1943 | { | |
1944 | unsigned port; | |
1945 | u8 val, bit; | |
1946 | u64 gpa; | |
34f80cfa | 1947 | |
ce2ac085 JR |
1948 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
1949 | return NESTED_EXIT_HOST; | |
34f80cfa | 1950 | |
ce2ac085 JR |
1951 | port = svm->vmcb->control.exit_info_1 >> 16; |
1952 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1953 | bit = port % 8; | |
1954 | val = 0; | |
1955 | ||
1956 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1957 | val &= (1 << bit); | |
1958 | ||
1959 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
1960 | } |
1961 | ||
d2477826 | 1962 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1963 | { |
0d6b3537 JR |
1964 | u32 offset, msr, value; |
1965 | int write, mask; | |
4c2161ae | 1966 | |
3d62d9aa | 1967 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 1968 | return NESTED_EXIT_HOST; |
3d62d9aa | 1969 | |
0d6b3537 JR |
1970 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1971 | offset = svm_msrpm_offset(msr); | |
1972 | write = svm->vmcb->control.exit_info_1 & 1; | |
1973 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 1974 | |
0d6b3537 JR |
1975 | if (offset == MSR_INVALID) |
1976 | return NESTED_EXIT_DONE; | |
4c2161ae | 1977 | |
0d6b3537 JR |
1978 | /* Offset is in 32 bit units but need in 8 bit units */ |
1979 | offset *= 4; | |
4c2161ae | 1980 | |
0d6b3537 JR |
1981 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
1982 | return NESTED_EXIT_DONE; | |
3d62d9aa | 1983 | |
0d6b3537 | 1984 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
1985 | } |
1986 | ||
410e4d57 | 1987 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1988 | { |
cf74a78b | 1989 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1990 | |
410e4d57 JR |
1991 | switch (exit_code) { |
1992 | case SVM_EXIT_INTR: | |
1993 | case SVM_EXIT_NMI: | |
ff47a49b | 1994 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 1995 | return NESTED_EXIT_HOST; |
410e4d57 | 1996 | case SVM_EXIT_NPF: |
e0231715 | 1997 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1998 | if (npt_enabled) |
1999 | return NESTED_EXIT_HOST; | |
2000 | break; | |
410e4d57 | 2001 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2002 | /* When we're shadowing, trap PFs, but not async PF */ |
2003 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2004 | return NESTED_EXIT_HOST; |
2005 | break; | |
66a562f7 JR |
2006 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2007 | nm_interception(svm); | |
2008 | break; | |
410e4d57 JR |
2009 | default: |
2010 | break; | |
cf74a78b AG |
2011 | } |
2012 | ||
410e4d57 JR |
2013 | return NESTED_EXIT_CONTINUE; |
2014 | } | |
2015 | ||
2016 | /* | |
2017 | * If this function returns true, this #vmexit was already handled | |
2018 | */ | |
b8e88bc8 | 2019 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2020 | { |
2021 | u32 exit_code = svm->vmcb->control.exit_code; | |
2022 | int vmexit = NESTED_EXIT_HOST; | |
2023 | ||
cf74a78b | 2024 | switch (exit_code) { |
9c4e40b9 | 2025 | case SVM_EXIT_MSR: |
3d62d9aa | 2026 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2027 | break; |
ce2ac085 JR |
2028 | case SVM_EXIT_IOIO: |
2029 | vmexit = nested_svm_intercept_ioio(svm); | |
2030 | break; | |
4ee546b4 RJ |
2031 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2032 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2033 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2034 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2035 | break; |
2036 | } | |
3aed041a JR |
2037 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2038 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2039 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2040 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2041 | break; |
2042 | } | |
2043 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2044 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2045 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2046 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2047 | /* async page fault always cause vmexit */ |
2048 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2049 | svm->apf_reason != 0) | |
2050 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2051 | break; |
2052 | } | |
228070b1 JR |
2053 | case SVM_EXIT_ERR: { |
2054 | vmexit = NESTED_EXIT_DONE; | |
2055 | break; | |
2056 | } | |
cf74a78b AG |
2057 | default: { |
2058 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2059 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2060 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2061 | } |
2062 | } | |
2063 | ||
b8e88bc8 JR |
2064 | return vmexit; |
2065 | } | |
2066 | ||
2067 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2068 | { | |
2069 | int vmexit; | |
2070 | ||
2071 | vmexit = nested_svm_intercept(svm); | |
2072 | ||
2073 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2074 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2075 | |
2076 | return vmexit; | |
cf74a78b AG |
2077 | } |
2078 | ||
0460a979 JR |
2079 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2080 | { | |
2081 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2082 | struct vmcb_control_area *from = &from_vmcb->control; | |
2083 | ||
4ee546b4 | 2084 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2085 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2086 | dst->intercept_exceptions = from->intercept_exceptions; |
2087 | dst->intercept = from->intercept; | |
2088 | dst->iopm_base_pa = from->iopm_base_pa; | |
2089 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2090 | dst->tsc_offset = from->tsc_offset; | |
2091 | dst->asid = from->asid; | |
2092 | dst->tlb_ctl = from->tlb_ctl; | |
2093 | dst->int_ctl = from->int_ctl; | |
2094 | dst->int_vector = from->int_vector; | |
2095 | dst->int_state = from->int_state; | |
2096 | dst->exit_code = from->exit_code; | |
2097 | dst->exit_code_hi = from->exit_code_hi; | |
2098 | dst->exit_info_1 = from->exit_info_1; | |
2099 | dst->exit_info_2 = from->exit_info_2; | |
2100 | dst->exit_int_info = from->exit_int_info; | |
2101 | dst->exit_int_info_err = from->exit_int_info_err; | |
2102 | dst->nested_ctl = from->nested_ctl; | |
2103 | dst->event_inj = from->event_inj; | |
2104 | dst->event_inj_err = from->event_inj_err; | |
2105 | dst->nested_cr3 = from->nested_cr3; | |
2106 | dst->lbr_ctl = from->lbr_ctl; | |
2107 | } | |
2108 | ||
34f80cfa | 2109 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2110 | { |
34f80cfa | 2111 | struct vmcb *nested_vmcb; |
e6aa9abd | 2112 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2113 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2114 | struct page *page; |
cf74a78b | 2115 | |
17897f36 JR |
2116 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2117 | vmcb->control.exit_info_1, | |
2118 | vmcb->control.exit_info_2, | |
2119 | vmcb->control.exit_int_info, | |
2120 | vmcb->control.exit_int_info_err); | |
2121 | ||
7597f129 | 2122 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2123 | if (!nested_vmcb) |
2124 | return 1; | |
2125 | ||
2030753d JR |
2126 | /* Exit Guest-Mode */ |
2127 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2128 | svm->nested.vmcb = 0; |
2129 | ||
cf74a78b | 2130 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2131 | disable_gif(svm); |
2132 | ||
2133 | nested_vmcb->save.es = vmcb->save.es; | |
2134 | nested_vmcb->save.cs = vmcb->save.cs; | |
2135 | nested_vmcb->save.ss = vmcb->save.ss; | |
2136 | nested_vmcb->save.ds = vmcb->save.ds; | |
2137 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2138 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2139 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2140 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2141 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2142 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2143 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2144 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2145 | nested_vmcb->save.rip = vmcb->save.rip; |
2146 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2147 | nested_vmcb->save.rax = vmcb->save.rax; | |
2148 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2149 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2150 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2151 | ||
2152 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2153 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2154 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2155 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2156 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2157 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2158 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2159 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2160 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2161 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2162 | |
2163 | /* | |
2164 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2165 | * to make sure that we do not lose injected events. So check event_inj | |
2166 | * here and copy it to exit_int_info if it is valid. | |
2167 | * Exit_int_info and event_inj can't be both valid because the case | |
2168 | * below only happens on a VMRUN instruction intercept which has | |
2169 | * no valid exit_int_info set. | |
2170 | */ | |
2171 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2172 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2173 | ||
2174 | nc->exit_int_info = vmcb->control.event_inj; | |
2175 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2176 | } | |
2177 | ||
33740e40 JR |
2178 | nested_vmcb->control.tlb_ctl = 0; |
2179 | nested_vmcb->control.event_inj = 0; | |
2180 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2181 | |
2182 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2183 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2184 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2185 | ||
cf74a78b | 2186 | /* Restore the original control entries */ |
0460a979 | 2187 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2188 | |
219b65dc AG |
2189 | kvm_clear_exception_queue(&svm->vcpu); |
2190 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2191 | |
4b16184c JR |
2192 | svm->nested.nested_cr3 = 0; |
2193 | ||
cf74a78b AG |
2194 | /* Restore selected save entries */ |
2195 | svm->vmcb->save.es = hsave->save.es; | |
2196 | svm->vmcb->save.cs = hsave->save.cs; | |
2197 | svm->vmcb->save.ss = hsave->save.ss; | |
2198 | svm->vmcb->save.ds = hsave->save.ds; | |
2199 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2200 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2201 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2202 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2203 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2204 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2205 | if (npt_enabled) { | |
2206 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2207 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2208 | } else { | |
2390218b | 2209 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2210 | } |
2211 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2212 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2213 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2214 | svm->vmcb->save.dr7 = 0; | |
2215 | svm->vmcb->save.cpl = 0; | |
2216 | svm->vmcb->control.exit_int_info = 0; | |
2217 | ||
8d28fec4 RJ |
2218 | mark_all_dirty(svm->vmcb); |
2219 | ||
7597f129 | 2220 | nested_svm_unmap(page); |
cf74a78b | 2221 | |
4b16184c | 2222 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2223 | kvm_mmu_reset_context(&svm->vcpu); |
2224 | kvm_mmu_load(&svm->vcpu); | |
2225 | ||
2226 | return 0; | |
2227 | } | |
3d6368ef | 2228 | |
9738b2c9 | 2229 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2230 | { |
323c3d80 JR |
2231 | /* |
2232 | * This function merges the msr permission bitmaps of kvm and the | |
2233 | * nested vmcb. It is omptimized in that it only merges the parts where | |
2234 | * the kvm msr permission bitmap may contain zero bits | |
2235 | */ | |
3d6368ef | 2236 | int i; |
9738b2c9 | 2237 | |
323c3d80 JR |
2238 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2239 | return true; | |
9738b2c9 | 2240 | |
323c3d80 JR |
2241 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2242 | u32 value, p; | |
2243 | u64 offset; | |
9738b2c9 | 2244 | |
323c3d80 JR |
2245 | if (msrpm_offsets[i] == 0xffffffff) |
2246 | break; | |
3d6368ef | 2247 | |
0d6b3537 JR |
2248 | p = msrpm_offsets[i]; |
2249 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2250 | |
2251 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2252 | return false; | |
2253 | ||
2254 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2255 | } | |
3d6368ef | 2256 | |
323c3d80 | 2257 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2258 | |
2259 | return true; | |
3d6368ef AG |
2260 | } |
2261 | ||
52c65a30 JR |
2262 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2263 | { | |
2264 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2265 | return false; | |
2266 | ||
dbe77584 JR |
2267 | if (vmcb->control.asid == 0) |
2268 | return false; | |
2269 | ||
4b16184c JR |
2270 | if (vmcb->control.nested_ctl && !npt_enabled) |
2271 | return false; | |
2272 | ||
52c65a30 JR |
2273 | return true; |
2274 | } | |
2275 | ||
9738b2c9 | 2276 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2277 | { |
9738b2c9 | 2278 | struct vmcb *nested_vmcb; |
e6aa9abd | 2279 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2280 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2281 | struct page *page; |
06fc7772 | 2282 | u64 vmcb_gpa; |
3d6368ef | 2283 | |
06fc7772 | 2284 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2285 | |
7597f129 | 2286 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2287 | if (!nested_vmcb) |
2288 | return false; | |
2289 | ||
52c65a30 JR |
2290 | if (!nested_vmcb_checks(nested_vmcb)) { |
2291 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2292 | nested_vmcb->control.exit_code_hi = 0; | |
2293 | nested_vmcb->control.exit_info_1 = 0; | |
2294 | nested_vmcb->control.exit_info_2 = 0; | |
2295 | ||
2296 | nested_svm_unmap(page); | |
2297 | ||
2298 | return false; | |
2299 | } | |
2300 | ||
b75f4eb3 | 2301 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2302 | nested_vmcb->save.rip, |
2303 | nested_vmcb->control.int_ctl, | |
2304 | nested_vmcb->control.event_inj, | |
2305 | nested_vmcb->control.nested_ctl); | |
2306 | ||
4ee546b4 RJ |
2307 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2308 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2309 | nested_vmcb->control.intercept_exceptions, |
2310 | nested_vmcb->control.intercept); | |
2311 | ||
3d6368ef | 2312 | /* Clear internal status */ |
219b65dc AG |
2313 | kvm_clear_exception_queue(&svm->vcpu); |
2314 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2315 | |
e0231715 JR |
2316 | /* |
2317 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2318 | * restore everything when a VMEXIT occurs | |
2319 | */ | |
defbba56 JR |
2320 | hsave->save.es = vmcb->save.es; |
2321 | hsave->save.cs = vmcb->save.cs; | |
2322 | hsave->save.ss = vmcb->save.ss; | |
2323 | hsave->save.ds = vmcb->save.ds; | |
2324 | hsave->save.gdtr = vmcb->save.gdtr; | |
2325 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2326 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2327 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2328 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2329 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2330 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2331 | hsave->save.rsp = vmcb->save.rsp; |
2332 | hsave->save.rax = vmcb->save.rax; | |
2333 | if (npt_enabled) | |
2334 | hsave->save.cr3 = vmcb->save.cr3; | |
2335 | else | |
9f8fe504 | 2336 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2337 | |
0460a979 | 2338 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2339 | |
f6e78475 | 2340 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2341 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2342 | else | |
2343 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2344 | ||
4b16184c JR |
2345 | if (nested_vmcb->control.nested_ctl) { |
2346 | kvm_mmu_unload(&svm->vcpu); | |
2347 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2348 | nested_svm_init_mmu_context(&svm->vcpu); | |
2349 | } | |
2350 | ||
3d6368ef AG |
2351 | /* Load the nested guest state */ |
2352 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2353 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2354 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2355 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2356 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2357 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2358 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2359 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2360 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2361 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2362 | if (npt_enabled) { | |
2363 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2364 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2365 | } else |
2390218b | 2366 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2367 | |
2368 | /* Guest paging mode is active - reset mmu */ | |
2369 | kvm_mmu_reset_context(&svm->vcpu); | |
2370 | ||
defbba56 | 2371 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2372 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2373 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2374 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2375 | |
3d6368ef AG |
2376 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2377 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2378 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2379 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2380 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2381 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2382 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2383 | ||
f7138538 | 2384 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2385 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2386 | |
aad42c64 | 2387 | /* cache intercepts */ |
4ee546b4 | 2388 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2389 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2390 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2391 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2392 | ||
f40f6a45 | 2393 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2394 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2395 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2396 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2397 | else | |
2398 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2399 | ||
88ab24ad JR |
2400 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2401 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2402 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2403 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2404 | } |
2405 | ||
0d945bd9 | 2406 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2407 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2408 | |
88ab24ad | 2409 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2410 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2411 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2412 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2413 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2414 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2415 | ||
7597f129 | 2416 | nested_svm_unmap(page); |
9738b2c9 | 2417 | |
2030753d JR |
2418 | /* Enter Guest-Mode */ |
2419 | enter_guest_mode(&svm->vcpu); | |
2420 | ||
384c6368 JR |
2421 | /* |
2422 | * Merge guest and host intercepts - must be called with vcpu in | |
2423 | * guest-mode to take affect here | |
2424 | */ | |
2425 | recalc_intercepts(svm); | |
2426 | ||
06fc7772 | 2427 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2428 | |
2af9194d | 2429 | enable_gif(svm); |
3d6368ef | 2430 | |
8d28fec4 RJ |
2431 | mark_all_dirty(svm->vmcb); |
2432 | ||
9738b2c9 | 2433 | return true; |
3d6368ef AG |
2434 | } |
2435 | ||
9966bf68 | 2436 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2437 | { |
2438 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2439 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2440 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2441 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2442 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2443 | to_vmcb->save.star = from_vmcb->save.star; | |
2444 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2445 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2446 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2447 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2448 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2449 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2450 | } |
2451 | ||
851ba692 | 2452 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2453 | { |
9966bf68 | 2454 | struct vmcb *nested_vmcb; |
7597f129 | 2455 | struct page *page; |
9966bf68 | 2456 | |
5542675b AG |
2457 | if (nested_svm_check_permissions(svm)) |
2458 | return 1; | |
2459 | ||
2460 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2461 | skip_emulated_instruction(&svm->vcpu); | |
2462 | ||
7597f129 | 2463 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2464 | if (!nested_vmcb) |
2465 | return 1; | |
2466 | ||
2467 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 2468 | nested_svm_unmap(page); |
5542675b AG |
2469 | |
2470 | return 1; | |
2471 | } | |
2472 | ||
851ba692 | 2473 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2474 | { |
9966bf68 | 2475 | struct vmcb *nested_vmcb; |
7597f129 | 2476 | struct page *page; |
9966bf68 | 2477 | |
5542675b AG |
2478 | if (nested_svm_check_permissions(svm)) |
2479 | return 1; | |
2480 | ||
2481 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2482 | skip_emulated_instruction(&svm->vcpu); | |
2483 | ||
7597f129 | 2484 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2485 | if (!nested_vmcb) |
2486 | return 1; | |
2487 | ||
2488 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 2489 | nested_svm_unmap(page); |
5542675b AG |
2490 | |
2491 | return 1; | |
2492 | } | |
2493 | ||
851ba692 | 2494 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2495 | { |
3d6368ef AG |
2496 | if (nested_svm_check_permissions(svm)) |
2497 | return 1; | |
2498 | ||
b75f4eb3 RJ |
2499 | /* Save rip after vmrun instruction */ |
2500 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2501 | |
9738b2c9 | 2502 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2503 | return 1; |
2504 | ||
9738b2c9 | 2505 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2506 | goto failed; |
2507 | ||
2508 | return 1; | |
2509 | ||
2510 | failed: | |
2511 | ||
2512 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2513 | svm->vmcb->control.exit_code_hi = 0; | |
2514 | svm->vmcb->control.exit_info_1 = 0; | |
2515 | svm->vmcb->control.exit_info_2 = 0; | |
2516 | ||
2517 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2518 | |
2519 | return 1; | |
2520 | } | |
2521 | ||
851ba692 | 2522 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2523 | { |
2524 | if (nested_svm_check_permissions(svm)) | |
2525 | return 1; | |
2526 | ||
2527 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2528 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2529 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2530 | |
2af9194d | 2531 | enable_gif(svm); |
1371d904 AG |
2532 | |
2533 | return 1; | |
2534 | } | |
2535 | ||
851ba692 | 2536 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2537 | { |
2538 | if (nested_svm_check_permissions(svm)) | |
2539 | return 1; | |
2540 | ||
2541 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2542 | skip_emulated_instruction(&svm->vcpu); | |
2543 | ||
2af9194d | 2544 | disable_gif(svm); |
1371d904 AG |
2545 | |
2546 | /* After a CLGI no interrupts should come */ | |
2547 | svm_clear_vintr(svm); | |
2548 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2549 | ||
decdbf6a JR |
2550 | mark_dirty(svm->vmcb, VMCB_INTR); |
2551 | ||
1371d904 AG |
2552 | return 1; |
2553 | } | |
2554 | ||
851ba692 | 2555 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2556 | { |
2557 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2558 | |
ec1ff790 JR |
2559 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2560 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2561 | ||
ff092385 AG |
2562 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2563 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2564 | ||
2565 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2566 | skip_emulated_instruction(&svm->vcpu); | |
2567 | return 1; | |
2568 | } | |
2569 | ||
532a46b9 JR |
2570 | static int skinit_interception(struct vcpu_svm *svm) |
2571 | { | |
2572 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2573 | ||
2574 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2575 | return 1; | |
2576 | } | |
2577 | ||
81dd35d4 JR |
2578 | static int xsetbv_interception(struct vcpu_svm *svm) |
2579 | { | |
2580 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2581 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2582 | ||
2583 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2584 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2585 | skip_emulated_instruction(&svm->vcpu); | |
2586 | } | |
2587 | ||
2588 | return 1; | |
2589 | } | |
2590 | ||
851ba692 | 2591 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2592 | { |
7ee5d940 | 2593 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2594 | return 1; |
2595 | } | |
2596 | ||
851ba692 | 2597 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2598 | { |
37817f29 | 2599 | u16 tss_selector; |
64a7ec06 GN |
2600 | int reason; |
2601 | int int_type = svm->vmcb->control.exit_int_info & | |
2602 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2603 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2604 | uint32_t type = |
2605 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2606 | uint32_t idt_v = | |
2607 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2608 | bool has_error_code = false; |
2609 | u32 error_code = 0; | |
37817f29 IE |
2610 | |
2611 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2612 | |
37817f29 IE |
2613 | if (svm->vmcb->control.exit_info_2 & |
2614 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2615 | reason = TASK_SWITCH_IRET; |
2616 | else if (svm->vmcb->control.exit_info_2 & | |
2617 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2618 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2619 | else if (idt_v) |
64a7ec06 GN |
2620 | reason = TASK_SWITCH_GATE; |
2621 | else | |
2622 | reason = TASK_SWITCH_CALL; | |
2623 | ||
fe8e7f83 GN |
2624 | if (reason == TASK_SWITCH_GATE) { |
2625 | switch (type) { | |
2626 | case SVM_EXITINTINFO_TYPE_NMI: | |
2627 | svm->vcpu.arch.nmi_injected = false; | |
2628 | break; | |
2629 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2630 | if (svm->vmcb->control.exit_info_2 & |
2631 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2632 | has_error_code = true; | |
2633 | error_code = | |
2634 | (u32)svm->vmcb->control.exit_info_2; | |
2635 | } | |
fe8e7f83 GN |
2636 | kvm_clear_exception_queue(&svm->vcpu); |
2637 | break; | |
2638 | case SVM_EXITINTINFO_TYPE_INTR: | |
2639 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2640 | break; | |
2641 | default: | |
2642 | break; | |
2643 | } | |
2644 | } | |
64a7ec06 | 2645 | |
8317c298 GN |
2646 | if (reason != TASK_SWITCH_GATE || |
2647 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2648 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2649 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2650 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2651 | |
acb54517 GN |
2652 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2653 | has_error_code, error_code) == EMULATE_FAIL) { | |
2654 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2655 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2656 | svm->vcpu.run->internal.ndata = 0; | |
2657 | return 0; | |
2658 | } | |
2659 | return 1; | |
6aa8b732 AK |
2660 | } |
2661 | ||
851ba692 | 2662 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2663 | { |
5fdbf976 | 2664 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2665 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2666 | return 1; |
6aa8b732 AK |
2667 | } |
2668 | ||
851ba692 | 2669 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2670 | { |
2671 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2672 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2673 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2674 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
95ba8273 GN |
2675 | return 1; |
2676 | } | |
2677 | ||
851ba692 | 2678 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2679 | { |
df4f3108 AP |
2680 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2681 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2682 | ||
2683 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2684 | skip_emulated_instruction(&svm->vcpu); | |
2685 | return 1; | |
a7052897 MT |
2686 | } |
2687 | ||
851ba692 | 2688 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2689 | { |
51d8b661 | 2690 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2691 | } |
2692 | ||
628afd2a JR |
2693 | bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val) |
2694 | { | |
2695 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
2696 | bool ret = false; | |
2697 | u64 intercept; | |
2698 | ||
2699 | intercept = svm->nested.intercept; | |
2700 | ||
2701 | if (!is_guest_mode(&svm->vcpu) || | |
2702 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
2703 | return false; | |
2704 | ||
2705 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
2706 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
2707 | ||
2708 | if (cr0 ^ val) { | |
2709 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
2710 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
2711 | } | |
2712 | ||
2713 | return ret; | |
2714 | } | |
2715 | ||
7ff76d58 AP |
2716 | #define CR_VALID (1ULL << 63) |
2717 | ||
2718 | static int cr_interception(struct vcpu_svm *svm) | |
2719 | { | |
2720 | int reg, cr; | |
2721 | unsigned long val; | |
2722 | int err; | |
2723 | ||
2724 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2725 | return emulate_on_interception(svm); | |
2726 | ||
2727 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2728 | return emulate_on_interception(svm); | |
2729 | ||
2730 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2731 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2732 | ||
2733 | err = 0; | |
2734 | if (cr >= 16) { /* mov to cr */ | |
2735 | cr -= 16; | |
2736 | val = kvm_register_read(&svm->vcpu, reg); | |
2737 | switch (cr) { | |
2738 | case 0: | |
628afd2a JR |
2739 | if (!check_selective_cr0_intercepted(svm, val)) |
2740 | err = kvm_set_cr0(&svm->vcpu, val); | |
7ff76d58 AP |
2741 | break; |
2742 | case 3: | |
2743 | err = kvm_set_cr3(&svm->vcpu, val); | |
2744 | break; | |
2745 | case 4: | |
2746 | err = kvm_set_cr4(&svm->vcpu, val); | |
2747 | break; | |
2748 | case 8: | |
2749 | err = kvm_set_cr8(&svm->vcpu, val); | |
2750 | break; | |
2751 | default: | |
2752 | WARN(1, "unhandled write to CR%d", cr); | |
2753 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2754 | return 1; | |
2755 | } | |
2756 | } else { /* mov from cr */ | |
2757 | switch (cr) { | |
2758 | case 0: | |
2759 | val = kvm_read_cr0(&svm->vcpu); | |
2760 | break; | |
2761 | case 2: | |
2762 | val = svm->vcpu.arch.cr2; | |
2763 | break; | |
2764 | case 3: | |
9f8fe504 | 2765 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2766 | break; |
2767 | case 4: | |
2768 | val = kvm_read_cr4(&svm->vcpu); | |
2769 | break; | |
2770 | case 8: | |
2771 | val = kvm_get_cr8(&svm->vcpu); | |
2772 | break; | |
2773 | default: | |
2774 | WARN(1, "unhandled read from CR%d", cr); | |
2775 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2776 | return 1; | |
2777 | } | |
2778 | kvm_register_write(&svm->vcpu, reg, val); | |
2779 | } | |
2780 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2781 | ||
2782 | return 1; | |
2783 | } | |
2784 | ||
cae3797a AP |
2785 | static int dr_interception(struct vcpu_svm *svm) |
2786 | { | |
2787 | int reg, dr; | |
2788 | unsigned long val; | |
2789 | int err; | |
2790 | ||
2791 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2792 | return emulate_on_interception(svm); | |
2793 | ||
2794 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2795 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2796 | ||
2797 | if (dr >= 16) { /* mov to DRn */ | |
2798 | val = kvm_register_read(&svm->vcpu, reg); | |
2799 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2800 | } else { | |
2801 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
2802 | if (!err) | |
2803 | kvm_register_write(&svm->vcpu, reg, val); | |
2804 | } | |
2805 | ||
2c46d2ae JR |
2806 | skip_emulated_instruction(&svm->vcpu); |
2807 | ||
cae3797a AP |
2808 | return 1; |
2809 | } | |
2810 | ||
851ba692 | 2811 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2812 | { |
851ba692 | 2813 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2814 | int r; |
851ba692 | 2815 | |
0a5fff19 GN |
2816 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2817 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2818 | r = cr_interception(svm); |
95ba8273 | 2819 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2820 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
7ff76d58 | 2821 | return r; |
95ba8273 | 2822 | } |
0a5fff19 | 2823 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 2824 | return r; |
1d075434 JR |
2825 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2826 | return 0; | |
2827 | } | |
2828 | ||
6aa8b732 AK |
2829 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2830 | { | |
a2fa3e9f GH |
2831 | struct vcpu_svm *svm = to_svm(vcpu); |
2832 | ||
6aa8b732 | 2833 | switch (ecx) { |
af24a4e4 | 2834 | case MSR_IA32_TSC: { |
4cc70310 | 2835 | struct vmcb *vmcb = get_host_vmcb(svm); |
6aa8b732 | 2836 | |
fbc0db76 JR |
2837 | *data = vmcb->control.tsc_offset + |
2838 | svm_scale_tsc(vcpu, native_read_tsc()); | |
2839 | ||
6aa8b732 AK |
2840 | break; |
2841 | } | |
8c06585d | 2842 | case MSR_STAR: |
a2fa3e9f | 2843 | *data = svm->vmcb->save.star; |
6aa8b732 | 2844 | break; |
0e859cac | 2845 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2846 | case MSR_LSTAR: |
a2fa3e9f | 2847 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2848 | break; |
2849 | case MSR_CSTAR: | |
a2fa3e9f | 2850 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2851 | break; |
2852 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2853 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2854 | break; |
2855 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2856 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2857 | break; |
2858 | #endif | |
2859 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2860 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2861 | break; |
2862 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2863 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2864 | break; |
2865 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2866 | *data = svm->sysenter_esp; |
6aa8b732 | 2867 | break; |
e0231715 JR |
2868 | /* |
2869 | * Nobody will change the following 5 values in the VMCB so we can | |
2870 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2871 | * implemented. | |
2872 | */ | |
a2938c80 JR |
2873 | case MSR_IA32_DEBUGCTLMSR: |
2874 | *data = svm->vmcb->save.dbgctl; | |
2875 | break; | |
2876 | case MSR_IA32_LASTBRANCHFROMIP: | |
2877 | *data = svm->vmcb->save.br_from; | |
2878 | break; | |
2879 | case MSR_IA32_LASTBRANCHTOIP: | |
2880 | *data = svm->vmcb->save.br_to; | |
2881 | break; | |
2882 | case MSR_IA32_LASTINTFROMIP: | |
2883 | *data = svm->vmcb->save.last_excp_from; | |
2884 | break; | |
2885 | case MSR_IA32_LASTINTTOIP: | |
2886 | *data = svm->vmcb->save.last_excp_to; | |
2887 | break; | |
b286d5d8 | 2888 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2889 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2890 | break; |
eb6f302e | 2891 | case MSR_VM_CR: |
4a810181 | 2892 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 2893 | break; |
c8a73f18 AG |
2894 | case MSR_IA32_UCODE_REV: |
2895 | *data = 0x01000065; | |
2896 | break; | |
6aa8b732 | 2897 | default: |
3bab1f5d | 2898 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2899 | } |
2900 | return 0; | |
2901 | } | |
2902 | ||
851ba692 | 2903 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2904 | { |
ad312c7c | 2905 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2906 | u64 data; |
2907 | ||
59200273 AK |
2908 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2909 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2910 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2911 | } else { |
229456fc | 2912 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2913 | |
5fdbf976 | 2914 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2915 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2916 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2917 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2918 | } |
2919 | return 1; | |
2920 | } | |
2921 | ||
4a810181 JR |
2922 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
2923 | { | |
2924 | struct vcpu_svm *svm = to_svm(vcpu); | |
2925 | int svm_dis, chg_mask; | |
2926 | ||
2927 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2928 | return 1; | |
2929 | ||
2930 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2931 | ||
2932 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2933 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2934 | ||
2935 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2936 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2937 | ||
2938 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2939 | ||
2940 | /* check for svm_disable while efer.svme is set */ | |
2941 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2942 | return 1; | |
2943 | ||
2944 | return 0; | |
2945 | } | |
2946 | ||
6aa8b732 AK |
2947 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
2948 | { | |
a2fa3e9f GH |
2949 | struct vcpu_svm *svm = to_svm(vcpu); |
2950 | ||
6aa8b732 | 2951 | switch (ecx) { |
f4e1b3c8 | 2952 | case MSR_IA32_TSC: |
99e3e30a | 2953 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 2954 | break; |
8c06585d | 2955 | case MSR_STAR: |
a2fa3e9f | 2956 | svm->vmcb->save.star = data; |
6aa8b732 | 2957 | break; |
49b14f24 | 2958 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2959 | case MSR_LSTAR: |
a2fa3e9f | 2960 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2961 | break; |
2962 | case MSR_CSTAR: | |
a2fa3e9f | 2963 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2964 | break; |
2965 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2966 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2967 | break; |
2968 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2969 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2970 | break; |
2971 | #endif | |
2972 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2973 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2974 | break; |
2975 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2976 | svm->sysenter_eip = data; |
a2fa3e9f | 2977 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2978 | break; |
2979 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2980 | svm->sysenter_esp = data; |
a2fa3e9f | 2981 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2982 | break; |
a2938c80 | 2983 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 2984 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
24e09cbf | 2985 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
b8688d51 | 2986 | __func__, data); |
24e09cbf JR |
2987 | break; |
2988 | } | |
2989 | if (data & DEBUGCTL_RESERVED_BITS) | |
2990 | return 1; | |
2991 | ||
2992 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 2993 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
2994 | if (data & (1ULL<<0)) |
2995 | svm_enable_lbrv(svm); | |
2996 | else | |
2997 | svm_disable_lbrv(svm); | |
a2938c80 | 2998 | break; |
b286d5d8 | 2999 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3000 | svm->nested.hsave_msr = data; |
62b9abaa | 3001 | break; |
3c5d0a44 | 3002 | case MSR_VM_CR: |
4a810181 | 3003 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3004 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
3005 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3006 | break; | |
6aa8b732 | 3007 | default: |
3bab1f5d | 3008 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
3009 | } |
3010 | return 0; | |
3011 | } | |
3012 | ||
851ba692 | 3013 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3014 | { |
ad312c7c | 3015 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 3016 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 3017 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 3018 | |
af9ca2d7 | 3019 | |
5fdbf976 | 3020 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
3021 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
3022 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 3023 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3024 | } else { |
3025 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3026 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3027 | } |
6aa8b732 AK |
3028 | return 1; |
3029 | } | |
3030 | ||
851ba692 | 3031 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3032 | { |
e756fc62 | 3033 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3034 | return wrmsr_interception(svm); |
6aa8b732 | 3035 | else |
851ba692 | 3036 | return rdmsr_interception(svm); |
6aa8b732 AK |
3037 | } |
3038 | ||
851ba692 | 3039 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3040 | { |
851ba692 AK |
3041 | struct kvm_run *kvm_run = svm->vcpu.run; |
3042 | ||
3842d135 | 3043 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3044 | svm_clear_vintr(svm); |
85f455f7 | 3045 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3046 | mark_dirty(svm->vmcb, VMCB_INTR); |
c1150d8c DL |
3047 | /* |
3048 | * If the user space waits to inject interrupts, exit as soon as | |
3049 | * possible | |
3050 | */ | |
8061823a GN |
3051 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3052 | kvm_run->request_interrupt_window && | |
3053 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 3054 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3055 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3056 | return 0; | |
3057 | } | |
3058 | ||
3059 | return 1; | |
3060 | } | |
3061 | ||
565d0998 ML |
3062 | static int pause_interception(struct vcpu_svm *svm) |
3063 | { | |
3064 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3065 | return 1; | |
3066 | } | |
3067 | ||
851ba692 | 3068 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3069 | [SVM_EXIT_READ_CR0] = cr_interception, |
3070 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3071 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3072 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3073 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
628afd2a | 3074 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3075 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3076 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3077 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3078 | [SVM_EXIT_READ_DR0] = dr_interception, |
3079 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3080 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3081 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3082 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3083 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3084 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3085 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3086 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3087 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3088 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3089 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3090 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3091 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3092 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3093 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3094 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3095 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3096 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3097 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3098 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3099 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3100 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3101 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3102 | [SVM_EXIT_SMI] = nop_on_interception, |
3103 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3104 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 | 3105 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3106 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3107 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3108 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3109 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3110 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3111 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3112 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3113 | [SVM_EXIT_MSR] = msr_interception, |
3114 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3115 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3116 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3117 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3118 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3119 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3120 | [SVM_EXIT_STGI] = stgi_interception, |
3121 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3122 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3123 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
3124 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
3125 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
81dd35d4 | 3126 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3127 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3128 | }; |
3129 | ||
3f10c846 JR |
3130 | void dump_vmcb(struct kvm_vcpu *vcpu) |
3131 | { | |
3132 | struct vcpu_svm *svm = to_svm(vcpu); | |
3133 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3134 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3135 | ||
3136 | pr_err("VMCB Control Area:\n"); | |
4ee546b4 RJ |
3137 | pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff); |
3138 | pr_err("cr_write: %04x\n", control->intercept_cr >> 16); | |
3aed041a JR |
3139 | pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff); |
3140 | pr_err("dr_write: %04x\n", control->intercept_dr >> 16); | |
3f10c846 JR |
3141 | pr_err("exceptions: %08x\n", control->intercept_exceptions); |
3142 | pr_err("intercepts: %016llx\n", control->intercept); | |
3143 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
3144 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
3145 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
3146 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
3147 | pr_err("asid: %d\n", control->asid); | |
3148 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
3149 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
3150 | pr_err("int_vector: %08x\n", control->int_vector); | |
3151 | pr_err("int_state: %08x\n", control->int_state); | |
3152 | pr_err("exit_code: %08x\n", control->exit_code); | |
3153 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
3154 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
3155 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
3156 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
3157 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
3158 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
3159 | pr_err("event_inj: %08x\n", control->event_inj); | |
3160 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
3161 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
3162 | pr_err("next_rip: %016llx\n", control->next_rip); | |
3163 | pr_err("VMCB State Save Area:\n"); | |
3164 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
3165 | save->es.selector, save->es.attrib, | |
3166 | save->es.limit, save->es.base); | |
3167 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3168 | save->cs.selector, save->cs.attrib, | |
3169 | save->cs.limit, save->cs.base); | |
3170 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
3171 | save->ss.selector, save->ss.attrib, | |
3172 | save->ss.limit, save->ss.base); | |
3173 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
3174 | save->ds.selector, save->ds.attrib, | |
3175 | save->ds.limit, save->ds.base); | |
3176 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3177 | save->fs.selector, save->fs.attrib, | |
3178 | save->fs.limit, save->fs.base); | |
3179 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3180 | save->gs.selector, save->gs.attrib, | |
3181 | save->gs.limit, save->gs.base); | |
3182 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3183 | save->gdtr.selector, save->gdtr.attrib, | |
3184 | save->gdtr.limit, save->gdtr.base); | |
3185 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3186 | save->ldtr.selector, save->ldtr.attrib, | |
3187 | save->ldtr.limit, save->ldtr.base); | |
3188 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3189 | save->idtr.selector, save->idtr.attrib, | |
3190 | save->idtr.limit, save->idtr.base); | |
3191 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3192 | save->tr.selector, save->tr.attrib, | |
3193 | save->tr.limit, save->tr.base); | |
3194 | pr_err("cpl: %d efer: %016llx\n", | |
3195 | save->cpl, save->efer); | |
3196 | pr_err("cr0: %016llx cr2: %016llx\n", | |
3197 | save->cr0, save->cr2); | |
3198 | pr_err("cr3: %016llx cr4: %016llx\n", | |
3199 | save->cr3, save->cr4); | |
3200 | pr_err("dr6: %016llx dr7: %016llx\n", | |
3201 | save->dr6, save->dr7); | |
3202 | pr_err("rip: %016llx rflags: %016llx\n", | |
3203 | save->rip, save->rflags); | |
3204 | pr_err("rsp: %016llx rax: %016llx\n", | |
3205 | save->rsp, save->rax); | |
3206 | pr_err("star: %016llx lstar: %016llx\n", | |
3207 | save->star, save->lstar); | |
3208 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
3209 | save->cstar, save->sfmask); | |
3210 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
3211 | save->kernel_gs_base, save->sysenter_cs); | |
3212 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
3213 | save->sysenter_esp, save->sysenter_eip); | |
3214 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
3215 | save->g_pat, save->dbgctl); | |
3216 | pr_err("br_from: %016llx br_to: %016llx\n", | |
3217 | save->br_from, save->br_to); | |
3218 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
3219 | save->last_excp_from, save->last_excp_to); | |
3220 | ||
3221 | } | |
3222 | ||
586f9607 AK |
3223 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3224 | { | |
3225 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3226 | ||
3227 | *info1 = control->exit_info_1; | |
3228 | *info2 = control->exit_info_2; | |
3229 | } | |
3230 | ||
851ba692 | 3231 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3232 | { |
04d2cc77 | 3233 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3234 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3235 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3236 | |
aa17911e | 3237 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
af9ca2d7 | 3238 | |
4ee546b4 | 3239 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3240 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3241 | if (npt_enabled) | |
3242 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3243 | |
cd3ff653 JR |
3244 | if (unlikely(svm->nested.exit_required)) { |
3245 | nested_svm_vmexit(svm); | |
3246 | svm->nested.exit_required = false; | |
3247 | ||
3248 | return 1; | |
3249 | } | |
3250 | ||
2030753d | 3251 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3252 | int vmexit; |
3253 | ||
d8cabddf JR |
3254 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3255 | svm->vmcb->control.exit_info_1, | |
3256 | svm->vmcb->control.exit_info_2, | |
3257 | svm->vmcb->control.exit_int_info, | |
3258 | svm->vmcb->control.exit_int_info_err); | |
3259 | ||
410e4d57 JR |
3260 | vmexit = nested_svm_exit_special(svm); |
3261 | ||
3262 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3263 | vmexit = nested_svm_exit_handled(svm); | |
3264 | ||
3265 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3266 | return 1; |
cf74a78b AG |
3267 | } |
3268 | ||
a5c3832d JR |
3269 | svm_complete_interrupts(svm); |
3270 | ||
04d2cc77 AK |
3271 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3272 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3273 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3274 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3275 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3276 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3277 | return 0; |
3278 | } | |
3279 | ||
a2fa3e9f | 3280 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3281 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3282 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3283 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3284 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3285 | "exit_code 0x%x\n", | |
b8688d51 | 3286 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3287 | exit_code); |
3288 | ||
9d8f549d | 3289 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3290 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3291 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3292 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3293 | return 0; |
3294 | } | |
3295 | ||
851ba692 | 3296 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3297 | } |
3298 | ||
3299 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3300 | { | |
3301 | int cpu = raw_smp_processor_id(); | |
3302 | ||
0fe1e009 TH |
3303 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3304 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3305 | load_TR_desc(); |
3306 | } | |
3307 | ||
e756fc62 | 3308 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3309 | { |
3310 | int cpu = raw_smp_processor_id(); | |
3311 | ||
0fe1e009 | 3312 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3313 | |
4b656b12 | 3314 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3315 | if (svm->asid_generation != sd->asid_generation) |
3316 | new_asid(svm, sd); | |
6aa8b732 AK |
3317 | } |
3318 | ||
95ba8273 GN |
3319 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3320 | { | |
3321 | struct vcpu_svm *svm = to_svm(vcpu); | |
3322 | ||
3323 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3324 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3325 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3326 | ++vcpu->stat.nmi_injections; |
3327 | } | |
6aa8b732 | 3328 | |
85f455f7 | 3329 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3330 | { |
3331 | struct vmcb_control_area *control; | |
3332 | ||
e756fc62 | 3333 | control = &svm->vmcb->control; |
85f455f7 | 3334 | control->int_vector = irq; |
6aa8b732 AK |
3335 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3336 | control->int_ctl |= V_IRQ_MASK | | |
3337 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3338 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3339 | } |
3340 | ||
66fd3f7f | 3341 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3342 | { |
3343 | struct vcpu_svm *svm = to_svm(vcpu); | |
3344 | ||
2af9194d | 3345 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3346 | |
9fb2d2b4 GN |
3347 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3348 | ++vcpu->stat.irq_injections; | |
3349 | ||
219b65dc AG |
3350 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3351 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3352 | } |
3353 | ||
95ba8273 | 3354 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3355 | { |
3356 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3357 | |
2030753d | 3358 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3359 | return; |
3360 | ||
95ba8273 | 3361 | if (irr == -1) |
aaacfc9a JR |
3362 | return; |
3363 | ||
95ba8273 | 3364 | if (tpr >= irr) |
4ee546b4 | 3365 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3366 | } |
aaacfc9a | 3367 | |
95ba8273 GN |
3368 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3369 | { | |
3370 | struct vcpu_svm *svm = to_svm(vcpu); | |
3371 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3372 | int ret; |
3373 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3374 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3375 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3376 | ||
3377 | return ret; | |
aaacfc9a JR |
3378 | } |
3379 | ||
3cfc3092 JK |
3380 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3381 | { | |
3382 | struct vcpu_svm *svm = to_svm(vcpu); | |
3383 | ||
3384 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3385 | } | |
3386 | ||
3387 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3388 | { | |
3389 | struct vcpu_svm *svm = to_svm(vcpu); | |
3390 | ||
3391 | if (masked) { | |
3392 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3393 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3394 | } else { |
3395 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3396 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3397 | } |
3398 | } | |
3399 | ||
78646121 GN |
3400 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3401 | { | |
3402 | struct vcpu_svm *svm = to_svm(vcpu); | |
3403 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3404 | int ret; |
3405 | ||
3406 | if (!gif_set(svm) || | |
3407 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3408 | return 0; | |
3409 | ||
f6e78475 | 3410 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3411 | |
2030753d | 3412 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3413 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3414 | ||
3415 | return ret; | |
78646121 GN |
3416 | } |
3417 | ||
9222be18 | 3418 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3419 | { |
219b65dc | 3420 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3421 | |
e0231715 JR |
3422 | /* |
3423 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3424 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3425 | * get that intercept, this function will be called again though and | |
3426 | * we'll get the vintr intercept. | |
3427 | */ | |
8fe54654 | 3428 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3429 | svm_set_vintr(svm); |
3430 | svm_inject_irq(svm, 0x0); | |
3431 | } | |
85f455f7 ED |
3432 | } |
3433 | ||
95ba8273 | 3434 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3435 | { |
04d2cc77 | 3436 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3437 | |
44c11430 GN |
3438 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3439 | == HF_NMI_MASK) | |
3440 | return; /* IRET will cause a vm exit */ | |
3441 | ||
e0231715 JR |
3442 | /* |
3443 | * Something prevents NMI from been injected. Single step over possible | |
3444 | * problem (IRET or exception injection or interrupt shadow) | |
3445 | */ | |
6be7d306 | 3446 | svm->nmi_singlestep = true; |
44c11430 GN |
3447 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3448 | update_db_intercept(vcpu); | |
c1150d8c DL |
3449 | } |
3450 | ||
cbc94022 IE |
3451 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3452 | { | |
3453 | return 0; | |
3454 | } | |
3455 | ||
d9e368d6 AK |
3456 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3457 | { | |
38e5e92f JR |
3458 | struct vcpu_svm *svm = to_svm(vcpu); |
3459 | ||
3460 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3461 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3462 | else | |
3463 | svm->asid_generation--; | |
d9e368d6 AK |
3464 | } |
3465 | ||
04d2cc77 AK |
3466 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3467 | { | |
3468 | } | |
3469 | ||
d7bf8221 JR |
3470 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3471 | { | |
3472 | struct vcpu_svm *svm = to_svm(vcpu); | |
3473 | ||
2030753d | 3474 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3475 | return; |
3476 | ||
4ee546b4 | 3477 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3478 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3479 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3480 | } |
3481 | } | |
3482 | ||
649d6864 JR |
3483 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3484 | { | |
3485 | struct vcpu_svm *svm = to_svm(vcpu); | |
3486 | u64 cr8; | |
3487 | ||
2030753d | 3488 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3489 | return; |
3490 | ||
649d6864 JR |
3491 | cr8 = kvm_get_cr8(vcpu); |
3492 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3493 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3494 | } | |
3495 | ||
9222be18 GN |
3496 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3497 | { | |
3498 | u8 vector; | |
3499 | int type; | |
3500 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3501 | unsigned int3_injected = svm->int3_injected; |
3502 | ||
3503 | svm->int3_injected = 0; | |
9222be18 | 3504 | |
bd3d1ec3 AK |
3505 | /* |
3506 | * If we've made progress since setting HF_IRET_MASK, we've | |
3507 | * executed an IRET and can allow NMI injection. | |
3508 | */ | |
3509 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3510 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3511 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3512 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3513 | } | |
44c11430 | 3514 | |
9222be18 GN |
3515 | svm->vcpu.arch.nmi_injected = false; |
3516 | kvm_clear_exception_queue(&svm->vcpu); | |
3517 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3518 | ||
3519 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3520 | return; | |
3521 | ||
3842d135 AK |
3522 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3523 | ||
9222be18 GN |
3524 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3525 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3526 | ||
3527 | switch (type) { | |
3528 | case SVM_EXITINTINFO_TYPE_NMI: | |
3529 | svm->vcpu.arch.nmi_injected = true; | |
3530 | break; | |
3531 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3532 | /* |
3533 | * In case of software exceptions, do not reinject the vector, | |
3534 | * but re-execute the instruction instead. Rewind RIP first | |
3535 | * if we emulated INT3 before. | |
3536 | */ | |
3537 | if (kvm_exception_is_soft(vector)) { | |
3538 | if (vector == BP_VECTOR && int3_injected && | |
3539 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3540 | kvm_rip_write(&svm->vcpu, | |
3541 | kvm_rip_read(&svm->vcpu) - | |
3542 | int3_injected); | |
9222be18 | 3543 | break; |
66b7138f | 3544 | } |
9222be18 GN |
3545 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3546 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3547 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3548 | |
3549 | } else | |
ce7ddec4 | 3550 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3551 | break; |
3552 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3553 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3554 | break; |
3555 | default: | |
3556 | break; | |
3557 | } | |
3558 | } | |
3559 | ||
b463a6f7 AK |
3560 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3561 | { | |
3562 | struct vcpu_svm *svm = to_svm(vcpu); | |
3563 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3564 | ||
3565 | control->exit_int_info = control->event_inj; | |
3566 | control->exit_int_info_err = control->event_inj_err; | |
3567 | control->event_inj = 0; | |
3568 | svm_complete_interrupts(svm); | |
3569 | } | |
3570 | ||
80e31d4f AK |
3571 | #ifdef CONFIG_X86_64 |
3572 | #define R "r" | |
3573 | #else | |
3574 | #define R "e" | |
3575 | #endif | |
3576 | ||
851ba692 | 3577 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3578 | { |
a2fa3e9f | 3579 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3580 | |
2041a06a JR |
3581 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3582 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3583 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3584 | ||
cd3ff653 JR |
3585 | /* |
3586 | * A vmexit emulation is required before the vcpu can be executed | |
3587 | * again. | |
3588 | */ | |
3589 | if (unlikely(svm->nested.exit_required)) | |
3590 | return; | |
3591 | ||
e756fc62 | 3592 | pre_svm_run(svm); |
6aa8b732 | 3593 | |
649d6864 JR |
3594 | sync_lapic_to_cr8(vcpu); |
3595 | ||
cda0ffdd | 3596 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3597 | |
04d2cc77 AK |
3598 | clgi(); |
3599 | ||
3600 | local_irq_enable(); | |
36241b8c | 3601 | |
6aa8b732 | 3602 | asm volatile ( |
80e31d4f AK |
3603 | "push %%"R"bp; \n\t" |
3604 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3605 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3606 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3607 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3608 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3609 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3610 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3611 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3612 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3613 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3614 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3615 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3616 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3617 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3618 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3619 | #endif |
3620 | ||
6aa8b732 | 3621 | /* Enter guest mode */ |
80e31d4f AK |
3622 | "push %%"R"ax \n\t" |
3623 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3624 | __ex(SVM_VMLOAD) "\n\t" |
3625 | __ex(SVM_VMRUN) "\n\t" | |
3626 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3627 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3628 | |
3629 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3630 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3631 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3632 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3633 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3634 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3635 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3636 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3637 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3638 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3639 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3640 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3641 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3642 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3643 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3644 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3645 | #endif |
80e31d4f | 3646 | "pop %%"R"bp" |
6aa8b732 | 3647 | : |
fb3f0f51 | 3648 | : [svm]"a"(svm), |
6aa8b732 | 3649 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3650 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3651 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3652 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3653 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3654 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3655 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3656 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3657 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3658 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3659 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3660 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3661 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3662 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3663 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3664 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3665 | #endif |
54a08c04 | 3666 | : "cc", "memory" |
80e31d4f | 3667 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3668 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3669 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3670 | #endif | |
3671 | ); | |
6aa8b732 | 3672 | |
82ca2d10 AK |
3673 | #ifdef CONFIG_X86_64 |
3674 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3675 | #else | |
dacccfdd | 3676 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3677 | #ifndef CONFIG_X86_32_LAZY_GS |
3678 | loadsegment(gs, svm->host.gs); | |
3679 | #endif | |
9581d442 | 3680 | #endif |
6aa8b732 AK |
3681 | |
3682 | reload_tss(vcpu); | |
3683 | ||
56ba47dd AK |
3684 | local_irq_disable(); |
3685 | ||
13c34e07 AK |
3686 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3687 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3688 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3689 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3690 | ||
3781c01c JR |
3691 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3692 | kvm_before_handle_nmi(&svm->vcpu); | |
3693 | ||
3694 | stgi(); | |
3695 | ||
3696 | /* Any pending NMI will happen here */ | |
3697 | ||
3698 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3699 | kvm_after_handle_nmi(&svm->vcpu); | |
3700 | ||
d7bf8221 JR |
3701 | sync_cr8_to_lapic(vcpu); |
3702 | ||
a2fa3e9f | 3703 | svm->next_rip = 0; |
9222be18 | 3704 | |
38e5e92f JR |
3705 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3706 | ||
631bc487 GN |
3707 | /* if exit due to PF check for async PF */ |
3708 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3709 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3710 | ||
6de4f3ad AK |
3711 | if (npt_enabled) { |
3712 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3713 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3714 | } | |
fe5913e4 JR |
3715 | |
3716 | /* | |
3717 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3718 | * change the physical cpu | |
3719 | */ | |
3720 | if (unlikely(svm->vmcb->control.exit_code == | |
3721 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3722 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3723 | |
3724 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3725 | } |
3726 | ||
80e31d4f AK |
3727 | #undef R |
3728 | ||
6aa8b732 AK |
3729 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3730 | { | |
a2fa3e9f GH |
3731 | struct vcpu_svm *svm = to_svm(vcpu); |
3732 | ||
3733 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3734 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3735 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3736 | } |
3737 | ||
1c97f0a0 JR |
3738 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3739 | { | |
3740 | struct vcpu_svm *svm = to_svm(vcpu); | |
3741 | ||
3742 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3743 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3744 | |
3745 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3746 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3747 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3748 | |
f40f6a45 | 3749 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3750 | } |
3751 | ||
6aa8b732 AK |
3752 | static int is_disabled(void) |
3753 | { | |
6031a61c JR |
3754 | u64 vm_cr; |
3755 | ||
3756 | rdmsrl(MSR_VM_CR, vm_cr); | |
3757 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3758 | return 1; | |
3759 | ||
6aa8b732 AK |
3760 | return 0; |
3761 | } | |
3762 | ||
102d8325 IM |
3763 | static void |
3764 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3765 | { | |
3766 | /* | |
3767 | * Patch in the VMMCALL instruction: | |
3768 | */ | |
3769 | hypercall[0] = 0x0f; | |
3770 | hypercall[1] = 0x01; | |
3771 | hypercall[2] = 0xd9; | |
102d8325 IM |
3772 | } |
3773 | ||
002c7f7c YS |
3774 | static void svm_check_processor_compat(void *rtn) |
3775 | { | |
3776 | *(int *)rtn = 0; | |
3777 | } | |
3778 | ||
774ead3a AK |
3779 | static bool svm_cpu_has_accelerated_tpr(void) |
3780 | { | |
3781 | return false; | |
3782 | } | |
3783 | ||
4b12f0de | 3784 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3785 | { |
3786 | return 0; | |
3787 | } | |
3788 | ||
0e851880 SY |
3789 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3790 | { | |
3791 | } | |
3792 | ||
d4330ef2 JR |
3793 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3794 | { | |
c2c63a49 | 3795 | switch (func) { |
4c62a2dc JR |
3796 | case 0x80000001: |
3797 | if (nested) | |
3798 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3799 | break; | |
c2c63a49 JR |
3800 | case 0x8000000A: |
3801 | entry->eax = 1; /* SVM revision 1 */ | |
3802 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3803 | ASID emulation to nested SVM */ | |
3804 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
3805 | entry->edx = 0; /* Per default do not support any |
3806 | additional features */ | |
3807 | ||
3808 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 3809 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 3810 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 3811 | |
3d4aeaad JR |
3812 | /* Support NPT for the guest if enabled */ |
3813 | if (npt_enabled) | |
3814 | entry->edx |= SVM_FEATURE_NPT; | |
3815 | ||
c2c63a49 JR |
3816 | break; |
3817 | } | |
d4330ef2 JR |
3818 | } |
3819 | ||
229456fc | 3820 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
e0231715 JR |
3821 | { SVM_EXIT_READ_CR0, "read_cr0" }, |
3822 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3823 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3824 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3825 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3826 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3827 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3828 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3829 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3830 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3831 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3832 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3833 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3834 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3835 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3836 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3837 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3838 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
229456fc MT |
3839 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, |
3840 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3841 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3842 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3843 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3844 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3845 | { SVM_EXIT_INTR, "interrupt" }, | |
3846 | { SVM_EXIT_NMI, "nmi" }, | |
3847 | { SVM_EXIT_SMI, "smi" }, | |
3848 | { SVM_EXIT_INIT, "init" }, | |
3849 | { SVM_EXIT_VINTR, "vintr" }, | |
3850 | { SVM_EXIT_CPUID, "cpuid" }, | |
3851 | { SVM_EXIT_INVD, "invd" }, | |
3852 | { SVM_EXIT_HLT, "hlt" }, | |
3853 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3854 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3855 | { SVM_EXIT_IOIO, "io" }, | |
3856 | { SVM_EXIT_MSR, "msr" }, | |
3857 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3858 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3859 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3860 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3861 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3862 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3863 | { SVM_EXIT_STGI, "stgi" }, | |
3864 | { SVM_EXIT_CLGI, "clgi" }, | |
3865 | { SVM_EXIT_SKINIT, "skinit" }, | |
3866 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3867 | { SVM_EXIT_MONITOR, "monitor" }, | |
3868 | { SVM_EXIT_MWAIT, "mwait" }, | |
81dd35d4 | 3869 | { SVM_EXIT_XSETBV, "xsetbv" }, |
229456fc MT |
3870 | { SVM_EXIT_NPF, "npf" }, |
3871 | { -1, NULL } | |
3872 | }; | |
3873 | ||
17cc3935 | 3874 | static int svm_get_lpage_level(void) |
344f414f | 3875 | { |
17cc3935 | 3876 | return PT_PDPE_LEVEL; |
344f414f JR |
3877 | } |
3878 | ||
4e47c7a6 SY |
3879 | static bool svm_rdtscp_supported(void) |
3880 | { | |
3881 | return false; | |
3882 | } | |
3883 | ||
f5f48ee1 SY |
3884 | static bool svm_has_wbinvd_exit(void) |
3885 | { | |
3886 | return true; | |
3887 | } | |
3888 | ||
02daab21 AK |
3889 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
3890 | { | |
3891 | struct vcpu_svm *svm = to_svm(vcpu); | |
3892 | ||
18c918c5 | 3893 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 3894 | update_cr0_intercept(svm); |
02daab21 AK |
3895 | } |
3896 | ||
8061252e JR |
3897 | #define PRE_EX(exit) { .exit_code = (exit), \ |
3898 | .stage = X86_ICPT_PRE_EXCEPT, \ | |
3899 | .valid = true } | |
cfec82cb JR |
3900 | #define POST_EX(exit) { .exit_code = (exit), \ |
3901 | .stage = X86_ICPT_POST_EXCEPT, \ | |
3902 | .valid = true } | |
d7eb8203 JR |
3903 | #define POST_MEM(exit) { .exit_code = (exit), \ |
3904 | .stage = X86_ICPT_POST_MEMACCESS, \ | |
3905 | .valid = true } | |
cfec82cb JR |
3906 | |
3907 | static struct __x86_intercept { | |
3908 | u32 exit_code; | |
3909 | enum x86_intercept_stage stage; | |
3910 | bool valid; | |
3911 | } x86_intercept_map[] = { | |
3912 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
3913 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
3914 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
3915 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
3916 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
3917 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
3918 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
3919 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
3920 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
3921 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
3922 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
3923 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
3924 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
3925 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
3926 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
3927 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
3928 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
3929 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
3930 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
3931 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
3932 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
3933 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
3934 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
3935 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
3936 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
3937 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
3938 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
3939 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
3940 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
3941 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
3942 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
3943 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
3944 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
3945 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
3946 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
3947 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
3948 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
3949 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
3950 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
3951 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
3952 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
3953 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
3954 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
3955 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
3956 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
3957 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
3958 | }; |
3959 | ||
8061252e | 3960 | #undef PRE_EX |
cfec82cb | 3961 | #undef POST_EX |
d7eb8203 | 3962 | #undef POST_MEM |
cfec82cb | 3963 | |
8a76d7f2 JR |
3964 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
3965 | struct x86_instruction_info *info, | |
3966 | enum x86_intercept_stage stage) | |
3967 | { | |
cfec82cb JR |
3968 | struct vcpu_svm *svm = to_svm(vcpu); |
3969 | int vmexit, ret = X86EMUL_CONTINUE; | |
3970 | struct __x86_intercept icpt_info; | |
3971 | struct vmcb *vmcb = svm->vmcb; | |
3972 | ||
3973 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
3974 | goto out; | |
3975 | ||
3976 | icpt_info = x86_intercept_map[info->intercept]; | |
3977 | ||
3978 | if (!icpt_info.valid || stage != icpt_info.stage) | |
3979 | goto out; | |
3980 | ||
3981 | switch (icpt_info.exit_code) { | |
3982 | case SVM_EXIT_READ_CR0: | |
3983 | if (info->intercept == x86_intercept_cr_read) | |
3984 | icpt_info.exit_code += info->modrm_reg; | |
3985 | break; | |
3986 | case SVM_EXIT_WRITE_CR0: { | |
3987 | unsigned long cr0, val; | |
3988 | u64 intercept; | |
3989 | ||
3990 | if (info->intercept == x86_intercept_cr_write) | |
3991 | icpt_info.exit_code += info->modrm_reg; | |
3992 | ||
3993 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0) | |
3994 | break; | |
3995 | ||
3996 | intercept = svm->nested.intercept; | |
3997 | ||
3998 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
3999 | break; | |
4000 | ||
4001 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4002 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4003 | ||
4004 | if (info->intercept == x86_intercept_lmsw) { | |
4005 | cr0 &= 0xfUL; | |
4006 | val &= 0xfUL; | |
4007 | /* lmsw can't clear PE - catch this here */ | |
4008 | if (cr0 & X86_CR0_PE) | |
4009 | val |= X86_CR0_PE; | |
4010 | } | |
4011 | ||
4012 | if (cr0 ^ val) | |
4013 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4014 | ||
4015 | break; | |
4016 | } | |
3b88e41a JR |
4017 | case SVM_EXIT_READ_DR0: |
4018 | case SVM_EXIT_WRITE_DR0: | |
4019 | icpt_info.exit_code += info->modrm_reg; | |
4020 | break; | |
8061252e JR |
4021 | case SVM_EXIT_MSR: |
4022 | if (info->intercept == x86_intercept_wrmsr) | |
4023 | vmcb->control.exit_info_1 = 1; | |
4024 | else | |
4025 | vmcb->control.exit_info_1 = 0; | |
4026 | break; | |
bf608f88 JR |
4027 | case SVM_EXIT_PAUSE: |
4028 | /* | |
4029 | * We get this for NOP only, but pause | |
4030 | * is rep not, check this here | |
4031 | */ | |
4032 | if (info->rep_prefix != REPE_PREFIX) | |
4033 | goto out; | |
f6511935 JR |
4034 | case SVM_EXIT_IOIO: { |
4035 | u64 exit_info; | |
4036 | u32 bytes; | |
4037 | ||
4038 | exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16; | |
4039 | ||
4040 | if (info->intercept == x86_intercept_in || | |
4041 | info->intercept == x86_intercept_ins) { | |
4042 | exit_info |= SVM_IOIO_TYPE_MASK; | |
4043 | bytes = info->src_bytes; | |
4044 | } else { | |
4045 | bytes = info->dst_bytes; | |
4046 | } | |
4047 | ||
4048 | if (info->intercept == x86_intercept_outs || | |
4049 | info->intercept == x86_intercept_ins) | |
4050 | exit_info |= SVM_IOIO_STR_MASK; | |
4051 | ||
4052 | if (info->rep_prefix) | |
4053 | exit_info |= SVM_IOIO_REP_MASK; | |
4054 | ||
4055 | bytes = min(bytes, 4u); | |
4056 | ||
4057 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4058 | ||
4059 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4060 | ||
4061 | vmcb->control.exit_info_1 = exit_info; | |
4062 | vmcb->control.exit_info_2 = info->next_rip; | |
4063 | ||
4064 | break; | |
4065 | } | |
cfec82cb JR |
4066 | default: |
4067 | break; | |
4068 | } | |
4069 | ||
4070 | vmcb->control.next_rip = info->next_rip; | |
4071 | vmcb->control.exit_code = icpt_info.exit_code; | |
4072 | vmexit = nested_svm_exit_handled(svm); | |
4073 | ||
4074 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4075 | : X86EMUL_CONTINUE; | |
4076 | ||
4077 | out: | |
4078 | return ret; | |
8a76d7f2 JR |
4079 | } |
4080 | ||
cbdd1bea | 4081 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4082 | .cpu_has_kvm_support = has_svm, |
4083 | .disabled_by_bios = is_disabled, | |
4084 | .hardware_setup = svm_hardware_setup, | |
4085 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4086 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4087 | .hardware_enable = svm_hardware_enable, |
4088 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4089 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
4090 | |
4091 | .vcpu_create = svm_create_vcpu, | |
4092 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4093 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4094 | |
04d2cc77 | 4095 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4096 | .vcpu_load = svm_vcpu_load, |
4097 | .vcpu_put = svm_vcpu_put, | |
4098 | ||
4099 | .set_guest_debug = svm_guest_debug, | |
4100 | .get_msr = svm_get_msr, | |
4101 | .set_msr = svm_set_msr, | |
4102 | .get_segment_base = svm_get_segment_base, | |
4103 | .get_segment = svm_get_segment, | |
4104 | .set_segment = svm_set_segment, | |
2e4d2653 | 4105 | .get_cpl = svm_get_cpl, |
1747fb71 | 4106 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4107 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4108 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4109 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4110 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4111 | .set_cr3 = svm_set_cr3, |
4112 | .set_cr4 = svm_set_cr4, | |
4113 | .set_efer = svm_set_efer, | |
4114 | .get_idt = svm_get_idt, | |
4115 | .set_idt = svm_set_idt, | |
4116 | .get_gdt = svm_get_gdt, | |
4117 | .set_gdt = svm_set_gdt, | |
020df079 | 4118 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 4119 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4120 | .get_rflags = svm_get_rflags, |
4121 | .set_rflags = svm_set_rflags, | |
6b52d186 | 4122 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4123 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4124 | |
6aa8b732 | 4125 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4126 | |
6aa8b732 | 4127 | .run = svm_vcpu_run, |
04d2cc77 | 4128 | .handle_exit = handle_exit, |
6aa8b732 | 4129 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4130 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4131 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4132 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4133 | .set_irq = svm_set_irq, |
95ba8273 | 4134 | .set_nmi = svm_inject_nmi, |
298101da | 4135 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4136 | .cancel_injection = svm_cancel_injection, |
78646121 | 4137 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4138 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4139 | .get_nmi_mask = svm_get_nmi_mask, |
4140 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4141 | .enable_nmi_window = enable_nmi_window, |
4142 | .enable_irq_window = enable_irq_window, | |
4143 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
4144 | |
4145 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4146 | .get_tdp_level = get_npt_level, |
4b12f0de | 4147 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4148 | |
586f9607 | 4149 | .get_exit_info = svm_get_exit_info, |
229456fc | 4150 | .exit_reasons_str = svm_exit_reasons_str, |
586f9607 | 4151 | |
17cc3935 | 4152 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4153 | |
4154 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4155 | |
4156 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
4157 | |
4158 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4159 | |
4160 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
4161 | |
4162 | .write_tsc_offset = svm_write_tsc_offset, | |
e48672fa | 4163 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
1c97f0a0 JR |
4164 | |
4165 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4166 | |
4167 | .check_intercept = svm_check_intercept, | |
6aa8b732 AK |
4168 | }; |
4169 | ||
4170 | static int __init svm_init(void) | |
4171 | { | |
cb498ea2 | 4172 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4173 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4174 | } |
4175 | ||
4176 | static void __exit svm_exit(void) | |
4177 | { | |
cb498ea2 | 4178 | kvm_exit(); |
6aa8b732 AK |
4179 | } |
4180 | ||
4181 | module_init(svm_init) | |
4182 | module_exit(svm_exit) |