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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
ae759544 | 25 | #include <linux/mod_devicetable.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/vmalloc.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
229456fc | 30 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
6aa8b732 | 32 | |
1018faa6 | 33 | #include <asm/perf_event.h> |
67ec6607 | 34 | #include <asm/tlbflush.h> |
e495606d | 35 | #include <asm/desc.h> |
631bc487 | 36 | #include <asm/kvm_para.h> |
6aa8b732 | 37 | |
63d1142f | 38 | #include <asm/virtext.h> |
229456fc | 39 | #include "trace.h" |
63d1142f | 40 | |
4ecac3fd AK |
41 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
42 | ||
6aa8b732 AK |
43 | MODULE_AUTHOR("Qumranet"); |
44 | MODULE_LICENSE("GPL"); | |
45 | ||
ae759544 JT |
46 | static const struct x86_cpu_id svm_cpu_id[] = { |
47 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
48 | {} | |
49 | }; | |
50 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
51 | ||
6aa8b732 AK |
52 | #define IOPM_ALLOC_ORDER 2 |
53 | #define MSRPM_ALLOC_ORDER 1 | |
54 | ||
6aa8b732 AK |
55 | #define SEG_TYPE_LDT 2 |
56 | #define SEG_TYPE_BUSY_TSS16 3 | |
57 | ||
6bc31bdc AP |
58 | #define SVM_FEATURE_NPT (1 << 0) |
59 | #define SVM_FEATURE_LBRV (1 << 1) | |
60 | #define SVM_FEATURE_SVML (1 << 2) | |
61 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
62 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
63 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
64 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
65 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 66 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 67 | |
410e4d57 JR |
68 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
69 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
70 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
71 | ||
24e09cbf JR |
72 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
73 | ||
fbc0db76 | 74 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
75 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
76 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 77 | |
67ec6607 JR |
78 | static bool erratum_383_found __read_mostly; |
79 | ||
6c8166a7 AK |
80 | static const u32 host_save_user_msrs[] = { |
81 | #ifdef CONFIG_X86_64 | |
82 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
83 | MSR_FS_BASE, | |
84 | #endif | |
85 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
86 | }; | |
87 | ||
88 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
89 | ||
90 | struct kvm_vcpu; | |
91 | ||
e6aa9abd JR |
92 | struct nested_state { |
93 | struct vmcb *hsave; | |
94 | u64 hsave_msr; | |
4a810181 | 95 | u64 vm_cr_msr; |
e6aa9abd JR |
96 | u64 vmcb; |
97 | ||
98 | /* These are the merged vectors */ | |
99 | u32 *msrpm; | |
100 | ||
101 | /* gpa pointers to the real vectors */ | |
102 | u64 vmcb_msrpm; | |
ce2ac085 | 103 | u64 vmcb_iopm; |
aad42c64 | 104 | |
cd3ff653 JR |
105 | /* A VMEXIT is required but not yet emulated */ |
106 | bool exit_required; | |
107 | ||
aad42c64 | 108 | /* cache for intercepts of the guest */ |
4ee546b4 | 109 | u32 intercept_cr; |
3aed041a | 110 | u32 intercept_dr; |
aad42c64 JR |
111 | u32 intercept_exceptions; |
112 | u64 intercept; | |
113 | ||
5bd2edc3 JR |
114 | /* Nested Paging related state */ |
115 | u64 nested_cr3; | |
e6aa9abd JR |
116 | }; |
117 | ||
323c3d80 JR |
118 | #define MSRPM_OFFSETS 16 |
119 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
120 | ||
2b036c6b BO |
121 | /* |
122 | * Set osvw_len to higher value when updated Revision Guides | |
123 | * are published and we know what the new status bits are | |
124 | */ | |
125 | static uint64_t osvw_len = 4, osvw_status; | |
126 | ||
6c8166a7 AK |
127 | struct vcpu_svm { |
128 | struct kvm_vcpu vcpu; | |
129 | struct vmcb *vmcb; | |
130 | unsigned long vmcb_pa; | |
131 | struct svm_cpu_data *svm_data; | |
132 | uint64_t asid_generation; | |
133 | uint64_t sysenter_esp; | |
134 | uint64_t sysenter_eip; | |
135 | ||
136 | u64 next_rip; | |
137 | ||
138 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 139 | struct { |
dacccfdd AK |
140 | u16 fs; |
141 | u16 gs; | |
142 | u16 ldt; | |
afe9e66f AK |
143 | u64 gs_base; |
144 | } host; | |
6c8166a7 AK |
145 | |
146 | u32 *msrpm; | |
6c8166a7 | 147 | |
bd3d1ec3 AK |
148 | ulong nmi_iret_rip; |
149 | ||
e6aa9abd | 150 | struct nested_state nested; |
6be7d306 JK |
151 | |
152 | bool nmi_singlestep; | |
66b7138f JK |
153 | |
154 | unsigned int3_injected; | |
155 | unsigned long int3_rip; | |
631bc487 | 156 | u32 apf_reason; |
fbc0db76 JR |
157 | |
158 | u64 tsc_ratio; | |
6c8166a7 AK |
159 | }; |
160 | ||
fbc0db76 JR |
161 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
162 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
163 | ||
455716fa JR |
164 | #define MSR_INVALID 0xffffffffU |
165 | ||
09941fbb | 166 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
167 | u32 index; /* Index of the MSR */ |
168 | bool always; /* True if intercept is always on */ | |
169 | } direct_access_msrs[] = { | |
8c06585d | 170 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
171 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
172 | #ifdef CONFIG_X86_64 | |
173 | { .index = MSR_GS_BASE, .always = true }, | |
174 | { .index = MSR_FS_BASE, .always = true }, | |
175 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
176 | { .index = MSR_LSTAR, .always = true }, | |
177 | { .index = MSR_CSTAR, .always = true }, | |
178 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
179 | #endif | |
180 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
181 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
182 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
183 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
184 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
185 | }; |
186 | ||
709ddebf JR |
187 | /* enable NPT for AMD64 and X86 with PAE */ |
188 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
189 | static bool npt_enabled = true; | |
190 | #else | |
e0231715 | 191 | static bool npt_enabled; |
709ddebf | 192 | #endif |
6c7dac72 | 193 | |
e2358851 DB |
194 | /* allow nested paging (virtualized MMU) for all guests */ |
195 | static int npt = true; | |
6c7dac72 | 196 | module_param(npt, int, S_IRUGO); |
e3da3acd | 197 | |
e2358851 DB |
198 | /* allow nested virtualization in KVM/SVM */ |
199 | static int nested = true; | |
236de055 AG |
200 | module_param(nested, int, S_IRUGO); |
201 | ||
44874f84 | 202 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 203 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 204 | |
410e4d57 | 205 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 206 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 207 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
208 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
209 | bool has_error_code, u32 error_code); | |
92a1f12d | 210 | static u64 __scale_tsc(u64 ratio, u64 tsc); |
cf74a78b | 211 | |
8d28fec4 | 212 | enum { |
116a0a23 JR |
213 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
214 | pause filter count */ | |
f56838e4 | 215 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 216 | VMCB_ASID, /* ASID */ |
decdbf6a | 217 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 218 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 219 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 220 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 221 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 222 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 223 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 224 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
225 | VMCB_DIRTY_MAX, |
226 | }; | |
227 | ||
0574dec0 JR |
228 | /* TPR and CR2 are always written before VMRUN */ |
229 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
230 | |
231 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
232 | { | |
233 | vmcb->control.clean = 0; | |
234 | } | |
235 | ||
236 | static inline void mark_all_clean(struct vmcb *vmcb) | |
237 | { | |
238 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
239 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
240 | } | |
241 | ||
242 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
243 | { | |
244 | vmcb->control.clean &= ~(1 << bit); | |
245 | } | |
246 | ||
a2fa3e9f GH |
247 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
248 | { | |
fb3f0f51 | 249 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
250 | } |
251 | ||
384c6368 JR |
252 | static void recalc_intercepts(struct vcpu_svm *svm) |
253 | { | |
254 | struct vmcb_control_area *c, *h; | |
255 | struct nested_state *g; | |
256 | ||
116a0a23 JR |
257 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
258 | ||
384c6368 JR |
259 | if (!is_guest_mode(&svm->vcpu)) |
260 | return; | |
261 | ||
262 | c = &svm->vmcb->control; | |
263 | h = &svm->nested.hsave->control; | |
264 | g = &svm->nested; | |
265 | ||
4ee546b4 | 266 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 267 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
268 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
269 | c->intercept = h->intercept | g->intercept; | |
270 | } | |
271 | ||
4ee546b4 RJ |
272 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
273 | { | |
274 | if (is_guest_mode(&svm->vcpu)) | |
275 | return svm->nested.hsave; | |
276 | else | |
277 | return svm->vmcb; | |
278 | } | |
279 | ||
280 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
281 | { | |
282 | struct vmcb *vmcb = get_host_vmcb(svm); | |
283 | ||
284 | vmcb->control.intercept_cr |= (1U << bit); | |
285 | ||
286 | recalc_intercepts(svm); | |
287 | } | |
288 | ||
289 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
290 | { | |
291 | struct vmcb *vmcb = get_host_vmcb(svm); | |
292 | ||
293 | vmcb->control.intercept_cr &= ~(1U << bit); | |
294 | ||
295 | recalc_intercepts(svm); | |
296 | } | |
297 | ||
298 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
299 | { | |
300 | struct vmcb *vmcb = get_host_vmcb(svm); | |
301 | ||
302 | return vmcb->control.intercept_cr & (1U << bit); | |
303 | } | |
304 | ||
3aed041a JR |
305 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
306 | { | |
307 | struct vmcb *vmcb = get_host_vmcb(svm); | |
308 | ||
309 | vmcb->control.intercept_dr |= (1U << bit); | |
310 | ||
311 | recalc_intercepts(svm); | |
312 | } | |
313 | ||
314 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
315 | { | |
316 | struct vmcb *vmcb = get_host_vmcb(svm); | |
317 | ||
318 | vmcb->control.intercept_dr &= ~(1U << bit); | |
319 | ||
320 | recalc_intercepts(svm); | |
321 | } | |
322 | ||
18c918c5 JR |
323 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
324 | { | |
325 | struct vmcb *vmcb = get_host_vmcb(svm); | |
326 | ||
327 | vmcb->control.intercept_exceptions |= (1U << bit); | |
328 | ||
329 | recalc_intercepts(svm); | |
330 | } | |
331 | ||
332 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
333 | { | |
334 | struct vmcb *vmcb = get_host_vmcb(svm); | |
335 | ||
336 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
337 | ||
338 | recalc_intercepts(svm); | |
339 | } | |
340 | ||
8a05a1b8 JR |
341 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
342 | { | |
343 | struct vmcb *vmcb = get_host_vmcb(svm); | |
344 | ||
345 | vmcb->control.intercept |= (1ULL << bit); | |
346 | ||
347 | recalc_intercepts(svm); | |
348 | } | |
349 | ||
350 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
351 | { | |
352 | struct vmcb *vmcb = get_host_vmcb(svm); | |
353 | ||
354 | vmcb->control.intercept &= ~(1ULL << bit); | |
355 | ||
356 | recalc_intercepts(svm); | |
357 | } | |
358 | ||
2af9194d JR |
359 | static inline void enable_gif(struct vcpu_svm *svm) |
360 | { | |
361 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
362 | } | |
363 | ||
364 | static inline void disable_gif(struct vcpu_svm *svm) | |
365 | { | |
366 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
367 | } | |
368 | ||
369 | static inline bool gif_set(struct vcpu_svm *svm) | |
370 | { | |
371 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
372 | } | |
373 | ||
4866d5e3 | 374 | static unsigned long iopm_base; |
6aa8b732 AK |
375 | |
376 | struct kvm_ldttss_desc { | |
377 | u16 limit0; | |
378 | u16 base0; | |
e0231715 JR |
379 | unsigned base1:8, type:5, dpl:2, p:1; |
380 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
381 | u32 base3; |
382 | u32 zero1; | |
383 | } __attribute__((packed)); | |
384 | ||
385 | struct svm_cpu_data { | |
386 | int cpu; | |
387 | ||
5008fdf5 AK |
388 | u64 asid_generation; |
389 | u32 max_asid; | |
390 | u32 next_asid; | |
6aa8b732 AK |
391 | struct kvm_ldttss_desc *tss_desc; |
392 | ||
393 | struct page *save_area; | |
394 | }; | |
395 | ||
396 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
397 | ||
398 | struct svm_init_data { | |
399 | int cpu; | |
400 | int r; | |
401 | }; | |
402 | ||
09941fbb | 403 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 404 | |
9d8f549d | 405 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
406 | #define MSRS_RANGE_SIZE 2048 |
407 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
408 | ||
455716fa JR |
409 | static u32 svm_msrpm_offset(u32 msr) |
410 | { | |
411 | u32 offset; | |
412 | int i; | |
413 | ||
414 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
415 | if (msr < msrpm_ranges[i] || | |
416 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
417 | continue; | |
418 | ||
419 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
420 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
421 | ||
422 | /* Now we have the u8 offset - but need the u32 offset */ | |
423 | return offset / 4; | |
424 | } | |
425 | ||
426 | /* MSR not in any range */ | |
427 | return MSR_INVALID; | |
428 | } | |
429 | ||
6aa8b732 AK |
430 | #define MAX_INST_SIZE 15 |
431 | ||
6aa8b732 AK |
432 | static inline void clgi(void) |
433 | { | |
4ecac3fd | 434 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
435 | } |
436 | ||
437 | static inline void stgi(void) | |
438 | { | |
4ecac3fd | 439 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
440 | } |
441 | ||
442 | static inline void invlpga(unsigned long addr, u32 asid) | |
443 | { | |
e0231715 | 444 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
445 | } |
446 | ||
4b16184c JR |
447 | static int get_npt_level(void) |
448 | { | |
449 | #ifdef CONFIG_X86_64 | |
450 | return PT64_ROOT_LEVEL; | |
451 | #else | |
452 | return PT32E_ROOT_LEVEL; | |
453 | #endif | |
454 | } | |
455 | ||
6aa8b732 AK |
456 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
457 | { | |
6dc696d4 | 458 | vcpu->arch.efer = efer; |
709ddebf | 459 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 460 | efer &= ~EFER_LME; |
6aa8b732 | 461 | |
9962d032 | 462 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 463 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
464 | } |
465 | ||
6aa8b732 AK |
466 | static int is_external_interrupt(u32 info) |
467 | { | |
468 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
469 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
470 | } | |
471 | ||
2809f5d2 GC |
472 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
473 | { | |
474 | struct vcpu_svm *svm = to_svm(vcpu); | |
475 | u32 ret = 0; | |
476 | ||
477 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 478 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
479 | return ret & mask; |
480 | } | |
481 | ||
482 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
483 | { | |
484 | struct vcpu_svm *svm = to_svm(vcpu); | |
485 | ||
486 | if (mask == 0) | |
487 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
488 | else | |
489 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
490 | ||
491 | } | |
492 | ||
6aa8b732 AK |
493 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
494 | { | |
a2fa3e9f GH |
495 | struct vcpu_svm *svm = to_svm(vcpu); |
496 | ||
6bc31bdc AP |
497 | if (svm->vmcb->control.next_rip != 0) |
498 | svm->next_rip = svm->vmcb->control.next_rip; | |
499 | ||
a2fa3e9f | 500 | if (!svm->next_rip) { |
51d8b661 | 501 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
502 | EMULATE_DONE) |
503 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
504 | return; |
505 | } | |
5fdbf976 MT |
506 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
507 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
508 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 509 | |
5fdbf976 | 510 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 511 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
512 | } |
513 | ||
116a4752 | 514 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
515 | bool has_error_code, u32 error_code, |
516 | bool reinject) | |
116a4752 JK |
517 | { |
518 | struct vcpu_svm *svm = to_svm(vcpu); | |
519 | ||
e0231715 JR |
520 | /* |
521 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
522 | * handle the exception | |
523 | */ | |
ce7ddec4 JR |
524 | if (!reinject && |
525 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
526 | return; |
527 | ||
2a6b20b8 | 528 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
529 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
530 | ||
531 | /* | |
532 | * For guest debugging where we have to reinject #BP if some | |
533 | * INT3 is guest-owned: | |
534 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
535 | * raises a fault that is not intercepted. Still better than | |
536 | * failing in all cases. | |
537 | */ | |
538 | skip_emulated_instruction(&svm->vcpu); | |
539 | rip = kvm_rip_read(&svm->vcpu); | |
540 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
541 | svm->int3_injected = rip - old_rip; | |
542 | } | |
543 | ||
116a4752 JK |
544 | svm->vmcb->control.event_inj = nr |
545 | | SVM_EVTINJ_VALID | |
546 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
547 | | SVM_EVTINJ_TYPE_EXEPT; | |
548 | svm->vmcb->control.event_inj_err = error_code; | |
549 | } | |
550 | ||
67ec6607 JR |
551 | static void svm_init_erratum_383(void) |
552 | { | |
553 | u32 low, high; | |
554 | int err; | |
555 | u64 val; | |
556 | ||
1be85a6d | 557 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
558 | return; |
559 | ||
560 | /* Use _safe variants to not break nested virtualization */ | |
561 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
562 | if (err) | |
563 | return; | |
564 | ||
565 | val |= (1ULL << 47); | |
566 | ||
567 | low = lower_32_bits(val); | |
568 | high = upper_32_bits(val); | |
569 | ||
570 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
571 | ||
572 | erratum_383_found = true; | |
573 | } | |
574 | ||
2b036c6b BO |
575 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
576 | { | |
577 | /* | |
578 | * Guests should see errata 400 and 415 as fixed (assuming that | |
579 | * HLT and IO instructions are intercepted). | |
580 | */ | |
581 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
582 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
583 | ||
584 | /* | |
585 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
586 | * all osvw.status bits inside that length, including bit 0 (which is | |
587 | * reserved for erratum 298), are valid. However, if host processor's | |
588 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
589 | * be conservative here and therefore we tell the guest that erratum 298 | |
590 | * is present (because we really don't know). | |
591 | */ | |
592 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
593 | vcpu->arch.osvw.status |= 1; | |
594 | } | |
595 | ||
6aa8b732 AK |
596 | static int has_svm(void) |
597 | { | |
63d1142f | 598 | const char *msg; |
6aa8b732 | 599 | |
63d1142f | 600 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 601 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
602 | return 0; |
603 | } | |
604 | ||
6aa8b732 AK |
605 | return 1; |
606 | } | |
607 | ||
608 | static void svm_hardware_disable(void *garbage) | |
609 | { | |
fbc0db76 JR |
610 | /* Make sure we clean up behind us */ |
611 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
612 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
613 | ||
2c8dceeb | 614 | cpu_svm_disable(); |
1018faa6 JR |
615 | |
616 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
617 | } |
618 | ||
10474ae8 | 619 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
620 | { |
621 | ||
0fe1e009 | 622 | struct svm_cpu_data *sd; |
6aa8b732 | 623 | uint64_t efer; |
89a27f4d | 624 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
625 | struct desc_struct *gdt; |
626 | int me = raw_smp_processor_id(); | |
627 | ||
10474ae8 AG |
628 | rdmsrl(MSR_EFER, efer); |
629 | if (efer & EFER_SVME) | |
630 | return -EBUSY; | |
631 | ||
6aa8b732 | 632 | if (!has_svm()) { |
1f5b77f5 | 633 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 634 | return -EINVAL; |
6aa8b732 | 635 | } |
0fe1e009 | 636 | sd = per_cpu(svm_data, me); |
0fe1e009 | 637 | if (!sd) { |
1f5b77f5 | 638 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 639 | return -EINVAL; |
6aa8b732 AK |
640 | } |
641 | ||
0fe1e009 TH |
642 | sd->asid_generation = 1; |
643 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
644 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 645 | |
d6ab1ed4 | 646 | native_store_gdt(&gdt_descr); |
89a27f4d | 647 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 648 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 649 | |
9962d032 | 650 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 651 | |
d0316554 | 652 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 653 | |
fbc0db76 JR |
654 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
655 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
656 | __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT; | |
657 | } | |
658 | ||
2b036c6b BO |
659 | |
660 | /* | |
661 | * Get OSVW bits. | |
662 | * | |
663 | * Note that it is possible to have a system with mixed processor | |
664 | * revisions and therefore different OSVW bits. If bits are not the same | |
665 | * on different processors then choose the worst case (i.e. if erratum | |
666 | * is present on one processor and not on another then assume that the | |
667 | * erratum is present everywhere). | |
668 | */ | |
669 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
670 | uint64_t len, status = 0; | |
671 | int err; | |
672 | ||
673 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
674 | if (!err) | |
675 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
676 | &err); | |
677 | ||
678 | if (err) | |
679 | osvw_status = osvw_len = 0; | |
680 | else { | |
681 | if (len < osvw_len) | |
682 | osvw_len = len; | |
683 | osvw_status |= status; | |
684 | osvw_status &= (1ULL << osvw_len) - 1; | |
685 | } | |
686 | } else | |
687 | osvw_status = osvw_len = 0; | |
688 | ||
67ec6607 JR |
689 | svm_init_erratum_383(); |
690 | ||
1018faa6 JR |
691 | amd_pmu_enable_virt(); |
692 | ||
10474ae8 | 693 | return 0; |
6aa8b732 AK |
694 | } |
695 | ||
0da1db75 JR |
696 | static void svm_cpu_uninit(int cpu) |
697 | { | |
0fe1e009 | 698 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 699 | |
0fe1e009 | 700 | if (!sd) |
0da1db75 JR |
701 | return; |
702 | ||
703 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
704 | __free_page(sd->save_area); |
705 | kfree(sd); | |
0da1db75 JR |
706 | } |
707 | ||
6aa8b732 AK |
708 | static int svm_cpu_init(int cpu) |
709 | { | |
0fe1e009 | 710 | struct svm_cpu_data *sd; |
6aa8b732 AK |
711 | int r; |
712 | ||
0fe1e009 TH |
713 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
714 | if (!sd) | |
6aa8b732 | 715 | return -ENOMEM; |
0fe1e009 TH |
716 | sd->cpu = cpu; |
717 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 718 | r = -ENOMEM; |
0fe1e009 | 719 | if (!sd->save_area) |
6aa8b732 AK |
720 | goto err_1; |
721 | ||
0fe1e009 | 722 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
723 | |
724 | return 0; | |
725 | ||
726 | err_1: | |
0fe1e009 | 727 | kfree(sd); |
6aa8b732 AK |
728 | return r; |
729 | ||
730 | } | |
731 | ||
ac72a9b7 JR |
732 | static bool valid_msr_intercept(u32 index) |
733 | { | |
734 | int i; | |
735 | ||
736 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
737 | if (direct_access_msrs[i].index == index) | |
738 | return true; | |
739 | ||
740 | return false; | |
741 | } | |
742 | ||
bfc733a7 RR |
743 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
744 | int read, int write) | |
6aa8b732 | 745 | { |
455716fa JR |
746 | u8 bit_read, bit_write; |
747 | unsigned long tmp; | |
748 | u32 offset; | |
6aa8b732 | 749 | |
ac72a9b7 JR |
750 | /* |
751 | * If this warning triggers extend the direct_access_msrs list at the | |
752 | * beginning of the file | |
753 | */ | |
754 | WARN_ON(!valid_msr_intercept(msr)); | |
755 | ||
455716fa JR |
756 | offset = svm_msrpm_offset(msr); |
757 | bit_read = 2 * (msr & 0x0f); | |
758 | bit_write = 2 * (msr & 0x0f) + 1; | |
759 | tmp = msrpm[offset]; | |
760 | ||
761 | BUG_ON(offset == MSR_INVALID); | |
762 | ||
763 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
764 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
765 | ||
766 | msrpm[offset] = tmp; | |
6aa8b732 AK |
767 | } |
768 | ||
f65c229c | 769 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
770 | { |
771 | int i; | |
772 | ||
f65c229c JR |
773 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
774 | ||
ac72a9b7 JR |
775 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
776 | if (!direct_access_msrs[i].always) | |
777 | continue; | |
778 | ||
779 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
780 | } | |
f65c229c JR |
781 | } |
782 | ||
323c3d80 JR |
783 | static void add_msr_offset(u32 offset) |
784 | { | |
785 | int i; | |
786 | ||
787 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
788 | ||
789 | /* Offset already in list? */ | |
790 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 791 | return; |
323c3d80 JR |
792 | |
793 | /* Slot used by another offset? */ | |
794 | if (msrpm_offsets[i] != MSR_INVALID) | |
795 | continue; | |
796 | ||
797 | /* Add offset to list */ | |
798 | msrpm_offsets[i] = offset; | |
799 | ||
800 | return; | |
6aa8b732 | 801 | } |
323c3d80 JR |
802 | |
803 | /* | |
804 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
805 | * increase MSRPM_OFFSETS in this case. | |
806 | */ | |
bfc733a7 | 807 | BUG(); |
6aa8b732 AK |
808 | } |
809 | ||
323c3d80 | 810 | static void init_msrpm_offsets(void) |
f65c229c | 811 | { |
323c3d80 | 812 | int i; |
f65c229c | 813 | |
323c3d80 JR |
814 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
815 | ||
816 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
817 | u32 offset; | |
818 | ||
819 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
820 | BUG_ON(offset == MSR_INVALID); | |
821 | ||
822 | add_msr_offset(offset); | |
823 | } | |
f65c229c JR |
824 | } |
825 | ||
24e09cbf JR |
826 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
827 | { | |
828 | u32 *msrpm = svm->msrpm; | |
829 | ||
830 | svm->vmcb->control.lbr_ctl = 1; | |
831 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
832 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
833 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
834 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
835 | } | |
836 | ||
837 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
838 | { | |
839 | u32 *msrpm = svm->msrpm; | |
840 | ||
841 | svm->vmcb->control.lbr_ctl = 0; | |
842 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
843 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
844 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
845 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
846 | } | |
847 | ||
6aa8b732 AK |
848 | static __init int svm_hardware_setup(void) |
849 | { | |
850 | int cpu; | |
851 | struct page *iopm_pages; | |
f65c229c | 852 | void *iopm_va; |
6aa8b732 AK |
853 | int r; |
854 | ||
6aa8b732 AK |
855 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
856 | ||
857 | if (!iopm_pages) | |
858 | return -ENOMEM; | |
c8681339 AL |
859 | |
860 | iopm_va = page_address(iopm_pages); | |
861 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
862 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
863 | ||
323c3d80 JR |
864 | init_msrpm_offsets(); |
865 | ||
50a37eb4 JR |
866 | if (boot_cpu_has(X86_FEATURE_NX)) |
867 | kvm_enable_efer_bits(EFER_NX); | |
868 | ||
1b2fd70c AG |
869 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
870 | kvm_enable_efer_bits(EFER_FFXSR); | |
871 | ||
92a1f12d JR |
872 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
873 | u64 max; | |
874 | ||
875 | kvm_has_tsc_control = true; | |
876 | ||
877 | /* | |
878 | * Make sure the user can only configure tsc_khz values that | |
879 | * fit into a signed integer. | |
880 | * A min value is not calculated needed because it will always | |
881 | * be 1 on all machines and a value of 0 is used to disable | |
882 | * tsc-scaling for the vcpu. | |
883 | */ | |
884 | max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX)); | |
885 | ||
886 | kvm_max_guest_tsc_khz = max; | |
887 | } | |
888 | ||
236de055 AG |
889 | if (nested) { |
890 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 891 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
892 | } |
893 | ||
3230bb47 | 894 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
895 | r = svm_cpu_init(cpu); |
896 | if (r) | |
f65c229c | 897 | goto err; |
6aa8b732 | 898 | } |
33bd6a0b | 899 | |
2a6b20b8 | 900 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
901 | npt_enabled = false; |
902 | ||
6c7dac72 JR |
903 | if (npt_enabled && !npt) { |
904 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
905 | npt_enabled = false; | |
906 | } | |
907 | ||
18552672 | 908 | if (npt_enabled) { |
e3da3acd | 909 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 910 | kvm_enable_tdp(); |
5f4cb662 JR |
911 | } else |
912 | kvm_disable_tdp(); | |
e3da3acd | 913 | |
6aa8b732 AK |
914 | return 0; |
915 | ||
f65c229c | 916 | err: |
6aa8b732 AK |
917 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
918 | iopm_base = 0; | |
919 | return r; | |
920 | } | |
921 | ||
922 | static __exit void svm_hardware_unsetup(void) | |
923 | { | |
0da1db75 JR |
924 | int cpu; |
925 | ||
3230bb47 | 926 | for_each_possible_cpu(cpu) |
0da1db75 JR |
927 | svm_cpu_uninit(cpu); |
928 | ||
6aa8b732 | 929 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 930 | iopm_base = 0; |
6aa8b732 AK |
931 | } |
932 | ||
933 | static void init_seg(struct vmcb_seg *seg) | |
934 | { | |
935 | seg->selector = 0; | |
936 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 937 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
938 | seg->limit = 0xffff; |
939 | seg->base = 0; | |
940 | } | |
941 | ||
942 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
943 | { | |
944 | seg->selector = 0; | |
945 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
946 | seg->limit = 0xffff; | |
947 | seg->base = 0; | |
948 | } | |
949 | ||
fbc0db76 JR |
950 | static u64 __scale_tsc(u64 ratio, u64 tsc) |
951 | { | |
952 | u64 mult, frac, _tsc; | |
953 | ||
954 | mult = ratio >> 32; | |
955 | frac = ratio & ((1ULL << 32) - 1); | |
956 | ||
957 | _tsc = tsc; | |
958 | _tsc *= mult; | |
959 | _tsc += (tsc >> 32) * frac; | |
960 | _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32; | |
961 | ||
962 | return _tsc; | |
963 | } | |
964 | ||
965 | static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
966 | { | |
967 | struct vcpu_svm *svm = to_svm(vcpu); | |
968 | u64 _tsc = tsc; | |
969 | ||
970 | if (svm->tsc_ratio != TSC_RATIO_DEFAULT) | |
971 | _tsc = __scale_tsc(svm->tsc_ratio, tsc); | |
972 | ||
973 | return _tsc; | |
974 | } | |
975 | ||
cc578287 | 976 | static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
4051b188 JR |
977 | { |
978 | struct vcpu_svm *svm = to_svm(vcpu); | |
979 | u64 ratio; | |
980 | u64 khz; | |
981 | ||
cc578287 ZA |
982 | /* Guest TSC same frequency as host TSC? */ |
983 | if (!scale) { | |
984 | svm->tsc_ratio = TSC_RATIO_DEFAULT; | |
4051b188 | 985 | return; |
cc578287 | 986 | } |
4051b188 | 987 | |
cc578287 ZA |
988 | /* TSC scaling supported? */ |
989 | if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { | |
990 | if (user_tsc_khz > tsc_khz) { | |
991 | vcpu->arch.tsc_catchup = 1; | |
992 | vcpu->arch.tsc_always_catchup = 1; | |
993 | } else | |
994 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
4051b188 JR |
995 | return; |
996 | } | |
997 | ||
998 | khz = user_tsc_khz; | |
999 | ||
1000 | /* TSC scaling required - calculate ratio */ | |
1001 | ratio = khz << 32; | |
1002 | do_div(ratio, tsc_khz); | |
1003 | ||
1004 | if (ratio == 0 || ratio & TSC_RATIO_RSVD) { | |
1005 | WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n", | |
1006 | user_tsc_khz); | |
1007 | return; | |
1008 | } | |
4051b188 JR |
1009 | svm->tsc_ratio = ratio; |
1010 | } | |
1011 | ||
f4e1b3c8 ZA |
1012 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1013 | { | |
1014 | struct vcpu_svm *svm = to_svm(vcpu); | |
1015 | u64 g_tsc_offset = 0; | |
1016 | ||
2030753d | 1017 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1018 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1019 | svm->nested.hsave->control.tsc_offset; | |
1020 | svm->nested.hsave->control.tsc_offset = offset; | |
1021 | } | |
1022 | ||
1023 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1024 | |
1025 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1026 | } |
1027 | ||
f1e2b260 | 1028 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host) |
e48672fa ZA |
1029 | { |
1030 | struct vcpu_svm *svm = to_svm(vcpu); | |
1031 | ||
f1e2b260 MT |
1032 | WARN_ON(adjustment < 0); |
1033 | if (host) | |
1034 | adjustment = svm_scale_tsc(vcpu, adjustment); | |
1035 | ||
e48672fa | 1036 | svm->vmcb->control.tsc_offset += adjustment; |
2030753d | 1037 | if (is_guest_mode(vcpu)) |
e48672fa | 1038 | svm->nested.hsave->control.tsc_offset += adjustment; |
116a0a23 | 1039 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
1040 | } |
1041 | ||
857e4099 JR |
1042 | static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1043 | { | |
1044 | u64 tsc; | |
1045 | ||
1046 | tsc = svm_scale_tsc(vcpu, native_read_tsc()); | |
1047 | ||
1048 | return target_tsc - tsc; | |
1049 | } | |
1050 | ||
e6101a96 | 1051 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1052 | { |
e6101a96 JR |
1053 | struct vmcb_control_area *control = &svm->vmcb->control; |
1054 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1055 | |
bff78274 | 1056 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 1057 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1058 | |
4ee546b4 RJ |
1059 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1060 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1061 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1062 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1063 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1064 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
1065 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1066 | |
3aed041a JR |
1067 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
1068 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
1069 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
1070 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
1071 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
1072 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
1073 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
1074 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
1075 | ||
1076 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
1077 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
1078 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
1079 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
1080 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
1081 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
1082 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
1083 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 1084 | |
18c918c5 JR |
1085 | set_exception_intercept(svm, PF_VECTOR); |
1086 | set_exception_intercept(svm, UD_VECTOR); | |
1087 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 1088 | |
8a05a1b8 JR |
1089 | set_intercept(svm, INTERCEPT_INTR); |
1090 | set_intercept(svm, INTERCEPT_NMI); | |
1091 | set_intercept(svm, INTERCEPT_SMI); | |
1092 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1093 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1094 | set_intercept(svm, INTERCEPT_CPUID); |
1095 | set_intercept(svm, INTERCEPT_INVD); | |
1096 | set_intercept(svm, INTERCEPT_HLT); | |
1097 | set_intercept(svm, INTERCEPT_INVLPG); | |
1098 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1099 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1100 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1101 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1102 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1103 | set_intercept(svm, INTERCEPT_VMRUN); | |
1104 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1105 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1106 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1107 | set_intercept(svm, INTERCEPT_STGI); | |
1108 | set_intercept(svm, INTERCEPT_CLGI); | |
1109 | set_intercept(svm, INTERCEPT_SKINIT); | |
1110 | set_intercept(svm, INTERCEPT_WBINVD); | |
1111 | set_intercept(svm, INTERCEPT_MONITOR); | |
1112 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 1113 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
1114 | |
1115 | control->iopm_base_pa = iopm_base; | |
f65c229c | 1116 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1117 | control->int_ctl = V_INTR_MASKING_MASK; |
1118 | ||
1119 | init_seg(&save->es); | |
1120 | init_seg(&save->ss); | |
1121 | init_seg(&save->ds); | |
1122 | init_seg(&save->fs); | |
1123 | init_seg(&save->gs); | |
1124 | ||
1125 | save->cs.selector = 0xf000; | |
1126 | /* Executable/Readable Code Segment */ | |
1127 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1128 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1129 | save->cs.limit = 0xffff; | |
d92899a0 AK |
1130 | /* |
1131 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
1132 | * be consistent with it. | |
1133 | * | |
1134 | * Replace when we have real mode working for vmx. | |
1135 | */ | |
1136 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
1137 | |
1138 | save->gdtr.limit = 0xffff; | |
1139 | save->idtr.limit = 0xffff; | |
1140 | ||
1141 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1142 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1143 | ||
eaa48512 | 1144 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1145 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1146 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1147 | save->rip = 0x0000fff0; |
5fdbf976 | 1148 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1149 | |
e0231715 JR |
1150 | /* |
1151 | * This is the guest-visible cr0 value. | |
18fa000a | 1152 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 1153 | */ |
678041ad MT |
1154 | svm->vcpu.arch.cr0 = 0; |
1155 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 1156 | |
66aee91a | 1157 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1158 | /* rdx = ?? */ |
709ddebf JR |
1159 | |
1160 | if (npt_enabled) { | |
1161 | /* Setup VMCB for Nested Paging */ | |
1162 | control->nested_ctl = 1; | |
8a05a1b8 | 1163 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1164 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1165 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1166 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 1167 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
1168 | save->cr3 = 0; |
1169 | save->cr4 = 0; | |
1170 | } | |
f40f6a45 | 1171 | svm->asid_generation = 0; |
1371d904 | 1172 | |
e6aa9abd | 1173 | svm->nested.vmcb = 0; |
2af9194d JR |
1174 | svm->vcpu.arch.hflags = 0; |
1175 | ||
2a6b20b8 | 1176 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1177 | control->pause_filter_count = 3000; |
8a05a1b8 | 1178 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1179 | } |
1180 | ||
8d28fec4 RJ |
1181 | mark_all_dirty(svm->vmcb); |
1182 | ||
2af9194d | 1183 | enable_gif(svm); |
6aa8b732 AK |
1184 | } |
1185 | ||
e00c8cf2 | 1186 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1187 | { |
1188 | struct vcpu_svm *svm = to_svm(vcpu); | |
1189 | ||
e6101a96 | 1190 | init_vmcb(svm); |
70433389 | 1191 | |
c5af89b6 | 1192 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 1193 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
1194 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
1195 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 1196 | } |
5fdbf976 MT |
1197 | vcpu->arch.regs_avail = ~0; |
1198 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
1199 | |
1200 | return 0; | |
04d2cc77 AK |
1201 | } |
1202 | ||
fb3f0f51 | 1203 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1204 | { |
a2fa3e9f | 1205 | struct vcpu_svm *svm; |
6aa8b732 | 1206 | struct page *page; |
f65c229c | 1207 | struct page *msrpm_pages; |
b286d5d8 | 1208 | struct page *hsave_page; |
3d6368ef | 1209 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1210 | int err; |
6aa8b732 | 1211 | |
c16f862d | 1212 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1213 | if (!svm) { |
1214 | err = -ENOMEM; | |
1215 | goto out; | |
1216 | } | |
1217 | ||
fbc0db76 JR |
1218 | svm->tsc_ratio = TSC_RATIO_DEFAULT; |
1219 | ||
fb3f0f51 RR |
1220 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); |
1221 | if (err) | |
1222 | goto free_svm; | |
1223 | ||
b7af4043 | 1224 | err = -ENOMEM; |
6aa8b732 | 1225 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1226 | if (!page) |
fb3f0f51 | 1227 | goto uninit; |
6aa8b732 | 1228 | |
f65c229c JR |
1229 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1230 | if (!msrpm_pages) | |
b7af4043 | 1231 | goto free_page1; |
3d6368ef AG |
1232 | |
1233 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1234 | if (!nested_msrpm_pages) | |
b7af4043 | 1235 | goto free_page2; |
f65c229c | 1236 | |
b286d5d8 AG |
1237 | hsave_page = alloc_page(GFP_KERNEL); |
1238 | if (!hsave_page) | |
b7af4043 TY |
1239 | goto free_page3; |
1240 | ||
e6aa9abd | 1241 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1242 | |
b7af4043 TY |
1243 | svm->msrpm = page_address(msrpm_pages); |
1244 | svm_vcpu_init_msrpm(svm->msrpm); | |
1245 | ||
e6aa9abd | 1246 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1247 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1248 | |
a2fa3e9f GH |
1249 | svm->vmcb = page_address(page); |
1250 | clear_page(svm->vmcb); | |
1251 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1252 | svm->asid_generation = 0; | |
e6101a96 | 1253 | init_vmcb(svm); |
a2fa3e9f | 1254 | |
10ab25cd JK |
1255 | err = fx_init(&svm->vcpu); |
1256 | if (err) | |
1257 | goto free_page4; | |
1258 | ||
ad312c7c | 1259 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1260 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1261 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1262 | |
2b036c6b BO |
1263 | svm_init_osvw(&svm->vcpu); |
1264 | ||
fb3f0f51 | 1265 | return &svm->vcpu; |
36241b8c | 1266 | |
10ab25cd JK |
1267 | free_page4: |
1268 | __free_page(hsave_page); | |
b7af4043 TY |
1269 | free_page3: |
1270 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1271 | free_page2: | |
1272 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1273 | free_page1: | |
1274 | __free_page(page); | |
fb3f0f51 RR |
1275 | uninit: |
1276 | kvm_vcpu_uninit(&svm->vcpu); | |
1277 | free_svm: | |
a4770347 | 1278 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1279 | out: |
1280 | return ERR_PTR(err); | |
6aa8b732 AK |
1281 | } |
1282 | ||
1283 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1284 | { | |
a2fa3e9f GH |
1285 | struct vcpu_svm *svm = to_svm(vcpu); |
1286 | ||
fb3f0f51 | 1287 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1288 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1289 | __free_page(virt_to_page(svm->nested.hsave)); |
1290 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1291 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1292 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1293 | } |
1294 | ||
15ad7146 | 1295 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1296 | { |
a2fa3e9f | 1297 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1298 | int i; |
0cc5064d | 1299 | |
0cc5064d | 1300 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1301 | svm->asid_generation = 0; |
8d28fec4 | 1302 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1303 | } |
94dfbdb3 | 1304 | |
82ca2d10 AK |
1305 | #ifdef CONFIG_X86_64 |
1306 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1307 | #endif | |
dacccfdd AK |
1308 | savesegment(fs, svm->host.fs); |
1309 | savesegment(gs, svm->host.gs); | |
1310 | svm->host.ldt = kvm_read_ldt(); | |
1311 | ||
94dfbdb3 | 1312 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1313 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 JR |
1314 | |
1315 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR) && | |
1316 | svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) { | |
1317 | __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio; | |
1318 | wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio); | |
1319 | } | |
6aa8b732 AK |
1320 | } |
1321 | ||
1322 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1323 | { | |
a2fa3e9f | 1324 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1325 | int i; |
1326 | ||
e1beb1d3 | 1327 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1328 | kvm_load_ldt(svm->host.ldt); |
1329 | #ifdef CONFIG_X86_64 | |
1330 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1331 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1332 | load_gs_index(svm->host.gs); |
dacccfdd | 1333 | #else |
831ca609 | 1334 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1335 | loadsegment(gs, svm->host.gs); |
831ca609 | 1336 | #endif |
dacccfdd | 1337 | #endif |
94dfbdb3 | 1338 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1339 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1340 | } |
1341 | ||
ea5e97e8 KW |
1342 | static void svm_update_cpl(struct kvm_vcpu *vcpu) |
1343 | { | |
1344 | struct vcpu_svm *svm = to_svm(vcpu); | |
1345 | int cpl; | |
1346 | ||
1347 | if (!is_protmode(vcpu)) | |
1348 | cpl = 0; | |
1349 | else if (svm->vmcb->save.rflags & X86_EFLAGS_VM) | |
1350 | cpl = 3; | |
1351 | else | |
1352 | cpl = svm->vmcb->save.cs.selector & 0x3; | |
1353 | ||
1354 | svm->vmcb->save.cpl = cpl; | |
1355 | } | |
1356 | ||
6aa8b732 AK |
1357 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1358 | { | |
a2fa3e9f | 1359 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1360 | } |
1361 | ||
1362 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1363 | { | |
4cee4798 KW |
1364 | unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags; |
1365 | ||
a2fa3e9f | 1366 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
4cee4798 KW |
1367 | if ((old_rflags ^ rflags) & X86_EFLAGS_VM) |
1368 | svm_update_cpl(vcpu); | |
6aa8b732 AK |
1369 | } |
1370 | ||
6de4f3ad AK |
1371 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1372 | { | |
1373 | switch (reg) { | |
1374 | case VCPU_EXREG_PDPTR: | |
1375 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1376 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1377 | break; |
1378 | default: | |
1379 | BUG(); | |
1380 | } | |
1381 | } | |
1382 | ||
f0b85051 AG |
1383 | static void svm_set_vintr(struct vcpu_svm *svm) |
1384 | { | |
8a05a1b8 | 1385 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1386 | } |
1387 | ||
1388 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1389 | { | |
8a05a1b8 | 1390 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1391 | } |
1392 | ||
6aa8b732 AK |
1393 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1394 | { | |
a2fa3e9f | 1395 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1396 | |
1397 | switch (seg) { | |
1398 | case VCPU_SREG_CS: return &save->cs; | |
1399 | case VCPU_SREG_DS: return &save->ds; | |
1400 | case VCPU_SREG_ES: return &save->es; | |
1401 | case VCPU_SREG_FS: return &save->fs; | |
1402 | case VCPU_SREG_GS: return &save->gs; | |
1403 | case VCPU_SREG_SS: return &save->ss; | |
1404 | case VCPU_SREG_TR: return &save->tr; | |
1405 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1406 | } | |
1407 | BUG(); | |
8b6d44c7 | 1408 | return NULL; |
6aa8b732 AK |
1409 | } |
1410 | ||
1411 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1412 | { | |
1413 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1414 | ||
1415 | return s->base; | |
1416 | } | |
1417 | ||
1418 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1419 | struct kvm_segment *var, int seg) | |
1420 | { | |
1421 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1422 | ||
1423 | var->base = s->base; | |
1424 | var->limit = s->limit; | |
1425 | var->selector = s->selector; | |
1426 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1427 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1428 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1429 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1430 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1431 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1432 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1433 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1434 | |
e0231715 JR |
1435 | /* |
1436 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1437 | * for cross vendor migration purposes by "not present" |
1438 | */ | |
1439 | var->unusable = !var->present || (var->type == 0); | |
1440 | ||
1fbdc7a5 AP |
1441 | switch (seg) { |
1442 | case VCPU_SREG_CS: | |
1443 | /* | |
1444 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1445 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1446 | * Intel's VMENTRY has a check on the 'G' bit. | |
1447 | */ | |
25022acc | 1448 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1449 | break; |
1450 | case VCPU_SREG_TR: | |
1451 | /* | |
1452 | * Work around a bug where the busy flag in the tr selector | |
1453 | * isn't exposed | |
1454 | */ | |
c0d09828 | 1455 | var->type |= 0x2; |
1fbdc7a5 AP |
1456 | break; |
1457 | case VCPU_SREG_DS: | |
1458 | case VCPU_SREG_ES: | |
1459 | case VCPU_SREG_FS: | |
1460 | case VCPU_SREG_GS: | |
1461 | /* | |
1462 | * The accessed bit must always be set in the segment | |
1463 | * descriptor cache, although it can be cleared in the | |
1464 | * descriptor, the cached bit always remains at 1. Since | |
1465 | * Intel has a check on this, set it here to support | |
1466 | * cross-vendor migration. | |
1467 | */ | |
1468 | if (!var->unusable) | |
1469 | var->type |= 0x1; | |
1470 | break; | |
b586eb02 | 1471 | case VCPU_SREG_SS: |
e0231715 JR |
1472 | /* |
1473 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1474 | * descriptor is left as 1, although the whole segment has |
1475 | * been made unusable. Clear it here to pass an Intel VMX | |
1476 | * entry check when cross vendor migrating. | |
1477 | */ | |
1478 | if (var->unusable) | |
1479 | var->db = 0; | |
1480 | break; | |
1fbdc7a5 | 1481 | } |
6aa8b732 AK |
1482 | } |
1483 | ||
2e4d2653 IE |
1484 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1485 | { | |
1486 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1487 | ||
1488 | return save->cpl; | |
1489 | } | |
1490 | ||
89a27f4d | 1491 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1492 | { |
a2fa3e9f GH |
1493 | struct vcpu_svm *svm = to_svm(vcpu); |
1494 | ||
89a27f4d GN |
1495 | dt->size = svm->vmcb->save.idtr.limit; |
1496 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1497 | } |
1498 | ||
89a27f4d | 1499 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1500 | { |
a2fa3e9f GH |
1501 | struct vcpu_svm *svm = to_svm(vcpu); |
1502 | ||
89a27f4d GN |
1503 | svm->vmcb->save.idtr.limit = dt->size; |
1504 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1505 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1506 | } |
1507 | ||
89a27f4d | 1508 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1509 | { |
a2fa3e9f GH |
1510 | struct vcpu_svm *svm = to_svm(vcpu); |
1511 | ||
89a27f4d GN |
1512 | dt->size = svm->vmcb->save.gdtr.limit; |
1513 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1514 | } |
1515 | ||
89a27f4d | 1516 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1517 | { |
a2fa3e9f GH |
1518 | struct vcpu_svm *svm = to_svm(vcpu); |
1519 | ||
89a27f4d GN |
1520 | svm->vmcb->save.gdtr.limit = dt->size; |
1521 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1522 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1523 | } |
1524 | ||
e8467fda AK |
1525 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1526 | { | |
1527 | } | |
1528 | ||
aff48baa AK |
1529 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1530 | { | |
1531 | } | |
1532 | ||
25c4c276 | 1533 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1534 | { |
1535 | } | |
1536 | ||
d225157b AK |
1537 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1538 | { | |
1539 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1540 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1541 | ||
1542 | if (!svm->vcpu.fpu_active) | |
1543 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1544 | else | |
1545 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1546 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1547 | ||
dcca1a65 | 1548 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1549 | |
1550 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1551 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1552 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1553 | } else { |
4ee546b4 RJ |
1554 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1555 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1556 | } |
1557 | } | |
1558 | ||
6aa8b732 AK |
1559 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1560 | { | |
a2fa3e9f GH |
1561 | struct vcpu_svm *svm = to_svm(vcpu); |
1562 | ||
05b3e0c2 | 1563 | #ifdef CONFIG_X86_64 |
f6801dff | 1564 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1565 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1566 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1567 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1568 | } |
1569 | ||
d77c26fc | 1570 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1571 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1572 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1573 | } |
1574 | } | |
1575 | #endif | |
ad312c7c | 1576 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1577 | |
1578 | if (!npt_enabled) | |
1579 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1580 | |
1581 | if (!vcpu->fpu_active) | |
334df50a | 1582 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1583 | /* |
1584 | * re-enable caching here because the QEMU bios | |
1585 | * does not do it - this results in some delay at | |
1586 | * reboot | |
1587 | */ | |
1588 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1589 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1590 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1591 | update_cr0_intercept(svm); |
6aa8b732 AK |
1592 | } |
1593 | ||
5e1746d6 | 1594 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1595 | { |
6394b649 | 1596 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1597 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1598 | ||
5e1746d6 NHE |
1599 | if (cr4 & X86_CR4_VMXE) |
1600 | return 1; | |
1601 | ||
e5eab0ce | 1602 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1603 | svm_flush_tlb(vcpu); |
6394b649 | 1604 | |
ec077263 JR |
1605 | vcpu->arch.cr4 = cr4; |
1606 | if (!npt_enabled) | |
1607 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1608 | cr4 |= host_cr4_mce; |
ec077263 | 1609 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1610 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1611 | return 0; |
6aa8b732 AK |
1612 | } |
1613 | ||
1614 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1615 | struct kvm_segment *var, int seg) | |
1616 | { | |
a2fa3e9f | 1617 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1618 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1619 | ||
1620 | s->base = var->base; | |
1621 | s->limit = var->limit; | |
1622 | s->selector = var->selector; | |
1623 | if (var->unusable) | |
1624 | s->attrib = 0; | |
1625 | else { | |
1626 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1627 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1628 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1629 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1630 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1631 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1632 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1633 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1634 | } | |
1635 | if (seg == VCPU_SREG_CS) | |
ea5e97e8 | 1636 | svm_update_cpl(vcpu); |
6aa8b732 | 1637 | |
060d0c9a | 1638 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1639 | } |
1640 | ||
c8639010 | 1641 | static void update_db_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1642 | { |
d0bfb940 JK |
1643 | struct vcpu_svm *svm = to_svm(vcpu); |
1644 | ||
18c918c5 JR |
1645 | clr_exception_intercept(svm, DB_VECTOR); |
1646 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1647 | |
6be7d306 | 1648 | if (svm->nmi_singlestep) |
18c918c5 | 1649 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1650 | |
d0bfb940 JK |
1651 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1652 | if (vcpu->guest_debug & | |
1653 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1654 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1655 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1656 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1657 | } else |
1658 | vcpu->guest_debug = 0; | |
44c11430 GN |
1659 | } |
1660 | ||
0fe1e009 | 1661 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1662 | { |
0fe1e009 TH |
1663 | if (sd->next_asid > sd->max_asid) { |
1664 | ++sd->asid_generation; | |
1665 | sd->next_asid = 1; | |
a2fa3e9f | 1666 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1667 | } |
1668 | ||
0fe1e009 TH |
1669 | svm->asid_generation = sd->asid_generation; |
1670 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1671 | |
1672 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1673 | } |
1674 | ||
020df079 | 1675 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1676 | { |
42dbaa5a | 1677 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1678 | |
020df079 | 1679 | svm->vmcb->save.dr7 = value; |
72214b96 | 1680 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1681 | } |
1682 | ||
851ba692 | 1683 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1684 | { |
631bc487 | 1685 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1686 | u32 error_code; |
631bc487 | 1687 | int r = 1; |
6aa8b732 | 1688 | |
631bc487 GN |
1689 | switch (svm->apf_reason) { |
1690 | default: | |
1691 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1692 | |
631bc487 GN |
1693 | trace_kvm_page_fault(fault_address, error_code); |
1694 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1695 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1696 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1697 | svm->vmcb->control.insn_bytes, | |
1698 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1699 | break; |
1700 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1701 | svm->apf_reason = 0; | |
1702 | local_irq_disable(); | |
1703 | kvm_async_pf_task_wait(fault_address); | |
1704 | local_irq_enable(); | |
1705 | break; | |
1706 | case KVM_PV_REASON_PAGE_READY: | |
1707 | svm->apf_reason = 0; | |
1708 | local_irq_disable(); | |
1709 | kvm_async_pf_task_wake(fault_address); | |
1710 | local_irq_enable(); | |
1711 | break; | |
1712 | } | |
1713 | return r; | |
6aa8b732 AK |
1714 | } |
1715 | ||
851ba692 | 1716 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1717 | { |
851ba692 AK |
1718 | struct kvm_run *kvm_run = svm->vcpu.run; |
1719 | ||
d0bfb940 | 1720 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1721 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1722 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1723 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1724 | return 1; | |
1725 | } | |
44c11430 | 1726 | |
6be7d306 JK |
1727 | if (svm->nmi_singlestep) { |
1728 | svm->nmi_singlestep = false; | |
44c11430 GN |
1729 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1730 | svm->vmcb->save.rflags &= | |
1731 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
c8639010 | 1732 | update_db_bp_intercept(&svm->vcpu); |
44c11430 GN |
1733 | } |
1734 | ||
1735 | if (svm->vcpu.guest_debug & | |
e0231715 | 1736 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1737 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1738 | kvm_run->debug.arch.pc = | |
1739 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1740 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1741 | return 0; | |
1742 | } | |
1743 | ||
1744 | return 1; | |
d0bfb940 JK |
1745 | } |
1746 | ||
851ba692 | 1747 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1748 | { |
851ba692 AK |
1749 | struct kvm_run *kvm_run = svm->vcpu.run; |
1750 | ||
d0bfb940 JK |
1751 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1752 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1753 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1754 | return 0; | |
1755 | } | |
1756 | ||
851ba692 | 1757 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1758 | { |
1759 | int er; | |
1760 | ||
51d8b661 | 1761 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1762 | if (er != EMULATE_DONE) |
7ee5d940 | 1763 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1764 | return 1; |
1765 | } | |
1766 | ||
6b52d186 | 1767 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1768 | { |
6b52d186 | 1769 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1770 | |
18c918c5 | 1771 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1772 | |
e756fc62 | 1773 | svm->vcpu.fpu_active = 1; |
d225157b | 1774 | update_cr0_intercept(svm); |
6b52d186 | 1775 | } |
a2fa3e9f | 1776 | |
6b52d186 AK |
1777 | static int nm_interception(struct vcpu_svm *svm) |
1778 | { | |
1779 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1780 | return 1; |
7807fa6c AL |
1781 | } |
1782 | ||
67ec6607 JR |
1783 | static bool is_erratum_383(void) |
1784 | { | |
1785 | int err, i; | |
1786 | u64 value; | |
1787 | ||
1788 | if (!erratum_383_found) | |
1789 | return false; | |
1790 | ||
1791 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1792 | if (err) | |
1793 | return false; | |
1794 | ||
1795 | /* Bit 62 may or may not be set for this mce */ | |
1796 | value &= ~(1ULL << 62); | |
1797 | ||
1798 | if (value != 0xb600000000010015ULL) | |
1799 | return false; | |
1800 | ||
1801 | /* Clear MCi_STATUS registers */ | |
1802 | for (i = 0; i < 6; ++i) | |
1803 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1804 | ||
1805 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1806 | if (!err) { | |
1807 | u32 low, high; | |
1808 | ||
1809 | value &= ~(1ULL << 2); | |
1810 | low = lower_32_bits(value); | |
1811 | high = upper_32_bits(value); | |
1812 | ||
1813 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1814 | } | |
1815 | ||
1816 | /* Flush tlb to evict multi-match entries */ | |
1817 | __flush_tlb_all(); | |
1818 | ||
1819 | return true; | |
1820 | } | |
1821 | ||
fe5913e4 | 1822 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1823 | { |
67ec6607 JR |
1824 | if (is_erratum_383()) { |
1825 | /* | |
1826 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1827 | * guest. | |
1828 | */ | |
1829 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1830 | ||
a8eeb04a | 1831 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1832 | |
1833 | return; | |
1834 | } | |
1835 | ||
53371b50 JR |
1836 | /* |
1837 | * On an #MC intercept the MCE handler is not called automatically in | |
1838 | * the host. So do it by hand here. | |
1839 | */ | |
1840 | asm volatile ( | |
1841 | "int $0x12\n"); | |
1842 | /* not sure if we ever come back to this point */ | |
1843 | ||
fe5913e4 JR |
1844 | return; |
1845 | } | |
1846 | ||
1847 | static int mc_interception(struct vcpu_svm *svm) | |
1848 | { | |
53371b50 JR |
1849 | return 1; |
1850 | } | |
1851 | ||
851ba692 | 1852 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1853 | { |
851ba692 AK |
1854 | struct kvm_run *kvm_run = svm->vcpu.run; |
1855 | ||
46fe4ddd JR |
1856 | /* |
1857 | * VMCB is undefined after a SHUTDOWN intercept | |
1858 | * so reinitialize it. | |
1859 | */ | |
a2fa3e9f | 1860 | clear_page(svm->vmcb); |
e6101a96 | 1861 | init_vmcb(svm); |
46fe4ddd JR |
1862 | |
1863 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1864 | return 0; | |
1865 | } | |
1866 | ||
851ba692 | 1867 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1868 | { |
cf8f70bf | 1869 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1870 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1871 | int size, in, string; |
039576c0 | 1872 | unsigned port; |
6aa8b732 | 1873 | |
e756fc62 | 1874 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1875 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1876 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1877 | if (string || in) |
51d8b661 | 1878 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1879 | |
039576c0 AK |
1880 | port = io_info >> 16; |
1881 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1882 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1883 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1884 | |
1885 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1886 | } |
1887 | ||
851ba692 | 1888 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1889 | { |
1890 | return 1; | |
1891 | } | |
1892 | ||
851ba692 | 1893 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1894 | { |
1895 | ++svm->vcpu.stat.irq_exits; | |
1896 | return 1; | |
1897 | } | |
1898 | ||
851ba692 | 1899 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1900 | { |
1901 | return 1; | |
1902 | } | |
1903 | ||
851ba692 | 1904 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1905 | { |
5fdbf976 | 1906 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1907 | skip_emulated_instruction(&svm->vcpu); |
1908 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1909 | } |
1910 | ||
851ba692 | 1911 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1912 | { |
5fdbf976 | 1913 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1914 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1915 | kvm_emulate_hypercall(&svm->vcpu); |
1916 | return 1; | |
02e235bc AK |
1917 | } |
1918 | ||
5bd2edc3 JR |
1919 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1920 | { | |
1921 | struct vcpu_svm *svm = to_svm(vcpu); | |
1922 | ||
1923 | return svm->nested.nested_cr3; | |
1924 | } | |
1925 | ||
e4e517b4 AK |
1926 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
1927 | { | |
1928 | struct vcpu_svm *svm = to_svm(vcpu); | |
1929 | u64 cr3 = svm->nested.nested_cr3; | |
1930 | u64 pdpte; | |
1931 | int ret; | |
1932 | ||
1933 | ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte, | |
1934 | offset_in_page(cr3) + index * 8, 8); | |
1935 | if (ret) | |
1936 | return 0; | |
1937 | return pdpte; | |
1938 | } | |
1939 | ||
5bd2edc3 JR |
1940 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
1941 | unsigned long root) | |
1942 | { | |
1943 | struct vcpu_svm *svm = to_svm(vcpu); | |
1944 | ||
1945 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1946 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1947 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1948 | } |
1949 | ||
6389ee94 AK |
1950 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1951 | struct x86_exception *fault) | |
5bd2edc3 JR |
1952 | { |
1953 | struct vcpu_svm *svm = to_svm(vcpu); | |
1954 | ||
1955 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1956 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1957 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1958 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1959 | |
1960 | nested_svm_vmexit(svm); | |
1961 | } | |
1962 | ||
4b16184c JR |
1963 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1964 | { | |
1965 | int r; | |
1966 | ||
1967 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1968 | ||
1969 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1970 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 1971 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
1972 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
1973 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1974 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1975 | ||
1976 | return r; | |
1977 | } | |
1978 | ||
1979 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1980 | { | |
1981 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1982 | } | |
1983 | ||
c0725420 AG |
1984 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1985 | { | |
f6801dff | 1986 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1987 | || !is_paging(&svm->vcpu)) { |
1988 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1989 | return 1; | |
1990 | } | |
1991 | ||
1992 | if (svm->vmcb->save.cpl) { | |
1993 | kvm_inject_gp(&svm->vcpu, 0); | |
1994 | return 1; | |
1995 | } | |
1996 | ||
1997 | return 0; | |
1998 | } | |
1999 | ||
cf74a78b AG |
2000 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2001 | bool has_error_code, u32 error_code) | |
2002 | { | |
b8e88bc8 JR |
2003 | int vmexit; |
2004 | ||
2030753d | 2005 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2006 | return 0; |
cf74a78b | 2007 | |
0295ad7d JR |
2008 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2009 | svm->vmcb->control.exit_code_hi = 0; | |
2010 | svm->vmcb->control.exit_info_1 = error_code; | |
2011 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
2012 | ||
b8e88bc8 JR |
2013 | vmexit = nested_svm_intercept(svm); |
2014 | if (vmexit == NESTED_EXIT_DONE) | |
2015 | svm->nested.exit_required = true; | |
2016 | ||
2017 | return vmexit; | |
cf74a78b AG |
2018 | } |
2019 | ||
8fe54654 JR |
2020 | /* This function returns true if it is save to enable the irq window */ |
2021 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2022 | { |
2030753d | 2023 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2024 | return true; |
cf74a78b | 2025 | |
26666957 | 2026 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2027 | return true; |
cf74a78b | 2028 | |
26666957 | 2029 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2030 | return false; |
cf74a78b | 2031 | |
a0a07cd2 GN |
2032 | /* |
2033 | * if vmexit was already requested (by intercepted exception | |
2034 | * for instance) do not overwrite it with "external interrupt" | |
2035 | * vmexit. | |
2036 | */ | |
2037 | if (svm->nested.exit_required) | |
2038 | return false; | |
2039 | ||
197717d5 JR |
2040 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2041 | svm->vmcb->control.exit_info_1 = 0; | |
2042 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2043 | |
cd3ff653 JR |
2044 | if (svm->nested.intercept & 1ULL) { |
2045 | /* | |
2046 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2047 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2048 | * #vmexit emulation might sleep. Only signal request for |
2049 | * the #vmexit here. | |
2050 | */ | |
2051 | svm->nested.exit_required = true; | |
236649de | 2052 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2053 | return false; |
cf74a78b AG |
2054 | } |
2055 | ||
8fe54654 | 2056 | return true; |
cf74a78b AG |
2057 | } |
2058 | ||
887f500c JR |
2059 | /* This function returns true if it is save to enable the nmi window */ |
2060 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2061 | { | |
2030753d | 2062 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2063 | return true; |
2064 | ||
2065 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2066 | return true; | |
2067 | ||
2068 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2069 | svm->nested.exit_required = true; | |
2070 | ||
2071 | return false; | |
cf74a78b AG |
2072 | } |
2073 | ||
7597f129 | 2074 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2075 | { |
2076 | struct page *page; | |
2077 | ||
6c3bd3d7 JR |
2078 | might_sleep(); |
2079 | ||
34f80cfa | 2080 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2081 | if (is_error_page(page)) |
2082 | goto error; | |
2083 | ||
7597f129 JR |
2084 | *_page = page; |
2085 | ||
2086 | return kmap(page); | |
34f80cfa JR |
2087 | |
2088 | error: | |
34f80cfa JR |
2089 | kvm_inject_gp(&svm->vcpu, 0); |
2090 | ||
2091 | return NULL; | |
2092 | } | |
2093 | ||
7597f129 | 2094 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2095 | { |
7597f129 | 2096 | kunmap(page); |
34f80cfa JR |
2097 | kvm_release_page_dirty(page); |
2098 | } | |
34f80cfa | 2099 | |
ce2ac085 JR |
2100 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2101 | { | |
2102 | unsigned port; | |
2103 | u8 val, bit; | |
2104 | u64 gpa; | |
34f80cfa | 2105 | |
ce2ac085 JR |
2106 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2107 | return NESTED_EXIT_HOST; | |
34f80cfa | 2108 | |
ce2ac085 JR |
2109 | port = svm->vmcb->control.exit_info_1 >> 16; |
2110 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
2111 | bit = port % 8; | |
2112 | val = 0; | |
2113 | ||
2114 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
2115 | val &= (1 << bit); | |
2116 | ||
2117 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
2118 | } |
2119 | ||
d2477826 | 2120 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2121 | { |
0d6b3537 JR |
2122 | u32 offset, msr, value; |
2123 | int write, mask; | |
4c2161ae | 2124 | |
3d62d9aa | 2125 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2126 | return NESTED_EXIT_HOST; |
3d62d9aa | 2127 | |
0d6b3537 JR |
2128 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2129 | offset = svm_msrpm_offset(msr); | |
2130 | write = svm->vmcb->control.exit_info_1 & 1; | |
2131 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2132 | |
0d6b3537 JR |
2133 | if (offset == MSR_INVALID) |
2134 | return NESTED_EXIT_DONE; | |
4c2161ae | 2135 | |
0d6b3537 JR |
2136 | /* Offset is in 32 bit units but need in 8 bit units */ |
2137 | offset *= 4; | |
4c2161ae | 2138 | |
0d6b3537 JR |
2139 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
2140 | return NESTED_EXIT_DONE; | |
3d62d9aa | 2141 | |
0d6b3537 | 2142 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2143 | } |
2144 | ||
410e4d57 | 2145 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2146 | { |
cf74a78b | 2147 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2148 | |
410e4d57 JR |
2149 | switch (exit_code) { |
2150 | case SVM_EXIT_INTR: | |
2151 | case SVM_EXIT_NMI: | |
ff47a49b | 2152 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2153 | return NESTED_EXIT_HOST; |
410e4d57 | 2154 | case SVM_EXIT_NPF: |
e0231715 | 2155 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2156 | if (npt_enabled) |
2157 | return NESTED_EXIT_HOST; | |
2158 | break; | |
410e4d57 | 2159 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2160 | /* When we're shadowing, trap PFs, but not async PF */ |
2161 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2162 | return NESTED_EXIT_HOST; |
2163 | break; | |
66a562f7 JR |
2164 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2165 | nm_interception(svm); | |
2166 | break; | |
410e4d57 JR |
2167 | default: |
2168 | break; | |
cf74a78b AG |
2169 | } |
2170 | ||
410e4d57 JR |
2171 | return NESTED_EXIT_CONTINUE; |
2172 | } | |
2173 | ||
2174 | /* | |
2175 | * If this function returns true, this #vmexit was already handled | |
2176 | */ | |
b8e88bc8 | 2177 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2178 | { |
2179 | u32 exit_code = svm->vmcb->control.exit_code; | |
2180 | int vmexit = NESTED_EXIT_HOST; | |
2181 | ||
cf74a78b | 2182 | switch (exit_code) { |
9c4e40b9 | 2183 | case SVM_EXIT_MSR: |
3d62d9aa | 2184 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2185 | break; |
ce2ac085 JR |
2186 | case SVM_EXIT_IOIO: |
2187 | vmexit = nested_svm_intercept_ioio(svm); | |
2188 | break; | |
4ee546b4 RJ |
2189 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2190 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2191 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2192 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2193 | break; |
2194 | } | |
3aed041a JR |
2195 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2196 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2197 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2198 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2199 | break; |
2200 | } | |
2201 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2202 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2203 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2204 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2205 | /* async page fault always cause vmexit */ |
2206 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2207 | svm->apf_reason != 0) | |
2208 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2209 | break; |
2210 | } | |
228070b1 JR |
2211 | case SVM_EXIT_ERR: { |
2212 | vmexit = NESTED_EXIT_DONE; | |
2213 | break; | |
2214 | } | |
cf74a78b AG |
2215 | default: { |
2216 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2217 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2218 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2219 | } |
2220 | } | |
2221 | ||
b8e88bc8 JR |
2222 | return vmexit; |
2223 | } | |
2224 | ||
2225 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2226 | { | |
2227 | int vmexit; | |
2228 | ||
2229 | vmexit = nested_svm_intercept(svm); | |
2230 | ||
2231 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2232 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2233 | |
2234 | return vmexit; | |
cf74a78b AG |
2235 | } |
2236 | ||
0460a979 JR |
2237 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2238 | { | |
2239 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2240 | struct vmcb_control_area *from = &from_vmcb->control; | |
2241 | ||
4ee546b4 | 2242 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2243 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2244 | dst->intercept_exceptions = from->intercept_exceptions; |
2245 | dst->intercept = from->intercept; | |
2246 | dst->iopm_base_pa = from->iopm_base_pa; | |
2247 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2248 | dst->tsc_offset = from->tsc_offset; | |
2249 | dst->asid = from->asid; | |
2250 | dst->tlb_ctl = from->tlb_ctl; | |
2251 | dst->int_ctl = from->int_ctl; | |
2252 | dst->int_vector = from->int_vector; | |
2253 | dst->int_state = from->int_state; | |
2254 | dst->exit_code = from->exit_code; | |
2255 | dst->exit_code_hi = from->exit_code_hi; | |
2256 | dst->exit_info_1 = from->exit_info_1; | |
2257 | dst->exit_info_2 = from->exit_info_2; | |
2258 | dst->exit_int_info = from->exit_int_info; | |
2259 | dst->exit_int_info_err = from->exit_int_info_err; | |
2260 | dst->nested_ctl = from->nested_ctl; | |
2261 | dst->event_inj = from->event_inj; | |
2262 | dst->event_inj_err = from->event_inj_err; | |
2263 | dst->nested_cr3 = from->nested_cr3; | |
2264 | dst->lbr_ctl = from->lbr_ctl; | |
2265 | } | |
2266 | ||
34f80cfa | 2267 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2268 | { |
34f80cfa | 2269 | struct vmcb *nested_vmcb; |
e6aa9abd | 2270 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2271 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2272 | struct page *page; |
cf74a78b | 2273 | |
17897f36 JR |
2274 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2275 | vmcb->control.exit_info_1, | |
2276 | vmcb->control.exit_info_2, | |
2277 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2278 | vmcb->control.exit_int_info_err, |
2279 | KVM_ISA_SVM); | |
17897f36 | 2280 | |
7597f129 | 2281 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2282 | if (!nested_vmcb) |
2283 | return 1; | |
2284 | ||
2030753d JR |
2285 | /* Exit Guest-Mode */ |
2286 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2287 | svm->nested.vmcb = 0; |
2288 | ||
cf74a78b | 2289 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2290 | disable_gif(svm); |
2291 | ||
2292 | nested_vmcb->save.es = vmcb->save.es; | |
2293 | nested_vmcb->save.cs = vmcb->save.cs; | |
2294 | nested_vmcb->save.ss = vmcb->save.ss; | |
2295 | nested_vmcb->save.ds = vmcb->save.ds; | |
2296 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2297 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2298 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2299 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2300 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2301 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2302 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2303 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2304 | nested_vmcb->save.rip = vmcb->save.rip; |
2305 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2306 | nested_vmcb->save.rax = vmcb->save.rax; | |
2307 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2308 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2309 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2310 | ||
2311 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2312 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2313 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2314 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2315 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2316 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2317 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2318 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2319 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2320 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2321 | |
2322 | /* | |
2323 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2324 | * to make sure that we do not lose injected events. So check event_inj | |
2325 | * here and copy it to exit_int_info if it is valid. | |
2326 | * Exit_int_info and event_inj can't be both valid because the case | |
2327 | * below only happens on a VMRUN instruction intercept which has | |
2328 | * no valid exit_int_info set. | |
2329 | */ | |
2330 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2331 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2332 | ||
2333 | nc->exit_int_info = vmcb->control.event_inj; | |
2334 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2335 | } | |
2336 | ||
33740e40 JR |
2337 | nested_vmcb->control.tlb_ctl = 0; |
2338 | nested_vmcb->control.event_inj = 0; | |
2339 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2340 | |
2341 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2342 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2343 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2344 | ||
cf74a78b | 2345 | /* Restore the original control entries */ |
0460a979 | 2346 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2347 | |
219b65dc AG |
2348 | kvm_clear_exception_queue(&svm->vcpu); |
2349 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2350 | |
4b16184c JR |
2351 | svm->nested.nested_cr3 = 0; |
2352 | ||
cf74a78b AG |
2353 | /* Restore selected save entries */ |
2354 | svm->vmcb->save.es = hsave->save.es; | |
2355 | svm->vmcb->save.cs = hsave->save.cs; | |
2356 | svm->vmcb->save.ss = hsave->save.ss; | |
2357 | svm->vmcb->save.ds = hsave->save.ds; | |
2358 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2359 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2360 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2361 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2362 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2363 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2364 | if (npt_enabled) { | |
2365 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2366 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2367 | } else { | |
2390218b | 2368 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2369 | } |
2370 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2371 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2372 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2373 | svm->vmcb->save.dr7 = 0; | |
2374 | svm->vmcb->save.cpl = 0; | |
2375 | svm->vmcb->control.exit_int_info = 0; | |
2376 | ||
8d28fec4 RJ |
2377 | mark_all_dirty(svm->vmcb); |
2378 | ||
7597f129 | 2379 | nested_svm_unmap(page); |
cf74a78b | 2380 | |
4b16184c | 2381 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2382 | kvm_mmu_reset_context(&svm->vcpu); |
2383 | kvm_mmu_load(&svm->vcpu); | |
2384 | ||
2385 | return 0; | |
2386 | } | |
3d6368ef | 2387 | |
9738b2c9 | 2388 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2389 | { |
323c3d80 JR |
2390 | /* |
2391 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2392 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2393 | * the kvm msr permission bitmap may contain zero bits |
2394 | */ | |
3d6368ef | 2395 | int i; |
9738b2c9 | 2396 | |
323c3d80 JR |
2397 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2398 | return true; | |
9738b2c9 | 2399 | |
323c3d80 JR |
2400 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2401 | u32 value, p; | |
2402 | u64 offset; | |
9738b2c9 | 2403 | |
323c3d80 JR |
2404 | if (msrpm_offsets[i] == 0xffffffff) |
2405 | break; | |
3d6368ef | 2406 | |
0d6b3537 JR |
2407 | p = msrpm_offsets[i]; |
2408 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2409 | |
2410 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2411 | return false; | |
2412 | ||
2413 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2414 | } | |
3d6368ef | 2415 | |
323c3d80 | 2416 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2417 | |
2418 | return true; | |
3d6368ef AG |
2419 | } |
2420 | ||
52c65a30 JR |
2421 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2422 | { | |
2423 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2424 | return false; | |
2425 | ||
dbe77584 JR |
2426 | if (vmcb->control.asid == 0) |
2427 | return false; | |
2428 | ||
4b16184c JR |
2429 | if (vmcb->control.nested_ctl && !npt_enabled) |
2430 | return false; | |
2431 | ||
52c65a30 JR |
2432 | return true; |
2433 | } | |
2434 | ||
9738b2c9 | 2435 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2436 | { |
9738b2c9 | 2437 | struct vmcb *nested_vmcb; |
e6aa9abd | 2438 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2439 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2440 | struct page *page; |
06fc7772 | 2441 | u64 vmcb_gpa; |
3d6368ef | 2442 | |
06fc7772 | 2443 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2444 | |
7597f129 | 2445 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2446 | if (!nested_vmcb) |
2447 | return false; | |
2448 | ||
52c65a30 JR |
2449 | if (!nested_vmcb_checks(nested_vmcb)) { |
2450 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2451 | nested_vmcb->control.exit_code_hi = 0; | |
2452 | nested_vmcb->control.exit_info_1 = 0; | |
2453 | nested_vmcb->control.exit_info_2 = 0; | |
2454 | ||
2455 | nested_svm_unmap(page); | |
2456 | ||
2457 | return false; | |
2458 | } | |
2459 | ||
b75f4eb3 | 2460 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2461 | nested_vmcb->save.rip, |
2462 | nested_vmcb->control.int_ctl, | |
2463 | nested_vmcb->control.event_inj, | |
2464 | nested_vmcb->control.nested_ctl); | |
2465 | ||
4ee546b4 RJ |
2466 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2467 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2468 | nested_vmcb->control.intercept_exceptions, |
2469 | nested_vmcb->control.intercept); | |
2470 | ||
3d6368ef | 2471 | /* Clear internal status */ |
219b65dc AG |
2472 | kvm_clear_exception_queue(&svm->vcpu); |
2473 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2474 | |
e0231715 JR |
2475 | /* |
2476 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2477 | * restore everything when a VMEXIT occurs | |
2478 | */ | |
defbba56 JR |
2479 | hsave->save.es = vmcb->save.es; |
2480 | hsave->save.cs = vmcb->save.cs; | |
2481 | hsave->save.ss = vmcb->save.ss; | |
2482 | hsave->save.ds = vmcb->save.ds; | |
2483 | hsave->save.gdtr = vmcb->save.gdtr; | |
2484 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2485 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2486 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2487 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2488 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2489 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2490 | hsave->save.rsp = vmcb->save.rsp; |
2491 | hsave->save.rax = vmcb->save.rax; | |
2492 | if (npt_enabled) | |
2493 | hsave->save.cr3 = vmcb->save.cr3; | |
2494 | else | |
9f8fe504 | 2495 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2496 | |
0460a979 | 2497 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2498 | |
f6e78475 | 2499 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2500 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2501 | else | |
2502 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2503 | ||
4b16184c JR |
2504 | if (nested_vmcb->control.nested_ctl) { |
2505 | kvm_mmu_unload(&svm->vcpu); | |
2506 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2507 | nested_svm_init_mmu_context(&svm->vcpu); | |
2508 | } | |
2509 | ||
3d6368ef AG |
2510 | /* Load the nested guest state */ |
2511 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2512 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2513 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2514 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2515 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2516 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2517 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2518 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2519 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2520 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2521 | if (npt_enabled) { | |
2522 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2523 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2524 | } else |
2390218b | 2525 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2526 | |
2527 | /* Guest paging mode is active - reset mmu */ | |
2528 | kvm_mmu_reset_context(&svm->vcpu); | |
2529 | ||
defbba56 | 2530 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2531 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2532 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2533 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2534 | |
3d6368ef AG |
2535 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2536 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2537 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2538 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2539 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2540 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2541 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2542 | ||
f7138538 | 2543 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2544 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2545 | |
aad42c64 | 2546 | /* cache intercepts */ |
4ee546b4 | 2547 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2548 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2549 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2550 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2551 | ||
f40f6a45 | 2552 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2553 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2554 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2555 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2556 | else | |
2557 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2558 | ||
88ab24ad JR |
2559 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2560 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2561 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2562 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2563 | } |
2564 | ||
0d945bd9 | 2565 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2566 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2567 | |
88ab24ad | 2568 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2569 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2570 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2571 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2572 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2573 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2574 | ||
7597f129 | 2575 | nested_svm_unmap(page); |
9738b2c9 | 2576 | |
2030753d JR |
2577 | /* Enter Guest-Mode */ |
2578 | enter_guest_mode(&svm->vcpu); | |
2579 | ||
384c6368 JR |
2580 | /* |
2581 | * Merge guest and host intercepts - must be called with vcpu in | |
2582 | * guest-mode to take affect here | |
2583 | */ | |
2584 | recalc_intercepts(svm); | |
2585 | ||
06fc7772 | 2586 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2587 | |
2af9194d | 2588 | enable_gif(svm); |
3d6368ef | 2589 | |
8d28fec4 RJ |
2590 | mark_all_dirty(svm->vmcb); |
2591 | ||
9738b2c9 | 2592 | return true; |
3d6368ef AG |
2593 | } |
2594 | ||
9966bf68 | 2595 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2596 | { |
2597 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2598 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2599 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2600 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2601 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2602 | to_vmcb->save.star = from_vmcb->save.star; | |
2603 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2604 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2605 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2606 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2607 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2608 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2609 | } |
2610 | ||
851ba692 | 2611 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2612 | { |
9966bf68 | 2613 | struct vmcb *nested_vmcb; |
7597f129 | 2614 | struct page *page; |
9966bf68 | 2615 | |
5542675b AG |
2616 | if (nested_svm_check_permissions(svm)) |
2617 | return 1; | |
2618 | ||
7597f129 | 2619 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2620 | if (!nested_vmcb) |
2621 | return 1; | |
2622 | ||
e3e9ed3d JR |
2623 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2624 | skip_emulated_instruction(&svm->vcpu); | |
2625 | ||
9966bf68 | 2626 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 2627 | nested_svm_unmap(page); |
5542675b AG |
2628 | |
2629 | return 1; | |
2630 | } | |
2631 | ||
851ba692 | 2632 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2633 | { |
9966bf68 | 2634 | struct vmcb *nested_vmcb; |
7597f129 | 2635 | struct page *page; |
9966bf68 | 2636 | |
5542675b AG |
2637 | if (nested_svm_check_permissions(svm)) |
2638 | return 1; | |
2639 | ||
7597f129 | 2640 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2641 | if (!nested_vmcb) |
2642 | return 1; | |
2643 | ||
e3e9ed3d JR |
2644 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2645 | skip_emulated_instruction(&svm->vcpu); | |
2646 | ||
9966bf68 | 2647 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 2648 | nested_svm_unmap(page); |
5542675b AG |
2649 | |
2650 | return 1; | |
2651 | } | |
2652 | ||
851ba692 | 2653 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2654 | { |
3d6368ef AG |
2655 | if (nested_svm_check_permissions(svm)) |
2656 | return 1; | |
2657 | ||
b75f4eb3 RJ |
2658 | /* Save rip after vmrun instruction */ |
2659 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2660 | |
9738b2c9 | 2661 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2662 | return 1; |
2663 | ||
9738b2c9 | 2664 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2665 | goto failed; |
2666 | ||
2667 | return 1; | |
2668 | ||
2669 | failed: | |
2670 | ||
2671 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2672 | svm->vmcb->control.exit_code_hi = 0; | |
2673 | svm->vmcb->control.exit_info_1 = 0; | |
2674 | svm->vmcb->control.exit_info_2 = 0; | |
2675 | ||
2676 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2677 | |
2678 | return 1; | |
2679 | } | |
2680 | ||
851ba692 | 2681 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2682 | { |
2683 | if (nested_svm_check_permissions(svm)) | |
2684 | return 1; | |
2685 | ||
2686 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2687 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2688 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2689 | |
2af9194d | 2690 | enable_gif(svm); |
1371d904 AG |
2691 | |
2692 | return 1; | |
2693 | } | |
2694 | ||
851ba692 | 2695 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2696 | { |
2697 | if (nested_svm_check_permissions(svm)) | |
2698 | return 1; | |
2699 | ||
2700 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2701 | skip_emulated_instruction(&svm->vcpu); | |
2702 | ||
2af9194d | 2703 | disable_gif(svm); |
1371d904 AG |
2704 | |
2705 | /* After a CLGI no interrupts should come */ | |
2706 | svm_clear_vintr(svm); | |
2707 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2708 | ||
decdbf6a JR |
2709 | mark_dirty(svm->vmcb, VMCB_INTR); |
2710 | ||
1371d904 AG |
2711 | return 1; |
2712 | } | |
2713 | ||
851ba692 | 2714 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2715 | { |
2716 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2717 | |
ec1ff790 JR |
2718 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2719 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2720 | ||
ff092385 AG |
2721 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2722 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2723 | ||
2724 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2725 | skip_emulated_instruction(&svm->vcpu); | |
2726 | return 1; | |
2727 | } | |
2728 | ||
532a46b9 JR |
2729 | static int skinit_interception(struct vcpu_svm *svm) |
2730 | { | |
2731 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2732 | ||
2733 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2734 | return 1; | |
2735 | } | |
2736 | ||
81dd35d4 JR |
2737 | static int xsetbv_interception(struct vcpu_svm *svm) |
2738 | { | |
2739 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2740 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2741 | ||
2742 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2743 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2744 | skip_emulated_instruction(&svm->vcpu); | |
2745 | } | |
2746 | ||
2747 | return 1; | |
2748 | } | |
2749 | ||
851ba692 | 2750 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2751 | { |
7ee5d940 | 2752 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2753 | return 1; |
2754 | } | |
2755 | ||
851ba692 | 2756 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2757 | { |
37817f29 | 2758 | u16 tss_selector; |
64a7ec06 GN |
2759 | int reason; |
2760 | int int_type = svm->vmcb->control.exit_int_info & | |
2761 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2762 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2763 | uint32_t type = |
2764 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2765 | uint32_t idt_v = | |
2766 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2767 | bool has_error_code = false; |
2768 | u32 error_code = 0; | |
37817f29 IE |
2769 | |
2770 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2771 | |
37817f29 IE |
2772 | if (svm->vmcb->control.exit_info_2 & |
2773 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2774 | reason = TASK_SWITCH_IRET; |
2775 | else if (svm->vmcb->control.exit_info_2 & | |
2776 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2777 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2778 | else if (idt_v) |
64a7ec06 GN |
2779 | reason = TASK_SWITCH_GATE; |
2780 | else | |
2781 | reason = TASK_SWITCH_CALL; | |
2782 | ||
fe8e7f83 GN |
2783 | if (reason == TASK_SWITCH_GATE) { |
2784 | switch (type) { | |
2785 | case SVM_EXITINTINFO_TYPE_NMI: | |
2786 | svm->vcpu.arch.nmi_injected = false; | |
2787 | break; | |
2788 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2789 | if (svm->vmcb->control.exit_info_2 & |
2790 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2791 | has_error_code = true; | |
2792 | error_code = | |
2793 | (u32)svm->vmcb->control.exit_info_2; | |
2794 | } | |
fe8e7f83 GN |
2795 | kvm_clear_exception_queue(&svm->vcpu); |
2796 | break; | |
2797 | case SVM_EXITINTINFO_TYPE_INTR: | |
2798 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2799 | break; | |
2800 | default: | |
2801 | break; | |
2802 | } | |
2803 | } | |
64a7ec06 | 2804 | |
8317c298 GN |
2805 | if (reason != TASK_SWITCH_GATE || |
2806 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2807 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2808 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2809 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2810 | |
7f3d35fd KW |
2811 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
2812 | int_vec = -1; | |
2813 | ||
2814 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
2815 | has_error_code, error_code) == EMULATE_FAIL) { |
2816 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2817 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2818 | svm->vcpu.run->internal.ndata = 0; | |
2819 | return 0; | |
2820 | } | |
2821 | return 1; | |
6aa8b732 AK |
2822 | } |
2823 | ||
851ba692 | 2824 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2825 | { |
5fdbf976 | 2826 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2827 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2828 | return 1; |
6aa8b732 AK |
2829 | } |
2830 | ||
851ba692 | 2831 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2832 | { |
2833 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2834 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2835 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2836 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
95ba8273 GN |
2837 | return 1; |
2838 | } | |
2839 | ||
851ba692 | 2840 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2841 | { |
df4f3108 AP |
2842 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2843 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2844 | ||
2845 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2846 | skip_emulated_instruction(&svm->vcpu); | |
2847 | return 1; | |
a7052897 MT |
2848 | } |
2849 | ||
851ba692 | 2850 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2851 | { |
51d8b661 | 2852 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2853 | } |
2854 | ||
332b56e4 AK |
2855 | static int rdpmc_interception(struct vcpu_svm *svm) |
2856 | { | |
2857 | int err; | |
2858 | ||
2859 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
2860 | return emulate_on_interception(svm); | |
2861 | ||
2862 | err = kvm_rdpmc(&svm->vcpu); | |
2863 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2864 | ||
2865 | return 1; | |
2866 | } | |
2867 | ||
628afd2a JR |
2868 | bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val) |
2869 | { | |
2870 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
2871 | bool ret = false; | |
2872 | u64 intercept; | |
2873 | ||
2874 | intercept = svm->nested.intercept; | |
2875 | ||
2876 | if (!is_guest_mode(&svm->vcpu) || | |
2877 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
2878 | return false; | |
2879 | ||
2880 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
2881 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
2882 | ||
2883 | if (cr0 ^ val) { | |
2884 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
2885 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
2886 | } | |
2887 | ||
2888 | return ret; | |
2889 | } | |
2890 | ||
7ff76d58 AP |
2891 | #define CR_VALID (1ULL << 63) |
2892 | ||
2893 | static int cr_interception(struct vcpu_svm *svm) | |
2894 | { | |
2895 | int reg, cr; | |
2896 | unsigned long val; | |
2897 | int err; | |
2898 | ||
2899 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2900 | return emulate_on_interception(svm); | |
2901 | ||
2902 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2903 | return emulate_on_interception(svm); | |
2904 | ||
2905 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2906 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2907 | ||
2908 | err = 0; | |
2909 | if (cr >= 16) { /* mov to cr */ | |
2910 | cr -= 16; | |
2911 | val = kvm_register_read(&svm->vcpu, reg); | |
2912 | switch (cr) { | |
2913 | case 0: | |
628afd2a JR |
2914 | if (!check_selective_cr0_intercepted(svm, val)) |
2915 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
2916 | else |
2917 | return 1; | |
2918 | ||
7ff76d58 AP |
2919 | break; |
2920 | case 3: | |
2921 | err = kvm_set_cr3(&svm->vcpu, val); | |
2922 | break; | |
2923 | case 4: | |
2924 | err = kvm_set_cr4(&svm->vcpu, val); | |
2925 | break; | |
2926 | case 8: | |
2927 | err = kvm_set_cr8(&svm->vcpu, val); | |
2928 | break; | |
2929 | default: | |
2930 | WARN(1, "unhandled write to CR%d", cr); | |
2931 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2932 | return 1; | |
2933 | } | |
2934 | } else { /* mov from cr */ | |
2935 | switch (cr) { | |
2936 | case 0: | |
2937 | val = kvm_read_cr0(&svm->vcpu); | |
2938 | break; | |
2939 | case 2: | |
2940 | val = svm->vcpu.arch.cr2; | |
2941 | break; | |
2942 | case 3: | |
9f8fe504 | 2943 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2944 | break; |
2945 | case 4: | |
2946 | val = kvm_read_cr4(&svm->vcpu); | |
2947 | break; | |
2948 | case 8: | |
2949 | val = kvm_get_cr8(&svm->vcpu); | |
2950 | break; | |
2951 | default: | |
2952 | WARN(1, "unhandled read from CR%d", cr); | |
2953 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2954 | return 1; | |
2955 | } | |
2956 | kvm_register_write(&svm->vcpu, reg, val); | |
2957 | } | |
2958 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2959 | ||
2960 | return 1; | |
2961 | } | |
2962 | ||
cae3797a AP |
2963 | static int dr_interception(struct vcpu_svm *svm) |
2964 | { | |
2965 | int reg, dr; | |
2966 | unsigned long val; | |
2967 | int err; | |
2968 | ||
2969 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2970 | return emulate_on_interception(svm); | |
2971 | ||
2972 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2973 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2974 | ||
2975 | if (dr >= 16) { /* mov to DRn */ | |
2976 | val = kvm_register_read(&svm->vcpu, reg); | |
2977 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2978 | } else { | |
2979 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
2980 | if (!err) | |
2981 | kvm_register_write(&svm->vcpu, reg, val); | |
2982 | } | |
2983 | ||
2c46d2ae JR |
2984 | skip_emulated_instruction(&svm->vcpu); |
2985 | ||
cae3797a AP |
2986 | return 1; |
2987 | } | |
2988 | ||
851ba692 | 2989 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2990 | { |
851ba692 | 2991 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2992 | int r; |
851ba692 | 2993 | |
0a5fff19 GN |
2994 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2995 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2996 | r = cr_interception(svm); |
95ba8273 | 2997 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2998 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
7ff76d58 | 2999 | return r; |
95ba8273 | 3000 | } |
0a5fff19 | 3001 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3002 | return r; |
1d075434 JR |
3003 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3004 | return 0; | |
3005 | } | |
3006 | ||
886b470c | 3007 | u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d NHE |
3008 | { |
3009 | struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu)); | |
3010 | return vmcb->control.tsc_offset + | |
886b470c | 3011 | svm_scale_tsc(vcpu, host_tsc); |
d5c1785d NHE |
3012 | } |
3013 | ||
6aa8b732 AK |
3014 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
3015 | { | |
a2fa3e9f GH |
3016 | struct vcpu_svm *svm = to_svm(vcpu); |
3017 | ||
6aa8b732 | 3018 | switch (ecx) { |
af24a4e4 | 3019 | case MSR_IA32_TSC: { |
45133eca | 3020 | *data = svm->vmcb->control.tsc_offset + |
fbc0db76 JR |
3021 | svm_scale_tsc(vcpu, native_read_tsc()); |
3022 | ||
6aa8b732 AK |
3023 | break; |
3024 | } | |
8c06585d | 3025 | case MSR_STAR: |
a2fa3e9f | 3026 | *data = svm->vmcb->save.star; |
6aa8b732 | 3027 | break; |
0e859cac | 3028 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3029 | case MSR_LSTAR: |
a2fa3e9f | 3030 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3031 | break; |
3032 | case MSR_CSTAR: | |
a2fa3e9f | 3033 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3034 | break; |
3035 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3036 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3037 | break; |
3038 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3039 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3040 | break; |
3041 | #endif | |
3042 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3043 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3044 | break; |
3045 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3046 | *data = svm->sysenter_eip; |
6aa8b732 AK |
3047 | break; |
3048 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3049 | *data = svm->sysenter_esp; |
6aa8b732 | 3050 | break; |
e0231715 JR |
3051 | /* |
3052 | * Nobody will change the following 5 values in the VMCB so we can | |
3053 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3054 | * implemented. | |
3055 | */ | |
a2938c80 JR |
3056 | case MSR_IA32_DEBUGCTLMSR: |
3057 | *data = svm->vmcb->save.dbgctl; | |
3058 | break; | |
3059 | case MSR_IA32_LASTBRANCHFROMIP: | |
3060 | *data = svm->vmcb->save.br_from; | |
3061 | break; | |
3062 | case MSR_IA32_LASTBRANCHTOIP: | |
3063 | *data = svm->vmcb->save.br_to; | |
3064 | break; | |
3065 | case MSR_IA32_LASTINTFROMIP: | |
3066 | *data = svm->vmcb->save.last_excp_from; | |
3067 | break; | |
3068 | case MSR_IA32_LASTINTTOIP: | |
3069 | *data = svm->vmcb->save.last_excp_to; | |
3070 | break; | |
b286d5d8 | 3071 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3072 | *data = svm->nested.hsave_msr; |
b286d5d8 | 3073 | break; |
eb6f302e | 3074 | case MSR_VM_CR: |
4a810181 | 3075 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 3076 | break; |
c8a73f18 AG |
3077 | case MSR_IA32_UCODE_REV: |
3078 | *data = 0x01000065; | |
3079 | break; | |
6aa8b732 | 3080 | default: |
3bab1f5d | 3081 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
3082 | } |
3083 | return 0; | |
3084 | } | |
3085 | ||
851ba692 | 3086 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3087 | { |
ad312c7c | 3088 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3089 | u64 data; |
3090 | ||
59200273 AK |
3091 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
3092 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 3093 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3094 | } else { |
229456fc | 3095 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 3096 | |
5fdbf976 | 3097 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 3098 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 3099 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3100 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3101 | } |
3102 | return 1; | |
3103 | } | |
3104 | ||
4a810181 JR |
3105 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3106 | { | |
3107 | struct vcpu_svm *svm = to_svm(vcpu); | |
3108 | int svm_dis, chg_mask; | |
3109 | ||
3110 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3111 | return 1; | |
3112 | ||
3113 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3114 | ||
3115 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3116 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3117 | ||
3118 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3119 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3120 | ||
3121 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3122 | ||
3123 | /* check for svm_disable while efer.svme is set */ | |
3124 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3125 | return 1; | |
3126 | ||
3127 | return 0; | |
3128 | } | |
3129 | ||
8fe8ab46 | 3130 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3131 | { |
a2fa3e9f GH |
3132 | struct vcpu_svm *svm = to_svm(vcpu); |
3133 | ||
8fe8ab46 WA |
3134 | u32 ecx = msr->index; |
3135 | u64 data = msr->data; | |
6aa8b732 | 3136 | switch (ecx) { |
f4e1b3c8 | 3137 | case MSR_IA32_TSC: |
8fe8ab46 | 3138 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3139 | break; |
8c06585d | 3140 | case MSR_STAR: |
a2fa3e9f | 3141 | svm->vmcb->save.star = data; |
6aa8b732 | 3142 | break; |
49b14f24 | 3143 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3144 | case MSR_LSTAR: |
a2fa3e9f | 3145 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3146 | break; |
3147 | case MSR_CSTAR: | |
a2fa3e9f | 3148 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3149 | break; |
3150 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3151 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3152 | break; |
3153 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3154 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3155 | break; |
3156 | #endif | |
3157 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3158 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3159 | break; |
3160 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3161 | svm->sysenter_eip = data; |
a2fa3e9f | 3162 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3163 | break; |
3164 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3165 | svm->sysenter_esp = data; |
a2fa3e9f | 3166 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3167 | break; |
a2938c80 | 3168 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3169 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3170 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3171 | __func__, data); | |
24e09cbf JR |
3172 | break; |
3173 | } | |
3174 | if (data & DEBUGCTL_RESERVED_BITS) | |
3175 | return 1; | |
3176 | ||
3177 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3178 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3179 | if (data & (1ULL<<0)) |
3180 | svm_enable_lbrv(svm); | |
3181 | else | |
3182 | svm_disable_lbrv(svm); | |
a2938c80 | 3183 | break; |
b286d5d8 | 3184 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3185 | svm->nested.hsave_msr = data; |
62b9abaa | 3186 | break; |
3c5d0a44 | 3187 | case MSR_VM_CR: |
4a810181 | 3188 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3189 | case MSR_VM_IGNNE: |
a737f256 | 3190 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3191 | break; |
6aa8b732 | 3192 | default: |
8fe8ab46 | 3193 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3194 | } |
3195 | return 0; | |
3196 | } | |
3197 | ||
851ba692 | 3198 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3199 | { |
8fe8ab46 | 3200 | struct msr_data msr; |
ad312c7c | 3201 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 3202 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 3203 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 3204 | |
8fe8ab46 WA |
3205 | msr.data = data; |
3206 | msr.index = ecx; | |
3207 | msr.host_initiated = false; | |
af9ca2d7 | 3208 | |
5fdbf976 | 3209 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
8fe8ab46 | 3210 | if (svm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3211 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3212 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3213 | } else { |
3214 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3215 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3216 | } |
6aa8b732 AK |
3217 | return 1; |
3218 | } | |
3219 | ||
851ba692 | 3220 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3221 | { |
e756fc62 | 3222 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3223 | return wrmsr_interception(svm); |
6aa8b732 | 3224 | else |
851ba692 | 3225 | return rdmsr_interception(svm); |
6aa8b732 AK |
3226 | } |
3227 | ||
851ba692 | 3228 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3229 | { |
851ba692 AK |
3230 | struct kvm_run *kvm_run = svm->vcpu.run; |
3231 | ||
3842d135 | 3232 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3233 | svm_clear_vintr(svm); |
85f455f7 | 3234 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3235 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3236 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3237 | /* |
3238 | * If the user space waits to inject interrupts, exit as soon as | |
3239 | * possible | |
3240 | */ | |
8061823a GN |
3241 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3242 | kvm_run->request_interrupt_window && | |
3243 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
c1150d8c DL |
3244 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3245 | return 0; | |
3246 | } | |
3247 | ||
3248 | return 1; | |
3249 | } | |
3250 | ||
565d0998 ML |
3251 | static int pause_interception(struct vcpu_svm *svm) |
3252 | { | |
3253 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3254 | return 1; | |
3255 | } | |
3256 | ||
09941fbb | 3257 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3258 | [SVM_EXIT_READ_CR0] = cr_interception, |
3259 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3260 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3261 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3262 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
628afd2a | 3263 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3264 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3265 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3266 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3267 | [SVM_EXIT_READ_DR0] = dr_interception, |
3268 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3269 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3270 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3271 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3272 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3273 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3274 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3275 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3276 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3277 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3278 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3279 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3280 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3281 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3282 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3283 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3284 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3285 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3286 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3287 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3288 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3289 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3290 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3291 | [SVM_EXIT_SMI] = nop_on_interception, |
3292 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3293 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 3294 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 3295 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3296 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3297 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3298 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3299 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3300 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3301 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3302 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3303 | [SVM_EXIT_MSR] = msr_interception, |
3304 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3305 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3306 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3307 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3308 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3309 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3310 | [SVM_EXIT_STGI] = stgi_interception, |
3311 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3312 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3313 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
3314 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
3315 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
81dd35d4 | 3316 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3317 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3318 | }; |
3319 | ||
ae8cc059 | 3320 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
3321 | { |
3322 | struct vcpu_svm *svm = to_svm(vcpu); | |
3323 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3324 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3325 | ||
3326 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
3327 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
3328 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
3329 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
3330 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
3331 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
3332 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
3333 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
3334 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
3335 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
3336 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
3337 | pr_err("%-20s%d\n", "asid:", control->asid); | |
3338 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
3339 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
3340 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
3341 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
3342 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
3343 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
3344 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
3345 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
3346 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
3347 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
3348 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
3349 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); | |
3350 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
3351 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
3352 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
3f10c846 | 3353 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
3354 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
3355 | "es:", | |
3356 | save->es.selector, save->es.attrib, | |
3357 | save->es.limit, save->es.base); | |
3358 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3359 | "cs:", | |
3360 | save->cs.selector, save->cs.attrib, | |
3361 | save->cs.limit, save->cs.base); | |
3362 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3363 | "ss:", | |
3364 | save->ss.selector, save->ss.attrib, | |
3365 | save->ss.limit, save->ss.base); | |
3366 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3367 | "ds:", | |
3368 | save->ds.selector, save->ds.attrib, | |
3369 | save->ds.limit, save->ds.base); | |
3370 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3371 | "fs:", | |
3372 | save->fs.selector, save->fs.attrib, | |
3373 | save->fs.limit, save->fs.base); | |
3374 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3375 | "gs:", | |
3376 | save->gs.selector, save->gs.attrib, | |
3377 | save->gs.limit, save->gs.base); | |
3378 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3379 | "gdtr:", | |
3380 | save->gdtr.selector, save->gdtr.attrib, | |
3381 | save->gdtr.limit, save->gdtr.base); | |
3382 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3383 | "ldtr:", | |
3384 | save->ldtr.selector, save->ldtr.attrib, | |
3385 | save->ldtr.limit, save->ldtr.base); | |
3386 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3387 | "idtr:", | |
3388 | save->idtr.selector, save->idtr.attrib, | |
3389 | save->idtr.limit, save->idtr.base); | |
3390 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3391 | "tr:", | |
3392 | save->tr.selector, save->tr.attrib, | |
3393 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
3394 | pr_err("cpl: %d efer: %016llx\n", |
3395 | save->cpl, save->efer); | |
ae8cc059 JP |
3396 | pr_err("%-15s %016llx %-13s %016llx\n", |
3397 | "cr0:", save->cr0, "cr2:", save->cr2); | |
3398 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3399 | "cr3:", save->cr3, "cr4:", save->cr4); | |
3400 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3401 | "dr6:", save->dr6, "dr7:", save->dr7); | |
3402 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3403 | "rip:", save->rip, "rflags:", save->rflags); | |
3404 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3405 | "rsp:", save->rsp, "rax:", save->rax); | |
3406 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3407 | "star:", save->star, "lstar:", save->lstar); | |
3408 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3409 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
3410 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3411 | "kernel_gs_base:", save->kernel_gs_base, | |
3412 | "sysenter_cs:", save->sysenter_cs); | |
3413 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3414 | "sysenter_esp:", save->sysenter_esp, | |
3415 | "sysenter_eip:", save->sysenter_eip); | |
3416 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3417 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
3418 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3419 | "br_from:", save->br_from, "br_to:", save->br_to); | |
3420 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3421 | "excp_from:", save->last_excp_from, | |
3422 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
3423 | } |
3424 | ||
586f9607 AK |
3425 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3426 | { | |
3427 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3428 | ||
3429 | *info1 = control->exit_info_1; | |
3430 | *info2 = control->exit_info_2; | |
3431 | } | |
3432 | ||
851ba692 | 3433 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3434 | { |
04d2cc77 | 3435 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3436 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3437 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3438 | |
4ee546b4 | 3439 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3440 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3441 | if (npt_enabled) | |
3442 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3443 | |
cd3ff653 JR |
3444 | if (unlikely(svm->nested.exit_required)) { |
3445 | nested_svm_vmexit(svm); | |
3446 | svm->nested.exit_required = false; | |
3447 | ||
3448 | return 1; | |
3449 | } | |
3450 | ||
2030753d | 3451 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3452 | int vmexit; |
3453 | ||
d8cabddf JR |
3454 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3455 | svm->vmcb->control.exit_info_1, | |
3456 | svm->vmcb->control.exit_info_2, | |
3457 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
3458 | svm->vmcb->control.exit_int_info_err, |
3459 | KVM_ISA_SVM); | |
d8cabddf | 3460 | |
410e4d57 JR |
3461 | vmexit = nested_svm_exit_special(svm); |
3462 | ||
3463 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3464 | vmexit = nested_svm_exit_handled(svm); | |
3465 | ||
3466 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3467 | return 1; |
cf74a78b AG |
3468 | } |
3469 | ||
a5c3832d JR |
3470 | svm_complete_interrupts(svm); |
3471 | ||
04d2cc77 AK |
3472 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3473 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3474 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3475 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3476 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3477 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3478 | return 0; |
3479 | } | |
3480 | ||
a2fa3e9f | 3481 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3482 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3483 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3484 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3485 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3486 | "exit_code 0x%x\n", | |
b8688d51 | 3487 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3488 | exit_code); |
3489 | ||
9d8f549d | 3490 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3491 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3492 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3493 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3494 | return 0; |
3495 | } | |
3496 | ||
851ba692 | 3497 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3498 | } |
3499 | ||
3500 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3501 | { | |
3502 | int cpu = raw_smp_processor_id(); | |
3503 | ||
0fe1e009 TH |
3504 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3505 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3506 | load_TR_desc(); |
3507 | } | |
3508 | ||
e756fc62 | 3509 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3510 | { |
3511 | int cpu = raw_smp_processor_id(); | |
3512 | ||
0fe1e009 | 3513 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3514 | |
4b656b12 | 3515 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3516 | if (svm->asid_generation != sd->asid_generation) |
3517 | new_asid(svm, sd); | |
6aa8b732 AK |
3518 | } |
3519 | ||
95ba8273 GN |
3520 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3521 | { | |
3522 | struct vcpu_svm *svm = to_svm(vcpu); | |
3523 | ||
3524 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3525 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3526 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3527 | ++vcpu->stat.nmi_injections; |
3528 | } | |
6aa8b732 | 3529 | |
85f455f7 | 3530 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3531 | { |
3532 | struct vmcb_control_area *control; | |
3533 | ||
e756fc62 | 3534 | control = &svm->vmcb->control; |
85f455f7 | 3535 | control->int_vector = irq; |
6aa8b732 AK |
3536 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3537 | control->int_ctl |= V_IRQ_MASK | | |
3538 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3539 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3540 | } |
3541 | ||
66fd3f7f | 3542 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3543 | { |
3544 | struct vcpu_svm *svm = to_svm(vcpu); | |
3545 | ||
2af9194d | 3546 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3547 | |
9fb2d2b4 GN |
3548 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3549 | ++vcpu->stat.irq_injections; | |
3550 | ||
219b65dc AG |
3551 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3552 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3553 | } |
3554 | ||
95ba8273 | 3555 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3556 | { |
3557 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3558 | |
2030753d | 3559 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3560 | return; |
3561 | ||
95ba8273 | 3562 | if (irr == -1) |
aaacfc9a JR |
3563 | return; |
3564 | ||
95ba8273 | 3565 | if (tpr >= irr) |
4ee546b4 | 3566 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3567 | } |
aaacfc9a | 3568 | |
95ba8273 GN |
3569 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3570 | { | |
3571 | struct vcpu_svm *svm = to_svm(vcpu); | |
3572 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3573 | int ret; |
3574 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3575 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3576 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3577 | ||
3578 | return ret; | |
aaacfc9a JR |
3579 | } |
3580 | ||
3cfc3092 JK |
3581 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3582 | { | |
3583 | struct vcpu_svm *svm = to_svm(vcpu); | |
3584 | ||
3585 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3586 | } | |
3587 | ||
3588 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3589 | { | |
3590 | struct vcpu_svm *svm = to_svm(vcpu); | |
3591 | ||
3592 | if (masked) { | |
3593 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3594 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3595 | } else { |
3596 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3597 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3598 | } |
3599 | } | |
3600 | ||
78646121 GN |
3601 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3602 | { | |
3603 | struct vcpu_svm *svm = to_svm(vcpu); | |
3604 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3605 | int ret; |
3606 | ||
3607 | if (!gif_set(svm) || | |
3608 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3609 | return 0; | |
3610 | ||
f6e78475 | 3611 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3612 | |
2030753d | 3613 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3614 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3615 | ||
3616 | return ret; | |
78646121 GN |
3617 | } |
3618 | ||
9222be18 | 3619 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3620 | { |
219b65dc | 3621 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3622 | |
e0231715 JR |
3623 | /* |
3624 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3625 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3626 | * get that intercept, this function will be called again though and | |
3627 | * we'll get the vintr intercept. | |
3628 | */ | |
8fe54654 | 3629 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3630 | svm_set_vintr(svm); |
3631 | svm_inject_irq(svm, 0x0); | |
3632 | } | |
85f455f7 ED |
3633 | } |
3634 | ||
95ba8273 | 3635 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3636 | { |
04d2cc77 | 3637 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3638 | |
44c11430 GN |
3639 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3640 | == HF_NMI_MASK) | |
3641 | return; /* IRET will cause a vm exit */ | |
3642 | ||
e0231715 JR |
3643 | /* |
3644 | * Something prevents NMI from been injected. Single step over possible | |
3645 | * problem (IRET or exception injection or interrupt shadow) | |
3646 | */ | |
6be7d306 | 3647 | svm->nmi_singlestep = true; |
44c11430 | 3648 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c8639010 | 3649 | update_db_bp_intercept(vcpu); |
c1150d8c DL |
3650 | } |
3651 | ||
cbc94022 IE |
3652 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3653 | { | |
3654 | return 0; | |
3655 | } | |
3656 | ||
d9e368d6 AK |
3657 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3658 | { | |
38e5e92f JR |
3659 | struct vcpu_svm *svm = to_svm(vcpu); |
3660 | ||
3661 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3662 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3663 | else | |
3664 | svm->asid_generation--; | |
d9e368d6 AK |
3665 | } |
3666 | ||
04d2cc77 AK |
3667 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3668 | { | |
3669 | } | |
3670 | ||
d7bf8221 JR |
3671 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3672 | { | |
3673 | struct vcpu_svm *svm = to_svm(vcpu); | |
3674 | ||
2030753d | 3675 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3676 | return; |
3677 | ||
4ee546b4 | 3678 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3679 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3680 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3681 | } |
3682 | } | |
3683 | ||
649d6864 JR |
3684 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3685 | { | |
3686 | struct vcpu_svm *svm = to_svm(vcpu); | |
3687 | u64 cr8; | |
3688 | ||
2030753d | 3689 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3690 | return; |
3691 | ||
649d6864 JR |
3692 | cr8 = kvm_get_cr8(vcpu); |
3693 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3694 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3695 | } | |
3696 | ||
9222be18 GN |
3697 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3698 | { | |
3699 | u8 vector; | |
3700 | int type; | |
3701 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3702 | unsigned int3_injected = svm->int3_injected; |
3703 | ||
3704 | svm->int3_injected = 0; | |
9222be18 | 3705 | |
bd3d1ec3 AK |
3706 | /* |
3707 | * If we've made progress since setting HF_IRET_MASK, we've | |
3708 | * executed an IRET and can allow NMI injection. | |
3709 | */ | |
3710 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3711 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3712 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3713 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3714 | } | |
44c11430 | 3715 | |
9222be18 GN |
3716 | svm->vcpu.arch.nmi_injected = false; |
3717 | kvm_clear_exception_queue(&svm->vcpu); | |
3718 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3719 | ||
3720 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3721 | return; | |
3722 | ||
3842d135 AK |
3723 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3724 | ||
9222be18 GN |
3725 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3726 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3727 | ||
3728 | switch (type) { | |
3729 | case SVM_EXITINTINFO_TYPE_NMI: | |
3730 | svm->vcpu.arch.nmi_injected = true; | |
3731 | break; | |
3732 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3733 | /* |
3734 | * In case of software exceptions, do not reinject the vector, | |
3735 | * but re-execute the instruction instead. Rewind RIP first | |
3736 | * if we emulated INT3 before. | |
3737 | */ | |
3738 | if (kvm_exception_is_soft(vector)) { | |
3739 | if (vector == BP_VECTOR && int3_injected && | |
3740 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3741 | kvm_rip_write(&svm->vcpu, | |
3742 | kvm_rip_read(&svm->vcpu) - | |
3743 | int3_injected); | |
9222be18 | 3744 | break; |
66b7138f | 3745 | } |
9222be18 GN |
3746 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3747 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3748 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3749 | |
3750 | } else | |
ce7ddec4 | 3751 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3752 | break; |
3753 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3754 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3755 | break; |
3756 | default: | |
3757 | break; | |
3758 | } | |
3759 | } | |
3760 | ||
b463a6f7 AK |
3761 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3762 | { | |
3763 | struct vcpu_svm *svm = to_svm(vcpu); | |
3764 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3765 | ||
3766 | control->exit_int_info = control->event_inj; | |
3767 | control->exit_int_info_err = control->event_inj_err; | |
3768 | control->event_inj = 0; | |
3769 | svm_complete_interrupts(svm); | |
3770 | } | |
3771 | ||
851ba692 | 3772 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3773 | { |
a2fa3e9f | 3774 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3775 | |
2041a06a JR |
3776 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3777 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3778 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3779 | ||
cd3ff653 JR |
3780 | /* |
3781 | * A vmexit emulation is required before the vcpu can be executed | |
3782 | * again. | |
3783 | */ | |
3784 | if (unlikely(svm->nested.exit_required)) | |
3785 | return; | |
3786 | ||
e756fc62 | 3787 | pre_svm_run(svm); |
6aa8b732 | 3788 | |
649d6864 JR |
3789 | sync_lapic_to_cr8(vcpu); |
3790 | ||
cda0ffdd | 3791 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3792 | |
04d2cc77 AK |
3793 | clgi(); |
3794 | ||
3795 | local_irq_enable(); | |
36241b8c | 3796 | |
6aa8b732 | 3797 | asm volatile ( |
7454766f AK |
3798 | "push %%" _ASM_BP "; \n\t" |
3799 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
3800 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
3801 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
3802 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
3803 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
3804 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 3805 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3806 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3807 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3808 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3809 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3810 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3811 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3812 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3813 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3814 | #endif |
3815 | ||
6aa8b732 | 3816 | /* Enter guest mode */ |
7454766f AK |
3817 | "push %%" _ASM_AX " \n\t" |
3818 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
3819 | __ex(SVM_VMLOAD) "\n\t" |
3820 | __ex(SVM_VMRUN) "\n\t" | |
3821 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 3822 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
3823 | |
3824 | /* Save guest registers, load host registers */ | |
7454766f AK |
3825 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
3826 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
3827 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
3828 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
3829 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
3830 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3831 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3832 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3833 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3834 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3835 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3836 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3837 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3838 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3839 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3840 | #endif |
7454766f | 3841 | "pop %%" _ASM_BP |
6aa8b732 | 3842 | : |
fb3f0f51 | 3843 | : [svm]"a"(svm), |
6aa8b732 | 3844 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3845 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3846 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3847 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3848 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3849 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3850 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3851 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3852 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3853 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3854 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3855 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3856 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3857 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3858 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3859 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3860 | #endif |
54a08c04 LV |
3861 | : "cc", "memory" |
3862 | #ifdef CONFIG_X86_64 | |
7454766f | 3863 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 3864 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
3865 | #else |
3866 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
3867 | #endif |
3868 | ); | |
6aa8b732 | 3869 | |
82ca2d10 AK |
3870 | #ifdef CONFIG_X86_64 |
3871 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3872 | #else | |
dacccfdd | 3873 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3874 | #ifndef CONFIG_X86_32_LAZY_GS |
3875 | loadsegment(gs, svm->host.gs); | |
3876 | #endif | |
9581d442 | 3877 | #endif |
6aa8b732 AK |
3878 | |
3879 | reload_tss(vcpu); | |
3880 | ||
56ba47dd AK |
3881 | local_irq_disable(); |
3882 | ||
13c34e07 AK |
3883 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3884 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3885 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3886 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3887 | ||
1e2b1dd7 JK |
3888 | trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM); |
3889 | ||
3781c01c JR |
3890 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3891 | kvm_before_handle_nmi(&svm->vcpu); | |
3892 | ||
3893 | stgi(); | |
3894 | ||
3895 | /* Any pending NMI will happen here */ | |
3896 | ||
3897 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3898 | kvm_after_handle_nmi(&svm->vcpu); | |
3899 | ||
d7bf8221 JR |
3900 | sync_cr8_to_lapic(vcpu); |
3901 | ||
a2fa3e9f | 3902 | svm->next_rip = 0; |
9222be18 | 3903 | |
38e5e92f JR |
3904 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3905 | ||
631bc487 GN |
3906 | /* if exit due to PF check for async PF */ |
3907 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3908 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3909 | ||
6de4f3ad AK |
3910 | if (npt_enabled) { |
3911 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3912 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3913 | } | |
fe5913e4 JR |
3914 | |
3915 | /* | |
3916 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3917 | * change the physical cpu | |
3918 | */ | |
3919 | if (unlikely(svm->vmcb->control.exit_code == | |
3920 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3921 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3922 | |
3923 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3924 | } |
3925 | ||
6aa8b732 AK |
3926 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3927 | { | |
a2fa3e9f GH |
3928 | struct vcpu_svm *svm = to_svm(vcpu); |
3929 | ||
3930 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3931 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3932 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3933 | } |
3934 | ||
1c97f0a0 JR |
3935 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3936 | { | |
3937 | struct vcpu_svm *svm = to_svm(vcpu); | |
3938 | ||
3939 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3940 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3941 | |
3942 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3943 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3944 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3945 | |
f40f6a45 | 3946 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3947 | } |
3948 | ||
6aa8b732 AK |
3949 | static int is_disabled(void) |
3950 | { | |
6031a61c JR |
3951 | u64 vm_cr; |
3952 | ||
3953 | rdmsrl(MSR_VM_CR, vm_cr); | |
3954 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3955 | return 1; | |
3956 | ||
6aa8b732 AK |
3957 | return 0; |
3958 | } | |
3959 | ||
102d8325 IM |
3960 | static void |
3961 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3962 | { | |
3963 | /* | |
3964 | * Patch in the VMMCALL instruction: | |
3965 | */ | |
3966 | hypercall[0] = 0x0f; | |
3967 | hypercall[1] = 0x01; | |
3968 | hypercall[2] = 0xd9; | |
102d8325 IM |
3969 | } |
3970 | ||
002c7f7c YS |
3971 | static void svm_check_processor_compat(void *rtn) |
3972 | { | |
3973 | *(int *)rtn = 0; | |
3974 | } | |
3975 | ||
774ead3a AK |
3976 | static bool svm_cpu_has_accelerated_tpr(void) |
3977 | { | |
3978 | return false; | |
3979 | } | |
3980 | ||
4b12f0de | 3981 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3982 | { |
3983 | return 0; | |
3984 | } | |
3985 | ||
0e851880 SY |
3986 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3987 | { | |
3988 | } | |
3989 | ||
d4330ef2 JR |
3990 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3991 | { | |
c2c63a49 | 3992 | switch (func) { |
4c62a2dc JR |
3993 | case 0x80000001: |
3994 | if (nested) | |
3995 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3996 | break; | |
c2c63a49 JR |
3997 | case 0x8000000A: |
3998 | entry->eax = 1; /* SVM revision 1 */ | |
3999 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
4000 | ASID emulation to nested SVM */ | |
4001 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
4002 | entry->edx = 0; /* Per default do not support any |
4003 | additional features */ | |
4004 | ||
4005 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 4006 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 4007 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 4008 | |
3d4aeaad JR |
4009 | /* Support NPT for the guest if enabled */ |
4010 | if (npt_enabled) | |
4011 | entry->edx |= SVM_FEATURE_NPT; | |
4012 | ||
c2c63a49 JR |
4013 | break; |
4014 | } | |
d4330ef2 JR |
4015 | } |
4016 | ||
17cc3935 | 4017 | static int svm_get_lpage_level(void) |
344f414f | 4018 | { |
17cc3935 | 4019 | return PT_PDPE_LEVEL; |
344f414f JR |
4020 | } |
4021 | ||
4e47c7a6 SY |
4022 | static bool svm_rdtscp_supported(void) |
4023 | { | |
4024 | return false; | |
4025 | } | |
4026 | ||
ad756a16 MJ |
4027 | static bool svm_invpcid_supported(void) |
4028 | { | |
4029 | return false; | |
4030 | } | |
4031 | ||
f5f48ee1 SY |
4032 | static bool svm_has_wbinvd_exit(void) |
4033 | { | |
4034 | return true; | |
4035 | } | |
4036 | ||
02daab21 AK |
4037 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
4038 | { | |
4039 | struct vcpu_svm *svm = to_svm(vcpu); | |
4040 | ||
18c918c5 | 4041 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 4042 | update_cr0_intercept(svm); |
02daab21 AK |
4043 | } |
4044 | ||
8061252e | 4045 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4046 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 4047 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4048 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 4049 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 4050 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 4051 | |
09941fbb | 4052 | static const struct __x86_intercept { |
cfec82cb JR |
4053 | u32 exit_code; |
4054 | enum x86_intercept_stage stage; | |
cfec82cb JR |
4055 | } x86_intercept_map[] = { |
4056 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
4057 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4058 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4059 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4060 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
4061 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
4062 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
4063 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
4064 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
4065 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
4066 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
4067 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
4068 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
4069 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
4070 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
4071 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
4072 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
4073 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
4074 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
4075 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
4076 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
4077 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
4078 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
4079 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
4080 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
4081 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
4082 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
4083 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
4084 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
4085 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
4086 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
4087 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
4088 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
4089 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
4090 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
4091 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
4092 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
4093 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
4094 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
4095 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
4096 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
4097 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
4098 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
4099 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
4100 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
4101 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
4102 | }; |
4103 | ||
8061252e | 4104 | #undef PRE_EX |
cfec82cb | 4105 | #undef POST_EX |
d7eb8203 | 4106 | #undef POST_MEM |
cfec82cb | 4107 | |
8a76d7f2 JR |
4108 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
4109 | struct x86_instruction_info *info, | |
4110 | enum x86_intercept_stage stage) | |
4111 | { | |
cfec82cb JR |
4112 | struct vcpu_svm *svm = to_svm(vcpu); |
4113 | int vmexit, ret = X86EMUL_CONTINUE; | |
4114 | struct __x86_intercept icpt_info; | |
4115 | struct vmcb *vmcb = svm->vmcb; | |
4116 | ||
4117 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
4118 | goto out; | |
4119 | ||
4120 | icpt_info = x86_intercept_map[info->intercept]; | |
4121 | ||
40e19b51 | 4122 | if (stage != icpt_info.stage) |
cfec82cb JR |
4123 | goto out; |
4124 | ||
4125 | switch (icpt_info.exit_code) { | |
4126 | case SVM_EXIT_READ_CR0: | |
4127 | if (info->intercept == x86_intercept_cr_read) | |
4128 | icpt_info.exit_code += info->modrm_reg; | |
4129 | break; | |
4130 | case SVM_EXIT_WRITE_CR0: { | |
4131 | unsigned long cr0, val; | |
4132 | u64 intercept; | |
4133 | ||
4134 | if (info->intercept == x86_intercept_cr_write) | |
4135 | icpt_info.exit_code += info->modrm_reg; | |
4136 | ||
4137 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0) | |
4138 | break; | |
4139 | ||
4140 | intercept = svm->nested.intercept; | |
4141 | ||
4142 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
4143 | break; | |
4144 | ||
4145 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4146 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4147 | ||
4148 | if (info->intercept == x86_intercept_lmsw) { | |
4149 | cr0 &= 0xfUL; | |
4150 | val &= 0xfUL; | |
4151 | /* lmsw can't clear PE - catch this here */ | |
4152 | if (cr0 & X86_CR0_PE) | |
4153 | val |= X86_CR0_PE; | |
4154 | } | |
4155 | ||
4156 | if (cr0 ^ val) | |
4157 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4158 | ||
4159 | break; | |
4160 | } | |
3b88e41a JR |
4161 | case SVM_EXIT_READ_DR0: |
4162 | case SVM_EXIT_WRITE_DR0: | |
4163 | icpt_info.exit_code += info->modrm_reg; | |
4164 | break; | |
8061252e JR |
4165 | case SVM_EXIT_MSR: |
4166 | if (info->intercept == x86_intercept_wrmsr) | |
4167 | vmcb->control.exit_info_1 = 1; | |
4168 | else | |
4169 | vmcb->control.exit_info_1 = 0; | |
4170 | break; | |
bf608f88 JR |
4171 | case SVM_EXIT_PAUSE: |
4172 | /* | |
4173 | * We get this for NOP only, but pause | |
4174 | * is rep not, check this here | |
4175 | */ | |
4176 | if (info->rep_prefix != REPE_PREFIX) | |
4177 | goto out; | |
f6511935 JR |
4178 | case SVM_EXIT_IOIO: { |
4179 | u64 exit_info; | |
4180 | u32 bytes; | |
4181 | ||
4182 | exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16; | |
4183 | ||
4184 | if (info->intercept == x86_intercept_in || | |
4185 | info->intercept == x86_intercept_ins) { | |
4186 | exit_info |= SVM_IOIO_TYPE_MASK; | |
4187 | bytes = info->src_bytes; | |
4188 | } else { | |
4189 | bytes = info->dst_bytes; | |
4190 | } | |
4191 | ||
4192 | if (info->intercept == x86_intercept_outs || | |
4193 | info->intercept == x86_intercept_ins) | |
4194 | exit_info |= SVM_IOIO_STR_MASK; | |
4195 | ||
4196 | if (info->rep_prefix) | |
4197 | exit_info |= SVM_IOIO_REP_MASK; | |
4198 | ||
4199 | bytes = min(bytes, 4u); | |
4200 | ||
4201 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4202 | ||
4203 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4204 | ||
4205 | vmcb->control.exit_info_1 = exit_info; | |
4206 | vmcb->control.exit_info_2 = info->next_rip; | |
4207 | ||
4208 | break; | |
4209 | } | |
cfec82cb JR |
4210 | default: |
4211 | break; | |
4212 | } | |
4213 | ||
4214 | vmcb->control.next_rip = info->next_rip; | |
4215 | vmcb->control.exit_code = icpt_info.exit_code; | |
4216 | vmexit = nested_svm_exit_handled(svm); | |
4217 | ||
4218 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4219 | : X86EMUL_CONTINUE; | |
4220 | ||
4221 | out: | |
4222 | return ret; | |
8a76d7f2 JR |
4223 | } |
4224 | ||
cbdd1bea | 4225 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4226 | .cpu_has_kvm_support = has_svm, |
4227 | .disabled_by_bios = is_disabled, | |
4228 | .hardware_setup = svm_hardware_setup, | |
4229 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4230 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4231 | .hardware_enable = svm_hardware_enable, |
4232 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4233 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
4234 | |
4235 | .vcpu_create = svm_create_vcpu, | |
4236 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4237 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4238 | |
04d2cc77 | 4239 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4240 | .vcpu_load = svm_vcpu_load, |
4241 | .vcpu_put = svm_vcpu_put, | |
4242 | ||
c8639010 | 4243 | .update_db_bp_intercept = update_db_bp_intercept, |
6aa8b732 AK |
4244 | .get_msr = svm_get_msr, |
4245 | .set_msr = svm_set_msr, | |
4246 | .get_segment_base = svm_get_segment_base, | |
4247 | .get_segment = svm_get_segment, | |
4248 | .set_segment = svm_set_segment, | |
2e4d2653 | 4249 | .get_cpl = svm_get_cpl, |
1747fb71 | 4250 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4251 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4252 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4253 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4254 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4255 | .set_cr3 = svm_set_cr3, |
4256 | .set_cr4 = svm_set_cr4, | |
4257 | .set_efer = svm_set_efer, | |
4258 | .get_idt = svm_get_idt, | |
4259 | .set_idt = svm_set_idt, | |
4260 | .get_gdt = svm_get_gdt, | |
4261 | .set_gdt = svm_set_gdt, | |
020df079 | 4262 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 4263 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4264 | .get_rflags = svm_get_rflags, |
4265 | .set_rflags = svm_set_rflags, | |
6b52d186 | 4266 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4267 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4268 | |
6aa8b732 | 4269 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4270 | |
6aa8b732 | 4271 | .run = svm_vcpu_run, |
04d2cc77 | 4272 | .handle_exit = handle_exit, |
6aa8b732 | 4273 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4274 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4275 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4276 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4277 | .set_irq = svm_set_irq, |
95ba8273 | 4278 | .set_nmi = svm_inject_nmi, |
298101da | 4279 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4280 | .cancel_injection = svm_cancel_injection, |
78646121 | 4281 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4282 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4283 | .get_nmi_mask = svm_get_nmi_mask, |
4284 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4285 | .enable_nmi_window = enable_nmi_window, |
4286 | .enable_irq_window = enable_irq_window, | |
4287 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
4288 | |
4289 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4290 | .get_tdp_level = get_npt_level, |
4b12f0de | 4291 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4292 | |
586f9607 | 4293 | .get_exit_info = svm_get_exit_info, |
586f9607 | 4294 | |
17cc3935 | 4295 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4296 | |
4297 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4298 | |
4299 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 4300 | .invpcid_supported = svm_invpcid_supported, |
d4330ef2 JR |
4301 | |
4302 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4303 | |
4304 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 4305 | |
4051b188 | 4306 | .set_tsc_khz = svm_set_tsc_khz, |
99e3e30a | 4307 | .write_tsc_offset = svm_write_tsc_offset, |
e48672fa | 4308 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
857e4099 | 4309 | .compute_tsc_offset = svm_compute_tsc_offset, |
d5c1785d | 4310 | .read_l1_tsc = svm_read_l1_tsc, |
1c97f0a0 JR |
4311 | |
4312 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4313 | |
4314 | .check_intercept = svm_check_intercept, | |
6aa8b732 AK |
4315 | }; |
4316 | ||
4317 | static int __init svm_init(void) | |
4318 | { | |
cb498ea2 | 4319 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4320 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4321 | } |
4322 | ||
4323 | static void __exit svm_exit(void) | |
4324 | { | |
cb498ea2 | 4325 | kvm_exit(); |
6aa8b732 AK |
4326 | } |
4327 | ||
4328 | module_init(svm_init) | |
4329 | module_exit(svm_exit) |