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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * AMD SVM support | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 13 | */ |
44a95dae SS |
14 | |
15 | #define pr_fmt(fmt) "SVM: " fmt | |
16 | ||
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
66f7b72e | 23 | #include "cpuid.h" |
25462f7f | 24 | #include "pmu.h" |
e495606d | 25 | |
6aa8b732 | 26 | #include <linux/module.h> |
ae759544 | 27 | #include <linux/mod_devicetable.h> |
9d8f549d | 28 | #include <linux/kernel.h> |
6aa8b732 AK |
29 | #include <linux/vmalloc.h> |
30 | #include <linux/highmem.h> | |
e8edc6e0 | 31 | #include <linux/sched.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
5881f737 SS |
34 | #include <linux/amd-iommu.h> |
35 | #include <linux/hashtable.h> | |
c207aee4 | 36 | #include <linux/frame.h> |
e9df0942 | 37 | #include <linux/psp-sev.h> |
1654efcb | 38 | #include <linux/file.h> |
89c50580 BS |
39 | #include <linux/pagemap.h> |
40 | #include <linux/swap.h> | |
33af3a7e | 41 | #include <linux/rwsem.h> |
6aa8b732 | 42 | |
8221c137 | 43 | #include <asm/apic.h> |
1018faa6 | 44 | #include <asm/perf_event.h> |
67ec6607 | 45 | #include <asm/tlbflush.h> |
e495606d | 46 | #include <asm/desc.h> |
facb0139 | 47 | #include <asm/debugreg.h> |
631bc487 | 48 | #include <asm/kvm_para.h> |
411b44ba | 49 | #include <asm/irq_remapping.h> |
28a27752 | 50 | #include <asm/spec-ctrl.h> |
6aa8b732 | 51 | |
63d1142f | 52 | #include <asm/virtext.h> |
229456fc | 53 | #include "trace.h" |
63d1142f | 54 | |
4ecac3fd AK |
55 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
56 | ||
6aa8b732 AK |
57 | MODULE_AUTHOR("Qumranet"); |
58 | MODULE_LICENSE("GPL"); | |
59 | ||
ae759544 JT |
60 | static const struct x86_cpu_id svm_cpu_id[] = { |
61 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
62 | {} | |
63 | }; | |
64 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
65 | ||
6aa8b732 AK |
66 | #define IOPM_ALLOC_ORDER 2 |
67 | #define MSRPM_ALLOC_ORDER 1 | |
68 | ||
6aa8b732 AK |
69 | #define SEG_TYPE_LDT 2 |
70 | #define SEG_TYPE_BUSY_TSS16 3 | |
71 | ||
6bc31bdc AP |
72 | #define SVM_FEATURE_LBRV (1 << 1) |
73 | #define SVM_FEATURE_SVML (1 << 2) | |
ddce97aa AP |
74 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
75 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
76 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
77 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 78 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 79 | |
340d3bc3 SS |
80 | #define SVM_AVIC_DOORBELL 0xc001011b |
81 | ||
410e4d57 JR |
82 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
83 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
84 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
85 | ||
24e09cbf JR |
86 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
87 | ||
fbc0db76 | 88 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
89 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
90 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 91 | |
5446a979 | 92 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) |
44a95dae SS |
93 | |
94 | /* | |
95 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
96 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
97 | */ | |
98 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
99 | ||
18f40c53 SS |
100 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 |
101 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
102 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
103 | ||
5ea11f2b SS |
104 | /* AVIC GATAG is encoded using VM and VCPU IDs */ |
105 | #define AVIC_VCPU_ID_BITS 8 | |
106 | #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1) | |
107 | ||
108 | #define AVIC_VM_ID_BITS 24 | |
109 | #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS) | |
110 | #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1) | |
111 | ||
112 | #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \ | |
113 | (y & AVIC_VCPU_ID_MASK)) | |
114 | #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK) | |
115 | #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) | |
116 | ||
67ec6607 JR |
117 | static bool erratum_383_found __read_mostly; |
118 | ||
6c8166a7 AK |
119 | static const u32 host_save_user_msrs[] = { |
120 | #ifdef CONFIG_X86_64 | |
121 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
122 | MSR_FS_BASE, | |
123 | #endif | |
124 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 125 | MSR_TSC_AUX, |
6c8166a7 AK |
126 | }; |
127 | ||
128 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
129 | ||
81811c16 SC |
130 | struct kvm_sev_info { |
131 | bool active; /* SEV enabled guest */ | |
132 | unsigned int asid; /* ASID used for this guest */ | |
133 | unsigned int handle; /* SEV firmware handle */ | |
134 | int fd; /* SEV device fd */ | |
135 | unsigned long pages_locked; /* Number of pages locked */ | |
136 | struct list_head regions_list; /* List of registered regions */ | |
137 | }; | |
138 | ||
139 | struct kvm_svm { | |
140 | struct kvm kvm; | |
141 | ||
142 | /* Struct members for AVIC */ | |
143 | u32 avic_vm_id; | |
81811c16 SC |
144 | struct page *avic_logical_id_table_page; |
145 | struct page *avic_physical_id_table_page; | |
146 | struct hlist_node hnode; | |
147 | ||
148 | struct kvm_sev_info sev_info; | |
149 | }; | |
150 | ||
6c8166a7 AK |
151 | struct kvm_vcpu; |
152 | ||
e6aa9abd JR |
153 | struct nested_state { |
154 | struct vmcb *hsave; | |
155 | u64 hsave_msr; | |
4a810181 | 156 | u64 vm_cr_msr; |
e6aa9abd JR |
157 | u64 vmcb; |
158 | ||
159 | /* These are the merged vectors */ | |
160 | u32 *msrpm; | |
161 | ||
162 | /* gpa pointers to the real vectors */ | |
163 | u64 vmcb_msrpm; | |
ce2ac085 | 164 | u64 vmcb_iopm; |
aad42c64 | 165 | |
cd3ff653 JR |
166 | /* A VMEXIT is required but not yet emulated */ |
167 | bool exit_required; | |
168 | ||
aad42c64 | 169 | /* cache for intercepts of the guest */ |
4ee546b4 | 170 | u32 intercept_cr; |
3aed041a | 171 | u32 intercept_dr; |
aad42c64 JR |
172 | u32 intercept_exceptions; |
173 | u64 intercept; | |
174 | ||
5bd2edc3 JR |
175 | /* Nested Paging related state */ |
176 | u64 nested_cr3; | |
e6aa9abd JR |
177 | }; |
178 | ||
323c3d80 JR |
179 | #define MSRPM_OFFSETS 16 |
180 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
181 | ||
2b036c6b BO |
182 | /* |
183 | * Set osvw_len to higher value when updated Revision Guides | |
184 | * are published and we know what the new status bits are | |
185 | */ | |
186 | static uint64_t osvw_len = 4, osvw_status; | |
187 | ||
6c8166a7 AK |
188 | struct vcpu_svm { |
189 | struct kvm_vcpu vcpu; | |
190 | struct vmcb *vmcb; | |
191 | unsigned long vmcb_pa; | |
192 | struct svm_cpu_data *svm_data; | |
193 | uint64_t asid_generation; | |
194 | uint64_t sysenter_esp; | |
195 | uint64_t sysenter_eip; | |
46896c73 | 196 | uint64_t tsc_aux; |
6c8166a7 | 197 | |
d1d93fa9 TL |
198 | u64 msr_decfg; |
199 | ||
6c8166a7 AK |
200 | u64 next_rip; |
201 | ||
202 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 203 | struct { |
dacccfdd AK |
204 | u16 fs; |
205 | u16 gs; | |
206 | u16 ldt; | |
afe9e66f AK |
207 | u64 gs_base; |
208 | } host; | |
6c8166a7 | 209 | |
b2ac58f9 | 210 | u64 spec_ctrl; |
ccbcd267 TG |
211 | /* |
212 | * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be | |
213 | * translated into the appropriate L2_CFG bits on the host to | |
214 | * perform speculative control. | |
215 | */ | |
216 | u64 virt_spec_ctrl; | |
b2ac58f9 | 217 | |
6c8166a7 | 218 | u32 *msrpm; |
6c8166a7 | 219 | |
bd3d1ec3 AK |
220 | ulong nmi_iret_rip; |
221 | ||
e6aa9abd | 222 | struct nested_state nested; |
6be7d306 JK |
223 | |
224 | bool nmi_singlestep; | |
ab2f4d73 | 225 | u64 nmi_singlestep_guest_rflags; |
66b7138f JK |
226 | |
227 | unsigned int3_injected; | |
228 | unsigned long int3_rip; | |
fbc0db76 | 229 | |
6092d3d3 JR |
230 | /* cached guest cpuid flags for faster access */ |
231 | bool nrips_enabled : 1; | |
44a95dae | 232 | |
18f40c53 | 233 | u32 ldr_reg; |
98d90582 | 234 | u32 dfr_reg; |
44a95dae SS |
235 | struct page *avic_backing_page; |
236 | u64 *avic_physical_id_cache; | |
8221c137 | 237 | bool avic_is_running; |
411b44ba SS |
238 | |
239 | /* | |
240 | * Per-vcpu list of struct amd_svm_iommu_ir: | |
241 | * This is used mainly to store interrupt remapping information used | |
242 | * when update the vcpu affinity. This avoids the need to scan for | |
243 | * IRTE and try to match ga_tag in the IOMMU driver. | |
244 | */ | |
245 | struct list_head ir_list; | |
246 | spinlock_t ir_list_lock; | |
70cd94e6 BS |
247 | |
248 | /* which host CPU was used for running this vcpu */ | |
249 | unsigned int last_cpu; | |
411b44ba SS |
250 | }; |
251 | ||
252 | /* | |
253 | * This is a wrapper of struct amd_iommu_ir_data. | |
254 | */ | |
255 | struct amd_svm_iommu_ir { | |
256 | struct list_head node; /* Used by SVM for per-vcpu ir_list */ | |
257 | void *data; /* Storing pointer to struct amd_ir_data */ | |
6c8166a7 AK |
258 | }; |
259 | ||
44a95dae | 260 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
e44e3eac | 261 | #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 |
44a95dae SS |
262 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) |
263 | ||
264 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
265 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
266 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
267 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
268 | ||
fbc0db76 JR |
269 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
270 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
271 | ||
455716fa JR |
272 | #define MSR_INVALID 0xffffffffU |
273 | ||
09941fbb | 274 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
275 | u32 index; /* Index of the MSR */ |
276 | bool always; /* True if intercept is always on */ | |
277 | } direct_access_msrs[] = { | |
8c06585d | 278 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
279 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
280 | #ifdef CONFIG_X86_64 | |
281 | { .index = MSR_GS_BASE, .always = true }, | |
282 | { .index = MSR_FS_BASE, .always = true }, | |
283 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
284 | { .index = MSR_LSTAR, .always = true }, | |
285 | { .index = MSR_CSTAR, .always = true }, | |
286 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
287 | #endif | |
b2ac58f9 | 288 | { .index = MSR_IA32_SPEC_CTRL, .always = false }, |
15d45071 | 289 | { .index = MSR_IA32_PRED_CMD, .always = false }, |
ac72a9b7 JR |
290 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, |
291 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
292 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
293 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
294 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
295 | }; |
296 | ||
709ddebf JR |
297 | /* enable NPT for AMD64 and X86 with PAE */ |
298 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
299 | static bool npt_enabled = true; | |
300 | #else | |
e0231715 | 301 | static bool npt_enabled; |
709ddebf | 302 | #endif |
6c7dac72 | 303 | |
8566ac8b BM |
304 | /* |
305 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
306 | * pause_filter_count: On processors that support Pause filtering(indicated | |
307 | * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter | |
308 | * count value. On VMRUN this value is loaded into an internal counter. | |
309 | * Each time a pause instruction is executed, this counter is decremented | |
310 | * until it reaches zero at which time a #VMEXIT is generated if pause | |
311 | * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause | |
312 | * Intercept Filtering for more details. | |
313 | * This also indicate if ple logic enabled. | |
314 | * | |
315 | * pause_filter_thresh: In addition, some processor families support advanced | |
316 | * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on | |
317 | * the amount of time a guest is allowed to execute in a pause loop. | |
318 | * In this mode, a 16-bit pause filter threshold field is added in the | |
319 | * VMCB. The threshold value is a cycle count that is used to reset the | |
320 | * pause counter. As with simple pause filtering, VMRUN loads the pause | |
321 | * count value from VMCB into an internal counter. Then, on each pause | |
322 | * instruction the hardware checks the elapsed number of cycles since | |
323 | * the most recent pause instruction against the pause filter threshold. | |
324 | * If the elapsed cycle count is greater than the pause filter threshold, | |
325 | * then the internal pause count is reloaded from the VMCB and execution | |
326 | * continues. If the elapsed cycle count is less than the pause filter | |
327 | * threshold, then the internal pause count is decremented. If the count | |
328 | * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is | |
329 | * triggered. If advanced pause filtering is supported and pause filter | |
330 | * threshold field is set to zero, the filter will operate in the simpler, | |
331 | * count only mode. | |
332 | */ | |
333 | ||
334 | static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP; | |
335 | module_param(pause_filter_thresh, ushort, 0444); | |
336 | ||
337 | static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW; | |
338 | module_param(pause_filter_count, ushort, 0444); | |
339 | ||
340 | /* Default doubles per-vcpu window every exit. */ | |
341 | static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW; | |
342 | module_param(pause_filter_count_grow, ushort, 0444); | |
343 | ||
344 | /* Default resets per-vcpu window every exit to pause_filter_count. */ | |
345 | static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; | |
346 | module_param(pause_filter_count_shrink, ushort, 0444); | |
347 | ||
348 | /* Default is to compute the maximum so we can never overflow. */ | |
349 | static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX; | |
350 | module_param(pause_filter_count_max, ushort, 0444); | |
351 | ||
e2358851 DB |
352 | /* allow nested paging (virtualized MMU) for all guests */ |
353 | static int npt = true; | |
6c7dac72 | 354 | module_param(npt, int, S_IRUGO); |
e3da3acd | 355 | |
e2358851 DB |
356 | /* allow nested virtualization in KVM/SVM */ |
357 | static int nested = true; | |
236de055 AG |
358 | module_param(nested, int, S_IRUGO); |
359 | ||
44a95dae SS |
360 | /* enable / disable AVIC */ |
361 | static int avic; | |
5b8abf1f | 362 | #ifdef CONFIG_X86_LOCAL_APIC |
44a95dae | 363 | module_param(avic, int, S_IRUGO); |
5b8abf1f | 364 | #endif |
44a95dae | 365 | |
d647eb63 PB |
366 | /* enable/disable Next RIP Save */ |
367 | static int nrips = true; | |
368 | module_param(nrips, int, 0444); | |
369 | ||
89c8a498 JN |
370 | /* enable/disable Virtual VMLOAD VMSAVE */ |
371 | static int vls = true; | |
372 | module_param(vls, int, 0444); | |
373 | ||
640bd6e5 JN |
374 | /* enable/disable Virtual GIF */ |
375 | static int vgif = true; | |
376 | module_param(vgif, int, 0444); | |
5ea11f2b | 377 | |
e9df0942 BS |
378 | /* enable/disable SEV support */ |
379 | static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT); | |
380 | module_param(sev, int, 0444); | |
381 | ||
6f2f8453 PB |
382 | static bool __read_mostly dump_invalid_vmcb = 0; |
383 | module_param(dump_invalid_vmcb, bool, 0644); | |
384 | ||
7607b717 BS |
385 | static u8 rsm_ins_bytes[] = "\x0f\xaa"; |
386 | ||
79a8059d | 387 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
c2ba05cc | 388 | static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa); |
a5c3832d | 389 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
6c3e4422 | 390 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu); |
04d2cc77 | 391 | |
410e4d57 | 392 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 393 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 394 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
395 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
396 | bool has_error_code, u32 error_code); | |
397 | ||
8d28fec4 | 398 | enum { |
116a0a23 JR |
399 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
400 | pause filter count */ | |
f56838e4 | 401 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 402 | VMCB_ASID, /* ASID */ |
decdbf6a | 403 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 404 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 405 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 406 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 407 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 408 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 409 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 410 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
411 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
412 | * AVIC PHYSICAL_TABLE pointer, | |
413 | * AVIC LOGICAL_TABLE pointer | |
414 | */ | |
8d28fec4 RJ |
415 | VMCB_DIRTY_MAX, |
416 | }; | |
417 | ||
0574dec0 JR |
418 | /* TPR and CR2 are always written before VMRUN */ |
419 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 420 | |
44a95dae SS |
421 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
422 | ||
33af3a7e TL |
423 | static int sev_flush_asids(void); |
424 | static DECLARE_RWSEM(sev_deactivate_lock); | |
e3b9a9e1 | 425 | static DEFINE_MUTEX(sev_bitmap_lock); |
ed3cd233 | 426 | static unsigned int max_sev_asid; |
1654efcb BS |
427 | static unsigned int min_sev_asid; |
428 | static unsigned long *sev_asid_bitmap; | |
33af3a7e | 429 | static unsigned long *sev_reclaim_asid_bitmap; |
89c50580 | 430 | #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) |
1654efcb | 431 | |
1e80fdc0 BS |
432 | struct enc_region { |
433 | struct list_head list; | |
434 | unsigned long npages; | |
435 | struct page **pages; | |
436 | unsigned long uaddr; | |
437 | unsigned long size; | |
438 | }; | |
439 | ||
81811c16 SC |
440 | |
441 | static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) | |
442 | { | |
443 | return container_of(kvm, struct kvm_svm, kvm); | |
444 | } | |
445 | ||
1654efcb BS |
446 | static inline bool svm_sev_enabled(void) |
447 | { | |
853c1109 | 448 | return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0; |
1654efcb BS |
449 | } |
450 | ||
451 | static inline bool sev_guest(struct kvm *kvm) | |
452 | { | |
853c1109 | 453 | #ifdef CONFIG_KVM_AMD_SEV |
81811c16 | 454 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1654efcb BS |
455 | |
456 | return sev->active; | |
853c1109 PB |
457 | #else |
458 | return false; | |
459 | #endif | |
1654efcb | 460 | } |
ed3cd233 | 461 | |
70cd94e6 BS |
462 | static inline int sev_get_asid(struct kvm *kvm) |
463 | { | |
81811c16 | 464 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
70cd94e6 BS |
465 | |
466 | return sev->asid; | |
467 | } | |
468 | ||
8d28fec4 RJ |
469 | static inline void mark_all_dirty(struct vmcb *vmcb) |
470 | { | |
471 | vmcb->control.clean = 0; | |
472 | } | |
473 | ||
474 | static inline void mark_all_clean(struct vmcb *vmcb) | |
475 | { | |
476 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
477 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
478 | } | |
479 | ||
480 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
481 | { | |
482 | vmcb->control.clean &= ~(1 << bit); | |
483 | } | |
484 | ||
a2fa3e9f GH |
485 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
486 | { | |
fb3f0f51 | 487 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
488 | } |
489 | ||
44a95dae SS |
490 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
491 | { | |
492 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
493 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
494 | } | |
495 | ||
340d3bc3 SS |
496 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
497 | { | |
498 | struct vcpu_svm *svm = to_svm(vcpu); | |
499 | u64 *entry = svm->avic_physical_id_cache; | |
500 | ||
501 | if (!entry) | |
502 | return false; | |
503 | ||
504 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
505 | } | |
506 | ||
384c6368 JR |
507 | static void recalc_intercepts(struct vcpu_svm *svm) |
508 | { | |
509 | struct vmcb_control_area *c, *h; | |
510 | struct nested_state *g; | |
511 | ||
116a0a23 JR |
512 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
513 | ||
384c6368 JR |
514 | if (!is_guest_mode(&svm->vcpu)) |
515 | return; | |
516 | ||
517 | c = &svm->vmcb->control; | |
518 | h = &svm->nested.hsave->control; | |
519 | g = &svm->nested; | |
520 | ||
4ee546b4 | 521 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 522 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
bd89525a | 523 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
384c6368 JR |
524 | c->intercept = h->intercept | g->intercept; |
525 | } | |
526 | ||
4ee546b4 RJ |
527 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
528 | { | |
529 | if (is_guest_mode(&svm->vcpu)) | |
530 | return svm->nested.hsave; | |
531 | else | |
532 | return svm->vmcb; | |
533 | } | |
534 | ||
535 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
536 | { | |
537 | struct vmcb *vmcb = get_host_vmcb(svm); | |
538 | ||
539 | vmcb->control.intercept_cr |= (1U << bit); | |
540 | ||
541 | recalc_intercepts(svm); | |
542 | } | |
543 | ||
544 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
545 | { | |
546 | struct vmcb *vmcb = get_host_vmcb(svm); | |
547 | ||
548 | vmcb->control.intercept_cr &= ~(1U << bit); | |
549 | ||
550 | recalc_intercepts(svm); | |
551 | } | |
552 | ||
553 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
554 | { | |
555 | struct vmcb *vmcb = get_host_vmcb(svm); | |
556 | ||
557 | return vmcb->control.intercept_cr & (1U << bit); | |
558 | } | |
559 | ||
5315c716 | 560 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
561 | { |
562 | struct vmcb *vmcb = get_host_vmcb(svm); | |
563 | ||
5315c716 PB |
564 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
565 | | (1 << INTERCEPT_DR1_READ) | |
566 | | (1 << INTERCEPT_DR2_READ) | |
567 | | (1 << INTERCEPT_DR3_READ) | |
568 | | (1 << INTERCEPT_DR4_READ) | |
569 | | (1 << INTERCEPT_DR5_READ) | |
570 | | (1 << INTERCEPT_DR6_READ) | |
571 | | (1 << INTERCEPT_DR7_READ) | |
572 | | (1 << INTERCEPT_DR0_WRITE) | |
573 | | (1 << INTERCEPT_DR1_WRITE) | |
574 | | (1 << INTERCEPT_DR2_WRITE) | |
575 | | (1 << INTERCEPT_DR3_WRITE) | |
576 | | (1 << INTERCEPT_DR4_WRITE) | |
577 | | (1 << INTERCEPT_DR5_WRITE) | |
578 | | (1 << INTERCEPT_DR6_WRITE) | |
579 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
580 | |
581 | recalc_intercepts(svm); | |
582 | } | |
583 | ||
5315c716 | 584 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
585 | { |
586 | struct vmcb *vmcb = get_host_vmcb(svm); | |
587 | ||
5315c716 | 588 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
589 | |
590 | recalc_intercepts(svm); | |
591 | } | |
592 | ||
18c918c5 JR |
593 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
594 | { | |
595 | struct vmcb *vmcb = get_host_vmcb(svm); | |
596 | ||
597 | vmcb->control.intercept_exceptions |= (1U << bit); | |
598 | ||
599 | recalc_intercepts(svm); | |
600 | } | |
601 | ||
602 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
603 | { | |
604 | struct vmcb *vmcb = get_host_vmcb(svm); | |
605 | ||
606 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
607 | ||
608 | recalc_intercepts(svm); | |
609 | } | |
610 | ||
8a05a1b8 JR |
611 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
612 | { | |
613 | struct vmcb *vmcb = get_host_vmcb(svm); | |
614 | ||
615 | vmcb->control.intercept |= (1ULL << bit); | |
616 | ||
617 | recalc_intercepts(svm); | |
618 | } | |
619 | ||
620 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
621 | { | |
622 | struct vmcb *vmcb = get_host_vmcb(svm); | |
623 | ||
624 | vmcb->control.intercept &= ~(1ULL << bit); | |
625 | ||
626 | recalc_intercepts(svm); | |
627 | } | |
628 | ||
640bd6e5 JN |
629 | static inline bool vgif_enabled(struct vcpu_svm *svm) |
630 | { | |
631 | return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); | |
632 | } | |
633 | ||
2af9194d JR |
634 | static inline void enable_gif(struct vcpu_svm *svm) |
635 | { | |
640bd6e5 JN |
636 | if (vgif_enabled(svm)) |
637 | svm->vmcb->control.int_ctl |= V_GIF_MASK; | |
638 | else | |
639 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
2af9194d JR |
640 | } |
641 | ||
642 | static inline void disable_gif(struct vcpu_svm *svm) | |
643 | { | |
640bd6e5 JN |
644 | if (vgif_enabled(svm)) |
645 | svm->vmcb->control.int_ctl &= ~V_GIF_MASK; | |
646 | else | |
647 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
2af9194d JR |
648 | } |
649 | ||
650 | static inline bool gif_set(struct vcpu_svm *svm) | |
651 | { | |
640bd6e5 JN |
652 | if (vgif_enabled(svm)) |
653 | return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); | |
654 | else | |
655 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
2af9194d JR |
656 | } |
657 | ||
4866d5e3 | 658 | static unsigned long iopm_base; |
6aa8b732 AK |
659 | |
660 | struct kvm_ldttss_desc { | |
661 | u16 limit0; | |
662 | u16 base0; | |
e0231715 JR |
663 | unsigned base1:8, type:5, dpl:2, p:1; |
664 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
665 | u32 base3; |
666 | u32 zero1; | |
667 | } __attribute__((packed)); | |
668 | ||
669 | struct svm_cpu_data { | |
670 | int cpu; | |
671 | ||
5008fdf5 AK |
672 | u64 asid_generation; |
673 | u32 max_asid; | |
674 | u32 next_asid; | |
4faefff3 | 675 | u32 min_asid; |
6aa8b732 AK |
676 | struct kvm_ldttss_desc *tss_desc; |
677 | ||
678 | struct page *save_area; | |
15d45071 | 679 | struct vmcb *current_vmcb; |
70cd94e6 BS |
680 | |
681 | /* index = sev_asid, value = vmcb pointer */ | |
682 | struct vmcb **sev_vmcbs; | |
6aa8b732 AK |
683 | }; |
684 | ||
685 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
686 | ||
09941fbb | 687 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 688 | |
9d8f549d | 689 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
690 | #define MSRS_RANGE_SIZE 2048 |
691 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
692 | ||
455716fa JR |
693 | static u32 svm_msrpm_offset(u32 msr) |
694 | { | |
695 | u32 offset; | |
696 | int i; | |
697 | ||
698 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
699 | if (msr < msrpm_ranges[i] || | |
700 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
701 | continue; | |
702 | ||
703 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
704 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
705 | ||
706 | /* Now we have the u8 offset - but need the u32 offset */ | |
707 | return offset / 4; | |
708 | } | |
709 | ||
710 | /* MSR not in any range */ | |
711 | return MSR_INVALID; | |
712 | } | |
713 | ||
6aa8b732 AK |
714 | #define MAX_INST_SIZE 15 |
715 | ||
6aa8b732 AK |
716 | static inline void clgi(void) |
717 | { | |
ac5ffda2 | 718 | asm volatile (__ex("clgi")); |
6aa8b732 AK |
719 | } |
720 | ||
721 | static inline void stgi(void) | |
722 | { | |
ac5ffda2 | 723 | asm volatile (__ex("stgi")); |
6aa8b732 AK |
724 | } |
725 | ||
726 | static inline void invlpga(unsigned long addr, u32 asid) | |
727 | { | |
ac5ffda2 | 728 | asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr)); |
6aa8b732 AK |
729 | } |
730 | ||
855feb67 | 731 | static int get_npt_level(struct kvm_vcpu *vcpu) |
4b16184c JR |
732 | { |
733 | #ifdef CONFIG_X86_64 | |
2a7266a8 | 734 | return PT64_ROOT_4LEVEL; |
4b16184c JR |
735 | #else |
736 | return PT32E_ROOT_LEVEL; | |
737 | #endif | |
738 | } | |
739 | ||
6aa8b732 AK |
740 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
741 | { | |
6dc696d4 | 742 | vcpu->arch.efer = efer; |
9167ab79 PB |
743 | |
744 | if (!npt_enabled) { | |
745 | /* Shadow paging assumes NX to be available. */ | |
746 | efer |= EFER_NX; | |
747 | ||
748 | if (!(efer & EFER_LMA)) | |
749 | efer &= ~EFER_LME; | |
750 | } | |
6aa8b732 | 751 | |
9962d032 | 752 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 753 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
754 | } |
755 | ||
6aa8b732 AK |
756 | static int is_external_interrupt(u32 info) |
757 | { | |
758 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
759 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
760 | } | |
761 | ||
37ccdcbe | 762 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
763 | { |
764 | struct vcpu_svm *svm = to_svm(vcpu); | |
765 | u32 ret = 0; | |
766 | ||
767 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
768 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
769 | return ret; | |
2809f5d2 GC |
770 | } |
771 | ||
772 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
773 | { | |
774 | struct vcpu_svm *svm = to_svm(vcpu); | |
775 | ||
776 | if (mask == 0) | |
777 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
778 | else | |
779 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
780 | ||
781 | } | |
782 | ||
f8ea7c60 | 783 | static int skip_emulated_instruction(struct kvm_vcpu *vcpu) |
6aa8b732 | 784 | { |
a2fa3e9f GH |
785 | struct vcpu_svm *svm = to_svm(vcpu); |
786 | ||
d647eb63 | 787 | if (nrips && svm->vmcb->control.next_rip != 0) { |
d2922422 | 788 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 789 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 790 | } |
6bc31bdc | 791 | |
1957aa63 SC |
792 | if (!svm->next_rip) { |
793 | if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) | |
794 | return 0; | |
795 | } else { | |
796 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) | |
797 | pr_err("%s: ip 0x%lx next 0x%llx\n", | |
798 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
799 | kvm_rip_write(vcpu, svm->next_rip); | |
800 | } | |
2809f5d2 | 801 | svm_set_interrupt_shadow(vcpu, 0); |
f8ea7c60 | 802 | |
60fc3d02 | 803 | return 1; |
6aa8b732 AK |
804 | } |
805 | ||
cfcd20e5 | 806 | static void svm_queue_exception(struct kvm_vcpu *vcpu) |
116a4752 JK |
807 | { |
808 | struct vcpu_svm *svm = to_svm(vcpu); | |
cfcd20e5 WL |
809 | unsigned nr = vcpu->arch.exception.nr; |
810 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
664f8e26 | 811 | bool reinject = vcpu->arch.exception.injected; |
cfcd20e5 | 812 | u32 error_code = vcpu->arch.exception.error_code; |
116a4752 | 813 | |
e0231715 JR |
814 | /* |
815 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
816 | * handle the exception | |
817 | */ | |
ce7ddec4 JR |
818 | if (!reinject && |
819 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
820 | return; |
821 | ||
da998b46 JM |
822 | kvm_deliver_exception_payload(&svm->vcpu); |
823 | ||
d647eb63 | 824 | if (nr == BP_VECTOR && !nrips) { |
66b7138f JK |
825 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
826 | ||
827 | /* | |
828 | * For guest debugging where we have to reinject #BP if some | |
829 | * INT3 is guest-owned: | |
830 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
831 | * raises a fault that is not intercepted. Still better than | |
832 | * failing in all cases. | |
833 | */ | |
f8ea7c60 | 834 | (void)skip_emulated_instruction(&svm->vcpu); |
66b7138f JK |
835 | rip = kvm_rip_read(&svm->vcpu); |
836 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
837 | svm->int3_injected = rip - old_rip; | |
838 | } | |
839 | ||
116a4752 JK |
840 | svm->vmcb->control.event_inj = nr |
841 | | SVM_EVTINJ_VALID | |
842 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
843 | | SVM_EVTINJ_TYPE_EXEPT; | |
844 | svm->vmcb->control.event_inj_err = error_code; | |
845 | } | |
846 | ||
67ec6607 JR |
847 | static void svm_init_erratum_383(void) |
848 | { | |
849 | u32 low, high; | |
850 | int err; | |
851 | u64 val; | |
852 | ||
e6ee94d5 | 853 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
854 | return; |
855 | ||
856 | /* Use _safe variants to not break nested virtualization */ | |
857 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
858 | if (err) | |
859 | return; | |
860 | ||
861 | val |= (1ULL << 47); | |
862 | ||
863 | low = lower_32_bits(val); | |
864 | high = upper_32_bits(val); | |
865 | ||
866 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
867 | ||
868 | erratum_383_found = true; | |
869 | } | |
870 | ||
2b036c6b BO |
871 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
872 | { | |
873 | /* | |
874 | * Guests should see errata 400 and 415 as fixed (assuming that | |
875 | * HLT and IO instructions are intercepted). | |
876 | */ | |
877 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
878 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
879 | ||
880 | /* | |
881 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
882 | * all osvw.status bits inside that length, including bit 0 (which is | |
883 | * reserved for erratum 298), are valid. However, if host processor's | |
884 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
885 | * be conservative here and therefore we tell the guest that erratum 298 | |
886 | * is present (because we really don't know). | |
887 | */ | |
888 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
889 | vcpu->arch.osvw.status |= 1; | |
890 | } | |
891 | ||
6aa8b732 AK |
892 | static int has_svm(void) |
893 | { | |
63d1142f | 894 | const char *msg; |
6aa8b732 | 895 | |
63d1142f | 896 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 897 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
898 | return 0; |
899 | } | |
900 | ||
6aa8b732 AK |
901 | return 1; |
902 | } | |
903 | ||
13a34e06 | 904 | static void svm_hardware_disable(void) |
6aa8b732 | 905 | { |
fbc0db76 JR |
906 | /* Make sure we clean up behind us */ |
907 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
908 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
909 | ||
2c8dceeb | 910 | cpu_svm_disable(); |
1018faa6 JR |
911 | |
912 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
913 | } |
914 | ||
13a34e06 | 915 | static int svm_hardware_enable(void) |
6aa8b732 AK |
916 | { |
917 | ||
0fe1e009 | 918 | struct svm_cpu_data *sd; |
6aa8b732 | 919 | uint64_t efer; |
6aa8b732 AK |
920 | struct desc_struct *gdt; |
921 | int me = raw_smp_processor_id(); | |
922 | ||
10474ae8 AG |
923 | rdmsrl(MSR_EFER, efer); |
924 | if (efer & EFER_SVME) | |
925 | return -EBUSY; | |
926 | ||
6aa8b732 | 927 | if (!has_svm()) { |
1f5b77f5 | 928 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 929 | return -EINVAL; |
6aa8b732 | 930 | } |
0fe1e009 | 931 | sd = per_cpu(svm_data, me); |
0fe1e009 | 932 | if (!sd) { |
1f5b77f5 | 933 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 934 | return -EINVAL; |
6aa8b732 AK |
935 | } |
936 | ||
0fe1e009 TH |
937 | sd->asid_generation = 1; |
938 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
939 | sd->next_asid = sd->max_asid + 1; | |
ed3cd233 | 940 | sd->min_asid = max_sev_asid + 1; |
6aa8b732 | 941 | |
45fc8757 | 942 | gdt = get_current_gdt_rw(); |
0fe1e009 | 943 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 944 | |
9962d032 | 945 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 946 | |
d0316554 | 947 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 948 | |
fbc0db76 JR |
949 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
950 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 951 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
952 | } |
953 | ||
2b036c6b BO |
954 | |
955 | /* | |
956 | * Get OSVW bits. | |
957 | * | |
958 | * Note that it is possible to have a system with mixed processor | |
959 | * revisions and therefore different OSVW bits. If bits are not the same | |
960 | * on different processors then choose the worst case (i.e. if erratum | |
961 | * is present on one processor and not on another then assume that the | |
962 | * erratum is present everywhere). | |
963 | */ | |
964 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
965 | uint64_t len, status = 0; | |
966 | int err; | |
967 | ||
968 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
969 | if (!err) | |
970 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
971 | &err); | |
972 | ||
973 | if (err) | |
974 | osvw_status = osvw_len = 0; | |
975 | else { | |
976 | if (len < osvw_len) | |
977 | osvw_len = len; | |
978 | osvw_status |= status; | |
979 | osvw_status &= (1ULL << osvw_len) - 1; | |
980 | } | |
981 | } else | |
982 | osvw_status = osvw_len = 0; | |
983 | ||
67ec6607 JR |
984 | svm_init_erratum_383(); |
985 | ||
1018faa6 JR |
986 | amd_pmu_enable_virt(); |
987 | ||
10474ae8 | 988 | return 0; |
6aa8b732 AK |
989 | } |
990 | ||
0da1db75 JR |
991 | static void svm_cpu_uninit(int cpu) |
992 | { | |
0fe1e009 | 993 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 994 | |
0fe1e009 | 995 | if (!sd) |
0da1db75 JR |
996 | return; |
997 | ||
998 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
70cd94e6 | 999 | kfree(sd->sev_vmcbs); |
0fe1e009 TH |
1000 | __free_page(sd->save_area); |
1001 | kfree(sd); | |
0da1db75 JR |
1002 | } |
1003 | ||
6aa8b732 AK |
1004 | static int svm_cpu_init(int cpu) |
1005 | { | |
0fe1e009 | 1006 | struct svm_cpu_data *sd; |
6aa8b732 AK |
1007 | int r; |
1008 | ||
0fe1e009 TH |
1009 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
1010 | if (!sd) | |
6aa8b732 | 1011 | return -ENOMEM; |
0fe1e009 | 1012 | sd->cpu = cpu; |
6aa8b732 | 1013 | r = -ENOMEM; |
70cd94e6 | 1014 | sd->save_area = alloc_page(GFP_KERNEL); |
0fe1e009 | 1015 | if (!sd->save_area) |
6aa8b732 AK |
1016 | goto err_1; |
1017 | ||
70cd94e6 BS |
1018 | if (svm_sev_enabled()) { |
1019 | r = -ENOMEM; | |
6da2ec56 KC |
1020 | sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1, |
1021 | sizeof(void *), | |
1022 | GFP_KERNEL); | |
70cd94e6 BS |
1023 | if (!sd->sev_vmcbs) |
1024 | goto err_1; | |
1025 | } | |
1026 | ||
0fe1e009 | 1027 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
1028 | |
1029 | return 0; | |
1030 | ||
1031 | err_1: | |
0fe1e009 | 1032 | kfree(sd); |
6aa8b732 AK |
1033 | return r; |
1034 | ||
1035 | } | |
1036 | ||
ac72a9b7 JR |
1037 | static bool valid_msr_intercept(u32 index) |
1038 | { | |
1039 | int i; | |
1040 | ||
1041 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
1042 | if (direct_access_msrs[i].index == index) | |
1043 | return true; | |
1044 | ||
1045 | return false; | |
1046 | } | |
1047 | ||
b2ac58f9 KA |
1048 | static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr) |
1049 | { | |
1050 | u8 bit_write; | |
1051 | unsigned long tmp; | |
1052 | u32 offset; | |
1053 | u32 *msrpm; | |
1054 | ||
1055 | msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm: | |
1056 | to_svm(vcpu)->msrpm; | |
1057 | ||
1058 | offset = svm_msrpm_offset(msr); | |
1059 | bit_write = 2 * (msr & 0x0f) + 1; | |
1060 | tmp = msrpm[offset]; | |
1061 | ||
1062 | BUG_ON(offset == MSR_INVALID); | |
1063 | ||
1064 | return !!test_bit(bit_write, &tmp); | |
1065 | } | |
1066 | ||
bfc733a7 RR |
1067 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
1068 | int read, int write) | |
6aa8b732 | 1069 | { |
455716fa JR |
1070 | u8 bit_read, bit_write; |
1071 | unsigned long tmp; | |
1072 | u32 offset; | |
6aa8b732 | 1073 | |
ac72a9b7 JR |
1074 | /* |
1075 | * If this warning triggers extend the direct_access_msrs list at the | |
1076 | * beginning of the file | |
1077 | */ | |
1078 | WARN_ON(!valid_msr_intercept(msr)); | |
1079 | ||
455716fa JR |
1080 | offset = svm_msrpm_offset(msr); |
1081 | bit_read = 2 * (msr & 0x0f); | |
1082 | bit_write = 2 * (msr & 0x0f) + 1; | |
1083 | tmp = msrpm[offset]; | |
1084 | ||
1085 | BUG_ON(offset == MSR_INVALID); | |
1086 | ||
1087 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
1088 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
1089 | ||
1090 | msrpm[offset] = tmp; | |
6aa8b732 AK |
1091 | } |
1092 | ||
f65c229c | 1093 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
1094 | { |
1095 | int i; | |
1096 | ||
f65c229c JR |
1097 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
1098 | ||
ac72a9b7 JR |
1099 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
1100 | if (!direct_access_msrs[i].always) | |
1101 | continue; | |
1102 | ||
1103 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
1104 | } | |
f65c229c JR |
1105 | } |
1106 | ||
323c3d80 JR |
1107 | static void add_msr_offset(u32 offset) |
1108 | { | |
1109 | int i; | |
1110 | ||
1111 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
1112 | ||
1113 | /* Offset already in list? */ | |
1114 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 1115 | return; |
323c3d80 JR |
1116 | |
1117 | /* Slot used by another offset? */ | |
1118 | if (msrpm_offsets[i] != MSR_INVALID) | |
1119 | continue; | |
1120 | ||
1121 | /* Add offset to list */ | |
1122 | msrpm_offsets[i] = offset; | |
1123 | ||
1124 | return; | |
6aa8b732 | 1125 | } |
323c3d80 JR |
1126 | |
1127 | /* | |
1128 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
1129 | * increase MSRPM_OFFSETS in this case. | |
1130 | */ | |
bfc733a7 | 1131 | BUG(); |
6aa8b732 AK |
1132 | } |
1133 | ||
323c3d80 | 1134 | static void init_msrpm_offsets(void) |
f65c229c | 1135 | { |
323c3d80 | 1136 | int i; |
f65c229c | 1137 | |
323c3d80 JR |
1138 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
1139 | ||
1140 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
1141 | u32 offset; | |
1142 | ||
1143 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
1144 | BUG_ON(offset == MSR_INVALID); | |
1145 | ||
1146 | add_msr_offset(offset); | |
1147 | } | |
f65c229c JR |
1148 | } |
1149 | ||
24e09cbf JR |
1150 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
1151 | { | |
1152 | u32 *msrpm = svm->msrpm; | |
1153 | ||
0dc92119 | 1154 | svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
1155 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); |
1156 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
1157 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
1158 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
1159 | } | |
1160 | ||
1161 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
1162 | { | |
1163 | u32 *msrpm = svm->msrpm; | |
1164 | ||
0dc92119 | 1165 | svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
1166 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); |
1167 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
1168 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
1169 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
1170 | } | |
1171 | ||
4aebd0e9 LP |
1172 | static void disable_nmi_singlestep(struct vcpu_svm *svm) |
1173 | { | |
1174 | svm->nmi_singlestep = false; | |
640bd6e5 | 1175 | |
ab2f4d73 LP |
1176 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) { |
1177 | /* Clear our flags if they were not set by the guest */ | |
1178 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
1179 | svm->vmcb->save.rflags &= ~X86_EFLAGS_TF; | |
1180 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
1181 | svm->vmcb->save.rflags &= ~X86_EFLAGS_RF; | |
1182 | } | |
4aebd0e9 LP |
1183 | } |
1184 | ||
5881f737 | 1185 | /* Note: |
81811c16 | 1186 | * This hash table is used to map VM_ID to a struct kvm_svm, |
5881f737 SS |
1187 | * when handling AMD IOMMU GALOG notification to schedule in |
1188 | * a particular vCPU. | |
1189 | */ | |
1190 | #define SVM_VM_DATA_HASH_BITS 8 | |
681bcea8 | 1191 | static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); |
3f0d4db7 DV |
1192 | static u32 next_vm_id = 0; |
1193 | static bool next_vm_id_wrapped = 0; | |
681bcea8 | 1194 | static DEFINE_SPINLOCK(svm_vm_data_hash_lock); |
5881f737 SS |
1195 | |
1196 | /* Note: | |
1197 | * This function is called from IOMMU driver to notify | |
1198 | * SVM to schedule in a particular vCPU of a particular VM. | |
1199 | */ | |
1200 | static int avic_ga_log_notifier(u32 ga_tag) | |
1201 | { | |
1202 | unsigned long flags; | |
81811c16 | 1203 | struct kvm_svm *kvm_svm; |
5881f737 SS |
1204 | struct kvm_vcpu *vcpu = NULL; |
1205 | u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag); | |
1206 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag); | |
1207 | ||
1208 | pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id); | |
1209 | ||
1210 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
81811c16 SC |
1211 | hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) { |
1212 | if (kvm_svm->avic_vm_id != vm_id) | |
5881f737 | 1213 | continue; |
81811c16 | 1214 | vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id); |
5881f737 SS |
1215 | break; |
1216 | } | |
1217 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1218 | ||
5881f737 SS |
1219 | /* Note: |
1220 | * At this point, the IOMMU should have already set the pending | |
1221 | * bit in the vAPIC backing page. So, we just need to schedule | |
1222 | * in the vcpu. | |
1223 | */ | |
1cf53587 | 1224 | if (vcpu) |
5881f737 SS |
1225 | kvm_vcpu_wake_up(vcpu); |
1226 | ||
1227 | return 0; | |
1228 | } | |
1229 | ||
e9df0942 BS |
1230 | static __init int sev_hardware_setup(void) |
1231 | { | |
1232 | struct sev_user_data_status *status; | |
1233 | int rc; | |
1234 | ||
1235 | /* Maximum number of encrypted guests supported simultaneously */ | |
1236 | max_sev_asid = cpuid_ecx(0x8000001F); | |
1237 | ||
1238 | if (!max_sev_asid) | |
1239 | return 1; | |
1240 | ||
1654efcb BS |
1241 | /* Minimum ASID value that should be used for SEV guest */ |
1242 | min_sev_asid = cpuid_edx(0x8000001F); | |
1243 | ||
33af3a7e | 1244 | /* Initialize SEV ASID bitmaps */ |
a101c9d6 | 1245 | sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL); |
1654efcb BS |
1246 | if (!sev_asid_bitmap) |
1247 | return 1; | |
1248 | ||
33af3a7e TL |
1249 | sev_reclaim_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL); |
1250 | if (!sev_reclaim_asid_bitmap) | |
1251 | return 1; | |
1252 | ||
e9df0942 BS |
1253 | status = kmalloc(sizeof(*status), GFP_KERNEL); |
1254 | if (!status) | |
1255 | return 1; | |
1256 | ||
1257 | /* | |
1258 | * Check SEV platform status. | |
1259 | * | |
1260 | * PLATFORM_STATUS can be called in any state, if we failed to query | |
1261 | * the PLATFORM status then either PSP firmware does not support SEV | |
1262 | * feature or SEV firmware is dead. | |
1263 | */ | |
1264 | rc = sev_platform_status(status, NULL); | |
1265 | if (rc) | |
1266 | goto err; | |
1267 | ||
1268 | pr_info("SEV supported\n"); | |
1269 | ||
1270 | err: | |
1271 | kfree(status); | |
1272 | return rc; | |
1273 | } | |
1274 | ||
8566ac8b BM |
1275 | static void grow_ple_window(struct kvm_vcpu *vcpu) |
1276 | { | |
1277 | struct vcpu_svm *svm = to_svm(vcpu); | |
1278 | struct vmcb_control_area *control = &svm->vmcb->control; | |
1279 | int old = control->pause_filter_count; | |
1280 | ||
1281 | control->pause_filter_count = __grow_ple_window(old, | |
1282 | pause_filter_count, | |
1283 | pause_filter_count_grow, | |
1284 | pause_filter_count_max); | |
1285 | ||
4f75bcc3 | 1286 | if (control->pause_filter_count != old) { |
8566ac8b | 1287 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
4f75bcc3 PX |
1288 | trace_kvm_ple_window_update(vcpu->vcpu_id, |
1289 | control->pause_filter_count, old); | |
1290 | } | |
8566ac8b BM |
1291 | } |
1292 | ||
1293 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
1294 | { | |
1295 | struct vcpu_svm *svm = to_svm(vcpu); | |
1296 | struct vmcb_control_area *control = &svm->vmcb->control; | |
1297 | int old = control->pause_filter_count; | |
1298 | ||
1299 | control->pause_filter_count = | |
1300 | __shrink_ple_window(old, | |
1301 | pause_filter_count, | |
1302 | pause_filter_count_shrink, | |
1303 | pause_filter_count); | |
4f75bcc3 | 1304 | if (control->pause_filter_count != old) { |
8566ac8b | 1305 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
4f75bcc3 PX |
1306 | trace_kvm_ple_window_update(vcpu->vcpu_id, |
1307 | control->pause_filter_count, old); | |
1308 | } | |
8566ac8b BM |
1309 | } |
1310 | ||
52918ed5 TL |
1311 | /* |
1312 | * The default MMIO mask is a single bit (excluding the present bit), | |
1313 | * which could conflict with the memory encryption bit. Check for | |
1314 | * memory encryption support and override the default MMIO mask if | |
1315 | * memory encryption is enabled. | |
1316 | */ | |
1317 | static __init void svm_adjust_mmio_mask(void) | |
1318 | { | |
1319 | unsigned int enc_bit, mask_bit; | |
1320 | u64 msr, mask; | |
1321 | ||
1322 | /* If there is no memory encryption support, use existing mask */ | |
1323 | if (cpuid_eax(0x80000000) < 0x8000001f) | |
1324 | return; | |
1325 | ||
1326 | /* If memory encryption is not enabled, use existing mask */ | |
1327 | rdmsrl(MSR_K8_SYSCFG, msr); | |
1328 | if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) | |
1329 | return; | |
1330 | ||
1331 | enc_bit = cpuid_ebx(0x8000001f) & 0x3f; | |
1332 | mask_bit = boot_cpu_data.x86_phys_bits; | |
1333 | ||
1334 | /* Increment the mask bit if it is the same as the encryption bit */ | |
1335 | if (enc_bit == mask_bit) | |
1336 | mask_bit++; | |
1337 | ||
1338 | /* | |
1339 | * If the mask bit location is below 52, then some bits above the | |
1340 | * physical addressing limit will always be reserved, so use the | |
1341 | * rsvd_bits() function to generate the mask. This mask, along with | |
1342 | * the present bit, will be used to generate a page fault with | |
1343 | * PFER.RSV = 1. | |
1344 | * | |
1345 | * If the mask bit location is 52 (or above), then clear the mask. | |
1346 | */ | |
1347 | mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0; | |
1348 | ||
1349 | kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK); | |
1350 | } | |
1351 | ||
6aa8b732 AK |
1352 | static __init int svm_hardware_setup(void) |
1353 | { | |
1354 | int cpu; | |
1355 | struct page *iopm_pages; | |
f65c229c | 1356 | void *iopm_va; |
6aa8b732 AK |
1357 | int r; |
1358 | ||
6aa8b732 AK |
1359 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
1360 | ||
1361 | if (!iopm_pages) | |
1362 | return -ENOMEM; | |
c8681339 AL |
1363 | |
1364 | iopm_va = page_address(iopm_pages); | |
1365 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
1366 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
1367 | ||
323c3d80 JR |
1368 | init_msrpm_offsets(); |
1369 | ||
50a37eb4 JR |
1370 | if (boot_cpu_has(X86_FEATURE_NX)) |
1371 | kvm_enable_efer_bits(EFER_NX); | |
1372 | ||
1b2fd70c AG |
1373 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
1374 | kvm_enable_efer_bits(EFER_FFXSR); | |
1375 | ||
92a1f12d | 1376 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 1377 | kvm_has_tsc_control = true; |
bc9b961b HZ |
1378 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
1379 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
1380 | } |
1381 | ||
8566ac8b BM |
1382 | /* Check for pause filtering support */ |
1383 | if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { | |
1384 | pause_filter_count = 0; | |
1385 | pause_filter_thresh = 0; | |
1386 | } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) { | |
1387 | pause_filter_thresh = 0; | |
1388 | } | |
1389 | ||
236de055 AG |
1390 | if (nested) { |
1391 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 1392 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
1393 | } |
1394 | ||
e9df0942 BS |
1395 | if (sev) { |
1396 | if (boot_cpu_has(X86_FEATURE_SEV) && | |
1397 | IS_ENABLED(CONFIG_KVM_AMD_SEV)) { | |
1398 | r = sev_hardware_setup(); | |
1399 | if (r) | |
1400 | sev = false; | |
1401 | } else { | |
1402 | sev = false; | |
1403 | } | |
1404 | } | |
1405 | ||
52918ed5 TL |
1406 | svm_adjust_mmio_mask(); |
1407 | ||
3230bb47 | 1408 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1409 | r = svm_cpu_init(cpu); |
1410 | if (r) | |
f65c229c | 1411 | goto err; |
6aa8b732 | 1412 | } |
33bd6a0b | 1413 | |
2a6b20b8 | 1414 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
1415 | npt_enabled = false; |
1416 | ||
6c7dac72 JR |
1417 | if (npt_enabled && !npt) { |
1418 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
1419 | npt_enabled = false; | |
1420 | } | |
1421 | ||
18552672 | 1422 | if (npt_enabled) { |
e3da3acd | 1423 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 1424 | kvm_enable_tdp(); |
5f4cb662 JR |
1425 | } else |
1426 | kvm_disable_tdp(); | |
e3da3acd | 1427 | |
d647eb63 PB |
1428 | if (nrips) { |
1429 | if (!boot_cpu_has(X86_FEATURE_NRIPS)) | |
1430 | nrips = false; | |
1431 | } | |
1432 | ||
5b8abf1f SS |
1433 | if (avic) { |
1434 | if (!npt_enabled || | |
1435 | !boot_cpu_has(X86_FEATURE_AVIC) || | |
5881f737 | 1436 | !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { |
5b8abf1f | 1437 | avic = false; |
5881f737 | 1438 | } else { |
5b8abf1f | 1439 | pr_info("AVIC enabled\n"); |
5881f737 | 1440 | |
5881f737 SS |
1441 | amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); |
1442 | } | |
5b8abf1f | 1443 | } |
44a95dae | 1444 | |
89c8a498 JN |
1445 | if (vls) { |
1446 | if (!npt_enabled || | |
5442c269 | 1447 | !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) || |
89c8a498 JN |
1448 | !IS_ENABLED(CONFIG_X86_64)) { |
1449 | vls = false; | |
1450 | } else { | |
1451 | pr_info("Virtual VMLOAD VMSAVE supported\n"); | |
1452 | } | |
1453 | } | |
1454 | ||
640bd6e5 JN |
1455 | if (vgif) { |
1456 | if (!boot_cpu_has(X86_FEATURE_VGIF)) | |
1457 | vgif = false; | |
1458 | else | |
1459 | pr_info("Virtual GIF supported\n"); | |
1460 | } | |
1461 | ||
6aa8b732 AK |
1462 | return 0; |
1463 | ||
f65c229c | 1464 | err: |
6aa8b732 AK |
1465 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
1466 | iopm_base = 0; | |
1467 | return r; | |
1468 | } | |
1469 | ||
1470 | static __exit void svm_hardware_unsetup(void) | |
1471 | { | |
0da1db75 JR |
1472 | int cpu; |
1473 | ||
33af3a7e | 1474 | if (svm_sev_enabled()) { |
a101c9d6 | 1475 | bitmap_free(sev_asid_bitmap); |
33af3a7e TL |
1476 | bitmap_free(sev_reclaim_asid_bitmap); |
1477 | ||
1478 | sev_flush_asids(); | |
1479 | } | |
1654efcb | 1480 | |
3230bb47 | 1481 | for_each_possible_cpu(cpu) |
0da1db75 JR |
1482 | svm_cpu_uninit(cpu); |
1483 | ||
6aa8b732 | 1484 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 1485 | iopm_base = 0; |
6aa8b732 AK |
1486 | } |
1487 | ||
1488 | static void init_seg(struct vmcb_seg *seg) | |
1489 | { | |
1490 | seg->selector = 0; | |
1491 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1492 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1493 | seg->limit = 0xffff; |
1494 | seg->base = 0; | |
1495 | } | |
1496 | ||
1497 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1498 | { | |
1499 | seg->selector = 0; | |
1500 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1501 | seg->limit = 0xffff; | |
1502 | seg->base = 0; | |
1503 | } | |
1504 | ||
e79f245d KA |
1505 | static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu) |
1506 | { | |
1507 | struct vcpu_svm *svm = to_svm(vcpu); | |
1508 | ||
1509 | if (is_guest_mode(vcpu)) | |
1510 | return svm->nested.hsave->control.tsc_offset; | |
1511 | ||
1512 | return vcpu->arch.tsc_offset; | |
1513 | } | |
1514 | ||
326e7425 | 1515 | static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
f4e1b3c8 ZA |
1516 | { |
1517 | struct vcpu_svm *svm = to_svm(vcpu); | |
1518 | u64 g_tsc_offset = 0; | |
1519 | ||
2030753d | 1520 | if (is_guest_mode(vcpu)) { |
e79f245d | 1521 | /* Write L1's TSC offset. */ |
f4e1b3c8 ZA |
1522 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1523 | svm->nested.hsave->control.tsc_offset; | |
1524 | svm->nested.hsave->control.tsc_offset = offset; | |
45c3af97 PB |
1525 | } |
1526 | ||
1527 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1528 | svm->vmcb->control.tsc_offset - g_tsc_offset, | |
1529 | offset); | |
f4e1b3c8 ZA |
1530 | |
1531 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1532 | |
1533 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
326e7425 | 1534 | return svm->vmcb->control.tsc_offset; |
f4e1b3c8 ZA |
1535 | } |
1536 | ||
44a95dae SS |
1537 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1538 | { | |
1539 | struct vmcb *vmcb = svm->vmcb; | |
81811c16 | 1540 | struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm); |
d0ec49d4 | 1541 | phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page)); |
81811c16 SC |
1542 | phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page)); |
1543 | phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page)); | |
44a95dae SS |
1544 | |
1545 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1546 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1547 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1548 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
6c3e4422 SS |
1549 | if (kvm_apicv_activated(svm->vcpu.kvm)) |
1550 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
1551 | else | |
1552 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
44a95dae SS |
1553 | } |
1554 | ||
5690891b | 1555 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1556 | { |
e6101a96 JR |
1557 | struct vmcb_control_area *control = &svm->vmcb->control; |
1558 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1559 | |
4ee546b4 | 1560 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1561 | |
4ee546b4 RJ |
1562 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1563 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1564 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1565 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1566 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1567 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
3bbf3565 SS |
1568 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
1569 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1570 | |
5315c716 | 1571 | set_dr_intercepts(svm); |
6aa8b732 | 1572 | |
18c918c5 JR |
1573 | set_exception_intercept(svm, PF_VECTOR); |
1574 | set_exception_intercept(svm, UD_VECTOR); | |
1575 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1576 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1577 | set_exception_intercept(svm, DB_VECTOR); |
9718420e LA |
1578 | /* |
1579 | * Guest access to VMware backdoor ports could legitimately | |
1580 | * trigger #GP because of TSS I/O permission bitmap. | |
1581 | * We intercept those #GP and allow access to them anyway | |
1582 | * as VMware does. | |
1583 | */ | |
1584 | if (enable_vmware_backdoor) | |
1585 | set_exception_intercept(svm, GP_VECTOR); | |
6aa8b732 | 1586 | |
8a05a1b8 JR |
1587 | set_intercept(svm, INTERCEPT_INTR); |
1588 | set_intercept(svm, INTERCEPT_NMI); | |
1589 | set_intercept(svm, INTERCEPT_SMI); | |
1590 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1591 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1592 | set_intercept(svm, INTERCEPT_CPUID); |
1593 | set_intercept(svm, INTERCEPT_INVD); | |
8a05a1b8 JR |
1594 | set_intercept(svm, INTERCEPT_INVLPG); |
1595 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1596 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1597 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1598 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1599 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1600 | set_intercept(svm, INTERCEPT_VMRUN); | |
1601 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1602 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1603 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1604 | set_intercept(svm, INTERCEPT_STGI); | |
1605 | set_intercept(svm, INTERCEPT_CLGI); | |
1606 | set_intercept(svm, INTERCEPT_SKINIT); | |
1607 | set_intercept(svm, INTERCEPT_WBINVD); | |
81dd35d4 | 1608 | set_intercept(svm, INTERCEPT_XSETBV); |
0cb8410b | 1609 | set_intercept(svm, INTERCEPT_RDPRU); |
7607b717 | 1610 | set_intercept(svm, INTERCEPT_RSM); |
6aa8b732 | 1611 | |
4d5422ce | 1612 | if (!kvm_mwait_in_guest(svm->vcpu.kvm)) { |
668fffa3 MT |
1613 | set_intercept(svm, INTERCEPT_MONITOR); |
1614 | set_intercept(svm, INTERCEPT_MWAIT); | |
1615 | } | |
1616 | ||
caa057a2 WL |
1617 | if (!kvm_hlt_in_guest(svm->vcpu.kvm)) |
1618 | set_intercept(svm, INTERCEPT_HLT); | |
1619 | ||
d0ec49d4 TL |
1620 | control->iopm_base_pa = __sme_set(iopm_base); |
1621 | control->msrpm_base_pa = __sme_set(__pa(svm->msrpm)); | |
6aa8b732 AK |
1622 | control->int_ctl = V_INTR_MASKING_MASK; |
1623 | ||
1624 | init_seg(&save->es); | |
1625 | init_seg(&save->ss); | |
1626 | init_seg(&save->ds); | |
1627 | init_seg(&save->fs); | |
1628 | init_seg(&save->gs); | |
1629 | ||
1630 | save->cs.selector = 0xf000; | |
04b66839 | 1631 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1632 | /* Executable/Readable Code Segment */ |
1633 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1634 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1635 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1636 | |
1637 | save->gdtr.limit = 0xffff; | |
1638 | save->idtr.limit = 0xffff; | |
1639 | ||
1640 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1641 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1642 | ||
5690891b | 1643 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1644 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1645 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1646 | save->rip = 0x0000fff0; |
5fdbf976 | 1647 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1648 | |
e0231715 | 1649 | /* |
18fa000a | 1650 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1651 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1652 | */ |
79a8059d | 1653 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1654 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1655 | |
66aee91a | 1656 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1657 | /* rdx = ?? */ |
709ddebf JR |
1658 | |
1659 | if (npt_enabled) { | |
1660 | /* Setup VMCB for Nested Paging */ | |
cea3a19b | 1661 | control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE; |
8a05a1b8 | 1662 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1663 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1664 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1665 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1666 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1667 | save->cr3 = 0; |
1668 | save->cr4 = 0; | |
1669 | } | |
f40f6a45 | 1670 | svm->asid_generation = 0; |
1371d904 | 1671 | |
e6aa9abd | 1672 | svm->nested.vmcb = 0; |
2af9194d JR |
1673 | svm->vcpu.arch.hflags = 0; |
1674 | ||
8566ac8b BM |
1675 | if (pause_filter_count) { |
1676 | control->pause_filter_count = pause_filter_count; | |
1677 | if (pause_filter_thresh) | |
1678 | control->pause_filter_thresh = pause_filter_thresh; | |
8a05a1b8 | 1679 | set_intercept(svm, INTERCEPT_PAUSE); |
8566ac8b BM |
1680 | } else { |
1681 | clr_intercept(svm, INTERCEPT_PAUSE); | |
565d0998 ML |
1682 | } |
1683 | ||
67034bb9 | 1684 | if (kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
1685 | avic_init_vmcb(svm); |
1686 | ||
89c8a498 JN |
1687 | /* |
1688 | * If hardware supports Virtual VMLOAD VMSAVE then enable it | |
1689 | * in VMCB and clear intercepts to avoid #VMEXIT. | |
1690 | */ | |
1691 | if (vls) { | |
1692 | clr_intercept(svm, INTERCEPT_VMLOAD); | |
1693 | clr_intercept(svm, INTERCEPT_VMSAVE); | |
1694 | svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; | |
1695 | } | |
1696 | ||
640bd6e5 JN |
1697 | if (vgif) { |
1698 | clr_intercept(svm, INTERCEPT_STGI); | |
1699 | clr_intercept(svm, INTERCEPT_CLGI); | |
1700 | svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK; | |
1701 | } | |
1702 | ||
35c6f649 | 1703 | if (sev_guest(svm->vcpu.kvm)) { |
1654efcb | 1704 | svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE; |
35c6f649 BS |
1705 | clr_exception_intercept(svm, UD_VECTOR); |
1706 | } | |
1654efcb | 1707 | |
8d28fec4 RJ |
1708 | mark_all_dirty(svm->vmcb); |
1709 | ||
2af9194d | 1710 | enable_gif(svm); |
44a95dae SS |
1711 | |
1712 | } | |
1713 | ||
d3e7dec0 DC |
1714 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, |
1715 | unsigned int index) | |
44a95dae SS |
1716 | { |
1717 | u64 *avic_physical_id_table; | |
81811c16 | 1718 | struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm); |
44a95dae SS |
1719 | |
1720 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1721 | return NULL; | |
1722 | ||
81811c16 | 1723 | avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page); |
44a95dae SS |
1724 | |
1725 | return &avic_physical_id_table[index]; | |
1726 | } | |
1727 | ||
1728 | /** | |
1729 | * Note: | |
1730 | * AVIC hardware walks the nested page table to check permissions, | |
1731 | * but does not use the SPA address specified in the leaf page | |
1732 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1733 | * field of the VMCB. Therefore, we set up the | |
1734 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1735 | */ | |
dcbcfa28 | 1736 | static int avic_update_access_page(struct kvm *kvm, bool activate) |
44a95dae | 1737 | { |
30510387 | 1738 | int ret = 0; |
44a95dae | 1739 | |
30510387 | 1740 | mutex_lock(&kvm->slots_lock); |
dcbcfa28 | 1741 | if (kvm->arch.apic_access_page_done == activate) |
30510387 | 1742 | goto out; |
44a95dae | 1743 | |
30510387 WW |
1744 | ret = __x86_set_memory_region(kvm, |
1745 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1746 | APIC_DEFAULT_PHYS_BASE, | |
dcbcfa28 | 1747 | activate ? PAGE_SIZE : 0); |
44a95dae | 1748 | if (ret) |
30510387 | 1749 | goto out; |
44a95dae | 1750 | |
dcbcfa28 | 1751 | kvm->arch.apic_access_page_done = activate; |
30510387 WW |
1752 | out: |
1753 | mutex_unlock(&kvm->slots_lock); | |
1754 | return ret; | |
44a95dae SS |
1755 | } |
1756 | ||
1757 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1758 | { | |
44a95dae SS |
1759 | u64 *entry, new_entry; |
1760 | int id = vcpu->vcpu_id; | |
1761 | struct vcpu_svm *svm = to_svm(vcpu); | |
1762 | ||
44a95dae SS |
1763 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) |
1764 | return -EINVAL; | |
1765 | ||
1766 | if (!svm->vcpu.arch.apic->regs) | |
1767 | return -EINVAL; | |
1768 | ||
6c3e4422 SS |
1769 | if (kvm_apicv_activated(vcpu->kvm)) { |
1770 | int ret; | |
1771 | ||
1772 | ret = avic_update_access_page(vcpu->kvm, true); | |
1773 | if (ret) | |
1774 | return ret; | |
1775 | } | |
1776 | ||
44a95dae SS |
1777 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); |
1778 | ||
1779 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1780 | entry = avic_get_physical_id_entry(vcpu, id); | |
1781 | if (!entry) | |
1782 | return -EINVAL; | |
1783 | ||
d0ec49d4 TL |
1784 | new_entry = __sme_set((page_to_phys(svm->avic_backing_page) & |
1785 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1786 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); | |
44a95dae SS |
1787 | WRITE_ONCE(*entry, new_entry); |
1788 | ||
1789 | svm->avic_physical_id_cache = entry; | |
1790 | ||
1791 | return 0; | |
1792 | } | |
1793 | ||
e3b9a9e1 | 1794 | static void sev_asid_free(int asid) |
1654efcb | 1795 | { |
70cd94e6 BS |
1796 | struct svm_cpu_data *sd; |
1797 | int cpu, pos; | |
1654efcb | 1798 | |
e3b9a9e1 TL |
1799 | mutex_lock(&sev_bitmap_lock); |
1800 | ||
1654efcb | 1801 | pos = asid - 1; |
33af3a7e | 1802 | __set_bit(pos, sev_reclaim_asid_bitmap); |
70cd94e6 BS |
1803 | |
1804 | for_each_possible_cpu(cpu) { | |
1805 | sd = per_cpu(svm_data, cpu); | |
1806 | sd->sev_vmcbs[pos] = NULL; | |
1807 | } | |
1654efcb | 1808 | |
e3b9a9e1 | 1809 | mutex_unlock(&sev_bitmap_lock); |
1654efcb BS |
1810 | } |
1811 | ||
59414c98 BS |
1812 | static void sev_unbind_asid(struct kvm *kvm, unsigned int handle) |
1813 | { | |
1814 | struct sev_data_decommission *decommission; | |
1815 | struct sev_data_deactivate *data; | |
1816 | ||
1817 | if (!handle) | |
1818 | return; | |
1819 | ||
1820 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1821 | if (!data) | |
1822 | return; | |
1823 | ||
1824 | /* deactivate handle */ | |
1825 | data->handle = handle; | |
83af5e65 | 1826 | |
33af3a7e TL |
1827 | /* Guard DEACTIVATE against WBINVD/DF_FLUSH used in ASID recycling */ |
1828 | down_read(&sev_deactivate_lock); | |
59414c98 | 1829 | sev_guest_deactivate(data, NULL); |
33af3a7e | 1830 | up_read(&sev_deactivate_lock); |
83af5e65 | 1831 | |
59414c98 BS |
1832 | kfree(data); |
1833 | ||
1834 | decommission = kzalloc(sizeof(*decommission), GFP_KERNEL); | |
1835 | if (!decommission) | |
1836 | return; | |
1837 | ||
1838 | /* decommission handle */ | |
1839 | decommission->handle = handle; | |
1840 | sev_guest_decommission(decommission, NULL); | |
1841 | ||
1842 | kfree(decommission); | |
1843 | } | |
1844 | ||
89c50580 BS |
1845 | static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr, |
1846 | unsigned long ulen, unsigned long *n, | |
1847 | int write) | |
1848 | { | |
81811c16 | 1849 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
89c50580 BS |
1850 | unsigned long npages, npinned, size; |
1851 | unsigned long locked, lock_limit; | |
1852 | struct page **pages; | |
86bf20cb DC |
1853 | unsigned long first, last; |
1854 | ||
1855 | if (ulen == 0 || uaddr + ulen < uaddr) | |
1856 | return NULL; | |
89c50580 BS |
1857 | |
1858 | /* Calculate number of pages. */ | |
1859 | first = (uaddr & PAGE_MASK) >> PAGE_SHIFT; | |
1860 | last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT; | |
1861 | npages = (last - first + 1); | |
1862 | ||
1863 | locked = sev->pages_locked + npages; | |
1864 | lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT; | |
1865 | if (locked > lock_limit && !capable(CAP_IPC_LOCK)) { | |
1866 | pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit); | |
1867 | return NULL; | |
1868 | } | |
1869 | ||
1870 | /* Avoid using vmalloc for smaller buffers. */ | |
1871 | size = npages * sizeof(struct page *); | |
1872 | if (size > PAGE_SIZE) | |
1ec69647 BG |
1873 | pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO, |
1874 | PAGE_KERNEL); | |
89c50580 | 1875 | else |
1ec69647 | 1876 | pages = kmalloc(size, GFP_KERNEL_ACCOUNT); |
89c50580 BS |
1877 | |
1878 | if (!pages) | |
1879 | return NULL; | |
1880 | ||
1881 | /* Pin the user virtual address. */ | |
73b0140b | 1882 | npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages); |
89c50580 BS |
1883 | if (npinned != npages) { |
1884 | pr_err("SEV: Failure locking %lu pages.\n", npages); | |
1885 | goto err; | |
1886 | } | |
1887 | ||
1888 | *n = npages; | |
1889 | sev->pages_locked = locked; | |
1890 | ||
1891 | return pages; | |
1892 | ||
1893 | err: | |
1894 | if (npinned > 0) | |
1895 | release_pages(pages, npinned); | |
1896 | ||
1897 | kvfree(pages); | |
1898 | return NULL; | |
1899 | } | |
1900 | ||
1901 | static void sev_unpin_memory(struct kvm *kvm, struct page **pages, | |
1902 | unsigned long npages) | |
1903 | { | |
81811c16 | 1904 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
89c50580 BS |
1905 | |
1906 | release_pages(pages, npages); | |
1907 | kvfree(pages); | |
1908 | sev->pages_locked -= npages; | |
1909 | } | |
1910 | ||
1911 | static void sev_clflush_pages(struct page *pages[], unsigned long npages) | |
1912 | { | |
1913 | uint8_t *page_virtual; | |
1914 | unsigned long i; | |
1915 | ||
1916 | if (npages == 0 || pages == NULL) | |
1917 | return; | |
1918 | ||
1919 | for (i = 0; i < npages; i++) { | |
1920 | page_virtual = kmap_atomic(pages[i]); | |
1921 | clflush_cache_range(page_virtual, PAGE_SIZE); | |
1922 | kunmap_atomic(page_virtual); | |
1923 | } | |
1924 | } | |
1925 | ||
1e80fdc0 BS |
1926 | static void __unregister_enc_region_locked(struct kvm *kvm, |
1927 | struct enc_region *region) | |
1928 | { | |
1929 | /* | |
1930 | * The guest may change the memory encryption attribute from C=0 -> C=1 | |
1931 | * or vice versa for this memory range. Lets make sure caches are | |
1932 | * flushed to ensure that guest data gets written into memory with | |
1933 | * correct C-bit. | |
1934 | */ | |
1935 | sev_clflush_pages(region->pages, region->npages); | |
1936 | ||
1937 | sev_unpin_memory(kvm, region->pages, region->npages); | |
1938 | list_del(®ion->list); | |
1939 | kfree(region); | |
1940 | } | |
1941 | ||
434a1e94 SC |
1942 | static struct kvm *svm_vm_alloc(void) |
1943 | { | |
1ec69647 BG |
1944 | struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm), |
1945 | GFP_KERNEL_ACCOUNT | __GFP_ZERO, | |
1946 | PAGE_KERNEL); | |
81811c16 | 1947 | return &kvm_svm->kvm; |
434a1e94 SC |
1948 | } |
1949 | ||
1950 | static void svm_vm_free(struct kvm *kvm) | |
1951 | { | |
d1e5b0e9 | 1952 | vfree(to_kvm_svm(kvm)); |
434a1e94 SC |
1953 | } |
1954 | ||
1654efcb BS |
1955 | static void sev_vm_destroy(struct kvm *kvm) |
1956 | { | |
81811c16 | 1957 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1e80fdc0 BS |
1958 | struct list_head *head = &sev->regions_list; |
1959 | struct list_head *pos, *q; | |
59414c98 | 1960 | |
1654efcb BS |
1961 | if (!sev_guest(kvm)) |
1962 | return; | |
1963 | ||
1e80fdc0 BS |
1964 | mutex_lock(&kvm->lock); |
1965 | ||
1966 | /* | |
1967 | * if userspace was terminated before unregistering the memory regions | |
1968 | * then lets unpin all the registered memory. | |
1969 | */ | |
1970 | if (!list_empty(head)) { | |
1971 | list_for_each_safe(pos, q, head) { | |
1972 | __unregister_enc_region_locked(kvm, | |
1973 | list_entry(pos, struct enc_region, list)); | |
1974 | } | |
1975 | } | |
1976 | ||
1977 | mutex_unlock(&kvm->lock); | |
1978 | ||
59414c98 | 1979 | sev_unbind_asid(kvm, sev->handle); |
e3b9a9e1 | 1980 | sev_asid_free(sev->asid); |
1654efcb BS |
1981 | } |
1982 | ||
44a95dae SS |
1983 | static void avic_vm_destroy(struct kvm *kvm) |
1984 | { | |
5881f737 | 1985 | unsigned long flags; |
81811c16 | 1986 | struct kvm_svm *kvm_svm = to_kvm_svm(kvm); |
44a95dae | 1987 | |
3863dff0 DV |
1988 | if (!avic) |
1989 | return; | |
1990 | ||
81811c16 SC |
1991 | if (kvm_svm->avic_logical_id_table_page) |
1992 | __free_page(kvm_svm->avic_logical_id_table_page); | |
1993 | if (kvm_svm->avic_physical_id_table_page) | |
1994 | __free_page(kvm_svm->avic_physical_id_table_page); | |
5881f737 SS |
1995 | |
1996 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
81811c16 | 1997 | hash_del(&kvm_svm->hnode); |
5881f737 | 1998 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); |
44a95dae SS |
1999 | } |
2000 | ||
1654efcb BS |
2001 | static void svm_vm_destroy(struct kvm *kvm) |
2002 | { | |
2003 | avic_vm_destroy(kvm); | |
2004 | sev_vm_destroy(kvm); | |
2005 | } | |
2006 | ||
44a95dae SS |
2007 | static int avic_vm_init(struct kvm *kvm) |
2008 | { | |
5881f737 | 2009 | unsigned long flags; |
3f0d4db7 | 2010 | int err = -ENOMEM; |
81811c16 SC |
2011 | struct kvm_svm *kvm_svm = to_kvm_svm(kvm); |
2012 | struct kvm_svm *k2; | |
44a95dae SS |
2013 | struct page *p_page; |
2014 | struct page *l_page; | |
3f0d4db7 | 2015 | u32 vm_id; |
44a95dae SS |
2016 | |
2017 | if (!avic) | |
2018 | return 0; | |
2019 | ||
2020 | /* Allocating physical APIC ID table (4KB) */ | |
1ec69647 | 2021 | p_page = alloc_page(GFP_KERNEL_ACCOUNT); |
44a95dae SS |
2022 | if (!p_page) |
2023 | goto free_avic; | |
2024 | ||
81811c16 | 2025 | kvm_svm->avic_physical_id_table_page = p_page; |
44a95dae SS |
2026 | clear_page(page_address(p_page)); |
2027 | ||
2028 | /* Allocating logical APIC ID table (4KB) */ | |
1ec69647 | 2029 | l_page = alloc_page(GFP_KERNEL_ACCOUNT); |
44a95dae SS |
2030 | if (!l_page) |
2031 | goto free_avic; | |
2032 | ||
81811c16 | 2033 | kvm_svm->avic_logical_id_table_page = l_page; |
44a95dae SS |
2034 | clear_page(page_address(l_page)); |
2035 | ||
5881f737 | 2036 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); |
3f0d4db7 DV |
2037 | again: |
2038 | vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK; | |
2039 | if (vm_id == 0) { /* id is 1-based, zero is not okay */ | |
2040 | next_vm_id_wrapped = 1; | |
2041 | goto again; | |
2042 | } | |
2043 | /* Is it still in use? Only possible if wrapped at least once */ | |
2044 | if (next_vm_id_wrapped) { | |
81811c16 SC |
2045 | hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) { |
2046 | if (k2->avic_vm_id == vm_id) | |
3f0d4db7 DV |
2047 | goto again; |
2048 | } | |
2049 | } | |
81811c16 SC |
2050 | kvm_svm->avic_vm_id = vm_id; |
2051 | hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id); | |
5881f737 SS |
2052 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); |
2053 | ||
44a95dae SS |
2054 | return 0; |
2055 | ||
2056 | free_avic: | |
2057 | avic_vm_destroy(kvm); | |
2058 | return err; | |
6aa8b732 AK |
2059 | } |
2060 | ||
4e19c36f SS |
2061 | static int svm_vm_init(struct kvm *kvm) |
2062 | { | |
2063 | if (avic) { | |
2064 | int ret = avic_vm_init(kvm); | |
2065 | if (ret) | |
2066 | return ret; | |
2067 | } | |
2068 | ||
2069 | kvm_apicv_init(kvm, avic && irqchip_split(kvm)); | |
2070 | return 0; | |
2071 | } | |
2072 | ||
411b44ba SS |
2073 | static inline int |
2074 | avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) | |
8221c137 | 2075 | { |
411b44ba SS |
2076 | int ret = 0; |
2077 | unsigned long flags; | |
2078 | struct amd_svm_iommu_ir *ir; | |
8221c137 SS |
2079 | struct vcpu_svm *svm = to_svm(vcpu); |
2080 | ||
411b44ba SS |
2081 | if (!kvm_arch_has_assigned_device(vcpu->kvm)) |
2082 | return 0; | |
8221c137 | 2083 | |
411b44ba SS |
2084 | /* |
2085 | * Here, we go through the per-vcpu ir_list to update all existing | |
2086 | * interrupt remapping table entry targeting this vcpu. | |
2087 | */ | |
2088 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
8221c137 | 2089 | |
411b44ba SS |
2090 | if (list_empty(&svm->ir_list)) |
2091 | goto out; | |
8221c137 | 2092 | |
411b44ba SS |
2093 | list_for_each_entry(ir, &svm->ir_list, node) { |
2094 | ret = amd_iommu_update_ga(cpu, r, ir->data); | |
2095 | if (ret) | |
2096 | break; | |
2097 | } | |
2098 | out: | |
2099 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
2100 | return ret; | |
8221c137 SS |
2101 | } |
2102 | ||
2103 | static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
2104 | { | |
2105 | u64 entry; | |
2106 | /* ID = 0xff (broadcast), ID > 0xff (reserved) */ | |
7d669f50 | 2107 | int h_physical_id = kvm_cpu_get_apicid(cpu); |
8221c137 SS |
2108 | struct vcpu_svm *svm = to_svm(vcpu); |
2109 | ||
2110 | if (!kvm_vcpu_apicv_active(vcpu)) | |
2111 | return; | |
2112 | ||
c9bcd3e3 SS |
2113 | /* |
2114 | * Since the host physical APIC id is 8 bits, | |
2115 | * we can support host APIC ID upto 255. | |
2116 | */ | |
2117 | if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK)) | |
8221c137 SS |
2118 | return; |
2119 | ||
2120 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
2121 | WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
2122 | ||
2123 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; | |
2124 | entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); | |
2125 | ||
2126 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
2127 | if (svm->avic_is_running) | |
2128 | entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
2129 | ||
2130 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
411b44ba SS |
2131 | avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, |
2132 | svm->avic_is_running); | |
8221c137 SS |
2133 | } |
2134 | ||
2135 | static void avic_vcpu_put(struct kvm_vcpu *vcpu) | |
2136 | { | |
2137 | u64 entry; | |
2138 | struct vcpu_svm *svm = to_svm(vcpu); | |
2139 | ||
2140 | if (!kvm_vcpu_apicv_active(vcpu)) | |
2141 | return; | |
2142 | ||
2143 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
411b44ba SS |
2144 | if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) |
2145 | avic_update_iommu_vcpu_affinity(vcpu, -1, 0); | |
2146 | ||
8221c137 SS |
2147 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; |
2148 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
6aa8b732 AK |
2149 | } |
2150 | ||
411b44ba SS |
2151 | /** |
2152 | * This function is called during VCPU halt/unhalt. | |
2153 | */ | |
2154 | static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) | |
2155 | { | |
2156 | struct vcpu_svm *svm = to_svm(vcpu); | |
2157 | ||
2158 | svm->avic_is_running = is_run; | |
2159 | if (is_run) | |
2160 | avic_vcpu_load(vcpu, vcpu->cpu); | |
2161 | else | |
2162 | avic_vcpu_put(vcpu); | |
2163 | } | |
2164 | ||
d28bc9dd | 2165 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
2166 | { |
2167 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
2168 | u32 dummy; |
2169 | u32 eax = 1; | |
04d2cc77 | 2170 | |
518e7b94 | 2171 | vcpu->arch.microcode_version = 0x01000065; |
b2ac58f9 | 2172 | svm->spec_ctrl = 0; |
ccbcd267 | 2173 | svm->virt_spec_ctrl = 0; |
b2ac58f9 | 2174 | |
d28bc9dd NA |
2175 | if (!init_event) { |
2176 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
2177 | MSR_IA32_APICBASE_ENABLE; | |
2178 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
2179 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
2180 | } | |
5690891b | 2181 | init_vmcb(svm); |
70433389 | 2182 | |
e911eb3b | 2183 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true); |
de3cd117 | 2184 | kvm_rdx_write(vcpu, eax); |
44a95dae SS |
2185 | |
2186 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
2187 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
2188 | } |
2189 | ||
dfa20099 SS |
2190 | static int avic_init_vcpu(struct vcpu_svm *svm) |
2191 | { | |
2192 | int ret; | |
2193 | ||
67034bb9 | 2194 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
dfa20099 SS |
2195 | return 0; |
2196 | ||
2197 | ret = avic_init_backing_page(&svm->vcpu); | |
2198 | if (ret) | |
2199 | return ret; | |
2200 | ||
2201 | INIT_LIST_HEAD(&svm->ir_list); | |
2202 | spin_lock_init(&svm->ir_list_lock); | |
98d90582 | 2203 | svm->dfr_reg = APIC_DFR_FLAT; |
dfa20099 SS |
2204 | |
2205 | return ret; | |
2206 | } | |
2207 | ||
987b2594 | 2208 | static int svm_create_vcpu(struct kvm_vcpu *vcpu) |
6aa8b732 | 2209 | { |
a2fa3e9f | 2210 | struct vcpu_svm *svm; |
6aa8b732 | 2211 | struct page *page; |
f65c229c | 2212 | struct page *msrpm_pages; |
b286d5d8 | 2213 | struct page *hsave_page; |
3d6368ef | 2214 | struct page *nested_msrpm_pages; |
fb3f0f51 | 2215 | int err; |
6aa8b732 | 2216 | |
a9dd6f09 SC |
2217 | BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0); |
2218 | svm = to_svm(vcpu); | |
fb3f0f51 | 2219 | |
b7af4043 | 2220 | err = -ENOMEM; |
1ec69647 | 2221 | page = alloc_page(GFP_KERNEL_ACCOUNT); |
b7af4043 | 2222 | if (!page) |
987b2594 | 2223 | goto out; |
6aa8b732 | 2224 | |
1ec69647 | 2225 | msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER); |
f65c229c | 2226 | if (!msrpm_pages) |
b7af4043 | 2227 | goto free_page1; |
3d6368ef | 2228 | |
1ec69647 | 2229 | nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER); |
3d6368ef | 2230 | if (!nested_msrpm_pages) |
b7af4043 | 2231 | goto free_page2; |
f65c229c | 2232 | |
1ec69647 | 2233 | hsave_page = alloc_page(GFP_KERNEL_ACCOUNT); |
b286d5d8 | 2234 | if (!hsave_page) |
b7af4043 TY |
2235 | goto free_page3; |
2236 | ||
dfa20099 SS |
2237 | err = avic_init_vcpu(svm); |
2238 | if (err) | |
2239 | goto free_page4; | |
44a95dae | 2240 | |
8221c137 SS |
2241 | /* We initialize this flag to true to make sure that the is_running |
2242 | * bit would be set the first time the vcpu is loaded. | |
2243 | */ | |
6c3e4422 SS |
2244 | if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm)) |
2245 | svm->avic_is_running = true; | |
8221c137 | 2246 | |
e6aa9abd | 2247 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 2248 | |
b7af4043 TY |
2249 | svm->msrpm = page_address(msrpm_pages); |
2250 | svm_vcpu_init_msrpm(svm->msrpm); | |
2251 | ||
e6aa9abd | 2252 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 2253 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 2254 | |
a2fa3e9f GH |
2255 | svm->vmcb = page_address(page); |
2256 | clear_page(svm->vmcb); | |
d0ec49d4 | 2257 | svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT); |
a2fa3e9f | 2258 | svm->asid_generation = 0; |
5690891b | 2259 | init_vmcb(svm); |
6aa8b732 | 2260 | |
7f27179a | 2261 | svm_init_osvw(vcpu); |
2b036c6b | 2262 | |
a9dd6f09 | 2263 | return 0; |
36241b8c | 2264 | |
44a95dae SS |
2265 | free_page4: |
2266 | __free_page(hsave_page); | |
b7af4043 TY |
2267 | free_page3: |
2268 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
2269 | free_page2: | |
2270 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
2271 | free_page1: | |
2272 | __free_page(page); | |
987b2594 | 2273 | out: |
a9dd6f09 | 2274 | return err; |
6aa8b732 AK |
2275 | } |
2276 | ||
fd65d314 JM |
2277 | static void svm_clear_current_vmcb(struct vmcb *vmcb) |
2278 | { | |
2279 | int i; | |
2280 | ||
2281 | for_each_online_cpu(i) | |
2282 | cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL); | |
2283 | } | |
2284 | ||
6aa8b732 AK |
2285 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) |
2286 | { | |
a2fa3e9f GH |
2287 | struct vcpu_svm *svm = to_svm(vcpu); |
2288 | ||
fd65d314 JM |
2289 | /* |
2290 | * The vmcb page can be recycled, causing a false negative in | |
2291 | * svm_vcpu_load(). So, ensure that no logical CPU has this | |
2292 | * vmcb page recorded as its current vmcb. | |
2293 | */ | |
2294 | svm_clear_current_vmcb(svm->vmcb); | |
2295 | ||
d0ec49d4 | 2296 | __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT)); |
f65c229c | 2297 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
2298 | __free_page(virt_to_page(svm->nested.hsave)); |
2299 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
6aa8b732 AK |
2300 | } |
2301 | ||
15ad7146 | 2302 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2303 | { |
a2fa3e9f | 2304 | struct vcpu_svm *svm = to_svm(vcpu); |
15d45071 | 2305 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
15ad7146 | 2306 | int i; |
0cc5064d | 2307 | |
0cc5064d | 2308 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 2309 | svm->asid_generation = 0; |
8d28fec4 | 2310 | mark_all_dirty(svm->vmcb); |
0cc5064d | 2311 | } |
94dfbdb3 | 2312 | |
82ca2d10 AK |
2313 | #ifdef CONFIG_X86_64 |
2314 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
2315 | #endif | |
dacccfdd AK |
2316 | savesegment(fs, svm->host.fs); |
2317 | savesegment(gs, svm->host.gs); | |
2318 | svm->host.ldt = kvm_read_ldt(); | |
2319 | ||
94dfbdb3 | 2320 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 2321 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 2322 | |
ad721883 HZ |
2323 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
2324 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
2325 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
2326 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
2327 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
2328 | } | |
fbc0db76 | 2329 | } |
46896c73 PB |
2330 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
2331 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
2332 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
8221c137 | 2333 | |
15d45071 AR |
2334 | if (sd->current_vmcb != svm->vmcb) { |
2335 | sd->current_vmcb = svm->vmcb; | |
2336 | indirect_branch_prediction_barrier(); | |
2337 | } | |
8221c137 | 2338 | avic_vcpu_load(vcpu, cpu); |
6aa8b732 AK |
2339 | } |
2340 | ||
2341 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
2342 | { | |
a2fa3e9f | 2343 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
2344 | int i; |
2345 | ||
8221c137 SS |
2346 | avic_vcpu_put(vcpu); |
2347 | ||
e1beb1d3 | 2348 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
2349 | kvm_load_ldt(svm->host.ldt); |
2350 | #ifdef CONFIG_X86_64 | |
2351 | loadsegment(fs, svm->host.fs); | |
296f781a | 2352 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase); |
893a5ab6 | 2353 | load_gs_index(svm->host.gs); |
dacccfdd | 2354 | #else |
831ca609 | 2355 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 2356 | loadsegment(gs, svm->host.gs); |
831ca609 | 2357 | #endif |
dacccfdd | 2358 | #endif |
94dfbdb3 | 2359 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 2360 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
2361 | } |
2362 | ||
8221c137 SS |
2363 | static void svm_vcpu_blocking(struct kvm_vcpu *vcpu) |
2364 | { | |
2365 | avic_set_running(vcpu, false); | |
2366 | } | |
2367 | ||
2368 | static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
2369 | { | |
6c3e4422 SS |
2370 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
2371 | kvm_vcpu_update_apicv(vcpu); | |
8221c137 SS |
2372 | avic_set_running(vcpu, true); |
2373 | } | |
2374 | ||
6aa8b732 AK |
2375 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
2376 | { | |
9b611747 LP |
2377 | struct vcpu_svm *svm = to_svm(vcpu); |
2378 | unsigned long rflags = svm->vmcb->save.rflags; | |
2379 | ||
2380 | if (svm->nmi_singlestep) { | |
2381 | /* Hide our flags if they were not set by the guest */ | |
2382 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
2383 | rflags &= ~X86_EFLAGS_TF; | |
2384 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
2385 | rflags &= ~X86_EFLAGS_RF; | |
2386 | } | |
2387 | return rflags; | |
6aa8b732 AK |
2388 | } |
2389 | ||
2390 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2391 | { | |
9b611747 LP |
2392 | if (to_svm(vcpu)->nmi_singlestep) |
2393 | rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
2394 | ||
ae9fedc7 | 2395 | /* |
bb3541f1 | 2396 | * Any change of EFLAGS.VM is accompanied by a reload of SS |
ae9fedc7 PB |
2397 | * (caused by either a task switch or an inter-privilege IRET), |
2398 | * so we do not need to update the CPL here. | |
2399 | */ | |
a2fa3e9f | 2400 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
2401 | } |
2402 | ||
6de4f3ad AK |
2403 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
2404 | { | |
2405 | switch (reg) { | |
2406 | case VCPU_EXREG_PDPTR: | |
2407 | BUG_ON(!npt_enabled); | |
9f8fe504 | 2408 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
2409 | break; |
2410 | default: | |
34059c25 | 2411 | WARN_ON_ONCE(1); |
6de4f3ad AK |
2412 | } |
2413 | } | |
2414 | ||
f0b85051 AG |
2415 | static void svm_set_vintr(struct vcpu_svm *svm) |
2416 | { | |
8a05a1b8 | 2417 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
2418 | } |
2419 | ||
2420 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
2421 | { | |
8a05a1b8 | 2422 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
2423 | } |
2424 | ||
6aa8b732 AK |
2425 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
2426 | { | |
a2fa3e9f | 2427 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
2428 | |
2429 | switch (seg) { | |
2430 | case VCPU_SREG_CS: return &save->cs; | |
2431 | case VCPU_SREG_DS: return &save->ds; | |
2432 | case VCPU_SREG_ES: return &save->es; | |
2433 | case VCPU_SREG_FS: return &save->fs; | |
2434 | case VCPU_SREG_GS: return &save->gs; | |
2435 | case VCPU_SREG_SS: return &save->ss; | |
2436 | case VCPU_SREG_TR: return &save->tr; | |
2437 | case VCPU_SREG_LDTR: return &save->ldtr; | |
2438 | } | |
2439 | BUG(); | |
8b6d44c7 | 2440 | return NULL; |
6aa8b732 AK |
2441 | } |
2442 | ||
2443 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
2444 | { | |
2445 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
2446 | ||
2447 | return s->base; | |
2448 | } | |
2449 | ||
2450 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
2451 | struct kvm_segment *var, int seg) | |
2452 | { | |
2453 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
2454 | ||
2455 | var->base = s->base; | |
2456 | var->limit = s->limit; | |
2457 | var->selector = s->selector; | |
2458 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
2459 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
2460 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
2461 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
2462 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
2463 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
2464 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
2465 | |
2466 | /* | |
2467 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
2468 | * However, the SVM spec states that the G bit is not observed by the | |
2469 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
2470 | * So let's synthesize a legal G bit for all segments, this helps | |
2471 | * running KVM nested. It also helps cross-vendor migration, because | |
2472 | * Intel's vmentry has a check on the 'G' bit. | |
2473 | */ | |
2474 | var->g = s->limit > 0xfffff; | |
25022acc | 2475 | |
e0231715 JR |
2476 | /* |
2477 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
2478 | * for cross vendor migration purposes by "not present" |
2479 | */ | |
8eae9570 | 2480 | var->unusable = !var->present; |
19bca6ab | 2481 | |
1fbdc7a5 | 2482 | switch (seg) { |
1fbdc7a5 AP |
2483 | case VCPU_SREG_TR: |
2484 | /* | |
2485 | * Work around a bug where the busy flag in the tr selector | |
2486 | * isn't exposed | |
2487 | */ | |
c0d09828 | 2488 | var->type |= 0x2; |
1fbdc7a5 AP |
2489 | break; |
2490 | case VCPU_SREG_DS: | |
2491 | case VCPU_SREG_ES: | |
2492 | case VCPU_SREG_FS: | |
2493 | case VCPU_SREG_GS: | |
2494 | /* | |
2495 | * The accessed bit must always be set in the segment | |
2496 | * descriptor cache, although it can be cleared in the | |
2497 | * descriptor, the cached bit always remains at 1. Since | |
2498 | * Intel has a check on this, set it here to support | |
2499 | * cross-vendor migration. | |
2500 | */ | |
2501 | if (!var->unusable) | |
2502 | var->type |= 0x1; | |
2503 | break; | |
b586eb02 | 2504 | case VCPU_SREG_SS: |
e0231715 JR |
2505 | /* |
2506 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
2507 | * descriptor is left as 1, although the whole segment has |
2508 | * been made unusable. Clear it here to pass an Intel VMX | |
2509 | * entry check when cross vendor migrating. | |
2510 | */ | |
2511 | if (var->unusable) | |
2512 | var->db = 0; | |
d9c1b543 | 2513 | /* This is symmetric with svm_set_segment() */ |
33b458d2 | 2514 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 2515 | break; |
1fbdc7a5 | 2516 | } |
6aa8b732 AK |
2517 | } |
2518 | ||
2e4d2653 IE |
2519 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
2520 | { | |
2521 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
2522 | ||
2523 | return save->cpl; | |
2524 | } | |
2525 | ||
89a27f4d | 2526 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2527 | { |
a2fa3e9f GH |
2528 | struct vcpu_svm *svm = to_svm(vcpu); |
2529 | ||
89a27f4d GN |
2530 | dt->size = svm->vmcb->save.idtr.limit; |
2531 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
2532 | } |
2533 | ||
89a27f4d | 2534 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2535 | { |
a2fa3e9f GH |
2536 | struct vcpu_svm *svm = to_svm(vcpu); |
2537 | ||
89a27f4d GN |
2538 | svm->vmcb->save.idtr.limit = dt->size; |
2539 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 2540 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
2541 | } |
2542 | ||
89a27f4d | 2543 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2544 | { |
a2fa3e9f GH |
2545 | struct vcpu_svm *svm = to_svm(vcpu); |
2546 | ||
89a27f4d GN |
2547 | dt->size = svm->vmcb->save.gdtr.limit; |
2548 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
2549 | } |
2550 | ||
89a27f4d | 2551 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2552 | { |
a2fa3e9f GH |
2553 | struct vcpu_svm *svm = to_svm(vcpu); |
2554 | ||
89a27f4d GN |
2555 | svm->vmcb->save.gdtr.limit = dt->size; |
2556 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 2557 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
2558 | } |
2559 | ||
e8467fda AK |
2560 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
2561 | { | |
2562 | } | |
2563 | ||
25c4c276 | 2564 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
2565 | { |
2566 | } | |
2567 | ||
d225157b AK |
2568 | static void update_cr0_intercept(struct vcpu_svm *svm) |
2569 | { | |
2570 | ulong gcr0 = svm->vcpu.arch.cr0; | |
2571 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
2572 | ||
bd7e5b08 PB |
2573 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) |
2574 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
d225157b | 2575 | |
dcca1a65 | 2576 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2577 | |
bd7e5b08 | 2578 | if (gcr0 == *hcr0) { |
4ee546b4 RJ |
2579 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
2580 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 2581 | } else { |
4ee546b4 RJ |
2582 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
2583 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
2584 | } |
2585 | } | |
2586 | ||
6aa8b732 AK |
2587 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
2588 | { | |
a2fa3e9f GH |
2589 | struct vcpu_svm *svm = to_svm(vcpu); |
2590 | ||
05b3e0c2 | 2591 | #ifdef CONFIG_X86_64 |
f6801dff | 2592 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 2593 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 2594 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 2595 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
2596 | } |
2597 | ||
d77c26fc | 2598 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 2599 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 2600 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
2601 | } |
2602 | } | |
2603 | #endif | |
ad312c7c | 2604 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
2605 | |
2606 | if (!npt_enabled) | |
2607 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 | 2608 | |
bcf166a9 PB |
2609 | /* |
2610 | * re-enable caching here because the QEMU bios | |
2611 | * does not do it - this results in some delay at | |
2612 | * reboot | |
2613 | */ | |
2614 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
2615 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 2616 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 2617 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2618 | update_cr0_intercept(svm); |
6aa8b732 AK |
2619 | } |
2620 | ||
5e1746d6 | 2621 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 2622 | { |
1e02ce4c | 2623 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
2624 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
2625 | ||
5e1746d6 NHE |
2626 | if (cr4 & X86_CR4_VMXE) |
2627 | return 1; | |
2628 | ||
e5eab0ce | 2629 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
c2ba05cc | 2630 | svm_flush_tlb(vcpu, true); |
6394b649 | 2631 | |
ec077263 JR |
2632 | vcpu->arch.cr4 = cr4; |
2633 | if (!npt_enabled) | |
2634 | cr4 |= X86_CR4_PAE; | |
6394b649 | 2635 | cr4 |= host_cr4_mce; |
ec077263 | 2636 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 2637 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 2638 | return 0; |
6aa8b732 AK |
2639 | } |
2640 | ||
2641 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
2642 | struct kvm_segment *var, int seg) | |
2643 | { | |
a2fa3e9f | 2644 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2645 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
2646 | ||
2647 | s->base = var->base; | |
2648 | s->limit = var->limit; | |
2649 | s->selector = var->selector; | |
d9c1b543 RP |
2650 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); |
2651 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
2652 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
2653 | s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT; | |
2654 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
2655 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
2656 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
2657 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
ae9fedc7 PB |
2658 | |
2659 | /* | |
2660 | * This is always accurate, except if SYSRET returned to a segment | |
2661 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
2662 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
2663 | * would entail passing the CPL to userspace and back. | |
2664 | */ | |
2665 | if (seg == VCPU_SREG_SS) | |
d9c1b543 RP |
2666 | /* This is symmetric with svm_get_segment() */ |
2667 | svm->vmcb->save.cpl = (var->dpl & 3); | |
6aa8b732 | 2668 | |
060d0c9a | 2669 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
2670 | } |
2671 | ||
cbdb967a | 2672 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 2673 | { |
d0bfb940 JK |
2674 | struct vcpu_svm *svm = to_svm(vcpu); |
2675 | ||
18c918c5 | 2676 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 2677 | |
d0bfb940 | 2678 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 2679 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 2680 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
2681 | } else |
2682 | vcpu->guest_debug = 0; | |
44c11430 GN |
2683 | } |
2684 | ||
0fe1e009 | 2685 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 2686 | { |
0fe1e009 TH |
2687 | if (sd->next_asid > sd->max_asid) { |
2688 | ++sd->asid_generation; | |
4faefff3 | 2689 | sd->next_asid = sd->min_asid; |
a2fa3e9f | 2690 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
2691 | } |
2692 | ||
0fe1e009 TH |
2693 | svm->asid_generation = sd->asid_generation; |
2694 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
2695 | |
2696 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
2697 | } |
2698 | ||
73aaf249 JK |
2699 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
2700 | { | |
2701 | return to_svm(vcpu)->vmcb->save.dr6; | |
2702 | } | |
2703 | ||
2704 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
2705 | { | |
2706 | struct vcpu_svm *svm = to_svm(vcpu); | |
2707 | ||
2708 | svm->vmcb->save.dr6 = value; | |
2709 | mark_dirty(svm->vmcb, VMCB_DR); | |
2710 | } | |
2711 | ||
facb0139 PB |
2712 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
2713 | { | |
2714 | struct vcpu_svm *svm = to_svm(vcpu); | |
2715 | ||
2716 | get_debugreg(vcpu->arch.db[0], 0); | |
2717 | get_debugreg(vcpu->arch.db[1], 1); | |
2718 | get_debugreg(vcpu->arch.db[2], 2); | |
2719 | get_debugreg(vcpu->arch.db[3], 3); | |
2720 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
2721 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
2722 | ||
2723 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
2724 | set_dr_intercepts(svm); | |
2725 | } | |
2726 | ||
020df079 | 2727 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 2728 | { |
42dbaa5a | 2729 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 2730 | |
020df079 | 2731 | svm->vmcb->save.dr7 = value; |
72214b96 | 2732 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
2733 | } |
2734 | ||
851ba692 | 2735 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 2736 | { |
0ede79e1 | 2737 | u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2); |
1261bfa3 | 2738 | u64 error_code = svm->vmcb->control.exit_info_1; |
6aa8b732 | 2739 | |
1261bfa3 | 2740 | return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address, |
00b10fe1 BS |
2741 | static_cpu_has(X86_FEATURE_DECODEASSISTS) ? |
2742 | svm->vmcb->control.insn_bytes : NULL, | |
d0006530 PB |
2743 | svm->vmcb->control.insn_len); |
2744 | } | |
2745 | ||
2746 | static int npf_interception(struct vcpu_svm *svm) | |
2747 | { | |
0ede79e1 | 2748 | u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2); |
d0006530 PB |
2749 | u64 error_code = svm->vmcb->control.exit_info_1; |
2750 | ||
2751 | trace_kvm_page_fault(fault_address, error_code); | |
2752 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, | |
00b10fe1 BS |
2753 | static_cpu_has(X86_FEATURE_DECODEASSISTS) ? |
2754 | svm->vmcb->control.insn_bytes : NULL, | |
d0006530 | 2755 | svm->vmcb->control.insn_len); |
6aa8b732 AK |
2756 | } |
2757 | ||
851ba692 | 2758 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 2759 | { |
851ba692 | 2760 | struct kvm_run *kvm_run = svm->vcpu.run; |
99c22179 | 2761 | struct kvm_vcpu *vcpu = &svm->vcpu; |
851ba692 | 2762 | |
d0bfb940 | 2763 | if (!(svm->vcpu.guest_debug & |
44c11430 | 2764 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 2765 | !svm->nmi_singlestep) { |
d0bfb940 JK |
2766 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
2767 | return 1; | |
2768 | } | |
44c11430 | 2769 | |
6be7d306 | 2770 | if (svm->nmi_singlestep) { |
4aebd0e9 | 2771 | disable_nmi_singlestep(svm); |
99c22179 VK |
2772 | /* Make sure we check for pending NMIs upon entry */ |
2773 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
44c11430 GN |
2774 | } |
2775 | ||
2776 | if (svm->vcpu.guest_debug & | |
e0231715 | 2777 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
2778 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2779 | kvm_run->debug.arch.pc = | |
2780 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2781 | kvm_run->debug.arch.exception = DB_VECTOR; | |
2782 | return 0; | |
2783 | } | |
2784 | ||
2785 | return 1; | |
d0bfb940 JK |
2786 | } |
2787 | ||
851ba692 | 2788 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 2789 | { |
851ba692 AK |
2790 | struct kvm_run *kvm_run = svm->vcpu.run; |
2791 | ||
d0bfb940 JK |
2792 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2793 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2794 | kvm_run->debug.arch.exception = BP_VECTOR; | |
2795 | return 0; | |
2796 | } | |
2797 | ||
851ba692 | 2798 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 | 2799 | { |
082d06ed | 2800 | return handle_ud(&svm->vcpu); |
7aa81cc0 AL |
2801 | } |
2802 | ||
54a20552 EN |
2803 | static int ac_interception(struct vcpu_svm *svm) |
2804 | { | |
2805 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
2806 | return 1; | |
2807 | } | |
2808 | ||
9718420e LA |
2809 | static int gp_interception(struct vcpu_svm *svm) |
2810 | { | |
2811 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
2812 | u32 error_code = svm->vmcb->control.exit_info_1; | |
9718420e LA |
2813 | |
2814 | WARN_ON_ONCE(!enable_vmware_backdoor); | |
2815 | ||
a6c6ed1e SC |
2816 | /* |
2817 | * VMware backdoor emulation on #GP interception only handles IN{S}, | |
2818 | * OUT{S}, and RDPMC, none of which generate a non-zero error code. | |
2819 | */ | |
2820 | if (error_code) { | |
2821 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
2822 | return 1; | |
2823 | } | |
60fc3d02 | 2824 | return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); |
9718420e LA |
2825 | } |
2826 | ||
67ec6607 JR |
2827 | static bool is_erratum_383(void) |
2828 | { | |
2829 | int err, i; | |
2830 | u64 value; | |
2831 | ||
2832 | if (!erratum_383_found) | |
2833 | return false; | |
2834 | ||
2835 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
2836 | if (err) | |
2837 | return false; | |
2838 | ||
2839 | /* Bit 62 may or may not be set for this mce */ | |
2840 | value &= ~(1ULL << 62); | |
2841 | ||
2842 | if (value != 0xb600000000010015ULL) | |
2843 | return false; | |
2844 | ||
2845 | /* Clear MCi_STATUS registers */ | |
2846 | for (i = 0; i < 6; ++i) | |
2847 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
2848 | ||
2849 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
2850 | if (!err) { | |
2851 | u32 low, high; | |
2852 | ||
2853 | value &= ~(1ULL << 2); | |
2854 | low = lower_32_bits(value); | |
2855 | high = upper_32_bits(value); | |
2856 | ||
2857 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
2858 | } | |
2859 | ||
2860 | /* Flush tlb to evict multi-match entries */ | |
2861 | __flush_tlb_all(); | |
2862 | ||
2863 | return true; | |
2864 | } | |
2865 | ||
fe5913e4 | 2866 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 2867 | { |
67ec6607 JR |
2868 | if (is_erratum_383()) { |
2869 | /* | |
2870 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
2871 | * guest. | |
2872 | */ | |
2873 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
2874 | ||
a8eeb04a | 2875 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
2876 | |
2877 | return; | |
2878 | } | |
2879 | ||
53371b50 JR |
2880 | /* |
2881 | * On an #MC intercept the MCE handler is not called automatically in | |
2882 | * the host. So do it by hand here. | |
2883 | */ | |
2884 | asm volatile ( | |
2885 | "int $0x12\n"); | |
2886 | /* not sure if we ever come back to this point */ | |
2887 | ||
fe5913e4 JR |
2888 | return; |
2889 | } | |
2890 | ||
2891 | static int mc_interception(struct vcpu_svm *svm) | |
2892 | { | |
53371b50 JR |
2893 | return 1; |
2894 | } | |
2895 | ||
851ba692 | 2896 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2897 | { |
851ba692 AK |
2898 | struct kvm_run *kvm_run = svm->vcpu.run; |
2899 | ||
46fe4ddd JR |
2900 | /* |
2901 | * VMCB is undefined after a SHUTDOWN intercept | |
2902 | * so reinitialize it. | |
2903 | */ | |
a2fa3e9f | 2904 | clear_page(svm->vmcb); |
5690891b | 2905 | init_vmcb(svm); |
46fe4ddd JR |
2906 | |
2907 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2908 | return 0; | |
2909 | } | |
2910 | ||
851ba692 | 2911 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2912 | { |
cf8f70bf | 2913 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2914 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
dca7f128 | 2915 | int size, in, string; |
039576c0 | 2916 | unsigned port; |
6aa8b732 | 2917 | |
e756fc62 | 2918 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2919 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2920 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
8370c3d0 | 2921 | if (string) |
60fc3d02 | 2922 | return kvm_emulate_instruction(vcpu, 0); |
cf8f70bf | 2923 | |
039576c0 AK |
2924 | port = io_info >> 16; |
2925 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2926 | svm->next_rip = svm->vmcb->control.exit_info_2; |
cf8f70bf | 2927 | |
dca7f128 | 2928 | return kvm_fast_pio(&svm->vcpu, size, port, in); |
6aa8b732 AK |
2929 | } |
2930 | ||
851ba692 | 2931 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2932 | { |
2933 | return 1; | |
2934 | } | |
2935 | ||
851ba692 | 2936 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2937 | { |
2938 | ++svm->vcpu.stat.irq_exits; | |
2939 | return 1; | |
2940 | } | |
2941 | ||
851ba692 | 2942 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2943 | { |
2944 | return 1; | |
2945 | } | |
2946 | ||
851ba692 | 2947 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2948 | { |
e756fc62 | 2949 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2950 | } |
2951 | ||
851ba692 | 2952 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2953 | { |
0d9c055e | 2954 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2955 | } |
2956 | ||
5bd2edc3 JR |
2957 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2958 | { | |
2959 | struct vcpu_svm *svm = to_svm(vcpu); | |
2960 | ||
2961 | return svm->nested.nested_cr3; | |
2962 | } | |
2963 | ||
e4e517b4 AK |
2964 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2965 | { | |
2966 | struct vcpu_svm *svm = to_svm(vcpu); | |
2967 | u64 cr3 = svm->nested.nested_cr3; | |
2968 | u64 pdpte; | |
2969 | int ret; | |
2970 | ||
d0ec49d4 | 2971 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte, |
54bf36aa | 2972 | offset_in_page(cr3) + index * 8, 8); |
e4e517b4 AK |
2973 | if (ret) |
2974 | return 0; | |
2975 | return pdpte; | |
2976 | } | |
2977 | ||
5bd2edc3 JR |
2978 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2979 | unsigned long root) | |
2980 | { | |
2981 | struct vcpu_svm *svm = to_svm(vcpu); | |
2982 | ||
d0ec49d4 | 2983 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 2984 | mark_dirty(svm->vmcb, VMCB_NPT); |
5bd2edc3 JR |
2985 | } |
2986 | ||
6389ee94 AK |
2987 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2988 | struct x86_exception *fault) | |
5bd2edc3 JR |
2989 | { |
2990 | struct vcpu_svm *svm = to_svm(vcpu); | |
2991 | ||
5e352519 PB |
2992 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2993 | /* | |
2994 | * TODO: track the cause of the nested page fault, and | |
2995 | * correctly fill in the high bits of exit_info_1. | |
2996 | */ | |
2997 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2998 | svm->vmcb->control.exit_code_hi = 0; | |
2999 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
3000 | svm->vmcb->control.exit_info_2 = fault->address; | |
3001 | } | |
3002 | ||
3003 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
3004 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
3005 | ||
3006 | /* | |
3007 | * The present bit is always zero for page structure faults on real | |
3008 | * hardware. | |
3009 | */ | |
3010 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
3011 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
3012 | |
3013 | nested_svm_vmexit(svm); | |
3014 | } | |
3015 | ||
8a3c1a33 | 3016 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 3017 | { |
ad896af0 | 3018 | WARN_ON(mmu_is_nested(vcpu)); |
3cf85f9f VK |
3019 | |
3020 | vcpu->arch.mmu = &vcpu->arch.guest_mmu; | |
ad896af0 | 3021 | kvm_init_shadow_mmu(vcpu); |
44dd3ffa VK |
3022 | vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3; |
3023 | vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3; | |
3024 | vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr; | |
3025 | vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit; | |
3026 | vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu); | |
3027 | reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu); | |
4b16184c | 3028 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
3029 | } |
3030 | ||
3031 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
3032 | { | |
3cf85f9f | 3033 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
44dd3ffa | 3034 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; |
4b16184c JR |
3035 | } |
3036 | ||
c0725420 AG |
3037 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
3038 | { | |
e9196ceb DC |
3039 | if (!(svm->vcpu.arch.efer & EFER_SVME) || |
3040 | !is_paging(&svm->vcpu)) { | |
c0725420 AG |
3041 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
3042 | return 1; | |
3043 | } | |
3044 | ||
3045 | if (svm->vmcb->save.cpl) { | |
3046 | kvm_inject_gp(&svm->vcpu, 0); | |
3047 | return 1; | |
3048 | } | |
3049 | ||
e9196ceb | 3050 | return 0; |
c0725420 AG |
3051 | } |
3052 | ||
cf74a78b AG |
3053 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
3054 | bool has_error_code, u32 error_code) | |
3055 | { | |
b8e88bc8 JR |
3056 | int vmexit; |
3057 | ||
2030753d | 3058 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 3059 | return 0; |
cf74a78b | 3060 | |
adfe20fb WL |
3061 | vmexit = nested_svm_intercept(svm); |
3062 | if (vmexit != NESTED_EXIT_DONE) | |
3063 | return 0; | |
3064 | ||
0295ad7d JR |
3065 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
3066 | svm->vmcb->control.exit_code_hi = 0; | |
3067 | svm->vmcb->control.exit_info_1 = error_code; | |
b96fb439 PB |
3068 | |
3069 | /* | |
da998b46 JM |
3070 | * EXITINFO2 is undefined for all exception intercepts other |
3071 | * than #PF. | |
b96fb439 | 3072 | */ |
adfe20fb WL |
3073 | if (svm->vcpu.arch.exception.nested_apf) |
3074 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token; | |
da998b46 JM |
3075 | else if (svm->vcpu.arch.exception.has_payload) |
3076 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload; | |
adfe20fb WL |
3077 | else |
3078 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
b8e88bc8 | 3079 | |
adfe20fb | 3080 | svm->nested.exit_required = true; |
b8e88bc8 | 3081 | return vmexit; |
cf74a78b AG |
3082 | } |
3083 | ||
8fe54654 JR |
3084 | /* This function returns true if it is save to enable the irq window */ |
3085 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 3086 | { |
2030753d | 3087 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 3088 | return true; |
cf74a78b | 3089 | |
26666957 | 3090 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 3091 | return true; |
cf74a78b | 3092 | |
26666957 | 3093 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 3094 | return false; |
cf74a78b | 3095 | |
a0a07cd2 GN |
3096 | /* |
3097 | * if vmexit was already requested (by intercepted exception | |
3098 | * for instance) do not overwrite it with "external interrupt" | |
3099 | * vmexit. | |
3100 | */ | |
3101 | if (svm->nested.exit_required) | |
3102 | return false; | |
3103 | ||
197717d5 JR |
3104 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
3105 | svm->vmcb->control.exit_info_1 = 0; | |
3106 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 3107 | |
cd3ff653 JR |
3108 | if (svm->nested.intercept & 1ULL) { |
3109 | /* | |
3110 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 3111 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
3112 | * #vmexit emulation might sleep. Only signal request for |
3113 | * the #vmexit here. | |
3114 | */ | |
3115 | svm->nested.exit_required = true; | |
236649de | 3116 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 3117 | return false; |
cf74a78b AG |
3118 | } |
3119 | ||
8fe54654 | 3120 | return true; |
cf74a78b AG |
3121 | } |
3122 | ||
887f500c JR |
3123 | /* This function returns true if it is save to enable the nmi window */ |
3124 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
3125 | { | |
2030753d | 3126 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
3127 | return true; |
3128 | ||
3129 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
3130 | return true; | |
3131 | ||
3132 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
3133 | svm->nested.exit_required = true; | |
3134 | ||
3135 | return false; | |
cf74a78b AG |
3136 | } |
3137 | ||
ce2ac085 JR |
3138 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
3139 | { | |
9bf41833 JK |
3140 | unsigned port, size, iopm_len; |
3141 | u16 val, mask; | |
3142 | u8 start_bit; | |
ce2ac085 | 3143 | u64 gpa; |
34f80cfa | 3144 | |
ce2ac085 JR |
3145 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
3146 | return NESTED_EXIT_HOST; | |
34f80cfa | 3147 | |
ce2ac085 | 3148 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
3149 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
3150 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 3151 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
3152 | start_bit = port % 8; |
3153 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
3154 | mask = (0xf >> (4 - size)) << start_bit; | |
3155 | val = 0; | |
ce2ac085 | 3156 | |
54bf36aa | 3157 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 3158 | return NESTED_EXIT_DONE; |
ce2ac085 | 3159 | |
9bf41833 | 3160 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
3161 | } |
3162 | ||
d2477826 | 3163 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 3164 | { |
0d6b3537 JR |
3165 | u32 offset, msr, value; |
3166 | int write, mask; | |
4c2161ae | 3167 | |
3d62d9aa | 3168 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 3169 | return NESTED_EXIT_HOST; |
3d62d9aa | 3170 | |
0d6b3537 JR |
3171 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
3172 | offset = svm_msrpm_offset(msr); | |
3173 | write = svm->vmcb->control.exit_info_1 & 1; | |
3174 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 3175 | |
0d6b3537 JR |
3176 | if (offset == MSR_INVALID) |
3177 | return NESTED_EXIT_DONE; | |
4c2161ae | 3178 | |
0d6b3537 JR |
3179 | /* Offset is in 32 bit units but need in 8 bit units */ |
3180 | offset *= 4; | |
4c2161ae | 3181 | |
54bf36aa | 3182 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 3183 | return NESTED_EXIT_DONE; |
3d62d9aa | 3184 | |
0d6b3537 | 3185 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
3186 | } |
3187 | ||
ab2f4d73 LP |
3188 | /* DB exceptions for our internal use must not cause vmexit */ |
3189 | static int nested_svm_intercept_db(struct vcpu_svm *svm) | |
3190 | { | |
3191 | unsigned long dr6; | |
3192 | ||
3193 | /* if we're not singlestepping, it's not ours */ | |
3194 | if (!svm->nmi_singlestep) | |
3195 | return NESTED_EXIT_DONE; | |
3196 | ||
3197 | /* if it's not a singlestep exception, it's not ours */ | |
3198 | if (kvm_get_dr(&svm->vcpu, 6, &dr6)) | |
3199 | return NESTED_EXIT_DONE; | |
3200 | if (!(dr6 & DR6_BS)) | |
3201 | return NESTED_EXIT_DONE; | |
3202 | ||
3203 | /* if the guest is singlestepping, it should get the vmexit */ | |
3204 | if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) { | |
3205 | disable_nmi_singlestep(svm); | |
3206 | return NESTED_EXIT_DONE; | |
3207 | } | |
3208 | ||
3209 | /* it's ours, the nested hypervisor must not see this one */ | |
3210 | return NESTED_EXIT_HOST; | |
3211 | } | |
3212 | ||
410e4d57 | 3213 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 3214 | { |
cf74a78b | 3215 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 3216 | |
410e4d57 JR |
3217 | switch (exit_code) { |
3218 | case SVM_EXIT_INTR: | |
3219 | case SVM_EXIT_NMI: | |
ff47a49b | 3220 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 3221 | return NESTED_EXIT_HOST; |
410e4d57 | 3222 | case SVM_EXIT_NPF: |
e0231715 | 3223 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
3224 | if (npt_enabled) |
3225 | return NESTED_EXIT_HOST; | |
3226 | break; | |
410e4d57 | 3227 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 | 3228 | /* When we're shadowing, trap PFs, but not async PF */ |
1261bfa3 | 3229 | if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0) |
410e4d57 JR |
3230 | return NESTED_EXIT_HOST; |
3231 | break; | |
3232 | default: | |
3233 | break; | |
cf74a78b AG |
3234 | } |
3235 | ||
410e4d57 JR |
3236 | return NESTED_EXIT_CONTINUE; |
3237 | } | |
3238 | ||
3239 | /* | |
3240 | * If this function returns true, this #vmexit was already handled | |
3241 | */ | |
b8e88bc8 | 3242 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
3243 | { |
3244 | u32 exit_code = svm->vmcb->control.exit_code; | |
3245 | int vmexit = NESTED_EXIT_HOST; | |
3246 | ||
cf74a78b | 3247 | switch (exit_code) { |
9c4e40b9 | 3248 | case SVM_EXIT_MSR: |
3d62d9aa | 3249 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 3250 | break; |
ce2ac085 JR |
3251 | case SVM_EXIT_IOIO: |
3252 | vmexit = nested_svm_intercept_ioio(svm); | |
3253 | break; | |
4ee546b4 RJ |
3254 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
3255 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
3256 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 3257 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3258 | break; |
3259 | } | |
3aed041a JR |
3260 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
3261 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
3262 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 3263 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3264 | break; |
3265 | } | |
3266 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
3267 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
ab2f4d73 LP |
3268 | if (svm->nested.intercept_exceptions & excp_bits) { |
3269 | if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR) | |
3270 | vmexit = nested_svm_intercept_db(svm); | |
3271 | else | |
3272 | vmexit = NESTED_EXIT_DONE; | |
3273 | } | |
631bc487 GN |
3274 | /* async page fault always cause vmexit */ |
3275 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
adfe20fb | 3276 | svm->vcpu.arch.exception.nested_apf != 0) |
631bc487 | 3277 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3278 | break; |
3279 | } | |
228070b1 JR |
3280 | case SVM_EXIT_ERR: { |
3281 | vmexit = NESTED_EXIT_DONE; | |
3282 | break; | |
3283 | } | |
cf74a78b AG |
3284 | default: { |
3285 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 3286 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 3287 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3288 | } |
3289 | } | |
3290 | ||
b8e88bc8 JR |
3291 | return vmexit; |
3292 | } | |
3293 | ||
3294 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
3295 | { | |
3296 | int vmexit; | |
3297 | ||
3298 | vmexit = nested_svm_intercept(svm); | |
3299 | ||
3300 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 3301 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
3302 | |
3303 | return vmexit; | |
cf74a78b AG |
3304 | } |
3305 | ||
0460a979 JR |
3306 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
3307 | { | |
3308 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
3309 | struct vmcb_control_area *from = &from_vmcb->control; | |
3310 | ||
4ee546b4 | 3311 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 3312 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
3313 | dst->intercept_exceptions = from->intercept_exceptions; |
3314 | dst->intercept = from->intercept; | |
3315 | dst->iopm_base_pa = from->iopm_base_pa; | |
3316 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
3317 | dst->tsc_offset = from->tsc_offset; | |
3318 | dst->asid = from->asid; | |
3319 | dst->tlb_ctl = from->tlb_ctl; | |
3320 | dst->int_ctl = from->int_ctl; | |
3321 | dst->int_vector = from->int_vector; | |
3322 | dst->int_state = from->int_state; | |
3323 | dst->exit_code = from->exit_code; | |
3324 | dst->exit_code_hi = from->exit_code_hi; | |
3325 | dst->exit_info_1 = from->exit_info_1; | |
3326 | dst->exit_info_2 = from->exit_info_2; | |
3327 | dst->exit_int_info = from->exit_int_info; | |
3328 | dst->exit_int_info_err = from->exit_int_info_err; | |
3329 | dst->nested_ctl = from->nested_ctl; | |
3330 | dst->event_inj = from->event_inj; | |
3331 | dst->event_inj_err = from->event_inj_err; | |
3332 | dst->nested_cr3 = from->nested_cr3; | |
0dc92119 | 3333 | dst->virt_ext = from->virt_ext; |
e081354d TW |
3334 | dst->pause_filter_count = from->pause_filter_count; |
3335 | dst->pause_filter_thresh = from->pause_filter_thresh; | |
0460a979 JR |
3336 | } |
3337 | ||
34f80cfa | 3338 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 3339 | { |
8c5fbf1a | 3340 | int rc; |
34f80cfa | 3341 | struct vmcb *nested_vmcb; |
e6aa9abd | 3342 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 3343 | struct vmcb *vmcb = svm->vmcb; |
8c5fbf1a | 3344 | struct kvm_host_map map; |
cf74a78b | 3345 | |
17897f36 JR |
3346 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
3347 | vmcb->control.exit_info_1, | |
3348 | vmcb->control.exit_info_2, | |
3349 | vmcb->control.exit_int_info, | |
e097e5ff SH |
3350 | vmcb->control.exit_int_info_err, |
3351 | KVM_ISA_SVM); | |
17897f36 | 3352 | |
8f38302c | 3353 | rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map); |
8c5fbf1a KA |
3354 | if (rc) { |
3355 | if (rc == -EINVAL) | |
3356 | kvm_inject_gp(&svm->vcpu, 0); | |
34f80cfa | 3357 | return 1; |
8c5fbf1a KA |
3358 | } |
3359 | ||
3360 | nested_vmcb = map.hva; | |
34f80cfa | 3361 | |
2030753d JR |
3362 | /* Exit Guest-Mode */ |
3363 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
3364 | svm->nested.vmcb = 0; |
3365 | ||
cf74a78b | 3366 | /* Give the current vmcb to the guest */ |
33740e40 JR |
3367 | disable_gif(svm); |
3368 | ||
3369 | nested_vmcb->save.es = vmcb->save.es; | |
3370 | nested_vmcb->save.cs = vmcb->save.cs; | |
3371 | nested_vmcb->save.ss = vmcb->save.ss; | |
3372 | nested_vmcb->save.ds = vmcb->save.ds; | |
3373 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
3374 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 3375 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 3376 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 3377 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 3378 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 3379 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 3380 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
3381 | nested_vmcb->save.rip = vmcb->save.rip; |
3382 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
3383 | nested_vmcb->save.rax = vmcb->save.rax; | |
3384 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
3385 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
3386 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
3387 | ||
3388 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
3389 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
3390 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
3391 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
3392 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
3393 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
3394 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
3395 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
3396 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
3397 | |
3398 | if (svm->nrips_enabled) | |
3399 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
3400 | |
3401 | /* | |
3402 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
3403 | * to make sure that we do not lose injected events. So check event_inj | |
3404 | * here and copy it to exit_int_info if it is valid. | |
3405 | * Exit_int_info and event_inj can't be both valid because the case | |
3406 | * below only happens on a VMRUN instruction intercept which has | |
3407 | * no valid exit_int_info set. | |
3408 | */ | |
3409 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
3410 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
3411 | ||
3412 | nc->exit_int_info = vmcb->control.event_inj; | |
3413 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
3414 | } | |
3415 | ||
33740e40 JR |
3416 | nested_vmcb->control.tlb_ctl = 0; |
3417 | nested_vmcb->control.event_inj = 0; | |
3418 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b | 3419 | |
e081354d TW |
3420 | nested_vmcb->control.pause_filter_count = |
3421 | svm->vmcb->control.pause_filter_count; | |
3422 | nested_vmcb->control.pause_filter_thresh = | |
3423 | svm->vmcb->control.pause_filter_thresh; | |
3424 | ||
cf74a78b AG |
3425 | /* We always set V_INTR_MASKING and remember the old value in hflags */ |
3426 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
3427 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
3428 | ||
cf74a78b | 3429 | /* Restore the original control entries */ |
0460a979 | 3430 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 3431 | |
e79f245d | 3432 | svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset; |
219b65dc AG |
3433 | kvm_clear_exception_queue(&svm->vcpu); |
3434 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 3435 | |
4b16184c JR |
3436 | svm->nested.nested_cr3 = 0; |
3437 | ||
cf74a78b AG |
3438 | /* Restore selected save entries */ |
3439 | svm->vmcb->save.es = hsave->save.es; | |
3440 | svm->vmcb->save.cs = hsave->save.cs; | |
3441 | svm->vmcb->save.ss = hsave->save.ss; | |
3442 | svm->vmcb->save.ds = hsave->save.ds; | |
3443 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
3444 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 3445 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
3446 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
3447 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
3448 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
3449 | if (npt_enabled) { | |
3450 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
3451 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
3452 | } else { | |
2390218b | 3453 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b | 3454 | } |
de3cd117 | 3455 | kvm_rax_write(&svm->vcpu, hsave->save.rax); |
e9c16c78 PB |
3456 | kvm_rsp_write(&svm->vcpu, hsave->save.rsp); |
3457 | kvm_rip_write(&svm->vcpu, hsave->save.rip); | |
cf74a78b AG |
3458 | svm->vmcb->save.dr7 = 0; |
3459 | svm->vmcb->save.cpl = 0; | |
3460 | svm->vmcb->control.exit_int_info = 0; | |
3461 | ||
8d28fec4 RJ |
3462 | mark_all_dirty(svm->vmcb); |
3463 | ||
8c5fbf1a | 3464 | kvm_vcpu_unmap(&svm->vcpu, &map, true); |
cf74a78b | 3465 | |
4b16184c | 3466 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
3467 | kvm_mmu_reset_context(&svm->vcpu); |
3468 | kvm_mmu_load(&svm->vcpu); | |
3469 | ||
619ad846 VK |
3470 | /* |
3471 | * Drop what we picked up for L2 via svm_complete_interrupts() so it | |
3472 | * doesn't end up in L1. | |
3473 | */ | |
3474 | svm->vcpu.arch.nmi_injected = false; | |
3475 | kvm_clear_exception_queue(&svm->vcpu); | |
3476 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3477 | ||
cf74a78b AG |
3478 | return 0; |
3479 | } | |
3d6368ef | 3480 | |
9738b2c9 | 3481 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 3482 | { |
323c3d80 JR |
3483 | /* |
3484 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 3485 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
3486 | * the kvm msr permission bitmap may contain zero bits |
3487 | */ | |
3d6368ef | 3488 | int i; |
9738b2c9 | 3489 | |
323c3d80 JR |
3490 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
3491 | return true; | |
9738b2c9 | 3492 | |
323c3d80 JR |
3493 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
3494 | u32 value, p; | |
3495 | u64 offset; | |
9738b2c9 | 3496 | |
323c3d80 JR |
3497 | if (msrpm_offsets[i] == 0xffffffff) |
3498 | break; | |
3d6368ef | 3499 | |
0d6b3537 JR |
3500 | p = msrpm_offsets[i]; |
3501 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 3502 | |
54bf36aa | 3503 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
3504 | return false; |
3505 | ||
3506 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
3507 | } | |
3d6368ef | 3508 | |
d0ec49d4 | 3509 | svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm)); |
9738b2c9 JR |
3510 | |
3511 | return true; | |
3d6368ef AG |
3512 | } |
3513 | ||
52c65a30 JR |
3514 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
3515 | { | |
3516 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
3517 | return false; | |
3518 | ||
dbe77584 JR |
3519 | if (vmcb->control.asid == 0) |
3520 | return false; | |
3521 | ||
cea3a19b TL |
3522 | if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) && |
3523 | !npt_enabled) | |
4b16184c JR |
3524 | return false; |
3525 | ||
52c65a30 JR |
3526 | return true; |
3527 | } | |
3528 | ||
c2634065 | 3529 | static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, |
8c5fbf1a | 3530 | struct vmcb *nested_vmcb, struct kvm_host_map *map) |
3d6368ef | 3531 | { |
f6e78475 | 3532 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
3533 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
3534 | else | |
3535 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
3536 | ||
cea3a19b | 3537 | if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) { |
4b16184c JR |
3538 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; |
3539 | nested_svm_init_mmu_context(&svm->vcpu); | |
3540 | } | |
3541 | ||
3d6368ef AG |
3542 | /* Load the nested guest state */ |
3543 | svm->vmcb->save.es = nested_vmcb->save.es; | |
3544 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
3545 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
3546 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
3547 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
3548 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 3549 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
3550 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
3551 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
3552 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
3553 | if (npt_enabled) { | |
3554 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
3555 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 3556 | } else |
2390218b | 3557 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
3558 | |
3559 | /* Guest paging mode is active - reset mmu */ | |
3560 | kvm_mmu_reset_context(&svm->vcpu); | |
3561 | ||
defbba56 | 3562 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
de3cd117 | 3563 | kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax); |
e9c16c78 PB |
3564 | kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp); |
3565 | kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip); | |
e0231715 | 3566 | |
3d6368ef AG |
3567 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
3568 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
3569 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
3570 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
3571 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
3572 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
3573 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
3574 | ||
f7138538 | 3575 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 3576 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 3577 | |
aad42c64 | 3578 | /* cache intercepts */ |
4ee546b4 | 3579 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 3580 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
3581 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
3582 | svm->nested.intercept = nested_vmcb->control.intercept; | |
3583 | ||
c2ba05cc | 3584 | svm_flush_tlb(&svm->vcpu, true); |
3d6368ef | 3585 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
3586 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
3587 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
3588 | else | |
3589 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
3590 | ||
88ab24ad JR |
3591 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
3592 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
3593 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
3594 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
3595 | } |
3596 | ||
0d945bd9 | 3597 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 3598 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 3599 | |
e79f245d KA |
3600 | svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset; |
3601 | svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset; | |
3602 | ||
0dc92119 | 3603 | svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext; |
3d6368ef AG |
3604 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
3605 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
3d6368ef AG |
3606 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
3607 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
3608 | ||
e081354d TW |
3609 | svm->vmcb->control.pause_filter_count = |
3610 | nested_vmcb->control.pause_filter_count; | |
3611 | svm->vmcb->control.pause_filter_thresh = | |
3612 | nested_vmcb->control.pause_filter_thresh; | |
3613 | ||
8c5fbf1a | 3614 | kvm_vcpu_unmap(&svm->vcpu, map, true); |
9738b2c9 | 3615 | |
2030753d JR |
3616 | /* Enter Guest-Mode */ |
3617 | enter_guest_mode(&svm->vcpu); | |
3618 | ||
384c6368 JR |
3619 | /* |
3620 | * Merge guest and host intercepts - must be called with vcpu in | |
3621 | * guest-mode to take affect here | |
3622 | */ | |
3623 | recalc_intercepts(svm); | |
3624 | ||
06fc7772 | 3625 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 3626 | |
2af9194d | 3627 | enable_gif(svm); |
3d6368ef | 3628 | |
8d28fec4 | 3629 | mark_all_dirty(svm->vmcb); |
c2634065 LP |
3630 | } |
3631 | ||
e7134c1b | 3632 | static int nested_svm_vmrun(struct vcpu_svm *svm) |
c2634065 | 3633 | { |
c8e16b78 | 3634 | int ret; |
c2634065 LP |
3635 | struct vmcb *nested_vmcb; |
3636 | struct vmcb *hsave = svm->nested.hsave; | |
3637 | struct vmcb *vmcb = svm->vmcb; | |
8c5fbf1a | 3638 | struct kvm_host_map map; |
c2634065 LP |
3639 | u64 vmcb_gpa; |
3640 | ||
3641 | vmcb_gpa = svm->vmcb->save.rax; | |
3642 | ||
c8e16b78 | 3643 | ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map); |
a061985b | 3644 | if (ret == -EINVAL) { |
c8e16b78 | 3645 | kvm_inject_gp(&svm->vcpu, 0); |
e7134c1b | 3646 | return 1; |
c8e16b78 VK |
3647 | } else if (ret) { |
3648 | return kvm_skip_emulated_instruction(&svm->vcpu); | |
8c5fbf1a KA |
3649 | } |
3650 | ||
c8e16b78 VK |
3651 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
3652 | ||
8c5fbf1a | 3653 | nested_vmcb = map.hva; |
c2634065 LP |
3654 | |
3655 | if (!nested_vmcb_checks(nested_vmcb)) { | |
3656 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
3657 | nested_vmcb->control.exit_code_hi = 0; | |
3658 | nested_vmcb->control.exit_info_1 = 0; | |
3659 | nested_vmcb->control.exit_info_2 = 0; | |
3660 | ||
8c5fbf1a | 3661 | kvm_vcpu_unmap(&svm->vcpu, &map, true); |
c2634065 | 3662 | |
c8e16b78 | 3663 | return ret; |
c2634065 LP |
3664 | } |
3665 | ||
3666 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, | |
3667 | nested_vmcb->save.rip, | |
3668 | nested_vmcb->control.int_ctl, | |
3669 | nested_vmcb->control.event_inj, | |
3670 | nested_vmcb->control.nested_ctl); | |
3671 | ||
3672 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, | |
3673 | nested_vmcb->control.intercept_cr >> 16, | |
3674 | nested_vmcb->control.intercept_exceptions, | |
3675 | nested_vmcb->control.intercept); | |
3676 | ||
3677 | /* Clear internal status */ | |
3678 | kvm_clear_exception_queue(&svm->vcpu); | |
3679 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3680 | ||
3681 | /* | |
3682 | * Save the old vmcb, so we don't need to pick what we save, but can | |
3683 | * restore everything when a VMEXIT occurs | |
3684 | */ | |
3685 | hsave->save.es = vmcb->save.es; | |
3686 | hsave->save.cs = vmcb->save.cs; | |
3687 | hsave->save.ss = vmcb->save.ss; | |
3688 | hsave->save.ds = vmcb->save.ds; | |
3689 | hsave->save.gdtr = vmcb->save.gdtr; | |
3690 | hsave->save.idtr = vmcb->save.idtr; | |
3691 | hsave->save.efer = svm->vcpu.arch.efer; | |
3692 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); | |
3693 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
3694 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); | |
3695 | hsave->save.rip = kvm_rip_read(&svm->vcpu); | |
3696 | hsave->save.rsp = vmcb->save.rsp; | |
3697 | hsave->save.rax = vmcb->save.rax; | |
3698 | if (npt_enabled) | |
3699 | hsave->save.cr3 = vmcb->save.cr3; | |
3700 | else | |
3701 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); | |
3702 | ||
3703 | copy_vmcb_control_area(hsave, vmcb); | |
3704 | ||
8c5fbf1a | 3705 | enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map); |
8d28fec4 | 3706 | |
e7134c1b VK |
3707 | if (!nested_svm_vmrun_msrpm(svm)) { |
3708 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
3709 | svm->vmcb->control.exit_code_hi = 0; | |
3710 | svm->vmcb->control.exit_info_1 = 0; | |
3711 | svm->vmcb->control.exit_info_2 = 0; | |
3712 | ||
3713 | nested_svm_vmexit(svm); | |
3714 | } | |
3715 | ||
c8e16b78 | 3716 | return ret; |
3d6368ef AG |
3717 | } |
3718 | ||
9966bf68 | 3719 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
3720 | { |
3721 | to_vmcb->save.fs = from_vmcb->save.fs; | |
3722 | to_vmcb->save.gs = from_vmcb->save.gs; | |
3723 | to_vmcb->save.tr = from_vmcb->save.tr; | |
3724 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
3725 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
3726 | to_vmcb->save.star = from_vmcb->save.star; | |
3727 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
3728 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
3729 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
3730 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
3731 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
3732 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
3733 | } |
3734 | ||
851ba692 | 3735 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 3736 | { |
9966bf68 | 3737 | struct vmcb *nested_vmcb; |
8c5fbf1a | 3738 | struct kvm_host_map map; |
b742c1e6 | 3739 | int ret; |
9966bf68 | 3740 | |
5542675b AG |
3741 | if (nested_svm_check_permissions(svm)) |
3742 | return 1; | |
3743 | ||
8c5fbf1a KA |
3744 | ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map); |
3745 | if (ret) { | |
3746 | if (ret == -EINVAL) | |
3747 | kvm_inject_gp(&svm->vcpu, 0); | |
9966bf68 | 3748 | return 1; |
8c5fbf1a KA |
3749 | } |
3750 | ||
3751 | nested_vmcb = map.hva; | |
9966bf68 | 3752 | |
b742c1e6 | 3753 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3754 | |
9966bf68 | 3755 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
8c5fbf1a | 3756 | kvm_vcpu_unmap(&svm->vcpu, &map, true); |
5542675b | 3757 | |
b742c1e6 | 3758 | return ret; |
5542675b AG |
3759 | } |
3760 | ||
851ba692 | 3761 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 3762 | { |
9966bf68 | 3763 | struct vmcb *nested_vmcb; |
8c5fbf1a | 3764 | struct kvm_host_map map; |
b742c1e6 | 3765 | int ret; |
9966bf68 | 3766 | |
5542675b AG |
3767 | if (nested_svm_check_permissions(svm)) |
3768 | return 1; | |
3769 | ||
8c5fbf1a KA |
3770 | ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map); |
3771 | if (ret) { | |
3772 | if (ret == -EINVAL) | |
3773 | kvm_inject_gp(&svm->vcpu, 0); | |
9966bf68 | 3774 | return 1; |
8c5fbf1a KA |
3775 | } |
3776 | ||
3777 | nested_vmcb = map.hva; | |
9966bf68 | 3778 | |
b742c1e6 | 3779 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3780 | |
9966bf68 | 3781 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
8c5fbf1a | 3782 | kvm_vcpu_unmap(&svm->vcpu, &map, true); |
5542675b | 3783 | |
b742c1e6 | 3784 | return ret; |
5542675b AG |
3785 | } |
3786 | ||
851ba692 | 3787 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 3788 | { |
3d6368ef AG |
3789 | if (nested_svm_check_permissions(svm)) |
3790 | return 1; | |
3791 | ||
e7134c1b | 3792 | return nested_svm_vmrun(svm); |
3d6368ef AG |
3793 | } |
3794 | ||
851ba692 | 3795 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 | 3796 | { |
b742c1e6 LP |
3797 | int ret; |
3798 | ||
1371d904 AG |
3799 | if (nested_svm_check_permissions(svm)) |
3800 | return 1; | |
3801 | ||
640bd6e5 JN |
3802 | /* |
3803 | * If VGIF is enabled, the STGI intercept is only added to | |
cc3d967f | 3804 | * detect the opening of the SMI/NMI window; remove it now. |
640bd6e5 JN |
3805 | */ |
3806 | if (vgif_enabled(svm)) | |
3807 | clr_intercept(svm, INTERCEPT_STGI); | |
3808 | ||
b742c1e6 | 3809 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
3842d135 | 3810 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 3811 | |
2af9194d | 3812 | enable_gif(svm); |
1371d904 | 3813 | |
b742c1e6 | 3814 | return ret; |
1371d904 AG |
3815 | } |
3816 | ||
851ba692 | 3817 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 | 3818 | { |
b742c1e6 LP |
3819 | int ret; |
3820 | ||
1371d904 AG |
3821 | if (nested_svm_check_permissions(svm)) |
3822 | return 1; | |
3823 | ||
b742c1e6 | 3824 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
1371d904 | 3825 | |
2af9194d | 3826 | disable_gif(svm); |
1371d904 AG |
3827 | |
3828 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
3829 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
3830 | svm_clear_vintr(svm); | |
3831 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
3832 | mark_dirty(svm->vmcb, VMCB_INTR); | |
3833 | } | |
decdbf6a | 3834 | |
b742c1e6 | 3835 | return ret; |
1371d904 AG |
3836 | } |
3837 | ||
851ba692 | 3838 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
3839 | { |
3840 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 3841 | |
de3cd117 SC |
3842 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu), |
3843 | kvm_rax_read(&svm->vcpu)); | |
ec1ff790 | 3844 | |
ff092385 | 3845 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
de3cd117 | 3846 | kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu)); |
ff092385 | 3847 | |
b742c1e6 | 3848 | return kvm_skip_emulated_instruction(&svm->vcpu); |
ff092385 AG |
3849 | } |
3850 | ||
532a46b9 JR |
3851 | static int skinit_interception(struct vcpu_svm *svm) |
3852 | { | |
de3cd117 | 3853 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu)); |
532a46b9 JR |
3854 | |
3855 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3856 | return 1; | |
3857 | } | |
3858 | ||
dab429a7 DK |
3859 | static int wbinvd_interception(struct vcpu_svm *svm) |
3860 | { | |
6affcbed | 3861 | return kvm_emulate_wbinvd(&svm->vcpu); |
dab429a7 DK |
3862 | } |
3863 | ||
81dd35d4 JR |
3864 | static int xsetbv_interception(struct vcpu_svm *svm) |
3865 | { | |
3866 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
de3cd117 | 3867 | u32 index = kvm_rcx_read(&svm->vcpu); |
81dd35d4 JR |
3868 | |
3869 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
b742c1e6 | 3870 | return kvm_skip_emulated_instruction(&svm->vcpu); |
81dd35d4 JR |
3871 | } |
3872 | ||
3873 | return 1; | |
3874 | } | |
3875 | ||
0cb8410b JM |
3876 | static int rdpru_interception(struct vcpu_svm *svm) |
3877 | { | |
3878 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3879 | return 1; | |
3880 | } | |
3881 | ||
851ba692 | 3882 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 3883 | { |
37817f29 | 3884 | u16 tss_selector; |
64a7ec06 GN |
3885 | int reason; |
3886 | int int_type = svm->vmcb->control.exit_int_info & | |
3887 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 3888 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
3889 | uint32_t type = |
3890 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
3891 | uint32_t idt_v = | |
3892 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
3893 | bool has_error_code = false; |
3894 | u32 error_code = 0; | |
37817f29 IE |
3895 | |
3896 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 3897 | |
37817f29 IE |
3898 | if (svm->vmcb->control.exit_info_2 & |
3899 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
3900 | reason = TASK_SWITCH_IRET; |
3901 | else if (svm->vmcb->control.exit_info_2 & | |
3902 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
3903 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 3904 | else if (idt_v) |
64a7ec06 GN |
3905 | reason = TASK_SWITCH_GATE; |
3906 | else | |
3907 | reason = TASK_SWITCH_CALL; | |
3908 | ||
fe8e7f83 GN |
3909 | if (reason == TASK_SWITCH_GATE) { |
3910 | switch (type) { | |
3911 | case SVM_EXITINTINFO_TYPE_NMI: | |
3912 | svm->vcpu.arch.nmi_injected = false; | |
3913 | break; | |
3914 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
3915 | if (svm->vmcb->control.exit_info_2 & |
3916 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
3917 | has_error_code = true; | |
3918 | error_code = | |
3919 | (u32)svm->vmcb->control.exit_info_2; | |
3920 | } | |
fe8e7f83 GN |
3921 | kvm_clear_exception_queue(&svm->vcpu); |
3922 | break; | |
3923 | case SVM_EXITINTINFO_TYPE_INTR: | |
3924 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3925 | break; | |
3926 | default: | |
3927 | break; | |
3928 | } | |
3929 | } | |
64a7ec06 | 3930 | |
8317c298 GN |
3931 | if (reason != TASK_SWITCH_GATE || |
3932 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
3933 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f8ea7c60 | 3934 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) { |
60fc3d02 | 3935 | if (!skip_emulated_instruction(&svm->vcpu)) |
738fece4 | 3936 | return 0; |
f8ea7c60 | 3937 | } |
64a7ec06 | 3938 | |
7f3d35fd KW |
3939 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
3940 | int_vec = -1; | |
3941 | ||
1051778f | 3942 | return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, |
60fc3d02 | 3943 | has_error_code, error_code); |
6aa8b732 AK |
3944 | } |
3945 | ||
851ba692 | 3946 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3947 | { |
6a908b62 | 3948 | return kvm_emulate_cpuid(&svm->vcpu); |
6aa8b732 AK |
3949 | } |
3950 | ||
851ba692 | 3951 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3952 | { |
3953 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3954 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3955 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3956 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3957 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3958 | return 1; |
3959 | } | |
3960 | ||
851ba692 | 3961 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3962 | { |
df4f3108 | 3963 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
60fc3d02 | 3964 | return kvm_emulate_instruction(&svm->vcpu, 0); |
df4f3108 AP |
3965 | |
3966 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
b742c1e6 | 3967 | return kvm_skip_emulated_instruction(&svm->vcpu); |
a7052897 MT |
3968 | } |
3969 | ||
851ba692 | 3970 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3971 | { |
60fc3d02 | 3972 | return kvm_emulate_instruction(&svm->vcpu, 0); |
6aa8b732 AK |
3973 | } |
3974 | ||
7607b717 BS |
3975 | static int rsm_interception(struct vcpu_svm *svm) |
3976 | { | |
60fc3d02 | 3977 | return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2); |
7607b717 BS |
3978 | } |
3979 | ||
332b56e4 AK |
3980 | static int rdpmc_interception(struct vcpu_svm *svm) |
3981 | { | |
3982 | int err; | |
3983 | ||
d647eb63 | 3984 | if (!nrips) |
332b56e4 AK |
3985 | return emulate_on_interception(svm); |
3986 | ||
3987 | err = kvm_rdpmc(&svm->vcpu); | |
6affcbed | 3988 | return kvm_complete_insn_gp(&svm->vcpu, err); |
332b56e4 AK |
3989 | } |
3990 | ||
52eb5a6d XL |
3991 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3992 | unsigned long val) | |
628afd2a JR |
3993 | { |
3994 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3995 | bool ret = false; | |
3996 | u64 intercept; | |
3997 | ||
3998 | intercept = svm->nested.intercept; | |
3999 | ||
4000 | if (!is_guest_mode(&svm->vcpu) || | |
4001 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
4002 | return false; | |
4003 | ||
4004 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
4005 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
4006 | ||
4007 | if (cr0 ^ val) { | |
4008 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4009 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
4010 | } | |
4011 | ||
4012 | return ret; | |
4013 | } | |
4014 | ||
7ff76d58 AP |
4015 | #define CR_VALID (1ULL << 63) |
4016 | ||
4017 | static int cr_interception(struct vcpu_svm *svm) | |
4018 | { | |
4019 | int reg, cr; | |
4020 | unsigned long val; | |
4021 | int err; | |
4022 | ||
4023 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
4024 | return emulate_on_interception(svm); | |
4025 | ||
4026 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
4027 | return emulate_on_interception(svm); | |
4028 | ||
4029 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
4030 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
4031 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
4032 | else | |
4033 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
4034 | |
4035 | err = 0; | |
4036 | if (cr >= 16) { /* mov to cr */ | |
4037 | cr -= 16; | |
4038 | val = kvm_register_read(&svm->vcpu, reg); | |
4039 | switch (cr) { | |
4040 | case 0: | |
628afd2a JR |
4041 | if (!check_selective_cr0_intercepted(svm, val)) |
4042 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
4043 | else |
4044 | return 1; | |
4045 | ||
7ff76d58 AP |
4046 | break; |
4047 | case 3: | |
4048 | err = kvm_set_cr3(&svm->vcpu, val); | |
4049 | break; | |
4050 | case 4: | |
4051 | err = kvm_set_cr4(&svm->vcpu, val); | |
4052 | break; | |
4053 | case 8: | |
4054 | err = kvm_set_cr8(&svm->vcpu, val); | |
4055 | break; | |
4056 | default: | |
4057 | WARN(1, "unhandled write to CR%d", cr); | |
4058 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
4059 | return 1; | |
4060 | } | |
4061 | } else { /* mov from cr */ | |
4062 | switch (cr) { | |
4063 | case 0: | |
4064 | val = kvm_read_cr0(&svm->vcpu); | |
4065 | break; | |
4066 | case 2: | |
4067 | val = svm->vcpu.arch.cr2; | |
4068 | break; | |
4069 | case 3: | |
9f8fe504 | 4070 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
4071 | break; |
4072 | case 4: | |
4073 | val = kvm_read_cr4(&svm->vcpu); | |
4074 | break; | |
4075 | case 8: | |
4076 | val = kvm_get_cr8(&svm->vcpu); | |
4077 | break; | |
4078 | default: | |
4079 | WARN(1, "unhandled read from CR%d", cr); | |
4080 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
4081 | return 1; | |
4082 | } | |
4083 | kvm_register_write(&svm->vcpu, reg, val); | |
4084 | } | |
6affcbed | 4085 | return kvm_complete_insn_gp(&svm->vcpu, err); |
7ff76d58 AP |
4086 | } |
4087 | ||
cae3797a AP |
4088 | static int dr_interception(struct vcpu_svm *svm) |
4089 | { | |
4090 | int reg, dr; | |
4091 | unsigned long val; | |
cae3797a | 4092 | |
facb0139 PB |
4093 | if (svm->vcpu.guest_debug == 0) { |
4094 | /* | |
4095 | * No more DR vmexits; force a reload of the debug registers | |
4096 | * and reenter on this instruction. The next vmexit will | |
4097 | * retrieve the full state of the debug registers. | |
4098 | */ | |
4099 | clr_dr_intercepts(svm); | |
4100 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
4101 | return 1; | |
4102 | } | |
4103 | ||
cae3797a AP |
4104 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
4105 | return emulate_on_interception(svm); | |
4106 | ||
4107 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
4108 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
4109 | ||
4110 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
4111 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
4112 | return 1; | |
cae3797a AP |
4113 | val = kvm_register_read(&svm->vcpu, reg); |
4114 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
4115 | } else { | |
16f8a6f9 NA |
4116 | if (!kvm_require_dr(&svm->vcpu, dr)) |
4117 | return 1; | |
4118 | kvm_get_dr(&svm->vcpu, dr, &val); | |
4119 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
4120 | } |
4121 | ||
b742c1e6 | 4122 | return kvm_skip_emulated_instruction(&svm->vcpu); |
cae3797a AP |
4123 | } |
4124 | ||
851ba692 | 4125 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 4126 | { |
851ba692 | 4127 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 4128 | int r; |
851ba692 | 4129 | |
0a5fff19 GN |
4130 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
4131 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 4132 | r = cr_interception(svm); |
35754c98 | 4133 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 4134 | return r; |
0a5fff19 | 4135 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 4136 | return r; |
1d075434 JR |
4137 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
4138 | return 0; | |
4139 | } | |
4140 | ||
801e459a TL |
4141 | static int svm_get_msr_feature(struct kvm_msr_entry *msr) |
4142 | { | |
d1d93fa9 TL |
4143 | msr->data = 0; |
4144 | ||
4145 | switch (msr->index) { | |
4146 | case MSR_F10H_DECFG: | |
4147 | if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) | |
4148 | msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE; | |
4149 | break; | |
4150 | default: | |
4151 | return 1; | |
4152 | } | |
4153 | ||
4154 | return 0; | |
801e459a TL |
4155 | } |
4156 | ||
609e36d3 | 4157 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 4158 | { |
a2fa3e9f GH |
4159 | struct vcpu_svm *svm = to_svm(vcpu); |
4160 | ||
609e36d3 | 4161 | switch (msr_info->index) { |
8c06585d | 4162 | case MSR_STAR: |
609e36d3 | 4163 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 4164 | break; |
0e859cac | 4165 | #ifdef CONFIG_X86_64 |
6aa8b732 | 4166 | case MSR_LSTAR: |
609e36d3 | 4167 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
4168 | break; |
4169 | case MSR_CSTAR: | |
609e36d3 | 4170 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
4171 | break; |
4172 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 4173 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
4174 | break; |
4175 | case MSR_SYSCALL_MASK: | |
609e36d3 | 4176 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
4177 | break; |
4178 | #endif | |
4179 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 4180 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
4181 | break; |
4182 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 4183 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
4184 | break; |
4185 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 4186 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 4187 | break; |
46896c73 PB |
4188 | case MSR_TSC_AUX: |
4189 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
4190 | return 1; | |
4191 | msr_info->data = svm->tsc_aux; | |
4192 | break; | |
e0231715 JR |
4193 | /* |
4194 | * Nobody will change the following 5 values in the VMCB so we can | |
4195 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
4196 | * implemented. | |
4197 | */ | |
a2938c80 | 4198 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 4199 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
4200 | break; |
4201 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 4202 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
4203 | break; |
4204 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 4205 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
4206 | break; |
4207 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 4208 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
4209 | break; |
4210 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 4211 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 4212 | break; |
b286d5d8 | 4213 | case MSR_VM_HSAVE_PA: |
609e36d3 | 4214 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 4215 | break; |
eb6f302e | 4216 | case MSR_VM_CR: |
609e36d3 | 4217 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 4218 | break; |
b2ac58f9 KA |
4219 | case MSR_IA32_SPEC_CTRL: |
4220 | if (!msr_info->host_initiated && | |
6ac2f49e KRW |
4221 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) && |
4222 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) | |
b2ac58f9 KA |
4223 | return 1; |
4224 | ||
4225 | msr_info->data = svm->spec_ctrl; | |
4226 | break; | |
bc226f07 TL |
4227 | case MSR_AMD64_VIRT_SPEC_CTRL: |
4228 | if (!msr_info->host_initiated && | |
4229 | !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD)) | |
4230 | return 1; | |
4231 | ||
4232 | msr_info->data = svm->virt_spec_ctrl; | |
4233 | break; | |
ae8b7875 BP |
4234 | case MSR_F15H_IC_CFG: { |
4235 | ||
4236 | int family, model; | |
4237 | ||
4238 | family = guest_cpuid_family(vcpu); | |
4239 | model = guest_cpuid_model(vcpu); | |
4240 | ||
4241 | if (family < 0 || model < 0) | |
4242 | return kvm_get_msr_common(vcpu, msr_info); | |
4243 | ||
4244 | msr_info->data = 0; | |
4245 | ||
4246 | if (family == 0x15 && | |
4247 | (model >= 0x2 && model < 0x20)) | |
4248 | msr_info->data = 0x1E; | |
4249 | } | |
4250 | break; | |
d1d93fa9 TL |
4251 | case MSR_F10H_DECFG: |
4252 | msr_info->data = svm->msr_decfg; | |
4253 | break; | |
6aa8b732 | 4254 | default: |
609e36d3 | 4255 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
4256 | } |
4257 | return 0; | |
4258 | } | |
4259 | ||
851ba692 | 4260 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 4261 | { |
1edce0a9 | 4262 | return kvm_emulate_rdmsr(&svm->vcpu); |
6aa8b732 AK |
4263 | } |
4264 | ||
4a810181 JR |
4265 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
4266 | { | |
4267 | struct vcpu_svm *svm = to_svm(vcpu); | |
4268 | int svm_dis, chg_mask; | |
4269 | ||
4270 | if (data & ~SVM_VM_CR_VALID_MASK) | |
4271 | return 1; | |
4272 | ||
4273 | chg_mask = SVM_VM_CR_VALID_MASK; | |
4274 | ||
4275 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
4276 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
4277 | ||
4278 | svm->nested.vm_cr_msr &= ~chg_mask; | |
4279 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
4280 | ||
4281 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
4282 | ||
4283 | /* check for svm_disable while efer.svme is set */ | |
4284 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
4285 | return 1; | |
4286 | ||
4287 | return 0; | |
4288 | } | |
4289 | ||
8fe8ab46 | 4290 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 4291 | { |
a2fa3e9f GH |
4292 | struct vcpu_svm *svm = to_svm(vcpu); |
4293 | ||
8fe8ab46 WA |
4294 | u32 ecx = msr->index; |
4295 | u64 data = msr->data; | |
6aa8b732 | 4296 | switch (ecx) { |
15038e14 PB |
4297 | case MSR_IA32_CR_PAT: |
4298 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) | |
4299 | return 1; | |
4300 | vcpu->arch.pat = data; | |
4301 | svm->vmcb->save.g_pat = data; | |
4302 | mark_dirty(svm->vmcb, VMCB_NPT); | |
4303 | break; | |
b2ac58f9 KA |
4304 | case MSR_IA32_SPEC_CTRL: |
4305 | if (!msr->host_initiated && | |
6ac2f49e KRW |
4306 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) && |
4307 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) | |
b2ac58f9 KA |
4308 | return 1; |
4309 | ||
6441fa61 | 4310 | if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) |
b2ac58f9 KA |
4311 | return 1; |
4312 | ||
4313 | svm->spec_ctrl = data; | |
b2ac58f9 KA |
4314 | if (!data) |
4315 | break; | |
4316 | ||
4317 | /* | |
4318 | * For non-nested: | |
4319 | * When it's written (to non-zero) for the first time, pass | |
4320 | * it through. | |
4321 | * | |
4322 | * For nested: | |
4323 | * The handling of the MSR bitmap for L2 guests is done in | |
4324 | * nested_svm_vmrun_msrpm. | |
4325 | * We update the L1 MSR bit as well since it will end up | |
4326 | * touching the MSR anyway now. | |
4327 | */ | |
4328 | set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1); | |
4329 | break; | |
15d45071 AR |
4330 | case MSR_IA32_PRED_CMD: |
4331 | if (!msr->host_initiated && | |
e7c587da | 4332 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB)) |
15d45071 AR |
4333 | return 1; |
4334 | ||
4335 | if (data & ~PRED_CMD_IBPB) | |
4336 | return 1; | |
6441fa61 PB |
4337 | if (!boot_cpu_has(X86_FEATURE_AMD_IBPB)) |
4338 | return 1; | |
15d45071 AR |
4339 | if (!data) |
4340 | break; | |
4341 | ||
4342 | wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); | |
15d45071 AR |
4343 | set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1); |
4344 | break; | |
bc226f07 TL |
4345 | case MSR_AMD64_VIRT_SPEC_CTRL: |
4346 | if (!msr->host_initiated && | |
4347 | !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD)) | |
4348 | return 1; | |
4349 | ||
4350 | if (data & ~SPEC_CTRL_SSBD) | |
4351 | return 1; | |
4352 | ||
4353 | svm->virt_spec_ctrl = data; | |
4354 | break; | |
8c06585d | 4355 | case MSR_STAR: |
a2fa3e9f | 4356 | svm->vmcb->save.star = data; |
6aa8b732 | 4357 | break; |
49b14f24 | 4358 | #ifdef CONFIG_X86_64 |
6aa8b732 | 4359 | case MSR_LSTAR: |
a2fa3e9f | 4360 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
4361 | break; |
4362 | case MSR_CSTAR: | |
a2fa3e9f | 4363 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
4364 | break; |
4365 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 4366 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
4367 | break; |
4368 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 4369 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
4370 | break; |
4371 | #endif | |
4372 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 4373 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
4374 | break; |
4375 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 4376 | svm->sysenter_eip = data; |
a2fa3e9f | 4377 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
4378 | break; |
4379 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 4380 | svm->sysenter_esp = data; |
a2fa3e9f | 4381 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 4382 | break; |
46896c73 PB |
4383 | case MSR_TSC_AUX: |
4384 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
4385 | return 1; | |
4386 | ||
4387 | /* | |
4388 | * This is rare, so we update the MSR here instead of using | |
4389 | * direct_access_msrs. Doing that would require a rdmsr in | |
4390 | * svm_vcpu_put. | |
4391 | */ | |
4392 | svm->tsc_aux = data; | |
4393 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
4394 | break; | |
a2938c80 | 4395 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 4396 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
4397 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
4398 | __func__, data); | |
24e09cbf JR |
4399 | break; |
4400 | } | |
4401 | if (data & DEBUGCTL_RESERVED_BITS) | |
4402 | return 1; | |
4403 | ||
4404 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 4405 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
4406 | if (data & (1ULL<<0)) |
4407 | svm_enable_lbrv(svm); | |
4408 | else | |
4409 | svm_disable_lbrv(svm); | |
a2938c80 | 4410 | break; |
b286d5d8 | 4411 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 4412 | svm->nested.hsave_msr = data; |
62b9abaa | 4413 | break; |
3c5d0a44 | 4414 | case MSR_VM_CR: |
4a810181 | 4415 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 4416 | case MSR_VM_IGNNE: |
a737f256 | 4417 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 4418 | break; |
d1d93fa9 TL |
4419 | case MSR_F10H_DECFG: { |
4420 | struct kvm_msr_entry msr_entry; | |
4421 | ||
4422 | msr_entry.index = msr->index; | |
4423 | if (svm_get_msr_feature(&msr_entry)) | |
4424 | return 1; | |
4425 | ||
4426 | /* Check the supported bits */ | |
4427 | if (data & ~msr_entry.data) | |
4428 | return 1; | |
4429 | ||
4430 | /* Don't allow the guest to change a bit, #GP */ | |
4431 | if (!msr->host_initiated && (data ^ msr_entry.data)) | |
4432 | return 1; | |
4433 | ||
4434 | svm->msr_decfg = data; | |
4435 | break; | |
4436 | } | |
44a95dae SS |
4437 | case MSR_IA32_APICBASE: |
4438 | if (kvm_vcpu_apicv_active(vcpu)) | |
4439 | avic_update_vapic_bar(to_svm(vcpu), data); | |
b2869f28 | 4440 | /* Fall through */ |
6aa8b732 | 4441 | default: |
8fe8ab46 | 4442 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
4443 | } |
4444 | return 0; | |
4445 | } | |
4446 | ||
851ba692 | 4447 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 4448 | { |
1edce0a9 | 4449 | return kvm_emulate_wrmsr(&svm->vcpu); |
6aa8b732 AK |
4450 | } |
4451 | ||
851ba692 | 4452 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 4453 | { |
e756fc62 | 4454 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 4455 | return wrmsr_interception(svm); |
6aa8b732 | 4456 | else |
851ba692 | 4457 | return rdmsr_interception(svm); |
6aa8b732 AK |
4458 | } |
4459 | ||
851ba692 | 4460 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 4461 | { |
3842d135 | 4462 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 4463 | svm_clear_vintr(svm); |
85f455f7 | 4464 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 4465 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 4466 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
4467 | return 1; |
4468 | } | |
4469 | ||
565d0998 ML |
4470 | static int pause_interception(struct vcpu_svm *svm) |
4471 | { | |
de63ad4c LM |
4472 | struct kvm_vcpu *vcpu = &svm->vcpu; |
4473 | bool in_kernel = (svm_get_cpl(vcpu) == 0); | |
4474 | ||
8566ac8b BM |
4475 | if (pause_filter_thresh) |
4476 | grow_ple_window(vcpu); | |
4477 | ||
de63ad4c | 4478 | kvm_vcpu_on_spin(vcpu, in_kernel); |
565d0998 ML |
4479 | return 1; |
4480 | } | |
4481 | ||
87c00572 GS |
4482 | static int nop_interception(struct vcpu_svm *svm) |
4483 | { | |
b742c1e6 | 4484 | return kvm_skip_emulated_instruction(&(svm->vcpu)); |
87c00572 GS |
4485 | } |
4486 | ||
4487 | static int monitor_interception(struct vcpu_svm *svm) | |
4488 | { | |
4489 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
4490 | return nop_interception(svm); | |
4491 | } | |
4492 | ||
4493 | static int mwait_interception(struct vcpu_svm *svm) | |
4494 | { | |
4495 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
4496 | return nop_interception(svm); | |
4497 | } | |
4498 | ||
18f40c53 SS |
4499 | enum avic_ipi_failure_cause { |
4500 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
4501 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
4502 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
4503 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
4504 | }; | |
4505 | ||
4506 | static int avic_incomplete_ipi_interception(struct vcpu_svm *svm) | |
4507 | { | |
4508 | u32 icrh = svm->vmcb->control.exit_info_1 >> 32; | |
4509 | u32 icrl = svm->vmcb->control.exit_info_1; | |
4510 | u32 id = svm->vmcb->control.exit_info_2 >> 32; | |
5446a979 | 4511 | u32 index = svm->vmcb->control.exit_info_2 & 0xFF; |
18f40c53 SS |
4512 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
4513 | ||
4514 | trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); | |
4515 | ||
4516 | switch (id) { | |
4517 | case AVIC_IPI_FAILURE_INVALID_INT_TYPE: | |
4518 | /* | |
4519 | * AVIC hardware handles the generation of | |
4520 | * IPIs when the specified Message Type is Fixed | |
4521 | * (also known as fixed delivery mode) and | |
4522 | * the Trigger Mode is edge-triggered. The hardware | |
4523 | * also supports self and broadcast delivery modes | |
4524 | * specified via the Destination Shorthand(DSH) | |
4525 | * field of the ICRL. Logical and physical APIC ID | |
4526 | * formats are supported. All other IPI types cause | |
4527 | * a #VMEXIT, which needs to emulated. | |
4528 | */ | |
4529 | kvm_lapic_reg_write(apic, APIC_ICR2, icrh); | |
4530 | kvm_lapic_reg_write(apic, APIC_ICR, icrl); | |
4531 | break; | |
4532 | case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { | |
4a58038b SS |
4533 | int i; |
4534 | struct kvm_vcpu *vcpu; | |
4535 | struct kvm *kvm = svm->vcpu.kvm; | |
18f40c53 SS |
4536 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
4537 | ||
4538 | /* | |
4a58038b SS |
4539 | * At this point, we expect that the AVIC HW has already |
4540 | * set the appropriate IRR bits on the valid target | |
4541 | * vcpus. So, we just need to kick the appropriate vcpu. | |
18f40c53 | 4542 | */ |
4a58038b SS |
4543 | kvm_for_each_vcpu(i, vcpu, kvm) { |
4544 | bool m = kvm_apic_match_dest(vcpu, apic, | |
ac8ef992 | 4545 | icrl & APIC_SHORT_MASK, |
4a58038b | 4546 | GET_APIC_DEST_FIELD(icrh), |
ac8ef992 | 4547 | icrl & APIC_DEST_MASK); |
4a58038b SS |
4548 | |
4549 | if (m && !avic_vcpu_is_running(vcpu)) | |
4550 | kvm_vcpu_wake_up(vcpu); | |
4551 | } | |
18f40c53 SS |
4552 | break; |
4553 | } | |
4554 | case AVIC_IPI_FAILURE_INVALID_TARGET: | |
37ef0c44 SS |
4555 | WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n", |
4556 | index, svm->vcpu.vcpu_id, icrh, icrl); | |
18f40c53 SS |
4557 | break; |
4558 | case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: | |
4559 | WARN_ONCE(1, "Invalid backing page\n"); | |
4560 | break; | |
4561 | default: | |
4562 | pr_err("Unknown IPI interception\n"); | |
4563 | } | |
4564 | ||
4565 | return 1; | |
4566 | } | |
4567 | ||
4568 | static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) | |
4569 | { | |
81811c16 | 4570 | struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm); |
18f40c53 SS |
4571 | int index; |
4572 | u32 *logical_apic_id_table; | |
4573 | int dlid = GET_APIC_LOGICAL_ID(ldr); | |
4574 | ||
4575 | if (!dlid) | |
4576 | return NULL; | |
4577 | ||
4578 | if (flat) { /* flat */ | |
4579 | index = ffs(dlid) - 1; | |
4580 | if (index > 7) | |
4581 | return NULL; | |
4582 | } else { /* cluster */ | |
4583 | int cluster = (dlid & 0xf0) >> 4; | |
4584 | int apic = ffs(dlid & 0x0f) - 1; | |
4585 | ||
4586 | if ((apic < 0) || (apic > 7) || | |
4587 | (cluster >= 0xf)) | |
4588 | return NULL; | |
4589 | index = (cluster << 2) + apic; | |
4590 | } | |
4591 | ||
81811c16 | 4592 | logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page); |
18f40c53 SS |
4593 | |
4594 | return &logical_apic_id_table[index]; | |
4595 | } | |
4596 | ||
98d90582 | 4597 | static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr) |
18f40c53 SS |
4598 | { |
4599 | bool flat; | |
4600 | u32 *entry, new_entry; | |
4601 | ||
4602 | flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; | |
4603 | entry = avic_get_logical_id_entry(vcpu, ldr, flat); | |
4604 | if (!entry) | |
4605 | return -EINVAL; | |
4606 | ||
4607 | new_entry = READ_ONCE(*entry); | |
4608 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; | |
4609 | new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); | |
98d90582 | 4610 | new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; |
18f40c53 SS |
4611 | WRITE_ONCE(*entry, new_entry); |
4612 | ||
4613 | return 0; | |
4614 | } | |
4615 | ||
98d90582 SS |
4616 | static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu) |
4617 | { | |
4618 | struct vcpu_svm *svm = to_svm(vcpu); | |
4619 | bool flat = svm->dfr_reg == APIC_DFR_FLAT; | |
4620 | u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat); | |
4621 | ||
4622 | if (entry) | |
e44e3eac | 4623 | clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry); |
98d90582 SS |
4624 | } |
4625 | ||
18f40c53 SS |
4626 | static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) |
4627 | { | |
98d90582 | 4628 | int ret = 0; |
18f40c53 SS |
4629 | struct vcpu_svm *svm = to_svm(vcpu); |
4630 | u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); | |
5c94ac5d | 4631 | u32 id = kvm_xapic_id(vcpu->arch.apic); |
18f40c53 | 4632 | |
98d90582 SS |
4633 | if (ldr == svm->ldr_reg) |
4634 | return 0; | |
18f40c53 | 4635 | |
98d90582 SS |
4636 | avic_invalidate_logical_id_entry(vcpu); |
4637 | ||
4638 | if (ldr) | |
5c94ac5d | 4639 | ret = avic_ldr_write(vcpu, id, ldr); |
98d90582 SS |
4640 | |
4641 | if (!ret) | |
18f40c53 | 4642 | svm->ldr_reg = ldr; |
98d90582 | 4643 | |
18f40c53 SS |
4644 | return ret; |
4645 | } | |
4646 | ||
4647 | static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) | |
4648 | { | |
4649 | u64 *old, *new; | |
4650 | struct vcpu_svm *svm = to_svm(vcpu); | |
5c94ac5d | 4651 | u32 id = kvm_xapic_id(vcpu->arch.apic); |
18f40c53 SS |
4652 | |
4653 | if (vcpu->vcpu_id == id) | |
4654 | return 0; | |
4655 | ||
4656 | old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); | |
4657 | new = avic_get_physical_id_entry(vcpu, id); | |
4658 | if (!new || !old) | |
4659 | return 1; | |
4660 | ||
4661 | /* We need to move physical_id_entry to new offset */ | |
4662 | *new = *old; | |
4663 | *old = 0ULL; | |
4664 | to_svm(vcpu)->avic_physical_id_cache = new; | |
4665 | ||
4666 | /* | |
4667 | * Also update the guest physical APIC ID in the logical | |
4668 | * APIC ID table entry if already setup the LDR. | |
4669 | */ | |
4670 | if (svm->ldr_reg) | |
4671 | avic_handle_ldr_update(vcpu); | |
4672 | ||
4673 | return 0; | |
4674 | } | |
4675 | ||
98d90582 | 4676 | static void avic_handle_dfr_update(struct kvm_vcpu *vcpu) |
18f40c53 SS |
4677 | { |
4678 | struct vcpu_svm *svm = to_svm(vcpu); | |
18f40c53 | 4679 | u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); |
18f40c53 | 4680 | |
98d90582 SS |
4681 | if (svm->dfr_reg == dfr) |
4682 | return; | |
18f40c53 | 4683 | |
98d90582 SS |
4684 | avic_invalidate_logical_id_entry(vcpu); |
4685 | svm->dfr_reg = dfr; | |
18f40c53 SS |
4686 | } |
4687 | ||
4688 | static int avic_unaccel_trap_write(struct vcpu_svm *svm) | |
4689 | { | |
4690 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
4691 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4692 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4693 | ||
4694 | switch (offset) { | |
4695 | case APIC_ID: | |
4696 | if (avic_handle_apic_id_update(&svm->vcpu)) | |
4697 | return 0; | |
4698 | break; | |
4699 | case APIC_LDR: | |
4700 | if (avic_handle_ldr_update(&svm->vcpu)) | |
4701 | return 0; | |
4702 | break; | |
4703 | case APIC_DFR: | |
4704 | avic_handle_dfr_update(&svm->vcpu); | |
4705 | break; | |
4706 | default: | |
4707 | break; | |
4708 | } | |
4709 | ||
4710 | kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); | |
4711 | ||
4712 | return 1; | |
4713 | } | |
4714 | ||
4715 | static bool is_avic_unaccelerated_access_trap(u32 offset) | |
4716 | { | |
4717 | bool ret = false; | |
4718 | ||
4719 | switch (offset) { | |
4720 | case APIC_ID: | |
4721 | case APIC_EOI: | |
4722 | case APIC_RRR: | |
4723 | case APIC_LDR: | |
4724 | case APIC_DFR: | |
4725 | case APIC_SPIV: | |
4726 | case APIC_ESR: | |
4727 | case APIC_ICR: | |
4728 | case APIC_LVTT: | |
4729 | case APIC_LVTTHMR: | |
4730 | case APIC_LVTPC: | |
4731 | case APIC_LVT0: | |
4732 | case APIC_LVT1: | |
4733 | case APIC_LVTERR: | |
4734 | case APIC_TMICT: | |
4735 | case APIC_TDCR: | |
4736 | ret = true; | |
4737 | break; | |
4738 | default: | |
4739 | break; | |
4740 | } | |
4741 | return ret; | |
4742 | } | |
4743 | ||
4744 | static int avic_unaccelerated_access_interception(struct vcpu_svm *svm) | |
4745 | { | |
4746 | int ret = 0; | |
4747 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4748 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4749 | u32 vector = svm->vmcb->control.exit_info_2 & | |
4750 | AVIC_UNACCEL_ACCESS_VECTOR_MASK; | |
4751 | bool write = (svm->vmcb->control.exit_info_1 >> 32) & | |
4752 | AVIC_UNACCEL_ACCESS_WRITE_MASK; | |
4753 | bool trap = is_avic_unaccelerated_access_trap(offset); | |
4754 | ||
4755 | trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, | |
4756 | trap, write, vector); | |
4757 | if (trap) { | |
4758 | /* Handling Trap */ | |
4759 | WARN_ONCE(!write, "svm: Handling trap read.\n"); | |
4760 | ret = avic_unaccel_trap_write(svm); | |
4761 | } else { | |
4762 | /* Handling Fault */ | |
60fc3d02 | 4763 | ret = kvm_emulate_instruction(&svm->vcpu, 0); |
18f40c53 SS |
4764 | } |
4765 | ||
4766 | return ret; | |
4767 | } | |
4768 | ||
09941fbb | 4769 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
4770 | [SVM_EXIT_READ_CR0] = cr_interception, |
4771 | [SVM_EXIT_READ_CR3] = cr_interception, | |
4772 | [SVM_EXIT_READ_CR4] = cr_interception, | |
4773 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 4774 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 4775 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
4776 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
4777 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 4778 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
4779 | [SVM_EXIT_READ_DR0] = dr_interception, |
4780 | [SVM_EXIT_READ_DR1] = dr_interception, | |
4781 | [SVM_EXIT_READ_DR2] = dr_interception, | |
4782 | [SVM_EXIT_READ_DR3] = dr_interception, | |
4783 | [SVM_EXIT_READ_DR4] = dr_interception, | |
4784 | [SVM_EXIT_READ_DR5] = dr_interception, | |
4785 | [SVM_EXIT_READ_DR6] = dr_interception, | |
4786 | [SVM_EXIT_READ_DR7] = dr_interception, | |
4787 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
4788 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
4789 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
4790 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
4791 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
4792 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
4793 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
4794 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
4795 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
4796 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 4797 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 | 4798 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
e0231715 | 4799 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
54a20552 | 4800 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
9718420e | 4801 | [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception, |
e0231715 | 4802 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 4803 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
4804 | [SVM_EXIT_SMI] = nop_on_interception, |
4805 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 4806 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 4807 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 4808 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 4809 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 4810 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 4811 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 4812 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 4813 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 4814 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 4815 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
4816 | [SVM_EXIT_MSR] = msr_interception, |
4817 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 4818 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 4819 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 4820 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
4821 | [SVM_EXIT_VMLOAD] = vmload_interception, |
4822 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
4823 | [SVM_EXIT_STGI] = stgi_interception, |
4824 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 4825 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 4826 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
4827 | [SVM_EXIT_MONITOR] = monitor_interception, |
4828 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 4829 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
0cb8410b | 4830 | [SVM_EXIT_RDPRU] = rdpru_interception, |
d0006530 | 4831 | [SVM_EXIT_NPF] = npf_interception, |
7607b717 | 4832 | [SVM_EXIT_RSM] = rsm_interception, |
18f40c53 SS |
4833 | [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, |
4834 | [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, | |
6aa8b732 AK |
4835 | }; |
4836 | ||
ae8cc059 | 4837 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
4838 | { |
4839 | struct vcpu_svm *svm = to_svm(vcpu); | |
4840 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4841 | struct vmcb_save_area *save = &svm->vmcb->save; | |
4842 | ||
6f2f8453 PB |
4843 | if (!dump_invalid_vmcb) { |
4844 | pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n"); | |
4845 | return; | |
4846 | } | |
4847 | ||
3f10c846 | 4848 | pr_err("VMCB Control Area:\n"); |
ae8cc059 JP |
4849 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
4850 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
4851 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
4852 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
4853 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
4854 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
4855 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
1d8fb44a BM |
4856 | pr_err("%-20s%d\n", "pause filter threshold:", |
4857 | control->pause_filter_thresh); | |
ae8cc059 JP |
4858 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); |
4859 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
4860 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
4861 | pr_err("%-20s%d\n", "asid:", control->asid); | |
4862 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
4863 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
4864 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
4865 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
4866 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
4867 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
4868 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
4869 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
4870 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
4871 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
4872 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 4873 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
4874 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
4875 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
0dc92119 | 4876 | pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext); |
ae8cc059 | 4877 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); |
44a95dae SS |
4878 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
4879 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
4880 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 4881 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
4882 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
4883 | "es:", | |
4884 | save->es.selector, save->es.attrib, | |
4885 | save->es.limit, save->es.base); | |
4886 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4887 | "cs:", | |
4888 | save->cs.selector, save->cs.attrib, | |
4889 | save->cs.limit, save->cs.base); | |
4890 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4891 | "ss:", | |
4892 | save->ss.selector, save->ss.attrib, | |
4893 | save->ss.limit, save->ss.base); | |
4894 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4895 | "ds:", | |
4896 | save->ds.selector, save->ds.attrib, | |
4897 | save->ds.limit, save->ds.base); | |
4898 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4899 | "fs:", | |
4900 | save->fs.selector, save->fs.attrib, | |
4901 | save->fs.limit, save->fs.base); | |
4902 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4903 | "gs:", | |
4904 | save->gs.selector, save->gs.attrib, | |
4905 | save->gs.limit, save->gs.base); | |
4906 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4907 | "gdtr:", | |
4908 | save->gdtr.selector, save->gdtr.attrib, | |
4909 | save->gdtr.limit, save->gdtr.base); | |
4910 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4911 | "ldtr:", | |
4912 | save->ldtr.selector, save->ldtr.attrib, | |
4913 | save->ldtr.limit, save->ldtr.base); | |
4914 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4915 | "idtr:", | |
4916 | save->idtr.selector, save->idtr.attrib, | |
4917 | save->idtr.limit, save->idtr.base); | |
4918 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4919 | "tr:", | |
4920 | save->tr.selector, save->tr.attrib, | |
4921 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
4922 | pr_err("cpl: %d efer: %016llx\n", |
4923 | save->cpl, save->efer); | |
ae8cc059 JP |
4924 | pr_err("%-15s %016llx %-13s %016llx\n", |
4925 | "cr0:", save->cr0, "cr2:", save->cr2); | |
4926 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4927 | "cr3:", save->cr3, "cr4:", save->cr4); | |
4928 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4929 | "dr6:", save->dr6, "dr7:", save->dr7); | |
4930 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4931 | "rip:", save->rip, "rflags:", save->rflags); | |
4932 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4933 | "rsp:", save->rsp, "rax:", save->rax); | |
4934 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4935 | "star:", save->star, "lstar:", save->lstar); | |
4936 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4937 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
4938 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4939 | "kernel_gs_base:", save->kernel_gs_base, | |
4940 | "sysenter_cs:", save->sysenter_cs); | |
4941 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4942 | "sysenter_esp:", save->sysenter_esp, | |
4943 | "sysenter_eip:", save->sysenter_eip); | |
4944 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4945 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
4946 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4947 | "br_from:", save->br_from, "br_to:", save->br_to); | |
4948 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4949 | "excp_from:", save->last_excp_from, | |
4950 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
4951 | } |
4952 | ||
586f9607 AK |
4953 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
4954 | { | |
4955 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
4956 | ||
4957 | *info1 = control->exit_info_1; | |
4958 | *info2 = control->exit_info_2; | |
4959 | } | |
4960 | ||
1e9e2622 WL |
4961 | static int handle_exit(struct kvm_vcpu *vcpu, |
4962 | enum exit_fastpath_completion exit_fastpath) | |
6aa8b732 | 4963 | { |
04d2cc77 | 4964 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 4965 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 4966 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 4967 | |
8b89fe1f PB |
4968 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
4969 | ||
4ee546b4 | 4970 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
4971 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
4972 | if (npt_enabled) | |
4973 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 4974 | |
cd3ff653 JR |
4975 | if (unlikely(svm->nested.exit_required)) { |
4976 | nested_svm_vmexit(svm); | |
4977 | svm->nested.exit_required = false; | |
4978 | ||
4979 | return 1; | |
4980 | } | |
4981 | ||
2030753d | 4982 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
4983 | int vmexit; |
4984 | ||
d8cabddf JR |
4985 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
4986 | svm->vmcb->control.exit_info_1, | |
4987 | svm->vmcb->control.exit_info_2, | |
4988 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
4989 | svm->vmcb->control.exit_int_info_err, |
4990 | KVM_ISA_SVM); | |
d8cabddf | 4991 | |
410e4d57 JR |
4992 | vmexit = nested_svm_exit_special(svm); |
4993 | ||
4994 | if (vmexit == NESTED_EXIT_CONTINUE) | |
4995 | vmexit = nested_svm_exit_handled(svm); | |
4996 | ||
4997 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 4998 | return 1; |
cf74a78b AG |
4999 | } |
5000 | ||
a5c3832d JR |
5001 | svm_complete_interrupts(svm); |
5002 | ||
04d2cc77 AK |
5003 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
5004 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
5005 | kvm_run->fail_entry.hardware_entry_failure_reason | |
5006 | = svm->vmcb->control.exit_code; | |
3f10c846 | 5007 | dump_vmcb(vcpu); |
04d2cc77 AK |
5008 | return 0; |
5009 | } | |
5010 | ||
a2fa3e9f | 5011 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 5012 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
5013 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
5014 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 5015 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 5016 | "exit_code 0x%x\n", |
b8688d51 | 5017 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
5018 | exit_code); |
5019 | ||
1e9e2622 WL |
5020 | if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { |
5021 | kvm_skip_emulated_instruction(vcpu); | |
5022 | return 1; | |
5023 | } else if (exit_code >= ARRAY_SIZE(svm_exit_handlers) | |
56919c5c | 5024 | || !svm_exit_handlers[exit_code]) { |
7396d337 LA |
5025 | vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code); |
5026 | dump_vmcb(vcpu); | |
5027 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5028 | vcpu->run->internal.suberror = | |
5029 | KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; | |
5030 | vcpu->run->internal.ndata = 1; | |
5031 | vcpu->run->internal.data[0] = exit_code; | |
5032 | return 0; | |
6aa8b732 AK |
5033 | } |
5034 | ||
3dcb2a3f AA |
5035 | #ifdef CONFIG_RETPOLINE |
5036 | if (exit_code == SVM_EXIT_MSR) | |
5037 | return msr_interception(svm); | |
5038 | else if (exit_code == SVM_EXIT_VINTR) | |
5039 | return interrupt_window_interception(svm); | |
5040 | else if (exit_code == SVM_EXIT_INTR) | |
5041 | return intr_interception(svm); | |
5042 | else if (exit_code == SVM_EXIT_HLT) | |
5043 | return halt_interception(svm); | |
5044 | else if (exit_code == SVM_EXIT_NPF) | |
5045 | return npf_interception(svm); | |
5046 | #endif | |
851ba692 | 5047 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
5048 | } |
5049 | ||
5050 | static void reload_tss(struct kvm_vcpu *vcpu) | |
5051 | { | |
5052 | int cpu = raw_smp_processor_id(); | |
5053 | ||
0fe1e009 TH |
5054 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
5055 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
5056 | load_TR_desc(); |
5057 | } | |
5058 | ||
70cd94e6 BS |
5059 | static void pre_sev_run(struct vcpu_svm *svm, int cpu) |
5060 | { | |
5061 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); | |
5062 | int asid = sev_get_asid(svm->vcpu.kvm); | |
5063 | ||
5064 | /* Assign the asid allocated with this SEV guest */ | |
5065 | svm->vmcb->control.asid = asid; | |
5066 | ||
5067 | /* | |
5068 | * Flush guest TLB: | |
5069 | * | |
5070 | * 1) when different VMCB for the same ASID is to be run on the same host CPU. | |
5071 | * 2) or this VMCB was executed on different host CPU in previous VMRUNs. | |
5072 | */ | |
5073 | if (sd->sev_vmcbs[asid] == svm->vmcb && | |
5074 | svm->last_cpu == cpu) | |
5075 | return; | |
5076 | ||
5077 | svm->last_cpu = cpu; | |
5078 | sd->sev_vmcbs[asid] = svm->vmcb; | |
5079 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
5080 | mark_dirty(svm->vmcb, VMCB_ASID); | |
5081 | } | |
5082 | ||
e756fc62 | 5083 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
5084 | { |
5085 | int cpu = raw_smp_processor_id(); | |
5086 | ||
0fe1e009 | 5087 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 5088 | |
70cd94e6 BS |
5089 | if (sev_guest(svm->vcpu.kvm)) |
5090 | return pre_sev_run(svm, cpu); | |
5091 | ||
4b656b12 | 5092 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
5093 | if (svm->asid_generation != sd->asid_generation) |
5094 | new_asid(svm, sd); | |
6aa8b732 AK |
5095 | } |
5096 | ||
95ba8273 GN |
5097 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
5098 | { | |
5099 | struct vcpu_svm *svm = to_svm(vcpu); | |
5100 | ||
5101 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
5102 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 5103 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
5104 | ++vcpu->stat.nmi_injections; |
5105 | } | |
6aa8b732 | 5106 | |
85f455f7 | 5107 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
5108 | { |
5109 | struct vmcb_control_area *control; | |
5110 | ||
340d3bc3 | 5111 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 5112 | control = &svm->vmcb->control; |
85f455f7 | 5113 | control->int_vector = irq; |
6aa8b732 AK |
5114 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
5115 | control->int_ctl |= V_IRQ_MASK | | |
5116 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 5117 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
5118 | } |
5119 | ||
66fd3f7f | 5120 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
5121 | { |
5122 | struct vcpu_svm *svm = to_svm(vcpu); | |
5123 | ||
2af9194d | 5124 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 5125 | |
9fb2d2b4 GN |
5126 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
5127 | ++vcpu->stat.irq_injections; | |
5128 | ||
219b65dc AG |
5129 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
5130 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
5131 | } |
5132 | ||
3bbf3565 SS |
5133 | static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu) |
5134 | { | |
5135 | return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK); | |
5136 | } | |
5137 | ||
95ba8273 | 5138 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
5139 | { |
5140 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 5141 | |
49d654d8 | 5142 | if (svm_nested_virtualize_tpr(vcpu)) |
88ab24ad JR |
5143 | return; |
5144 | ||
596f3142 RK |
5145 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
5146 | ||
95ba8273 | 5147 | if (irr == -1) |
aaacfc9a JR |
5148 | return; |
5149 | ||
95ba8273 | 5150 | if (tpr >= irr) |
4ee546b4 | 5151 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 5152 | } |
aaacfc9a | 5153 | |
8d860bbe | 5154 | static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu) |
8d14695f YZ |
5155 | { |
5156 | return; | |
5157 | } | |
5158 | ||
44a95dae SS |
5159 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) |
5160 | { | |
d62caabb AS |
5161 | } |
5162 | ||
67c9dddc | 5163 | static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
44a95dae | 5164 | { |
d62caabb AS |
5165 | } |
5166 | ||
8937d762 SS |
5167 | static int svm_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) |
5168 | { | |
5169 | int ret = 0; | |
5170 | unsigned long flags; | |
5171 | struct amd_svm_iommu_ir *ir; | |
5172 | struct vcpu_svm *svm = to_svm(vcpu); | |
5173 | ||
5174 | if (!kvm_arch_has_assigned_device(vcpu->kvm)) | |
5175 | return 0; | |
5176 | ||
5177 | /* | |
5178 | * Here, we go through the per-vcpu ir_list to update all existing | |
5179 | * interrupt remapping table entry targeting this vcpu. | |
5180 | */ | |
5181 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
5182 | ||
5183 | if (list_empty(&svm->ir_list)) | |
5184 | goto out; | |
5185 | ||
5186 | list_for_each_entry(ir, &svm->ir_list, node) { | |
5187 | if (activate) | |
5188 | ret = amd_iommu_activate_guest_mode(ir->data); | |
5189 | else | |
5190 | ret = amd_iommu_deactivate_guest_mode(ir->data); | |
5191 | if (ret) | |
5192 | break; | |
5193 | } | |
5194 | out: | |
5195 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
5196 | return ret; | |
5197 | } | |
5198 | ||
d62caabb | 5199 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 5200 | { |
44a95dae SS |
5201 | struct vcpu_svm *svm = to_svm(vcpu); |
5202 | struct vmcb *vmcb = svm->vmcb; | |
8937d762 | 5203 | bool activated = kvm_vcpu_apicv_active(vcpu); |
44a95dae | 5204 | |
6c3e4422 SS |
5205 | if (activated) { |
5206 | /** | |
5207 | * During AVIC temporary deactivation, guest could update | |
5208 | * APIC ID, DFR and LDR registers, which would not be trapped | |
5209 | * by avic_unaccelerated_access_interception(). In this case, | |
5210 | * we need to check and update the AVIC logical APIC ID table | |
5211 | * accordingly before re-activating. | |
5212 | */ | |
5213 | avic_post_state_restore(vcpu); | |
c57cd3c8 | 5214 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; |
6c3e4422 | 5215 | } else { |
c57cd3c8 | 5216 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; |
6c3e4422 | 5217 | } |
c57cd3c8 | 5218 | mark_dirty(vmcb, VMCB_AVIC); |
8937d762 SS |
5219 | |
5220 | svm_set_pi_irte_mode(vcpu, activated); | |
c7c9c56c YZ |
5221 | } |
5222 | ||
6308630b | 5223 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
5224 | { |
5225 | return; | |
5226 | } | |
5227 | ||
340d3bc3 SS |
5228 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
5229 | { | |
5230 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
5231 | smp_mb__after_atomic(); | |
5232 | ||
0532dd52 SS |
5233 | if (avic_vcpu_is_running(vcpu)) { |
5234 | int cpuid = vcpu->cpu; | |
5235 | ||
5236 | if (cpuid != get_cpu()) | |
5237 | wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid)); | |
5238 | put_cpu(); | |
5239 | } else | |
340d3bc3 SS |
5240 | kvm_vcpu_wake_up(vcpu); |
5241 | } | |
5242 | ||
17e433b5 WL |
5243 | static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) |
5244 | { | |
5245 | return false; | |
5246 | } | |
5247 | ||
411b44ba SS |
5248 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) |
5249 | { | |
5250 | unsigned long flags; | |
5251 | struct amd_svm_iommu_ir *cur; | |
5252 | ||
5253 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
5254 | list_for_each_entry(cur, &svm->ir_list, node) { | |
5255 | if (cur->data != pi->ir_data) | |
5256 | continue; | |
5257 | list_del(&cur->node); | |
5258 | kfree(cur); | |
5259 | break; | |
5260 | } | |
5261 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
5262 | } | |
5263 | ||
5264 | static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) | |
5265 | { | |
5266 | int ret = 0; | |
5267 | unsigned long flags; | |
5268 | struct amd_svm_iommu_ir *ir; | |
5269 | ||
5270 | /** | |
5271 | * In some cases, the existing irte is updaed and re-set, | |
5272 | * so we need to check here if it's already been * added | |
5273 | * to the ir_list. | |
5274 | */ | |
5275 | if (pi->ir_data && (pi->prev_ga_tag != 0)) { | |
5276 | struct kvm *kvm = svm->vcpu.kvm; | |
5277 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); | |
5278 | struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
5279 | struct vcpu_svm *prev_svm; | |
5280 | ||
5281 | if (!prev_vcpu) { | |
5282 | ret = -EINVAL; | |
5283 | goto out; | |
5284 | } | |
5285 | ||
5286 | prev_svm = to_svm(prev_vcpu); | |
5287 | svm_ir_list_del(prev_svm, pi); | |
5288 | } | |
5289 | ||
5290 | /** | |
5291 | * Allocating new amd_iommu_pi_data, which will get | |
5292 | * add to the per-vcpu ir_list. | |
5293 | */ | |
1ec69647 | 5294 | ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT); |
411b44ba SS |
5295 | if (!ir) { |
5296 | ret = -ENOMEM; | |
5297 | goto out; | |
5298 | } | |
5299 | ir->data = pi->ir_data; | |
5300 | ||
5301 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
5302 | list_add(&ir->node, &svm->ir_list); | |
5303 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
5304 | out: | |
5305 | return ret; | |
5306 | } | |
5307 | ||
5308 | /** | |
5309 | * Note: | |
5310 | * The HW cannot support posting multicast/broadcast | |
5311 | * interrupts to a vCPU. So, we still use legacy interrupt | |
5312 | * remapping for these kind of interrupts. | |
5313 | * | |
5314 | * For lowest-priority interrupts, we only support | |
5315 | * those with single CPU as the destination, e.g. user | |
5316 | * configures the interrupts via /proc/irq or uses | |
5317 | * irqbalance to make the interrupts single-CPU. | |
5318 | */ | |
5319 | static int | |
5320 | get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, | |
5321 | struct vcpu_data *vcpu_info, struct vcpu_svm **svm) | |
5322 | { | |
5323 | struct kvm_lapic_irq irq; | |
5324 | struct kvm_vcpu *vcpu = NULL; | |
5325 | ||
5326 | kvm_set_msi_irq(kvm, e, &irq); | |
5327 | ||
fdcf7562 AG |
5328 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || |
5329 | !kvm_irq_is_postable(&irq)) { | |
411b44ba SS |
5330 | pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", |
5331 | __func__, irq.vector); | |
5332 | return -1; | |
5333 | } | |
5334 | ||
5335 | pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, | |
5336 | irq.vector); | |
5337 | *svm = to_svm(vcpu); | |
d0ec49d4 | 5338 | vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page)); |
411b44ba SS |
5339 | vcpu_info->vector = irq.vector; |
5340 | ||
5341 | return 0; | |
5342 | } | |
5343 | ||
5344 | /* | |
5345 | * svm_update_pi_irte - set IRTE for Posted-Interrupts | |
5346 | * | |
5347 | * @kvm: kvm | |
5348 | * @host_irq: host irq of the interrupt | |
5349 | * @guest_irq: gsi of the interrupt | |
5350 | * @set: set or unset PI | |
5351 | * returns 0 on success, < 0 on failure | |
5352 | */ | |
5353 | static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
5354 | uint32_t guest_irq, bool set) | |
5355 | { | |
5356 | struct kvm_kernel_irq_routing_entry *e; | |
5357 | struct kvm_irq_routing_table *irq_rt; | |
5358 | int idx, ret = -EINVAL; | |
5359 | ||
5360 | if (!kvm_arch_has_assigned_device(kvm) || | |
5361 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
5362 | return 0; | |
5363 | ||
5364 | pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n", | |
5365 | __func__, host_irq, guest_irq, set); | |
5366 | ||
5367 | idx = srcu_read_lock(&kvm->irq_srcu); | |
5368 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
5369 | WARN_ON(guest_irq >= irq_rt->nr_rt_entries); | |
5370 | ||
5371 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
5372 | struct vcpu_data vcpu_info; | |
5373 | struct vcpu_svm *svm = NULL; | |
5374 | ||
5375 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
5376 | continue; | |
5377 | ||
5378 | /** | |
5379 | * Here, we setup with legacy mode in the following cases: | |
5380 | * 1. When cannot target interrupt to a specific vcpu. | |
5381 | * 2. Unsetting posted interrupt. | |
5382 | * 3. APIC virtialization is disabled for the vcpu. | |
fdcf7562 | 5383 | * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) |
411b44ba SS |
5384 | */ |
5385 | if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && | |
5386 | kvm_vcpu_apicv_active(&svm->vcpu)) { | |
5387 | struct amd_iommu_pi_data pi; | |
5388 | ||
5389 | /* Try to enable guest_mode in IRTE */ | |
d0ec49d4 TL |
5390 | pi.base = __sme_set(page_to_phys(svm->avic_backing_page) & |
5391 | AVIC_HPA_MASK); | |
81811c16 | 5392 | pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, |
411b44ba SS |
5393 | svm->vcpu.vcpu_id); |
5394 | pi.is_guest_mode = true; | |
5395 | pi.vcpu_data = &vcpu_info; | |
5396 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
5397 | ||
5398 | /** | |
5399 | * Here, we successfully setting up vcpu affinity in | |
5400 | * IOMMU guest mode. Now, we need to store the posted | |
5401 | * interrupt information in a per-vcpu ir_list so that | |
5402 | * we can reference to them directly when we update vcpu | |
5403 | * scheduling information in IOMMU irte. | |
5404 | */ | |
5405 | if (!ret && pi.is_guest_mode) | |
5406 | svm_ir_list_add(svm, &pi); | |
5407 | } else { | |
5408 | /* Use legacy mode in IRTE */ | |
5409 | struct amd_iommu_pi_data pi; | |
5410 | ||
5411 | /** | |
5412 | * Here, pi is used to: | |
5413 | * - Tell IOMMU to use legacy mode for this interrupt. | |
5414 | * - Retrieve ga_tag of prior interrupt remapping data. | |
5415 | */ | |
5416 | pi.is_guest_mode = false; | |
5417 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
5418 | ||
5419 | /** | |
5420 | * Check if the posted interrupt was previously | |
5421 | * setup with the guest_mode by checking if the ga_tag | |
5422 | * was cached. If so, we need to clean up the per-vcpu | |
5423 | * ir_list. | |
5424 | */ | |
5425 | if (!ret && pi.prev_ga_tag) { | |
5426 | int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); | |
5427 | struct kvm_vcpu *vcpu; | |
5428 | ||
5429 | vcpu = kvm_get_vcpu_by_id(kvm, id); | |
5430 | if (vcpu) | |
5431 | svm_ir_list_del(to_svm(vcpu), &pi); | |
5432 | } | |
5433 | } | |
5434 | ||
5435 | if (!ret && svm) { | |
2698d82e | 5436 | trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id, |
5437 | e->gsi, vcpu_info.vector, | |
411b44ba SS |
5438 | vcpu_info.pi_desc_addr, set); |
5439 | } | |
5440 | ||
5441 | if (ret < 0) { | |
5442 | pr_err("%s: failed to update PI IRTE\n", __func__); | |
5443 | goto out; | |
5444 | } | |
5445 | } | |
5446 | ||
5447 | ret = 0; | |
5448 | out: | |
5449 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
5450 | return ret; | |
5451 | } | |
5452 | ||
95ba8273 GN |
5453 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
5454 | { | |
5455 | struct vcpu_svm *svm = to_svm(vcpu); | |
5456 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
5457 | int ret; |
5458 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
5459 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
5460 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
5461 | ||
5462 | return ret; | |
aaacfc9a JR |
5463 | } |
5464 | ||
3cfc3092 JK |
5465 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
5466 | { | |
5467 | struct vcpu_svm *svm = to_svm(vcpu); | |
5468 | ||
5469 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
5470 | } | |
5471 | ||
5472 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5473 | { | |
5474 | struct vcpu_svm *svm = to_svm(vcpu); | |
5475 | ||
5476 | if (masked) { | |
5477 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 5478 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
5479 | } else { |
5480 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 5481 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
5482 | } |
5483 | } | |
5484 | ||
78646121 GN |
5485 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
5486 | { | |
5487 | struct vcpu_svm *svm = to_svm(vcpu); | |
5488 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
5489 | int ret; |
5490 | ||
5491 | if (!gif_set(svm) || | |
5492 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
5493 | return 0; | |
5494 | ||
f6e78475 | 5495 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 5496 | |
2030753d | 5497 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
5498 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
5499 | ||
5500 | return ret; | |
78646121 GN |
5501 | } |
5502 | ||
c9a7953f | 5503 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 5504 | { |
219b65dc | 5505 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 5506 | |
340d3bc3 SS |
5507 | if (kvm_vcpu_apicv_active(vcpu)) |
5508 | return; | |
5509 | ||
e0231715 JR |
5510 | /* |
5511 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
5512 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
5513 | * get that intercept, this function will be called again though and | |
640bd6e5 JN |
5514 | * we'll get the vintr intercept. However, if the vGIF feature is |
5515 | * enabled, the STGI interception will not occur. Enable the irq | |
5516 | * window under the assumption that the hardware will set the GIF. | |
e0231715 | 5517 | */ |
640bd6e5 | 5518 | if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) { |
219b65dc AG |
5519 | svm_set_vintr(svm); |
5520 | svm_inject_irq(svm, 0x0); | |
5521 | } | |
85f455f7 ED |
5522 | } |
5523 | ||
c9a7953f | 5524 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 5525 | { |
04d2cc77 | 5526 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 5527 | |
44c11430 GN |
5528 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
5529 | == HF_NMI_MASK) | |
c9a7953f | 5530 | return; /* IRET will cause a vm exit */ |
44c11430 | 5531 | |
640bd6e5 JN |
5532 | if (!gif_set(svm)) { |
5533 | if (vgif_enabled(svm)) | |
5534 | set_intercept(svm, INTERCEPT_STGI); | |
1a5e1852 | 5535 | return; /* STGI will cause a vm exit */ |
640bd6e5 | 5536 | } |
1a5e1852 LP |
5537 | |
5538 | if (svm->nested.exit_required) | |
5539 | return; /* we're not going to run the guest yet */ | |
5540 | ||
e0231715 JR |
5541 | /* |
5542 | * Something prevents NMI from been injected. Single step over possible | |
5543 | * problem (IRET or exception injection or interrupt shadow) | |
5544 | */ | |
ab2f4d73 | 5545 | svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu); |
6be7d306 | 5546 | svm->nmi_singlestep = true; |
44c11430 | 5547 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
5548 | } |
5549 | ||
cbc94022 IE |
5550 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5551 | { | |
5552 | return 0; | |
5553 | } | |
5554 | ||
2ac52ab8 SC |
5555 | static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) |
5556 | { | |
5557 | return 0; | |
5558 | } | |
5559 | ||
c2ba05cc | 5560 | static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) |
d9e368d6 | 5561 | { |
38e5e92f JR |
5562 | struct vcpu_svm *svm = to_svm(vcpu); |
5563 | ||
5564 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
5565 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
5566 | else | |
5567 | svm->asid_generation--; | |
d9e368d6 AK |
5568 | } |
5569 | ||
faff8758 JS |
5570 | static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva) |
5571 | { | |
5572 | struct vcpu_svm *svm = to_svm(vcpu); | |
5573 | ||
5574 | invlpga(gva, svm->vmcb->control.asid); | |
5575 | } | |
5576 | ||
04d2cc77 AK |
5577 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
5578 | { | |
5579 | } | |
5580 | ||
d7bf8221 JR |
5581 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
5582 | { | |
5583 | struct vcpu_svm *svm = to_svm(vcpu); | |
5584 | ||
3bbf3565 | 5585 | if (svm_nested_virtualize_tpr(vcpu)) |
88ab24ad JR |
5586 | return; |
5587 | ||
4ee546b4 | 5588 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 5589 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 5590 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
5591 | } |
5592 | } | |
5593 | ||
649d6864 JR |
5594 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
5595 | { | |
5596 | struct vcpu_svm *svm = to_svm(vcpu); | |
5597 | u64 cr8; | |
5598 | ||
3bbf3565 SS |
5599 | if (svm_nested_virtualize_tpr(vcpu) || |
5600 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
5601 | return; |
5602 | ||
649d6864 JR |
5603 | cr8 = kvm_get_cr8(vcpu); |
5604 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
5605 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
5606 | } | |
5607 | ||
9222be18 GN |
5608 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
5609 | { | |
5610 | u8 vector; | |
5611 | int type; | |
5612 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
5613 | unsigned int3_injected = svm->int3_injected; |
5614 | ||
5615 | svm->int3_injected = 0; | |
9222be18 | 5616 | |
bd3d1ec3 AK |
5617 | /* |
5618 | * If we've made progress since setting HF_IRET_MASK, we've | |
5619 | * executed an IRET and can allow NMI injection. | |
5620 | */ | |
5621 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
5622 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 5623 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
5624 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
5625 | } | |
44c11430 | 5626 | |
9222be18 GN |
5627 | svm->vcpu.arch.nmi_injected = false; |
5628 | kvm_clear_exception_queue(&svm->vcpu); | |
5629 | kvm_clear_interrupt_queue(&svm->vcpu); | |
5630 | ||
5631 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
5632 | return; | |
5633 | ||
3842d135 AK |
5634 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
5635 | ||
9222be18 GN |
5636 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
5637 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
5638 | ||
5639 | switch (type) { | |
5640 | case SVM_EXITINTINFO_TYPE_NMI: | |
5641 | svm->vcpu.arch.nmi_injected = true; | |
5642 | break; | |
5643 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
5644 | /* |
5645 | * In case of software exceptions, do not reinject the vector, | |
5646 | * but re-execute the instruction instead. Rewind RIP first | |
5647 | * if we emulated INT3 before. | |
5648 | */ | |
5649 | if (kvm_exception_is_soft(vector)) { | |
5650 | if (vector == BP_VECTOR && int3_injected && | |
5651 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
5652 | kvm_rip_write(&svm->vcpu, | |
5653 | kvm_rip_read(&svm->vcpu) - | |
5654 | int3_injected); | |
9222be18 | 5655 | break; |
66b7138f | 5656 | } |
9222be18 GN |
5657 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
5658 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 5659 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
5660 | |
5661 | } else | |
ce7ddec4 | 5662 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
5663 | break; |
5664 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 5665 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
5666 | break; |
5667 | default: | |
5668 | break; | |
5669 | } | |
5670 | } | |
5671 | ||
b463a6f7 AK |
5672 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
5673 | { | |
5674 | struct vcpu_svm *svm = to_svm(vcpu); | |
5675 | struct vmcb_control_area *control = &svm->vmcb->control; | |
5676 | ||
5677 | control->exit_int_info = control->event_inj; | |
5678 | control->exit_int_info_err = control->event_inj_err; | |
5679 | control->event_inj = 0; | |
5680 | svm_complete_interrupts(svm); | |
5681 | } | |
5682 | ||
851ba692 | 5683 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 5684 | { |
a2fa3e9f | 5685 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 5686 | |
2041a06a JR |
5687 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
5688 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
5689 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
5690 | ||
cd3ff653 JR |
5691 | /* |
5692 | * A vmexit emulation is required before the vcpu can be executed | |
5693 | * again. | |
5694 | */ | |
5695 | if (unlikely(svm->nested.exit_required)) | |
5696 | return; | |
5697 | ||
a12713c2 LP |
5698 | /* |
5699 | * Disable singlestep if we're injecting an interrupt/exception. | |
5700 | * We don't want our modified rflags to be pushed on the stack where | |
5701 | * we might not be able to easily reset them if we disabled NMI | |
5702 | * singlestep later. | |
5703 | */ | |
5704 | if (svm->nmi_singlestep && svm->vmcb->control.event_inj) { | |
5705 | /* | |
5706 | * Event injection happens before external interrupts cause a | |
5707 | * vmexit and interrupts are disabled here, so smp_send_reschedule | |
5708 | * is enough to force an immediate vmexit. | |
5709 | */ | |
5710 | disable_nmi_singlestep(svm); | |
5711 | smp_send_reschedule(vcpu->cpu); | |
5712 | } | |
5713 | ||
e756fc62 | 5714 | pre_svm_run(svm); |
6aa8b732 | 5715 | |
649d6864 JR |
5716 | sync_lapic_to_cr8(vcpu); |
5717 | ||
cda0ffdd | 5718 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 5719 | |
04d2cc77 | 5720 | clgi(); |
139a12cf | 5721 | kvm_load_guest_xsave_state(vcpu); |
04d2cc77 | 5722 | |
b6c4bc65 WL |
5723 | if (lapic_in_kernel(vcpu) && |
5724 | vcpu->arch.apic->lapic_timer.timer_advance_ns) | |
5725 | kvm_wait_lapic_expire(vcpu); | |
5726 | ||
b2ac58f9 KA |
5727 | /* |
5728 | * If this vCPU has touched SPEC_CTRL, restore the guest's value if | |
5729 | * it's non-zero. Since vmentry is serialising on affected CPUs, there | |
5730 | * is no need to worry about the conditional branch over the wrmsr | |
5731 | * being speculatively taken. | |
5732 | */ | |
ccbcd267 | 5733 | x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl); |
b2ac58f9 | 5734 | |
024d83ca TG |
5735 | local_irq_enable(); |
5736 | ||
6aa8b732 | 5737 | asm volatile ( |
7454766f AK |
5738 | "push %%" _ASM_BP "; \n\t" |
5739 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
5740 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
5741 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
5742 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
5743 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
5744 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 5745 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
5746 | "mov %c[r8](%[svm]), %%r8 \n\t" |
5747 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
5748 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
5749 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
5750 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
5751 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
5752 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
5753 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
5754 | #endif |
5755 | ||
6aa8b732 | 5756 | /* Enter guest mode */ |
7454766f AK |
5757 | "push %%" _ASM_AX " \n\t" |
5758 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
ac5ffda2 UB |
5759 | __ex("vmload %%" _ASM_AX) "\n\t" |
5760 | __ex("vmrun %%" _ASM_AX) "\n\t" | |
5761 | __ex("vmsave %%" _ASM_AX) "\n\t" | |
7454766f | 5762 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
5763 | |
5764 | /* Save guest registers, load host registers */ | |
7454766f AK |
5765 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
5766 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
5767 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
5768 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
5769 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
5770 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 5771 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
5772 | "mov %%r8, %c[r8](%[svm]) \n\t" |
5773 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
5774 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
5775 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
5776 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
5777 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
5778 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
5779 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
0cb5b306 JM |
5780 | /* |
5781 | * Clear host registers marked as clobbered to prevent | |
5782 | * speculative use. | |
5783 | */ | |
43ce76ce UB |
5784 | "xor %%r8d, %%r8d \n\t" |
5785 | "xor %%r9d, %%r9d \n\t" | |
5786 | "xor %%r10d, %%r10d \n\t" | |
5787 | "xor %%r11d, %%r11d \n\t" | |
5788 | "xor %%r12d, %%r12d \n\t" | |
5789 | "xor %%r13d, %%r13d \n\t" | |
5790 | "xor %%r14d, %%r14d \n\t" | |
5791 | "xor %%r15d, %%r15d \n\t" | |
6aa8b732 | 5792 | #endif |
43ce76ce UB |
5793 | "xor %%ebx, %%ebx \n\t" |
5794 | "xor %%ecx, %%ecx \n\t" | |
5795 | "xor %%edx, %%edx \n\t" | |
5796 | "xor %%esi, %%esi \n\t" | |
5797 | "xor %%edi, %%edi \n\t" | |
7454766f | 5798 | "pop %%" _ASM_BP |
6aa8b732 | 5799 | : |
fb3f0f51 | 5800 | : [svm]"a"(svm), |
6aa8b732 | 5801 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
5802 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
5803 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
5804 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
5805 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
5806 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
5807 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 5808 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
5809 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
5810 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
5811 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
5812 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
5813 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
5814 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
5815 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
5816 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 5817 | #endif |
54a08c04 LV |
5818 | : "cc", "memory" |
5819 | #ifdef CONFIG_X86_64 | |
7454766f | 5820 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 5821 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
5822 | #else |
5823 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
5824 | #endif |
5825 | ); | |
6aa8b732 | 5826 | |
15e6c22f TG |
5827 | /* Eliminate branch target predictions from guest mode */ |
5828 | vmexit_fill_RSB(); | |
5829 | ||
5830 | #ifdef CONFIG_X86_64 | |
5831 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
5832 | #else | |
5833 | loadsegment(fs, svm->host.fs); | |
5834 | #ifndef CONFIG_X86_32_LAZY_GS | |
5835 | loadsegment(gs, svm->host.gs); | |
5836 | #endif | |
5837 | #endif | |
5838 | ||
b2ac58f9 KA |
5839 | /* |
5840 | * We do not use IBRS in the kernel. If this vCPU has used the | |
5841 | * SPEC_CTRL MSR it may have left it on; save the value and | |
5842 | * turn it off. This is much more efficient than blindly adding | |
5843 | * it to the atomic save/restore list. Especially as the former | |
5844 | * (Saving guest MSRs on vmexit) doesn't even exist in KVM. | |
5845 | * | |
5846 | * For non-nested case: | |
5847 | * If the L01 MSR bitmap does not intercept the MSR, then we need to | |
5848 | * save it. | |
5849 | * | |
5850 | * For nested case: | |
5851 | * If the L02 MSR bitmap does not intercept the MSR, then we need to | |
5852 | * save it. | |
5853 | */ | |
946fbbc1 | 5854 | if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) |
ecb586bd | 5855 | svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); |
b2ac58f9 | 5856 | |
6aa8b732 AK |
5857 | reload_tss(vcpu); |
5858 | ||
56ba47dd AK |
5859 | local_irq_disable(); |
5860 | ||
024d83ca TG |
5861 | x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl); |
5862 | ||
13c34e07 AK |
5863 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5864 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
5865 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
5866 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
5867 | ||
3781c01c | 5868 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
dd60d217 | 5869 | kvm_before_interrupt(&svm->vcpu); |
3781c01c | 5870 | |
139a12cf | 5871 | kvm_load_host_xsave_state(vcpu); |
3781c01c JR |
5872 | stgi(); |
5873 | ||
5874 | /* Any pending NMI will happen here */ | |
5875 | ||
5876 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
dd60d217 | 5877 | kvm_after_interrupt(&svm->vcpu); |
3781c01c | 5878 | |
d7bf8221 JR |
5879 | sync_cr8_to_lapic(vcpu); |
5880 | ||
a2fa3e9f | 5881 | svm->next_rip = 0; |
9222be18 | 5882 | |
38e5e92f JR |
5883 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
5884 | ||
631bc487 GN |
5885 | /* if exit due to PF check for async PF */ |
5886 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
1261bfa3 | 5887 | svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); |
631bc487 | 5888 | |
6de4f3ad AK |
5889 | if (npt_enabled) { |
5890 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
5891 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
5892 | } | |
fe5913e4 JR |
5893 | |
5894 | /* | |
5895 | * We need to handle MC intercepts here before the vcpu has a chance to | |
5896 | * change the physical cpu | |
5897 | */ | |
5898 | if (unlikely(svm->vmcb->control.exit_code == | |
5899 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
5900 | svm_handle_mce(svm); | |
8d28fec4 RJ |
5901 | |
5902 | mark_all_clean(svm->vmcb); | |
6aa8b732 | 5903 | } |
c207aee4 | 5904 | STACK_FRAME_NON_STANDARD(svm_vcpu_run); |
6aa8b732 | 5905 | |
6aa8b732 AK |
5906 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5907 | { | |
a2fa3e9f GH |
5908 | struct vcpu_svm *svm = to_svm(vcpu); |
5909 | ||
d0ec49d4 | 5910 | svm->vmcb->save.cr3 = __sme_set(root); |
dcca1a65 | 5911 | mark_dirty(svm->vmcb, VMCB_CR); |
6aa8b732 AK |
5912 | } |
5913 | ||
1c97f0a0 JR |
5914 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5915 | { | |
5916 | struct vcpu_svm *svm = to_svm(vcpu); | |
5917 | ||
d0ec49d4 | 5918 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 5919 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
5920 | |
5921 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 5922 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 5923 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 JR |
5924 | } |
5925 | ||
6aa8b732 AK |
5926 | static int is_disabled(void) |
5927 | { | |
6031a61c JR |
5928 | u64 vm_cr; |
5929 | ||
5930 | rdmsrl(MSR_VM_CR, vm_cr); | |
5931 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
5932 | return 1; | |
5933 | ||
6aa8b732 AK |
5934 | return 0; |
5935 | } | |
5936 | ||
102d8325 IM |
5937 | static void |
5938 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5939 | { | |
5940 | /* | |
5941 | * Patch in the VMMCALL instruction: | |
5942 | */ | |
5943 | hypercall[0] = 0x0f; | |
5944 | hypercall[1] = 0x01; | |
5945 | hypercall[2] = 0xd9; | |
102d8325 IM |
5946 | } |
5947 | ||
f257d6dc | 5948 | static int __init svm_check_processor_compat(void) |
002c7f7c | 5949 | { |
f257d6dc | 5950 | return 0; |
002c7f7c YS |
5951 | } |
5952 | ||
774ead3a AK |
5953 | static bool svm_cpu_has_accelerated_tpr(void) |
5954 | { | |
5955 | return false; | |
5956 | } | |
5957 | ||
bc226f07 | 5958 | static bool svm_has_emulated_msr(int index) |
6d396b55 | 5959 | { |
e87555e5 VK |
5960 | switch (index) { |
5961 | case MSR_IA32_MCG_EXT_CTL: | |
95c5c7c7 | 5962 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: |
e87555e5 VK |
5963 | return false; |
5964 | default: | |
5965 | break; | |
5966 | } | |
5967 | ||
6d396b55 PB |
5968 | return true; |
5969 | } | |
5970 | ||
fc07e76a PB |
5971 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
5972 | { | |
5973 | return 0; | |
5974 | } | |
5975 | ||
0e851880 SY |
5976 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
5977 | { | |
6092d3d3 JR |
5978 | struct vcpu_svm *svm = to_svm(vcpu); |
5979 | ||
7204160e | 5980 | vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && |
96be4e06 | 5981 | boot_cpu_has(X86_FEATURE_XSAVE) && |
7204160e AL |
5982 | boot_cpu_has(X86_FEATURE_XSAVES); |
5983 | ||
6092d3d3 | 5984 | /* Update nrips enabled cache */ |
d6321d49 | 5985 | svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS); |
46781eae SS |
5986 | |
5987 | if (!kvm_vcpu_apicv_active(vcpu)) | |
5988 | return; | |
5989 | ||
1b4d56b8 | 5990 | guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC); |
9a0bf054 SS |
5991 | |
5992 | /* | |
5993 | * Currently, AVIC does not work with nested virtualization. | |
5994 | * So, we disable AVIC when cpuid for SVM is set in the L1 guest. | |
5995 | */ | |
5996 | if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM)) | |
5997 | kvm_request_apicv_update(vcpu->kvm, false, | |
5998 | APICV_INHIBIT_REASON_NESTED); | |
0e851880 SY |
5999 | } |
6000 | ||
87382003 | 6001 | #define F feature_bit |
50896de4 | 6002 | |
d4330ef2 JR |
6003 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
6004 | { | |
c2c63a49 | 6005 | switch (func) { |
46781eae SS |
6006 | case 0x1: |
6007 | if (avic) | |
87382003 | 6008 | entry->ecx &= ~F(X2APIC); |
46781eae | 6009 | break; |
4c62a2dc JR |
6010 | case 0x80000001: |
6011 | if (nested) | |
6012 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
6013 | break; | |
50896de4 PB |
6014 | case 0x80000008: |
6015 | if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) || | |
6016 | boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
6017 | entry->ebx |= F(VIRT_SSBD); | |
6018 | break; | |
c2c63a49 JR |
6019 | case 0x8000000A: |
6020 | entry->eax = 1; /* SVM revision 1 */ | |
6021 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
6022 | ASID emulation to nested SVM */ | |
6023 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
6024 | entry->edx = 0; /* Per default do not support any |
6025 | additional features */ | |
6026 | ||
6027 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 6028 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
50896de4 | 6029 | entry->edx |= F(NRIPS); |
c2c63a49 | 6030 | |
3d4aeaad JR |
6031 | /* Support NPT for the guest if enabled */ |
6032 | if (npt_enabled) | |
50896de4 | 6033 | entry->edx |= F(NPT); |
3d4aeaad | 6034 | |
c2c63a49 | 6035 | } |
d4330ef2 JR |
6036 | } |
6037 | ||
17cc3935 | 6038 | static int svm_get_lpage_level(void) |
344f414f | 6039 | { |
17cc3935 | 6040 | return PT_PDPE_LEVEL; |
344f414f JR |
6041 | } |
6042 | ||
4e47c7a6 SY |
6043 | static bool svm_rdtscp_supported(void) |
6044 | { | |
46896c73 | 6045 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
6046 | } |
6047 | ||
ad756a16 MJ |
6048 | static bool svm_invpcid_supported(void) |
6049 | { | |
6050 | return false; | |
6051 | } | |
6052 | ||
93c4adc7 PB |
6053 | static bool svm_mpx_supported(void) |
6054 | { | |
6055 | return false; | |
6056 | } | |
6057 | ||
55412b2e WL |
6058 | static bool svm_xsaves_supported(void) |
6059 | { | |
52297436 | 6060 | return boot_cpu_has(X86_FEATURE_XSAVES); |
55412b2e WL |
6061 | } |
6062 | ||
66336cab PB |
6063 | static bool svm_umip_emulated(void) |
6064 | { | |
6065 | return false; | |
6066 | } | |
6067 | ||
86f5201d CP |
6068 | static bool svm_pt_supported(void) |
6069 | { | |
6070 | return false; | |
6071 | } | |
6072 | ||
f5f48ee1 SY |
6073 | static bool svm_has_wbinvd_exit(void) |
6074 | { | |
6075 | return true; | |
6076 | } | |
6077 | ||
a47970ed JA |
6078 | static bool svm_pku_supported(void) |
6079 | { | |
6080 | return false; | |
6081 | } | |
6082 | ||
8061252e | 6083 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 6084 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 6085 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 6086 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 6087 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 6088 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 6089 | |
09941fbb | 6090 | static const struct __x86_intercept { |
cfec82cb JR |
6091 | u32 exit_code; |
6092 | enum x86_intercept_stage stage; | |
cfec82cb JR |
6093 | } x86_intercept_map[] = { |
6094 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
6095 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
6096 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
6097 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
6098 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
6099 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
6100 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
6101 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
6102 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
6103 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
6104 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
6105 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
6106 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
6107 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
6108 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
6109 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
6110 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
6111 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
6112 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
6113 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
6114 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
6115 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
6116 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
6117 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
6118 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
6119 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
6120 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
6121 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
6122 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
6123 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
6124 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
6125 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
6126 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
6127 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
6128 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
6129 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
6130 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
6131 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
6132 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
6133 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
6134 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
6135 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
6136 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
6137 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
6138 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
6139 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
02d4160f | 6140 | [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV), |
cfec82cb JR |
6141 | }; |
6142 | ||
8061252e | 6143 | #undef PRE_EX |
cfec82cb | 6144 | #undef POST_EX |
d7eb8203 | 6145 | #undef POST_MEM |
cfec82cb | 6146 | |
8a76d7f2 JR |
6147 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
6148 | struct x86_instruction_info *info, | |
6149 | enum x86_intercept_stage stage) | |
6150 | { | |
cfec82cb JR |
6151 | struct vcpu_svm *svm = to_svm(vcpu); |
6152 | int vmexit, ret = X86EMUL_CONTINUE; | |
6153 | struct __x86_intercept icpt_info; | |
6154 | struct vmcb *vmcb = svm->vmcb; | |
6155 | ||
6156 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
6157 | goto out; | |
6158 | ||
6159 | icpt_info = x86_intercept_map[info->intercept]; | |
6160 | ||
40e19b51 | 6161 | if (stage != icpt_info.stage) |
cfec82cb JR |
6162 | goto out; |
6163 | ||
6164 | switch (icpt_info.exit_code) { | |
6165 | case SVM_EXIT_READ_CR0: | |
6166 | if (info->intercept == x86_intercept_cr_read) | |
6167 | icpt_info.exit_code += info->modrm_reg; | |
6168 | break; | |
6169 | case SVM_EXIT_WRITE_CR0: { | |
6170 | unsigned long cr0, val; | |
6171 | u64 intercept; | |
6172 | ||
6173 | if (info->intercept == x86_intercept_cr_write) | |
6174 | icpt_info.exit_code += info->modrm_reg; | |
6175 | ||
62baf44c JK |
6176 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
6177 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
6178 | break; |
6179 | ||
6180 | intercept = svm->nested.intercept; | |
6181 | ||
6182 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
6183 | break; | |
6184 | ||
6185 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
6186 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
6187 | ||
6188 | if (info->intercept == x86_intercept_lmsw) { | |
6189 | cr0 &= 0xfUL; | |
6190 | val &= 0xfUL; | |
6191 | /* lmsw can't clear PE - catch this here */ | |
6192 | if (cr0 & X86_CR0_PE) | |
6193 | val |= X86_CR0_PE; | |
6194 | } | |
6195 | ||
6196 | if (cr0 ^ val) | |
6197 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
6198 | ||
6199 | break; | |
6200 | } | |
3b88e41a JR |
6201 | case SVM_EXIT_READ_DR0: |
6202 | case SVM_EXIT_WRITE_DR0: | |
6203 | icpt_info.exit_code += info->modrm_reg; | |
6204 | break; | |
8061252e JR |
6205 | case SVM_EXIT_MSR: |
6206 | if (info->intercept == x86_intercept_wrmsr) | |
6207 | vmcb->control.exit_info_1 = 1; | |
6208 | else | |
6209 | vmcb->control.exit_info_1 = 0; | |
6210 | break; | |
bf608f88 JR |
6211 | case SVM_EXIT_PAUSE: |
6212 | /* | |
6213 | * We get this for NOP only, but pause | |
6214 | * is rep not, check this here | |
6215 | */ | |
6216 | if (info->rep_prefix != REPE_PREFIX) | |
6217 | goto out; | |
49a8afca | 6218 | break; |
f6511935 JR |
6219 | case SVM_EXIT_IOIO: { |
6220 | u64 exit_info; | |
6221 | u32 bytes; | |
6222 | ||
f6511935 JR |
6223 | if (info->intercept == x86_intercept_in || |
6224 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
6225 | exit_info = ((info->src_val & 0xffff) << 16) | |
6226 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 6227 | bytes = info->dst_bytes; |
6493f157 | 6228 | } else { |
6cbc5f5a | 6229 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 6230 | bytes = info->src_bytes; |
f6511935 JR |
6231 | } |
6232 | ||
6233 | if (info->intercept == x86_intercept_outs || | |
6234 | info->intercept == x86_intercept_ins) | |
6235 | exit_info |= SVM_IOIO_STR_MASK; | |
6236 | ||
6237 | if (info->rep_prefix) | |
6238 | exit_info |= SVM_IOIO_REP_MASK; | |
6239 | ||
6240 | bytes = min(bytes, 4u); | |
6241 | ||
6242 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
6243 | ||
6244 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
6245 | ||
6246 | vmcb->control.exit_info_1 = exit_info; | |
6247 | vmcb->control.exit_info_2 = info->next_rip; | |
6248 | ||
6249 | break; | |
6250 | } | |
cfec82cb JR |
6251 | default: |
6252 | break; | |
6253 | } | |
6254 | ||
f104765b BD |
6255 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
6256 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
6257 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
6258 | vmcb->control.exit_code = icpt_info.exit_code; |
6259 | vmexit = nested_svm_exit_handled(svm); | |
6260 | ||
6261 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
6262 | : X86EMUL_CONTINUE; | |
6263 | ||
6264 | out: | |
6265 | return ret; | |
8a76d7f2 JR |
6266 | } |
6267 | ||
1e9e2622 WL |
6268 | static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu, |
6269 | enum exit_fastpath_completion *exit_fastpath) | |
a547c6db | 6270 | { |
1e9e2622 WL |
6271 | if (!is_guest_mode(vcpu) && |
6272 | to_svm(vcpu)->vmcb->control.exit_code == EXIT_REASON_MSR_WRITE) | |
6273 | *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); | |
a547c6db YZ |
6274 | } |
6275 | ||
ae97a3b8 RK |
6276 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
6277 | { | |
8566ac8b BM |
6278 | if (pause_filter_thresh) |
6279 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
6280 | } |
6281 | ||
be8ca170 SS |
6282 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu) |
6283 | { | |
6284 | if (avic_handle_apic_id_update(vcpu) != 0) | |
6285 | return; | |
98d90582 | 6286 | avic_handle_dfr_update(vcpu); |
be8ca170 SS |
6287 | avic_handle_ldr_update(vcpu); |
6288 | } | |
6289 | ||
74f16909 BP |
6290 | static void svm_setup_mce(struct kvm_vcpu *vcpu) |
6291 | { | |
6292 | /* [63:9] are reserved. */ | |
6293 | vcpu->arch.mcg_cap &= 0x1ff; | |
6294 | } | |
6295 | ||
72d7b374 LP |
6296 | static int svm_smi_allowed(struct kvm_vcpu *vcpu) |
6297 | { | |
05cade71 LP |
6298 | struct vcpu_svm *svm = to_svm(vcpu); |
6299 | ||
6300 | /* Per APM Vol.2 15.22.2 "Response to SMI" */ | |
6301 | if (!gif_set(svm)) | |
6302 | return 0; | |
6303 | ||
6304 | if (is_guest_mode(&svm->vcpu) && | |
6305 | svm->nested.intercept & (1ULL << INTERCEPT_SMI)) { | |
6306 | /* TODO: Might need to set exit_info_1 and exit_info_2 here */ | |
6307 | svm->vmcb->control.exit_code = SVM_EXIT_SMI; | |
6308 | svm->nested.exit_required = true; | |
6309 | return 0; | |
6310 | } | |
6311 | ||
72d7b374 LP |
6312 | return 1; |
6313 | } | |
6314 | ||
0234bf88 LP |
6315 | static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
6316 | { | |
05cade71 LP |
6317 | struct vcpu_svm *svm = to_svm(vcpu); |
6318 | int ret; | |
6319 | ||
6320 | if (is_guest_mode(vcpu)) { | |
6321 | /* FED8h - SVM Guest */ | |
6322 | put_smstate(u64, smstate, 0x7ed8, 1); | |
6323 | /* FEE0h - SVM Guest VMCB Physical Address */ | |
6324 | put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb); | |
6325 | ||
6326 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; | |
6327 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
6328 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
6329 | ||
6330 | ret = nested_svm_vmexit(svm); | |
6331 | if (ret) | |
6332 | return ret; | |
6333 | } | |
0234bf88 LP |
6334 | return 0; |
6335 | } | |
6336 | ||
ed19321f | 6337 | static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) |
0234bf88 | 6338 | { |
05cade71 LP |
6339 | struct vcpu_svm *svm = to_svm(vcpu); |
6340 | struct vmcb *nested_vmcb; | |
8c5fbf1a | 6341 | struct kvm_host_map map; |
ed19321f SC |
6342 | u64 guest; |
6343 | u64 vmcb; | |
05cade71 | 6344 | |
ed19321f SC |
6345 | guest = GET_SMSTATE(u64, smstate, 0x7ed8); |
6346 | vmcb = GET_SMSTATE(u64, smstate, 0x7ee0); | |
05cade71 | 6347 | |
ed19321f | 6348 | if (guest) { |
8c5fbf1a | 6349 | if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL) |
9ec19493 | 6350 | return 1; |
8c5fbf1a KA |
6351 | nested_vmcb = map.hva; |
6352 | enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map); | |
05cade71 | 6353 | } |
9ec19493 | 6354 | return 0; |
0234bf88 LP |
6355 | } |
6356 | ||
cc3d967f LP |
6357 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
6358 | { | |
6359 | struct vcpu_svm *svm = to_svm(vcpu); | |
6360 | ||
6361 | if (!gif_set(svm)) { | |
6362 | if (vgif_enabled(svm)) | |
6363 | set_intercept(svm, INTERCEPT_STGI); | |
6364 | /* STGI will cause a vm exit */ | |
6365 | return 1; | |
6366 | } | |
6367 | return 0; | |
6368 | } | |
6369 | ||
33af3a7e TL |
6370 | static int sev_flush_asids(void) |
6371 | { | |
6372 | int ret, error; | |
6373 | ||
6374 | /* | |
6375 | * DEACTIVATE will clear the WBINVD indicator causing DF_FLUSH to fail, | |
6376 | * so it must be guarded. | |
6377 | */ | |
6378 | down_write(&sev_deactivate_lock); | |
6379 | ||
6380 | wbinvd_on_all_cpus(); | |
6381 | ret = sev_guest_df_flush(&error); | |
6382 | ||
6383 | up_write(&sev_deactivate_lock); | |
6384 | ||
6385 | if (ret) | |
6386 | pr_err("SEV: DF_FLUSH failed, ret=%d, error=%#x\n", ret, error); | |
6387 | ||
6388 | return ret; | |
6389 | } | |
6390 | ||
6391 | /* Must be called with the sev_bitmap_lock held */ | |
6392 | static bool __sev_recycle_asids(void) | |
6393 | { | |
6394 | int pos; | |
6395 | ||
6396 | /* Check if there are any ASIDs to reclaim before performing a flush */ | |
6397 | pos = find_next_bit(sev_reclaim_asid_bitmap, | |
6398 | max_sev_asid, min_sev_asid - 1); | |
6399 | if (pos >= max_sev_asid) | |
6400 | return false; | |
6401 | ||
6402 | if (sev_flush_asids()) | |
6403 | return false; | |
6404 | ||
6405 | bitmap_xor(sev_asid_bitmap, sev_asid_bitmap, sev_reclaim_asid_bitmap, | |
6406 | max_sev_asid); | |
6407 | bitmap_zero(sev_reclaim_asid_bitmap, max_sev_asid); | |
6408 | ||
6409 | return true; | |
6410 | } | |
6411 | ||
1654efcb BS |
6412 | static int sev_asid_new(void) |
6413 | { | |
33af3a7e | 6414 | bool retry = true; |
1654efcb BS |
6415 | int pos; |
6416 | ||
e3b9a9e1 TL |
6417 | mutex_lock(&sev_bitmap_lock); |
6418 | ||
1654efcb BS |
6419 | /* |
6420 | * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid. | |
6421 | */ | |
33af3a7e | 6422 | again: |
1654efcb | 6423 | pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1); |
e3b9a9e1 | 6424 | if (pos >= max_sev_asid) { |
33af3a7e TL |
6425 | if (retry && __sev_recycle_asids()) { |
6426 | retry = false; | |
6427 | goto again; | |
6428 | } | |
e3b9a9e1 | 6429 | mutex_unlock(&sev_bitmap_lock); |
1654efcb | 6430 | return -EBUSY; |
e3b9a9e1 TL |
6431 | } |
6432 | ||
6433 | __set_bit(pos, sev_asid_bitmap); | |
6434 | ||
6435 | mutex_unlock(&sev_bitmap_lock); | |
1654efcb | 6436 | |
1654efcb BS |
6437 | return pos + 1; |
6438 | } | |
6439 | ||
6440 | static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp) | |
6441 | { | |
81811c16 | 6442 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1654efcb BS |
6443 | int asid, ret; |
6444 | ||
6445 | ret = -EBUSY; | |
3f14a89d DR |
6446 | if (unlikely(sev->active)) |
6447 | return ret; | |
6448 | ||
1654efcb BS |
6449 | asid = sev_asid_new(); |
6450 | if (asid < 0) | |
6451 | return ret; | |
6452 | ||
6453 | ret = sev_platform_init(&argp->error); | |
6454 | if (ret) | |
6455 | goto e_free; | |
6456 | ||
6457 | sev->active = true; | |
6458 | sev->asid = asid; | |
1e80fdc0 | 6459 | INIT_LIST_HEAD(&sev->regions_list); |
1654efcb BS |
6460 | |
6461 | return 0; | |
6462 | ||
6463 | e_free: | |
e3b9a9e1 | 6464 | sev_asid_free(asid); |
1654efcb BS |
6465 | return ret; |
6466 | } | |
6467 | ||
59414c98 BS |
6468 | static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error) |
6469 | { | |
6470 | struct sev_data_activate *data; | |
6471 | int asid = sev_get_asid(kvm); | |
6472 | int ret; | |
6473 | ||
1ec69647 | 6474 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
59414c98 BS |
6475 | if (!data) |
6476 | return -ENOMEM; | |
6477 | ||
6478 | /* activate ASID on the given handle */ | |
6479 | data->handle = handle; | |
6480 | data->asid = asid; | |
6481 | ret = sev_guest_activate(data, error); | |
6482 | kfree(data); | |
6483 | ||
6484 | return ret; | |
6485 | } | |
6486 | ||
89c50580 | 6487 | static int __sev_issue_cmd(int fd, int id, void *data, int *error) |
59414c98 BS |
6488 | { |
6489 | struct fd f; | |
6490 | int ret; | |
6491 | ||
6492 | f = fdget(fd); | |
6493 | if (!f.file) | |
6494 | return -EBADF; | |
6495 | ||
6496 | ret = sev_issue_cmd_external_user(f.file, id, data, error); | |
6497 | ||
6498 | fdput(f); | |
6499 | return ret; | |
6500 | } | |
6501 | ||
89c50580 BS |
6502 | static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error) |
6503 | { | |
81811c16 | 6504 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
89c50580 BS |
6505 | |
6506 | return __sev_issue_cmd(sev->fd, id, data, error); | |
6507 | } | |
6508 | ||
59414c98 BS |
6509 | static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6510 | { | |
81811c16 | 6511 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
59414c98 BS |
6512 | struct sev_data_launch_start *start; |
6513 | struct kvm_sev_launch_start params; | |
6514 | void *dh_blob, *session_blob; | |
6515 | int *error = &argp->error; | |
6516 | int ret; | |
6517 | ||
6518 | if (!sev_guest(kvm)) | |
6519 | return -ENOTTY; | |
6520 | ||
6521 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
6522 | return -EFAULT; | |
6523 | ||
1ec69647 | 6524 | start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT); |
59414c98 BS |
6525 | if (!start) |
6526 | return -ENOMEM; | |
6527 | ||
6528 | dh_blob = NULL; | |
6529 | if (params.dh_uaddr) { | |
6530 | dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len); | |
6531 | if (IS_ERR(dh_blob)) { | |
6532 | ret = PTR_ERR(dh_blob); | |
6533 | goto e_free; | |
6534 | } | |
6535 | ||
6536 | start->dh_cert_address = __sme_set(__pa(dh_blob)); | |
6537 | start->dh_cert_len = params.dh_len; | |
6538 | } | |
6539 | ||
6540 | session_blob = NULL; | |
6541 | if (params.session_uaddr) { | |
6542 | session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len); | |
6543 | if (IS_ERR(session_blob)) { | |
6544 | ret = PTR_ERR(session_blob); | |
6545 | goto e_free_dh; | |
6546 | } | |
6547 | ||
6548 | start->session_address = __sme_set(__pa(session_blob)); | |
6549 | start->session_len = params.session_len; | |
6550 | } | |
6551 | ||
6552 | start->handle = params.handle; | |
6553 | start->policy = params.policy; | |
6554 | ||
6555 | /* create memory encryption context */ | |
89c50580 | 6556 | ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error); |
59414c98 BS |
6557 | if (ret) |
6558 | goto e_free_session; | |
6559 | ||
6560 | /* Bind ASID to this guest */ | |
6561 | ret = sev_bind_asid(kvm, start->handle, error); | |
6562 | if (ret) | |
6563 | goto e_free_session; | |
6564 | ||
6565 | /* return handle to userspace */ | |
6566 | params.handle = start->handle; | |
6567 | if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) { | |
6568 | sev_unbind_asid(kvm, start->handle); | |
6569 | ret = -EFAULT; | |
6570 | goto e_free_session; | |
6571 | } | |
6572 | ||
6573 | sev->handle = start->handle; | |
6574 | sev->fd = argp->sev_fd; | |
6575 | ||
6576 | e_free_session: | |
6577 | kfree(session_blob); | |
6578 | e_free_dh: | |
6579 | kfree(dh_blob); | |
6580 | e_free: | |
6581 | kfree(start); | |
6582 | return ret; | |
6583 | } | |
6584 | ||
ede885ec DR |
6585 | static unsigned long get_num_contig_pages(unsigned long idx, |
6586 | struct page **inpages, unsigned long npages) | |
89c50580 BS |
6587 | { |
6588 | unsigned long paddr, next_paddr; | |
ede885ec | 6589 | unsigned long i = idx + 1, pages = 1; |
89c50580 BS |
6590 | |
6591 | /* find the number of contiguous pages starting from idx */ | |
6592 | paddr = __sme_page_pa(inpages[idx]); | |
6593 | while (i < npages) { | |
6594 | next_paddr = __sme_page_pa(inpages[i++]); | |
6595 | if ((paddr + PAGE_SIZE) == next_paddr) { | |
6596 | pages++; | |
6597 | paddr = next_paddr; | |
6598 | continue; | |
6599 | } | |
6600 | break; | |
6601 | } | |
6602 | ||
6603 | return pages; | |
6604 | } | |
6605 | ||
6606 | static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) | |
6607 | { | |
ede885ec | 6608 | unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i; |
81811c16 | 6609 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
89c50580 BS |
6610 | struct kvm_sev_launch_update_data params; |
6611 | struct sev_data_launch_update_data *data; | |
6612 | struct page **inpages; | |
ede885ec | 6613 | int ret; |
89c50580 BS |
6614 | |
6615 | if (!sev_guest(kvm)) | |
6616 | return -ENOTTY; | |
6617 | ||
6618 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
6619 | return -EFAULT; | |
6620 | ||
1ec69647 | 6621 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
89c50580 BS |
6622 | if (!data) |
6623 | return -ENOMEM; | |
6624 | ||
6625 | vaddr = params.uaddr; | |
6626 | size = params.len; | |
6627 | vaddr_end = vaddr + size; | |
6628 | ||
6629 | /* Lock the user memory. */ | |
6630 | inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1); | |
6631 | if (!inpages) { | |
6632 | ret = -ENOMEM; | |
6633 | goto e_free; | |
6634 | } | |
6635 | ||
6636 | /* | |
6637 | * The LAUNCH_UPDATE command will perform in-place encryption of the | |
6638 | * memory content (i.e it will write the same memory region with C=1). | |
6639 | * It's possible that the cache may contain the data with C=0, i.e., | |
6640 | * unencrypted so invalidate it first. | |
6641 | */ | |
6642 | sev_clflush_pages(inpages, npages); | |
6643 | ||
6644 | for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) { | |
6645 | int offset, len; | |
6646 | ||
6647 | /* | |
6648 | * If the user buffer is not page-aligned, calculate the offset | |
6649 | * within the page. | |
6650 | */ | |
6651 | offset = vaddr & (PAGE_SIZE - 1); | |
6652 | ||
6653 | /* Calculate the number of pages that can be encrypted in one go. */ | |
6654 | pages = get_num_contig_pages(i, inpages, npages); | |
6655 | ||
6656 | len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size); | |
6657 | ||
6658 | data->handle = sev->handle; | |
6659 | data->len = len; | |
6660 | data->address = __sme_page_pa(inpages[i]) + offset; | |
6661 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error); | |
6662 | if (ret) | |
6663 | goto e_unpin; | |
6664 | ||
6665 | size -= len; | |
6666 | next_vaddr = vaddr + len; | |
6667 | } | |
6668 | ||
6669 | e_unpin: | |
6670 | /* content of memory is updated, mark pages dirty */ | |
6671 | for (i = 0; i < npages; i++) { | |
6672 | set_page_dirty_lock(inpages[i]); | |
6673 | mark_page_accessed(inpages[i]); | |
6674 | } | |
6675 | /* unlock the user pages */ | |
6676 | sev_unpin_memory(kvm, inpages, npages); | |
6677 | e_free: | |
6678 | kfree(data); | |
6679 | return ret; | |
6680 | } | |
6681 | ||
0d0736f7 BS |
6682 | static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6683 | { | |
3e233385 | 6684 | void __user *measure = (void __user *)(uintptr_t)argp->data; |
81811c16 | 6685 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
0d0736f7 BS |
6686 | struct sev_data_launch_measure *data; |
6687 | struct kvm_sev_launch_measure params; | |
3e233385 | 6688 | void __user *p = NULL; |
0d0736f7 BS |
6689 | void *blob = NULL; |
6690 | int ret; | |
6691 | ||
6692 | if (!sev_guest(kvm)) | |
6693 | return -ENOTTY; | |
6694 | ||
3e233385 | 6695 | if (copy_from_user(¶ms, measure, sizeof(params))) |
0d0736f7 BS |
6696 | return -EFAULT; |
6697 | ||
1ec69647 | 6698 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
0d0736f7 BS |
6699 | if (!data) |
6700 | return -ENOMEM; | |
6701 | ||
6702 | /* User wants to query the blob length */ | |
6703 | if (!params.len) | |
6704 | goto cmd; | |
6705 | ||
3e233385 BS |
6706 | p = (void __user *)(uintptr_t)params.uaddr; |
6707 | if (p) { | |
0d0736f7 BS |
6708 | if (params.len > SEV_FW_BLOB_MAX_SIZE) { |
6709 | ret = -EINVAL; | |
6710 | goto e_free; | |
6711 | } | |
6712 | ||
0d0736f7 BS |
6713 | ret = -ENOMEM; |
6714 | blob = kmalloc(params.len, GFP_KERNEL); | |
6715 | if (!blob) | |
6716 | goto e_free; | |
6717 | ||
6718 | data->address = __psp_pa(blob); | |
6719 | data->len = params.len; | |
6720 | } | |
6721 | ||
6722 | cmd: | |
6723 | data->handle = sev->handle; | |
6724 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error); | |
6725 | ||
6726 | /* | |
6727 | * If we query the session length, FW responded with expected data. | |
6728 | */ | |
6729 | if (!params.len) | |
6730 | goto done; | |
6731 | ||
6732 | if (ret) | |
6733 | goto e_free_blob; | |
6734 | ||
6735 | if (blob) { | |
3e233385 | 6736 | if (copy_to_user(p, blob, params.len)) |
0d0736f7 BS |
6737 | ret = -EFAULT; |
6738 | } | |
6739 | ||
6740 | done: | |
6741 | params.len = data->len; | |
3e233385 | 6742 | if (copy_to_user(measure, ¶ms, sizeof(params))) |
0d0736f7 BS |
6743 | ret = -EFAULT; |
6744 | e_free_blob: | |
6745 | kfree(blob); | |
6746 | e_free: | |
6747 | kfree(data); | |
6748 | return ret; | |
6749 | } | |
6750 | ||
5bdb0e2f BS |
6751 | static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6752 | { | |
81811c16 | 6753 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
5bdb0e2f BS |
6754 | struct sev_data_launch_finish *data; |
6755 | int ret; | |
6756 | ||
6757 | if (!sev_guest(kvm)) | |
6758 | return -ENOTTY; | |
6759 | ||
1ec69647 | 6760 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
5bdb0e2f BS |
6761 | if (!data) |
6762 | return -ENOMEM; | |
6763 | ||
6764 | data->handle = sev->handle; | |
6765 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error); | |
6766 | ||
6767 | kfree(data); | |
6768 | return ret; | |
6769 | } | |
6770 | ||
255d9e75 BS |
6771 | static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6772 | { | |
81811c16 | 6773 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
255d9e75 BS |
6774 | struct kvm_sev_guest_status params; |
6775 | struct sev_data_guest_status *data; | |
6776 | int ret; | |
6777 | ||
6778 | if (!sev_guest(kvm)) | |
6779 | return -ENOTTY; | |
6780 | ||
1ec69647 | 6781 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
255d9e75 BS |
6782 | if (!data) |
6783 | return -ENOMEM; | |
6784 | ||
6785 | data->handle = sev->handle; | |
6786 | ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error); | |
6787 | if (ret) | |
6788 | goto e_free; | |
6789 | ||
6790 | params.policy = data->policy; | |
6791 | params.state = data->state; | |
6792 | params.handle = data->handle; | |
6793 | ||
6794 | if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) | |
6795 | ret = -EFAULT; | |
6796 | e_free: | |
6797 | kfree(data); | |
6798 | return ret; | |
6799 | } | |
6800 | ||
24f41fb2 BS |
6801 | static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src, |
6802 | unsigned long dst, int size, | |
6803 | int *error, bool enc) | |
6804 | { | |
81811c16 | 6805 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
24f41fb2 BS |
6806 | struct sev_data_dbg *data; |
6807 | int ret; | |
6808 | ||
1ec69647 | 6809 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
24f41fb2 BS |
6810 | if (!data) |
6811 | return -ENOMEM; | |
6812 | ||
6813 | data->handle = sev->handle; | |
6814 | data->dst_addr = dst; | |
6815 | data->src_addr = src; | |
6816 | data->len = size; | |
6817 | ||
6818 | ret = sev_issue_cmd(kvm, | |
6819 | enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT, | |
6820 | data, error); | |
6821 | kfree(data); | |
6822 | return ret; | |
6823 | } | |
6824 | ||
6825 | static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr, | |
6826 | unsigned long dst_paddr, int sz, int *err) | |
6827 | { | |
6828 | int offset; | |
6829 | ||
6830 | /* | |
6831 | * Its safe to read more than we are asked, caller should ensure that | |
6832 | * destination has enough space. | |
6833 | */ | |
6834 | src_paddr = round_down(src_paddr, 16); | |
6835 | offset = src_paddr & 15; | |
6836 | sz = round_up(sz + offset, 16); | |
6837 | ||
6838 | return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false); | |
6839 | } | |
6840 | ||
6841 | static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr, | |
6842 | unsigned long __user dst_uaddr, | |
6843 | unsigned long dst_paddr, | |
6844 | int size, int *err) | |
6845 | { | |
6846 | struct page *tpage = NULL; | |
6847 | int ret, offset; | |
6848 | ||
6849 | /* if inputs are not 16-byte then use intermediate buffer */ | |
6850 | if (!IS_ALIGNED(dst_paddr, 16) || | |
6851 | !IS_ALIGNED(paddr, 16) || | |
6852 | !IS_ALIGNED(size, 16)) { | |
6853 | tpage = (void *)alloc_page(GFP_KERNEL); | |
6854 | if (!tpage) | |
6855 | return -ENOMEM; | |
6856 | ||
6857 | dst_paddr = __sme_page_pa(tpage); | |
6858 | } | |
6859 | ||
6860 | ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err); | |
6861 | if (ret) | |
6862 | goto e_free; | |
6863 | ||
6864 | if (tpage) { | |
6865 | offset = paddr & 15; | |
6866 | if (copy_to_user((void __user *)(uintptr_t)dst_uaddr, | |
6867 | page_address(tpage) + offset, size)) | |
6868 | ret = -EFAULT; | |
6869 | } | |
6870 | ||
6871 | e_free: | |
6872 | if (tpage) | |
6873 | __free_page(tpage); | |
6874 | ||
6875 | return ret; | |
6876 | } | |
6877 | ||
7d1594f5 BS |
6878 | static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr, |
6879 | unsigned long __user vaddr, | |
6880 | unsigned long dst_paddr, | |
6881 | unsigned long __user dst_vaddr, | |
6882 | int size, int *error) | |
6883 | { | |
6884 | struct page *src_tpage = NULL; | |
6885 | struct page *dst_tpage = NULL; | |
6886 | int ret, len = size; | |
6887 | ||
6888 | /* If source buffer is not aligned then use an intermediate buffer */ | |
6889 | if (!IS_ALIGNED(vaddr, 16)) { | |
6890 | src_tpage = alloc_page(GFP_KERNEL); | |
6891 | if (!src_tpage) | |
6892 | return -ENOMEM; | |
6893 | ||
6894 | if (copy_from_user(page_address(src_tpage), | |
6895 | (void __user *)(uintptr_t)vaddr, size)) { | |
6896 | __free_page(src_tpage); | |
6897 | return -EFAULT; | |
6898 | } | |
6899 | ||
6900 | paddr = __sme_page_pa(src_tpage); | |
6901 | } | |
6902 | ||
6903 | /* | |
6904 | * If destination buffer or length is not aligned then do read-modify-write: | |
6905 | * - decrypt destination in an intermediate buffer | |
6906 | * - copy the source buffer in an intermediate buffer | |
6907 | * - use the intermediate buffer as source buffer | |
6908 | */ | |
6909 | if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) { | |
6910 | int dst_offset; | |
6911 | ||
6912 | dst_tpage = alloc_page(GFP_KERNEL); | |
6913 | if (!dst_tpage) { | |
6914 | ret = -ENOMEM; | |
6915 | goto e_free; | |
6916 | } | |
6917 | ||
6918 | ret = __sev_dbg_decrypt(kvm, dst_paddr, | |
6919 | __sme_page_pa(dst_tpage), size, error); | |
6920 | if (ret) | |
6921 | goto e_free; | |
6922 | ||
6923 | /* | |
6924 | * If source is kernel buffer then use memcpy() otherwise | |
6925 | * copy_from_user(). | |
6926 | */ | |
6927 | dst_offset = dst_paddr & 15; | |
6928 | ||
6929 | if (src_tpage) | |
6930 | memcpy(page_address(dst_tpage) + dst_offset, | |
6931 | page_address(src_tpage), size); | |
6932 | else { | |
6933 | if (copy_from_user(page_address(dst_tpage) + dst_offset, | |
6934 | (void __user *)(uintptr_t)vaddr, size)) { | |
6935 | ret = -EFAULT; | |
6936 | goto e_free; | |
6937 | } | |
6938 | } | |
6939 | ||
6940 | paddr = __sme_page_pa(dst_tpage); | |
6941 | dst_paddr = round_down(dst_paddr, 16); | |
6942 | len = round_up(size, 16); | |
6943 | } | |
6944 | ||
6945 | ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true); | |
6946 | ||
6947 | e_free: | |
6948 | if (src_tpage) | |
6949 | __free_page(src_tpage); | |
6950 | if (dst_tpage) | |
6951 | __free_page(dst_tpage); | |
6952 | return ret; | |
6953 | } | |
6954 | ||
24f41fb2 BS |
6955 | static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec) |
6956 | { | |
6957 | unsigned long vaddr, vaddr_end, next_vaddr; | |
0186ec82 | 6958 | unsigned long dst_vaddr; |
24f41fb2 BS |
6959 | struct page **src_p, **dst_p; |
6960 | struct kvm_sev_dbg debug; | |
6961 | unsigned long n; | |
b86bc285 DR |
6962 | unsigned int size; |
6963 | int ret; | |
24f41fb2 BS |
6964 | |
6965 | if (!sev_guest(kvm)) | |
6966 | return -ENOTTY; | |
6967 | ||
6968 | if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug))) | |
6969 | return -EFAULT; | |
6970 | ||
b86bc285 DR |
6971 | if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr) |
6972 | return -EINVAL; | |
6973 | if (!debug.dst_uaddr) | |
6974 | return -EINVAL; | |
6975 | ||
24f41fb2 BS |
6976 | vaddr = debug.src_uaddr; |
6977 | size = debug.len; | |
6978 | vaddr_end = vaddr + size; | |
6979 | dst_vaddr = debug.dst_uaddr; | |
24f41fb2 BS |
6980 | |
6981 | for (; vaddr < vaddr_end; vaddr = next_vaddr) { | |
6982 | int len, s_off, d_off; | |
6983 | ||
6984 | /* lock userspace source and destination page */ | |
6985 | src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0); | |
6986 | if (!src_p) | |
6987 | return -EFAULT; | |
6988 | ||
6989 | dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1); | |
6990 | if (!dst_p) { | |
6991 | sev_unpin_memory(kvm, src_p, n); | |
6992 | return -EFAULT; | |
6993 | } | |
6994 | ||
6995 | /* | |
6996 | * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the | |
6997 | * memory content (i.e it will write the same memory region with C=1). | |
6998 | * It's possible that the cache may contain the data with C=0, i.e., | |
6999 | * unencrypted so invalidate it first. | |
7000 | */ | |
7001 | sev_clflush_pages(src_p, 1); | |
7002 | sev_clflush_pages(dst_p, 1); | |
7003 | ||
7004 | /* | |
7005 | * Since user buffer may not be page aligned, calculate the | |
7006 | * offset within the page. | |
7007 | */ | |
7008 | s_off = vaddr & ~PAGE_MASK; | |
7009 | d_off = dst_vaddr & ~PAGE_MASK; | |
7010 | len = min_t(size_t, (PAGE_SIZE - s_off), size); | |
7011 | ||
7d1594f5 BS |
7012 | if (dec) |
7013 | ret = __sev_dbg_decrypt_user(kvm, | |
7014 | __sme_page_pa(src_p[0]) + s_off, | |
7015 | dst_vaddr, | |
7016 | __sme_page_pa(dst_p[0]) + d_off, | |
7017 | len, &argp->error); | |
7018 | else | |
7019 | ret = __sev_dbg_encrypt_user(kvm, | |
7020 | __sme_page_pa(src_p[0]) + s_off, | |
7021 | vaddr, | |
7022 | __sme_page_pa(dst_p[0]) + d_off, | |
7023 | dst_vaddr, | |
7024 | len, &argp->error); | |
24f41fb2 | 7025 | |
b86bc285 DR |
7026 | sev_unpin_memory(kvm, src_p, n); |
7027 | sev_unpin_memory(kvm, dst_p, n); | |
24f41fb2 BS |
7028 | |
7029 | if (ret) | |
7030 | goto err; | |
7031 | ||
7032 | next_vaddr = vaddr + len; | |
7033 | dst_vaddr = dst_vaddr + len; | |
7034 | size -= len; | |
7035 | } | |
7036 | err: | |
7037 | return ret; | |
7038 | } | |
7039 | ||
9f5b5b95 BS |
7040 | static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp) |
7041 | { | |
81811c16 | 7042 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
9f5b5b95 BS |
7043 | struct sev_data_launch_secret *data; |
7044 | struct kvm_sev_launch_secret params; | |
7045 | struct page **pages; | |
7046 | void *blob, *hdr; | |
7047 | unsigned long n; | |
9c5e0afa | 7048 | int ret, offset; |
9f5b5b95 BS |
7049 | |
7050 | if (!sev_guest(kvm)) | |
7051 | return -ENOTTY; | |
7052 | ||
7053 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
7054 | return -EFAULT; | |
7055 | ||
7056 | pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1); | |
7057 | if (!pages) | |
7058 | return -ENOMEM; | |
7059 | ||
7060 | /* | |
7061 | * The secret must be copied into contiguous memory region, lets verify | |
7062 | * that userspace memory pages are contiguous before we issue command. | |
7063 | */ | |
7064 | if (get_num_contig_pages(0, pages, n) != n) { | |
7065 | ret = -EINVAL; | |
7066 | goto e_unpin_memory; | |
7067 | } | |
7068 | ||
7069 | ret = -ENOMEM; | |
1ec69647 | 7070 | data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); |
9f5b5b95 BS |
7071 | if (!data) |
7072 | goto e_unpin_memory; | |
7073 | ||
9c5e0afa BS |
7074 | offset = params.guest_uaddr & (PAGE_SIZE - 1); |
7075 | data->guest_address = __sme_page_pa(pages[0]) + offset; | |
7076 | data->guest_len = params.guest_len; | |
7077 | ||
9f5b5b95 BS |
7078 | blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len); |
7079 | if (IS_ERR(blob)) { | |
7080 | ret = PTR_ERR(blob); | |
7081 | goto e_free; | |
7082 | } | |
7083 | ||
7084 | data->trans_address = __psp_pa(blob); | |
7085 | data->trans_len = params.trans_len; | |
7086 | ||
7087 | hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len); | |
7088 | if (IS_ERR(hdr)) { | |
7089 | ret = PTR_ERR(hdr); | |
7090 | goto e_free_blob; | |
7091 | } | |
9c5e0afa BS |
7092 | data->hdr_address = __psp_pa(hdr); |
7093 | data->hdr_len = params.hdr_len; | |
9f5b5b95 BS |
7094 | |
7095 | data->handle = sev->handle; | |
7096 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error); | |
7097 | ||
7098 | kfree(hdr); | |
7099 | ||
7100 | e_free_blob: | |
7101 | kfree(blob); | |
7102 | e_free: | |
7103 | kfree(data); | |
7104 | e_unpin_memory: | |
7105 | sev_unpin_memory(kvm, pages, n); | |
7106 | return ret; | |
7107 | } | |
7108 | ||
1654efcb BS |
7109 | static int svm_mem_enc_op(struct kvm *kvm, void __user *argp) |
7110 | { | |
7111 | struct kvm_sev_cmd sev_cmd; | |
7112 | int r; | |
7113 | ||
7114 | if (!svm_sev_enabled()) | |
7115 | return -ENOTTY; | |
7116 | ||
7117 | if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd))) | |
7118 | return -EFAULT; | |
7119 | ||
7120 | mutex_lock(&kvm->lock); | |
7121 | ||
7122 | switch (sev_cmd.id) { | |
7123 | case KVM_SEV_INIT: | |
7124 | r = sev_guest_init(kvm, &sev_cmd); | |
7125 | break; | |
59414c98 BS |
7126 | case KVM_SEV_LAUNCH_START: |
7127 | r = sev_launch_start(kvm, &sev_cmd); | |
7128 | break; | |
89c50580 BS |
7129 | case KVM_SEV_LAUNCH_UPDATE_DATA: |
7130 | r = sev_launch_update_data(kvm, &sev_cmd); | |
7131 | break; | |
0d0736f7 BS |
7132 | case KVM_SEV_LAUNCH_MEASURE: |
7133 | r = sev_launch_measure(kvm, &sev_cmd); | |
7134 | break; | |
5bdb0e2f BS |
7135 | case KVM_SEV_LAUNCH_FINISH: |
7136 | r = sev_launch_finish(kvm, &sev_cmd); | |
7137 | break; | |
255d9e75 BS |
7138 | case KVM_SEV_GUEST_STATUS: |
7139 | r = sev_guest_status(kvm, &sev_cmd); | |
7140 | break; | |
24f41fb2 BS |
7141 | case KVM_SEV_DBG_DECRYPT: |
7142 | r = sev_dbg_crypt(kvm, &sev_cmd, true); | |
7143 | break; | |
7d1594f5 BS |
7144 | case KVM_SEV_DBG_ENCRYPT: |
7145 | r = sev_dbg_crypt(kvm, &sev_cmd, false); | |
7146 | break; | |
9f5b5b95 BS |
7147 | case KVM_SEV_LAUNCH_SECRET: |
7148 | r = sev_launch_secret(kvm, &sev_cmd); | |
7149 | break; | |
1654efcb BS |
7150 | default: |
7151 | r = -EINVAL; | |
7152 | goto out; | |
7153 | } | |
7154 | ||
7155 | if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd))) | |
7156 | r = -EFAULT; | |
7157 | ||
7158 | out: | |
7159 | mutex_unlock(&kvm->lock); | |
7160 | return r; | |
7161 | } | |
7162 | ||
1e80fdc0 BS |
7163 | static int svm_register_enc_region(struct kvm *kvm, |
7164 | struct kvm_enc_region *range) | |
7165 | { | |
81811c16 | 7166 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1e80fdc0 BS |
7167 | struct enc_region *region; |
7168 | int ret = 0; | |
7169 | ||
7170 | if (!sev_guest(kvm)) | |
7171 | return -ENOTTY; | |
7172 | ||
86bf20cb DC |
7173 | if (range->addr > ULONG_MAX || range->size > ULONG_MAX) |
7174 | return -EINVAL; | |
7175 | ||
1ec69647 | 7176 | region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT); |
1e80fdc0 BS |
7177 | if (!region) |
7178 | return -ENOMEM; | |
7179 | ||
7180 | region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1); | |
7181 | if (!region->pages) { | |
7182 | ret = -ENOMEM; | |
7183 | goto e_free; | |
7184 | } | |
7185 | ||
7186 | /* | |
7187 | * The guest may change the memory encryption attribute from C=0 -> C=1 | |
7188 | * or vice versa for this memory range. Lets make sure caches are | |
7189 | * flushed to ensure that guest data gets written into memory with | |
7190 | * correct C-bit. | |
7191 | */ | |
7192 | sev_clflush_pages(region->pages, region->npages); | |
7193 | ||
7194 | region->uaddr = range->addr; | |
7195 | region->size = range->size; | |
7196 | ||
7197 | mutex_lock(&kvm->lock); | |
7198 | list_add_tail(®ion->list, &sev->regions_list); | |
7199 | mutex_unlock(&kvm->lock); | |
7200 | ||
7201 | return ret; | |
7202 | ||
7203 | e_free: | |
7204 | kfree(region); | |
7205 | return ret; | |
7206 | } | |
7207 | ||
7208 | static struct enc_region * | |
7209 | find_enc_region(struct kvm *kvm, struct kvm_enc_region *range) | |
7210 | { | |
81811c16 | 7211 | struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; |
1e80fdc0 BS |
7212 | struct list_head *head = &sev->regions_list; |
7213 | struct enc_region *i; | |
7214 | ||
7215 | list_for_each_entry(i, head, list) { | |
7216 | if (i->uaddr == range->addr && | |
7217 | i->size == range->size) | |
7218 | return i; | |
7219 | } | |
7220 | ||
7221 | return NULL; | |
7222 | } | |
7223 | ||
7224 | ||
7225 | static int svm_unregister_enc_region(struct kvm *kvm, | |
7226 | struct kvm_enc_region *range) | |
7227 | { | |
7228 | struct enc_region *region; | |
7229 | int ret; | |
7230 | ||
7231 | mutex_lock(&kvm->lock); | |
7232 | ||
7233 | if (!sev_guest(kvm)) { | |
7234 | ret = -ENOTTY; | |
7235 | goto failed; | |
7236 | } | |
7237 | ||
7238 | region = find_enc_region(kvm, range); | |
7239 | if (!region) { | |
7240 | ret = -EINVAL; | |
7241 | goto failed; | |
7242 | } | |
7243 | ||
7244 | __unregister_enc_region_locked(kvm, region); | |
7245 | ||
7246 | mutex_unlock(&kvm->lock); | |
7247 | return 0; | |
7248 | ||
7249 | failed: | |
7250 | mutex_unlock(&kvm->lock); | |
7251 | return ret; | |
7252 | } | |
7253 | ||
05d5a486 SB |
7254 | static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) |
7255 | { | |
118154bd LA |
7256 | unsigned long cr4 = kvm_read_cr4(vcpu); |
7257 | bool smep = cr4 & X86_CR4_SMEP; | |
7258 | bool smap = cr4 & X86_CR4_SMAP; | |
7259 | bool is_user = svm_get_cpl(vcpu) == 3; | |
05d5a486 SB |
7260 | |
7261 | /* | |
118154bd LA |
7262 | * Detect and workaround Errata 1096 Fam_17h_00_0Fh. |
7263 | * | |
7264 | * Errata: | |
7265 | * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is | |
7266 | * possible that CPU microcode implementing DecodeAssist will fail | |
7267 | * to read bytes of instruction which caused #NPF. In this case, | |
7268 | * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly | |
7269 | * return 0 instead of the correct guest instruction bytes. | |
7270 | * | |
7271 | * This happens because CPU microcode reading instruction bytes | |
7272 | * uses a special opcode which attempts to read data using CPL=0 | |
7273 | * priviledges. The microcode reads CS:RIP and if it hits a SMAP | |
7274 | * fault, it gives up and returns no instruction bytes. | |
7275 | * | |
7276 | * Detection: | |
7277 | * We reach here in case CPU supports DecodeAssist, raised #NPF and | |
7278 | * returned 0 in GuestIntrBytes field of the VMCB. | |
7279 | * First, errata can only be triggered in case vCPU CR4.SMAP=1. | |
7280 | * Second, if vCPU CR4.SMEP=1, errata could only be triggered | |
7281 | * in case vCPU CPL==3 (Because otherwise guest would have triggered | |
7282 | * a SMEP fault instead of #NPF). | |
7283 | * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL. | |
7284 | * As most guests enable SMAP if they have also enabled SMEP, use above | |
7285 | * logic in order to attempt minimize false-positive of detecting errata | |
7286 | * while still preserving all cases semantic correctness. | |
7287 | * | |
7288 | * Workaround: | |
7289 | * To determine what instruction the guest was executing, the hypervisor | |
7290 | * will have to decode the instruction at the instruction pointer. | |
05d5a486 SB |
7291 | * |
7292 | * In non SEV guest, hypervisor will be able to read the guest | |
7293 | * memory to decode the instruction pointer when insn_len is zero | |
7294 | * so we return true to indicate that decoding is possible. | |
7295 | * | |
7296 | * But in the SEV guest, the guest memory is encrypted with the | |
7297 | * guest specific key and hypervisor will not be able to decode the | |
7298 | * instruction pointer so we will not able to workaround it. Lets | |
7299 | * print the error and request to kill the guest. | |
7300 | */ | |
118154bd | 7301 | if (smap && (!smep || is_user)) { |
05d5a486 SB |
7302 | if (!sev_guest(vcpu->kvm)) |
7303 | return true; | |
7304 | ||
118154bd | 7305 | pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n"); |
05d5a486 SB |
7306 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
7307 | } | |
7308 | ||
7309 | return false; | |
7310 | } | |
7311 | ||
4b9852f4 LA |
7312 | static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu) |
7313 | { | |
7314 | struct vcpu_svm *svm = to_svm(vcpu); | |
7315 | ||
7316 | /* | |
7317 | * TODO: Last condition latch INIT signals on vCPU when | |
7318 | * vCPU is in guest-mode and vmcb12 defines intercept on INIT. | |
7319 | * To properly emulate the INIT intercept, SVM should implement | |
7320 | * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit() | |
7321 | * there if an INIT signal is pending. | |
7322 | */ | |
7323 | return !gif_set(svm) || | |
7324 | (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT)); | |
7325 | } | |
7326 | ||
ef8efd7a SS |
7327 | static bool svm_check_apicv_inhibit_reasons(ulong bit) |
7328 | { | |
f4fdc0a2 | 7329 | ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | |
9a0bf054 SS |
7330 | BIT(APICV_INHIBIT_REASON_HYPERV) | |
7331 | BIT(APICV_INHIBIT_REASON_NESTED); | |
ef8efd7a SS |
7332 | |
7333 | return supported & BIT(bit); | |
7334 | } | |
7335 | ||
2de9d0cc SS |
7336 | static void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate) |
7337 | { | |
7338 | avic_update_access_page(kvm, activate); | |
7339 | } | |
7340 | ||
404f6aac | 7341 | static struct kvm_x86_ops svm_x86_ops __ro_after_init = { |
6aa8b732 AK |
7342 | .cpu_has_kvm_support = has_svm, |
7343 | .disabled_by_bios = is_disabled, | |
7344 | .hardware_setup = svm_hardware_setup, | |
7345 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 7346 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
7347 | .hardware_enable = svm_hardware_enable, |
7348 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 7349 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
bc226f07 | 7350 | .has_emulated_msr = svm_has_emulated_msr, |
6aa8b732 AK |
7351 | |
7352 | .vcpu_create = svm_create_vcpu, | |
7353 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 7354 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 7355 | |
434a1e94 SC |
7356 | .vm_alloc = svm_vm_alloc, |
7357 | .vm_free = svm_vm_free, | |
4e19c36f | 7358 | .vm_init = svm_vm_init, |
1654efcb | 7359 | .vm_destroy = svm_vm_destroy, |
44a95dae | 7360 | |
04d2cc77 | 7361 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
7362 | .vcpu_load = svm_vcpu_load, |
7363 | .vcpu_put = svm_vcpu_put, | |
8221c137 SS |
7364 | .vcpu_blocking = svm_vcpu_blocking, |
7365 | .vcpu_unblocking = svm_vcpu_unblocking, | |
6aa8b732 | 7366 | |
a96036b8 | 7367 | .update_bp_intercept = update_bp_intercept, |
801e459a | 7368 | .get_msr_feature = svm_get_msr_feature, |
6aa8b732 AK |
7369 | .get_msr = svm_get_msr, |
7370 | .set_msr = svm_set_msr, | |
7371 | .get_segment_base = svm_get_segment_base, | |
7372 | .get_segment = svm_get_segment, | |
7373 | .set_segment = svm_set_segment, | |
2e4d2653 | 7374 | .get_cpl = svm_get_cpl, |
1747fb71 | 7375 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 7376 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
25c4c276 | 7377 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 7378 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
7379 | .set_cr3 = svm_set_cr3, |
7380 | .set_cr4 = svm_set_cr4, | |
7381 | .set_efer = svm_set_efer, | |
7382 | .get_idt = svm_get_idt, | |
7383 | .set_idt = svm_set_idt, | |
7384 | .get_gdt = svm_get_gdt, | |
7385 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
7386 | .get_dr6 = svm_get_dr6, |
7387 | .set_dr6 = svm_set_dr6, | |
020df079 | 7388 | .set_dr7 = svm_set_dr7, |
facb0139 | 7389 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 7390 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
7391 | .get_rflags = svm_get_rflags, |
7392 | .set_rflags = svm_set_rflags, | |
be94f6b7 | 7393 | |
6aa8b732 | 7394 | .tlb_flush = svm_flush_tlb, |
faff8758 | 7395 | .tlb_flush_gva = svm_flush_tlb_gva, |
6aa8b732 | 7396 | |
6aa8b732 | 7397 | .run = svm_vcpu_run, |
04d2cc77 | 7398 | .handle_exit = handle_exit, |
6aa8b732 | 7399 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
7400 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
7401 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 7402 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 7403 | .set_irq = svm_set_irq, |
95ba8273 | 7404 | .set_nmi = svm_inject_nmi, |
298101da | 7405 | .queue_exception = svm_queue_exception, |
b463a6f7 | 7406 | .cancel_injection = svm_cancel_injection, |
78646121 | 7407 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 7408 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
7409 | .get_nmi_mask = svm_get_nmi_mask, |
7410 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
7411 | .enable_nmi_window = enable_nmi_window, |
7412 | .enable_irq_window = enable_irq_window, | |
7413 | .update_cr8_intercept = update_cr8_intercept, | |
8d860bbe | 7414 | .set_virtual_apic_mode = svm_set_virtual_apic_mode, |
d62caabb | 7415 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, |
ef8efd7a | 7416 | .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons, |
2de9d0cc | 7417 | .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl, |
c7c9c56c | 7418 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
44a95dae SS |
7419 | .hwapic_irr_update = svm_hwapic_irr_update, |
7420 | .hwapic_isr_update = svm_hwapic_isr_update, | |
fa59cc00 | 7421 | .sync_pir_to_irr = kvm_lapic_find_highest_irr, |
be8ca170 | 7422 | .apicv_post_state_restore = avic_post_state_restore, |
cbc94022 IE |
7423 | |
7424 | .set_tss_addr = svm_set_tss_addr, | |
2ac52ab8 | 7425 | .set_identity_map_addr = svm_set_identity_map_addr, |
67253af5 | 7426 | .get_tdp_level = get_npt_level, |
4b12f0de | 7427 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 7428 | |
586f9607 | 7429 | .get_exit_info = svm_get_exit_info, |
586f9607 | 7430 | |
17cc3935 | 7431 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
7432 | |
7433 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
7434 | |
7435 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 7436 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 7437 | .mpx_supported = svm_mpx_supported, |
55412b2e | 7438 | .xsaves_supported = svm_xsaves_supported, |
66336cab | 7439 | .umip_emulated = svm_umip_emulated, |
86f5201d | 7440 | .pt_supported = svm_pt_supported, |
a47970ed | 7441 | .pku_supported = svm_pku_supported, |
d4330ef2 JR |
7442 | |
7443 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
7444 | |
7445 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 7446 | |
e79f245d | 7447 | .read_l1_tsc_offset = svm_read_l1_tsc_offset, |
326e7425 | 7448 | .write_l1_tsc_offset = svm_write_l1_tsc_offset, |
1c97f0a0 JR |
7449 | |
7450 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
7451 | |
7452 | .check_intercept = svm_check_intercept, | |
95b5a48c | 7453 | .handle_exit_irqoff = svm_handle_exit_irqoff, |
ae97a3b8 | 7454 | |
d264ee0c SC |
7455 | .request_immediate_exit = __kvm_request_immediate_exit, |
7456 | ||
ae97a3b8 | 7457 | .sched_in = svm_sched_in, |
25462f7f WH |
7458 | |
7459 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 7460 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
17e433b5 | 7461 | .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt, |
411b44ba | 7462 | .update_pi_irte = svm_update_pi_irte, |
74f16909 | 7463 | .setup_mce = svm_setup_mce, |
0234bf88 | 7464 | |
72d7b374 | 7465 | .smi_allowed = svm_smi_allowed, |
0234bf88 LP |
7466 | .pre_enter_smm = svm_pre_enter_smm, |
7467 | .pre_leave_smm = svm_pre_leave_smm, | |
cc3d967f | 7468 | .enable_smi_window = enable_smi_window, |
1654efcb BS |
7469 | |
7470 | .mem_enc_op = svm_mem_enc_op, | |
1e80fdc0 BS |
7471 | .mem_enc_reg_region = svm_register_enc_region, |
7472 | .mem_enc_unreg_region = svm_unregister_enc_region, | |
57b119da | 7473 | |
956e255c | 7474 | .nested_enable_evmcs = NULL, |
ea152987 | 7475 | .nested_get_evmcs_version = NULL, |
05d5a486 SB |
7476 | |
7477 | .need_emulation_on_page_fault = svm_need_emulation_on_page_fault, | |
4b9852f4 LA |
7478 | |
7479 | .apic_init_signal_blocked = svm_apic_init_signal_blocked, | |
6aa8b732 AK |
7480 | }; |
7481 | ||
7482 | static int __init svm_init(void) | |
7483 | { | |
cb498ea2 | 7484 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 7485 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
7486 | } |
7487 | ||
7488 | static void __exit svm_exit(void) | |
7489 | { | |
cb498ea2 | 7490 | kvm_exit(); |
6aa8b732 AK |
7491 | } |
7492 | ||
7493 | module_init(svm_init) | |
7494 | module_exit(svm_exit) |