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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/vmalloc.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
6aa8b732 | 27 | |
e495606d | 28 | #include <asm/desc.h> |
6aa8b732 AK |
29 | |
30 | MODULE_AUTHOR("Qumranet"); | |
31 | MODULE_LICENSE("GPL"); | |
32 | ||
33 | #define IOPM_ALLOC_ORDER 2 | |
34 | #define MSRPM_ALLOC_ORDER 1 | |
35 | ||
36 | #define DB_VECTOR 1 | |
37 | #define UD_VECTOR 6 | |
38 | #define GP_VECTOR 13 | |
39 | ||
40 | #define DR7_GD_MASK (1 << 13) | |
41 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
42 | |
43 | #define SEG_TYPE_LDT 2 | |
44 | #define SEG_TYPE_BUSY_TSS16 3 | |
45 | ||
80b7706e JR |
46 | #define SVM_FEATURE_NPT (1 << 0) |
47 | #define SVM_FEATURE_LBRV (1 << 1) | |
48 | #define SVM_DEATURE_SVML (1 << 2) | |
49 | ||
24e09cbf JR |
50 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
51 | ||
709ddebf JR |
52 | /* enable NPT for AMD64 and X86 with PAE */ |
53 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
54 | static bool npt_enabled = true; | |
55 | #else | |
e3da3acd | 56 | static bool npt_enabled = false; |
709ddebf | 57 | #endif |
6c7dac72 JR |
58 | static int npt = 1; |
59 | ||
60 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 61 | |
04d2cc77 AK |
62 | static void kvm_reput_irq(struct vcpu_svm *svm); |
63 | ||
a2fa3e9f GH |
64 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
65 | { | |
fb3f0f51 | 66 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
67 | } |
68 | ||
4866d5e3 | 69 | static unsigned long iopm_base; |
6aa8b732 AK |
70 | |
71 | struct kvm_ldttss_desc { | |
72 | u16 limit0; | |
73 | u16 base0; | |
74 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
75 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
76 | u32 base3; | |
77 | u32 zero1; | |
78 | } __attribute__((packed)); | |
79 | ||
80 | struct svm_cpu_data { | |
81 | int cpu; | |
82 | ||
5008fdf5 AK |
83 | u64 asid_generation; |
84 | u32 max_asid; | |
85 | u32 next_asid; | |
6aa8b732 AK |
86 | struct kvm_ldttss_desc *tss_desc; |
87 | ||
88 | struct page *save_area; | |
89 | }; | |
90 | ||
91 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 92 | static uint32_t svm_features; |
6aa8b732 AK |
93 | |
94 | struct svm_init_data { | |
95 | int cpu; | |
96 | int r; | |
97 | }; | |
98 | ||
99 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
100 | ||
9d8f549d | 101 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
102 | #define MSRS_RANGE_SIZE 2048 |
103 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
104 | ||
105 | #define MAX_INST_SIZE 15 | |
106 | ||
80b7706e JR |
107 | static inline u32 svm_has(u32 feat) |
108 | { | |
109 | return svm_features & feat; | |
110 | } | |
111 | ||
6aa8b732 AK |
112 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
113 | { | |
ad312c7c ZX |
114 | int word_index = __ffs(vcpu->arch.irq_summary); |
115 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
116 | int irq = word_index * BITS_PER_LONG + bit_index; |
117 | ||
ad312c7c ZX |
118 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
119 | if (!vcpu->arch.irq_pending[word_index]) | |
120 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
121 | return irq; |
122 | } | |
123 | ||
124 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
125 | { | |
ad312c7c ZX |
126 | set_bit(irq, vcpu->arch.irq_pending); |
127 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
128 | } |
129 | ||
130 | static inline void clgi(void) | |
131 | { | |
132 | asm volatile (SVM_CLGI); | |
133 | } | |
134 | ||
135 | static inline void stgi(void) | |
136 | { | |
137 | asm volatile (SVM_STGI); | |
138 | } | |
139 | ||
140 | static inline void invlpga(unsigned long addr, u32 asid) | |
141 | { | |
142 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
143 | } | |
144 | ||
145 | static inline unsigned long kvm_read_cr2(void) | |
146 | { | |
147 | unsigned long cr2; | |
148 | ||
149 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
150 | return cr2; | |
151 | } | |
152 | ||
153 | static inline void kvm_write_cr2(unsigned long val) | |
154 | { | |
155 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
156 | } | |
157 | ||
158 | static inline unsigned long read_dr6(void) | |
159 | { | |
160 | unsigned long dr6; | |
161 | ||
162 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
163 | return dr6; | |
164 | } | |
165 | ||
166 | static inline void write_dr6(unsigned long val) | |
167 | { | |
168 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
169 | } | |
170 | ||
171 | static inline unsigned long read_dr7(void) | |
172 | { | |
173 | unsigned long dr7; | |
174 | ||
175 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
176 | return dr7; | |
177 | } | |
178 | ||
179 | static inline void write_dr7(unsigned long val) | |
180 | { | |
181 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
182 | } | |
183 | ||
6aa8b732 AK |
184 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
185 | { | |
a2fa3e9f | 186 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
187 | } |
188 | ||
189 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
190 | { | |
191 | force_new_asid(vcpu); | |
192 | } | |
193 | ||
194 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
195 | { | |
709ddebf | 196 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 197 | efer &= ~EFER_LME; |
6aa8b732 | 198 | |
a2fa3e9f | 199 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
ad312c7c | 200 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
201 | } |
202 | ||
298101da AK |
203 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
204 | bool has_error_code, u32 error_code) | |
205 | { | |
206 | struct vcpu_svm *svm = to_svm(vcpu); | |
207 | ||
208 | svm->vmcb->control.event_inj = nr | |
209 | | SVM_EVTINJ_VALID | |
210 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
211 | | SVM_EVTINJ_TYPE_EXEPT; | |
212 | svm->vmcb->control.event_inj_err = error_code; | |
213 | } | |
214 | ||
215 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
216 | { | |
217 | struct vcpu_svm *svm = to_svm(vcpu); | |
218 | ||
219 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
220 | } | |
221 | ||
6aa8b732 AK |
222 | static int is_external_interrupt(u32 info) |
223 | { | |
224 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
225 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
226 | } | |
227 | ||
228 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
229 | { | |
a2fa3e9f GH |
230 | struct vcpu_svm *svm = to_svm(vcpu); |
231 | ||
232 | if (!svm->next_rip) { | |
b8688d51 | 233 | printk(KERN_DEBUG "%s: NOP\n", __func__); |
6aa8b732 AK |
234 | return; |
235 | } | |
d77c26fc | 236 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 | 237 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
b8688d51 | 238 | __func__, |
a2fa3e9f GH |
239 | svm->vmcb->save.rip, |
240 | svm->next_rip); | |
6aa8b732 | 241 | |
ad312c7c | 242 | vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip; |
a2fa3e9f | 243 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 244 | |
ad312c7c | 245 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
246 | } |
247 | ||
248 | static int has_svm(void) | |
249 | { | |
250 | uint32_t eax, ebx, ecx, edx; | |
251 | ||
1e885461 | 252 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
253 | printk(KERN_INFO "has_svm: not amd\n"); |
254 | return 0; | |
255 | } | |
256 | ||
257 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
258 | if (eax < SVM_CPUID_FUNC) { | |
259 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
260 | return 0; | |
261 | } | |
262 | ||
263 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
264 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
265 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
266 | return 0; | |
267 | } | |
268 | return 1; | |
269 | } | |
270 | ||
271 | static void svm_hardware_disable(void *garbage) | |
272 | { | |
273 | struct svm_cpu_data *svm_data | |
274 | = per_cpu(svm_data, raw_smp_processor_id()); | |
275 | ||
276 | if (svm_data) { | |
277 | uint64_t efer; | |
278 | ||
279 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
280 | rdmsrl(MSR_EFER, efer); | |
281 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 282 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
283 | __free_page(svm_data->save_area); |
284 | kfree(svm_data); | |
285 | } | |
286 | } | |
287 | ||
288 | static void svm_hardware_enable(void *garbage) | |
289 | { | |
290 | ||
291 | struct svm_cpu_data *svm_data; | |
292 | uint64_t efer; | |
6aa8b732 | 293 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
294 | struct desc_struct *gdt; |
295 | int me = raw_smp_processor_id(); | |
296 | ||
297 | if (!has_svm()) { | |
298 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
299 | return; | |
300 | } | |
301 | svm_data = per_cpu(svm_data, me); | |
302 | ||
303 | if (!svm_data) { | |
304 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
305 | me); | |
306 | return; | |
307 | } | |
308 | ||
309 | svm_data->asid_generation = 1; | |
310 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
311 | svm_data->next_asid = svm_data->max_asid + 1; | |
312 | ||
d77c26fc | 313 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
314 | gdt = (struct desc_struct *)gdt_descr.address; |
315 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
316 | ||
317 | rdmsrl(MSR_EFER, efer); | |
318 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
319 | ||
320 | wrmsrl(MSR_VM_HSAVE_PA, | |
321 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
322 | } | |
323 | ||
324 | static int svm_cpu_init(int cpu) | |
325 | { | |
326 | struct svm_cpu_data *svm_data; | |
327 | int r; | |
328 | ||
329 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
330 | if (!svm_data) | |
331 | return -ENOMEM; | |
332 | svm_data->cpu = cpu; | |
333 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
334 | r = -ENOMEM; | |
335 | if (!svm_data->save_area) | |
336 | goto err_1; | |
337 | ||
338 | per_cpu(svm_data, cpu) = svm_data; | |
339 | ||
340 | return 0; | |
341 | ||
342 | err_1: | |
343 | kfree(svm_data); | |
344 | return r; | |
345 | ||
346 | } | |
347 | ||
bfc733a7 RR |
348 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
349 | int read, int write) | |
6aa8b732 AK |
350 | { |
351 | int i; | |
352 | ||
353 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
354 | if (msr >= msrpm_ranges[i] && | |
355 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
356 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
357 | msrpm_ranges[i]) * 2; | |
358 | ||
359 | u32 *base = msrpm + (msr_offset / 32); | |
360 | u32 msr_shift = msr_offset % 32; | |
361 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
362 | *base = (*base & ~(0x3 << msr_shift)) | | |
363 | (mask << msr_shift); | |
bfc733a7 | 364 | return; |
6aa8b732 AK |
365 | } |
366 | } | |
bfc733a7 | 367 | BUG(); |
6aa8b732 AK |
368 | } |
369 | ||
f65c229c JR |
370 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
371 | { | |
372 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
373 | ||
374 | #ifdef CONFIG_X86_64 | |
375 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
376 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
377 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
378 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
379 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
380 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
381 | #endif | |
382 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
383 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
384 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); | |
385 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); | |
386 | } | |
387 | ||
24e09cbf JR |
388 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
389 | { | |
390 | u32 *msrpm = svm->msrpm; | |
391 | ||
392 | svm->vmcb->control.lbr_ctl = 1; | |
393 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
394 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
395 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
396 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
397 | } | |
398 | ||
399 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
400 | { | |
401 | u32 *msrpm = svm->msrpm; | |
402 | ||
403 | svm->vmcb->control.lbr_ctl = 0; | |
404 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
405 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
406 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
407 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
408 | } | |
409 | ||
6aa8b732 AK |
410 | static __init int svm_hardware_setup(void) |
411 | { | |
412 | int cpu; | |
413 | struct page *iopm_pages; | |
f65c229c | 414 | void *iopm_va; |
6aa8b732 AK |
415 | int r; |
416 | ||
6aa8b732 AK |
417 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
418 | ||
419 | if (!iopm_pages) | |
420 | return -ENOMEM; | |
c8681339 AL |
421 | |
422 | iopm_va = page_address(iopm_pages); | |
423 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
424 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
425 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
426 | ||
50a37eb4 JR |
427 | if (boot_cpu_has(X86_FEATURE_NX)) |
428 | kvm_enable_efer_bits(EFER_NX); | |
429 | ||
6aa8b732 AK |
430 | for_each_online_cpu(cpu) { |
431 | r = svm_cpu_init(cpu); | |
432 | if (r) | |
f65c229c | 433 | goto err; |
6aa8b732 | 434 | } |
33bd6a0b JR |
435 | |
436 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
437 | ||
e3da3acd JR |
438 | if (!svm_has(SVM_FEATURE_NPT)) |
439 | npt_enabled = false; | |
440 | ||
6c7dac72 JR |
441 | if (npt_enabled && !npt) { |
442 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
443 | npt_enabled = false; | |
444 | } | |
445 | ||
18552672 | 446 | if (npt_enabled) { |
e3da3acd | 447 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 JR |
448 | kvm_enable_tdp(); |
449 | } | |
e3da3acd | 450 | |
6aa8b732 AK |
451 | return 0; |
452 | ||
f65c229c | 453 | err: |
6aa8b732 AK |
454 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
455 | iopm_base = 0; | |
456 | return r; | |
457 | } | |
458 | ||
459 | static __exit void svm_hardware_unsetup(void) | |
460 | { | |
6aa8b732 | 461 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 462 | iopm_base = 0; |
6aa8b732 AK |
463 | } |
464 | ||
465 | static void init_seg(struct vmcb_seg *seg) | |
466 | { | |
467 | seg->selector = 0; | |
468 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
469 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
470 | seg->limit = 0xffff; | |
471 | seg->base = 0; | |
472 | } | |
473 | ||
474 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
475 | { | |
476 | seg->selector = 0; | |
477 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
478 | seg->limit = 0xffff; | |
479 | seg->base = 0; | |
480 | } | |
481 | ||
e6101a96 | 482 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 483 | { |
e6101a96 JR |
484 | struct vmcb_control_area *control = &svm->vmcb->control; |
485 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
486 | |
487 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
488 | INTERCEPT_CR3_MASK | | |
649d6864 | 489 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
490 | |
491 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
492 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
493 | INTERCEPT_CR4_MASK | |
494 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
495 | |
496 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
497 | INTERCEPT_DR1_MASK | | |
498 | INTERCEPT_DR2_MASK | | |
499 | INTERCEPT_DR3_MASK; | |
500 | ||
501 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
502 | INTERCEPT_DR1_MASK | | |
503 | INTERCEPT_DR2_MASK | | |
504 | INTERCEPT_DR3_MASK | | |
505 | INTERCEPT_DR5_MASK | | |
506 | INTERCEPT_DR7_MASK; | |
507 | ||
7aa81cc0 | 508 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
509 | (1 << UD_VECTOR) | |
510 | (1 << MC_VECTOR); | |
6aa8b732 AK |
511 | |
512 | ||
513 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
514 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 515 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 | 516 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 517 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 518 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
519 | (1ULL << INTERCEPT_INVLPGA) | |
520 | (1ULL << INTERCEPT_IOIO_PROT) | | |
521 | (1ULL << INTERCEPT_MSR_PROT) | | |
522 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 523 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
524 | (1ULL << INTERCEPT_VMRUN) | |
525 | (1ULL << INTERCEPT_VMMCALL) | | |
526 | (1ULL << INTERCEPT_VMLOAD) | | |
527 | (1ULL << INTERCEPT_VMSAVE) | | |
528 | (1ULL << INTERCEPT_STGI) | | |
529 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 530 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 531 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
532 | (1ULL << INTERCEPT_MONITOR) | |
533 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
534 | |
535 | control->iopm_base_pa = iopm_base; | |
f65c229c | 536 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 537 | control->tsc_offset = 0; |
6aa8b732 AK |
538 | control->int_ctl = V_INTR_MASKING_MASK; |
539 | ||
540 | init_seg(&save->es); | |
541 | init_seg(&save->ss); | |
542 | init_seg(&save->ds); | |
543 | init_seg(&save->fs); | |
544 | init_seg(&save->gs); | |
545 | ||
546 | save->cs.selector = 0xf000; | |
547 | /* Executable/Readable Code Segment */ | |
548 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
549 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
550 | save->cs.limit = 0xffff; | |
d92899a0 AK |
551 | /* |
552 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
553 | * be consistent with it. | |
554 | * | |
555 | * Replace when we have real mode working for vmx. | |
556 | */ | |
557 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
558 | |
559 | save->gdtr.limit = 0xffff; | |
560 | save->idtr.limit = 0xffff; | |
561 | ||
562 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
563 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
564 | ||
565 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 566 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
567 | save->dr7 = 0x400; |
568 | save->rflags = 2; | |
569 | save->rip = 0x0000fff0; | |
570 | ||
571 | /* | |
572 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
573 | * cache by default. the orderly way is to enable cache in bios. | |
574 | */ | |
707d92fa | 575 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 576 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 577 | /* rdx = ?? */ |
709ddebf JR |
578 | |
579 | if (npt_enabled) { | |
580 | /* Setup VMCB for Nested Paging */ | |
581 | control->nested_ctl = 1; | |
3564990a | 582 | control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH); |
709ddebf JR |
583 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
584 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
585 | INTERCEPT_CR3_MASK); | |
586 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
587 | INTERCEPT_CR3_MASK); | |
588 | save->g_pat = 0x0007040600070406ULL; | |
589 | /* enable caching because the QEMU Bios doesn't enable it */ | |
590 | save->cr0 = X86_CR0_ET; | |
591 | save->cr3 = 0; | |
592 | save->cr4 = 0; | |
593 | } | |
a79d2f18 | 594 | force_new_asid(&svm->vcpu); |
6aa8b732 AK |
595 | } |
596 | ||
e00c8cf2 | 597 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
598 | { |
599 | struct vcpu_svm *svm = to_svm(vcpu); | |
600 | ||
e6101a96 | 601 | init_vmcb(svm); |
70433389 AK |
602 | |
603 | if (vcpu->vcpu_id != 0) { | |
604 | svm->vmcb->save.rip = 0; | |
ad312c7c ZX |
605 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
606 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 607 | } |
e00c8cf2 AK |
608 | |
609 | return 0; | |
04d2cc77 AK |
610 | } |
611 | ||
fb3f0f51 | 612 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 613 | { |
a2fa3e9f | 614 | struct vcpu_svm *svm; |
6aa8b732 | 615 | struct page *page; |
f65c229c | 616 | struct page *msrpm_pages; |
fb3f0f51 | 617 | int err; |
6aa8b732 | 618 | |
c16f862d | 619 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
620 | if (!svm) { |
621 | err = -ENOMEM; | |
622 | goto out; | |
623 | } | |
624 | ||
625 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
626 | if (err) | |
627 | goto free_svm; | |
628 | ||
6aa8b732 | 629 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
630 | if (!page) { |
631 | err = -ENOMEM; | |
632 | goto uninit; | |
633 | } | |
6aa8b732 | 634 | |
f65c229c JR |
635 | err = -ENOMEM; |
636 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
637 | if (!msrpm_pages) | |
638 | goto uninit; | |
639 | svm->msrpm = page_address(msrpm_pages); | |
640 | svm_vcpu_init_msrpm(svm->msrpm); | |
641 | ||
a2fa3e9f GH |
642 | svm->vmcb = page_address(page); |
643 | clear_page(svm->vmcb); | |
644 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
645 | svm->asid_generation = 0; | |
646 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
e6101a96 | 647 | init_vmcb(svm); |
a2fa3e9f | 648 | |
fb3f0f51 RR |
649 | fx_init(&svm->vcpu); |
650 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 651 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 652 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 653 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 654 | |
fb3f0f51 | 655 | return &svm->vcpu; |
36241b8c | 656 | |
fb3f0f51 RR |
657 | uninit: |
658 | kvm_vcpu_uninit(&svm->vcpu); | |
659 | free_svm: | |
a4770347 | 660 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
661 | out: |
662 | return ERR_PTR(err); | |
6aa8b732 AK |
663 | } |
664 | ||
665 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
666 | { | |
a2fa3e9f GH |
667 | struct vcpu_svm *svm = to_svm(vcpu); |
668 | ||
fb3f0f51 | 669 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 670 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
fb3f0f51 | 671 | kvm_vcpu_uninit(vcpu); |
a4770347 | 672 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
673 | } |
674 | ||
15ad7146 | 675 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 676 | { |
a2fa3e9f | 677 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 678 | int i; |
0cc5064d | 679 | |
0cc5064d AK |
680 | if (unlikely(cpu != vcpu->cpu)) { |
681 | u64 tsc_this, delta; | |
682 | ||
683 | /* | |
684 | * Make sure that the guest sees a monotonically | |
685 | * increasing TSC. | |
686 | */ | |
687 | rdtscll(tsc_this); | |
ad312c7c | 688 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 689 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 690 | vcpu->cpu = cpu; |
a3d7f85f | 691 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 692 | } |
94dfbdb3 AL |
693 | |
694 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 695 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
696 | } |
697 | ||
698 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
699 | { | |
a2fa3e9f | 700 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
701 | int i; |
702 | ||
e1beb1d3 | 703 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 704 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 705 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 706 | |
ad312c7c | 707 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
708 | } |
709 | ||
774c47f1 AK |
710 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
711 | { | |
712 | } | |
713 | ||
6aa8b732 AK |
714 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
715 | { | |
a2fa3e9f GH |
716 | struct vcpu_svm *svm = to_svm(vcpu); |
717 | ||
ad312c7c ZX |
718 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
719 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
720 | vcpu->arch.rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
721 | } |
722 | ||
723 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
724 | { | |
a2fa3e9f | 725 | struct vcpu_svm *svm = to_svm(vcpu); |
ad312c7c ZX |
726 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
727 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
728 | svm->vmcb->save.rip = vcpu->arch.rip; | |
6aa8b732 AK |
729 | } |
730 | ||
731 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
732 | { | |
a2fa3e9f | 733 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
734 | } |
735 | ||
736 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
737 | { | |
a2fa3e9f | 738 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
739 | } |
740 | ||
741 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
742 | { | |
a2fa3e9f | 743 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
744 | |
745 | switch (seg) { | |
746 | case VCPU_SREG_CS: return &save->cs; | |
747 | case VCPU_SREG_DS: return &save->ds; | |
748 | case VCPU_SREG_ES: return &save->es; | |
749 | case VCPU_SREG_FS: return &save->fs; | |
750 | case VCPU_SREG_GS: return &save->gs; | |
751 | case VCPU_SREG_SS: return &save->ss; | |
752 | case VCPU_SREG_TR: return &save->tr; | |
753 | case VCPU_SREG_LDTR: return &save->ldtr; | |
754 | } | |
755 | BUG(); | |
8b6d44c7 | 756 | return NULL; |
6aa8b732 AK |
757 | } |
758 | ||
759 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
760 | { | |
761 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
762 | ||
763 | return s->base; | |
764 | } | |
765 | ||
766 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
767 | struct kvm_segment *var, int seg) | |
768 | { | |
769 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
770 | ||
771 | var->base = s->base; | |
772 | var->limit = s->limit; | |
773 | var->selector = s->selector; | |
774 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
775 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
776 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
777 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
778 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
779 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
780 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
781 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
782 | var->unusable = !var->present; | |
783 | } | |
784 | ||
2e4d2653 IE |
785 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
786 | { | |
787 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
788 | ||
789 | return save->cpl; | |
790 | } | |
791 | ||
6aa8b732 AK |
792 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
793 | { | |
a2fa3e9f GH |
794 | struct vcpu_svm *svm = to_svm(vcpu); |
795 | ||
796 | dt->limit = svm->vmcb->save.idtr.limit; | |
797 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
798 | } |
799 | ||
800 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
801 | { | |
a2fa3e9f GH |
802 | struct vcpu_svm *svm = to_svm(vcpu); |
803 | ||
804 | svm->vmcb->save.idtr.limit = dt->limit; | |
805 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
806 | } |
807 | ||
808 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
809 | { | |
a2fa3e9f GH |
810 | struct vcpu_svm *svm = to_svm(vcpu); |
811 | ||
812 | dt->limit = svm->vmcb->save.gdtr.limit; | |
813 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
814 | } |
815 | ||
816 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
817 | { | |
a2fa3e9f GH |
818 | struct vcpu_svm *svm = to_svm(vcpu); |
819 | ||
820 | svm->vmcb->save.gdtr.limit = dt->limit; | |
821 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
822 | } |
823 | ||
25c4c276 | 824 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
825 | { |
826 | } | |
827 | ||
6aa8b732 AK |
828 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
829 | { | |
a2fa3e9f GH |
830 | struct vcpu_svm *svm = to_svm(vcpu); |
831 | ||
05b3e0c2 | 832 | #ifdef CONFIG_X86_64 |
ad312c7c | 833 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 834 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 835 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 836 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
837 | } |
838 | ||
d77c26fc | 839 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 840 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 841 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
842 | } |
843 | } | |
844 | #endif | |
709ddebf JR |
845 | if (npt_enabled) |
846 | goto set; | |
847 | ||
ad312c7c | 848 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 849 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
850 | vcpu->fpu_active = 1; |
851 | } | |
852 | ||
ad312c7c | 853 | vcpu->arch.cr0 = cr0; |
707d92fa | 854 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
855 | if (!vcpu->fpu_active) { |
856 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 857 | cr0 |= X86_CR0_TS; |
6b390b63 | 858 | } |
709ddebf JR |
859 | set: |
860 | /* | |
861 | * re-enable caching here because the QEMU bios | |
862 | * does not do it - this results in some delay at | |
863 | * reboot | |
864 | */ | |
865 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 866 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
867 | } |
868 | ||
869 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
870 | { | |
6394b649 JR |
871 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
872 | ||
ec077263 JR |
873 | vcpu->arch.cr4 = cr4; |
874 | if (!npt_enabled) | |
875 | cr4 |= X86_CR4_PAE; | |
6394b649 | 876 | cr4 |= host_cr4_mce; |
ec077263 | 877 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
878 | } |
879 | ||
880 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
881 | struct kvm_segment *var, int seg) | |
882 | { | |
a2fa3e9f | 883 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
884 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
885 | ||
886 | s->base = var->base; | |
887 | s->limit = var->limit; | |
888 | s->selector = var->selector; | |
889 | if (var->unusable) | |
890 | s->attrib = 0; | |
891 | else { | |
892 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
893 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
894 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
895 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
896 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
897 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
898 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
899 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
900 | } | |
901 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
902 | svm->vmcb->save.cpl |
903 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
904 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
905 | ||
906 | } | |
907 | ||
6aa8b732 AK |
908 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) |
909 | { | |
910 | return -EOPNOTSUPP; | |
911 | } | |
912 | ||
2a8067f1 ED |
913 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
914 | { | |
915 | struct vcpu_svm *svm = to_svm(vcpu); | |
916 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
917 | ||
918 | if (is_external_interrupt(exit_int_info)) | |
919 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
920 | return -1; | |
921 | } | |
922 | ||
6aa8b732 AK |
923 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
924 | { | |
94dfbdb3 | 925 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 926 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 927 | #endif |
6aa8b732 AK |
928 | } |
929 | ||
930 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
931 | { | |
94dfbdb3 | 932 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 933 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 934 | #endif |
6aa8b732 AK |
935 | } |
936 | ||
e756fc62 | 937 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
938 | { |
939 | if (svm_data->next_asid > svm_data->max_asid) { | |
940 | ++svm_data->asid_generation; | |
941 | svm_data->next_asid = 1; | |
a2fa3e9f | 942 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
943 | } |
944 | ||
e756fc62 | 945 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
946 | svm->asid_generation = svm_data->asid_generation; |
947 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
948 | } |
949 | ||
6aa8b732 AK |
950 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
951 | { | |
a2fa3e9f | 952 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
953 | } |
954 | ||
955 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
956 | int *exception) | |
957 | { | |
a2fa3e9f GH |
958 | struct vcpu_svm *svm = to_svm(vcpu); |
959 | ||
6aa8b732 AK |
960 | *exception = 0; |
961 | ||
a2fa3e9f GH |
962 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
963 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
964 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
965 | *exception = DB_VECTOR; |
966 | return; | |
967 | } | |
968 | ||
969 | switch (dr) { | |
970 | case 0 ... 3: | |
a2fa3e9f | 971 | svm->db_regs[dr] = value; |
6aa8b732 AK |
972 | return; |
973 | case 4 ... 5: | |
ad312c7c | 974 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
975 | *exception = UD_VECTOR; |
976 | return; | |
977 | } | |
978 | case 7: { | |
979 | if (value & ~((1ULL << 32) - 1)) { | |
980 | *exception = GP_VECTOR; | |
981 | return; | |
982 | } | |
a2fa3e9f | 983 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
984 | return; |
985 | } | |
986 | default: | |
987 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
b8688d51 | 988 | __func__, dr); |
6aa8b732 AK |
989 | *exception = UD_VECTOR; |
990 | return; | |
991 | } | |
992 | } | |
993 | ||
e756fc62 | 994 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 995 | { |
a2fa3e9f | 996 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 997 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
998 | u64 fault_address; |
999 | u32 error_code; | |
6aa8b732 | 1000 | |
85f455f7 ED |
1001 | if (!irqchip_in_kernel(kvm) && |
1002 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 1003 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 1004 | |
a2fa3e9f GH |
1005 | fault_address = svm->vmcb->control.exit_info_2; |
1006 | error_code = svm->vmcb->control.exit_info_1; | |
3067714c | 1007 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1008 | } |
1009 | ||
7aa81cc0 AL |
1010 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1011 | { | |
1012 | int er; | |
1013 | ||
571008da | 1014 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1015 | if (er != EMULATE_DONE) |
7ee5d940 | 1016 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1017 | return 1; |
1018 | } | |
1019 | ||
e756fc62 | 1020 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 1021 | { |
a2fa3e9f | 1022 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1023 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1024 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1025 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1026 | |
1027 | return 1; | |
7807fa6c AL |
1028 | } |
1029 | ||
53371b50 JR |
1030 | static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1031 | { | |
1032 | /* | |
1033 | * On an #MC intercept the MCE handler is not called automatically in | |
1034 | * the host. So do it by hand here. | |
1035 | */ | |
1036 | asm volatile ( | |
1037 | "int $0x12\n"); | |
1038 | /* not sure if we ever come back to this point */ | |
1039 | ||
1040 | return 1; | |
1041 | } | |
1042 | ||
e756fc62 | 1043 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
1044 | { |
1045 | /* | |
1046 | * VMCB is undefined after a SHUTDOWN intercept | |
1047 | * so reinitialize it. | |
1048 | */ | |
a2fa3e9f | 1049 | clear_page(svm->vmcb); |
e6101a96 | 1050 | init_vmcb(svm); |
46fe4ddd JR |
1051 | |
1052 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1053 | return 0; | |
1054 | } | |
1055 | ||
e756fc62 | 1056 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1057 | { |
d77c26fc | 1058 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1059 | int size, down, in, string, rep; |
1060 | unsigned port; | |
6aa8b732 | 1061 | |
e756fc62 | 1062 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1063 | |
a2fa3e9f | 1064 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1065 | |
e70669ab LV |
1066 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1067 | ||
1068 | if (string) { | |
3427318f LV |
1069 | if (emulate_instruction(&svm->vcpu, |
1070 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1071 | return 0; |
1072 | return 1; | |
1073 | } | |
1074 | ||
039576c0 AK |
1075 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1076 | port = io_info >> 16; | |
1077 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1078 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1079 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1080 | |
3090dd73 | 1081 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1082 | } |
1083 | ||
e756fc62 | 1084 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1085 | { |
1086 | return 1; | |
1087 | } | |
1088 | ||
e756fc62 | 1089 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1090 | { |
a2fa3e9f | 1091 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1092 | skip_emulated_instruction(&svm->vcpu); |
1093 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1094 | } |
1095 | ||
e756fc62 | 1096 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1097 | { |
a2fa3e9f | 1098 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1099 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1100 | kvm_emulate_hypercall(&svm->vcpu); |
1101 | return 1; | |
02e235bc AK |
1102 | } |
1103 | ||
e756fc62 RR |
1104 | static int invalid_op_interception(struct vcpu_svm *svm, |
1105 | struct kvm_run *kvm_run) | |
6aa8b732 | 1106 | { |
7ee5d940 | 1107 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1108 | return 1; |
1109 | } | |
1110 | ||
e756fc62 RR |
1111 | static int task_switch_interception(struct vcpu_svm *svm, |
1112 | struct kvm_run *kvm_run) | |
6aa8b732 | 1113 | { |
37817f29 IE |
1114 | u16 tss_selector; |
1115 | ||
1116 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
1117 | if (svm->vmcb->control.exit_info_2 & | |
1118 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
1119 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1120 | TASK_SWITCH_IRET); | |
1121 | if (svm->vmcb->control.exit_info_2 & | |
1122 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
1123 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1124 | TASK_SWITCH_JMP); | |
1125 | return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL); | |
6aa8b732 AK |
1126 | } |
1127 | ||
e756fc62 | 1128 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1129 | { |
a2fa3e9f | 1130 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1131 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1132 | return 1; |
6aa8b732 AK |
1133 | } |
1134 | ||
e756fc62 RR |
1135 | static int emulate_on_interception(struct vcpu_svm *svm, |
1136 | struct kvm_run *kvm_run) | |
6aa8b732 | 1137 | { |
3427318f | 1138 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 1139 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
1140 | return 1; |
1141 | } | |
1142 | ||
1d075434 JR |
1143 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1144 | { | |
1145 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1146 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1147 | return 1; | |
1148 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1149 | return 0; | |
1150 | } | |
1151 | ||
6aa8b732 AK |
1152 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1153 | { | |
a2fa3e9f GH |
1154 | struct vcpu_svm *svm = to_svm(vcpu); |
1155 | ||
6aa8b732 | 1156 | switch (ecx) { |
6aa8b732 AK |
1157 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1158 | u64 tsc; | |
1159 | ||
1160 | rdtscll(tsc); | |
a2fa3e9f | 1161 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1162 | break; |
1163 | } | |
0e859cac | 1164 | case MSR_K6_STAR: |
a2fa3e9f | 1165 | *data = svm->vmcb->save.star; |
6aa8b732 | 1166 | break; |
0e859cac | 1167 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1168 | case MSR_LSTAR: |
a2fa3e9f | 1169 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1170 | break; |
1171 | case MSR_CSTAR: | |
a2fa3e9f | 1172 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1173 | break; |
1174 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1175 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1176 | break; |
1177 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1178 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1179 | break; |
1180 | #endif | |
1181 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1182 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1183 | break; |
1184 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1185 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1186 | break; |
1187 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1188 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1189 | break; |
a2938c80 JR |
1190 | /* Nobody will change the following 5 values in the VMCB so |
1191 | we can safely return them on rdmsr. They will always be 0 | |
1192 | until LBRV is implemented. */ | |
1193 | case MSR_IA32_DEBUGCTLMSR: | |
1194 | *data = svm->vmcb->save.dbgctl; | |
1195 | break; | |
1196 | case MSR_IA32_LASTBRANCHFROMIP: | |
1197 | *data = svm->vmcb->save.br_from; | |
1198 | break; | |
1199 | case MSR_IA32_LASTBRANCHTOIP: | |
1200 | *data = svm->vmcb->save.br_to; | |
1201 | break; | |
1202 | case MSR_IA32_LASTINTFROMIP: | |
1203 | *data = svm->vmcb->save.last_excp_from; | |
1204 | break; | |
1205 | case MSR_IA32_LASTINTTOIP: | |
1206 | *data = svm->vmcb->save.last_excp_to; | |
1207 | break; | |
6aa8b732 | 1208 | default: |
3bab1f5d | 1209 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1210 | } |
1211 | return 0; | |
1212 | } | |
1213 | ||
e756fc62 | 1214 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1215 | { |
ad312c7c | 1216 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1217 | u64 data; |
1218 | ||
e756fc62 | 1219 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1220 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1221 | else { |
a2fa3e9f | 1222 | svm->vmcb->save.rax = data & 0xffffffff; |
ad312c7c | 1223 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1224 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1225 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1226 | } |
1227 | return 1; | |
1228 | } | |
1229 | ||
1230 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1231 | { | |
a2fa3e9f GH |
1232 | struct vcpu_svm *svm = to_svm(vcpu); |
1233 | ||
6aa8b732 | 1234 | switch (ecx) { |
6aa8b732 AK |
1235 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1236 | u64 tsc; | |
1237 | ||
1238 | rdtscll(tsc); | |
a2fa3e9f | 1239 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1240 | break; |
1241 | } | |
0e859cac | 1242 | case MSR_K6_STAR: |
a2fa3e9f | 1243 | svm->vmcb->save.star = data; |
6aa8b732 | 1244 | break; |
49b14f24 | 1245 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1246 | case MSR_LSTAR: |
a2fa3e9f | 1247 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1248 | break; |
1249 | case MSR_CSTAR: | |
a2fa3e9f | 1250 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1251 | break; |
1252 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1253 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1254 | break; |
1255 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1256 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1257 | break; |
1258 | #endif | |
1259 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1260 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1261 | break; |
1262 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1263 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1264 | break; |
1265 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1266 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1267 | break; |
a2938c80 | 1268 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
1269 | if (!svm_has(SVM_FEATURE_LBRV)) { |
1270 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 1271 | __func__, data); |
24e09cbf JR |
1272 | break; |
1273 | } | |
1274 | if (data & DEBUGCTL_RESERVED_BITS) | |
1275 | return 1; | |
1276 | ||
1277 | svm->vmcb->save.dbgctl = data; | |
1278 | if (data & (1ULL<<0)) | |
1279 | svm_enable_lbrv(svm); | |
1280 | else | |
1281 | svm_disable_lbrv(svm); | |
a2938c80 | 1282 | break; |
62b9abaa JR |
1283 | case MSR_K7_EVNTSEL0: |
1284 | case MSR_K7_EVNTSEL1: | |
1285 | case MSR_K7_EVNTSEL2: | |
1286 | case MSR_K7_EVNTSEL3: | |
1287 | /* | |
1288 | * only support writing 0 to the performance counters for now | |
1289 | * to make Windows happy. Should be replaced by a real | |
1290 | * performance counter emulation later. | |
1291 | */ | |
1292 | if (data != 0) | |
1293 | goto unhandled; | |
1294 | break; | |
6aa8b732 | 1295 | default: |
62b9abaa | 1296 | unhandled: |
3bab1f5d | 1297 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1298 | } |
1299 | return 0; | |
1300 | } | |
1301 | ||
e756fc62 | 1302 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1303 | { |
ad312c7c | 1304 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1305 | u64 data = (svm->vmcb->save.rax & -1u) |
ad312c7c | 1306 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1307 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1308 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1309 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1310 | else |
e756fc62 | 1311 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1312 | return 1; |
1313 | } | |
1314 | ||
e756fc62 | 1315 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1316 | { |
e756fc62 RR |
1317 | if (svm->vmcb->control.exit_info_1) |
1318 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1319 | else |
e756fc62 | 1320 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1321 | } |
1322 | ||
e756fc62 | 1323 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1324 | struct kvm_run *kvm_run) |
1325 | { | |
85f455f7 ED |
1326 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1327 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1328 | /* |
1329 | * If the user space waits to inject interrupts, exit as soon as | |
1330 | * possible | |
1331 | */ | |
1332 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1333 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1334 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1335 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1336 | return 0; | |
1337 | } | |
1338 | ||
1339 | return 1; | |
1340 | } | |
1341 | ||
e756fc62 | 1342 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1343 | struct kvm_run *kvm_run) = { |
1344 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1345 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1346 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1347 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1348 | /* for now: */ |
1349 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1350 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1351 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1352 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1353 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1354 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1355 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1356 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1357 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1358 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1359 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1360 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1361 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1362 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1363 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1364 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1365 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 1366 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
6aa8b732 AK |
1367 | [SVM_EXIT_INTR] = nop_on_interception, |
1368 | [SVM_EXIT_NMI] = nop_on_interception, | |
1369 | [SVM_EXIT_SMI] = nop_on_interception, | |
1370 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1371 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1372 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1373 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1374 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1375 | [SVM_EXIT_HLT] = halt_interception, |
1376 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1377 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1378 | [SVM_EXIT_IOIO] = io_interception, | |
1379 | [SVM_EXIT_MSR] = msr_interception, | |
1380 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1381 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1382 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1383 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1384 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1385 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1386 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1387 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1388 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1389 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1390 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1391 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 1392 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
1393 | }; |
1394 | ||
04d2cc77 | 1395 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1396 | { |
04d2cc77 | 1397 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1398 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1399 | |
709ddebf JR |
1400 | if (npt_enabled) { |
1401 | int mmu_reload = 0; | |
1402 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
1403 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
1404 | mmu_reload = 1; | |
1405 | } | |
1406 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
1407 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
1408 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1409 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1410 | kvm_inject_gp(vcpu, 0); | |
1411 | return 1; | |
1412 | } | |
1413 | } | |
1414 | if (mmu_reload) { | |
1415 | kvm_mmu_reset_context(vcpu); | |
1416 | kvm_mmu_load(vcpu); | |
1417 | } | |
1418 | } | |
1419 | ||
04d2cc77 AK |
1420 | kvm_reput_irq(svm); |
1421 | ||
1422 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1423 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1424 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1425 | = svm->vmcb->control.exit_code; | |
1426 | return 0; | |
1427 | } | |
1428 | ||
a2fa3e9f | 1429 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf JR |
1430 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
1431 | exit_code != SVM_EXIT_NPF) | |
6aa8b732 AK |
1432 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
1433 | "exit_code 0x%x\n", | |
b8688d51 | 1434 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1435 | exit_code); |
1436 | ||
9d8f549d | 1437 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1438 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1439 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1440 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1441 | return 0; |
1442 | } | |
1443 | ||
e756fc62 | 1444 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1445 | } |
1446 | ||
1447 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1448 | { | |
1449 | int cpu = raw_smp_processor_id(); | |
1450 | ||
1451 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1452 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1453 | load_TR_desc(); |
1454 | } | |
1455 | ||
e756fc62 | 1456 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1457 | { |
1458 | int cpu = raw_smp_processor_id(); | |
1459 | ||
1460 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1461 | ||
a2fa3e9f | 1462 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1463 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1464 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1465 | new_asid(svm, svm_data); |
6aa8b732 AK |
1466 | } |
1467 | ||
1468 | ||
85f455f7 | 1469 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1470 | { |
1471 | struct vmcb_control_area *control; | |
1472 | ||
e756fc62 | 1473 | control = &svm->vmcb->control; |
85f455f7 | 1474 | control->int_vector = irq; |
6aa8b732 AK |
1475 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1476 | control->int_ctl |= V_IRQ_MASK | | |
1477 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1478 | } | |
1479 | ||
2a8067f1 ED |
1480 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1481 | { | |
1482 | struct vcpu_svm *svm = to_svm(vcpu); | |
1483 | ||
1484 | svm_inject_irq(svm, irq); | |
1485 | } | |
1486 | ||
aaacfc9a JR |
1487 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
1488 | { | |
1489 | struct vcpu_svm *svm = to_svm(vcpu); | |
1490 | struct vmcb *vmcb = svm->vmcb; | |
1491 | int max_irr, tpr; | |
1492 | ||
1493 | if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr) | |
1494 | return; | |
1495 | ||
1496 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1497 | ||
1498 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
1499 | if (max_irr == -1) | |
1500 | return; | |
1501 | ||
1502 | tpr = kvm_lapic_get_cr8(vcpu) << 4; | |
1503 | ||
1504 | if (tpr >= (max_irr & 0xf0)) | |
1505 | vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
1506 | } | |
1507 | ||
04d2cc77 | 1508 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1509 | { |
04d2cc77 | 1510 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1511 | struct vmcb *vmcb = svm->vmcb; |
1512 | int intr_vector = -1; | |
1513 | ||
1514 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1515 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1516 | intr_vector = vmcb->control.exit_int_info & | |
1517 | SVM_EVTINJ_VEC_MASK; | |
1518 | vmcb->control.exit_int_info = 0; | |
1519 | svm_inject_irq(svm, intr_vector); | |
aaacfc9a | 1520 | goto out; |
85f455f7 ED |
1521 | } |
1522 | ||
1523 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
aaacfc9a | 1524 | goto out; |
85f455f7 | 1525 | |
1b9778da | 1526 | if (!kvm_cpu_has_interrupt(vcpu)) |
aaacfc9a | 1527 | goto out; |
85f455f7 ED |
1528 | |
1529 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1530 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1531 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1532 | /* unable to deliver irq, set pending irq */ | |
1533 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1534 | svm_inject_irq(svm, 0x0); | |
aaacfc9a | 1535 | goto out; |
85f455f7 ED |
1536 | } |
1537 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1538 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1539 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1540 | kvm_timer_intr_post(vcpu, intr_vector); |
aaacfc9a JR |
1541 | out: |
1542 | update_cr8_intercept(vcpu); | |
85f455f7 ED |
1543 | } |
1544 | ||
1545 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1546 | { | |
e756fc62 | 1547 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1548 | |
7017fc3d ED |
1549 | if ((control->int_ctl & V_IRQ_MASK) |
1550 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1551 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1552 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1553 | } |
c1150d8c | 1554 | |
ad312c7c | 1555 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1556 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1557 | } | |
1558 | ||
85f455f7 ED |
1559 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1560 | { | |
1561 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1562 | int word_index = __ffs(vcpu->arch.irq_summary); |
1563 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1564 | int irq = word_index * BITS_PER_LONG + bit_index; |
1565 | ||
ad312c7c ZX |
1566 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1567 | if (!vcpu->arch.irq_pending[word_index]) | |
1568 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1569 | svm_inject_irq(svm, irq); |
1570 | } | |
1571 | ||
04d2cc77 | 1572 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1573 | struct kvm_run *kvm_run) |
1574 | { | |
04d2cc77 | 1575 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1576 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1577 | |
ad312c7c | 1578 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1579 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1580 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1581 | |
ad312c7c | 1582 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1583 | /* |
1584 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1585 | */ | |
85f455f7 | 1586 | svm_do_inject_vector(svm); |
c1150d8c DL |
1587 | |
1588 | /* | |
1589 | * Interrupts blocked. Wait for unblock. | |
1590 | */ | |
ad312c7c ZX |
1591 | if (!svm->vcpu.arch.interrupt_window_open && |
1592 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
c1150d8c | 1593 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1594 | else |
c1150d8c DL |
1595 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1596 | } | |
1597 | ||
cbc94022 IE |
1598 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1599 | { | |
1600 | return 0; | |
1601 | } | |
1602 | ||
6aa8b732 AK |
1603 | static void save_db_regs(unsigned long *db_regs) |
1604 | { | |
5aff458e AK |
1605 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1606 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1607 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1608 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1609 | } |
1610 | ||
1611 | static void load_db_regs(unsigned long *db_regs) | |
1612 | { | |
5aff458e AK |
1613 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1614 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1615 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1616 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1617 | } |
1618 | ||
d9e368d6 AK |
1619 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1620 | { | |
1621 | force_new_asid(vcpu); | |
1622 | } | |
1623 | ||
04d2cc77 AK |
1624 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1625 | { | |
1626 | } | |
1627 | ||
d7bf8221 JR |
1628 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
1629 | { | |
1630 | struct vcpu_svm *svm = to_svm(vcpu); | |
1631 | ||
1632 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
1633 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
1634 | kvm_lapic_set_tpr(vcpu, cr8); | |
1635 | } | |
1636 | } | |
1637 | ||
649d6864 JR |
1638 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
1639 | { | |
1640 | struct vcpu_svm *svm = to_svm(vcpu); | |
1641 | u64 cr8; | |
1642 | ||
1643 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1644 | return; | |
1645 | ||
1646 | cr8 = kvm_get_cr8(vcpu); | |
1647 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
1648 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
1649 | } | |
1650 | ||
04d2cc77 | 1651 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 1652 | { |
a2fa3e9f | 1653 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1654 | u16 fs_selector; |
1655 | u16 gs_selector; | |
1656 | u16 ldt_selector; | |
d9e368d6 | 1657 | |
e756fc62 | 1658 | pre_svm_run(svm); |
6aa8b732 | 1659 | |
649d6864 JR |
1660 | sync_lapic_to_cr8(vcpu); |
1661 | ||
6aa8b732 AK |
1662 | save_host_msrs(vcpu); |
1663 | fs_selector = read_fs(); | |
1664 | gs_selector = read_gs(); | |
1665 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1666 | svm->host_cr2 = kvm_read_cr2(); |
1667 | svm->host_dr6 = read_dr6(); | |
1668 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1669 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
1670 | /* required for live migration with NPT */ |
1671 | if (npt_enabled) | |
1672 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 1673 | |
a2fa3e9f | 1674 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1675 | write_dr7(0); |
a2fa3e9f GH |
1676 | save_db_regs(svm->host_db_regs); |
1677 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1678 | } |
36241b8c | 1679 | |
04d2cc77 AK |
1680 | clgi(); |
1681 | ||
1682 | local_irq_enable(); | |
36241b8c | 1683 | |
6aa8b732 | 1684 | asm volatile ( |
05b3e0c2 | 1685 | #ifdef CONFIG_X86_64 |
54a08c04 | 1686 | "push %%rbp; \n\t" |
6aa8b732 | 1687 | #else |
fe7935d4 | 1688 | "push %%ebp; \n\t" |
6aa8b732 AK |
1689 | #endif |
1690 | ||
05b3e0c2 | 1691 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1692 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1693 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1694 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1695 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1696 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1697 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1698 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1699 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1700 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1701 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1702 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1703 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1704 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1705 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1706 | #else |
fb3f0f51 RR |
1707 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1708 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1709 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1710 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1711 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1712 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1713 | #endif |
1714 | ||
05b3e0c2 | 1715 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1716 | /* Enter guest mode */ |
1717 | "push %%rax \n\t" | |
fb3f0f51 | 1718 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1719 | SVM_VMLOAD "\n\t" |
1720 | SVM_VMRUN "\n\t" | |
1721 | SVM_VMSAVE "\n\t" | |
1722 | "pop %%rax \n\t" | |
1723 | #else | |
1724 | /* Enter guest mode */ | |
1725 | "push %%eax \n\t" | |
fb3f0f51 | 1726 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1727 | SVM_VMLOAD "\n\t" |
1728 | SVM_VMRUN "\n\t" | |
1729 | SVM_VMSAVE "\n\t" | |
1730 | "pop %%eax \n\t" | |
1731 | #endif | |
1732 | ||
1733 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1734 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1735 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1736 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1737 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1738 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1739 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1740 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1741 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1742 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1743 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1744 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1745 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1746 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1747 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1748 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1749 | |
54a08c04 | 1750 | "pop %%rbp; \n\t" |
6aa8b732 | 1751 | #else |
fb3f0f51 RR |
1752 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1753 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1754 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1755 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1756 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1757 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1758 | |
fe7935d4 | 1759 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1760 | #endif |
1761 | : | |
fb3f0f51 | 1762 | : [svm]"a"(svm), |
6aa8b732 | 1763 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1764 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1765 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1766 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1767 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1768 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1769 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1770 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1771 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1772 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1773 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1774 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1775 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1776 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1777 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1778 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1779 | #endif |
54a08c04 LV |
1780 | : "cc", "memory" |
1781 | #ifdef CONFIG_X86_64 | |
1782 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1783 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1784 | #else |
1785 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1786 | #endif |
1787 | ); | |
6aa8b732 | 1788 | |
a2fa3e9f GH |
1789 | if ((svm->vmcb->save.dr7 & 0xff)) |
1790 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1791 | |
ad312c7c | 1792 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1793 | |
a2fa3e9f GH |
1794 | write_dr6(svm->host_dr6); |
1795 | write_dr7(svm->host_dr7); | |
1796 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1797 | |
1798 | load_fs(fs_selector); | |
1799 | load_gs(gs_selector); | |
1800 | load_ldt(ldt_selector); | |
1801 | load_host_msrs(vcpu); | |
1802 | ||
1803 | reload_tss(vcpu); | |
1804 | ||
56ba47dd AK |
1805 | local_irq_disable(); |
1806 | ||
1807 | stgi(); | |
1808 | ||
d7bf8221 JR |
1809 | sync_cr8_to_lapic(vcpu); |
1810 | ||
a2fa3e9f | 1811 | svm->next_rip = 0; |
6aa8b732 AK |
1812 | } |
1813 | ||
6aa8b732 AK |
1814 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1815 | { | |
a2fa3e9f GH |
1816 | struct vcpu_svm *svm = to_svm(vcpu); |
1817 | ||
709ddebf JR |
1818 | if (npt_enabled) { |
1819 | svm->vmcb->control.nested_cr3 = root; | |
1820 | force_new_asid(vcpu); | |
1821 | return; | |
1822 | } | |
1823 | ||
a2fa3e9f | 1824 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 1825 | force_new_asid(vcpu); |
7807fa6c AL |
1826 | |
1827 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1828 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1829 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1830 | vcpu->fpu_active = 0; |
1831 | } | |
6aa8b732 AK |
1832 | } |
1833 | ||
6aa8b732 AK |
1834 | static int is_disabled(void) |
1835 | { | |
6031a61c JR |
1836 | u64 vm_cr; |
1837 | ||
1838 | rdmsrl(MSR_VM_CR, vm_cr); | |
1839 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1840 | return 1; | |
1841 | ||
6aa8b732 AK |
1842 | return 0; |
1843 | } | |
1844 | ||
102d8325 IM |
1845 | static void |
1846 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1847 | { | |
1848 | /* | |
1849 | * Patch in the VMMCALL instruction: | |
1850 | */ | |
1851 | hypercall[0] = 0x0f; | |
1852 | hypercall[1] = 0x01; | |
1853 | hypercall[2] = 0xd9; | |
102d8325 IM |
1854 | } |
1855 | ||
002c7f7c YS |
1856 | static void svm_check_processor_compat(void *rtn) |
1857 | { | |
1858 | *(int *)rtn = 0; | |
1859 | } | |
1860 | ||
774ead3a AK |
1861 | static bool svm_cpu_has_accelerated_tpr(void) |
1862 | { | |
1863 | return false; | |
1864 | } | |
1865 | ||
67253af5 SY |
1866 | static int get_npt_level(void) |
1867 | { | |
1868 | #ifdef CONFIG_X86_64 | |
1869 | return PT64_ROOT_LEVEL; | |
1870 | #else | |
1871 | return PT32E_ROOT_LEVEL; | |
1872 | #endif | |
1873 | } | |
1874 | ||
cbdd1bea | 1875 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1876 | .cpu_has_kvm_support = has_svm, |
1877 | .disabled_by_bios = is_disabled, | |
1878 | .hardware_setup = svm_hardware_setup, | |
1879 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1880 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1881 | .hardware_enable = svm_hardware_enable, |
1882 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 1883 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
1884 | |
1885 | .vcpu_create = svm_create_vcpu, | |
1886 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1887 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1888 | |
04d2cc77 | 1889 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1890 | .vcpu_load = svm_vcpu_load, |
1891 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1892 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1893 | |
1894 | .set_guest_debug = svm_guest_debug, | |
1895 | .get_msr = svm_get_msr, | |
1896 | .set_msr = svm_set_msr, | |
1897 | .get_segment_base = svm_get_segment_base, | |
1898 | .get_segment = svm_get_segment, | |
1899 | .set_segment = svm_set_segment, | |
2e4d2653 | 1900 | .get_cpl = svm_get_cpl, |
1747fb71 | 1901 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1902 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1903 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1904 | .set_cr3 = svm_set_cr3, |
1905 | .set_cr4 = svm_set_cr4, | |
1906 | .set_efer = svm_set_efer, | |
1907 | .get_idt = svm_get_idt, | |
1908 | .set_idt = svm_set_idt, | |
1909 | .get_gdt = svm_get_gdt, | |
1910 | .set_gdt = svm_set_gdt, | |
1911 | .get_dr = svm_get_dr, | |
1912 | .set_dr = svm_set_dr, | |
1913 | .cache_regs = svm_cache_regs, | |
1914 | .decache_regs = svm_decache_regs, | |
1915 | .get_rflags = svm_get_rflags, | |
1916 | .set_rflags = svm_set_rflags, | |
1917 | ||
6aa8b732 | 1918 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1919 | |
6aa8b732 | 1920 | .run = svm_vcpu_run, |
04d2cc77 | 1921 | .handle_exit = handle_exit, |
6aa8b732 | 1922 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1923 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1924 | .get_irq = svm_get_irq, |
1925 | .set_irq = svm_set_irq, | |
298101da AK |
1926 | .queue_exception = svm_queue_exception, |
1927 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1928 | .inject_pending_irq = svm_intr_assist, |
1929 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1930 | |
1931 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 1932 | .get_tdp_level = get_npt_level, |
6aa8b732 AK |
1933 | }; |
1934 | ||
1935 | static int __init svm_init(void) | |
1936 | { | |
cb498ea2 | 1937 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1938 | THIS_MODULE); |
6aa8b732 AK |
1939 | } |
1940 | ||
1941 | static void __exit svm_exit(void) | |
1942 | { | |
cb498ea2 | 1943 | kvm_exit(); |
6aa8b732 AK |
1944 | } |
1945 | ||
1946 | module_init(svm_init) | |
1947 | module_exit(svm_exit) |