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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
631bc487 | 34 | #include <asm/kvm_para.h> |
6aa8b732 | 35 | |
63d1142f | 36 | #include <asm/virtext.h> |
229456fc | 37 | #include "trace.h" |
63d1142f | 38 | |
4ecac3fd AK |
39 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
40 | ||
6aa8b732 AK |
41 | MODULE_AUTHOR("Qumranet"); |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | #define IOPM_ALLOC_ORDER 2 | |
45 | #define MSRPM_ALLOC_ORDER 1 | |
46 | ||
6aa8b732 AK |
47 | #define SEG_TYPE_LDT 2 |
48 | #define SEG_TYPE_BUSY_TSS16 3 | |
49 | ||
6bc31bdc AP |
50 | #define SVM_FEATURE_NPT (1 << 0) |
51 | #define SVM_FEATURE_LBRV (1 << 1) | |
52 | #define SVM_FEATURE_SVML (1 << 2) | |
53 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
54 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
55 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
56 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
57 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 58 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 59 | |
410e4d57 JR |
60 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
61 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
62 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
63 | ||
24e09cbf JR |
64 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
65 | ||
67ec6607 JR |
66 | static bool erratum_383_found __read_mostly; |
67 | ||
6c8166a7 AK |
68 | static const u32 host_save_user_msrs[] = { |
69 | #ifdef CONFIG_X86_64 | |
70 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
71 | MSR_FS_BASE, | |
72 | #endif | |
73 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
74 | }; | |
75 | ||
76 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
77 | ||
78 | struct kvm_vcpu; | |
79 | ||
e6aa9abd JR |
80 | struct nested_state { |
81 | struct vmcb *hsave; | |
82 | u64 hsave_msr; | |
4a810181 | 83 | u64 vm_cr_msr; |
e6aa9abd JR |
84 | u64 vmcb; |
85 | ||
86 | /* These are the merged vectors */ | |
87 | u32 *msrpm; | |
88 | ||
89 | /* gpa pointers to the real vectors */ | |
90 | u64 vmcb_msrpm; | |
ce2ac085 | 91 | u64 vmcb_iopm; |
aad42c64 | 92 | |
cd3ff653 JR |
93 | /* A VMEXIT is required but not yet emulated */ |
94 | bool exit_required; | |
95 | ||
cda00082 JR |
96 | /* |
97 | * If we vmexit during an instruction emulation we need this to restore | |
98 | * the l1 guest rip after the emulation | |
99 | */ | |
100 | unsigned long vmexit_rip; | |
101 | unsigned long vmexit_rsp; | |
102 | unsigned long vmexit_rax; | |
103 | ||
aad42c64 | 104 | /* cache for intercepts of the guest */ |
4ee546b4 | 105 | u32 intercept_cr; |
3aed041a | 106 | u32 intercept_dr; |
aad42c64 JR |
107 | u32 intercept_exceptions; |
108 | u64 intercept; | |
109 | ||
5bd2edc3 JR |
110 | /* Nested Paging related state */ |
111 | u64 nested_cr3; | |
e6aa9abd JR |
112 | }; |
113 | ||
323c3d80 JR |
114 | #define MSRPM_OFFSETS 16 |
115 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
116 | ||
6c8166a7 AK |
117 | struct vcpu_svm { |
118 | struct kvm_vcpu vcpu; | |
119 | struct vmcb *vmcb; | |
120 | unsigned long vmcb_pa; | |
121 | struct svm_cpu_data *svm_data; | |
122 | uint64_t asid_generation; | |
123 | uint64_t sysenter_esp; | |
124 | uint64_t sysenter_eip; | |
125 | ||
126 | u64 next_rip; | |
127 | ||
128 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 129 | struct { |
dacccfdd AK |
130 | u16 fs; |
131 | u16 gs; | |
132 | u16 ldt; | |
afe9e66f AK |
133 | u64 gs_base; |
134 | } host; | |
6c8166a7 AK |
135 | |
136 | u32 *msrpm; | |
6c8166a7 | 137 | |
e6aa9abd | 138 | struct nested_state nested; |
6be7d306 JK |
139 | |
140 | bool nmi_singlestep; | |
66b7138f JK |
141 | |
142 | unsigned int3_injected; | |
143 | unsigned long int3_rip; | |
631bc487 | 144 | u32 apf_reason; |
6c8166a7 AK |
145 | }; |
146 | ||
455716fa JR |
147 | #define MSR_INVALID 0xffffffffU |
148 | ||
ac72a9b7 JR |
149 | static struct svm_direct_access_msrs { |
150 | u32 index; /* Index of the MSR */ | |
151 | bool always; /* True if intercept is always on */ | |
152 | } direct_access_msrs[] = { | |
8c06585d | 153 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
154 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
155 | #ifdef CONFIG_X86_64 | |
156 | { .index = MSR_GS_BASE, .always = true }, | |
157 | { .index = MSR_FS_BASE, .always = true }, | |
158 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
159 | { .index = MSR_LSTAR, .always = true }, | |
160 | { .index = MSR_CSTAR, .always = true }, | |
161 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
162 | #endif | |
163 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
164 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
165 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
166 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
167 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
168 | }; |
169 | ||
709ddebf JR |
170 | /* enable NPT for AMD64 and X86 with PAE */ |
171 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
172 | static bool npt_enabled = true; | |
173 | #else | |
e0231715 | 174 | static bool npt_enabled; |
709ddebf | 175 | #endif |
6c7dac72 JR |
176 | static int npt = 1; |
177 | ||
178 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 179 | |
4b6e4dca | 180 | static int nested = 1; |
236de055 AG |
181 | module_param(nested, int, S_IRUGO); |
182 | ||
44874f84 | 183 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 184 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 185 | |
410e4d57 | 186 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 187 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 188 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
189 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
190 | bool has_error_code, u32 error_code); | |
191 | ||
8d28fec4 | 192 | enum { |
116a0a23 JR |
193 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
194 | pause filter count */ | |
f56838e4 | 195 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 196 | VMCB_ASID, /* ASID */ |
decdbf6a | 197 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 198 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 199 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 200 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 201 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 202 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 203 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 204 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
205 | VMCB_DIRTY_MAX, |
206 | }; | |
207 | ||
0574dec0 JR |
208 | /* TPR and CR2 are always written before VMRUN */ |
209 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
210 | |
211 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
212 | { | |
213 | vmcb->control.clean = 0; | |
214 | } | |
215 | ||
216 | static inline void mark_all_clean(struct vmcb *vmcb) | |
217 | { | |
218 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
219 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
220 | } | |
221 | ||
222 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
223 | { | |
224 | vmcb->control.clean &= ~(1 << bit); | |
225 | } | |
226 | ||
a2fa3e9f GH |
227 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
228 | { | |
fb3f0f51 | 229 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
230 | } |
231 | ||
384c6368 JR |
232 | static void recalc_intercepts(struct vcpu_svm *svm) |
233 | { | |
234 | struct vmcb_control_area *c, *h; | |
235 | struct nested_state *g; | |
236 | ||
116a0a23 JR |
237 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
238 | ||
384c6368 JR |
239 | if (!is_guest_mode(&svm->vcpu)) |
240 | return; | |
241 | ||
242 | c = &svm->vmcb->control; | |
243 | h = &svm->nested.hsave->control; | |
244 | g = &svm->nested; | |
245 | ||
4ee546b4 | 246 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 247 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
248 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
249 | c->intercept = h->intercept | g->intercept; | |
250 | } | |
251 | ||
4ee546b4 RJ |
252 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
253 | { | |
254 | if (is_guest_mode(&svm->vcpu)) | |
255 | return svm->nested.hsave; | |
256 | else | |
257 | return svm->vmcb; | |
258 | } | |
259 | ||
260 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
261 | { | |
262 | struct vmcb *vmcb = get_host_vmcb(svm); | |
263 | ||
264 | vmcb->control.intercept_cr |= (1U << bit); | |
265 | ||
266 | recalc_intercepts(svm); | |
267 | } | |
268 | ||
269 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
270 | { | |
271 | struct vmcb *vmcb = get_host_vmcb(svm); | |
272 | ||
273 | vmcb->control.intercept_cr &= ~(1U << bit); | |
274 | ||
275 | recalc_intercepts(svm); | |
276 | } | |
277 | ||
278 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
279 | { | |
280 | struct vmcb *vmcb = get_host_vmcb(svm); | |
281 | ||
282 | return vmcb->control.intercept_cr & (1U << bit); | |
283 | } | |
284 | ||
3aed041a JR |
285 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
286 | { | |
287 | struct vmcb *vmcb = get_host_vmcb(svm); | |
288 | ||
289 | vmcb->control.intercept_dr |= (1U << bit); | |
290 | ||
291 | recalc_intercepts(svm); | |
292 | } | |
293 | ||
294 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
295 | { | |
296 | struct vmcb *vmcb = get_host_vmcb(svm); | |
297 | ||
298 | vmcb->control.intercept_dr &= ~(1U << bit); | |
299 | ||
300 | recalc_intercepts(svm); | |
301 | } | |
302 | ||
18c918c5 JR |
303 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
304 | { | |
305 | struct vmcb *vmcb = get_host_vmcb(svm); | |
306 | ||
307 | vmcb->control.intercept_exceptions |= (1U << bit); | |
308 | ||
309 | recalc_intercepts(svm); | |
310 | } | |
311 | ||
312 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
313 | { | |
314 | struct vmcb *vmcb = get_host_vmcb(svm); | |
315 | ||
316 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
317 | ||
318 | recalc_intercepts(svm); | |
319 | } | |
320 | ||
8a05a1b8 JR |
321 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
322 | { | |
323 | struct vmcb *vmcb = get_host_vmcb(svm); | |
324 | ||
325 | vmcb->control.intercept |= (1ULL << bit); | |
326 | ||
327 | recalc_intercepts(svm); | |
328 | } | |
329 | ||
330 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
331 | { | |
332 | struct vmcb *vmcb = get_host_vmcb(svm); | |
333 | ||
334 | vmcb->control.intercept &= ~(1ULL << bit); | |
335 | ||
336 | recalc_intercepts(svm); | |
337 | } | |
338 | ||
2af9194d JR |
339 | static inline void enable_gif(struct vcpu_svm *svm) |
340 | { | |
341 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
342 | } | |
343 | ||
344 | static inline void disable_gif(struct vcpu_svm *svm) | |
345 | { | |
346 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
347 | } | |
348 | ||
349 | static inline bool gif_set(struct vcpu_svm *svm) | |
350 | { | |
351 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
352 | } | |
353 | ||
4866d5e3 | 354 | static unsigned long iopm_base; |
6aa8b732 AK |
355 | |
356 | struct kvm_ldttss_desc { | |
357 | u16 limit0; | |
358 | u16 base0; | |
e0231715 JR |
359 | unsigned base1:8, type:5, dpl:2, p:1; |
360 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
361 | u32 base3; |
362 | u32 zero1; | |
363 | } __attribute__((packed)); | |
364 | ||
365 | struct svm_cpu_data { | |
366 | int cpu; | |
367 | ||
5008fdf5 AK |
368 | u64 asid_generation; |
369 | u32 max_asid; | |
370 | u32 next_asid; | |
6aa8b732 AK |
371 | struct kvm_ldttss_desc *tss_desc; |
372 | ||
373 | struct page *save_area; | |
374 | }; | |
375 | ||
376 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 377 | static uint32_t svm_features; |
6aa8b732 AK |
378 | |
379 | struct svm_init_data { | |
380 | int cpu; | |
381 | int r; | |
382 | }; | |
383 | ||
384 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
385 | ||
9d8f549d | 386 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
387 | #define MSRS_RANGE_SIZE 2048 |
388 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
389 | ||
455716fa JR |
390 | static u32 svm_msrpm_offset(u32 msr) |
391 | { | |
392 | u32 offset; | |
393 | int i; | |
394 | ||
395 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
396 | if (msr < msrpm_ranges[i] || | |
397 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
398 | continue; | |
399 | ||
400 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
401 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
402 | ||
403 | /* Now we have the u8 offset - but need the u32 offset */ | |
404 | return offset / 4; | |
405 | } | |
406 | ||
407 | /* MSR not in any range */ | |
408 | return MSR_INVALID; | |
409 | } | |
410 | ||
6aa8b732 AK |
411 | #define MAX_INST_SIZE 15 |
412 | ||
6aa8b732 AK |
413 | static inline void clgi(void) |
414 | { | |
4ecac3fd | 415 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
416 | } |
417 | ||
418 | static inline void stgi(void) | |
419 | { | |
4ecac3fd | 420 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
421 | } |
422 | ||
423 | static inline void invlpga(unsigned long addr, u32 asid) | |
424 | { | |
e0231715 | 425 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
426 | } |
427 | ||
4b16184c JR |
428 | static int get_npt_level(void) |
429 | { | |
430 | #ifdef CONFIG_X86_64 | |
431 | return PT64_ROOT_LEVEL; | |
432 | #else | |
433 | return PT32E_ROOT_LEVEL; | |
434 | #endif | |
435 | } | |
436 | ||
6aa8b732 AK |
437 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
438 | { | |
6dc696d4 | 439 | vcpu->arch.efer = efer; |
709ddebf | 440 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 441 | efer &= ~EFER_LME; |
6aa8b732 | 442 | |
9962d032 | 443 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 444 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
445 | } |
446 | ||
6aa8b732 AK |
447 | static int is_external_interrupt(u32 info) |
448 | { | |
449 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
450 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
451 | } | |
452 | ||
2809f5d2 GC |
453 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
454 | { | |
455 | struct vcpu_svm *svm = to_svm(vcpu); | |
456 | u32 ret = 0; | |
457 | ||
458 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 459 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
460 | return ret & mask; |
461 | } | |
462 | ||
463 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
464 | { | |
465 | struct vcpu_svm *svm = to_svm(vcpu); | |
466 | ||
467 | if (mask == 0) | |
468 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
469 | else | |
470 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
471 | ||
472 | } | |
473 | ||
6aa8b732 AK |
474 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
475 | { | |
a2fa3e9f GH |
476 | struct vcpu_svm *svm = to_svm(vcpu); |
477 | ||
6bc31bdc AP |
478 | if (svm->vmcb->control.next_rip != 0) |
479 | svm->next_rip = svm->vmcb->control.next_rip; | |
480 | ||
a2fa3e9f | 481 | if (!svm->next_rip) { |
51d8b661 | 482 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
483 | EMULATE_DONE) |
484 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
485 | return; |
486 | } | |
5fdbf976 MT |
487 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
488 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
489 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 490 | |
5fdbf976 | 491 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 492 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
493 | } |
494 | ||
116a4752 | 495 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
496 | bool has_error_code, u32 error_code, |
497 | bool reinject) | |
116a4752 JK |
498 | { |
499 | struct vcpu_svm *svm = to_svm(vcpu); | |
500 | ||
e0231715 JR |
501 | /* |
502 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
503 | * handle the exception | |
504 | */ | |
ce7ddec4 JR |
505 | if (!reinject && |
506 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
507 | return; |
508 | ||
2a6b20b8 | 509 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
510 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
511 | ||
512 | /* | |
513 | * For guest debugging where we have to reinject #BP if some | |
514 | * INT3 is guest-owned: | |
515 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
516 | * raises a fault that is not intercepted. Still better than | |
517 | * failing in all cases. | |
518 | */ | |
519 | skip_emulated_instruction(&svm->vcpu); | |
520 | rip = kvm_rip_read(&svm->vcpu); | |
521 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
522 | svm->int3_injected = rip - old_rip; | |
523 | } | |
524 | ||
116a4752 JK |
525 | svm->vmcb->control.event_inj = nr |
526 | | SVM_EVTINJ_VALID | |
527 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
528 | | SVM_EVTINJ_TYPE_EXEPT; | |
529 | svm->vmcb->control.event_inj_err = error_code; | |
530 | } | |
531 | ||
67ec6607 JR |
532 | static void svm_init_erratum_383(void) |
533 | { | |
534 | u32 low, high; | |
535 | int err; | |
536 | u64 val; | |
537 | ||
1be85a6d | 538 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
539 | return; |
540 | ||
541 | /* Use _safe variants to not break nested virtualization */ | |
542 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
543 | if (err) | |
544 | return; | |
545 | ||
546 | val |= (1ULL << 47); | |
547 | ||
548 | low = lower_32_bits(val); | |
549 | high = upper_32_bits(val); | |
550 | ||
551 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
552 | ||
553 | erratum_383_found = true; | |
554 | } | |
555 | ||
6aa8b732 AK |
556 | static int has_svm(void) |
557 | { | |
63d1142f | 558 | const char *msg; |
6aa8b732 | 559 | |
63d1142f | 560 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 561 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
562 | return 0; |
563 | } | |
564 | ||
6aa8b732 AK |
565 | return 1; |
566 | } | |
567 | ||
568 | static void svm_hardware_disable(void *garbage) | |
569 | { | |
2c8dceeb | 570 | cpu_svm_disable(); |
6aa8b732 AK |
571 | } |
572 | ||
10474ae8 | 573 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
574 | { |
575 | ||
0fe1e009 | 576 | struct svm_cpu_data *sd; |
6aa8b732 | 577 | uint64_t efer; |
89a27f4d | 578 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
579 | struct desc_struct *gdt; |
580 | int me = raw_smp_processor_id(); | |
581 | ||
10474ae8 AG |
582 | rdmsrl(MSR_EFER, efer); |
583 | if (efer & EFER_SVME) | |
584 | return -EBUSY; | |
585 | ||
6aa8b732 | 586 | if (!has_svm()) { |
e6732a5a ZA |
587 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
588 | me); | |
10474ae8 | 589 | return -EINVAL; |
6aa8b732 | 590 | } |
0fe1e009 | 591 | sd = per_cpu(svm_data, me); |
6aa8b732 | 592 | |
0fe1e009 | 593 | if (!sd) { |
e6732a5a | 594 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 595 | me); |
10474ae8 | 596 | return -EINVAL; |
6aa8b732 AK |
597 | } |
598 | ||
0fe1e009 TH |
599 | sd->asid_generation = 1; |
600 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
601 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 602 | |
d6ab1ed4 | 603 | native_store_gdt(&gdt_descr); |
89a27f4d | 604 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 605 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 606 | |
9962d032 | 607 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 608 | |
d0316554 | 609 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 610 | |
67ec6607 JR |
611 | svm_init_erratum_383(); |
612 | ||
10474ae8 | 613 | return 0; |
6aa8b732 AK |
614 | } |
615 | ||
0da1db75 JR |
616 | static void svm_cpu_uninit(int cpu) |
617 | { | |
0fe1e009 | 618 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 619 | |
0fe1e009 | 620 | if (!sd) |
0da1db75 JR |
621 | return; |
622 | ||
623 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
624 | __free_page(sd->save_area); |
625 | kfree(sd); | |
0da1db75 JR |
626 | } |
627 | ||
6aa8b732 AK |
628 | static int svm_cpu_init(int cpu) |
629 | { | |
0fe1e009 | 630 | struct svm_cpu_data *sd; |
6aa8b732 AK |
631 | int r; |
632 | ||
0fe1e009 TH |
633 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
634 | if (!sd) | |
6aa8b732 | 635 | return -ENOMEM; |
0fe1e009 TH |
636 | sd->cpu = cpu; |
637 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 638 | r = -ENOMEM; |
0fe1e009 | 639 | if (!sd->save_area) |
6aa8b732 AK |
640 | goto err_1; |
641 | ||
0fe1e009 | 642 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
643 | |
644 | return 0; | |
645 | ||
646 | err_1: | |
0fe1e009 | 647 | kfree(sd); |
6aa8b732 AK |
648 | return r; |
649 | ||
650 | } | |
651 | ||
ac72a9b7 JR |
652 | static bool valid_msr_intercept(u32 index) |
653 | { | |
654 | int i; | |
655 | ||
656 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
657 | if (direct_access_msrs[i].index == index) | |
658 | return true; | |
659 | ||
660 | return false; | |
661 | } | |
662 | ||
bfc733a7 RR |
663 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
664 | int read, int write) | |
6aa8b732 | 665 | { |
455716fa JR |
666 | u8 bit_read, bit_write; |
667 | unsigned long tmp; | |
668 | u32 offset; | |
6aa8b732 | 669 | |
ac72a9b7 JR |
670 | /* |
671 | * If this warning triggers extend the direct_access_msrs list at the | |
672 | * beginning of the file | |
673 | */ | |
674 | WARN_ON(!valid_msr_intercept(msr)); | |
675 | ||
455716fa JR |
676 | offset = svm_msrpm_offset(msr); |
677 | bit_read = 2 * (msr & 0x0f); | |
678 | bit_write = 2 * (msr & 0x0f) + 1; | |
679 | tmp = msrpm[offset]; | |
680 | ||
681 | BUG_ON(offset == MSR_INVALID); | |
682 | ||
683 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
684 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
685 | ||
686 | msrpm[offset] = tmp; | |
6aa8b732 AK |
687 | } |
688 | ||
f65c229c | 689 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
690 | { |
691 | int i; | |
692 | ||
f65c229c JR |
693 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
694 | ||
ac72a9b7 JR |
695 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
696 | if (!direct_access_msrs[i].always) | |
697 | continue; | |
698 | ||
699 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
700 | } | |
f65c229c JR |
701 | } |
702 | ||
323c3d80 JR |
703 | static void add_msr_offset(u32 offset) |
704 | { | |
705 | int i; | |
706 | ||
707 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
708 | ||
709 | /* Offset already in list? */ | |
710 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 711 | return; |
323c3d80 JR |
712 | |
713 | /* Slot used by another offset? */ | |
714 | if (msrpm_offsets[i] != MSR_INVALID) | |
715 | continue; | |
716 | ||
717 | /* Add offset to list */ | |
718 | msrpm_offsets[i] = offset; | |
719 | ||
720 | return; | |
6aa8b732 | 721 | } |
323c3d80 JR |
722 | |
723 | /* | |
724 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
725 | * increase MSRPM_OFFSETS in this case. | |
726 | */ | |
bfc733a7 | 727 | BUG(); |
6aa8b732 AK |
728 | } |
729 | ||
323c3d80 | 730 | static void init_msrpm_offsets(void) |
f65c229c | 731 | { |
323c3d80 | 732 | int i; |
f65c229c | 733 | |
323c3d80 JR |
734 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
735 | ||
736 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
737 | u32 offset; | |
738 | ||
739 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
740 | BUG_ON(offset == MSR_INVALID); | |
741 | ||
742 | add_msr_offset(offset); | |
743 | } | |
f65c229c JR |
744 | } |
745 | ||
24e09cbf JR |
746 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
747 | { | |
748 | u32 *msrpm = svm->msrpm; | |
749 | ||
750 | svm->vmcb->control.lbr_ctl = 1; | |
751 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
752 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
753 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
754 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
755 | } | |
756 | ||
757 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
758 | { | |
759 | u32 *msrpm = svm->msrpm; | |
760 | ||
761 | svm->vmcb->control.lbr_ctl = 0; | |
762 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
763 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
764 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
765 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
766 | } | |
767 | ||
6aa8b732 AK |
768 | static __init int svm_hardware_setup(void) |
769 | { | |
770 | int cpu; | |
771 | struct page *iopm_pages; | |
f65c229c | 772 | void *iopm_va; |
6aa8b732 AK |
773 | int r; |
774 | ||
6aa8b732 AK |
775 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
776 | ||
777 | if (!iopm_pages) | |
778 | return -ENOMEM; | |
c8681339 AL |
779 | |
780 | iopm_va = page_address(iopm_pages); | |
781 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
782 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
783 | ||
323c3d80 JR |
784 | init_msrpm_offsets(); |
785 | ||
50a37eb4 JR |
786 | if (boot_cpu_has(X86_FEATURE_NX)) |
787 | kvm_enable_efer_bits(EFER_NX); | |
788 | ||
1b2fd70c AG |
789 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
790 | kvm_enable_efer_bits(EFER_FFXSR); | |
791 | ||
236de055 AG |
792 | if (nested) { |
793 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 794 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
795 | } |
796 | ||
3230bb47 | 797 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
798 | r = svm_cpu_init(cpu); |
799 | if (r) | |
f65c229c | 800 | goto err; |
6aa8b732 | 801 | } |
33bd6a0b JR |
802 | |
803 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
804 | ||
2a6b20b8 | 805 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
806 | npt_enabled = false; |
807 | ||
6c7dac72 JR |
808 | if (npt_enabled && !npt) { |
809 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
810 | npt_enabled = false; | |
811 | } | |
812 | ||
18552672 | 813 | if (npt_enabled) { |
e3da3acd | 814 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 815 | kvm_enable_tdp(); |
5f4cb662 JR |
816 | } else |
817 | kvm_disable_tdp(); | |
e3da3acd | 818 | |
6aa8b732 AK |
819 | return 0; |
820 | ||
f65c229c | 821 | err: |
6aa8b732 AK |
822 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
823 | iopm_base = 0; | |
824 | return r; | |
825 | } | |
826 | ||
827 | static __exit void svm_hardware_unsetup(void) | |
828 | { | |
0da1db75 JR |
829 | int cpu; |
830 | ||
3230bb47 | 831 | for_each_possible_cpu(cpu) |
0da1db75 JR |
832 | svm_cpu_uninit(cpu); |
833 | ||
6aa8b732 | 834 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 835 | iopm_base = 0; |
6aa8b732 AK |
836 | } |
837 | ||
838 | static void init_seg(struct vmcb_seg *seg) | |
839 | { | |
840 | seg->selector = 0; | |
841 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 842 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
843 | seg->limit = 0xffff; |
844 | seg->base = 0; | |
845 | } | |
846 | ||
847 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
848 | { | |
849 | seg->selector = 0; | |
850 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
851 | seg->limit = 0xffff; | |
852 | seg->base = 0; | |
853 | } | |
854 | ||
f4e1b3c8 ZA |
855 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
856 | { | |
857 | struct vcpu_svm *svm = to_svm(vcpu); | |
858 | u64 g_tsc_offset = 0; | |
859 | ||
2030753d | 860 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
861 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
862 | svm->nested.hsave->control.tsc_offset; | |
863 | svm->nested.hsave->control.tsc_offset = offset; | |
864 | } | |
865 | ||
866 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
867 | |
868 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
869 | } |
870 | ||
e48672fa ZA |
871 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
872 | { | |
873 | struct vcpu_svm *svm = to_svm(vcpu); | |
874 | ||
875 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 876 | if (is_guest_mode(vcpu)) |
e48672fa | 877 | svm->nested.hsave->control.tsc_offset += adjustment; |
116a0a23 | 878 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
879 | } |
880 | ||
e6101a96 | 881 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 882 | { |
e6101a96 JR |
883 | struct vmcb_control_area *control = &svm->vmcb->control; |
884 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 885 | |
bff78274 | 886 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 887 | svm->vcpu.arch.hflags = 0; |
bff78274 | 888 | |
4ee546b4 RJ |
889 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
890 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
891 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
892 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
893 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
894 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
895 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 896 | |
3aed041a JR |
897 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
898 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
899 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
900 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
901 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
902 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
903 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
904 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
905 | ||
906 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
907 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
908 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
909 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
910 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
911 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
912 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
913 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 914 | |
18c918c5 JR |
915 | set_exception_intercept(svm, PF_VECTOR); |
916 | set_exception_intercept(svm, UD_VECTOR); | |
917 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 918 | |
8a05a1b8 JR |
919 | set_intercept(svm, INTERCEPT_INTR); |
920 | set_intercept(svm, INTERCEPT_NMI); | |
921 | set_intercept(svm, INTERCEPT_SMI); | |
922 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
923 | set_intercept(svm, INTERCEPT_CPUID); | |
924 | set_intercept(svm, INTERCEPT_INVD); | |
925 | set_intercept(svm, INTERCEPT_HLT); | |
926 | set_intercept(svm, INTERCEPT_INVLPG); | |
927 | set_intercept(svm, INTERCEPT_INVLPGA); | |
928 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
929 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
930 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
931 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
932 | set_intercept(svm, INTERCEPT_VMRUN); | |
933 | set_intercept(svm, INTERCEPT_VMMCALL); | |
934 | set_intercept(svm, INTERCEPT_VMLOAD); | |
935 | set_intercept(svm, INTERCEPT_VMSAVE); | |
936 | set_intercept(svm, INTERCEPT_STGI); | |
937 | set_intercept(svm, INTERCEPT_CLGI); | |
938 | set_intercept(svm, INTERCEPT_SKINIT); | |
939 | set_intercept(svm, INTERCEPT_WBINVD); | |
940 | set_intercept(svm, INTERCEPT_MONITOR); | |
941 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 942 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
943 | |
944 | control->iopm_base_pa = iopm_base; | |
f65c229c | 945 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
946 | control->int_ctl = V_INTR_MASKING_MASK; |
947 | ||
948 | init_seg(&save->es); | |
949 | init_seg(&save->ss); | |
950 | init_seg(&save->ds); | |
951 | init_seg(&save->fs); | |
952 | init_seg(&save->gs); | |
953 | ||
954 | save->cs.selector = 0xf000; | |
955 | /* Executable/Readable Code Segment */ | |
956 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
957 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
958 | save->cs.limit = 0xffff; | |
d92899a0 AK |
959 | /* |
960 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
961 | * be consistent with it. | |
962 | * | |
963 | * Replace when we have real mode working for vmx. | |
964 | */ | |
965 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
966 | |
967 | save->gdtr.limit = 0xffff; | |
968 | save->idtr.limit = 0xffff; | |
969 | ||
970 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
971 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
972 | ||
eaa48512 | 973 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 974 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
975 | save->dr7 = 0x400; |
976 | save->rflags = 2; | |
977 | save->rip = 0x0000fff0; | |
5fdbf976 | 978 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 979 | |
e0231715 JR |
980 | /* |
981 | * This is the guest-visible cr0 value. | |
18fa000a | 982 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 983 | */ |
678041ad MT |
984 | svm->vcpu.arch.cr0 = 0; |
985 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 986 | |
66aee91a | 987 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 988 | /* rdx = ?? */ |
709ddebf JR |
989 | |
990 | if (npt_enabled) { | |
991 | /* Setup VMCB for Nested Paging */ | |
992 | control->nested_ctl = 1; | |
8a05a1b8 JR |
993 | clr_intercept(svm, INTERCEPT_TASK_SWITCH); |
994 | clr_intercept(svm, INTERCEPT_INVLPG); | |
18c918c5 | 995 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
996 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
997 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 998 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
999 | save->cr3 = 0; |
1000 | save->cr4 = 0; | |
1001 | } | |
f40f6a45 | 1002 | svm->asid_generation = 0; |
1371d904 | 1003 | |
e6aa9abd | 1004 | svm->nested.vmcb = 0; |
2af9194d JR |
1005 | svm->vcpu.arch.hflags = 0; |
1006 | ||
2a6b20b8 | 1007 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1008 | control->pause_filter_count = 3000; |
8a05a1b8 | 1009 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1010 | } |
1011 | ||
8d28fec4 RJ |
1012 | mark_all_dirty(svm->vmcb); |
1013 | ||
2af9194d | 1014 | enable_gif(svm); |
6aa8b732 AK |
1015 | } |
1016 | ||
e00c8cf2 | 1017 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1018 | { |
1019 | struct vcpu_svm *svm = to_svm(vcpu); | |
1020 | ||
e6101a96 | 1021 | init_vmcb(svm); |
70433389 | 1022 | |
c5af89b6 | 1023 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 1024 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
1025 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
1026 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 1027 | } |
5fdbf976 MT |
1028 | vcpu->arch.regs_avail = ~0; |
1029 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
1030 | |
1031 | return 0; | |
04d2cc77 AK |
1032 | } |
1033 | ||
fb3f0f51 | 1034 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1035 | { |
a2fa3e9f | 1036 | struct vcpu_svm *svm; |
6aa8b732 | 1037 | struct page *page; |
f65c229c | 1038 | struct page *msrpm_pages; |
b286d5d8 | 1039 | struct page *hsave_page; |
3d6368ef | 1040 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1041 | int err; |
6aa8b732 | 1042 | |
c16f862d | 1043 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1044 | if (!svm) { |
1045 | err = -ENOMEM; | |
1046 | goto out; | |
1047 | } | |
1048 | ||
1049 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1050 | if (err) | |
1051 | goto free_svm; | |
1052 | ||
b7af4043 | 1053 | err = -ENOMEM; |
6aa8b732 | 1054 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1055 | if (!page) |
fb3f0f51 | 1056 | goto uninit; |
6aa8b732 | 1057 | |
f65c229c JR |
1058 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1059 | if (!msrpm_pages) | |
b7af4043 | 1060 | goto free_page1; |
3d6368ef AG |
1061 | |
1062 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1063 | if (!nested_msrpm_pages) | |
b7af4043 | 1064 | goto free_page2; |
f65c229c | 1065 | |
b286d5d8 AG |
1066 | hsave_page = alloc_page(GFP_KERNEL); |
1067 | if (!hsave_page) | |
b7af4043 TY |
1068 | goto free_page3; |
1069 | ||
e6aa9abd | 1070 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1071 | |
b7af4043 TY |
1072 | svm->msrpm = page_address(msrpm_pages); |
1073 | svm_vcpu_init_msrpm(svm->msrpm); | |
1074 | ||
e6aa9abd | 1075 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1076 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1077 | |
a2fa3e9f GH |
1078 | svm->vmcb = page_address(page); |
1079 | clear_page(svm->vmcb); | |
1080 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1081 | svm->asid_generation = 0; | |
e6101a96 | 1082 | init_vmcb(svm); |
99e3e30a | 1083 | kvm_write_tsc(&svm->vcpu, 0); |
a2fa3e9f | 1084 | |
10ab25cd JK |
1085 | err = fx_init(&svm->vcpu); |
1086 | if (err) | |
1087 | goto free_page4; | |
1088 | ||
ad312c7c | 1089 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1090 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1091 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1092 | |
fb3f0f51 | 1093 | return &svm->vcpu; |
36241b8c | 1094 | |
10ab25cd JK |
1095 | free_page4: |
1096 | __free_page(hsave_page); | |
b7af4043 TY |
1097 | free_page3: |
1098 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1099 | free_page2: | |
1100 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1101 | free_page1: | |
1102 | __free_page(page); | |
fb3f0f51 RR |
1103 | uninit: |
1104 | kvm_vcpu_uninit(&svm->vcpu); | |
1105 | free_svm: | |
a4770347 | 1106 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1107 | out: |
1108 | return ERR_PTR(err); | |
6aa8b732 AK |
1109 | } |
1110 | ||
1111 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1112 | { | |
a2fa3e9f GH |
1113 | struct vcpu_svm *svm = to_svm(vcpu); |
1114 | ||
fb3f0f51 | 1115 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1116 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1117 | __free_page(virt_to_page(svm->nested.hsave)); |
1118 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1119 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1120 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1121 | } |
1122 | ||
15ad7146 | 1123 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1124 | { |
a2fa3e9f | 1125 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1126 | int i; |
0cc5064d | 1127 | |
0cc5064d | 1128 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1129 | svm->asid_generation = 0; |
8d28fec4 | 1130 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1131 | } |
94dfbdb3 | 1132 | |
82ca2d10 AK |
1133 | #ifdef CONFIG_X86_64 |
1134 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1135 | #endif | |
dacccfdd AK |
1136 | savesegment(fs, svm->host.fs); |
1137 | savesegment(gs, svm->host.gs); | |
1138 | svm->host.ldt = kvm_read_ldt(); | |
1139 | ||
94dfbdb3 | 1140 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1141 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1142 | } |
1143 | ||
1144 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1145 | { | |
a2fa3e9f | 1146 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1147 | int i; |
1148 | ||
e1beb1d3 | 1149 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1150 | kvm_load_ldt(svm->host.ldt); |
1151 | #ifdef CONFIG_X86_64 | |
1152 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1153 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1154 | load_gs_index(svm->host.gs); |
dacccfdd AK |
1155 | #else |
1156 | loadsegment(gs, svm->host.gs); | |
1157 | #endif | |
94dfbdb3 | 1158 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1159 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1160 | } |
1161 | ||
6aa8b732 AK |
1162 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1163 | { | |
a2fa3e9f | 1164 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1165 | } |
1166 | ||
1167 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1168 | { | |
a2fa3e9f | 1169 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1170 | } |
1171 | ||
6de4f3ad AK |
1172 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1173 | { | |
1174 | switch (reg) { | |
1175 | case VCPU_EXREG_PDPTR: | |
1176 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1177 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1178 | break; |
1179 | default: | |
1180 | BUG(); | |
1181 | } | |
1182 | } | |
1183 | ||
f0b85051 AG |
1184 | static void svm_set_vintr(struct vcpu_svm *svm) |
1185 | { | |
8a05a1b8 | 1186 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1187 | } |
1188 | ||
1189 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1190 | { | |
8a05a1b8 | 1191 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1192 | } |
1193 | ||
6aa8b732 AK |
1194 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1195 | { | |
a2fa3e9f | 1196 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1197 | |
1198 | switch (seg) { | |
1199 | case VCPU_SREG_CS: return &save->cs; | |
1200 | case VCPU_SREG_DS: return &save->ds; | |
1201 | case VCPU_SREG_ES: return &save->es; | |
1202 | case VCPU_SREG_FS: return &save->fs; | |
1203 | case VCPU_SREG_GS: return &save->gs; | |
1204 | case VCPU_SREG_SS: return &save->ss; | |
1205 | case VCPU_SREG_TR: return &save->tr; | |
1206 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1207 | } | |
1208 | BUG(); | |
8b6d44c7 | 1209 | return NULL; |
6aa8b732 AK |
1210 | } |
1211 | ||
1212 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1213 | { | |
1214 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1215 | ||
1216 | return s->base; | |
1217 | } | |
1218 | ||
1219 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1220 | struct kvm_segment *var, int seg) | |
1221 | { | |
1222 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1223 | ||
1224 | var->base = s->base; | |
1225 | var->limit = s->limit; | |
1226 | var->selector = s->selector; | |
1227 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1228 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1229 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1230 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1231 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1232 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1233 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1234 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1235 | |
e0231715 JR |
1236 | /* |
1237 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1238 | * for cross vendor migration purposes by "not present" |
1239 | */ | |
1240 | var->unusable = !var->present || (var->type == 0); | |
1241 | ||
1fbdc7a5 AP |
1242 | switch (seg) { |
1243 | case VCPU_SREG_CS: | |
1244 | /* | |
1245 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1246 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1247 | * Intel's VMENTRY has a check on the 'G' bit. | |
1248 | */ | |
25022acc | 1249 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1250 | break; |
1251 | case VCPU_SREG_TR: | |
1252 | /* | |
1253 | * Work around a bug where the busy flag in the tr selector | |
1254 | * isn't exposed | |
1255 | */ | |
c0d09828 | 1256 | var->type |= 0x2; |
1fbdc7a5 AP |
1257 | break; |
1258 | case VCPU_SREG_DS: | |
1259 | case VCPU_SREG_ES: | |
1260 | case VCPU_SREG_FS: | |
1261 | case VCPU_SREG_GS: | |
1262 | /* | |
1263 | * The accessed bit must always be set in the segment | |
1264 | * descriptor cache, although it can be cleared in the | |
1265 | * descriptor, the cached bit always remains at 1. Since | |
1266 | * Intel has a check on this, set it here to support | |
1267 | * cross-vendor migration. | |
1268 | */ | |
1269 | if (!var->unusable) | |
1270 | var->type |= 0x1; | |
1271 | break; | |
b586eb02 | 1272 | case VCPU_SREG_SS: |
e0231715 JR |
1273 | /* |
1274 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1275 | * descriptor is left as 1, although the whole segment has |
1276 | * been made unusable. Clear it here to pass an Intel VMX | |
1277 | * entry check when cross vendor migrating. | |
1278 | */ | |
1279 | if (var->unusable) | |
1280 | var->db = 0; | |
1281 | break; | |
1fbdc7a5 | 1282 | } |
6aa8b732 AK |
1283 | } |
1284 | ||
2e4d2653 IE |
1285 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1286 | { | |
1287 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1288 | ||
1289 | return save->cpl; | |
1290 | } | |
1291 | ||
89a27f4d | 1292 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1293 | { |
a2fa3e9f GH |
1294 | struct vcpu_svm *svm = to_svm(vcpu); |
1295 | ||
89a27f4d GN |
1296 | dt->size = svm->vmcb->save.idtr.limit; |
1297 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1298 | } |
1299 | ||
89a27f4d | 1300 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1301 | { |
a2fa3e9f GH |
1302 | struct vcpu_svm *svm = to_svm(vcpu); |
1303 | ||
89a27f4d GN |
1304 | svm->vmcb->save.idtr.limit = dt->size; |
1305 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1306 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1307 | } |
1308 | ||
89a27f4d | 1309 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1310 | { |
a2fa3e9f GH |
1311 | struct vcpu_svm *svm = to_svm(vcpu); |
1312 | ||
89a27f4d GN |
1313 | dt->size = svm->vmcb->save.gdtr.limit; |
1314 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1315 | } |
1316 | ||
89a27f4d | 1317 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1318 | { |
a2fa3e9f GH |
1319 | struct vcpu_svm *svm = to_svm(vcpu); |
1320 | ||
89a27f4d GN |
1321 | svm->vmcb->save.gdtr.limit = dt->size; |
1322 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1323 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1324 | } |
1325 | ||
e8467fda AK |
1326 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1327 | { | |
1328 | } | |
1329 | ||
aff48baa AK |
1330 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1331 | { | |
1332 | } | |
1333 | ||
25c4c276 | 1334 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1335 | { |
1336 | } | |
1337 | ||
d225157b AK |
1338 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1339 | { | |
1340 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1341 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1342 | ||
1343 | if (!svm->vcpu.fpu_active) | |
1344 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1345 | else | |
1346 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1347 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1348 | ||
dcca1a65 | 1349 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1350 | |
1351 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1352 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1353 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1354 | } else { |
4ee546b4 RJ |
1355 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1356 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1357 | } |
1358 | } | |
1359 | ||
6aa8b732 AK |
1360 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1361 | { | |
a2fa3e9f GH |
1362 | struct vcpu_svm *svm = to_svm(vcpu); |
1363 | ||
2030753d | 1364 | if (is_guest_mode(vcpu)) { |
7f5d8b56 JR |
1365 | /* |
1366 | * We are here because we run in nested mode, the host kvm | |
1367 | * intercepts cr0 writes but the l1 hypervisor does not. | |
1368 | * But the L1 hypervisor may intercept selective cr0 writes. | |
1369 | * This needs to be checked here. | |
1370 | */ | |
1371 | unsigned long old, new; | |
1372 | ||
1373 | /* Remove bits that would trigger a real cr0 write intercept */ | |
1374 | old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK; | |
1375 | new = cr0 & SVM_CR0_SELECTIVE_MASK; | |
1376 | ||
1377 | if (old == new) { | |
1378 | /* cr0 write with ts and mp unchanged */ | |
1379 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
cda00082 JR |
1380 | if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) { |
1381 | svm->nested.vmexit_rip = kvm_rip_read(vcpu); | |
1382 | svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
1383 | svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
7f5d8b56 | 1384 | return; |
cda00082 | 1385 | } |
7f5d8b56 JR |
1386 | } |
1387 | } | |
1388 | ||
05b3e0c2 | 1389 | #ifdef CONFIG_X86_64 |
f6801dff | 1390 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1391 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1392 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1393 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1394 | } |
1395 | ||
d77c26fc | 1396 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1397 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1398 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1399 | } |
1400 | } | |
1401 | #endif | |
ad312c7c | 1402 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1403 | |
1404 | if (!npt_enabled) | |
1405 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1406 | |
1407 | if (!vcpu->fpu_active) | |
334df50a | 1408 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1409 | /* |
1410 | * re-enable caching here because the QEMU bios | |
1411 | * does not do it - this results in some delay at | |
1412 | * reboot | |
1413 | */ | |
1414 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1415 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1416 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1417 | update_cr0_intercept(svm); |
6aa8b732 AK |
1418 | } |
1419 | ||
1420 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1421 | { | |
6394b649 | 1422 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1423 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1424 | ||
1425 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
f40f6a45 | 1426 | svm_flush_tlb(vcpu); |
6394b649 | 1427 | |
ec077263 JR |
1428 | vcpu->arch.cr4 = cr4; |
1429 | if (!npt_enabled) | |
1430 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1431 | cr4 |= host_cr4_mce; |
ec077263 | 1432 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1433 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
1434 | } |
1435 | ||
1436 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1437 | struct kvm_segment *var, int seg) | |
1438 | { | |
a2fa3e9f | 1439 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1440 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1441 | ||
1442 | s->base = var->base; | |
1443 | s->limit = var->limit; | |
1444 | s->selector = var->selector; | |
1445 | if (var->unusable) | |
1446 | s->attrib = 0; | |
1447 | else { | |
1448 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1449 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1450 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1451 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1452 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1453 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1454 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1455 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1456 | } | |
1457 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1458 | svm->vmcb->save.cpl |
1459 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1460 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1461 | ||
060d0c9a | 1462 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1463 | } |
1464 | ||
44c11430 | 1465 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1466 | { |
d0bfb940 JK |
1467 | struct vcpu_svm *svm = to_svm(vcpu); |
1468 | ||
18c918c5 JR |
1469 | clr_exception_intercept(svm, DB_VECTOR); |
1470 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1471 | |
6be7d306 | 1472 | if (svm->nmi_singlestep) |
18c918c5 | 1473 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1474 | |
d0bfb940 JK |
1475 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1476 | if (vcpu->guest_debug & | |
1477 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1478 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1479 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1480 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1481 | } else |
1482 | vcpu->guest_debug = 0; | |
44c11430 GN |
1483 | } |
1484 | ||
355be0b9 | 1485 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1486 | { |
44c11430 GN |
1487 | struct vcpu_svm *svm = to_svm(vcpu); |
1488 | ||
ae675ef0 JK |
1489 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1490 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1491 | else | |
1492 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1493 | ||
72214b96 JR |
1494 | mark_dirty(svm->vmcb, VMCB_DR); |
1495 | ||
355be0b9 | 1496 | update_db_intercept(vcpu); |
6aa8b732 AK |
1497 | } |
1498 | ||
0fe1e009 | 1499 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1500 | { |
0fe1e009 TH |
1501 | if (sd->next_asid > sd->max_asid) { |
1502 | ++sd->asid_generation; | |
1503 | sd->next_asid = 1; | |
a2fa3e9f | 1504 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1505 | } |
1506 | ||
0fe1e009 TH |
1507 | svm->asid_generation = sd->asid_generation; |
1508 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1509 | |
1510 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1511 | } |
1512 | ||
020df079 | 1513 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1514 | { |
42dbaa5a | 1515 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1516 | |
020df079 | 1517 | svm->vmcb->save.dr7 = value; |
72214b96 | 1518 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1519 | } |
1520 | ||
851ba692 | 1521 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1522 | { |
631bc487 | 1523 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1524 | u32 error_code; |
631bc487 | 1525 | int r = 1; |
6aa8b732 | 1526 | |
631bc487 GN |
1527 | switch (svm->apf_reason) { |
1528 | default: | |
1529 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1530 | |
631bc487 GN |
1531 | trace_kvm_page_fault(fault_address, error_code); |
1532 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1533 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1534 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1535 | svm->vmcb->control.insn_bytes, | |
1536 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1537 | break; |
1538 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1539 | svm->apf_reason = 0; | |
1540 | local_irq_disable(); | |
1541 | kvm_async_pf_task_wait(fault_address); | |
1542 | local_irq_enable(); | |
1543 | break; | |
1544 | case KVM_PV_REASON_PAGE_READY: | |
1545 | svm->apf_reason = 0; | |
1546 | local_irq_disable(); | |
1547 | kvm_async_pf_task_wake(fault_address); | |
1548 | local_irq_enable(); | |
1549 | break; | |
1550 | } | |
1551 | return r; | |
6aa8b732 AK |
1552 | } |
1553 | ||
851ba692 | 1554 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1555 | { |
851ba692 AK |
1556 | struct kvm_run *kvm_run = svm->vcpu.run; |
1557 | ||
d0bfb940 | 1558 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1559 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1560 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1561 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1562 | return 1; | |
1563 | } | |
44c11430 | 1564 | |
6be7d306 JK |
1565 | if (svm->nmi_singlestep) { |
1566 | svm->nmi_singlestep = false; | |
44c11430 GN |
1567 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1568 | svm->vmcb->save.rflags &= | |
1569 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1570 | update_db_intercept(&svm->vcpu); | |
1571 | } | |
1572 | ||
1573 | if (svm->vcpu.guest_debug & | |
e0231715 | 1574 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1575 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1576 | kvm_run->debug.arch.pc = | |
1577 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1578 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1579 | return 0; | |
1580 | } | |
1581 | ||
1582 | return 1; | |
d0bfb940 JK |
1583 | } |
1584 | ||
851ba692 | 1585 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1586 | { |
851ba692 AK |
1587 | struct kvm_run *kvm_run = svm->vcpu.run; |
1588 | ||
d0bfb940 JK |
1589 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1590 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1591 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1592 | return 0; | |
1593 | } | |
1594 | ||
851ba692 | 1595 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1596 | { |
1597 | int er; | |
1598 | ||
51d8b661 | 1599 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1600 | if (er != EMULATE_DONE) |
7ee5d940 | 1601 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1602 | return 1; |
1603 | } | |
1604 | ||
6b52d186 | 1605 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1606 | { |
6b52d186 | 1607 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1608 | |
18c918c5 | 1609 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1610 | |
e756fc62 | 1611 | svm->vcpu.fpu_active = 1; |
d225157b | 1612 | update_cr0_intercept(svm); |
6b52d186 | 1613 | } |
a2fa3e9f | 1614 | |
6b52d186 AK |
1615 | static int nm_interception(struct vcpu_svm *svm) |
1616 | { | |
1617 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1618 | return 1; |
7807fa6c AL |
1619 | } |
1620 | ||
67ec6607 JR |
1621 | static bool is_erratum_383(void) |
1622 | { | |
1623 | int err, i; | |
1624 | u64 value; | |
1625 | ||
1626 | if (!erratum_383_found) | |
1627 | return false; | |
1628 | ||
1629 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1630 | if (err) | |
1631 | return false; | |
1632 | ||
1633 | /* Bit 62 may or may not be set for this mce */ | |
1634 | value &= ~(1ULL << 62); | |
1635 | ||
1636 | if (value != 0xb600000000010015ULL) | |
1637 | return false; | |
1638 | ||
1639 | /* Clear MCi_STATUS registers */ | |
1640 | for (i = 0; i < 6; ++i) | |
1641 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1642 | ||
1643 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1644 | if (!err) { | |
1645 | u32 low, high; | |
1646 | ||
1647 | value &= ~(1ULL << 2); | |
1648 | low = lower_32_bits(value); | |
1649 | high = upper_32_bits(value); | |
1650 | ||
1651 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1652 | } | |
1653 | ||
1654 | /* Flush tlb to evict multi-match entries */ | |
1655 | __flush_tlb_all(); | |
1656 | ||
1657 | return true; | |
1658 | } | |
1659 | ||
fe5913e4 | 1660 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1661 | { |
67ec6607 JR |
1662 | if (is_erratum_383()) { |
1663 | /* | |
1664 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1665 | * guest. | |
1666 | */ | |
1667 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1668 | ||
a8eeb04a | 1669 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1670 | |
1671 | return; | |
1672 | } | |
1673 | ||
53371b50 JR |
1674 | /* |
1675 | * On an #MC intercept the MCE handler is not called automatically in | |
1676 | * the host. So do it by hand here. | |
1677 | */ | |
1678 | asm volatile ( | |
1679 | "int $0x12\n"); | |
1680 | /* not sure if we ever come back to this point */ | |
1681 | ||
fe5913e4 JR |
1682 | return; |
1683 | } | |
1684 | ||
1685 | static int mc_interception(struct vcpu_svm *svm) | |
1686 | { | |
53371b50 JR |
1687 | return 1; |
1688 | } | |
1689 | ||
851ba692 | 1690 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1691 | { |
851ba692 AK |
1692 | struct kvm_run *kvm_run = svm->vcpu.run; |
1693 | ||
46fe4ddd JR |
1694 | /* |
1695 | * VMCB is undefined after a SHUTDOWN intercept | |
1696 | * so reinitialize it. | |
1697 | */ | |
a2fa3e9f | 1698 | clear_page(svm->vmcb); |
e6101a96 | 1699 | init_vmcb(svm); |
46fe4ddd JR |
1700 | |
1701 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1702 | return 0; | |
1703 | } | |
1704 | ||
851ba692 | 1705 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1706 | { |
cf8f70bf | 1707 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1708 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1709 | int size, in, string; |
039576c0 | 1710 | unsigned port; |
6aa8b732 | 1711 | |
e756fc62 | 1712 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1713 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1714 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1715 | if (string || in) |
51d8b661 | 1716 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1717 | |
039576c0 AK |
1718 | port = io_info >> 16; |
1719 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1720 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1721 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1722 | |
1723 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1724 | } |
1725 | ||
851ba692 | 1726 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1727 | { |
1728 | return 1; | |
1729 | } | |
1730 | ||
851ba692 | 1731 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1732 | { |
1733 | ++svm->vcpu.stat.irq_exits; | |
1734 | return 1; | |
1735 | } | |
1736 | ||
851ba692 | 1737 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1738 | { |
1739 | return 1; | |
1740 | } | |
1741 | ||
851ba692 | 1742 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1743 | { |
5fdbf976 | 1744 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1745 | skip_emulated_instruction(&svm->vcpu); |
1746 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1747 | } |
1748 | ||
851ba692 | 1749 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1750 | { |
5fdbf976 | 1751 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1752 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1753 | kvm_emulate_hypercall(&svm->vcpu); |
1754 | return 1; | |
02e235bc AK |
1755 | } |
1756 | ||
5bd2edc3 JR |
1757 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1758 | { | |
1759 | struct vcpu_svm *svm = to_svm(vcpu); | |
1760 | ||
1761 | return svm->nested.nested_cr3; | |
1762 | } | |
1763 | ||
1764 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, | |
1765 | unsigned long root) | |
1766 | { | |
1767 | struct vcpu_svm *svm = to_svm(vcpu); | |
1768 | ||
1769 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1770 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1771 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1772 | } |
1773 | ||
6389ee94 AK |
1774 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1775 | struct x86_exception *fault) | |
5bd2edc3 JR |
1776 | { |
1777 | struct vcpu_svm *svm = to_svm(vcpu); | |
1778 | ||
1779 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1780 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1781 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1782 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1783 | |
1784 | nested_svm_vmexit(svm); | |
1785 | } | |
1786 | ||
4b16184c JR |
1787 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1788 | { | |
1789 | int r; | |
1790 | ||
1791 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1792 | ||
1793 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1794 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
1795 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; | |
1796 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1797 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1798 | ||
1799 | return r; | |
1800 | } | |
1801 | ||
1802 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1803 | { | |
1804 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1805 | } | |
1806 | ||
c0725420 AG |
1807 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1808 | { | |
f6801dff | 1809 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1810 | || !is_paging(&svm->vcpu)) { |
1811 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1812 | return 1; | |
1813 | } | |
1814 | ||
1815 | if (svm->vmcb->save.cpl) { | |
1816 | kvm_inject_gp(&svm->vcpu, 0); | |
1817 | return 1; | |
1818 | } | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
cf74a78b AG |
1823 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1824 | bool has_error_code, u32 error_code) | |
1825 | { | |
b8e88bc8 JR |
1826 | int vmexit; |
1827 | ||
2030753d | 1828 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1829 | return 0; |
cf74a78b | 1830 | |
0295ad7d JR |
1831 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1832 | svm->vmcb->control.exit_code_hi = 0; | |
1833 | svm->vmcb->control.exit_info_1 = error_code; | |
1834 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1835 | ||
b8e88bc8 JR |
1836 | vmexit = nested_svm_intercept(svm); |
1837 | if (vmexit == NESTED_EXIT_DONE) | |
1838 | svm->nested.exit_required = true; | |
1839 | ||
1840 | return vmexit; | |
cf74a78b AG |
1841 | } |
1842 | ||
8fe54654 JR |
1843 | /* This function returns true if it is save to enable the irq window */ |
1844 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1845 | { |
2030753d | 1846 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 1847 | return true; |
cf74a78b | 1848 | |
26666957 | 1849 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1850 | return true; |
cf74a78b | 1851 | |
26666957 | 1852 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1853 | return false; |
cf74a78b | 1854 | |
a0a07cd2 GN |
1855 | /* |
1856 | * if vmexit was already requested (by intercepted exception | |
1857 | * for instance) do not overwrite it with "external interrupt" | |
1858 | * vmexit. | |
1859 | */ | |
1860 | if (svm->nested.exit_required) | |
1861 | return false; | |
1862 | ||
197717d5 JR |
1863 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1864 | svm->vmcb->control.exit_info_1 = 0; | |
1865 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1866 | |
cd3ff653 JR |
1867 | if (svm->nested.intercept & 1ULL) { |
1868 | /* | |
1869 | * The #vmexit can't be emulated here directly because this | |
1870 | * code path runs with irqs and preemtion disabled. A | |
1871 | * #vmexit emulation might sleep. Only signal request for | |
1872 | * the #vmexit here. | |
1873 | */ | |
1874 | svm->nested.exit_required = true; | |
236649de | 1875 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 1876 | return false; |
cf74a78b AG |
1877 | } |
1878 | ||
8fe54654 | 1879 | return true; |
cf74a78b AG |
1880 | } |
1881 | ||
887f500c JR |
1882 | /* This function returns true if it is save to enable the nmi window */ |
1883 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1884 | { | |
2030753d | 1885 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
1886 | return true; |
1887 | ||
1888 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1889 | return true; | |
1890 | ||
1891 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1892 | svm->nested.exit_required = true; | |
1893 | ||
1894 | return false; | |
cf74a78b AG |
1895 | } |
1896 | ||
7597f129 | 1897 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1898 | { |
1899 | struct page *page; | |
1900 | ||
6c3bd3d7 JR |
1901 | might_sleep(); |
1902 | ||
34f80cfa | 1903 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1904 | if (is_error_page(page)) |
1905 | goto error; | |
1906 | ||
7597f129 JR |
1907 | *_page = page; |
1908 | ||
1909 | return kmap(page); | |
34f80cfa JR |
1910 | |
1911 | error: | |
1912 | kvm_release_page_clean(page); | |
1913 | kvm_inject_gp(&svm->vcpu, 0); | |
1914 | ||
1915 | return NULL; | |
1916 | } | |
1917 | ||
7597f129 | 1918 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1919 | { |
7597f129 | 1920 | kunmap(page); |
34f80cfa JR |
1921 | kvm_release_page_dirty(page); |
1922 | } | |
34f80cfa | 1923 | |
ce2ac085 JR |
1924 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
1925 | { | |
1926 | unsigned port; | |
1927 | u8 val, bit; | |
1928 | u64 gpa; | |
34f80cfa | 1929 | |
ce2ac085 JR |
1930 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
1931 | return NESTED_EXIT_HOST; | |
34f80cfa | 1932 | |
ce2ac085 JR |
1933 | port = svm->vmcb->control.exit_info_1 >> 16; |
1934 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1935 | bit = port % 8; | |
1936 | val = 0; | |
1937 | ||
1938 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1939 | val &= (1 << bit); | |
1940 | ||
1941 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
1942 | } |
1943 | ||
d2477826 | 1944 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1945 | { |
0d6b3537 JR |
1946 | u32 offset, msr, value; |
1947 | int write, mask; | |
4c2161ae | 1948 | |
3d62d9aa | 1949 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 1950 | return NESTED_EXIT_HOST; |
3d62d9aa | 1951 | |
0d6b3537 JR |
1952 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1953 | offset = svm_msrpm_offset(msr); | |
1954 | write = svm->vmcb->control.exit_info_1 & 1; | |
1955 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 1956 | |
0d6b3537 JR |
1957 | if (offset == MSR_INVALID) |
1958 | return NESTED_EXIT_DONE; | |
4c2161ae | 1959 | |
0d6b3537 JR |
1960 | /* Offset is in 32 bit units but need in 8 bit units */ |
1961 | offset *= 4; | |
4c2161ae | 1962 | |
0d6b3537 JR |
1963 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
1964 | return NESTED_EXIT_DONE; | |
3d62d9aa | 1965 | |
0d6b3537 | 1966 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
1967 | } |
1968 | ||
410e4d57 | 1969 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1970 | { |
cf74a78b | 1971 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1972 | |
410e4d57 JR |
1973 | switch (exit_code) { |
1974 | case SVM_EXIT_INTR: | |
1975 | case SVM_EXIT_NMI: | |
ff47a49b | 1976 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 1977 | return NESTED_EXIT_HOST; |
410e4d57 | 1978 | case SVM_EXIT_NPF: |
e0231715 | 1979 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1980 | if (npt_enabled) |
1981 | return NESTED_EXIT_HOST; | |
1982 | break; | |
410e4d57 | 1983 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
1984 | /* When we're shadowing, trap PFs, but not async PF */ |
1985 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
1986 | return NESTED_EXIT_HOST; |
1987 | break; | |
66a562f7 JR |
1988 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
1989 | nm_interception(svm); | |
1990 | break; | |
410e4d57 JR |
1991 | default: |
1992 | break; | |
cf74a78b AG |
1993 | } |
1994 | ||
410e4d57 JR |
1995 | return NESTED_EXIT_CONTINUE; |
1996 | } | |
1997 | ||
1998 | /* | |
1999 | * If this function returns true, this #vmexit was already handled | |
2000 | */ | |
b8e88bc8 | 2001 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2002 | { |
2003 | u32 exit_code = svm->vmcb->control.exit_code; | |
2004 | int vmexit = NESTED_EXIT_HOST; | |
2005 | ||
cf74a78b | 2006 | switch (exit_code) { |
9c4e40b9 | 2007 | case SVM_EXIT_MSR: |
3d62d9aa | 2008 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2009 | break; |
ce2ac085 JR |
2010 | case SVM_EXIT_IOIO: |
2011 | vmexit = nested_svm_intercept_ioio(svm); | |
2012 | break; | |
4ee546b4 RJ |
2013 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2014 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2015 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2016 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2017 | break; |
2018 | } | |
3aed041a JR |
2019 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2020 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2021 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2022 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2023 | break; |
2024 | } | |
2025 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2026 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2027 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2028 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2029 | /* async page fault always cause vmexit */ |
2030 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2031 | svm->apf_reason != 0) | |
2032 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2033 | break; |
2034 | } | |
228070b1 JR |
2035 | case SVM_EXIT_ERR: { |
2036 | vmexit = NESTED_EXIT_DONE; | |
2037 | break; | |
2038 | } | |
cf74a78b AG |
2039 | default: { |
2040 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2041 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2042 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2043 | } |
2044 | } | |
2045 | ||
b8e88bc8 JR |
2046 | return vmexit; |
2047 | } | |
2048 | ||
2049 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2050 | { | |
2051 | int vmexit; | |
2052 | ||
2053 | vmexit = nested_svm_intercept(svm); | |
2054 | ||
2055 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2056 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2057 | |
2058 | return vmexit; | |
cf74a78b AG |
2059 | } |
2060 | ||
0460a979 JR |
2061 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2062 | { | |
2063 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2064 | struct vmcb_control_area *from = &from_vmcb->control; | |
2065 | ||
4ee546b4 | 2066 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2067 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2068 | dst->intercept_exceptions = from->intercept_exceptions; |
2069 | dst->intercept = from->intercept; | |
2070 | dst->iopm_base_pa = from->iopm_base_pa; | |
2071 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2072 | dst->tsc_offset = from->tsc_offset; | |
2073 | dst->asid = from->asid; | |
2074 | dst->tlb_ctl = from->tlb_ctl; | |
2075 | dst->int_ctl = from->int_ctl; | |
2076 | dst->int_vector = from->int_vector; | |
2077 | dst->int_state = from->int_state; | |
2078 | dst->exit_code = from->exit_code; | |
2079 | dst->exit_code_hi = from->exit_code_hi; | |
2080 | dst->exit_info_1 = from->exit_info_1; | |
2081 | dst->exit_info_2 = from->exit_info_2; | |
2082 | dst->exit_int_info = from->exit_int_info; | |
2083 | dst->exit_int_info_err = from->exit_int_info_err; | |
2084 | dst->nested_ctl = from->nested_ctl; | |
2085 | dst->event_inj = from->event_inj; | |
2086 | dst->event_inj_err = from->event_inj_err; | |
2087 | dst->nested_cr3 = from->nested_cr3; | |
2088 | dst->lbr_ctl = from->lbr_ctl; | |
2089 | } | |
2090 | ||
34f80cfa | 2091 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2092 | { |
34f80cfa | 2093 | struct vmcb *nested_vmcb; |
e6aa9abd | 2094 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2095 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2096 | struct page *page; |
cf74a78b | 2097 | |
17897f36 JR |
2098 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2099 | vmcb->control.exit_info_1, | |
2100 | vmcb->control.exit_info_2, | |
2101 | vmcb->control.exit_int_info, | |
2102 | vmcb->control.exit_int_info_err); | |
2103 | ||
7597f129 | 2104 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2105 | if (!nested_vmcb) |
2106 | return 1; | |
2107 | ||
2030753d JR |
2108 | /* Exit Guest-Mode */ |
2109 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2110 | svm->nested.vmcb = 0; |
2111 | ||
cf74a78b | 2112 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2113 | disable_gif(svm); |
2114 | ||
2115 | nested_vmcb->save.es = vmcb->save.es; | |
2116 | nested_vmcb->save.cs = vmcb->save.cs; | |
2117 | nested_vmcb->save.ss = vmcb->save.ss; | |
2118 | nested_vmcb->save.ds = vmcb->save.ds; | |
2119 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2120 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2121 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2122 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2123 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2124 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2125 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
33740e40 JR |
2126 | nested_vmcb->save.rflags = vmcb->save.rflags; |
2127 | nested_vmcb->save.rip = vmcb->save.rip; | |
2128 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2129 | nested_vmcb->save.rax = vmcb->save.rax; | |
2130 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2131 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2132 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2133 | ||
2134 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2135 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2136 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2137 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2138 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2139 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2140 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2141 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2142 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2143 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2144 | |
2145 | /* | |
2146 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2147 | * to make sure that we do not lose injected events. So check event_inj | |
2148 | * here and copy it to exit_int_info if it is valid. | |
2149 | * Exit_int_info and event_inj can't be both valid because the case | |
2150 | * below only happens on a VMRUN instruction intercept which has | |
2151 | * no valid exit_int_info set. | |
2152 | */ | |
2153 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2154 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2155 | ||
2156 | nc->exit_int_info = vmcb->control.event_inj; | |
2157 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2158 | } | |
2159 | ||
33740e40 JR |
2160 | nested_vmcb->control.tlb_ctl = 0; |
2161 | nested_vmcb->control.event_inj = 0; | |
2162 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2163 | |
2164 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2165 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2166 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2167 | ||
cf74a78b | 2168 | /* Restore the original control entries */ |
0460a979 | 2169 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2170 | |
219b65dc AG |
2171 | kvm_clear_exception_queue(&svm->vcpu); |
2172 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2173 | |
4b16184c JR |
2174 | svm->nested.nested_cr3 = 0; |
2175 | ||
cf74a78b AG |
2176 | /* Restore selected save entries */ |
2177 | svm->vmcb->save.es = hsave->save.es; | |
2178 | svm->vmcb->save.cs = hsave->save.cs; | |
2179 | svm->vmcb->save.ss = hsave->save.ss; | |
2180 | svm->vmcb->save.ds = hsave->save.ds; | |
2181 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2182 | svm->vmcb->save.idtr = hsave->save.idtr; | |
2183 | svm->vmcb->save.rflags = hsave->save.rflags; | |
2184 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
2185 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2186 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2187 | if (npt_enabled) { | |
2188 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2189 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2190 | } else { | |
2390218b | 2191 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2192 | } |
2193 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2194 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2195 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2196 | svm->vmcb->save.dr7 = 0; | |
2197 | svm->vmcb->save.cpl = 0; | |
2198 | svm->vmcb->control.exit_int_info = 0; | |
2199 | ||
8d28fec4 RJ |
2200 | mark_all_dirty(svm->vmcb); |
2201 | ||
7597f129 | 2202 | nested_svm_unmap(page); |
cf74a78b | 2203 | |
4b16184c | 2204 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2205 | kvm_mmu_reset_context(&svm->vcpu); |
2206 | kvm_mmu_load(&svm->vcpu); | |
2207 | ||
2208 | return 0; | |
2209 | } | |
3d6368ef | 2210 | |
9738b2c9 | 2211 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2212 | { |
323c3d80 JR |
2213 | /* |
2214 | * This function merges the msr permission bitmaps of kvm and the | |
2215 | * nested vmcb. It is omptimized in that it only merges the parts where | |
2216 | * the kvm msr permission bitmap may contain zero bits | |
2217 | */ | |
3d6368ef | 2218 | int i; |
9738b2c9 | 2219 | |
323c3d80 JR |
2220 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2221 | return true; | |
9738b2c9 | 2222 | |
323c3d80 JR |
2223 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2224 | u32 value, p; | |
2225 | u64 offset; | |
9738b2c9 | 2226 | |
323c3d80 JR |
2227 | if (msrpm_offsets[i] == 0xffffffff) |
2228 | break; | |
3d6368ef | 2229 | |
0d6b3537 JR |
2230 | p = msrpm_offsets[i]; |
2231 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2232 | |
2233 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2234 | return false; | |
2235 | ||
2236 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2237 | } | |
3d6368ef | 2238 | |
323c3d80 | 2239 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2240 | |
2241 | return true; | |
3d6368ef AG |
2242 | } |
2243 | ||
52c65a30 JR |
2244 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2245 | { | |
2246 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2247 | return false; | |
2248 | ||
dbe77584 JR |
2249 | if (vmcb->control.asid == 0) |
2250 | return false; | |
2251 | ||
4b16184c JR |
2252 | if (vmcb->control.nested_ctl && !npt_enabled) |
2253 | return false; | |
2254 | ||
52c65a30 JR |
2255 | return true; |
2256 | } | |
2257 | ||
9738b2c9 | 2258 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2259 | { |
9738b2c9 | 2260 | struct vmcb *nested_vmcb; |
e6aa9abd | 2261 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2262 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2263 | struct page *page; |
06fc7772 | 2264 | u64 vmcb_gpa; |
3d6368ef | 2265 | |
06fc7772 | 2266 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2267 | |
7597f129 | 2268 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2269 | if (!nested_vmcb) |
2270 | return false; | |
2271 | ||
52c65a30 JR |
2272 | if (!nested_vmcb_checks(nested_vmcb)) { |
2273 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2274 | nested_vmcb->control.exit_code_hi = 0; | |
2275 | nested_vmcb->control.exit_info_1 = 0; | |
2276 | nested_vmcb->control.exit_info_2 = 0; | |
2277 | ||
2278 | nested_svm_unmap(page); | |
2279 | ||
2280 | return false; | |
2281 | } | |
2282 | ||
b75f4eb3 | 2283 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2284 | nested_vmcb->save.rip, |
2285 | nested_vmcb->control.int_ctl, | |
2286 | nested_vmcb->control.event_inj, | |
2287 | nested_vmcb->control.nested_ctl); | |
2288 | ||
4ee546b4 RJ |
2289 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2290 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2291 | nested_vmcb->control.intercept_exceptions, |
2292 | nested_vmcb->control.intercept); | |
2293 | ||
3d6368ef | 2294 | /* Clear internal status */ |
219b65dc AG |
2295 | kvm_clear_exception_queue(&svm->vcpu); |
2296 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2297 | |
e0231715 JR |
2298 | /* |
2299 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2300 | * restore everything when a VMEXIT occurs | |
2301 | */ | |
defbba56 JR |
2302 | hsave->save.es = vmcb->save.es; |
2303 | hsave->save.cs = vmcb->save.cs; | |
2304 | hsave->save.ss = vmcb->save.ss; | |
2305 | hsave->save.ds = vmcb->save.ds; | |
2306 | hsave->save.gdtr = vmcb->save.gdtr; | |
2307 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2308 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2309 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 JR |
2310 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
2311 | hsave->save.rflags = vmcb->save.rflags; | |
b75f4eb3 | 2312 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2313 | hsave->save.rsp = vmcb->save.rsp; |
2314 | hsave->save.rax = vmcb->save.rax; | |
2315 | if (npt_enabled) | |
2316 | hsave->save.cr3 = vmcb->save.cr3; | |
2317 | else | |
9f8fe504 | 2318 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2319 | |
0460a979 | 2320 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
2321 | |
2322 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
2323 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
2324 | else | |
2325 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2326 | ||
4b16184c JR |
2327 | if (nested_vmcb->control.nested_ctl) { |
2328 | kvm_mmu_unload(&svm->vcpu); | |
2329 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2330 | nested_svm_init_mmu_context(&svm->vcpu); | |
2331 | } | |
2332 | ||
3d6368ef AG |
2333 | /* Load the nested guest state */ |
2334 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2335 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2336 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2337 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2338 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2339 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
2340 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
2341 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
2342 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2343 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2344 | if (npt_enabled) { | |
2345 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2346 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2347 | } else |
2390218b | 2348 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2349 | |
2350 | /* Guest paging mode is active - reset mmu */ | |
2351 | kvm_mmu_reset_context(&svm->vcpu); | |
2352 | ||
defbba56 | 2353 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2354 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2355 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2356 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2357 | |
3d6368ef AG |
2358 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2359 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2360 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2361 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2362 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2363 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2364 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2365 | ||
f7138538 | 2366 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2367 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2368 | |
aad42c64 | 2369 | /* cache intercepts */ |
4ee546b4 | 2370 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2371 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2372 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2373 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2374 | ||
f40f6a45 | 2375 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2376 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2377 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2378 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2379 | else | |
2380 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2381 | ||
88ab24ad JR |
2382 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2383 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2384 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2385 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2386 | } |
2387 | ||
0d945bd9 | 2388 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2389 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2390 | |
88ab24ad | 2391 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2392 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2393 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2394 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2395 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2396 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2397 | ||
7597f129 | 2398 | nested_svm_unmap(page); |
9738b2c9 | 2399 | |
2030753d JR |
2400 | /* Enter Guest-Mode */ |
2401 | enter_guest_mode(&svm->vcpu); | |
2402 | ||
384c6368 JR |
2403 | /* |
2404 | * Merge guest and host intercepts - must be called with vcpu in | |
2405 | * guest-mode to take affect here | |
2406 | */ | |
2407 | recalc_intercepts(svm); | |
2408 | ||
06fc7772 | 2409 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2410 | |
2af9194d | 2411 | enable_gif(svm); |
3d6368ef | 2412 | |
8d28fec4 RJ |
2413 | mark_all_dirty(svm->vmcb); |
2414 | ||
9738b2c9 | 2415 | return true; |
3d6368ef AG |
2416 | } |
2417 | ||
9966bf68 | 2418 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2419 | { |
2420 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2421 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2422 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2423 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2424 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2425 | to_vmcb->save.star = from_vmcb->save.star; | |
2426 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2427 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2428 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2429 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2430 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2431 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2432 | } |
2433 | ||
851ba692 | 2434 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2435 | { |
9966bf68 | 2436 | struct vmcb *nested_vmcb; |
7597f129 | 2437 | struct page *page; |
9966bf68 | 2438 | |
5542675b AG |
2439 | if (nested_svm_check_permissions(svm)) |
2440 | return 1; | |
2441 | ||
2442 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2443 | skip_emulated_instruction(&svm->vcpu); | |
2444 | ||
7597f129 | 2445 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2446 | if (!nested_vmcb) |
2447 | return 1; | |
2448 | ||
2449 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 2450 | nested_svm_unmap(page); |
5542675b AG |
2451 | |
2452 | return 1; | |
2453 | } | |
2454 | ||
851ba692 | 2455 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2456 | { |
9966bf68 | 2457 | struct vmcb *nested_vmcb; |
7597f129 | 2458 | struct page *page; |
9966bf68 | 2459 | |
5542675b AG |
2460 | if (nested_svm_check_permissions(svm)) |
2461 | return 1; | |
2462 | ||
2463 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2464 | skip_emulated_instruction(&svm->vcpu); | |
2465 | ||
7597f129 | 2466 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2467 | if (!nested_vmcb) |
2468 | return 1; | |
2469 | ||
2470 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 2471 | nested_svm_unmap(page); |
5542675b AG |
2472 | |
2473 | return 1; | |
2474 | } | |
2475 | ||
851ba692 | 2476 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2477 | { |
3d6368ef AG |
2478 | if (nested_svm_check_permissions(svm)) |
2479 | return 1; | |
2480 | ||
b75f4eb3 RJ |
2481 | /* Save rip after vmrun instruction */ |
2482 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2483 | |
9738b2c9 | 2484 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2485 | return 1; |
2486 | ||
9738b2c9 | 2487 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2488 | goto failed; |
2489 | ||
2490 | return 1; | |
2491 | ||
2492 | failed: | |
2493 | ||
2494 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2495 | svm->vmcb->control.exit_code_hi = 0; | |
2496 | svm->vmcb->control.exit_info_1 = 0; | |
2497 | svm->vmcb->control.exit_info_2 = 0; | |
2498 | ||
2499 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2500 | |
2501 | return 1; | |
2502 | } | |
2503 | ||
851ba692 | 2504 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2505 | { |
2506 | if (nested_svm_check_permissions(svm)) | |
2507 | return 1; | |
2508 | ||
2509 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2510 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2511 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2512 | |
2af9194d | 2513 | enable_gif(svm); |
1371d904 AG |
2514 | |
2515 | return 1; | |
2516 | } | |
2517 | ||
851ba692 | 2518 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2519 | { |
2520 | if (nested_svm_check_permissions(svm)) | |
2521 | return 1; | |
2522 | ||
2523 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2524 | skip_emulated_instruction(&svm->vcpu); | |
2525 | ||
2af9194d | 2526 | disable_gif(svm); |
1371d904 AG |
2527 | |
2528 | /* After a CLGI no interrupts should come */ | |
2529 | svm_clear_vintr(svm); | |
2530 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2531 | ||
decdbf6a JR |
2532 | mark_dirty(svm->vmcb, VMCB_INTR); |
2533 | ||
1371d904 AG |
2534 | return 1; |
2535 | } | |
2536 | ||
851ba692 | 2537 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2538 | { |
2539 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2540 | |
ec1ff790 JR |
2541 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2542 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2543 | ||
ff092385 AG |
2544 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2545 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2546 | ||
2547 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2548 | skip_emulated_instruction(&svm->vcpu); | |
2549 | return 1; | |
2550 | } | |
2551 | ||
532a46b9 JR |
2552 | static int skinit_interception(struct vcpu_svm *svm) |
2553 | { | |
2554 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2555 | ||
2556 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2557 | return 1; | |
2558 | } | |
2559 | ||
81dd35d4 JR |
2560 | static int xsetbv_interception(struct vcpu_svm *svm) |
2561 | { | |
2562 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2563 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2564 | ||
2565 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2566 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2567 | skip_emulated_instruction(&svm->vcpu); | |
2568 | } | |
2569 | ||
2570 | return 1; | |
2571 | } | |
2572 | ||
851ba692 | 2573 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2574 | { |
7ee5d940 | 2575 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2576 | return 1; |
2577 | } | |
2578 | ||
851ba692 | 2579 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2580 | { |
37817f29 | 2581 | u16 tss_selector; |
64a7ec06 GN |
2582 | int reason; |
2583 | int int_type = svm->vmcb->control.exit_int_info & | |
2584 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2585 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2586 | uint32_t type = |
2587 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2588 | uint32_t idt_v = | |
2589 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2590 | bool has_error_code = false; |
2591 | u32 error_code = 0; | |
37817f29 IE |
2592 | |
2593 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2594 | |
37817f29 IE |
2595 | if (svm->vmcb->control.exit_info_2 & |
2596 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2597 | reason = TASK_SWITCH_IRET; |
2598 | else if (svm->vmcb->control.exit_info_2 & | |
2599 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2600 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2601 | else if (idt_v) |
64a7ec06 GN |
2602 | reason = TASK_SWITCH_GATE; |
2603 | else | |
2604 | reason = TASK_SWITCH_CALL; | |
2605 | ||
fe8e7f83 GN |
2606 | if (reason == TASK_SWITCH_GATE) { |
2607 | switch (type) { | |
2608 | case SVM_EXITINTINFO_TYPE_NMI: | |
2609 | svm->vcpu.arch.nmi_injected = false; | |
2610 | break; | |
2611 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2612 | if (svm->vmcb->control.exit_info_2 & |
2613 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2614 | has_error_code = true; | |
2615 | error_code = | |
2616 | (u32)svm->vmcb->control.exit_info_2; | |
2617 | } | |
fe8e7f83 GN |
2618 | kvm_clear_exception_queue(&svm->vcpu); |
2619 | break; | |
2620 | case SVM_EXITINTINFO_TYPE_INTR: | |
2621 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2622 | break; | |
2623 | default: | |
2624 | break; | |
2625 | } | |
2626 | } | |
64a7ec06 | 2627 | |
8317c298 GN |
2628 | if (reason != TASK_SWITCH_GATE || |
2629 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2630 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2631 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2632 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2633 | |
acb54517 GN |
2634 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2635 | has_error_code, error_code) == EMULATE_FAIL) { | |
2636 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2637 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2638 | svm->vcpu.run->internal.ndata = 0; | |
2639 | return 0; | |
2640 | } | |
2641 | return 1; | |
6aa8b732 AK |
2642 | } |
2643 | ||
851ba692 | 2644 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2645 | { |
5fdbf976 | 2646 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2647 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2648 | return 1; |
6aa8b732 AK |
2649 | } |
2650 | ||
851ba692 | 2651 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2652 | { |
2653 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2654 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2655 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2656 | return 1; |
2657 | } | |
2658 | ||
851ba692 | 2659 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2660 | { |
df4f3108 AP |
2661 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2662 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2663 | ||
2664 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2665 | skip_emulated_instruction(&svm->vcpu); | |
2666 | return 1; | |
a7052897 MT |
2667 | } |
2668 | ||
851ba692 | 2669 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2670 | { |
51d8b661 | 2671 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2672 | } |
2673 | ||
7ff76d58 AP |
2674 | #define CR_VALID (1ULL << 63) |
2675 | ||
2676 | static int cr_interception(struct vcpu_svm *svm) | |
2677 | { | |
2678 | int reg, cr; | |
2679 | unsigned long val; | |
2680 | int err; | |
2681 | ||
2682 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2683 | return emulate_on_interception(svm); | |
2684 | ||
2685 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2686 | return emulate_on_interception(svm); | |
2687 | ||
2688 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2689 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2690 | ||
2691 | err = 0; | |
2692 | if (cr >= 16) { /* mov to cr */ | |
2693 | cr -= 16; | |
2694 | val = kvm_register_read(&svm->vcpu, reg); | |
2695 | switch (cr) { | |
2696 | case 0: | |
2697 | err = kvm_set_cr0(&svm->vcpu, val); | |
2698 | break; | |
2699 | case 3: | |
2700 | err = kvm_set_cr3(&svm->vcpu, val); | |
2701 | break; | |
2702 | case 4: | |
2703 | err = kvm_set_cr4(&svm->vcpu, val); | |
2704 | break; | |
2705 | case 8: | |
2706 | err = kvm_set_cr8(&svm->vcpu, val); | |
2707 | break; | |
2708 | default: | |
2709 | WARN(1, "unhandled write to CR%d", cr); | |
2710 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2711 | return 1; | |
2712 | } | |
2713 | } else { /* mov from cr */ | |
2714 | switch (cr) { | |
2715 | case 0: | |
2716 | val = kvm_read_cr0(&svm->vcpu); | |
2717 | break; | |
2718 | case 2: | |
2719 | val = svm->vcpu.arch.cr2; | |
2720 | break; | |
2721 | case 3: | |
9f8fe504 | 2722 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2723 | break; |
2724 | case 4: | |
2725 | val = kvm_read_cr4(&svm->vcpu); | |
2726 | break; | |
2727 | case 8: | |
2728 | val = kvm_get_cr8(&svm->vcpu); | |
2729 | break; | |
2730 | default: | |
2731 | WARN(1, "unhandled read from CR%d", cr); | |
2732 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2733 | return 1; | |
2734 | } | |
2735 | kvm_register_write(&svm->vcpu, reg, val); | |
2736 | } | |
2737 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2738 | ||
2739 | return 1; | |
2740 | } | |
2741 | ||
cda00082 JR |
2742 | static int cr0_write_interception(struct vcpu_svm *svm) |
2743 | { | |
2744 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
2745 | int r; | |
2746 | ||
7ff76d58 | 2747 | r = cr_interception(svm); |
cda00082 JR |
2748 | |
2749 | if (svm->nested.vmexit_rip) { | |
2750 | kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip); | |
2751 | kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp); | |
2752 | kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax); | |
2753 | svm->nested.vmexit_rip = 0; | |
2754 | } | |
2755 | ||
7ff76d58 | 2756 | return r; |
cda00082 JR |
2757 | } |
2758 | ||
cae3797a AP |
2759 | static int dr_interception(struct vcpu_svm *svm) |
2760 | { | |
2761 | int reg, dr; | |
2762 | unsigned long val; | |
2763 | int err; | |
2764 | ||
2765 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2766 | return emulate_on_interception(svm); | |
2767 | ||
2768 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2769 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2770 | ||
2771 | if (dr >= 16) { /* mov to DRn */ | |
2772 | val = kvm_register_read(&svm->vcpu, reg); | |
2773 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2774 | } else { | |
2775 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
2776 | if (!err) | |
2777 | kvm_register_write(&svm->vcpu, reg, val); | |
2778 | } | |
2779 | ||
2780 | return 1; | |
2781 | } | |
2782 | ||
851ba692 | 2783 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2784 | { |
851ba692 | 2785 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2786 | int r; |
851ba692 | 2787 | |
0a5fff19 GN |
2788 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2789 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2790 | r = cr_interception(svm); |
95ba8273 | 2791 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2792 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
7ff76d58 | 2793 | return r; |
95ba8273 | 2794 | } |
0a5fff19 | 2795 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 2796 | return r; |
1d075434 JR |
2797 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2798 | return 0; | |
2799 | } | |
2800 | ||
6aa8b732 AK |
2801 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2802 | { | |
a2fa3e9f GH |
2803 | struct vcpu_svm *svm = to_svm(vcpu); |
2804 | ||
6aa8b732 | 2805 | switch (ecx) { |
af24a4e4 | 2806 | case MSR_IA32_TSC: { |
4cc70310 | 2807 | struct vmcb *vmcb = get_host_vmcb(svm); |
6aa8b732 | 2808 | |
4cc70310 | 2809 | *data = vmcb->control.tsc_offset + native_read_tsc(); |
6aa8b732 AK |
2810 | break; |
2811 | } | |
8c06585d | 2812 | case MSR_STAR: |
a2fa3e9f | 2813 | *data = svm->vmcb->save.star; |
6aa8b732 | 2814 | break; |
0e859cac | 2815 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2816 | case MSR_LSTAR: |
a2fa3e9f | 2817 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2818 | break; |
2819 | case MSR_CSTAR: | |
a2fa3e9f | 2820 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2821 | break; |
2822 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2823 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2824 | break; |
2825 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2826 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2827 | break; |
2828 | #endif | |
2829 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2830 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2831 | break; |
2832 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2833 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2834 | break; |
2835 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2836 | *data = svm->sysenter_esp; |
6aa8b732 | 2837 | break; |
e0231715 JR |
2838 | /* |
2839 | * Nobody will change the following 5 values in the VMCB so we can | |
2840 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2841 | * implemented. | |
2842 | */ | |
a2938c80 JR |
2843 | case MSR_IA32_DEBUGCTLMSR: |
2844 | *data = svm->vmcb->save.dbgctl; | |
2845 | break; | |
2846 | case MSR_IA32_LASTBRANCHFROMIP: | |
2847 | *data = svm->vmcb->save.br_from; | |
2848 | break; | |
2849 | case MSR_IA32_LASTBRANCHTOIP: | |
2850 | *data = svm->vmcb->save.br_to; | |
2851 | break; | |
2852 | case MSR_IA32_LASTINTFROMIP: | |
2853 | *data = svm->vmcb->save.last_excp_from; | |
2854 | break; | |
2855 | case MSR_IA32_LASTINTTOIP: | |
2856 | *data = svm->vmcb->save.last_excp_to; | |
2857 | break; | |
b286d5d8 | 2858 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2859 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2860 | break; |
eb6f302e | 2861 | case MSR_VM_CR: |
4a810181 | 2862 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 2863 | break; |
c8a73f18 AG |
2864 | case MSR_IA32_UCODE_REV: |
2865 | *data = 0x01000065; | |
2866 | break; | |
6aa8b732 | 2867 | default: |
3bab1f5d | 2868 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2869 | } |
2870 | return 0; | |
2871 | } | |
2872 | ||
851ba692 | 2873 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2874 | { |
ad312c7c | 2875 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2876 | u64 data; |
2877 | ||
59200273 AK |
2878 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2879 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2880 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2881 | } else { |
229456fc | 2882 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2883 | |
5fdbf976 | 2884 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2885 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2886 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2887 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2888 | } |
2889 | return 1; | |
2890 | } | |
2891 | ||
4a810181 JR |
2892 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
2893 | { | |
2894 | struct vcpu_svm *svm = to_svm(vcpu); | |
2895 | int svm_dis, chg_mask; | |
2896 | ||
2897 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2898 | return 1; | |
2899 | ||
2900 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2901 | ||
2902 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2903 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2904 | ||
2905 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2906 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2907 | ||
2908 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2909 | ||
2910 | /* check for svm_disable while efer.svme is set */ | |
2911 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2912 | return 1; | |
2913 | ||
2914 | return 0; | |
2915 | } | |
2916 | ||
6aa8b732 AK |
2917 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
2918 | { | |
a2fa3e9f GH |
2919 | struct vcpu_svm *svm = to_svm(vcpu); |
2920 | ||
6aa8b732 | 2921 | switch (ecx) { |
f4e1b3c8 | 2922 | case MSR_IA32_TSC: |
99e3e30a | 2923 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 2924 | break; |
8c06585d | 2925 | case MSR_STAR: |
a2fa3e9f | 2926 | svm->vmcb->save.star = data; |
6aa8b732 | 2927 | break; |
49b14f24 | 2928 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2929 | case MSR_LSTAR: |
a2fa3e9f | 2930 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2931 | break; |
2932 | case MSR_CSTAR: | |
a2fa3e9f | 2933 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2934 | break; |
2935 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2936 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2937 | break; |
2938 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2939 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2940 | break; |
2941 | #endif | |
2942 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2943 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2944 | break; |
2945 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2946 | svm->sysenter_eip = data; |
a2fa3e9f | 2947 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2948 | break; |
2949 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2950 | svm->sysenter_esp = data; |
a2fa3e9f | 2951 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2952 | break; |
a2938c80 | 2953 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 2954 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
24e09cbf | 2955 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
b8688d51 | 2956 | __func__, data); |
24e09cbf JR |
2957 | break; |
2958 | } | |
2959 | if (data & DEBUGCTL_RESERVED_BITS) | |
2960 | return 1; | |
2961 | ||
2962 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 2963 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
2964 | if (data & (1ULL<<0)) |
2965 | svm_enable_lbrv(svm); | |
2966 | else | |
2967 | svm_disable_lbrv(svm); | |
a2938c80 | 2968 | break; |
b286d5d8 | 2969 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2970 | svm->nested.hsave_msr = data; |
62b9abaa | 2971 | break; |
3c5d0a44 | 2972 | case MSR_VM_CR: |
4a810181 | 2973 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 2974 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
2975 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2976 | break; | |
6aa8b732 | 2977 | default: |
3bab1f5d | 2978 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2979 | } |
2980 | return 0; | |
2981 | } | |
2982 | ||
851ba692 | 2983 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2984 | { |
ad312c7c | 2985 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2986 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2987 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2988 | |
af9ca2d7 | 2989 | |
5fdbf976 | 2990 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2991 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2992 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 2993 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
2994 | } else { |
2995 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 2996 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 2997 | } |
6aa8b732 AK |
2998 | return 1; |
2999 | } | |
3000 | ||
851ba692 | 3001 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3002 | { |
e756fc62 | 3003 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3004 | return wrmsr_interception(svm); |
6aa8b732 | 3005 | else |
851ba692 | 3006 | return rdmsr_interception(svm); |
6aa8b732 AK |
3007 | } |
3008 | ||
851ba692 | 3009 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3010 | { |
851ba692 AK |
3011 | struct kvm_run *kvm_run = svm->vcpu.run; |
3012 | ||
3842d135 | 3013 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3014 | svm_clear_vintr(svm); |
85f455f7 | 3015 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3016 | mark_dirty(svm->vmcb, VMCB_INTR); |
c1150d8c DL |
3017 | /* |
3018 | * If the user space waits to inject interrupts, exit as soon as | |
3019 | * possible | |
3020 | */ | |
8061823a GN |
3021 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3022 | kvm_run->request_interrupt_window && | |
3023 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 3024 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3025 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3026 | return 0; | |
3027 | } | |
3028 | ||
3029 | return 1; | |
3030 | } | |
3031 | ||
565d0998 ML |
3032 | static int pause_interception(struct vcpu_svm *svm) |
3033 | { | |
3034 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3035 | return 1; | |
3036 | } | |
3037 | ||
851ba692 | 3038 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3039 | [SVM_EXIT_READ_CR0] = cr_interception, |
3040 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3041 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3042 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3043 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
cda00082 | 3044 | [SVM_EXIT_WRITE_CR0] = cr0_write_interception, |
7ff76d58 AP |
3045 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3046 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3047 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3048 | [SVM_EXIT_READ_DR0] = dr_interception, |
3049 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3050 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3051 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3052 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3053 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3054 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3055 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3056 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3057 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3058 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3059 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3060 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3061 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3062 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3063 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3064 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3065 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3066 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3067 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3068 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3069 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3070 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3071 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3072 | [SVM_EXIT_SMI] = nop_on_interception, |
3073 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3074 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 | 3075 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3076 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3077 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3078 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3079 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3080 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3081 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3082 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3083 | [SVM_EXIT_MSR] = msr_interception, |
3084 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3085 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3086 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3087 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3088 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3089 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3090 | [SVM_EXIT_STGI] = stgi_interception, |
3091 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3092 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3093 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
3094 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
3095 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
81dd35d4 | 3096 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3097 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3098 | }; |
3099 | ||
3f10c846 JR |
3100 | void dump_vmcb(struct kvm_vcpu *vcpu) |
3101 | { | |
3102 | struct vcpu_svm *svm = to_svm(vcpu); | |
3103 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3104 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3105 | ||
3106 | pr_err("VMCB Control Area:\n"); | |
4ee546b4 RJ |
3107 | pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff); |
3108 | pr_err("cr_write: %04x\n", control->intercept_cr >> 16); | |
3aed041a JR |
3109 | pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff); |
3110 | pr_err("dr_write: %04x\n", control->intercept_dr >> 16); | |
3f10c846 JR |
3111 | pr_err("exceptions: %08x\n", control->intercept_exceptions); |
3112 | pr_err("intercepts: %016llx\n", control->intercept); | |
3113 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
3114 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
3115 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
3116 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
3117 | pr_err("asid: %d\n", control->asid); | |
3118 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
3119 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
3120 | pr_err("int_vector: %08x\n", control->int_vector); | |
3121 | pr_err("int_state: %08x\n", control->int_state); | |
3122 | pr_err("exit_code: %08x\n", control->exit_code); | |
3123 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
3124 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
3125 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
3126 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
3127 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
3128 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
3129 | pr_err("event_inj: %08x\n", control->event_inj); | |
3130 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
3131 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
3132 | pr_err("next_rip: %016llx\n", control->next_rip); | |
3133 | pr_err("VMCB State Save Area:\n"); | |
3134 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
3135 | save->es.selector, save->es.attrib, | |
3136 | save->es.limit, save->es.base); | |
3137 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3138 | save->cs.selector, save->cs.attrib, | |
3139 | save->cs.limit, save->cs.base); | |
3140 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
3141 | save->ss.selector, save->ss.attrib, | |
3142 | save->ss.limit, save->ss.base); | |
3143 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
3144 | save->ds.selector, save->ds.attrib, | |
3145 | save->ds.limit, save->ds.base); | |
3146 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3147 | save->fs.selector, save->fs.attrib, | |
3148 | save->fs.limit, save->fs.base); | |
3149 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3150 | save->gs.selector, save->gs.attrib, | |
3151 | save->gs.limit, save->gs.base); | |
3152 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3153 | save->gdtr.selector, save->gdtr.attrib, | |
3154 | save->gdtr.limit, save->gdtr.base); | |
3155 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3156 | save->ldtr.selector, save->ldtr.attrib, | |
3157 | save->ldtr.limit, save->ldtr.base); | |
3158 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3159 | save->idtr.selector, save->idtr.attrib, | |
3160 | save->idtr.limit, save->idtr.base); | |
3161 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3162 | save->tr.selector, save->tr.attrib, | |
3163 | save->tr.limit, save->tr.base); | |
3164 | pr_err("cpl: %d efer: %016llx\n", | |
3165 | save->cpl, save->efer); | |
3166 | pr_err("cr0: %016llx cr2: %016llx\n", | |
3167 | save->cr0, save->cr2); | |
3168 | pr_err("cr3: %016llx cr4: %016llx\n", | |
3169 | save->cr3, save->cr4); | |
3170 | pr_err("dr6: %016llx dr7: %016llx\n", | |
3171 | save->dr6, save->dr7); | |
3172 | pr_err("rip: %016llx rflags: %016llx\n", | |
3173 | save->rip, save->rflags); | |
3174 | pr_err("rsp: %016llx rax: %016llx\n", | |
3175 | save->rsp, save->rax); | |
3176 | pr_err("star: %016llx lstar: %016llx\n", | |
3177 | save->star, save->lstar); | |
3178 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
3179 | save->cstar, save->sfmask); | |
3180 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
3181 | save->kernel_gs_base, save->sysenter_cs); | |
3182 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
3183 | save->sysenter_esp, save->sysenter_eip); | |
3184 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
3185 | save->g_pat, save->dbgctl); | |
3186 | pr_err("br_from: %016llx br_to: %016llx\n", | |
3187 | save->br_from, save->br_to); | |
3188 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
3189 | save->last_excp_from, save->last_excp_to); | |
3190 | ||
3191 | } | |
3192 | ||
586f9607 AK |
3193 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3194 | { | |
3195 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3196 | ||
3197 | *info1 = control->exit_info_1; | |
3198 | *info2 = control->exit_info_2; | |
3199 | } | |
3200 | ||
851ba692 | 3201 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3202 | { |
04d2cc77 | 3203 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3204 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3205 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3206 | |
aa17911e | 3207 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
af9ca2d7 | 3208 | |
4ee546b4 | 3209 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3210 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3211 | if (npt_enabled) | |
3212 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3213 | |
cd3ff653 JR |
3214 | if (unlikely(svm->nested.exit_required)) { |
3215 | nested_svm_vmexit(svm); | |
3216 | svm->nested.exit_required = false; | |
3217 | ||
3218 | return 1; | |
3219 | } | |
3220 | ||
2030753d | 3221 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3222 | int vmexit; |
3223 | ||
d8cabddf JR |
3224 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3225 | svm->vmcb->control.exit_info_1, | |
3226 | svm->vmcb->control.exit_info_2, | |
3227 | svm->vmcb->control.exit_int_info, | |
3228 | svm->vmcb->control.exit_int_info_err); | |
3229 | ||
410e4d57 JR |
3230 | vmexit = nested_svm_exit_special(svm); |
3231 | ||
3232 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3233 | vmexit = nested_svm_exit_handled(svm); | |
3234 | ||
3235 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3236 | return 1; |
cf74a78b AG |
3237 | } |
3238 | ||
a5c3832d JR |
3239 | svm_complete_interrupts(svm); |
3240 | ||
04d2cc77 AK |
3241 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3242 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3243 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3244 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3245 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3246 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3247 | return 0; |
3248 | } | |
3249 | ||
a2fa3e9f | 3250 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3251 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3252 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3253 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3254 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3255 | "exit_code 0x%x\n", | |
b8688d51 | 3256 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3257 | exit_code); |
3258 | ||
9d8f549d | 3259 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3260 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3261 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3262 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3263 | return 0; |
3264 | } | |
3265 | ||
851ba692 | 3266 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3267 | } |
3268 | ||
3269 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3270 | { | |
3271 | int cpu = raw_smp_processor_id(); | |
3272 | ||
0fe1e009 TH |
3273 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3274 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3275 | load_TR_desc(); |
3276 | } | |
3277 | ||
e756fc62 | 3278 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3279 | { |
3280 | int cpu = raw_smp_processor_id(); | |
3281 | ||
0fe1e009 | 3282 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3283 | |
4b656b12 | 3284 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3285 | if (svm->asid_generation != sd->asid_generation) |
3286 | new_asid(svm, sd); | |
6aa8b732 AK |
3287 | } |
3288 | ||
95ba8273 GN |
3289 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3290 | { | |
3291 | struct vcpu_svm *svm = to_svm(vcpu); | |
3292 | ||
3293 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3294 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3295 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3296 | ++vcpu->stat.nmi_injections; |
3297 | } | |
6aa8b732 | 3298 | |
85f455f7 | 3299 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3300 | { |
3301 | struct vmcb_control_area *control; | |
3302 | ||
e756fc62 | 3303 | control = &svm->vmcb->control; |
85f455f7 | 3304 | control->int_vector = irq; |
6aa8b732 AK |
3305 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3306 | control->int_ctl |= V_IRQ_MASK | | |
3307 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3308 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3309 | } |
3310 | ||
66fd3f7f | 3311 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3312 | { |
3313 | struct vcpu_svm *svm = to_svm(vcpu); | |
3314 | ||
2af9194d | 3315 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3316 | |
9fb2d2b4 GN |
3317 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3318 | ++vcpu->stat.irq_injections; | |
3319 | ||
219b65dc AG |
3320 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3321 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3322 | } |
3323 | ||
95ba8273 | 3324 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3325 | { |
3326 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3327 | |
2030753d | 3328 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3329 | return; |
3330 | ||
95ba8273 | 3331 | if (irr == -1) |
aaacfc9a JR |
3332 | return; |
3333 | ||
95ba8273 | 3334 | if (tpr >= irr) |
4ee546b4 | 3335 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3336 | } |
aaacfc9a | 3337 | |
95ba8273 GN |
3338 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3339 | { | |
3340 | struct vcpu_svm *svm = to_svm(vcpu); | |
3341 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3342 | int ret; |
3343 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3344 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3345 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3346 | ||
3347 | return ret; | |
aaacfc9a JR |
3348 | } |
3349 | ||
3cfc3092 JK |
3350 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3351 | { | |
3352 | struct vcpu_svm *svm = to_svm(vcpu); | |
3353 | ||
3354 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3355 | } | |
3356 | ||
3357 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3358 | { | |
3359 | struct vcpu_svm *svm = to_svm(vcpu); | |
3360 | ||
3361 | if (masked) { | |
3362 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3363 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3364 | } else { |
3365 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3366 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3367 | } |
3368 | } | |
3369 | ||
78646121 GN |
3370 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3371 | { | |
3372 | struct vcpu_svm *svm = to_svm(vcpu); | |
3373 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3374 | int ret; |
3375 | ||
3376 | if (!gif_set(svm) || | |
3377 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3378 | return 0; | |
3379 | ||
3380 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
3381 | ||
2030753d | 3382 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3383 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3384 | ||
3385 | return ret; | |
78646121 GN |
3386 | } |
3387 | ||
9222be18 | 3388 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3389 | { |
219b65dc | 3390 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3391 | |
e0231715 JR |
3392 | /* |
3393 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3394 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3395 | * get that intercept, this function will be called again though and | |
3396 | * we'll get the vintr intercept. | |
3397 | */ | |
8fe54654 | 3398 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3399 | svm_set_vintr(svm); |
3400 | svm_inject_irq(svm, 0x0); | |
3401 | } | |
85f455f7 ED |
3402 | } |
3403 | ||
95ba8273 | 3404 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3405 | { |
04d2cc77 | 3406 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3407 | |
44c11430 GN |
3408 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3409 | == HF_NMI_MASK) | |
3410 | return; /* IRET will cause a vm exit */ | |
3411 | ||
e0231715 JR |
3412 | /* |
3413 | * Something prevents NMI from been injected. Single step over possible | |
3414 | * problem (IRET or exception injection or interrupt shadow) | |
3415 | */ | |
6be7d306 | 3416 | svm->nmi_singlestep = true; |
44c11430 GN |
3417 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3418 | update_db_intercept(vcpu); | |
c1150d8c DL |
3419 | } |
3420 | ||
cbc94022 IE |
3421 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3422 | { | |
3423 | return 0; | |
3424 | } | |
3425 | ||
d9e368d6 AK |
3426 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3427 | { | |
38e5e92f JR |
3428 | struct vcpu_svm *svm = to_svm(vcpu); |
3429 | ||
3430 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3431 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3432 | else | |
3433 | svm->asid_generation--; | |
d9e368d6 AK |
3434 | } |
3435 | ||
04d2cc77 AK |
3436 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3437 | { | |
3438 | } | |
3439 | ||
d7bf8221 JR |
3440 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3441 | { | |
3442 | struct vcpu_svm *svm = to_svm(vcpu); | |
3443 | ||
2030753d | 3444 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3445 | return; |
3446 | ||
4ee546b4 | 3447 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3448 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3449 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3450 | } |
3451 | } | |
3452 | ||
649d6864 JR |
3453 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3454 | { | |
3455 | struct vcpu_svm *svm = to_svm(vcpu); | |
3456 | u64 cr8; | |
3457 | ||
2030753d | 3458 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3459 | return; |
3460 | ||
649d6864 JR |
3461 | cr8 = kvm_get_cr8(vcpu); |
3462 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3463 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3464 | } | |
3465 | ||
9222be18 GN |
3466 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3467 | { | |
3468 | u8 vector; | |
3469 | int type; | |
3470 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3471 | unsigned int3_injected = svm->int3_injected; |
3472 | ||
3473 | svm->int3_injected = 0; | |
9222be18 | 3474 | |
3842d135 | 3475 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) { |
44c11430 | 3476 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3477 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3478 | } | |
44c11430 | 3479 | |
9222be18 GN |
3480 | svm->vcpu.arch.nmi_injected = false; |
3481 | kvm_clear_exception_queue(&svm->vcpu); | |
3482 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3483 | ||
3484 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3485 | return; | |
3486 | ||
3842d135 AK |
3487 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3488 | ||
9222be18 GN |
3489 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3490 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3491 | ||
3492 | switch (type) { | |
3493 | case SVM_EXITINTINFO_TYPE_NMI: | |
3494 | svm->vcpu.arch.nmi_injected = true; | |
3495 | break; | |
3496 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3497 | /* |
3498 | * In case of software exceptions, do not reinject the vector, | |
3499 | * but re-execute the instruction instead. Rewind RIP first | |
3500 | * if we emulated INT3 before. | |
3501 | */ | |
3502 | if (kvm_exception_is_soft(vector)) { | |
3503 | if (vector == BP_VECTOR && int3_injected && | |
3504 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3505 | kvm_rip_write(&svm->vcpu, | |
3506 | kvm_rip_read(&svm->vcpu) - | |
3507 | int3_injected); | |
9222be18 | 3508 | break; |
66b7138f | 3509 | } |
9222be18 GN |
3510 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3511 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3512 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3513 | |
3514 | } else | |
ce7ddec4 | 3515 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3516 | break; |
3517 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3518 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3519 | break; |
3520 | default: | |
3521 | break; | |
3522 | } | |
3523 | } | |
3524 | ||
b463a6f7 AK |
3525 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3526 | { | |
3527 | struct vcpu_svm *svm = to_svm(vcpu); | |
3528 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3529 | ||
3530 | control->exit_int_info = control->event_inj; | |
3531 | control->exit_int_info_err = control->event_inj_err; | |
3532 | control->event_inj = 0; | |
3533 | svm_complete_interrupts(svm); | |
3534 | } | |
3535 | ||
80e31d4f AK |
3536 | #ifdef CONFIG_X86_64 |
3537 | #define R "r" | |
3538 | #else | |
3539 | #define R "e" | |
3540 | #endif | |
3541 | ||
851ba692 | 3542 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3543 | { |
a2fa3e9f | 3544 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3545 | |
2041a06a JR |
3546 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3547 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3548 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3549 | ||
cd3ff653 JR |
3550 | /* |
3551 | * A vmexit emulation is required before the vcpu can be executed | |
3552 | * again. | |
3553 | */ | |
3554 | if (unlikely(svm->nested.exit_required)) | |
3555 | return; | |
3556 | ||
e756fc62 | 3557 | pre_svm_run(svm); |
6aa8b732 | 3558 | |
649d6864 JR |
3559 | sync_lapic_to_cr8(vcpu); |
3560 | ||
cda0ffdd | 3561 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3562 | |
04d2cc77 AK |
3563 | clgi(); |
3564 | ||
3565 | local_irq_enable(); | |
36241b8c | 3566 | |
6aa8b732 | 3567 | asm volatile ( |
80e31d4f AK |
3568 | "push %%"R"bp; \n\t" |
3569 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3570 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3571 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3572 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3573 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3574 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3575 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3576 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3577 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3578 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3579 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3580 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3581 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3582 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3583 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3584 | #endif |
3585 | ||
6aa8b732 | 3586 | /* Enter guest mode */ |
80e31d4f AK |
3587 | "push %%"R"ax \n\t" |
3588 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3589 | __ex(SVM_VMLOAD) "\n\t" |
3590 | __ex(SVM_VMRUN) "\n\t" | |
3591 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3592 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3593 | |
3594 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3595 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3596 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3597 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3598 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3599 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3600 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3601 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3602 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3603 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3604 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3605 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3606 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3607 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3608 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3609 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3610 | #endif |
80e31d4f | 3611 | "pop %%"R"bp" |
6aa8b732 | 3612 | : |
fb3f0f51 | 3613 | : [svm]"a"(svm), |
6aa8b732 | 3614 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3615 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3616 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3617 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3618 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3619 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3620 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3621 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3622 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3623 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3624 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3625 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3626 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3627 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3628 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3629 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3630 | #endif |
54a08c04 | 3631 | : "cc", "memory" |
80e31d4f | 3632 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3633 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3634 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3635 | #endif | |
3636 | ); | |
6aa8b732 | 3637 | |
82ca2d10 AK |
3638 | #ifdef CONFIG_X86_64 |
3639 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3640 | #else | |
dacccfdd | 3641 | loadsegment(fs, svm->host.fs); |
9581d442 | 3642 | #endif |
6aa8b732 AK |
3643 | |
3644 | reload_tss(vcpu); | |
3645 | ||
56ba47dd AK |
3646 | local_irq_disable(); |
3647 | ||
3648 | stgi(); | |
3649 | ||
13c34e07 AK |
3650 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3651 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3652 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3653 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3654 | ||
d7bf8221 JR |
3655 | sync_cr8_to_lapic(vcpu); |
3656 | ||
a2fa3e9f | 3657 | svm->next_rip = 0; |
9222be18 | 3658 | |
38e5e92f JR |
3659 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3660 | ||
631bc487 GN |
3661 | /* if exit due to PF check for async PF */ |
3662 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3663 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3664 | ||
6de4f3ad AK |
3665 | if (npt_enabled) { |
3666 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3667 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3668 | } | |
fe5913e4 JR |
3669 | |
3670 | /* | |
3671 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3672 | * change the physical cpu | |
3673 | */ | |
3674 | if (unlikely(svm->vmcb->control.exit_code == | |
3675 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3676 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3677 | |
3678 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3679 | } |
3680 | ||
80e31d4f AK |
3681 | #undef R |
3682 | ||
6aa8b732 AK |
3683 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3684 | { | |
a2fa3e9f GH |
3685 | struct vcpu_svm *svm = to_svm(vcpu); |
3686 | ||
3687 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3688 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3689 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3690 | } |
3691 | ||
1c97f0a0 JR |
3692 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3693 | { | |
3694 | struct vcpu_svm *svm = to_svm(vcpu); | |
3695 | ||
3696 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3697 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3698 | |
3699 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3700 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3701 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3702 | |
f40f6a45 | 3703 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3704 | } |
3705 | ||
6aa8b732 AK |
3706 | static int is_disabled(void) |
3707 | { | |
6031a61c JR |
3708 | u64 vm_cr; |
3709 | ||
3710 | rdmsrl(MSR_VM_CR, vm_cr); | |
3711 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3712 | return 1; | |
3713 | ||
6aa8b732 AK |
3714 | return 0; |
3715 | } | |
3716 | ||
102d8325 IM |
3717 | static void |
3718 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3719 | { | |
3720 | /* | |
3721 | * Patch in the VMMCALL instruction: | |
3722 | */ | |
3723 | hypercall[0] = 0x0f; | |
3724 | hypercall[1] = 0x01; | |
3725 | hypercall[2] = 0xd9; | |
102d8325 IM |
3726 | } |
3727 | ||
002c7f7c YS |
3728 | static void svm_check_processor_compat(void *rtn) |
3729 | { | |
3730 | *(int *)rtn = 0; | |
3731 | } | |
3732 | ||
774ead3a AK |
3733 | static bool svm_cpu_has_accelerated_tpr(void) |
3734 | { | |
3735 | return false; | |
3736 | } | |
3737 | ||
4b12f0de | 3738 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3739 | { |
3740 | return 0; | |
3741 | } | |
3742 | ||
0e851880 SY |
3743 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3744 | { | |
3745 | } | |
3746 | ||
d4330ef2 JR |
3747 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3748 | { | |
c2c63a49 | 3749 | switch (func) { |
4c62a2dc JR |
3750 | case 0x80000001: |
3751 | if (nested) | |
3752 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3753 | break; | |
c2c63a49 JR |
3754 | case 0x8000000A: |
3755 | entry->eax = 1; /* SVM revision 1 */ | |
3756 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3757 | ASID emulation to nested SVM */ | |
3758 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
3759 | entry->edx = 0; /* Per default do not support any |
3760 | additional features */ | |
3761 | ||
3762 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 3763 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 3764 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 3765 | |
3d4aeaad JR |
3766 | /* Support NPT for the guest if enabled */ |
3767 | if (npt_enabled) | |
3768 | entry->edx |= SVM_FEATURE_NPT; | |
3769 | ||
c2c63a49 JR |
3770 | break; |
3771 | } | |
d4330ef2 JR |
3772 | } |
3773 | ||
229456fc | 3774 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
e0231715 JR |
3775 | { SVM_EXIT_READ_CR0, "read_cr0" }, |
3776 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3777 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3778 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3779 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3780 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3781 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3782 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3783 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3784 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3785 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3786 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3787 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3788 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3789 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3790 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3791 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3792 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
229456fc MT |
3793 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, |
3794 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3795 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3796 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3797 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3798 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3799 | { SVM_EXIT_INTR, "interrupt" }, | |
3800 | { SVM_EXIT_NMI, "nmi" }, | |
3801 | { SVM_EXIT_SMI, "smi" }, | |
3802 | { SVM_EXIT_INIT, "init" }, | |
3803 | { SVM_EXIT_VINTR, "vintr" }, | |
3804 | { SVM_EXIT_CPUID, "cpuid" }, | |
3805 | { SVM_EXIT_INVD, "invd" }, | |
3806 | { SVM_EXIT_HLT, "hlt" }, | |
3807 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3808 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3809 | { SVM_EXIT_IOIO, "io" }, | |
3810 | { SVM_EXIT_MSR, "msr" }, | |
3811 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3812 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3813 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3814 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3815 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3816 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3817 | { SVM_EXIT_STGI, "stgi" }, | |
3818 | { SVM_EXIT_CLGI, "clgi" }, | |
3819 | { SVM_EXIT_SKINIT, "skinit" }, | |
3820 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3821 | { SVM_EXIT_MONITOR, "monitor" }, | |
3822 | { SVM_EXIT_MWAIT, "mwait" }, | |
81dd35d4 | 3823 | { SVM_EXIT_XSETBV, "xsetbv" }, |
229456fc MT |
3824 | { SVM_EXIT_NPF, "npf" }, |
3825 | { -1, NULL } | |
3826 | }; | |
3827 | ||
17cc3935 | 3828 | static int svm_get_lpage_level(void) |
344f414f | 3829 | { |
17cc3935 | 3830 | return PT_PDPE_LEVEL; |
344f414f JR |
3831 | } |
3832 | ||
4e47c7a6 SY |
3833 | static bool svm_rdtscp_supported(void) |
3834 | { | |
3835 | return false; | |
3836 | } | |
3837 | ||
f5f48ee1 SY |
3838 | static bool svm_has_wbinvd_exit(void) |
3839 | { | |
3840 | return true; | |
3841 | } | |
3842 | ||
02daab21 AK |
3843 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
3844 | { | |
3845 | struct vcpu_svm *svm = to_svm(vcpu); | |
3846 | ||
18c918c5 | 3847 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 3848 | update_cr0_intercept(svm); |
02daab21 AK |
3849 | } |
3850 | ||
cbdd1bea | 3851 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
3852 | .cpu_has_kvm_support = has_svm, |
3853 | .disabled_by_bios = is_disabled, | |
3854 | .hardware_setup = svm_hardware_setup, | |
3855 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 3856 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
3857 | .hardware_enable = svm_hardware_enable, |
3858 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 3859 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
3860 | |
3861 | .vcpu_create = svm_create_vcpu, | |
3862 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 3863 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 3864 | |
04d2cc77 | 3865 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
3866 | .vcpu_load = svm_vcpu_load, |
3867 | .vcpu_put = svm_vcpu_put, | |
3868 | ||
3869 | .set_guest_debug = svm_guest_debug, | |
3870 | .get_msr = svm_get_msr, | |
3871 | .set_msr = svm_set_msr, | |
3872 | .get_segment_base = svm_get_segment_base, | |
3873 | .get_segment = svm_get_segment, | |
3874 | .set_segment = svm_set_segment, | |
2e4d2653 | 3875 | .get_cpl = svm_get_cpl, |
1747fb71 | 3876 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 3877 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 3878 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 3879 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 3880 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
3881 | .set_cr3 = svm_set_cr3, |
3882 | .set_cr4 = svm_set_cr4, | |
3883 | .set_efer = svm_set_efer, | |
3884 | .get_idt = svm_get_idt, | |
3885 | .set_idt = svm_set_idt, | |
3886 | .get_gdt = svm_get_gdt, | |
3887 | .set_gdt = svm_set_gdt, | |
020df079 | 3888 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 3889 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
3890 | .get_rflags = svm_get_rflags, |
3891 | .set_rflags = svm_set_rflags, | |
6b52d186 | 3892 | .fpu_activate = svm_fpu_activate, |
02daab21 | 3893 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 3894 | |
6aa8b732 | 3895 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 3896 | |
6aa8b732 | 3897 | .run = svm_vcpu_run, |
04d2cc77 | 3898 | .handle_exit = handle_exit, |
6aa8b732 | 3899 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
3900 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
3901 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 3902 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 3903 | .set_irq = svm_set_irq, |
95ba8273 | 3904 | .set_nmi = svm_inject_nmi, |
298101da | 3905 | .queue_exception = svm_queue_exception, |
b463a6f7 | 3906 | .cancel_injection = svm_cancel_injection, |
78646121 | 3907 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 3908 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
3909 | .get_nmi_mask = svm_get_nmi_mask, |
3910 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
3911 | .enable_nmi_window = enable_nmi_window, |
3912 | .enable_irq_window = enable_irq_window, | |
3913 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
3914 | |
3915 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 3916 | .get_tdp_level = get_npt_level, |
4b12f0de | 3917 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 3918 | |
586f9607 | 3919 | .get_exit_info = svm_get_exit_info, |
229456fc | 3920 | .exit_reasons_str = svm_exit_reasons_str, |
586f9607 | 3921 | |
17cc3935 | 3922 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
3923 | |
3924 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
3925 | |
3926 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
3927 | |
3928 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
3929 | |
3930 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
3931 | |
3932 | .write_tsc_offset = svm_write_tsc_offset, | |
e48672fa | 3933 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
1c97f0a0 JR |
3934 | |
3935 | .set_tdp_cr3 = set_tdp_cr3, | |
6aa8b732 AK |
3936 | }; |
3937 | ||
3938 | static int __init svm_init(void) | |
3939 | { | |
cb498ea2 | 3940 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 3941 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
3942 | } |
3943 | ||
3944 | static void __exit svm_exit(void) | |
3945 | { | |
cb498ea2 | 3946 | kvm_exit(); |
6aa8b732 AK |
3947 | } |
3948 | ||
3949 | module_init(svm_init) | |
3950 | module_exit(svm_exit) |