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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
85f455f7 | 18 | #include "irq.h" |
1d737c8a | 19 | #include "mmu.h" |
5fdbf976 | 20 | #include "kvm_cache_regs.h" |
fe4c7b19 | 21 | #include "x86.h" |
e495606d | 22 | |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/vmalloc.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
229456fc | 28 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
6aa8b732 | 30 | |
e495606d | 31 | #include <asm/desc.h> |
6aa8b732 | 32 | |
63d1142f | 33 | #include <asm/virtext.h> |
229456fc | 34 | #include "trace.h" |
63d1142f | 35 | |
4ecac3fd AK |
36 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
37 | ||
6aa8b732 AK |
38 | MODULE_AUTHOR("Qumranet"); |
39 | MODULE_LICENSE("GPL"); | |
40 | ||
41 | #define IOPM_ALLOC_ORDER 2 | |
42 | #define MSRPM_ALLOC_ORDER 1 | |
43 | ||
6aa8b732 AK |
44 | #define SEG_TYPE_LDT 2 |
45 | #define SEG_TYPE_BUSY_TSS16 3 | |
46 | ||
80b7706e JR |
47 | #define SVM_FEATURE_NPT (1 << 0) |
48 | #define SVM_FEATURE_LBRV (1 << 1) | |
94c935a1 | 49 | #define SVM_FEATURE_SVML (1 << 2) |
565d0998 | 50 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 51 | |
410e4d57 JR |
52 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
53 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
54 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
55 | ||
24e09cbf JR |
56 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
57 | ||
6c8166a7 AK |
58 | static const u32 host_save_user_msrs[] = { |
59 | #ifdef CONFIG_X86_64 | |
60 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
61 | MSR_FS_BASE, | |
62 | #endif | |
63 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
64 | }; | |
65 | ||
66 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
67 | ||
68 | struct kvm_vcpu; | |
69 | ||
e6aa9abd JR |
70 | struct nested_state { |
71 | struct vmcb *hsave; | |
72 | u64 hsave_msr; | |
73 | u64 vmcb; | |
74 | ||
75 | /* These are the merged vectors */ | |
76 | u32 *msrpm; | |
77 | ||
78 | /* gpa pointers to the real vectors */ | |
79 | u64 vmcb_msrpm; | |
aad42c64 | 80 | |
cd3ff653 JR |
81 | /* A VMEXIT is required but not yet emulated */ |
82 | bool exit_required; | |
83 | ||
aad42c64 JR |
84 | /* cache for intercepts of the guest */ |
85 | u16 intercept_cr_read; | |
86 | u16 intercept_cr_write; | |
87 | u16 intercept_dr_read; | |
88 | u16 intercept_dr_write; | |
89 | u32 intercept_exceptions; | |
90 | u64 intercept; | |
91 | ||
e6aa9abd JR |
92 | }; |
93 | ||
6c8166a7 AK |
94 | struct vcpu_svm { |
95 | struct kvm_vcpu vcpu; | |
96 | struct vmcb *vmcb; | |
97 | unsigned long vmcb_pa; | |
98 | struct svm_cpu_data *svm_data; | |
99 | uint64_t asid_generation; | |
100 | uint64_t sysenter_esp; | |
101 | uint64_t sysenter_eip; | |
102 | ||
103 | u64 next_rip; | |
104 | ||
105 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
106 | u64 host_gs_base; | |
6c8166a7 AK |
107 | |
108 | u32 *msrpm; | |
6c8166a7 | 109 | |
e6aa9abd | 110 | struct nested_state nested; |
6be7d306 JK |
111 | |
112 | bool nmi_singlestep; | |
6c8166a7 AK |
113 | }; |
114 | ||
709ddebf JR |
115 | /* enable NPT for AMD64 and X86 with PAE */ |
116 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
117 | static bool npt_enabled = true; | |
118 | #else | |
e3da3acd | 119 | static bool npt_enabled = false; |
709ddebf | 120 | #endif |
6c7dac72 JR |
121 | static int npt = 1; |
122 | ||
123 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 124 | |
4b6e4dca | 125 | static int nested = 1; |
236de055 AG |
126 | module_param(nested, int, S_IRUGO); |
127 | ||
44874f84 | 128 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 129 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 130 | |
410e4d57 | 131 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 132 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 133 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
134 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
135 | bool has_error_code, u32 error_code); | |
136 | ||
a2fa3e9f GH |
137 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
138 | { | |
fb3f0f51 | 139 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
140 | } |
141 | ||
3d6368ef AG |
142 | static inline bool is_nested(struct vcpu_svm *svm) |
143 | { | |
e6aa9abd | 144 | return svm->nested.vmcb; |
3d6368ef AG |
145 | } |
146 | ||
2af9194d JR |
147 | static inline void enable_gif(struct vcpu_svm *svm) |
148 | { | |
149 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
150 | } | |
151 | ||
152 | static inline void disable_gif(struct vcpu_svm *svm) | |
153 | { | |
154 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
155 | } | |
156 | ||
157 | static inline bool gif_set(struct vcpu_svm *svm) | |
158 | { | |
159 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
160 | } | |
161 | ||
4866d5e3 | 162 | static unsigned long iopm_base; |
6aa8b732 AK |
163 | |
164 | struct kvm_ldttss_desc { | |
165 | u16 limit0; | |
166 | u16 base0; | |
167 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
168 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
169 | u32 base3; | |
170 | u32 zero1; | |
171 | } __attribute__((packed)); | |
172 | ||
173 | struct svm_cpu_data { | |
174 | int cpu; | |
175 | ||
5008fdf5 AK |
176 | u64 asid_generation; |
177 | u32 max_asid; | |
178 | u32 next_asid; | |
6aa8b732 AK |
179 | struct kvm_ldttss_desc *tss_desc; |
180 | ||
181 | struct page *save_area; | |
182 | }; | |
183 | ||
184 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 185 | static uint32_t svm_features; |
6aa8b732 AK |
186 | |
187 | struct svm_init_data { | |
188 | int cpu; | |
189 | int r; | |
190 | }; | |
191 | ||
192 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
193 | ||
9d8f549d | 194 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
195 | #define MSRS_RANGE_SIZE 2048 |
196 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
197 | ||
198 | #define MAX_INST_SIZE 15 | |
199 | ||
80b7706e JR |
200 | static inline u32 svm_has(u32 feat) |
201 | { | |
202 | return svm_features & feat; | |
203 | } | |
204 | ||
6aa8b732 AK |
205 | static inline void clgi(void) |
206 | { | |
4ecac3fd | 207 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
208 | } |
209 | ||
210 | static inline void stgi(void) | |
211 | { | |
4ecac3fd | 212 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
213 | } |
214 | ||
215 | static inline void invlpga(unsigned long addr, u32 asid) | |
216 | { | |
4ecac3fd | 217 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
218 | } |
219 | ||
6aa8b732 AK |
220 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
221 | { | |
a2fa3e9f | 222 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
223 | } |
224 | ||
225 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
226 | { | |
227 | force_new_asid(vcpu); | |
228 | } | |
229 | ||
230 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
231 | { | |
709ddebf | 232 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 233 | efer &= ~EFER_LME; |
6aa8b732 | 234 | |
9962d032 | 235 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
f6801dff | 236 | vcpu->arch.efer = efer; |
6aa8b732 AK |
237 | } |
238 | ||
298101da AK |
239 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
240 | bool has_error_code, u32 error_code) | |
241 | { | |
242 | struct vcpu_svm *svm = to_svm(vcpu); | |
243 | ||
cf74a78b AG |
244 | /* If we are within a nested VM we'd better #VMEXIT and let the |
245 | guest handle the exception */ | |
246 | if (nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
247 | return; | |
248 | ||
298101da AK |
249 | svm->vmcb->control.event_inj = nr |
250 | | SVM_EVTINJ_VALID | |
251 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
252 | | SVM_EVTINJ_TYPE_EXEPT; | |
253 | svm->vmcb->control.event_inj_err = error_code; | |
254 | } | |
255 | ||
6aa8b732 AK |
256 | static int is_external_interrupt(u32 info) |
257 | { | |
258 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
259 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
260 | } | |
261 | ||
2809f5d2 GC |
262 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
263 | { | |
264 | struct vcpu_svm *svm = to_svm(vcpu); | |
265 | u32 ret = 0; | |
266 | ||
267 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
268 | ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS; | |
269 | return ret & mask; | |
270 | } | |
271 | ||
272 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
273 | { | |
274 | struct vcpu_svm *svm = to_svm(vcpu); | |
275 | ||
276 | if (mask == 0) | |
277 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
278 | else | |
279 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
280 | ||
281 | } | |
282 | ||
6aa8b732 AK |
283 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
284 | { | |
a2fa3e9f GH |
285 | struct vcpu_svm *svm = to_svm(vcpu); |
286 | ||
287 | if (!svm->next_rip) { | |
851ba692 | 288 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != |
f629cf84 GN |
289 | EMULATE_DONE) |
290 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
291 | return; |
292 | } | |
5fdbf976 MT |
293 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
294 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
295 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 296 | |
5fdbf976 | 297 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 298 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
299 | } |
300 | ||
301 | static int has_svm(void) | |
302 | { | |
63d1142f | 303 | const char *msg; |
6aa8b732 | 304 | |
63d1142f | 305 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 306 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
307 | return 0; |
308 | } | |
309 | ||
6aa8b732 AK |
310 | return 1; |
311 | } | |
312 | ||
313 | static void svm_hardware_disable(void *garbage) | |
314 | { | |
2c8dceeb | 315 | cpu_svm_disable(); |
6aa8b732 AK |
316 | } |
317 | ||
10474ae8 | 318 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
319 | { |
320 | ||
0fe1e009 | 321 | struct svm_cpu_data *sd; |
6aa8b732 | 322 | uint64_t efer; |
89a27f4d | 323 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
324 | struct desc_struct *gdt; |
325 | int me = raw_smp_processor_id(); | |
326 | ||
10474ae8 AG |
327 | rdmsrl(MSR_EFER, efer); |
328 | if (efer & EFER_SVME) | |
329 | return -EBUSY; | |
330 | ||
6aa8b732 | 331 | if (!has_svm()) { |
e6732a5a ZA |
332 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
333 | me); | |
10474ae8 | 334 | return -EINVAL; |
6aa8b732 | 335 | } |
0fe1e009 | 336 | sd = per_cpu(svm_data, me); |
6aa8b732 | 337 | |
0fe1e009 | 338 | if (!sd) { |
e6732a5a | 339 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 340 | me); |
10474ae8 | 341 | return -EINVAL; |
6aa8b732 AK |
342 | } |
343 | ||
0fe1e009 TH |
344 | sd->asid_generation = 1; |
345 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
346 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 347 | |
b792c344 | 348 | kvm_get_gdt(&gdt_descr); |
89a27f4d | 349 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 350 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 351 | |
9962d032 | 352 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 353 | |
d0316554 | 354 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 AG |
355 | |
356 | return 0; | |
6aa8b732 AK |
357 | } |
358 | ||
0da1db75 JR |
359 | static void svm_cpu_uninit(int cpu) |
360 | { | |
0fe1e009 | 361 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 362 | |
0fe1e009 | 363 | if (!sd) |
0da1db75 JR |
364 | return; |
365 | ||
366 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
367 | __free_page(sd->save_area); |
368 | kfree(sd); | |
0da1db75 JR |
369 | } |
370 | ||
6aa8b732 AK |
371 | static int svm_cpu_init(int cpu) |
372 | { | |
0fe1e009 | 373 | struct svm_cpu_data *sd; |
6aa8b732 AK |
374 | int r; |
375 | ||
0fe1e009 TH |
376 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
377 | if (!sd) | |
6aa8b732 | 378 | return -ENOMEM; |
0fe1e009 TH |
379 | sd->cpu = cpu; |
380 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 381 | r = -ENOMEM; |
0fe1e009 | 382 | if (!sd->save_area) |
6aa8b732 AK |
383 | goto err_1; |
384 | ||
0fe1e009 | 385 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
386 | |
387 | return 0; | |
388 | ||
389 | err_1: | |
0fe1e009 | 390 | kfree(sd); |
6aa8b732 AK |
391 | return r; |
392 | ||
393 | } | |
394 | ||
bfc733a7 RR |
395 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
396 | int read, int write) | |
6aa8b732 AK |
397 | { |
398 | int i; | |
399 | ||
400 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
401 | if (msr >= msrpm_ranges[i] && | |
402 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
403 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
404 | msrpm_ranges[i]) * 2; | |
405 | ||
406 | u32 *base = msrpm + (msr_offset / 32); | |
407 | u32 msr_shift = msr_offset % 32; | |
408 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
409 | *base = (*base & ~(0x3 << msr_shift)) | | |
410 | (mask << msr_shift); | |
bfc733a7 | 411 | return; |
6aa8b732 AK |
412 | } |
413 | } | |
bfc733a7 | 414 | BUG(); |
6aa8b732 AK |
415 | } |
416 | ||
f65c229c JR |
417 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
418 | { | |
419 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
420 | ||
421 | #ifdef CONFIG_X86_64 | |
422 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
423 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
424 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
425 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
426 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
427 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
428 | #endif | |
429 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
430 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
f65c229c JR |
431 | } |
432 | ||
24e09cbf JR |
433 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
434 | { | |
435 | u32 *msrpm = svm->msrpm; | |
436 | ||
437 | svm->vmcb->control.lbr_ctl = 1; | |
438 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
439 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
440 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
441 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
442 | } | |
443 | ||
444 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
445 | { | |
446 | u32 *msrpm = svm->msrpm; | |
447 | ||
448 | svm->vmcb->control.lbr_ctl = 0; | |
449 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
450 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
451 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
452 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
453 | } | |
454 | ||
6aa8b732 AK |
455 | static __init int svm_hardware_setup(void) |
456 | { | |
457 | int cpu; | |
458 | struct page *iopm_pages; | |
f65c229c | 459 | void *iopm_va; |
6aa8b732 AK |
460 | int r; |
461 | ||
6aa8b732 AK |
462 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
463 | ||
464 | if (!iopm_pages) | |
465 | return -ENOMEM; | |
c8681339 AL |
466 | |
467 | iopm_va = page_address(iopm_pages); | |
468 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
469 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
470 | ||
50a37eb4 JR |
471 | if (boot_cpu_has(X86_FEATURE_NX)) |
472 | kvm_enable_efer_bits(EFER_NX); | |
473 | ||
1b2fd70c AG |
474 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
475 | kvm_enable_efer_bits(EFER_FFXSR); | |
476 | ||
236de055 AG |
477 | if (nested) { |
478 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
479 | kvm_enable_efer_bits(EFER_SVME); | |
480 | } | |
481 | ||
3230bb47 | 482 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
483 | r = svm_cpu_init(cpu); |
484 | if (r) | |
f65c229c | 485 | goto err; |
6aa8b732 | 486 | } |
33bd6a0b JR |
487 | |
488 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
489 | ||
e3da3acd JR |
490 | if (!svm_has(SVM_FEATURE_NPT)) |
491 | npt_enabled = false; | |
492 | ||
6c7dac72 JR |
493 | if (npt_enabled && !npt) { |
494 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
495 | npt_enabled = false; | |
496 | } | |
497 | ||
18552672 | 498 | if (npt_enabled) { |
e3da3acd | 499 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 500 | kvm_enable_tdp(); |
5f4cb662 JR |
501 | } else |
502 | kvm_disable_tdp(); | |
e3da3acd | 503 | |
6aa8b732 AK |
504 | return 0; |
505 | ||
f65c229c | 506 | err: |
6aa8b732 AK |
507 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
508 | iopm_base = 0; | |
509 | return r; | |
510 | } | |
511 | ||
512 | static __exit void svm_hardware_unsetup(void) | |
513 | { | |
0da1db75 JR |
514 | int cpu; |
515 | ||
3230bb47 | 516 | for_each_possible_cpu(cpu) |
0da1db75 JR |
517 | svm_cpu_uninit(cpu); |
518 | ||
6aa8b732 | 519 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 520 | iopm_base = 0; |
6aa8b732 AK |
521 | } |
522 | ||
523 | static void init_seg(struct vmcb_seg *seg) | |
524 | { | |
525 | seg->selector = 0; | |
526 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
527 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
528 | seg->limit = 0xffff; | |
529 | seg->base = 0; | |
530 | } | |
531 | ||
532 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
533 | { | |
534 | seg->selector = 0; | |
535 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
536 | seg->limit = 0xffff; | |
537 | seg->base = 0; | |
538 | } | |
539 | ||
e6101a96 | 540 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 541 | { |
e6101a96 JR |
542 | struct vmcb_control_area *control = &svm->vmcb->control; |
543 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 544 | |
bff78274 AK |
545 | svm->vcpu.fpu_active = 1; |
546 | ||
6aa8b732 AK |
547 | control->intercept_cr_read = INTERCEPT_CR0_MASK | |
548 | INTERCEPT_CR3_MASK | | |
649d6864 | 549 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
550 | |
551 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
552 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
553 | INTERCEPT_CR4_MASK | |
554 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
555 | |
556 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
557 | INTERCEPT_DR1_MASK | | |
558 | INTERCEPT_DR2_MASK | | |
727f5a23 JK |
559 | INTERCEPT_DR3_MASK | |
560 | INTERCEPT_DR4_MASK | | |
561 | INTERCEPT_DR5_MASK | | |
562 | INTERCEPT_DR6_MASK | | |
563 | INTERCEPT_DR7_MASK; | |
6aa8b732 AK |
564 | |
565 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
566 | INTERCEPT_DR1_MASK | | |
567 | INTERCEPT_DR2_MASK | | |
568 | INTERCEPT_DR3_MASK | | |
727f5a23 | 569 | INTERCEPT_DR4_MASK | |
6aa8b732 | 570 | INTERCEPT_DR5_MASK | |
727f5a23 | 571 | INTERCEPT_DR6_MASK | |
6aa8b732 AK |
572 | INTERCEPT_DR7_MASK; |
573 | ||
7aa81cc0 | 574 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
575 | (1 << UD_VECTOR) | |
576 | (1 << MC_VECTOR); | |
6aa8b732 AK |
577 | |
578 | ||
579 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
580 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 581 | (1ULL << INTERCEPT_SMI) | |
d225157b | 582 | (1ULL << INTERCEPT_SELECTIVE_CR0) | |
6aa8b732 | 583 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 584 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 585 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 586 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
587 | (1ULL << INTERCEPT_INVLPGA) | |
588 | (1ULL << INTERCEPT_IOIO_PROT) | | |
589 | (1ULL << INTERCEPT_MSR_PROT) | | |
590 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 591 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
592 | (1ULL << INTERCEPT_VMRUN) | |
593 | (1ULL << INTERCEPT_VMMCALL) | | |
594 | (1ULL << INTERCEPT_VMLOAD) | | |
595 | (1ULL << INTERCEPT_VMSAVE) | | |
596 | (1ULL << INTERCEPT_STGI) | | |
597 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 598 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 599 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
600 | (1ULL << INTERCEPT_MONITOR) | |
601 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
602 | |
603 | control->iopm_base_pa = iopm_base; | |
f65c229c | 604 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 605 | control->tsc_offset = 0; |
6aa8b732 AK |
606 | control->int_ctl = V_INTR_MASKING_MASK; |
607 | ||
608 | init_seg(&save->es); | |
609 | init_seg(&save->ss); | |
610 | init_seg(&save->ds); | |
611 | init_seg(&save->fs); | |
612 | init_seg(&save->gs); | |
613 | ||
614 | save->cs.selector = 0xf000; | |
615 | /* Executable/Readable Code Segment */ | |
616 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
617 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
618 | save->cs.limit = 0xffff; | |
d92899a0 AK |
619 | /* |
620 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
621 | * be consistent with it. | |
622 | * | |
623 | * Replace when we have real mode working for vmx. | |
624 | */ | |
625 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
626 | |
627 | save->gdtr.limit = 0xffff; | |
628 | save->idtr.limit = 0xffff; | |
629 | ||
630 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
631 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
632 | ||
9962d032 | 633 | save->efer = EFER_SVME; |
d77c26fc | 634 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
635 | save->dr7 = 0x400; |
636 | save->rflags = 2; | |
637 | save->rip = 0x0000fff0; | |
5fdbf976 | 638 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 639 | |
18fa000a EH |
640 | /* This is the guest-visible cr0 value. |
641 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. | |
6aa8b732 | 642 | */ |
18fa000a EH |
643 | svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
644 | kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0); | |
645 | ||
66aee91a | 646 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 647 | /* rdx = ?? */ |
709ddebf JR |
648 | |
649 | if (npt_enabled) { | |
650 | /* Setup VMCB for Nested Paging */ | |
651 | control->nested_ctl = 1; | |
a7052897 MT |
652 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
653 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf | 654 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
888f9f3e AK |
655 | control->intercept_cr_read &= ~INTERCEPT_CR3_MASK; |
656 | control->intercept_cr_write &= ~INTERCEPT_CR3_MASK; | |
709ddebf | 657 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
658 | save->cr3 = 0; |
659 | save->cr4 = 0; | |
660 | } | |
a79d2f18 | 661 | force_new_asid(&svm->vcpu); |
1371d904 | 662 | |
e6aa9abd | 663 | svm->nested.vmcb = 0; |
2af9194d JR |
664 | svm->vcpu.arch.hflags = 0; |
665 | ||
565d0998 ML |
666 | if (svm_has(SVM_FEATURE_PAUSE_FILTER)) { |
667 | control->pause_filter_count = 3000; | |
668 | control->intercept |= (1ULL << INTERCEPT_PAUSE); | |
669 | } | |
670 | ||
2af9194d | 671 | enable_gif(svm); |
6aa8b732 AK |
672 | } |
673 | ||
e00c8cf2 | 674 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
675 | { |
676 | struct vcpu_svm *svm = to_svm(vcpu); | |
677 | ||
e6101a96 | 678 | init_vmcb(svm); |
70433389 | 679 | |
c5af89b6 | 680 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 681 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
682 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
683 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 684 | } |
5fdbf976 MT |
685 | vcpu->arch.regs_avail = ~0; |
686 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
687 | |
688 | return 0; | |
04d2cc77 AK |
689 | } |
690 | ||
fb3f0f51 | 691 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 692 | { |
a2fa3e9f | 693 | struct vcpu_svm *svm; |
6aa8b732 | 694 | struct page *page; |
f65c229c | 695 | struct page *msrpm_pages; |
b286d5d8 | 696 | struct page *hsave_page; |
3d6368ef | 697 | struct page *nested_msrpm_pages; |
fb3f0f51 | 698 | int err; |
6aa8b732 | 699 | |
c16f862d | 700 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
701 | if (!svm) { |
702 | err = -ENOMEM; | |
703 | goto out; | |
704 | } | |
705 | ||
706 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
707 | if (err) | |
708 | goto free_svm; | |
709 | ||
b7af4043 | 710 | err = -ENOMEM; |
6aa8b732 | 711 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 712 | if (!page) |
fb3f0f51 | 713 | goto uninit; |
6aa8b732 | 714 | |
f65c229c JR |
715 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
716 | if (!msrpm_pages) | |
b7af4043 | 717 | goto free_page1; |
3d6368ef AG |
718 | |
719 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
720 | if (!nested_msrpm_pages) | |
b7af4043 | 721 | goto free_page2; |
f65c229c | 722 | |
b286d5d8 AG |
723 | hsave_page = alloc_page(GFP_KERNEL); |
724 | if (!hsave_page) | |
b7af4043 TY |
725 | goto free_page3; |
726 | ||
e6aa9abd | 727 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 728 | |
b7af4043 TY |
729 | svm->msrpm = page_address(msrpm_pages); |
730 | svm_vcpu_init_msrpm(svm->msrpm); | |
731 | ||
e6aa9abd | 732 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
3d6368ef | 733 | |
a2fa3e9f GH |
734 | svm->vmcb = page_address(page); |
735 | clear_page(svm->vmcb); | |
736 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
737 | svm->asid_generation = 0; | |
e6101a96 | 738 | init_vmcb(svm); |
a2fa3e9f | 739 | |
fb3f0f51 | 740 | fx_init(&svm->vcpu); |
ad312c7c | 741 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 742 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 743 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 744 | |
fb3f0f51 | 745 | return &svm->vcpu; |
36241b8c | 746 | |
b7af4043 TY |
747 | free_page3: |
748 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
749 | free_page2: | |
750 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
751 | free_page1: | |
752 | __free_page(page); | |
fb3f0f51 RR |
753 | uninit: |
754 | kvm_vcpu_uninit(&svm->vcpu); | |
755 | free_svm: | |
a4770347 | 756 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
757 | out: |
758 | return ERR_PTR(err); | |
6aa8b732 AK |
759 | } |
760 | ||
761 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
762 | { | |
a2fa3e9f GH |
763 | struct vcpu_svm *svm = to_svm(vcpu); |
764 | ||
fb3f0f51 | 765 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 766 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
767 | __free_page(virt_to_page(svm->nested.hsave)); |
768 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 769 | kvm_vcpu_uninit(vcpu); |
a4770347 | 770 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
771 | } |
772 | ||
15ad7146 | 773 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 774 | { |
a2fa3e9f | 775 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 776 | int i; |
0cc5064d | 777 | |
0cc5064d | 778 | if (unlikely(cpu != vcpu->cpu)) { |
e935d48e | 779 | u64 delta; |
0cc5064d | 780 | |
953899b6 JR |
781 | if (check_tsc_unstable()) { |
782 | /* | |
783 | * Make sure that the guest sees a monotonically | |
784 | * increasing TSC. | |
785 | */ | |
786 | delta = vcpu->arch.host_tsc - native_read_tsc(); | |
787 | svm->vmcb->control.tsc_offset += delta; | |
788 | if (is_nested(svm)) | |
789 | svm->nested.hsave->control.tsc_offset += delta; | |
790 | } | |
0cc5064d | 791 | vcpu->cpu = cpu; |
2f599714 | 792 | kvm_migrate_timers(vcpu); |
4b656b12 | 793 | svm->asid_generation = 0; |
0cc5064d | 794 | } |
94dfbdb3 AL |
795 | |
796 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 797 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
798 | } |
799 | ||
800 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
801 | { | |
a2fa3e9f | 802 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
803 | int i; |
804 | ||
e1beb1d3 | 805 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 806 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 807 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 808 | |
e935d48e | 809 | vcpu->arch.host_tsc = native_read_tsc(); |
6aa8b732 AK |
810 | } |
811 | ||
6aa8b732 AK |
812 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
813 | { | |
a2fa3e9f | 814 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
815 | } |
816 | ||
817 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
818 | { | |
a2fa3e9f | 819 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
820 | } |
821 | ||
6de4f3ad AK |
822 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
823 | { | |
824 | switch (reg) { | |
825 | case VCPU_EXREG_PDPTR: | |
826 | BUG_ON(!npt_enabled); | |
827 | load_pdptrs(vcpu, vcpu->arch.cr3); | |
828 | break; | |
829 | default: | |
830 | BUG(); | |
831 | } | |
832 | } | |
833 | ||
f0b85051 AG |
834 | static void svm_set_vintr(struct vcpu_svm *svm) |
835 | { | |
836 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
837 | } | |
838 | ||
839 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
840 | { | |
841 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
842 | } | |
843 | ||
6aa8b732 AK |
844 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
845 | { | |
a2fa3e9f | 846 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
847 | |
848 | switch (seg) { | |
849 | case VCPU_SREG_CS: return &save->cs; | |
850 | case VCPU_SREG_DS: return &save->ds; | |
851 | case VCPU_SREG_ES: return &save->es; | |
852 | case VCPU_SREG_FS: return &save->fs; | |
853 | case VCPU_SREG_GS: return &save->gs; | |
854 | case VCPU_SREG_SS: return &save->ss; | |
855 | case VCPU_SREG_TR: return &save->tr; | |
856 | case VCPU_SREG_LDTR: return &save->ldtr; | |
857 | } | |
858 | BUG(); | |
8b6d44c7 | 859 | return NULL; |
6aa8b732 AK |
860 | } |
861 | ||
862 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
863 | { | |
864 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
865 | ||
866 | return s->base; | |
867 | } | |
868 | ||
869 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
870 | struct kvm_segment *var, int seg) | |
871 | { | |
872 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
873 | ||
874 | var->base = s->base; | |
875 | var->limit = s->limit; | |
876 | var->selector = s->selector; | |
877 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
878 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
879 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
880 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
881 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
882 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
883 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
884 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 885 | |
19bca6ab AP |
886 | /* AMD's VMCB does not have an explicit unusable field, so emulate it |
887 | * for cross vendor migration purposes by "not present" | |
888 | */ | |
889 | var->unusable = !var->present || (var->type == 0); | |
890 | ||
1fbdc7a5 AP |
891 | switch (seg) { |
892 | case VCPU_SREG_CS: | |
893 | /* | |
894 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
895 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
896 | * Intel's VMENTRY has a check on the 'G' bit. | |
897 | */ | |
25022acc | 898 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
899 | break; |
900 | case VCPU_SREG_TR: | |
901 | /* | |
902 | * Work around a bug where the busy flag in the tr selector | |
903 | * isn't exposed | |
904 | */ | |
c0d09828 | 905 | var->type |= 0x2; |
1fbdc7a5 AP |
906 | break; |
907 | case VCPU_SREG_DS: | |
908 | case VCPU_SREG_ES: | |
909 | case VCPU_SREG_FS: | |
910 | case VCPU_SREG_GS: | |
911 | /* | |
912 | * The accessed bit must always be set in the segment | |
913 | * descriptor cache, although it can be cleared in the | |
914 | * descriptor, the cached bit always remains at 1. Since | |
915 | * Intel has a check on this, set it here to support | |
916 | * cross-vendor migration. | |
917 | */ | |
918 | if (!var->unusable) | |
919 | var->type |= 0x1; | |
920 | break; | |
b586eb02 AP |
921 | case VCPU_SREG_SS: |
922 | /* On AMD CPUs sometimes the DB bit in the segment | |
923 | * descriptor is left as 1, although the whole segment has | |
924 | * been made unusable. Clear it here to pass an Intel VMX | |
925 | * entry check when cross vendor migrating. | |
926 | */ | |
927 | if (var->unusable) | |
928 | var->db = 0; | |
929 | break; | |
1fbdc7a5 | 930 | } |
6aa8b732 AK |
931 | } |
932 | ||
2e4d2653 IE |
933 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
934 | { | |
935 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
936 | ||
937 | return save->cpl; | |
938 | } | |
939 | ||
89a27f4d | 940 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 941 | { |
a2fa3e9f GH |
942 | struct vcpu_svm *svm = to_svm(vcpu); |
943 | ||
89a27f4d GN |
944 | dt->size = svm->vmcb->save.idtr.limit; |
945 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
946 | } |
947 | ||
89a27f4d | 948 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 949 | { |
a2fa3e9f GH |
950 | struct vcpu_svm *svm = to_svm(vcpu); |
951 | ||
89a27f4d GN |
952 | svm->vmcb->save.idtr.limit = dt->size; |
953 | svm->vmcb->save.idtr.base = dt->address ; | |
6aa8b732 AK |
954 | } |
955 | ||
89a27f4d | 956 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 957 | { |
a2fa3e9f GH |
958 | struct vcpu_svm *svm = to_svm(vcpu); |
959 | ||
89a27f4d GN |
960 | dt->size = svm->vmcb->save.gdtr.limit; |
961 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
962 | } |
963 | ||
89a27f4d | 964 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 965 | { |
a2fa3e9f GH |
966 | struct vcpu_svm *svm = to_svm(vcpu); |
967 | ||
89a27f4d GN |
968 | svm->vmcb->save.gdtr.limit = dt->size; |
969 | svm->vmcb->save.gdtr.base = dt->address ; | |
6aa8b732 AK |
970 | } |
971 | ||
e8467fda AK |
972 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
973 | { | |
974 | } | |
975 | ||
25c4c276 | 976 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
977 | { |
978 | } | |
979 | ||
d225157b AK |
980 | static void update_cr0_intercept(struct vcpu_svm *svm) |
981 | { | |
982 | ulong gcr0 = svm->vcpu.arch.cr0; | |
983 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
984 | ||
985 | if (!svm->vcpu.fpu_active) | |
986 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
987 | else | |
988 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
989 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
990 | ||
991 | ||
992 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
993 | svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; | |
994 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; | |
995 | } else { | |
996 | svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK; | |
997 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK; | |
998 | } | |
999 | } | |
1000 | ||
6aa8b732 AK |
1001 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1002 | { | |
a2fa3e9f GH |
1003 | struct vcpu_svm *svm = to_svm(vcpu); |
1004 | ||
05b3e0c2 | 1005 | #ifdef CONFIG_X86_64 |
f6801dff | 1006 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1007 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1008 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1009 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1010 | } |
1011 | ||
d77c26fc | 1012 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1013 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1014 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1015 | } |
1016 | } | |
1017 | #endif | |
ad312c7c | 1018 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1019 | |
1020 | if (!npt_enabled) | |
1021 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1022 | |
1023 | if (!vcpu->fpu_active) | |
334df50a | 1024 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1025 | /* |
1026 | * re-enable caching here because the QEMU bios | |
1027 | * does not do it - this results in some delay at | |
1028 | * reboot | |
1029 | */ | |
1030 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1031 | svm->vmcb->save.cr0 = cr0; |
d225157b | 1032 | update_cr0_intercept(svm); |
6aa8b732 AK |
1033 | } |
1034 | ||
1035 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1036 | { | |
6394b649 | 1037 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1038 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1039 | ||
1040 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1041 | force_new_asid(vcpu); | |
6394b649 | 1042 | |
ec077263 JR |
1043 | vcpu->arch.cr4 = cr4; |
1044 | if (!npt_enabled) | |
1045 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1046 | cr4 |= host_cr4_mce; |
ec077263 | 1047 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
1048 | } |
1049 | ||
1050 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1051 | struct kvm_segment *var, int seg) | |
1052 | { | |
a2fa3e9f | 1053 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1054 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1055 | ||
1056 | s->base = var->base; | |
1057 | s->limit = var->limit; | |
1058 | s->selector = var->selector; | |
1059 | if (var->unusable) | |
1060 | s->attrib = 0; | |
1061 | else { | |
1062 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1063 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1064 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1065 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1066 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1067 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1068 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1069 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1070 | } | |
1071 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1072 | svm->vmcb->save.cpl |
1073 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1074 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1075 | ||
1076 | } | |
1077 | ||
44c11430 | 1078 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1079 | { |
d0bfb940 JK |
1080 | struct vcpu_svm *svm = to_svm(vcpu); |
1081 | ||
d0bfb940 JK |
1082 | svm->vmcb->control.intercept_exceptions &= |
1083 | ~((1 << DB_VECTOR) | (1 << BP_VECTOR)); | |
44c11430 | 1084 | |
6be7d306 | 1085 | if (svm->nmi_singlestep) |
44c11430 GN |
1086 | svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR); |
1087 | ||
d0bfb940 JK |
1088 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1089 | if (vcpu->guest_debug & | |
1090 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
1091 | svm->vmcb->control.intercept_exceptions |= | |
1092 | 1 << DB_VECTOR; | |
1093 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
1094 | svm->vmcb->control.intercept_exceptions |= | |
1095 | 1 << BP_VECTOR; | |
1096 | } else | |
1097 | vcpu->guest_debug = 0; | |
44c11430 GN |
1098 | } |
1099 | ||
355be0b9 | 1100 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1101 | { |
44c11430 GN |
1102 | struct vcpu_svm *svm = to_svm(vcpu); |
1103 | ||
ae675ef0 JK |
1104 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1105 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1106 | else | |
1107 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1108 | ||
355be0b9 | 1109 | update_db_intercept(vcpu); |
6aa8b732 AK |
1110 | } |
1111 | ||
1112 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
1113 | { | |
94dfbdb3 | 1114 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1115 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1116 | #endif |
6aa8b732 AK |
1117 | } |
1118 | ||
1119 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
1120 | { | |
94dfbdb3 | 1121 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1122 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1123 | #endif |
6aa8b732 AK |
1124 | } |
1125 | ||
0fe1e009 | 1126 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1127 | { |
0fe1e009 TH |
1128 | if (sd->next_asid > sd->max_asid) { |
1129 | ++sd->asid_generation; | |
1130 | sd->next_asid = 1; | |
a2fa3e9f | 1131 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1132 | } |
1133 | ||
0fe1e009 TH |
1134 | svm->asid_generation = sd->asid_generation; |
1135 | svm->vmcb->control.asid = sd->next_asid++; | |
6aa8b732 AK |
1136 | } |
1137 | ||
c76de350 | 1138 | static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest) |
6aa8b732 | 1139 | { |
42dbaa5a | 1140 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a JK |
1141 | |
1142 | switch (dr) { | |
1143 | case 0 ... 3: | |
c76de350 | 1144 | *dest = vcpu->arch.db[dr]; |
42dbaa5a | 1145 | break; |
c76de350 JK |
1146 | case 4: |
1147 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
1148 | return EMULATE_FAIL; /* will re-inject UD */ | |
1149 | /* fall through */ | |
42dbaa5a JK |
1150 | case 6: |
1151 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
c76de350 | 1152 | *dest = vcpu->arch.dr6; |
42dbaa5a | 1153 | else |
c76de350 | 1154 | *dest = svm->vmcb->save.dr6; |
42dbaa5a | 1155 | break; |
c76de350 JK |
1156 | case 5: |
1157 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
1158 | return EMULATE_FAIL; /* will re-inject UD */ | |
1159 | /* fall through */ | |
42dbaa5a JK |
1160 | case 7: |
1161 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
c76de350 | 1162 | *dest = vcpu->arch.dr7; |
42dbaa5a | 1163 | else |
c76de350 | 1164 | *dest = svm->vmcb->save.dr7; |
42dbaa5a | 1165 | break; |
42dbaa5a JK |
1166 | } |
1167 | ||
c76de350 | 1168 | return EMULATE_DONE; |
6aa8b732 AK |
1169 | } |
1170 | ||
c76de350 | 1171 | static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value) |
6aa8b732 | 1172 | { |
a2fa3e9f GH |
1173 | struct vcpu_svm *svm = to_svm(vcpu); |
1174 | ||
6aa8b732 AK |
1175 | switch (dr) { |
1176 | case 0 ... 3: | |
42dbaa5a JK |
1177 | vcpu->arch.db[dr] = value; |
1178 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1179 | vcpu->arch.eff_db[dr] = value; | |
c76de350 JK |
1180 | break; |
1181 | case 4: | |
1182 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
1183 | return EMULATE_FAIL; /* will re-inject UD */ | |
1184 | /* fall through */ | |
42dbaa5a | 1185 | case 6: |
42dbaa5a | 1186 | vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1; |
c76de350 JK |
1187 | break; |
1188 | case 5: | |
1189 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
1190 | return EMULATE_FAIL; /* will re-inject UD */ | |
1191 | /* fall through */ | |
42dbaa5a | 1192 | case 7: |
42dbaa5a JK |
1193 | vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1; |
1194 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1195 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1196 | vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK); | |
1197 | } | |
c76de350 | 1198 | break; |
6aa8b732 | 1199 | } |
c76de350 JK |
1200 | |
1201 | return EMULATE_DONE; | |
6aa8b732 AK |
1202 | } |
1203 | ||
851ba692 | 1204 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1205 | { |
6aa8b732 AK |
1206 | u64 fault_address; |
1207 | u32 error_code; | |
6aa8b732 | 1208 | |
a2fa3e9f GH |
1209 | fault_address = svm->vmcb->control.exit_info_2; |
1210 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1211 | |
229456fc | 1212 | trace_kvm_page_fault(fault_address, error_code); |
52c7847d AK |
1213 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) |
1214 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
3067714c | 1215 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1216 | } |
1217 | ||
851ba692 | 1218 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1219 | { |
851ba692 AK |
1220 | struct kvm_run *kvm_run = svm->vcpu.run; |
1221 | ||
d0bfb940 | 1222 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1223 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1224 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1225 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1226 | return 1; | |
1227 | } | |
44c11430 | 1228 | |
6be7d306 JK |
1229 | if (svm->nmi_singlestep) { |
1230 | svm->nmi_singlestep = false; | |
44c11430 GN |
1231 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1232 | svm->vmcb->save.rflags &= | |
1233 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1234 | update_db_intercept(&svm->vcpu); | |
1235 | } | |
1236 | ||
1237 | if (svm->vcpu.guest_debug & | |
1238 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){ | |
1239 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1240 | kvm_run->debug.arch.pc = | |
1241 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1242 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1243 | return 0; | |
1244 | } | |
1245 | ||
1246 | return 1; | |
d0bfb940 JK |
1247 | } |
1248 | ||
851ba692 | 1249 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1250 | { |
851ba692 AK |
1251 | struct kvm_run *kvm_run = svm->vcpu.run; |
1252 | ||
d0bfb940 JK |
1253 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1254 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1255 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1256 | return 0; | |
1257 | } | |
1258 | ||
851ba692 | 1259 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1260 | { |
1261 | int er; | |
1262 | ||
851ba692 | 1263 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1264 | if (er != EMULATE_DONE) |
7ee5d940 | 1265 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1266 | return 1; |
1267 | } | |
1268 | ||
6b52d186 | 1269 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1270 | { |
6b52d186 | 1271 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1272 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 1273 | svm->vcpu.fpu_active = 1; |
d225157b | 1274 | update_cr0_intercept(svm); |
6b52d186 | 1275 | } |
a2fa3e9f | 1276 | |
6b52d186 AK |
1277 | static int nm_interception(struct vcpu_svm *svm) |
1278 | { | |
1279 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1280 | return 1; |
7807fa6c AL |
1281 | } |
1282 | ||
851ba692 | 1283 | static int mc_interception(struct vcpu_svm *svm) |
53371b50 JR |
1284 | { |
1285 | /* | |
1286 | * On an #MC intercept the MCE handler is not called automatically in | |
1287 | * the host. So do it by hand here. | |
1288 | */ | |
1289 | asm volatile ( | |
1290 | "int $0x12\n"); | |
1291 | /* not sure if we ever come back to this point */ | |
1292 | ||
1293 | return 1; | |
1294 | } | |
1295 | ||
851ba692 | 1296 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1297 | { |
851ba692 AK |
1298 | struct kvm_run *kvm_run = svm->vcpu.run; |
1299 | ||
46fe4ddd JR |
1300 | /* |
1301 | * VMCB is undefined after a SHUTDOWN intercept | |
1302 | * so reinitialize it. | |
1303 | */ | |
a2fa3e9f | 1304 | clear_page(svm->vmcb); |
e6101a96 | 1305 | init_vmcb(svm); |
46fe4ddd JR |
1306 | |
1307 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1308 | return 0; | |
1309 | } | |
1310 | ||
851ba692 | 1311 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1312 | { |
d77c26fc | 1313 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1314 | int size, in, string; |
039576c0 | 1315 | unsigned port; |
6aa8b732 | 1316 | |
e756fc62 | 1317 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1318 | |
a2fa3e9f | 1319 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1320 | |
e70669ab LV |
1321 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1322 | ||
1323 | if (string) { | |
3427318f | 1324 | if (emulate_instruction(&svm->vcpu, |
851ba692 | 1325 | 0, 0, 0) == EMULATE_DO_MMIO) |
e70669ab LV |
1326 | return 0; |
1327 | return 1; | |
1328 | } | |
1329 | ||
039576c0 AK |
1330 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1331 | port = io_info >> 16; | |
1332 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
6aa8b732 | 1333 | |
e93f36bc | 1334 | skip_emulated_instruction(&svm->vcpu); |
851ba692 | 1335 | return kvm_emulate_pio(&svm->vcpu, in, size, port); |
6aa8b732 AK |
1336 | } |
1337 | ||
851ba692 | 1338 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1339 | { |
1340 | return 1; | |
1341 | } | |
1342 | ||
851ba692 | 1343 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1344 | { |
1345 | ++svm->vcpu.stat.irq_exits; | |
1346 | return 1; | |
1347 | } | |
1348 | ||
851ba692 | 1349 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1350 | { |
1351 | return 1; | |
1352 | } | |
1353 | ||
851ba692 | 1354 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1355 | { |
5fdbf976 | 1356 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1357 | skip_emulated_instruction(&svm->vcpu); |
1358 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1359 | } |
1360 | ||
851ba692 | 1361 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1362 | { |
5fdbf976 | 1363 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1364 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1365 | kvm_emulate_hypercall(&svm->vcpu); |
1366 | return 1; | |
02e235bc AK |
1367 | } |
1368 | ||
c0725420 AG |
1369 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1370 | { | |
f6801dff | 1371 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1372 | || !is_paging(&svm->vcpu)) { |
1373 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1374 | return 1; | |
1375 | } | |
1376 | ||
1377 | if (svm->vmcb->save.cpl) { | |
1378 | kvm_inject_gp(&svm->vcpu, 0); | |
1379 | return 1; | |
1380 | } | |
1381 | ||
1382 | return 0; | |
1383 | } | |
1384 | ||
cf74a78b AG |
1385 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1386 | bool has_error_code, u32 error_code) | |
1387 | { | |
b8e88bc8 JR |
1388 | int vmexit; |
1389 | ||
0295ad7d JR |
1390 | if (!is_nested(svm)) |
1391 | return 0; | |
cf74a78b | 1392 | |
0295ad7d JR |
1393 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1394 | svm->vmcb->control.exit_code_hi = 0; | |
1395 | svm->vmcb->control.exit_info_1 = error_code; | |
1396 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1397 | ||
b8e88bc8 JR |
1398 | vmexit = nested_svm_intercept(svm); |
1399 | if (vmexit == NESTED_EXIT_DONE) | |
1400 | svm->nested.exit_required = true; | |
1401 | ||
1402 | return vmexit; | |
cf74a78b AG |
1403 | } |
1404 | ||
1405 | static inline int nested_svm_intr(struct vcpu_svm *svm) | |
1406 | { | |
26666957 JR |
1407 | if (!is_nested(svm)) |
1408 | return 0; | |
cf74a78b | 1409 | |
26666957 JR |
1410 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
1411 | return 0; | |
cf74a78b | 1412 | |
26666957 JR |
1413 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
1414 | return 0; | |
cf74a78b | 1415 | |
26666957 JR |
1416 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1417 | ||
cd3ff653 JR |
1418 | if (svm->nested.intercept & 1ULL) { |
1419 | /* | |
1420 | * The #vmexit can't be emulated here directly because this | |
1421 | * code path runs with irqs and preemtion disabled. A | |
1422 | * #vmexit emulation might sleep. Only signal request for | |
1423 | * the #vmexit here. | |
1424 | */ | |
1425 | svm->nested.exit_required = true; | |
236649de | 1426 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
26666957 | 1427 | return 1; |
cf74a78b AG |
1428 | } |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | ||
7597f129 | 1433 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1434 | { |
1435 | struct page *page; | |
1436 | ||
34f80cfa | 1437 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1438 | if (is_error_page(page)) |
1439 | goto error; | |
1440 | ||
7597f129 JR |
1441 | *_page = page; |
1442 | ||
1443 | return kmap(page); | |
34f80cfa JR |
1444 | |
1445 | error: | |
1446 | kvm_release_page_clean(page); | |
1447 | kvm_inject_gp(&svm->vcpu, 0); | |
1448 | ||
1449 | return NULL; | |
1450 | } | |
1451 | ||
7597f129 | 1452 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1453 | { |
7597f129 | 1454 | kunmap(page); |
34f80cfa JR |
1455 | kvm_release_page_dirty(page); |
1456 | } | |
1457 | ||
3d62d9aa | 1458 | static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1459 | { |
4c2161ae | 1460 | u32 param = svm->vmcb->control.exit_info_1 & 1; |
3d62d9aa | 1461 | u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
7597f129 | 1462 | struct page *page; |
3d62d9aa JR |
1463 | bool ret = false; |
1464 | u32 t0, t1; | |
1465 | u8 *msrpm; | |
4c2161ae | 1466 | |
3d62d9aa JR |
1467 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
1468 | return false; | |
1469 | ||
7597f129 | 1470 | msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page); |
3d62d9aa JR |
1471 | |
1472 | if (!msrpm) | |
1473 | goto out; | |
4c2161ae JR |
1474 | |
1475 | switch (msr) { | |
1476 | case 0 ... 0x1fff: | |
1477 | t0 = (msr * 2) % 8; | |
1478 | t1 = msr / 8; | |
1479 | break; | |
1480 | case 0xc0000000 ... 0xc0001fff: | |
1481 | t0 = (8192 + msr - 0xc0000000) * 2; | |
1482 | t1 = (t0 / 8); | |
1483 | t0 %= 8; | |
1484 | break; | |
1485 | case 0xc0010000 ... 0xc0011fff: | |
1486 | t0 = (16384 + msr - 0xc0010000) * 2; | |
1487 | t1 = (t0 / 8); | |
1488 | t0 %= 8; | |
1489 | break; | |
1490 | default: | |
3d62d9aa JR |
1491 | ret = true; |
1492 | goto out; | |
4c2161ae | 1493 | } |
4c2161ae | 1494 | |
3d62d9aa JR |
1495 | ret = msrpm[t1] & ((1 << param) << t0); |
1496 | ||
1497 | out: | |
7597f129 | 1498 | nested_svm_unmap(page); |
3d62d9aa JR |
1499 | |
1500 | return ret; | |
4c2161ae JR |
1501 | } |
1502 | ||
410e4d57 | 1503 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1504 | { |
cf74a78b | 1505 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1506 | |
410e4d57 JR |
1507 | switch (exit_code) { |
1508 | case SVM_EXIT_INTR: | |
1509 | case SVM_EXIT_NMI: | |
1510 | return NESTED_EXIT_HOST; | |
cf74a78b | 1511 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1512 | case SVM_EXIT_NPF: |
1513 | if (npt_enabled) | |
1514 | return NESTED_EXIT_HOST; | |
1515 | break; | |
1516 | /* When we're shadowing, trap PFs */ | |
1517 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: | |
1518 | if (!npt_enabled) | |
1519 | return NESTED_EXIT_HOST; | |
1520 | break; | |
1521 | default: | |
1522 | break; | |
cf74a78b AG |
1523 | } |
1524 | ||
410e4d57 JR |
1525 | return NESTED_EXIT_CONTINUE; |
1526 | } | |
1527 | ||
1528 | /* | |
1529 | * If this function returns true, this #vmexit was already handled | |
1530 | */ | |
b8e88bc8 | 1531 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
1532 | { |
1533 | u32 exit_code = svm->vmcb->control.exit_code; | |
1534 | int vmexit = NESTED_EXIT_HOST; | |
1535 | ||
cf74a78b | 1536 | switch (exit_code) { |
9c4e40b9 | 1537 | case SVM_EXIT_MSR: |
3d62d9aa | 1538 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1539 | break; |
cf74a78b AG |
1540 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { |
1541 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); | |
aad42c64 | 1542 | if (svm->nested.intercept_cr_read & cr_bits) |
410e4d57 | 1543 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1544 | break; |
1545 | } | |
1546 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: { | |
1547 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0); | |
aad42c64 | 1548 | if (svm->nested.intercept_cr_write & cr_bits) |
410e4d57 | 1549 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1550 | break; |
1551 | } | |
1552 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: { | |
1553 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0); | |
aad42c64 | 1554 | if (svm->nested.intercept_dr_read & dr_bits) |
410e4d57 | 1555 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1556 | break; |
1557 | } | |
1558 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: { | |
1559 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0); | |
aad42c64 | 1560 | if (svm->nested.intercept_dr_write & dr_bits) |
410e4d57 | 1561 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1562 | break; |
1563 | } | |
1564 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1565 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1566 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1567 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1568 | break; |
1569 | } | |
1570 | default: { | |
1571 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 1572 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 1573 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1574 | } |
1575 | } | |
1576 | ||
b8e88bc8 JR |
1577 | return vmexit; |
1578 | } | |
1579 | ||
1580 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1581 | { | |
1582 | int vmexit; | |
1583 | ||
1584 | vmexit = nested_svm_intercept(svm); | |
1585 | ||
1586 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 1587 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
1588 | |
1589 | return vmexit; | |
cf74a78b AG |
1590 | } |
1591 | ||
0460a979 JR |
1592 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
1593 | { | |
1594 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
1595 | struct vmcb_control_area *from = &from_vmcb->control; | |
1596 | ||
1597 | dst->intercept_cr_read = from->intercept_cr_read; | |
1598 | dst->intercept_cr_write = from->intercept_cr_write; | |
1599 | dst->intercept_dr_read = from->intercept_dr_read; | |
1600 | dst->intercept_dr_write = from->intercept_dr_write; | |
1601 | dst->intercept_exceptions = from->intercept_exceptions; | |
1602 | dst->intercept = from->intercept; | |
1603 | dst->iopm_base_pa = from->iopm_base_pa; | |
1604 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
1605 | dst->tsc_offset = from->tsc_offset; | |
1606 | dst->asid = from->asid; | |
1607 | dst->tlb_ctl = from->tlb_ctl; | |
1608 | dst->int_ctl = from->int_ctl; | |
1609 | dst->int_vector = from->int_vector; | |
1610 | dst->int_state = from->int_state; | |
1611 | dst->exit_code = from->exit_code; | |
1612 | dst->exit_code_hi = from->exit_code_hi; | |
1613 | dst->exit_info_1 = from->exit_info_1; | |
1614 | dst->exit_info_2 = from->exit_info_2; | |
1615 | dst->exit_int_info = from->exit_int_info; | |
1616 | dst->exit_int_info_err = from->exit_int_info_err; | |
1617 | dst->nested_ctl = from->nested_ctl; | |
1618 | dst->event_inj = from->event_inj; | |
1619 | dst->event_inj_err = from->event_inj_err; | |
1620 | dst->nested_cr3 = from->nested_cr3; | |
1621 | dst->lbr_ctl = from->lbr_ctl; | |
1622 | } | |
1623 | ||
34f80cfa | 1624 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 1625 | { |
34f80cfa | 1626 | struct vmcb *nested_vmcb; |
e6aa9abd | 1627 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 1628 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 1629 | struct page *page; |
cf74a78b | 1630 | |
17897f36 JR |
1631 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
1632 | vmcb->control.exit_info_1, | |
1633 | vmcb->control.exit_info_2, | |
1634 | vmcb->control.exit_int_info, | |
1635 | vmcb->control.exit_int_info_err); | |
1636 | ||
7597f129 | 1637 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
1638 | if (!nested_vmcb) |
1639 | return 1; | |
1640 | ||
cf74a78b | 1641 | /* Give the current vmcb to the guest */ |
33740e40 JR |
1642 | disable_gif(svm); |
1643 | ||
1644 | nested_vmcb->save.es = vmcb->save.es; | |
1645 | nested_vmcb->save.cs = vmcb->save.cs; | |
1646 | nested_vmcb->save.ss = vmcb->save.ss; | |
1647 | nested_vmcb->save.ds = vmcb->save.ds; | |
1648 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
1649 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
1650 | if (npt_enabled) | |
1651 | nested_vmcb->save.cr3 = vmcb->save.cr3; | |
1652 | nested_vmcb->save.cr2 = vmcb->save.cr2; | |
1653 | nested_vmcb->save.rflags = vmcb->save.rflags; | |
1654 | nested_vmcb->save.rip = vmcb->save.rip; | |
1655 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
1656 | nested_vmcb->save.rax = vmcb->save.rax; | |
1657 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
1658 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
1659 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
1660 | ||
1661 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
1662 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
1663 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
1664 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
1665 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
1666 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
1667 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
1668 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
1669 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
8d23c466 AG |
1670 | |
1671 | /* | |
1672 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
1673 | * to make sure that we do not lose injected events. So check event_inj | |
1674 | * here and copy it to exit_int_info if it is valid. | |
1675 | * Exit_int_info and event_inj can't be both valid because the case | |
1676 | * below only happens on a VMRUN instruction intercept which has | |
1677 | * no valid exit_int_info set. | |
1678 | */ | |
1679 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
1680 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
1681 | ||
1682 | nc->exit_int_info = vmcb->control.event_inj; | |
1683 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
1684 | } | |
1685 | ||
33740e40 JR |
1686 | nested_vmcb->control.tlb_ctl = 0; |
1687 | nested_vmcb->control.event_inj = 0; | |
1688 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
1689 | |
1690 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
1691 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1692 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
1693 | ||
cf74a78b | 1694 | /* Restore the original control entries */ |
0460a979 | 1695 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 1696 | |
219b65dc AG |
1697 | kvm_clear_exception_queue(&svm->vcpu); |
1698 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b AG |
1699 | |
1700 | /* Restore selected save entries */ | |
1701 | svm->vmcb->save.es = hsave->save.es; | |
1702 | svm->vmcb->save.cs = hsave->save.cs; | |
1703 | svm->vmcb->save.ss = hsave->save.ss; | |
1704 | svm->vmcb->save.ds = hsave->save.ds; | |
1705 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
1706 | svm->vmcb->save.idtr = hsave->save.idtr; | |
1707 | svm->vmcb->save.rflags = hsave->save.rflags; | |
1708 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
1709 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
1710 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
1711 | if (npt_enabled) { | |
1712 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
1713 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
1714 | } else { | |
1715 | kvm_set_cr3(&svm->vcpu, hsave->save.cr3); | |
1716 | } | |
1717 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
1718 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
1719 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
1720 | svm->vmcb->save.dr7 = 0; | |
1721 | svm->vmcb->save.cpl = 0; | |
1722 | svm->vmcb->control.exit_int_info = 0; | |
1723 | ||
cf74a78b | 1724 | /* Exit nested SVM mode */ |
e6aa9abd | 1725 | svm->nested.vmcb = 0; |
cf74a78b | 1726 | |
7597f129 | 1727 | nested_svm_unmap(page); |
cf74a78b AG |
1728 | |
1729 | kvm_mmu_reset_context(&svm->vcpu); | |
1730 | kvm_mmu_load(&svm->vcpu); | |
1731 | ||
1732 | return 0; | |
1733 | } | |
3d6368ef | 1734 | |
9738b2c9 | 1735 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 1736 | { |
9738b2c9 | 1737 | u32 *nested_msrpm; |
7597f129 | 1738 | struct page *page; |
3d6368ef | 1739 | int i; |
9738b2c9 | 1740 | |
7597f129 | 1741 | nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page); |
9738b2c9 JR |
1742 | if (!nested_msrpm) |
1743 | return false; | |
1744 | ||
3d6368ef | 1745 | for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++) |
e6aa9abd | 1746 | svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i]; |
9738b2c9 | 1747 | |
e6aa9abd | 1748 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
3d6368ef | 1749 | |
7597f129 | 1750 | nested_svm_unmap(page); |
9738b2c9 JR |
1751 | |
1752 | return true; | |
3d6368ef AG |
1753 | } |
1754 | ||
9738b2c9 | 1755 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 1756 | { |
9738b2c9 | 1757 | struct vmcb *nested_vmcb; |
e6aa9abd | 1758 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 1759 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 1760 | struct page *page; |
3d6368ef | 1761 | |
7597f129 | 1762 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
1763 | if (!nested_vmcb) |
1764 | return false; | |
1765 | ||
3d6368ef | 1766 | /* nested_vmcb is our indicator if nested SVM is activated */ |
e6aa9abd | 1767 | svm->nested.vmcb = svm->vmcb->save.rax; |
3d6368ef | 1768 | |
0ac406de JR |
1769 | trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb, |
1770 | nested_vmcb->save.rip, | |
1771 | nested_vmcb->control.int_ctl, | |
1772 | nested_vmcb->control.event_inj, | |
1773 | nested_vmcb->control.nested_ctl); | |
1774 | ||
3d6368ef | 1775 | /* Clear internal status */ |
219b65dc AG |
1776 | kvm_clear_exception_queue(&svm->vcpu); |
1777 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef AG |
1778 | |
1779 | /* Save the old vmcb, so we don't need to pick what we save, but | |
1780 | can restore everything when a VMEXIT occurs */ | |
defbba56 JR |
1781 | hsave->save.es = vmcb->save.es; |
1782 | hsave->save.cs = vmcb->save.cs; | |
1783 | hsave->save.ss = vmcb->save.ss; | |
1784 | hsave->save.ds = vmcb->save.ds; | |
1785 | hsave->save.gdtr = vmcb->save.gdtr; | |
1786 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 1787 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 1788 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 JR |
1789 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
1790 | hsave->save.rflags = vmcb->save.rflags; | |
1791 | hsave->save.rip = svm->next_rip; | |
1792 | hsave->save.rsp = vmcb->save.rsp; | |
1793 | hsave->save.rax = vmcb->save.rax; | |
1794 | if (npt_enabled) | |
1795 | hsave->save.cr3 = vmcb->save.cr3; | |
1796 | else | |
1797 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
1798 | ||
0460a979 | 1799 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
1800 | |
1801 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
1802 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
1803 | else | |
1804 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
1805 | ||
1806 | /* Load the nested guest state */ | |
1807 | svm->vmcb->save.es = nested_vmcb->save.es; | |
1808 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
1809 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
1810 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
1811 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
1812 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
1813 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
1814 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
1815 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
1816 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
1817 | if (npt_enabled) { | |
1818 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
1819 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
1820 | } else { | |
1821 | kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); | |
1822 | kvm_mmu_reset_context(&svm->vcpu); | |
1823 | } | |
defbba56 | 1824 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
1825 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
1826 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
1827 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
1828 | /* In case we don't even reach vcpu_run, the fields are not updated */ | |
1829 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
1830 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
1831 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
1832 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
1833 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
1834 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
1835 | ||
1836 | /* We don't want a nested guest to be more powerful than the guest, | |
1837 | so all intercepts are ORed */ | |
1838 | svm->vmcb->control.intercept_cr_read |= | |
1839 | nested_vmcb->control.intercept_cr_read; | |
1840 | svm->vmcb->control.intercept_cr_write |= | |
1841 | nested_vmcb->control.intercept_cr_write; | |
1842 | svm->vmcb->control.intercept_dr_read |= | |
1843 | nested_vmcb->control.intercept_dr_read; | |
1844 | svm->vmcb->control.intercept_dr_write |= | |
1845 | nested_vmcb->control.intercept_dr_write; | |
1846 | svm->vmcb->control.intercept_exceptions |= | |
1847 | nested_vmcb->control.intercept_exceptions; | |
1848 | ||
1849 | svm->vmcb->control.intercept |= nested_vmcb->control.intercept; | |
1850 | ||
e6aa9abd | 1851 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa; |
3d6368ef | 1852 | |
aad42c64 JR |
1853 | /* cache intercepts */ |
1854 | svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read; | |
1855 | svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write; | |
1856 | svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read; | |
1857 | svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write; | |
1858 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; | |
1859 | svm->nested.intercept = nested_vmcb->control.intercept; | |
1860 | ||
3d6368ef | 1861 | force_new_asid(&svm->vcpu); |
3d6368ef | 1862 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
1863 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
1864 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
1865 | else | |
1866 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
1867 | ||
3d6368ef AG |
1868 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
1869 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
1870 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
1871 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
1872 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
1873 | ||
7597f129 | 1874 | nested_svm_unmap(page); |
9738b2c9 | 1875 | |
2af9194d | 1876 | enable_gif(svm); |
3d6368ef | 1877 | |
9738b2c9 | 1878 | return true; |
3d6368ef AG |
1879 | } |
1880 | ||
9966bf68 | 1881 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
1882 | { |
1883 | to_vmcb->save.fs = from_vmcb->save.fs; | |
1884 | to_vmcb->save.gs = from_vmcb->save.gs; | |
1885 | to_vmcb->save.tr = from_vmcb->save.tr; | |
1886 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
1887 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
1888 | to_vmcb->save.star = from_vmcb->save.star; | |
1889 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
1890 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
1891 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
1892 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
1893 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
1894 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
1895 | } |
1896 | ||
851ba692 | 1897 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 1898 | { |
9966bf68 | 1899 | struct vmcb *nested_vmcb; |
7597f129 | 1900 | struct page *page; |
9966bf68 | 1901 | |
5542675b AG |
1902 | if (nested_svm_check_permissions(svm)) |
1903 | return 1; | |
1904 | ||
1905 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1906 | skip_emulated_instruction(&svm->vcpu); | |
1907 | ||
7597f129 | 1908 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
1909 | if (!nested_vmcb) |
1910 | return 1; | |
1911 | ||
1912 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 1913 | nested_svm_unmap(page); |
5542675b AG |
1914 | |
1915 | return 1; | |
1916 | } | |
1917 | ||
851ba692 | 1918 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 1919 | { |
9966bf68 | 1920 | struct vmcb *nested_vmcb; |
7597f129 | 1921 | struct page *page; |
9966bf68 | 1922 | |
5542675b AG |
1923 | if (nested_svm_check_permissions(svm)) |
1924 | return 1; | |
1925 | ||
1926 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1927 | skip_emulated_instruction(&svm->vcpu); | |
1928 | ||
7597f129 | 1929 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
1930 | if (!nested_vmcb) |
1931 | return 1; | |
1932 | ||
1933 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 1934 | nested_svm_unmap(page); |
5542675b AG |
1935 | |
1936 | return 1; | |
1937 | } | |
1938 | ||
851ba692 | 1939 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 1940 | { |
3d6368ef AG |
1941 | if (nested_svm_check_permissions(svm)) |
1942 | return 1; | |
1943 | ||
1944 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1945 | skip_emulated_instruction(&svm->vcpu); | |
1946 | ||
9738b2c9 | 1947 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
1948 | return 1; |
1949 | ||
9738b2c9 | 1950 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
1951 | goto failed; |
1952 | ||
1953 | return 1; | |
1954 | ||
1955 | failed: | |
1956 | ||
1957 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
1958 | svm->vmcb->control.exit_code_hi = 0; | |
1959 | svm->vmcb->control.exit_info_1 = 0; | |
1960 | svm->vmcb->control.exit_info_2 = 0; | |
1961 | ||
1962 | nested_svm_vmexit(svm); | |
3d6368ef AG |
1963 | |
1964 | return 1; | |
1965 | } | |
1966 | ||
851ba692 | 1967 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
1968 | { |
1969 | if (nested_svm_check_permissions(svm)) | |
1970 | return 1; | |
1971 | ||
1972 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1973 | skip_emulated_instruction(&svm->vcpu); | |
1974 | ||
2af9194d | 1975 | enable_gif(svm); |
1371d904 AG |
1976 | |
1977 | return 1; | |
1978 | } | |
1979 | ||
851ba692 | 1980 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
1981 | { |
1982 | if (nested_svm_check_permissions(svm)) | |
1983 | return 1; | |
1984 | ||
1985 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1986 | skip_emulated_instruction(&svm->vcpu); | |
1987 | ||
2af9194d | 1988 | disable_gif(svm); |
1371d904 AG |
1989 | |
1990 | /* After a CLGI no interrupts should come */ | |
1991 | svm_clear_vintr(svm); | |
1992 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
1993 | ||
1994 | return 1; | |
1995 | } | |
1996 | ||
851ba692 | 1997 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
1998 | { |
1999 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2000 | |
ec1ff790 JR |
2001 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2002 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2003 | ||
ff092385 AG |
2004 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2005 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2006 | ||
2007 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2008 | skip_emulated_instruction(&svm->vcpu); | |
2009 | return 1; | |
2010 | } | |
2011 | ||
532a46b9 JR |
2012 | static int skinit_interception(struct vcpu_svm *svm) |
2013 | { | |
2014 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2015 | ||
2016 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2017 | return 1; | |
2018 | } | |
2019 | ||
851ba692 | 2020 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2021 | { |
7ee5d940 | 2022 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2023 | return 1; |
2024 | } | |
2025 | ||
851ba692 | 2026 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2027 | { |
37817f29 | 2028 | u16 tss_selector; |
64a7ec06 GN |
2029 | int reason; |
2030 | int int_type = svm->vmcb->control.exit_int_info & | |
2031 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2032 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2033 | uint32_t type = |
2034 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2035 | uint32_t idt_v = | |
2036 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
37817f29 IE |
2037 | |
2038 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2039 | |
37817f29 IE |
2040 | if (svm->vmcb->control.exit_info_2 & |
2041 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2042 | reason = TASK_SWITCH_IRET; |
2043 | else if (svm->vmcb->control.exit_info_2 & | |
2044 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2045 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2046 | else if (idt_v) |
64a7ec06 GN |
2047 | reason = TASK_SWITCH_GATE; |
2048 | else | |
2049 | reason = TASK_SWITCH_CALL; | |
2050 | ||
fe8e7f83 GN |
2051 | if (reason == TASK_SWITCH_GATE) { |
2052 | switch (type) { | |
2053 | case SVM_EXITINTINFO_TYPE_NMI: | |
2054 | svm->vcpu.arch.nmi_injected = false; | |
2055 | break; | |
2056 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
2057 | kvm_clear_exception_queue(&svm->vcpu); | |
2058 | break; | |
2059 | case SVM_EXITINTINFO_TYPE_INTR: | |
2060 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2061 | break; | |
2062 | default: | |
2063 | break; | |
2064 | } | |
2065 | } | |
64a7ec06 | 2066 | |
8317c298 GN |
2067 | if (reason != TASK_SWITCH_GATE || |
2068 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2069 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2070 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2071 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 GN |
2072 | |
2073 | return kvm_task_switch(&svm->vcpu, tss_selector, reason); | |
6aa8b732 AK |
2074 | } |
2075 | ||
851ba692 | 2076 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2077 | { |
5fdbf976 | 2078 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2079 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2080 | return 1; |
6aa8b732 AK |
2081 | } |
2082 | ||
851ba692 | 2083 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2084 | { |
2085 | ++svm->vcpu.stat.nmi_window_exits; | |
2086 | svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET); | |
44c11430 | 2087 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2088 | return 1; |
2089 | } | |
2090 | ||
851ba692 | 2091 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2092 | { |
851ba692 | 2093 | if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE) |
a7052897 MT |
2094 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
2095 | return 1; | |
2096 | } | |
2097 | ||
851ba692 | 2098 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2099 | { |
851ba692 | 2100 | if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 2101 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
2102 | return 1; |
2103 | } | |
2104 | ||
851ba692 | 2105 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2106 | { |
851ba692 AK |
2107 | struct kvm_run *kvm_run = svm->vcpu.run; |
2108 | ||
0a5fff19 GN |
2109 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2110 | /* instruction emulation calls kvm_set_cr8() */ | |
851ba692 | 2111 | emulate_instruction(&svm->vcpu, 0, 0, 0); |
95ba8273 GN |
2112 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
2113 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1d075434 | 2114 | return 1; |
95ba8273 | 2115 | } |
0a5fff19 GN |
2116 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
2117 | return 1; | |
1d075434 JR |
2118 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2119 | return 0; | |
2120 | } | |
2121 | ||
6aa8b732 AK |
2122 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2123 | { | |
a2fa3e9f GH |
2124 | struct vcpu_svm *svm = to_svm(vcpu); |
2125 | ||
6aa8b732 | 2126 | switch (ecx) { |
af24a4e4 | 2127 | case MSR_IA32_TSC: { |
20824f30 | 2128 | u64 tsc_offset; |
6aa8b732 | 2129 | |
20824f30 JR |
2130 | if (is_nested(svm)) |
2131 | tsc_offset = svm->nested.hsave->control.tsc_offset; | |
2132 | else | |
2133 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2134 | ||
2135 | *data = tsc_offset + native_read_tsc(); | |
6aa8b732 AK |
2136 | break; |
2137 | } | |
0e859cac | 2138 | case MSR_K6_STAR: |
a2fa3e9f | 2139 | *data = svm->vmcb->save.star; |
6aa8b732 | 2140 | break; |
0e859cac | 2141 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2142 | case MSR_LSTAR: |
a2fa3e9f | 2143 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2144 | break; |
2145 | case MSR_CSTAR: | |
a2fa3e9f | 2146 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2147 | break; |
2148 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2149 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2150 | break; |
2151 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2152 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2153 | break; |
2154 | #endif | |
2155 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2156 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2157 | break; |
2158 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2159 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2160 | break; |
2161 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2162 | *data = svm->sysenter_esp; |
6aa8b732 | 2163 | break; |
a2938c80 JR |
2164 | /* Nobody will change the following 5 values in the VMCB so |
2165 | we can safely return them on rdmsr. They will always be 0 | |
2166 | until LBRV is implemented. */ | |
2167 | case MSR_IA32_DEBUGCTLMSR: | |
2168 | *data = svm->vmcb->save.dbgctl; | |
2169 | break; | |
2170 | case MSR_IA32_LASTBRANCHFROMIP: | |
2171 | *data = svm->vmcb->save.br_from; | |
2172 | break; | |
2173 | case MSR_IA32_LASTBRANCHTOIP: | |
2174 | *data = svm->vmcb->save.br_to; | |
2175 | break; | |
2176 | case MSR_IA32_LASTINTFROMIP: | |
2177 | *data = svm->vmcb->save.last_excp_from; | |
2178 | break; | |
2179 | case MSR_IA32_LASTINTTOIP: | |
2180 | *data = svm->vmcb->save.last_excp_to; | |
2181 | break; | |
b286d5d8 | 2182 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2183 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2184 | break; |
eb6f302e JR |
2185 | case MSR_VM_CR: |
2186 | *data = 0; | |
2187 | break; | |
c8a73f18 AG |
2188 | case MSR_IA32_UCODE_REV: |
2189 | *data = 0x01000065; | |
2190 | break; | |
6aa8b732 | 2191 | default: |
3bab1f5d | 2192 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2193 | } |
2194 | return 0; | |
2195 | } | |
2196 | ||
851ba692 | 2197 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2198 | { |
ad312c7c | 2199 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2200 | u64 data; |
2201 | ||
59200273 AK |
2202 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2203 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2204 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2205 | } else { |
229456fc | 2206 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2207 | |
5fdbf976 | 2208 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2209 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2210 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2211 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2212 | } |
2213 | return 1; | |
2214 | } | |
2215 | ||
2216 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
2217 | { | |
a2fa3e9f GH |
2218 | struct vcpu_svm *svm = to_svm(vcpu); |
2219 | ||
6aa8b732 | 2220 | switch (ecx) { |
af24a4e4 | 2221 | case MSR_IA32_TSC: { |
20824f30 JR |
2222 | u64 tsc_offset = data - native_read_tsc(); |
2223 | u64 g_tsc_offset = 0; | |
2224 | ||
2225 | if (is_nested(svm)) { | |
2226 | g_tsc_offset = svm->vmcb->control.tsc_offset - | |
2227 | svm->nested.hsave->control.tsc_offset; | |
2228 | svm->nested.hsave->control.tsc_offset = tsc_offset; | |
2229 | } | |
2230 | ||
2231 | svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset; | |
6aa8b732 | 2232 | |
6aa8b732 AK |
2233 | break; |
2234 | } | |
0e859cac | 2235 | case MSR_K6_STAR: |
a2fa3e9f | 2236 | svm->vmcb->save.star = data; |
6aa8b732 | 2237 | break; |
49b14f24 | 2238 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2239 | case MSR_LSTAR: |
a2fa3e9f | 2240 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2241 | break; |
2242 | case MSR_CSTAR: | |
a2fa3e9f | 2243 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2244 | break; |
2245 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2246 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2247 | break; |
2248 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2249 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2250 | break; |
2251 | #endif | |
2252 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2253 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2254 | break; |
2255 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2256 | svm->sysenter_eip = data; |
a2fa3e9f | 2257 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2258 | break; |
2259 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2260 | svm->sysenter_esp = data; |
a2fa3e9f | 2261 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2262 | break; |
a2938c80 | 2263 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
2264 | if (!svm_has(SVM_FEATURE_LBRV)) { |
2265 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 2266 | __func__, data); |
24e09cbf JR |
2267 | break; |
2268 | } | |
2269 | if (data & DEBUGCTL_RESERVED_BITS) | |
2270 | return 1; | |
2271 | ||
2272 | svm->vmcb->save.dbgctl = data; | |
2273 | if (data & (1ULL<<0)) | |
2274 | svm_enable_lbrv(svm); | |
2275 | else | |
2276 | svm_disable_lbrv(svm); | |
a2938c80 | 2277 | break; |
b286d5d8 | 2278 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2279 | svm->nested.hsave_msr = data; |
62b9abaa | 2280 | break; |
3c5d0a44 AG |
2281 | case MSR_VM_CR: |
2282 | case MSR_VM_IGNNE: | |
3c5d0a44 AG |
2283 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2284 | break; | |
6aa8b732 | 2285 | default: |
3bab1f5d | 2286 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2287 | } |
2288 | return 0; | |
2289 | } | |
2290 | ||
851ba692 | 2291 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2292 | { |
ad312c7c | 2293 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2294 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2295 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2296 | |
af9ca2d7 | 2297 | |
5fdbf976 | 2298 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2299 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2300 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 2301 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
2302 | } else { |
2303 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 2304 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 2305 | } |
6aa8b732 AK |
2306 | return 1; |
2307 | } | |
2308 | ||
851ba692 | 2309 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2310 | { |
e756fc62 | 2311 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2312 | return wrmsr_interception(svm); |
6aa8b732 | 2313 | else |
851ba692 | 2314 | return rdmsr_interception(svm); |
6aa8b732 AK |
2315 | } |
2316 | ||
851ba692 | 2317 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2318 | { |
851ba692 AK |
2319 | struct kvm_run *kvm_run = svm->vcpu.run; |
2320 | ||
f0b85051 | 2321 | svm_clear_vintr(svm); |
85f455f7 | 2322 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2323 | /* |
2324 | * If the user space waits to inject interrupts, exit as soon as | |
2325 | * possible | |
2326 | */ | |
8061823a GN |
2327 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
2328 | kvm_run->request_interrupt_window && | |
2329 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 2330 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2331 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2332 | return 0; | |
2333 | } | |
2334 | ||
2335 | return 1; | |
2336 | } | |
2337 | ||
565d0998 ML |
2338 | static int pause_interception(struct vcpu_svm *svm) |
2339 | { | |
2340 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
2341 | return 1; | |
2342 | } | |
2343 | ||
851ba692 | 2344 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
6aa8b732 AK |
2345 | [SVM_EXIT_READ_CR0] = emulate_on_interception, |
2346 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2347 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 2348 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
d225157b | 2349 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
6aa8b732 AK |
2350 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, |
2351 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
2352 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 2353 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
2354 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
2355 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
2356 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2357 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
727f5a23 JK |
2358 | [SVM_EXIT_READ_DR4] = emulate_on_interception, |
2359 | [SVM_EXIT_READ_DR5] = emulate_on_interception, | |
2360 | [SVM_EXIT_READ_DR6] = emulate_on_interception, | |
2361 | [SVM_EXIT_READ_DR7] = emulate_on_interception, | |
6aa8b732 AK |
2362 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, |
2363 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2364 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2365 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
727f5a23 | 2366 | [SVM_EXIT_WRITE_DR4] = emulate_on_interception, |
6aa8b732 | 2367 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, |
727f5a23 | 2368 | [SVM_EXIT_WRITE_DR6] = emulate_on_interception, |
6aa8b732 | 2369 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, |
d0bfb940 JK |
2370 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
2371 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 2372 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 2373 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 2374 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 2375 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 2376 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 2377 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2378 | [SVM_EXIT_SMI] = nop_on_interception, |
2379 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2380 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
2381 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
2382 | [SVM_EXIT_CPUID] = cpuid_interception, | |
95ba8273 | 2383 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 2384 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 2385 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 2386 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2387 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 2388 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
6aa8b732 AK |
2389 | [SVM_EXIT_IOIO] = io_interception, |
2390 | [SVM_EXIT_MSR] = msr_interception, | |
2391 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2392 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2393 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2394 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2395 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2396 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2397 | [SVM_EXIT_STGI] = stgi_interception, |
2398 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 2399 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 2400 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2401 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2402 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2403 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2404 | }; |
2405 | ||
851ba692 | 2406 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 2407 | { |
04d2cc77 | 2408 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 2409 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 2410 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 2411 | |
229456fc | 2412 | trace_kvm_exit(exit_code, svm->vmcb->save.rip); |
af9ca2d7 | 2413 | |
cd3ff653 JR |
2414 | if (unlikely(svm->nested.exit_required)) { |
2415 | nested_svm_vmexit(svm); | |
2416 | svm->nested.exit_required = false; | |
2417 | ||
2418 | return 1; | |
2419 | } | |
2420 | ||
cf74a78b | 2421 | if (is_nested(svm)) { |
410e4d57 JR |
2422 | int vmexit; |
2423 | ||
d8cabddf JR |
2424 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
2425 | svm->vmcb->control.exit_info_1, | |
2426 | svm->vmcb->control.exit_info_2, | |
2427 | svm->vmcb->control.exit_int_info, | |
2428 | svm->vmcb->control.exit_int_info_err); | |
2429 | ||
410e4d57 JR |
2430 | vmexit = nested_svm_exit_special(svm); |
2431 | ||
2432 | if (vmexit == NESTED_EXIT_CONTINUE) | |
2433 | vmexit = nested_svm_exit_handled(svm); | |
2434 | ||
2435 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 2436 | return 1; |
cf74a78b AG |
2437 | } |
2438 | ||
a5c3832d JR |
2439 | svm_complete_interrupts(svm); |
2440 | ||
888f9f3e | 2441 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK)) |
709ddebf | 2442 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
888f9f3e | 2443 | if (npt_enabled) |
709ddebf | 2444 | vcpu->arch.cr3 = svm->vmcb->save.cr3; |
04d2cc77 AK |
2445 | |
2446 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
2447 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2448 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2449 | = svm->vmcb->control.exit_code; | |
2450 | return 0; | |
2451 | } | |
2452 | ||
a2fa3e9f | 2453 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 2454 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
fe8e7f83 | 2455 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH) |
6aa8b732 AK |
2456 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
2457 | "exit_code 0x%x\n", | |
b8688d51 | 2458 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
2459 | exit_code); |
2460 | ||
9d8f549d | 2461 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 2462 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 2463 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 2464 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
2465 | return 0; |
2466 | } | |
2467 | ||
851ba692 | 2468 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
2469 | } |
2470 | ||
2471 | static void reload_tss(struct kvm_vcpu *vcpu) | |
2472 | { | |
2473 | int cpu = raw_smp_processor_id(); | |
2474 | ||
0fe1e009 TH |
2475 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
2476 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
2477 | load_TR_desc(); |
2478 | } | |
2479 | ||
e756fc62 | 2480 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
2481 | { |
2482 | int cpu = raw_smp_processor_id(); | |
2483 | ||
0fe1e009 | 2484 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 2485 | |
a2fa3e9f | 2486 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4b656b12 | 2487 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
2488 | if (svm->asid_generation != sd->asid_generation) |
2489 | new_asid(svm, sd); | |
6aa8b732 AK |
2490 | } |
2491 | ||
95ba8273 GN |
2492 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
2493 | { | |
2494 | struct vcpu_svm *svm = to_svm(vcpu); | |
2495 | ||
2496 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
2497 | vcpu->arch.hflags |= HF_NMI_MASK; | |
2498 | svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET); | |
2499 | ++vcpu->stat.nmi_injections; | |
2500 | } | |
6aa8b732 | 2501 | |
85f455f7 | 2502 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
2503 | { |
2504 | struct vmcb_control_area *control; | |
2505 | ||
229456fc | 2506 | trace_kvm_inj_virq(irq); |
af9ca2d7 | 2507 | |
fa89a817 | 2508 | ++svm->vcpu.stat.irq_injections; |
e756fc62 | 2509 | control = &svm->vmcb->control; |
85f455f7 | 2510 | control->int_vector = irq; |
6aa8b732 AK |
2511 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
2512 | control->int_ctl |= V_IRQ_MASK | | |
2513 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
2514 | } | |
2515 | ||
66fd3f7f | 2516 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
2517 | { |
2518 | struct vcpu_svm *svm = to_svm(vcpu); | |
2519 | ||
2af9194d | 2520 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 2521 | |
219b65dc AG |
2522 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
2523 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
2524 | } |
2525 | ||
95ba8273 | 2526 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
2527 | { |
2528 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 2529 | |
95ba8273 | 2530 | if (irr == -1) |
aaacfc9a JR |
2531 | return; |
2532 | ||
95ba8273 GN |
2533 | if (tpr >= irr) |
2534 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
2535 | } | |
aaacfc9a | 2536 | |
95ba8273 GN |
2537 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
2538 | { | |
2539 | struct vcpu_svm *svm = to_svm(vcpu); | |
2540 | struct vmcb *vmcb = svm->vmcb; | |
2541 | return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
2542 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
aaacfc9a JR |
2543 | } |
2544 | ||
3cfc3092 JK |
2545 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
2546 | { | |
2547 | struct vcpu_svm *svm = to_svm(vcpu); | |
2548 | ||
2549 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
2550 | } | |
2551 | ||
2552 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
2553 | { | |
2554 | struct vcpu_svm *svm = to_svm(vcpu); | |
2555 | ||
2556 | if (masked) { | |
2557 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
2558 | svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET); | |
2559 | } else { | |
2560 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
2561 | svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET); | |
2562 | } | |
2563 | } | |
2564 | ||
78646121 GN |
2565 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
2566 | { | |
2567 | struct vcpu_svm *svm = to_svm(vcpu); | |
2568 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
2569 | int ret; |
2570 | ||
2571 | if (!gif_set(svm) || | |
2572 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
2573 | return 0; | |
2574 | ||
2575 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
2576 | ||
2577 | if (is_nested(svm)) | |
2578 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); | |
2579 | ||
2580 | return ret; | |
78646121 GN |
2581 | } |
2582 | ||
9222be18 | 2583 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 2584 | { |
219b65dc | 2585 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc AG |
2586 | |
2587 | nested_svm_intr(svm); | |
2588 | ||
2589 | /* In case GIF=0 we can't rely on the CPU to tell us when | |
2590 | * GIF becomes 1, because that's a separate STGI/VMRUN intercept. | |
2591 | * The next time we get that intercept, this function will be | |
2592 | * called again though and we'll get the vintr intercept. */ | |
2af9194d | 2593 | if (gif_set(svm)) { |
219b65dc AG |
2594 | svm_set_vintr(svm); |
2595 | svm_inject_irq(svm, 0x0); | |
2596 | } | |
85f455f7 ED |
2597 | } |
2598 | ||
95ba8273 | 2599 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 2600 | { |
04d2cc77 | 2601 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 2602 | |
44c11430 GN |
2603 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
2604 | == HF_NMI_MASK) | |
2605 | return; /* IRET will cause a vm exit */ | |
2606 | ||
2607 | /* Something prevents NMI from been injected. Single step over | |
2608 | possible problem (IRET or exception injection or interrupt | |
2609 | shadow) */ | |
6be7d306 | 2610 | svm->nmi_singlestep = true; |
44c11430 GN |
2611 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
2612 | update_db_intercept(vcpu); | |
c1150d8c DL |
2613 | } |
2614 | ||
cbc94022 IE |
2615 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2616 | { | |
2617 | return 0; | |
2618 | } | |
2619 | ||
d9e368d6 AK |
2620 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
2621 | { | |
2622 | force_new_asid(vcpu); | |
2623 | } | |
2624 | ||
04d2cc77 AK |
2625 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
2626 | { | |
2627 | } | |
2628 | ||
d7bf8221 JR |
2629 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
2630 | { | |
2631 | struct vcpu_svm *svm = to_svm(vcpu); | |
2632 | ||
2633 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
2634 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
615d5193 | 2635 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
2636 | } |
2637 | } | |
2638 | ||
649d6864 JR |
2639 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
2640 | { | |
2641 | struct vcpu_svm *svm = to_svm(vcpu); | |
2642 | u64 cr8; | |
2643 | ||
649d6864 JR |
2644 | cr8 = kvm_get_cr8(vcpu); |
2645 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
2646 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
2647 | } | |
2648 | ||
9222be18 GN |
2649 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
2650 | { | |
2651 | u8 vector; | |
2652 | int type; | |
2653 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
2654 | ||
44c11430 GN |
2655 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) |
2656 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); | |
2657 | ||
9222be18 GN |
2658 | svm->vcpu.arch.nmi_injected = false; |
2659 | kvm_clear_exception_queue(&svm->vcpu); | |
2660 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2661 | ||
2662 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
2663 | return; | |
2664 | ||
2665 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; | |
2666 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
2667 | ||
2668 | switch (type) { | |
2669 | case SVM_EXITINTINFO_TYPE_NMI: | |
2670 | svm->vcpu.arch.nmi_injected = true; | |
2671 | break; | |
2672 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
2673 | /* In case of software exception do not reinject an exception | |
2674 | vector, but re-execute and instruction instead */ | |
219b65dc AG |
2675 | if (is_nested(svm)) |
2676 | break; | |
66fd3f7f | 2677 | if (kvm_exception_is_soft(vector)) |
9222be18 GN |
2678 | break; |
2679 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { | |
2680 | u32 err = svm->vmcb->control.exit_int_info_err; | |
2681 | kvm_queue_exception_e(&svm->vcpu, vector, err); | |
2682 | ||
2683 | } else | |
2684 | kvm_queue_exception(&svm->vcpu, vector); | |
2685 | break; | |
2686 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 2687 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
2688 | break; |
2689 | default: | |
2690 | break; | |
2691 | } | |
2692 | } | |
2693 | ||
80e31d4f AK |
2694 | #ifdef CONFIG_X86_64 |
2695 | #define R "r" | |
2696 | #else | |
2697 | #define R "e" | |
2698 | #endif | |
2699 | ||
851ba692 | 2700 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 2701 | { |
a2fa3e9f | 2702 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2703 | u16 fs_selector; |
2704 | u16 gs_selector; | |
2705 | u16 ldt_selector; | |
d9e368d6 | 2706 | |
cd3ff653 JR |
2707 | /* |
2708 | * A vmexit emulation is required before the vcpu can be executed | |
2709 | * again. | |
2710 | */ | |
2711 | if (unlikely(svm->nested.exit_required)) | |
2712 | return; | |
2713 | ||
5fdbf976 MT |
2714 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
2715 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
2716 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
2717 | ||
e756fc62 | 2718 | pre_svm_run(svm); |
6aa8b732 | 2719 | |
649d6864 JR |
2720 | sync_lapic_to_cr8(vcpu); |
2721 | ||
6aa8b732 | 2722 | save_host_msrs(vcpu); |
d6e88aec AK |
2723 | fs_selector = kvm_read_fs(); |
2724 | gs_selector = kvm_read_gs(); | |
2725 | ldt_selector = kvm_read_ldt(); | |
cda0ffdd | 2726 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
2727 | /* required for live migration with NPT */ |
2728 | if (npt_enabled) | |
2729 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 2730 | |
04d2cc77 AK |
2731 | clgi(); |
2732 | ||
2733 | local_irq_enable(); | |
36241b8c | 2734 | |
6aa8b732 | 2735 | asm volatile ( |
80e31d4f AK |
2736 | "push %%"R"bp; \n\t" |
2737 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
2738 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
2739 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
2740 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
2741 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
2742 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 2743 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2744 | "mov %c[r8](%[svm]), %%r8 \n\t" |
2745 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
2746 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
2747 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
2748 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
2749 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
2750 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
2751 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
2752 | #endif |
2753 | ||
6aa8b732 | 2754 | /* Enter guest mode */ |
80e31d4f AK |
2755 | "push %%"R"ax \n\t" |
2756 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
2757 | __ex(SVM_VMLOAD) "\n\t" |
2758 | __ex(SVM_VMRUN) "\n\t" | |
2759 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 2760 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
2761 | |
2762 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
2763 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
2764 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
2765 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
2766 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
2767 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
2768 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 2769 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2770 | "mov %%r8, %c[r8](%[svm]) \n\t" |
2771 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
2772 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
2773 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
2774 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
2775 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
2776 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
2777 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 2778 | #endif |
80e31d4f | 2779 | "pop %%"R"bp" |
6aa8b732 | 2780 | : |
fb3f0f51 | 2781 | : [svm]"a"(svm), |
6aa8b732 | 2782 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
2783 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
2784 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
2785 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
2786 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
2787 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
2788 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 2789 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2790 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
2791 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
2792 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
2793 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
2794 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
2795 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
2796 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
2797 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 2798 | #endif |
54a08c04 | 2799 | : "cc", "memory" |
80e31d4f | 2800 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 2801 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
2802 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
2803 | #endif | |
2804 | ); | |
6aa8b732 | 2805 | |
ad312c7c | 2806 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5fdbf976 MT |
2807 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
2808 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
2809 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
6aa8b732 | 2810 | |
d6e88aec AK |
2811 | kvm_load_fs(fs_selector); |
2812 | kvm_load_gs(gs_selector); | |
2813 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
2814 | load_host_msrs(vcpu); |
2815 | ||
2816 | reload_tss(vcpu); | |
2817 | ||
56ba47dd AK |
2818 | local_irq_disable(); |
2819 | ||
2820 | stgi(); | |
2821 | ||
d7bf8221 JR |
2822 | sync_cr8_to_lapic(vcpu); |
2823 | ||
a2fa3e9f | 2824 | svm->next_rip = 0; |
9222be18 | 2825 | |
6de4f3ad AK |
2826 | if (npt_enabled) { |
2827 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
2828 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
2829 | } | |
6aa8b732 AK |
2830 | } |
2831 | ||
80e31d4f AK |
2832 | #undef R |
2833 | ||
6aa8b732 AK |
2834 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
2835 | { | |
a2fa3e9f GH |
2836 | struct vcpu_svm *svm = to_svm(vcpu); |
2837 | ||
709ddebf JR |
2838 | if (npt_enabled) { |
2839 | svm->vmcb->control.nested_cr3 = root; | |
2840 | force_new_asid(vcpu); | |
2841 | return; | |
2842 | } | |
2843 | ||
a2fa3e9f | 2844 | svm->vmcb->save.cr3 = root; |
6aa8b732 AK |
2845 | force_new_asid(vcpu); |
2846 | } | |
2847 | ||
6aa8b732 AK |
2848 | static int is_disabled(void) |
2849 | { | |
6031a61c JR |
2850 | u64 vm_cr; |
2851 | ||
2852 | rdmsrl(MSR_VM_CR, vm_cr); | |
2853 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
2854 | return 1; | |
2855 | ||
6aa8b732 AK |
2856 | return 0; |
2857 | } | |
2858 | ||
102d8325 IM |
2859 | static void |
2860 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2861 | { | |
2862 | /* | |
2863 | * Patch in the VMMCALL instruction: | |
2864 | */ | |
2865 | hypercall[0] = 0x0f; | |
2866 | hypercall[1] = 0x01; | |
2867 | hypercall[2] = 0xd9; | |
102d8325 IM |
2868 | } |
2869 | ||
002c7f7c YS |
2870 | static void svm_check_processor_compat(void *rtn) |
2871 | { | |
2872 | *(int *)rtn = 0; | |
2873 | } | |
2874 | ||
774ead3a AK |
2875 | static bool svm_cpu_has_accelerated_tpr(void) |
2876 | { | |
2877 | return false; | |
2878 | } | |
2879 | ||
67253af5 SY |
2880 | static int get_npt_level(void) |
2881 | { | |
2882 | #ifdef CONFIG_X86_64 | |
2883 | return PT64_ROOT_LEVEL; | |
2884 | #else | |
2885 | return PT32E_ROOT_LEVEL; | |
2886 | #endif | |
2887 | } | |
2888 | ||
4b12f0de | 2889 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
2890 | { |
2891 | return 0; | |
2892 | } | |
2893 | ||
0e851880 SY |
2894 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
2895 | { | |
2896 | } | |
2897 | ||
229456fc MT |
2898 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
2899 | { SVM_EXIT_READ_CR0, "read_cr0" }, | |
2900 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
2901 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
2902 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
2903 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
2904 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
2905 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
2906 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
2907 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
2908 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
2909 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
2910 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
2911 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
2912 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
2913 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
2914 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
2915 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
2916 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
2917 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, | |
2918 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
2919 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
2920 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
2921 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
2922 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
2923 | { SVM_EXIT_INTR, "interrupt" }, | |
2924 | { SVM_EXIT_NMI, "nmi" }, | |
2925 | { SVM_EXIT_SMI, "smi" }, | |
2926 | { SVM_EXIT_INIT, "init" }, | |
2927 | { SVM_EXIT_VINTR, "vintr" }, | |
2928 | { SVM_EXIT_CPUID, "cpuid" }, | |
2929 | { SVM_EXIT_INVD, "invd" }, | |
2930 | { SVM_EXIT_HLT, "hlt" }, | |
2931 | { SVM_EXIT_INVLPG, "invlpg" }, | |
2932 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
2933 | { SVM_EXIT_IOIO, "io" }, | |
2934 | { SVM_EXIT_MSR, "msr" }, | |
2935 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
2936 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
2937 | { SVM_EXIT_VMRUN, "vmrun" }, | |
2938 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
2939 | { SVM_EXIT_VMLOAD, "vmload" }, | |
2940 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
2941 | { SVM_EXIT_STGI, "stgi" }, | |
2942 | { SVM_EXIT_CLGI, "clgi" }, | |
2943 | { SVM_EXIT_SKINIT, "skinit" }, | |
2944 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
2945 | { SVM_EXIT_MONITOR, "monitor" }, | |
2946 | { SVM_EXIT_MWAIT, "mwait" }, | |
2947 | { SVM_EXIT_NPF, "npf" }, | |
2948 | { -1, NULL } | |
2949 | }; | |
2950 | ||
17cc3935 | 2951 | static int svm_get_lpage_level(void) |
344f414f | 2952 | { |
17cc3935 | 2953 | return PT_PDPE_LEVEL; |
344f414f JR |
2954 | } |
2955 | ||
4e47c7a6 SY |
2956 | static bool svm_rdtscp_supported(void) |
2957 | { | |
2958 | return false; | |
2959 | } | |
2960 | ||
02daab21 AK |
2961 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
2962 | { | |
2963 | struct vcpu_svm *svm = to_svm(vcpu); | |
2964 | ||
d225157b | 2965 | update_cr0_intercept(svm); |
02daab21 | 2966 | svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR; |
02daab21 AK |
2967 | } |
2968 | ||
cbdd1bea | 2969 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
2970 | .cpu_has_kvm_support = has_svm, |
2971 | .disabled_by_bios = is_disabled, | |
2972 | .hardware_setup = svm_hardware_setup, | |
2973 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 2974 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
2975 | .hardware_enable = svm_hardware_enable, |
2976 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 2977 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
2978 | |
2979 | .vcpu_create = svm_create_vcpu, | |
2980 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 2981 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 2982 | |
04d2cc77 | 2983 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
2984 | .vcpu_load = svm_vcpu_load, |
2985 | .vcpu_put = svm_vcpu_put, | |
2986 | ||
2987 | .set_guest_debug = svm_guest_debug, | |
2988 | .get_msr = svm_get_msr, | |
2989 | .set_msr = svm_set_msr, | |
2990 | .get_segment_base = svm_get_segment_base, | |
2991 | .get_segment = svm_get_segment, | |
2992 | .set_segment = svm_set_segment, | |
2e4d2653 | 2993 | .get_cpl = svm_get_cpl, |
1747fb71 | 2994 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 2995 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
25c4c276 | 2996 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 2997 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
2998 | .set_cr3 = svm_set_cr3, |
2999 | .set_cr4 = svm_set_cr4, | |
3000 | .set_efer = svm_set_efer, | |
3001 | .get_idt = svm_get_idt, | |
3002 | .set_idt = svm_set_idt, | |
3003 | .get_gdt = svm_get_gdt, | |
3004 | .set_gdt = svm_set_gdt, | |
3005 | .get_dr = svm_get_dr, | |
3006 | .set_dr = svm_set_dr, | |
6de4f3ad | 3007 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
3008 | .get_rflags = svm_get_rflags, |
3009 | .set_rflags = svm_set_rflags, | |
6b52d186 | 3010 | .fpu_activate = svm_fpu_activate, |
02daab21 | 3011 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 3012 | |
6aa8b732 | 3013 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 3014 | |
6aa8b732 | 3015 | .run = svm_vcpu_run, |
04d2cc77 | 3016 | .handle_exit = handle_exit, |
6aa8b732 | 3017 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
3018 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
3019 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 3020 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 3021 | .set_irq = svm_set_irq, |
95ba8273 | 3022 | .set_nmi = svm_inject_nmi, |
298101da | 3023 | .queue_exception = svm_queue_exception, |
78646121 | 3024 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 3025 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
3026 | .get_nmi_mask = svm_get_nmi_mask, |
3027 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
3028 | .enable_nmi_window = enable_nmi_window, |
3029 | .enable_irq_window = enable_irq_window, | |
3030 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
3031 | |
3032 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 3033 | .get_tdp_level = get_npt_level, |
4b12f0de | 3034 | .get_mt_mask = svm_get_mt_mask, |
229456fc MT |
3035 | |
3036 | .exit_reasons_str = svm_exit_reasons_str, | |
17cc3935 | 3037 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
3038 | |
3039 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
3040 | |
3041 | .rdtscp_supported = svm_rdtscp_supported, | |
6aa8b732 AK |
3042 | }; |
3043 | ||
3044 | static int __init svm_init(void) | |
3045 | { | |
cb498ea2 | 3046 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 3047 | THIS_MODULE); |
6aa8b732 AK |
3048 | } |
3049 | ||
3050 | static void __exit svm_exit(void) | |
3051 | { | |
cb498ea2 | 3052 | kvm_exit(); |
6aa8b732 AK |
3053 | } |
3054 | ||
3055 | module_init(svm_init) | |
3056 | module_exit(svm_exit) |