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KVM: x86 emulator: Add new mode of instruction emulation: skip
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
e495606d 18#include "kvm_svm.h"
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f
EH		 32#include <asm/virtext.h>
33
4ecac3fd
AK		 34#define __ex(x) __kvm_handle_fault_on_reboot(x)
35
6aa8b732
AK		 36MODULE_AUTHOR("Qumranet");
37MODULE_LICENSE("GPL");
38
39#define IOPM_ALLOC_ORDER 2
40#define MSRPM_ALLOC_ORDER 1
41
6aa8b732
AK		 42#define SEG_TYPE_LDT 2
43#define SEG_TYPE_BUSY_TSS16 3
44
80b7706e
JR		 45#define SVM_FEATURE_NPT (1 << 0)
46#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 47#define SVM_FEATURE_SVML (1 << 2)
80b7706e 48
24e09cbf
JR		 49#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
50
c0725420
AG		 51/* Turn on to get debugging output*/
52/* #define NESTED_DEBUG */
53
54#ifdef NESTED_DEBUG
55#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
56#else
57#define nsvm_printk(fmt, args...) do {} while(0)
58#endif
59
709ddebf
JR		 60/* enable NPT for AMD64 and X86 with PAE */
61#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
62static bool npt_enabled = true;
63#else
e3da3acd 64static bool npt_enabled = false;
709ddebf 65#endif
6c7dac72
JR		 66static int npt = 1;
67
68module_param(npt, int, S_IRUGO);
e3da3acd 69
236de055
AG		 70static int nested = 0;
71module_param(nested, int, S_IRUGO);
72
04d2cc77 73static void kvm_reput_irq(struct vcpu_svm *svm);
44874f84 74static void svm_flush_tlb(struct kvm_vcpu *vcpu);
04d2cc77 75
cf74a78b
AG		 76static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
77static int nested_svm_vmexit(struct vcpu_svm *svm);
78static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
79 void *arg2, void *opaque);
80static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
81 bool has_error_code, u32 error_code);
82
a2fa3e9f
GH		 83static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
84{
fb3f0f51 85 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 86}
87
3d6368ef
AG		 88static inline bool is_nested(struct vcpu_svm *svm)
89{
90 return svm->nested_vmcb;
91}
92
4866d5e3 93static unsigned long iopm_base;
6aa8b732
AK		 94
95struct kvm_ldttss_desc {
96 u16 limit0;
97 u16 base0;
98 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
99 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
100 u32 base3;
101 u32 zero1;
102} __attribute__((packed));
103
104struct svm_cpu_data {
105 int cpu;
106
5008fdf5
AK		 107 u64 asid_generation;
108 u32 max_asid;
109 u32 next_asid;
6aa8b732
AK		 110 struct kvm_ldttss_desc *tss_desc;
111
112 struct page *save_area;
113};
114
115static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 116static uint32_t svm_features;
6aa8b732
AK		 117
118struct svm_init_data {
119 int cpu;
120 int r;
121};
122
123static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
124
9d8f549d 125#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 126#define MSRS_RANGE_SIZE 2048
127#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
128
129#define MAX_INST_SIZE 15
130
80b7706e
JR		 131static inline u32 svm_has(u32 feat)
132{
133 return svm_features & feat;
134}
135
6aa8b732
AK		 136static inline void clgi(void)
137{
4ecac3fd 138 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 139}
140
141static inline void stgi(void)
142{
4ecac3fd 143 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 144}
145
146static inline void invlpga(unsigned long addr, u32 asid)
147{
4ecac3fd 148 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 149}
150
151static inline unsigned long kvm_read_cr2(void)
152{
153 unsigned long cr2;
154
155 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
156 return cr2;
157}
158
159static inline void kvm_write_cr2(unsigned long val)
160{
161 asm volatile ("mov %0, %%cr2" :: "r" (val));
162}
163
6aa8b732
AK		 164static inline void force_new_asid(struct kvm_vcpu *vcpu)
165{
a2fa3e9f 166 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 167}
168
169static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
170{
171 force_new_asid(vcpu);
172}
173
174static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
175{
709ddebf 176 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 177 efer &= ~EFER_LME;
6aa8b732 178
9962d032 179 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 180 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 181}
182
298101da
AK		 183static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
184 bool has_error_code, u32 error_code)
185{
186 struct vcpu_svm *svm = to_svm(vcpu);
187
cf74a78b
AG		 188 /* If we are within a nested VM we'd better #VMEXIT and let the
189 guest handle the exception */
190 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
191 return;
192
298101da
AK		 193 svm->vmcb->control.event_inj = nr
194 | SVM_EVTINJ_VALID
195 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
196 | SVM_EVTINJ_TYPE_EXEPT;
197 svm->vmcb->control.event_inj_err = error_code;
198}
199
200static bool svm_exception_injected(struct kvm_vcpu *vcpu)
201{
202 struct vcpu_svm *svm = to_svm(vcpu);
203
204 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
205}
206
6aa8b732
AK		 207static int is_external_interrupt(u32 info)
208{
209 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
210 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
211}
212
213static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
214{
a2fa3e9f
GH		 215 struct vcpu_svm *svm = to_svm(vcpu);
216
217 if (!svm->next_rip) {
b8688d51 218 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 219 return;
220 }
5fdbf976
MT		 221 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
222 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
223 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 224
5fdbf976 225 kvm_rip_write(vcpu, svm->next_rip);
a2fa3e9f 226 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
c1150d8c 227
1371d904 228 vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
6aa8b732
AK		 229}
230
231static int has_svm(void)
232{
63d1142f 233 const char *msg;
6aa8b732 234
63d1142f 235 if (!cpu_has_svm(&msg)) {
ff81ff10 236 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 237 return 0;
238 }
239
6aa8b732
AK		 240 return 1;
241}
242
243static void svm_hardware_disable(void *garbage)
244{
2c8dceeb 245 cpu_svm_disable();
6aa8b732
AK		 246}
247
248static void svm_hardware_enable(void *garbage)
249{
250
251 struct svm_cpu_data *svm_data;
252 uint64_t efer;
6aa8b732 253 struct desc_ptr gdt_descr;
6aa8b732
AK		 254 struct desc_struct *gdt;
255 int me = raw_smp_processor_id();
256
257 if (!has_svm()) {
258 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
259 return;
260 }
261 svm_data = per_cpu(svm_data, me);
262
263 if (!svm_data) {
264 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
265 me);
266 return;
267 }
268
269 svm_data->asid_generation = 1;
270 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
271 svm_data->next_asid = svm_data->max_asid + 1;
272
d77c26fc 273 asm volatile ("sgdt %0" : "=m"(gdt_descr));
6aa8b732
AK		 274 gdt = (struct desc_struct *)gdt_descr.address;
275 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
276
277 rdmsrl(MSR_EFER, efer);
9962d032 278 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 279
280 wrmsrl(MSR_VM_HSAVE_PA,
281 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
282}
283
0da1db75
JR		 284static void svm_cpu_uninit(int cpu)
285{
286 struct svm_cpu_data *svm_data
287 = per_cpu(svm_data, raw_smp_processor_id());
288
289 if (!svm_data)
290 return;
291
292 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
293 __free_page(svm_data->save_area);
294 kfree(svm_data);
295}
296
6aa8b732
AK		 297static int svm_cpu_init(int cpu)
298{
299 struct svm_cpu_data *svm_data;
300 int r;
301
302 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
303 if (!svm_data)
304 return -ENOMEM;
305 svm_data->cpu = cpu;
306 svm_data->save_area = alloc_page(GFP_KERNEL);
307 r = -ENOMEM;
308 if (!svm_data->save_area)
309 goto err_1;
310
311 per_cpu(svm_data, cpu) = svm_data;
312
313 return 0;
314
315err_1:
316 kfree(svm_data);
317 return r;
318
319}
320
bfc733a7
RR		 321static void set_msr_interception(u32 *msrpm, unsigned msr,
322 int read, int write)
6aa8b732
AK		 323{
324 int i;
325
326 for (i = 0; i < NUM_MSR_MAPS; i++) {
327 if (msr >= msrpm_ranges[i] &&
328 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
329 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
330 msrpm_ranges[i]) * 2;
331
332 u32 *base = msrpm + (msr_offset / 32);
333 u32 msr_shift = msr_offset % 32;
334 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
335 *base = (*base & ~(0x3 << msr_shift)) |
336 (mask << msr_shift);
bfc733a7 337 return;
6aa8b732
AK		 338 }
339 }
bfc733a7 340 BUG();
6aa8b732
AK		 341}
342
f65c229c
JR		 343static void svm_vcpu_init_msrpm(u32 *msrpm)
344{
345 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
346
347#ifdef CONFIG_X86_64
348 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
349 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
350 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
351 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
352 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
353 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
354#endif
355 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
356 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
357 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
358 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
359}
360
24e09cbf
JR		 361static void svm_enable_lbrv(struct vcpu_svm *svm)
362{
363 u32 *msrpm = svm->msrpm;
364
365 svm->vmcb->control.lbr_ctl = 1;
366 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
367 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
368 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
369 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
370}
371
372static void svm_disable_lbrv(struct vcpu_svm *svm)
373{
374 u32 *msrpm = svm->msrpm;
375
376 svm->vmcb->control.lbr_ctl = 0;
377 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
378 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
379 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
380 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
381}
382
6aa8b732
AK		 383static __init int svm_hardware_setup(void)
384{
385 int cpu;
386 struct page *iopm_pages;
f65c229c 387 void *iopm_va;
6aa8b732
AK		 388 int r;
389
6aa8b732
AK		 390 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
391
392 if (!iopm_pages)
393 return -ENOMEM;
c8681339
AL		 394
395 iopm_va = page_address(iopm_pages);
396 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 397 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
398
50a37eb4
JR		 399 if (boot_cpu_has(X86_FEATURE_NX))
400 kvm_enable_efer_bits(EFER_NX);
401
1b2fd70c
AG		 402 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
403 kvm_enable_efer_bits(EFER_FFXSR);
404
236de055
AG		 405 if (nested) {
406 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
407 kvm_enable_efer_bits(EFER_SVME);
408 }
409
6aa8b732
AK		 410 for_each_online_cpu(cpu) {
411 r = svm_cpu_init(cpu);
412 if (r)
f65c229c 413 goto err;
6aa8b732 414 }
33bd6a0b
JR		 415
416 svm_features = cpuid_edx(SVM_CPUID_FUNC);
417
e3da3acd
JR		 418 if (!svm_has(SVM_FEATURE_NPT))
419 npt_enabled = false;
420
6c7dac72
JR		 421 if (npt_enabled && !npt) {
422 printk(KERN_INFO "kvm: Nested Paging disabled\n");
423 npt_enabled = false;
424 }
425
18552672 426 if (npt_enabled) {
e3da3acd 427 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 428 kvm_enable_tdp();
5f4cb662
JR		 429 } else
430 kvm_disable_tdp();
e3da3acd 431
6aa8b732
AK		 432 return 0;
433
f65c229c 434err:
6aa8b732
AK		 435 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
436 iopm_base = 0;
437 return r;
438}
439
440static __exit void svm_hardware_unsetup(void)
441{
0da1db75
JR		 442 int cpu;
443
444 for_each_online_cpu(cpu)
445 svm_cpu_uninit(cpu);
446
6aa8b732 447 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 448 iopm_base = 0;
6aa8b732
AK		 449}
450
451static void init_seg(struct vmcb_seg *seg)
452{
453 seg->selector = 0;
454 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
455 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
456 seg->limit = 0xffff;
457 seg->base = 0;
458}
459
460static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
461{
462 seg->selector = 0;
463 seg->attrib = SVM_SELECTOR_P_MASK | type;
464 seg->limit = 0xffff;
465 seg->base = 0;
466}
467
e6101a96 468static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 469{
e6101a96
JR		 470 struct vmcb_control_area *control = &svm->vmcb->control;
471 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 472
473 control->intercept_cr_read = INTERCEPT_CR0_MASK |
474 INTERCEPT_CR3_MASK |
649d6864 475 INTERCEPT_CR4_MASK;
6aa8b732
AK		 476
477 control->intercept_cr_write = INTERCEPT_CR0_MASK |
478 INTERCEPT_CR3_MASK |
80a8119c
AK		 479 INTERCEPT_CR4_MASK |
480 INTERCEPT_CR8_MASK;
6aa8b732
AK		 481
482 control->intercept_dr_read = INTERCEPT_DR0_MASK |
483 INTERCEPT_DR1_MASK |
484 INTERCEPT_DR2_MASK |
485 INTERCEPT_DR3_MASK;
486
487 control->intercept_dr_write = INTERCEPT_DR0_MASK |
488 INTERCEPT_DR1_MASK |
489 INTERCEPT_DR2_MASK |
490 INTERCEPT_DR3_MASK |
491 INTERCEPT_DR5_MASK |
492 INTERCEPT_DR7_MASK;
493
7aa81cc0 494 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 495 (1 << UD_VECTOR) |
496 (1 << MC_VECTOR);
6aa8b732
AK		 497
498
499 control->intercept = (1ULL << INTERCEPT_INTR) |
500 (1ULL << INTERCEPT_NMI) |
0152527b 501 (1ULL << INTERCEPT_SMI) |
6aa8b732 502 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 503 (1ULL << INTERCEPT_INVD) |
6aa8b732 504 (1ULL << INTERCEPT_HLT) |
a7052897 505 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 506 (1ULL << INTERCEPT_INVLPGA) |
507 (1ULL << INTERCEPT_IOIO_PROT) |
508 (1ULL << INTERCEPT_MSR_PROT) |
509 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 510 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 511 (1ULL << INTERCEPT_VMRUN) |
512 (1ULL << INTERCEPT_VMMCALL) |
513 (1ULL << INTERCEPT_VMLOAD) |
514 (1ULL << INTERCEPT_VMSAVE) |
515 (1ULL << INTERCEPT_STGI) |
516 (1ULL << INTERCEPT_CLGI) |
916ce236 517 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 518 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 519 (1ULL << INTERCEPT_MONITOR) |
520 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 521
522 control->iopm_base_pa = iopm_base;
f65c229c 523 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 524 control->tsc_offset = 0;
6aa8b732
AK		 525 control->int_ctl = V_INTR_MASKING_MASK;
526
527 init_seg(&save->es);
528 init_seg(&save->ss);
529 init_seg(&save->ds);
530 init_seg(&save->fs);
531 init_seg(&save->gs);
532
533 save->cs.selector = 0xf000;
534 /* Executable/Readable Code Segment */
535 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
536 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
537 save->cs.limit = 0xffff;
d92899a0
AK		 538 /*
539 * cs.base should really be 0xffff0000, but vmx can't handle that, so
540 * be consistent with it.
541 *
542 * Replace when we have real mode working for vmx.
543 */
544 save->cs.base = 0xf0000;
6aa8b732
AK		 545
546 save->gdtr.limit = 0xffff;
547 save->idtr.limit = 0xffff;
548
549 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
550 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
551
9962d032 552 save->efer = EFER_SVME;
d77c26fc 553 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 554 save->dr7 = 0x400;
555 save->rflags = 2;
556 save->rip = 0x0000fff0;
5fdbf976 557 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 558
559 /*
560 * cr0 val on cpu init should be 0x60000010, we enable cpu
561 * cache by default. the orderly way is to enable cache in bios.
562 */
707d92fa 563 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 564 save->cr4 = X86_CR4_PAE;
6aa8b732 565 /* rdx = ?? */
709ddebf
JR		 566
567 if (npt_enabled) {
568 /* Setup VMCB for Nested Paging */
569 control->nested_ctl = 1;
a7052897
MT		 570 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
571 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 572 control->intercept_exceptions &= ~(1 << PF_VECTOR);
573 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
574 INTERCEPT_CR3_MASK);
575 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
576 INTERCEPT_CR3_MASK);
577 save->g_pat = 0x0007040600070406ULL;
578 /* enable caching because the QEMU Bios doesn't enable it */
579 save->cr0 = X86_CR0_ET;
580 save->cr3 = 0;
581 save->cr4 = 0;
582 }
a79d2f18 583 force_new_asid(&svm->vcpu);
1371d904 584
3d6368ef 585 svm->nested_vmcb = 0;
1371d904 586 svm->vcpu.arch.hflags = HF_GIF_MASK;
6aa8b732
AK		 587}
588
e00c8cf2 589static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 590{
591 struct vcpu_svm *svm = to_svm(vcpu);
592
e6101a96 593 init_vmcb(svm);
70433389
AK		 594
595 if (vcpu->vcpu_id != 0) {
5fdbf976 596 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 597 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
598 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 599 }
5fdbf976
MT		 600 vcpu->arch.regs_avail = ~0;
601 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 602
603 return 0;
04d2cc77
AK		 604}
605
fb3f0f51 606static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 607{
a2fa3e9f 608 struct vcpu_svm *svm;
6aa8b732 609 struct page *page;
f65c229c 610 struct page *msrpm_pages;
b286d5d8 611 struct page *hsave_page;
3d6368ef 612 struct page *nested_msrpm_pages;
fb3f0f51 613 int err;
6aa8b732 614
c16f862d 615 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 616 if (!svm) {
617 err = -ENOMEM;
618 goto out;
619 }
620
621 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
622 if (err)
623 goto free_svm;
624
6aa8b732 625 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 626 if (!page) {
627 err = -ENOMEM;
628 goto uninit;
629 }
6aa8b732 630
f65c229c
JR		 631 err = -ENOMEM;
632 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
633 if (!msrpm_pages)
634 goto uninit;
3d6368ef
AG		 635
636 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
637 if (!nested_msrpm_pages)
638 goto uninit;
639
f65c229c
JR		 640 svm->msrpm = page_address(msrpm_pages);
641 svm_vcpu_init_msrpm(svm->msrpm);
642
b286d5d8
AG		 643 hsave_page = alloc_page(GFP_KERNEL);
644 if (!hsave_page)
645 goto uninit;
646 svm->hsave = page_address(hsave_page);
647
3d6368ef
AG		 648 svm->nested_msrpm = page_address(nested_msrpm_pages);
649
a2fa3e9f
GH		 650 svm->vmcb = page_address(page);
651 clear_page(svm->vmcb);
652 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
653 svm->asid_generation = 0;
e6101a96 654 init_vmcb(svm);
a2fa3e9f 655
fb3f0f51
RR		 656 fx_init(&svm->vcpu);
657 svm->vcpu.fpu_active = 1;
ad312c7c 658 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
fb3f0f51 659 if (svm->vcpu.vcpu_id == 0)
ad312c7c 660 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 661
fb3f0f51 662 return &svm->vcpu;
36241b8c 663
fb3f0f51
RR		 664uninit:
665 kvm_vcpu_uninit(&svm->vcpu);
666free_svm:
a4770347 667 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 668out:
669 return ERR_PTR(err);
6aa8b732
AK		 670}
671
672static void svm_free_vcpu(struct kvm_vcpu *vcpu)
673{
a2fa3e9f
GH		 674 struct vcpu_svm *svm = to_svm(vcpu);
675
fb3f0f51 676 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 677 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
b286d5d8 678 __free_page(virt_to_page(svm->hsave));
3d6368ef 679 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 680 kvm_vcpu_uninit(vcpu);
a4770347 681 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 682}
683
15ad7146 684static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 685{
a2fa3e9f 686 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 687 int i;
0cc5064d 688
0cc5064d
AK		 689 if (unlikely(cpu != vcpu->cpu)) {
690 u64 tsc_this, delta;
691
692 /*
693 * Make sure that the guest sees a monotonically
694 * increasing TSC.
695 */
696 rdtscll(tsc_this);
ad312c7c 697 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 698 svm->vmcb->control.tsc_offset += delta;
0cc5064d 699 vcpu->cpu = cpu;
2f599714 700 kvm_migrate_timers(vcpu);
0cc5064d 701 }
94dfbdb3
AL		 702
703 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 704 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 705}
706
707static void svm_vcpu_put(struct kvm_vcpu *vcpu)
708{
a2fa3e9f 709 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 710 int i;
711
e1beb1d3 712 ++vcpu->stat.host_state_reload;
94dfbdb3 713 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 714 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 715
ad312c7c 716 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 717}
718
6aa8b732
AK		 719static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
720{
a2fa3e9f 721 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 722}
723
724static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
725{
a2fa3e9f 726 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 727}
728
f0b85051
AG		 729static void svm_set_vintr(struct vcpu_svm *svm)
730{
731 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
732}
733
734static void svm_clear_vintr(struct vcpu_svm *svm)
735{
736 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
737}
738
6aa8b732
AK		 739static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
740{
a2fa3e9f 741 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 742
743 switch (seg) {
744 case VCPU_SREG_CS: return &save->cs;
745 case VCPU_SREG_DS: return &save->ds;
746 case VCPU_SREG_ES: return &save->es;
747 case VCPU_SREG_FS: return &save->fs;
748 case VCPU_SREG_GS: return &save->gs;
749 case VCPU_SREG_SS: return &save->ss;
750 case VCPU_SREG_TR: return &save->tr;
751 case VCPU_SREG_LDTR: return &save->ldtr;
752 }
753 BUG();
8b6d44c7 754 return NULL;
6aa8b732
AK		 755}
756
757static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
758{
759 struct vmcb_seg *s = svm_seg(vcpu, seg);
760
761 return s->base;
762}
763
764static void svm_get_segment(struct kvm_vcpu *vcpu,
765 struct kvm_segment *var, int seg)
766{
767 struct vmcb_seg *s = svm_seg(vcpu, seg);
768
769 var->base = s->base;
770 var->limit = s->limit;
771 var->selector = s->selector;
772 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
773 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
774 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
775 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
776 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
777 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
778 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
779 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 780
19bca6ab
AP		 781 /* AMD's VMCB does not have an explicit unusable field, so emulate it
782 * for cross vendor migration purposes by "not present"
783 */
784 var->unusable = !var->present || (var->type == 0);
785
1fbdc7a5
AP		 786 switch (seg) {
787 case VCPU_SREG_CS:
788 /*
789 * SVM always stores 0 for the 'G' bit in the CS selector in
790 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
791 * Intel's VMENTRY has a check on the 'G' bit.
792 */
25022acc 793 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 794 break;
795 case VCPU_SREG_TR:
796 /*
797 * Work around a bug where the busy flag in the tr selector
798 * isn't exposed
799 */
c0d09828 800 var->type |= 0x2;
1fbdc7a5
AP		 801 break;
802 case VCPU_SREG_DS:
803 case VCPU_SREG_ES:
804 case VCPU_SREG_FS:
805 case VCPU_SREG_GS:
806 /*
807 * The accessed bit must always be set in the segment
808 * descriptor cache, although it can be cleared in the
809 * descriptor, the cached bit always remains at 1. Since
810 * Intel has a check on this, set it here to support
811 * cross-vendor migration.
812 */
813 if (!var->unusable)
814 var->type |= 0x1;
815 break;
816 }
6aa8b732
AK		 817}
818
2e4d2653
IE		 819static int svm_get_cpl(struct kvm_vcpu *vcpu)
820{
821 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
822
823 return save->cpl;
824}
825
6aa8b732
AK		 826static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
827{
a2fa3e9f
GH		 828 struct vcpu_svm *svm = to_svm(vcpu);
829
830 dt->limit = svm->vmcb->save.idtr.limit;
831 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 832}
833
834static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
835{
a2fa3e9f
GH		 836 struct vcpu_svm *svm = to_svm(vcpu);
837
838 svm->vmcb->save.idtr.limit = dt->limit;
839 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 840}
841
842static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
843{
a2fa3e9f
GH		 844 struct vcpu_svm *svm = to_svm(vcpu);
845
846 dt->limit = svm->vmcb->save.gdtr.limit;
847 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 848}
849
850static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
851{
a2fa3e9f
GH		 852 struct vcpu_svm *svm = to_svm(vcpu);
853
854 svm->vmcb->save.gdtr.limit = dt->limit;
855 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 856}
857
25c4c276 858static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 859{
860}
861
6aa8b732
AK		 862static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
863{
a2fa3e9f
GH		 864 struct vcpu_svm *svm = to_svm(vcpu);
865
05b3e0c2 866#ifdef CONFIG_X86_64
ad312c7c 867 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 868 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 869 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 870 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 871 }
872
d77c26fc 873 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 874 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 875 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 876 }
877 }
878#endif
709ddebf
JR		 879 if (npt_enabled)
880 goto set;
881
ad312c7c 882 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 883 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 884 vcpu->fpu_active = 1;
885 }
886
ad312c7c 887 vcpu->arch.cr0 = cr0;
707d92fa 888 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 889 if (!vcpu->fpu_active) {
890 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 891 cr0 |= X86_CR0_TS;
6b390b63 892 }
709ddebf
JR		 893set:
894 /*
895 * re-enable caching here because the QEMU bios
896 * does not do it - this results in some delay at
897 * reboot
898 */
899 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 900 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 901}
902
903static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
904{
6394b649 905 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 906 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
907
908 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
909 force_new_asid(vcpu);
6394b649 910
ec077263
JR		 911 vcpu->arch.cr4 = cr4;
912 if (!npt_enabled)
913 cr4 |= X86_CR4_PAE;
6394b649 914 cr4 |= host_cr4_mce;
ec077263 915 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 916}
917
918static void svm_set_segment(struct kvm_vcpu *vcpu,
919 struct kvm_segment *var, int seg)
920{
a2fa3e9f 921 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 922 struct vmcb_seg *s = svm_seg(vcpu, seg);
923
924 s->base = var->base;
925 s->limit = var->limit;
926 s->selector = var->selector;
927 if (var->unusable)
928 s->attrib = 0;
929 else {
930 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
931 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
932 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
933 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
934 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
935 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
936 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
937 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
938 }
939 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 940 svm->vmcb->save.cpl
941 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 942 >> SVM_SELECTOR_DPL_SHIFT) & 3;
943
944}
945
d0bfb940 946static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 947{
d0bfb940
JK		 948 int old_debug = vcpu->guest_debug;
949 struct vcpu_svm *svm = to_svm(vcpu);
950
951 vcpu->guest_debug = dbg->control;
952
953 svm->vmcb->control.intercept_exceptions &=
954 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
955 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
956 if (vcpu->guest_debug &
957 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
958 svm->vmcb->control.intercept_exceptions |=
959 1 << DB_VECTOR;
960 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
961 svm->vmcb->control.intercept_exceptions |=
962 1 << BP_VECTOR;
963 } else
964 vcpu->guest_debug = 0;
965
ae675ef0
JK		 966 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
967 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
968 else
969 svm->vmcb->save.dr7 = vcpu->arch.dr7;
970
d0bfb940
JK		 971 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
972 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
973 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
974 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
975
976 return 0;
6aa8b732
AK		 977}
978
2a8067f1
ED		 979static int svm_get_irq(struct kvm_vcpu *vcpu)
980{
981 struct vcpu_svm *svm = to_svm(vcpu);
982 u32 exit_int_info = svm->vmcb->control.exit_int_info;
983
984 if (is_external_interrupt(exit_int_info))
985 return exit_int_info & SVM_EVTINJ_VEC_MASK;
986 return -1;
987}
988
6aa8b732
AK		 989static void load_host_msrs(struct kvm_vcpu *vcpu)
990{
94dfbdb3 991#ifdef CONFIG_X86_64
a2fa3e9f 992 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 993#endif
6aa8b732
AK		 994}
995
996static void save_host_msrs(struct kvm_vcpu *vcpu)
997{
94dfbdb3 998#ifdef CONFIG_X86_64
a2fa3e9f 999 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1000#endif
6aa8b732
AK		 1001}
1002
e756fc62 1003static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1004{
1005 if (svm_data->next_asid > svm_data->max_asid) {
1006 ++svm_data->asid_generation;
1007 svm_data->next_asid = 1;
a2fa3e9f 1008 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1009 }
1010
e756fc62 1011 svm->vcpu.cpu = svm_data->cpu;
a2fa3e9f
GH		 1012 svm->asid_generation = svm_data->asid_generation;
1013 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1014}
1015
6aa8b732
AK		 1016static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1017{
42dbaa5a
JK		 1018 struct vcpu_svm *svm = to_svm(vcpu);
1019 unsigned long val;
1020
1021 switch (dr) {
1022 case 0 ... 3:
1023 val = vcpu->arch.db[dr];
1024 break;
1025 case 6:
1026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027 val = vcpu->arch.dr6;
1028 else
1029 val = svm->vmcb->save.dr6;
1030 break;
1031 case 7:
1032 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1033 val = vcpu->arch.dr7;
1034 else
1035 val = svm->vmcb->save.dr7;
1036 break;
1037 default:
1038 val = 0;
1039 }
1040
af9ca2d7
JR		 1041 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1042 return val;
6aa8b732
AK		 1043}
1044
1045static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1046 int *exception)
1047{
a2fa3e9f
GH		 1048 struct vcpu_svm *svm = to_svm(vcpu);
1049
42dbaa5a 1050 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
6aa8b732 1051
42dbaa5a 1052 *exception = 0;
6aa8b732
AK		 1053
1054 switch (dr) {
1055 case 0 ... 3:
42dbaa5a
JK		 1056 vcpu->arch.db[dr] = value;
1057 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1058 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1059 return;
1060 case 4 ... 5:
42dbaa5a 1061 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1062 *exception = UD_VECTOR;
42dbaa5a
JK		 1063 return;
1064 case 6:
1065 if (value & 0xffffffff00000000ULL) {
1066 *exception = GP_VECTOR;
6aa8b732
AK		 1067 return;
1068 }
42dbaa5a
JK		 1069 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1070 return;
1071 case 7:
1072 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1073 *exception = GP_VECTOR;
1074 return;
1075 }
42dbaa5a
JK		 1076 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1077 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1078 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1079 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1080 }
6aa8b732 1081 return;
6aa8b732 1082 default:
42dbaa5a 1083 /* FIXME: Possible case? */
6aa8b732 1084 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1085 __func__, dr);
6aa8b732
AK		 1086 *exception = UD_VECTOR;
1087 return;
1088 }
1089}
1090
e756fc62 1091static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1092{
a2fa3e9f 1093 u32 exit_int_info = svm->vmcb->control.exit_int_info;
e756fc62 1094 struct kvm *kvm = svm->vcpu.kvm;
6aa8b732
AK		 1095 u64 fault_address;
1096 u32 error_code;
577bdc49 1097 bool event_injection = false;
6aa8b732 1098
85f455f7 1099 if (!irqchip_in_kernel(kvm) &&
577bdc49
AK		 1100 is_external_interrupt(exit_int_info)) {
1101 event_injection = true;
fe4c7b19 1102 kvm_push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
577bdc49 1103 }
6aa8b732 1104
a2fa3e9f
GH		 1105 fault_address = svm->vmcb->control.exit_info_2;
1106 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7
JR		 1107
1108 if (!npt_enabled)
1109 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1110 (u32)fault_address, (u32)(fault_address >> 32),
1111 handler);
d2ebb410
JR		 1112 else
1113 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1114 (u32)fault_address, (u32)(fault_address >> 32),
1115 handler);
44874f84
JR		 1116 /*
1117 * FIXME: Tis shouldn't be necessary here, but there is a flush
1118 * missing in the MMU code. Until we find this bug, flush the
1119 * complete TLB here on an NPF
1120 */
1121 if (npt_enabled)
1122 svm_flush_tlb(&svm->vcpu);
af9ca2d7 1123
48d15039 1124 if (!npt_enabled && event_injection)
577bdc49 1125 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1126 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1127}
1128
d0bfb940
JK		 1129static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1130{
1131 if (!(svm->vcpu.guest_debug &
1132 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1133 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1134 return 1;
1135 }
1136 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1137 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1138 kvm_run->debug.arch.exception = DB_VECTOR;
1139 return 0;
1140}
1141
1142static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1143{
1144 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1145 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1146 kvm_run->debug.arch.exception = BP_VECTOR;
1147 return 0;
1148}
1149
7aa81cc0
AL		 1150static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1151{
1152 int er;
1153
571008da 1154 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1155 if (er != EMULATE_DONE)
7ee5d940 1156 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1157 return 1;
1158}
1159
e756fc62 1160static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1161{
a2fa3e9f 1162 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1163 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1164 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1165 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1166
1167 return 1;
7807fa6c
AL		 1168}
1169
53371b50
JR		 1170static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1171{
1172 /*
1173 * On an #MC intercept the MCE handler is not called automatically in
1174 * the host. So do it by hand here.
1175 */
1176 asm volatile (
1177 "int $0x12\n");
1178 /* not sure if we ever come back to this point */
1179
1180 return 1;
1181}
1182
e756fc62 1183static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1184{
1185 /*
1186 * VMCB is undefined after a SHUTDOWN intercept
1187 * so reinitialize it.
1188 */
a2fa3e9f 1189 clear_page(svm->vmcb);
e6101a96 1190 init_vmcb(svm);
46fe4ddd
JR		 1191
1192 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1193 return 0;
1194}
1195
e756fc62 1196static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1197{
d77c26fc 1198 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1199 int size, in, string;
039576c0 1200 unsigned port;
6aa8b732 1201
e756fc62 1202 ++svm->vcpu.stat.io_exits;
6aa8b732 1203
a2fa3e9f 1204 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1205
e70669ab
LV		 1206 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1207
1208 if (string) {
3427318f
LV		 1209 if (emulate_instruction(&svm->vcpu,
1210 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1211 return 0;
1212 return 1;
1213 }
1214
039576c0
AK		 1215 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1216 port = io_info >> 16;
1217 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1218
e93f36bc 1219 skip_emulated_instruction(&svm->vcpu);
3090dd73 1220 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1221}
1222
c47f098d
JR		 1223static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1224{
af9ca2d7 1225 KVMTRACE_0D(NMI, &svm->vcpu, handler);
c47f098d
JR		 1226 return 1;
1227}
1228
a0698055
JR		 1229static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1230{
1231 ++svm->vcpu.stat.irq_exits;
af9ca2d7 1232 KVMTRACE_0D(INTR, &svm->vcpu, handler);
a0698055
JR		 1233 return 1;
1234}
1235
e756fc62 1236static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1237{
1238 return 1;
1239}
1240
e756fc62 1241static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1242{
5fdbf976 1243 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1244 skip_emulated_instruction(&svm->vcpu);
1245 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1246}
1247
e756fc62 1248static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1249{
5fdbf976 1250 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1251 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1252 kvm_emulate_hypercall(&svm->vcpu);
1253 return 1;
02e235bc
AK		 1254}
1255
c0725420
AG		 1256static int nested_svm_check_permissions(struct vcpu_svm *svm)
1257{
1258 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1259 || !is_paging(&svm->vcpu)) {
1260 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1261 return 1;
1262 }
1263
1264 if (svm->vmcb->save.cpl) {
1265 kvm_inject_gp(&svm->vcpu, 0);
1266 return 1;
1267 }
1268
1269 return 0;
1270}
1271
cf74a78b
AG		 1272static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1273 bool has_error_code, u32 error_code)
1274{
1275 if (is_nested(svm)) {
1276 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1277 svm->vmcb->control.exit_code_hi = 0;
1278 svm->vmcb->control.exit_info_1 = error_code;
1279 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1280 if (nested_svm_exit_handled(svm, false)) {
1281 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1282
1283 nested_svm_vmexit(svm);
1284 return 1;
1285 }
1286 }
1287
1288 return 0;
1289}
1290
1291static inline int nested_svm_intr(struct vcpu_svm *svm)
1292{
1293 if (is_nested(svm)) {
1294 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1295 return 0;
1296
1297 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1298 return 0;
1299
1300 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1301
1302 if (nested_svm_exit_handled(svm, false)) {
1303 nsvm_printk("VMexit -> INTR\n");
1304 nested_svm_vmexit(svm);
1305 return 1;
1306 }
1307 }
1308
1309 return 0;
1310}
1311
c0725420
AG		 1312static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1313{
1314 struct page *page;
1315
1316 down_read(&current->mm->mmap_sem);
1317 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1318 up_read(&current->mm->mmap_sem);
1319
1320 if (is_error_page(page)) {
1321 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1322 __func__, gpa);
1323 kvm_release_page_clean(page);
1324 kvm_inject_gp(&svm->vcpu, 0);
1325 return NULL;
1326 }
1327 return page;
1328}
1329
1330static int nested_svm_do(struct vcpu_svm *svm,
1331 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1332 int (*handler)(struct vcpu_svm *svm,
1333 void *arg1,
1334 void *arg2,
1335 void *opaque))
1336{
1337 struct page *arg1_page;
1338 struct page *arg2_page = NULL;
1339 void *arg1;
1340 void *arg2 = NULL;
1341 int retval;
1342
1343 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1344 if(arg1_page == NULL)
1345 return 1;
1346
1347 if (arg2_gpa) {
1348 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1349 if(arg2_page == NULL) {
1350 kvm_release_page_clean(arg1_page);
1351 return 1;
1352 }
1353 }
1354
1355 arg1 = kmap_atomic(arg1_page, KM_USER0);
1356 if (arg2_gpa)
1357 arg2 = kmap_atomic(arg2_page, KM_USER1);
1358
1359 retval = handler(svm, arg1, arg2, opaque);
1360
1361 kunmap_atomic(arg1, KM_USER0);
1362 if (arg2_gpa)
1363 kunmap_atomic(arg2, KM_USER1);
1364
1365 kvm_release_page_dirty(arg1_page);
1366 if (arg2_gpa)
1367 kvm_release_page_dirty(arg2_page);
1368
1369 return retval;
1370}
1371
cf74a78b
AG		 1372static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1373 void *arg1,
1374 void *arg2,
1375 void *opaque)
1376{
1377 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1378 bool kvm_overrides = *(bool *)opaque;
1379 u32 exit_code = svm->vmcb->control.exit_code;
1380
1381 if (kvm_overrides) {
1382 switch (exit_code) {
1383 case SVM_EXIT_INTR:
1384 case SVM_EXIT_NMI:
1385 return 0;
1386 /* For now we are always handling NPFs when using them */
1387 case SVM_EXIT_NPF:
1388 if (npt_enabled)
1389 return 0;
1390 break;
1391 /* When we're shadowing, trap PFs */
1392 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1393 if (!npt_enabled)
1394 return 0;
1395 break;
1396 default:
1397 break;
1398 }
1399 }
1400
1401 switch (exit_code) {
1402 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1403 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1404 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1405 return 1;
1406 break;
1407 }
1408 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1409 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1410 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1411 return 1;
1412 break;
1413 }
1414 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1415 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1416 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1417 return 1;
1418 break;
1419 }
1420 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1421 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1422 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1423 return 1;
1424 break;
1425 }
1426 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1427 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1428 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1429 return 1;
1430 break;
1431 }
1432 default: {
1433 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1434 nsvm_printk("exit code: 0x%x\n", exit_code);
1435 if (nested_vmcb->control.intercept & exit_bits)
1436 return 1;
1437 }
1438 }
1439
1440 return 0;
1441}
1442
1443static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1444 void *arg1, void *arg2,
1445 void *opaque)
1446{
1447 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1448 u8 *msrpm = (u8 *)arg2;
1449 u32 t0, t1;
1450 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1451 u32 param = svm->vmcb->control.exit_info_1 & 1;
1452
1453 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1454 return 0;
1455
1456 switch(msr) {
1457 case 0 ... 0x1fff:
1458 t0 = (msr * 2) % 8;
1459 t1 = msr / 8;
1460 break;
1461 case 0xc0000000 ... 0xc0001fff:
1462 t0 = (8192 + msr - 0xc0000000) * 2;
1463 t1 = (t0 / 8);
1464 t0 %= 8;
1465 break;
1466 case 0xc0010000 ... 0xc0011fff:
1467 t0 = (16384 + msr - 0xc0010000) * 2;
1468 t1 = (t0 / 8);
1469 t0 %= 8;
1470 break;
1471 default:
1472 return 1;
1473 break;
1474 }
1475 if (msrpm[t1] & ((1 << param) << t0))
1476 return 1;
1477
1478 return 0;
1479}
1480
1481static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1482{
1483 bool k = kvm_override;
1484
1485 switch (svm->vmcb->control.exit_code) {
1486 case SVM_EXIT_MSR:
1487 return nested_svm_do(svm, svm->nested_vmcb,
1488 svm->nested_vmcb_msrpm, NULL,
1489 nested_svm_exit_handled_msr);
1490 default: break;
1491 }
1492
1493 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1494 nested_svm_exit_handled_real);
1495}
1496
1497static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1498 void *arg2, void *opaque)
1499{
1500 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1501 struct vmcb *hsave = svm->hsave;
1502 u64 nested_save[] = { nested_vmcb->save.cr0,
1503 nested_vmcb->save.cr3,
1504 nested_vmcb->save.cr4,
1505 nested_vmcb->save.efer,
1506 nested_vmcb->control.intercept_cr_read,
1507 nested_vmcb->control.intercept_cr_write,
1508 nested_vmcb->control.intercept_dr_read,
1509 nested_vmcb->control.intercept_dr_write,
1510 nested_vmcb->control.intercept_exceptions,
1511 nested_vmcb->control.intercept,
1512 nested_vmcb->control.msrpm_base_pa,
1513 nested_vmcb->control.iopm_base_pa,
1514 nested_vmcb->control.tsc_offset };
1515
1516 /* Give the current vmcb to the guest */
1517 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1518 nested_vmcb->save.cr0 = nested_save[0];
1519 if (!npt_enabled)
1520 nested_vmcb->save.cr3 = nested_save[1];
1521 nested_vmcb->save.cr4 = nested_save[2];
1522 nested_vmcb->save.efer = nested_save[3];
1523 nested_vmcb->control.intercept_cr_read = nested_save[4];
1524 nested_vmcb->control.intercept_cr_write = nested_save[5];
1525 nested_vmcb->control.intercept_dr_read = nested_save[6];
1526 nested_vmcb->control.intercept_dr_write = nested_save[7];
1527 nested_vmcb->control.intercept_exceptions = nested_save[8];
1528 nested_vmcb->control.intercept = nested_save[9];
1529 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1530 nested_vmcb->control.iopm_base_pa = nested_save[11];
1531 nested_vmcb->control.tsc_offset = nested_save[12];
1532
1533 /* We always set V_INTR_MASKING and remember the old value in hflags */
1534 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1535 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1536
1537 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1538 (nested_vmcb->control.int_vector)) {
1539 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1540 nested_vmcb->control.int_vector);
1541 }
1542
1543 /* Restore the original control entries */
1544 svm->vmcb->control = hsave->control;
1545
1546 /* Kill any pending exceptions */
1547 if (svm->vcpu.arch.exception.pending == true)
1548 nsvm_printk("WARNING: Pending Exception\n");
1549 svm->vcpu.arch.exception.pending = false;
1550
1551 /* Restore selected save entries */
1552 svm->vmcb->save.es = hsave->save.es;
1553 svm->vmcb->save.cs = hsave->save.cs;
1554 svm->vmcb->save.ss = hsave->save.ss;
1555 svm->vmcb->save.ds = hsave->save.ds;
1556 svm->vmcb->save.gdtr = hsave->save.gdtr;
1557 svm->vmcb->save.idtr = hsave->save.idtr;
1558 svm->vmcb->save.rflags = hsave->save.rflags;
1559 svm_set_efer(&svm->vcpu, hsave->save.efer);
1560 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1561 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1562 if (npt_enabled) {
1563 svm->vmcb->save.cr3 = hsave->save.cr3;
1564 svm->vcpu.arch.cr3 = hsave->save.cr3;
1565 } else {
1566 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1567 }
1568 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1569 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1570 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1571 svm->vmcb->save.dr7 = 0;
1572 svm->vmcb->save.cpl = 0;
1573 svm->vmcb->control.exit_int_info = 0;
1574
1575 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1576 /* Exit nested SVM mode */
1577 svm->nested_vmcb = 0;
1578
1579 return 0;
1580}
1581
1582static int nested_svm_vmexit(struct vcpu_svm *svm)
1583{
1584 nsvm_printk("VMexit\n");
1585 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1586 NULL, nested_svm_vmexit_real))
1587 return 1;
1588
1589 kvm_mmu_reset_context(&svm->vcpu);
1590 kvm_mmu_load(&svm->vcpu);
1591
1592 return 0;
1593}
3d6368ef
AG		 1594
1595static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1596 void *arg2, void *opaque)
1597{
1598 int i;
1599 u32 *nested_msrpm = (u32*)arg1;
1600 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1601 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1602 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1603
1604 return 0;
1605}
1606
1607static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1608 void *arg2, void *opaque)
1609{
1610 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1611 struct vmcb *hsave = svm->hsave;
1612
1613 /* nested_vmcb is our indicator if nested SVM is activated */
1614 svm->nested_vmcb = svm->vmcb->save.rax;
1615
1616 /* Clear internal status */
1617 svm->vcpu.arch.exception.pending = false;
1618
1619 /* Save the old vmcb, so we don't need to pick what we save, but
1620 can restore everything when a VMEXIT occurs */
1621 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1622 /* We need to remember the original CR3 in the SPT case */
1623 if (!npt_enabled)
1624 hsave->save.cr3 = svm->vcpu.arch.cr3;
1625 hsave->save.cr4 = svm->vcpu.arch.cr4;
1626 hsave->save.rip = svm->next_rip;
1627
1628 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1629 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1630 else
1631 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1632
1633 /* Load the nested guest state */
1634 svm->vmcb->save.es = nested_vmcb->save.es;
1635 svm->vmcb->save.cs = nested_vmcb->save.cs;
1636 svm->vmcb->save.ss = nested_vmcb->save.ss;
1637 svm->vmcb->save.ds = nested_vmcb->save.ds;
1638 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1639 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1640 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1641 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1642 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1643 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1644 if (npt_enabled) {
1645 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1646 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1647 } else {
1648 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1649 kvm_mmu_reset_context(&svm->vcpu);
1650 }
1651 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1652 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1653 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1654 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1655 /* In case we don't even reach vcpu_run, the fields are not updated */
1656 svm->vmcb->save.rax = nested_vmcb->save.rax;
1657 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1658 svm->vmcb->save.rip = nested_vmcb->save.rip;
1659 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1660 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1661 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1662
1663 /* We don't want a nested guest to be more powerful than the guest,
1664 so all intercepts are ORed */
1665 svm->vmcb->control.intercept_cr_read |=
1666 nested_vmcb->control.intercept_cr_read;
1667 svm->vmcb->control.intercept_cr_write |=
1668 nested_vmcb->control.intercept_cr_write;
1669 svm->vmcb->control.intercept_dr_read |=
1670 nested_vmcb->control.intercept_dr_read;
1671 svm->vmcb->control.intercept_dr_write |=
1672 nested_vmcb->control.intercept_dr_write;
1673 svm->vmcb->control.intercept_exceptions |=
1674 nested_vmcb->control.intercept_exceptions;
1675
1676 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1677
1678 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1679
1680 force_new_asid(&svm->vcpu);
1681 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1682 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1683 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1684 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1685 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1686 nested_vmcb->control.int_ctl);
1687 }
1688 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1689 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1690 else
1691 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1692
1693 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1694 nested_vmcb->control.exit_int_info,
1695 nested_vmcb->control.int_state);
1696
1697 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1698 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1699 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1700 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1701 nsvm_printk("Injecting Event: 0x%x\n",
1702 nested_vmcb->control.event_inj);
1703 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1704 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1705
1706 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1707
1708 return 0;
1709}
1710
5542675b
AG		 1711static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1712{
1713 to_vmcb->save.fs = from_vmcb->save.fs;
1714 to_vmcb->save.gs = from_vmcb->save.gs;
1715 to_vmcb->save.tr = from_vmcb->save.tr;
1716 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1717 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1718 to_vmcb->save.star = from_vmcb->save.star;
1719 to_vmcb->save.lstar = from_vmcb->save.lstar;
1720 to_vmcb->save.cstar = from_vmcb->save.cstar;
1721 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1722 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1723 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1724 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1725
1726 return 1;
1727}
1728
1729static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1730 void *arg2, void *opaque)
1731{
1732 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1733}
1734
1735static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1736 void *arg2, void *opaque)
1737{
1738 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1739}
1740
1741static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1742{
1743 if (nested_svm_check_permissions(svm))
1744 return 1;
1745
1746 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1747 skip_emulated_instruction(&svm->vcpu);
1748
1749 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1750
1751 return 1;
1752}
1753
1754static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1755{
1756 if (nested_svm_check_permissions(svm))
1757 return 1;
1758
1759 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1760 skip_emulated_instruction(&svm->vcpu);
1761
1762 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1763
1764 return 1;
1765}
1766
3d6368ef
AG		 1767static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1768{
1769 nsvm_printk("VMrun\n");
1770 if (nested_svm_check_permissions(svm))
1771 return 1;
1772
1773 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1774 skip_emulated_instruction(&svm->vcpu);
1775
1776 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1777 NULL, nested_svm_vmrun))
1778 return 1;
1779
1780 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1781 NULL, nested_svm_vmrun_msrpm))
1782 return 1;
1783
1784 return 1;
1785}
1786
1371d904
AG		 1787static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1788{
1789 if (nested_svm_check_permissions(svm))
1790 return 1;
1791
1792 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1793 skip_emulated_instruction(&svm->vcpu);
1794
1795 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1796
1797 return 1;
1798}
1799
1800static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1801{
1802 if (nested_svm_check_permissions(svm))
1803 return 1;
1804
1805 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1806 skip_emulated_instruction(&svm->vcpu);
1807
1808 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1809
1810 /* After a CLGI no interrupts should come */
1811 svm_clear_vintr(svm);
1812 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1813
1814 return 1;
1815}
1816
e756fc62
RR		 1817static int invalid_op_interception(struct vcpu_svm *svm,
1818 struct kvm_run *kvm_run)
6aa8b732 1819{
7ee5d940 1820 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1821 return 1;
1822}
1823
e756fc62
RR		 1824static int task_switch_interception(struct vcpu_svm *svm,
1825 struct kvm_run *kvm_run)
6aa8b732 1826{
37817f29 1827 u16 tss_selector;
64a7ec06
GN		 1828 int reason;
1829 int int_type = svm->vmcb->control.exit_int_info &
1830 SVM_EXITINTINFO_TYPE_MASK;
37817f29
IE		 1831
1832 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1833
37817f29
IE		 1834 if (svm->vmcb->control.exit_info_2 &
1835 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1836 reason = TASK_SWITCH_IRET;
1837 else if (svm->vmcb->control.exit_info_2 &
1838 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1839 reason = TASK_SWITCH_JMP;
1840 else if (svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID)
1841 reason = TASK_SWITCH_GATE;
1842 else
1843 reason = TASK_SWITCH_CALL;
1844
1845
1846 if (reason != TASK_SWITCH_GATE || int_type == SVM_EXITINTINFO_TYPE_SOFT)
1847 skip_emulated_instruction(&svm->vcpu);
1848
1849 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 1850}
1851
e756fc62 1852static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1853{
5fdbf976 1854 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1855 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 1856 return 1;
6aa8b732
AK		 1857}
1858
a7052897
MT		 1859static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1860{
1861 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1862 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1863 return 1;
1864}
1865
e756fc62
RR		 1866static int emulate_on_interception(struct vcpu_svm *svm,
1867 struct kvm_run *kvm_run)
6aa8b732 1868{
3427318f 1869 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 1870 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 1871 return 1;
1872}
1873
1d075434
JR		 1874static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1875{
1876 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1877 if (irqchip_in_kernel(svm->vcpu.kvm))
1878 return 1;
1879 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1880 return 0;
1881}
1882
6aa8b732
AK		 1883static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1884{
a2fa3e9f
GH		 1885 struct vcpu_svm *svm = to_svm(vcpu);
1886
6aa8b732 1887 switch (ecx) {
6aa8b732
AK		 1888 case MSR_IA32_TIME_STAMP_COUNTER: {
1889 u64 tsc;
1890
1891 rdtscll(tsc);
a2fa3e9f 1892 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 1893 break;
1894 }
0e859cac 1895 case MSR_K6_STAR:
a2fa3e9f 1896 *data = svm->vmcb->save.star;
6aa8b732 1897 break;
0e859cac 1898#ifdef CONFIG_X86_64
6aa8b732 1899 case MSR_LSTAR:
a2fa3e9f 1900 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 1901 break;
1902 case MSR_CSTAR:
a2fa3e9f 1903 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 1904 break;
1905 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1906 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 1907 break;
1908 case MSR_SYSCALL_MASK:
a2fa3e9f 1909 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 1910 break;
1911#endif
1912 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 1913 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 1914 break;
1915 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 1916 *data = svm->vmcb->save.sysenter_eip;
6aa8b732
AK		 1917 break;
1918 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 1919 *data = svm->vmcb->save.sysenter_esp;
6aa8b732 1920 break;
a2938c80
JR		 1921 /* Nobody will change the following 5 values in the VMCB so
1922 we can safely return them on rdmsr. They will always be 0
1923 until LBRV is implemented. */
1924 case MSR_IA32_DEBUGCTLMSR:
1925 *data = svm->vmcb->save.dbgctl;
1926 break;
1927 case MSR_IA32_LASTBRANCHFROMIP:
1928 *data = svm->vmcb->save.br_from;
1929 break;
1930 case MSR_IA32_LASTBRANCHTOIP:
1931 *data = svm->vmcb->save.br_to;
1932 break;
1933 case MSR_IA32_LASTINTFROMIP:
1934 *data = svm->vmcb->save.last_excp_from;
1935 break;
1936 case MSR_IA32_LASTINTTOIP:
1937 *data = svm->vmcb->save.last_excp_to;
1938 break;
b286d5d8
AG		 1939 case MSR_VM_HSAVE_PA:
1940 *data = svm->hsave_msr;
1941 break;
eb6f302e
JR		 1942 case MSR_VM_CR:
1943 *data = 0;
1944 break;
c8a73f18
AG		 1945 case MSR_IA32_UCODE_REV:
1946 *data = 0x01000065;
1947 break;
6aa8b732 1948 default:
3bab1f5d 1949 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1950 }
1951 return 0;
1952}
1953
e756fc62 1954static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1955{
ad312c7c 1956 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 1957 u64 data;
1958
e756fc62 1959 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 1960 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 1961 else {
af9ca2d7
JR		 1962 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1963 (u32)(data >> 32), handler);
1964
5fdbf976 1965 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 1966 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 1967 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1968 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 1969 }
1970 return 1;
1971}
1972
1973static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1974{
a2fa3e9f
GH		 1975 struct vcpu_svm *svm = to_svm(vcpu);
1976
6aa8b732 1977 switch (ecx) {
6aa8b732
AK		 1978 case MSR_IA32_TIME_STAMP_COUNTER: {
1979 u64 tsc;
1980
1981 rdtscll(tsc);
a2fa3e9f 1982 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 1983 break;
1984 }
0e859cac 1985 case MSR_K6_STAR:
a2fa3e9f 1986 svm->vmcb->save.star = data;
6aa8b732 1987 break;
49b14f24 1988#ifdef CONFIG_X86_64
6aa8b732 1989 case MSR_LSTAR:
a2fa3e9f 1990 svm->vmcb->save.lstar = data;
6aa8b732
AK		 1991 break;
1992 case MSR_CSTAR:
a2fa3e9f 1993 svm->vmcb->save.cstar = data;
6aa8b732
AK		 1994 break;
1995 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1996 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 1997 break;
1998 case MSR_SYSCALL_MASK:
a2fa3e9f 1999 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2000 break;
2001#endif
2002 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2003 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2004 break;
2005 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 2006 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2007 break;
2008 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 2009 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2010 break;
a2938c80 2011 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2012 if (!svm_has(SVM_FEATURE_LBRV)) {
2013 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2014 __func__, data);
24e09cbf
JR		 2015 break;
2016 }
2017 if (data & DEBUGCTL_RESERVED_BITS)
2018 return 1;
2019
2020 svm->vmcb->save.dbgctl = data;
2021 if (data & (1ULL<<0))
2022 svm_enable_lbrv(svm);
2023 else
2024 svm_disable_lbrv(svm);
a2938c80 2025 break;
62b9abaa
JR		 2026 case MSR_K7_EVNTSEL0:
2027 case MSR_K7_EVNTSEL1:
2028 case MSR_K7_EVNTSEL2:
2029 case MSR_K7_EVNTSEL3:
14ae51b6
CL		 2030 case MSR_K7_PERFCTR0:
2031 case MSR_K7_PERFCTR1:
2032 case MSR_K7_PERFCTR2:
2033 case MSR_K7_PERFCTR3:
62b9abaa 2034 /*
14ae51b6
CL		 2035 * Just discard all writes to the performance counters; this
2036 * should keep both older linux and windows 64-bit guests
2037 * happy
62b9abaa 2038 */
14ae51b6
CL		 2039 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2040
b286d5d8
AG		 2041 break;
2042 case MSR_VM_HSAVE_PA:
2043 svm->hsave_msr = data;
62b9abaa 2044 break;
6aa8b732 2045 default:
3bab1f5d 2046 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2047 }
2048 return 0;
2049}
2050
e756fc62 2051static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2052{
ad312c7c 2053 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2054 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2055 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7
JR		 2056
2057 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2058 handler);
2059
5fdbf976 2060 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2061 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2062 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2063 else
e756fc62 2064 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2065 return 1;
2066}
2067
e756fc62 2068static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2069{
e756fc62
RR		 2070 if (svm->vmcb->control.exit_info_1)
2071 return wrmsr_interception(svm, kvm_run);
6aa8b732 2072 else
e756fc62 2073 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2074}
2075
e756fc62 2076static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2077 struct kvm_run *kvm_run)
2078{
af9ca2d7
JR		 2079 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2080
f0b85051 2081 svm_clear_vintr(svm);
85f455f7 2082 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2083 /*
2084 * If the user space waits to inject interrupts, exit as soon as
2085 * possible
2086 */
2087 if (kvm_run->request_interrupt_window &&
ad312c7c 2088 !svm->vcpu.arch.irq_summary) {
e756fc62 2089 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2090 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2091 return 0;
2092 }
2093
2094 return 1;
2095}
2096
e756fc62 2097static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2098 struct kvm_run *kvm_run) = {
2099 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2100 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2101 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2102 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2103 /* for now: */
2104 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2105 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2106 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2107 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2108 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2109 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2110 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2111 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2112 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2113 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2114 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2115 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2116 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2117 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2118 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2119 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2120 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2121 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2122 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2123 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2124 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2125 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2126 [SVM_EXIT_SMI] = nop_on_interception,
2127 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2128 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2129 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2130 [SVM_EXIT_CPUID] = cpuid_interception,
cf5a94d1 2131 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2132 [SVM_EXIT_HLT] = halt_interception,
a7052897 2133 [SVM_EXIT_INVLPG] = invlpg_interception,
6aa8b732
AK		 2134 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2135 [SVM_EXIT_IOIO] = io_interception,
2136 [SVM_EXIT_MSR] = msr_interception,
2137 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2138 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2139 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2140 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2141 [SVM_EXIT_VMLOAD] = vmload_interception,
2142 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2143 [SVM_EXIT_STGI] = stgi_interception,
2144 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2145 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2146 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2147 [SVM_EXIT_MONITOR] = invalid_op_interception,
2148 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2149 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2150};
2151
04d2cc77 2152static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2153{
04d2cc77 2154 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2155 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2156
af9ca2d7
JR		 2157 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2158 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2159
cf74a78b
AG		 2160 if (is_nested(svm)) {
2161 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2162 exit_code, svm->vmcb->control.exit_info_1,
2163 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2164 if (nested_svm_exit_handled(svm, true)) {
2165 nested_svm_vmexit(svm);
2166 nsvm_printk("-> #VMEXIT\n");
2167 return 1;
2168 }
2169 }
2170
709ddebf
JR		 2171 if (npt_enabled) {
2172 int mmu_reload = 0;
2173 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2174 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2175 mmu_reload = 1;
2176 }
2177 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2178 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2179 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2180 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2181 kvm_inject_gp(vcpu, 0);
2182 return 1;
2183 }
2184 }
2185 if (mmu_reload) {
2186 kvm_mmu_reset_context(vcpu);
2187 kvm_mmu_load(vcpu);
2188 }
2189 }
2190
04d2cc77
AK		 2191 kvm_reput_irq(svm);
2192
2193 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2194 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2195 kvm_run->fail_entry.hardware_entry_failure_reason
2196 = svm->vmcb->control.exit_code;
2197 return 0;
2198 }
2199
a2fa3e9f 2200 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf
JR		 2201 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2202 exit_code != SVM_EXIT_NPF)
6aa8b732
AK		 2203 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2204 "exit_code 0x%x\n",
b8688d51 2205 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2206 exit_code);
2207
9d8f549d 2208 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2209 || !svm_exit_handlers[exit_code]) {
6aa8b732 2210 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2211 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2212 return 0;
2213 }
2214
e756fc62 2215 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2216}
2217
2218static void reload_tss(struct kvm_vcpu *vcpu)
2219{
2220 int cpu = raw_smp_processor_id();
2221
2222 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2223 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2224 load_TR_desc();
2225}
2226
e756fc62 2227static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2228{
2229 int cpu = raw_smp_processor_id();
2230
2231 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2232
a2fa3e9f 2233 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e756fc62 2234 if (svm->vcpu.cpu != cpu ||
a2fa3e9f 2235 svm->asid_generation != svm_data->asid_generation)
e756fc62 2236 new_asid(svm, svm_data);
6aa8b732
AK		 2237}
2238
2239
85f455f7 2240static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2241{
2242 struct vmcb_control_area *control;
2243
af9ca2d7
JR		 2244 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2245
fa89a817 2246 ++svm->vcpu.stat.irq_injections;
e756fc62 2247 control = &svm->vmcb->control;
85f455f7 2248 control->int_vector = irq;
6aa8b732
AK		 2249 control->int_ctl &= ~V_INTR_PRIO_MASK;
2250 control->int_ctl |= V_IRQ_MASK |
2251 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2252}
2253
2a8067f1
ED		 2254static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2255{
2256 struct vcpu_svm *svm = to_svm(vcpu);
2257
cf74a78b
AG		 2258 nested_svm_intr(svm);
2259
2a8067f1
ED		 2260 svm_inject_irq(svm, irq);
2261}
2262
aaacfc9a
JR		 2263static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2264{
2265 struct vcpu_svm *svm = to_svm(vcpu);
2266 struct vmcb *vmcb = svm->vmcb;
2267 int max_irr, tpr;
2268
2269 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2270 return;
2271
2272 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2273
2274 max_irr = kvm_lapic_find_highest_irr(vcpu);
2275 if (max_irr == -1)
2276 return;
2277
2278 tpr = kvm_lapic_get_cr8(vcpu) << 4;
2279
2280 if (tpr >= (max_irr & 0xf0))
2281 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2282}
2283
78646121
GN		 2284static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2285{
2286 struct vcpu_svm *svm = to_svm(vcpu);
2287 struct vmcb *vmcb = svm->vmcb;
2288 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2289 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2290 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2291}
2292
04d2cc77 2293static void svm_intr_assist(struct kvm_vcpu *vcpu)
6aa8b732 2294{
04d2cc77 2295 struct vcpu_svm *svm = to_svm(vcpu);
85f455f7
ED		 2296 struct vmcb *vmcb = svm->vmcb;
2297 int intr_vector = -1;
2298
2299 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
2300 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
2301 intr_vector = vmcb->control.exit_int_info &
2302 SVM_EVTINJ_VEC_MASK;
2303 vmcb->control.exit_int_info = 0;
2304 svm_inject_irq(svm, intr_vector);
aaacfc9a 2305 goto out;
85f455f7
ED		 2306 }
2307
2308 if (vmcb->control.int_ctl & V_IRQ_MASK)
aaacfc9a 2309 goto out;
85f455f7 2310
1b9778da 2311 if (!kvm_cpu_has_interrupt(vcpu))
aaacfc9a 2312 goto out;
85f455f7 2313
cf74a78b
AG		 2314 if (nested_svm_intr(svm))
2315 goto out;
2316
1371d904
AG		 2317 if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
2318 goto out;
2319
85f455f7
ED		 2320 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
2321 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
2322 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
2323 /* unable to deliver irq, set pending irq */
f0b85051 2324 svm_set_vintr(svm);
85f455f7 2325 svm_inject_irq(svm, 0x0);
aaacfc9a 2326 goto out;
85f455f7
ED		 2327 }
2328 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1b9778da 2329 intr_vector = kvm_cpu_get_interrupt(vcpu);
85f455f7 2330 svm_inject_irq(svm, intr_vector);
aaacfc9a
JR		 2331out:
2332 update_cr8_intercept(vcpu);
85f455f7
ED		 2333}
2334
2335static void kvm_reput_irq(struct vcpu_svm *svm)
2336{
e756fc62 2337 struct vmcb_control_area *control = &svm->vmcb->control;
6aa8b732 2338
7017fc3d
ED		 2339 if ((control->int_ctl & V_IRQ_MASK)
2340 && !irqchip_in_kernel(svm->vcpu.kvm)) {
6aa8b732 2341 control->int_ctl &= ~V_IRQ_MASK;
fe4c7b19 2342 kvm_push_irq(&svm->vcpu, control->int_vector);
6aa8b732 2343 }
c1150d8c 2344
ad312c7c 2345 svm->vcpu.arch.interrupt_window_open =
1371d904
AG		 2346 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2347 (svm->vcpu.arch.hflags & HF_GIF_MASK);
c1150d8c
DL		 2348}
2349
85f455f7
ED		 2350static void svm_do_inject_vector(struct vcpu_svm *svm)
2351{
fe4c7b19 2352 svm_inject_irq(svm, kvm_pop_irq(&svm->vcpu));
85f455f7
ED		 2353}
2354
04d2cc77 2355static void do_interrupt_requests(struct kvm_vcpu *vcpu,
c1150d8c
DL		 2356 struct kvm_run *kvm_run)
2357{
04d2cc77 2358 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2359 struct vmcb_control_area *control = &svm->vmcb->control;
c1150d8c 2360
cf74a78b
AG		 2361 if (nested_svm_intr(svm))
2362 return;
2363
ad312c7c 2364 svm->vcpu.arch.interrupt_window_open =
c1150d8c 2365 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1371d904
AG		 2366 (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
2367 (svm->vcpu.arch.hflags & HF_GIF_MASK));
c1150d8c 2368
ad312c7c 2369 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
c1150d8c
DL		 2370 /*
2371 * If interrupts enabled, and not blocked by sti or mov ss. Good.
2372 */
85f455f7 2373 svm_do_inject_vector(svm);
c1150d8c
DL		 2374
2375 /*
2376 * Interrupts blocked. Wait for unblock.
2377 */
ad312c7c
ZX		 2378 if (!svm->vcpu.arch.interrupt_window_open &&
2379 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
f0b85051
AG		 2380 svm_set_vintr(svm);
2381 else
2382 svm_clear_vintr(svm);
c1150d8c
DL		 2383}
2384
cbc94022
IE		 2385static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2386{
2387 return 0;
2388}
2389
d9e368d6
AK		 2390static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2391{
2392 force_new_asid(vcpu);
2393}
2394
04d2cc77
AK		 2395static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2396{
2397}
2398
d7bf8221
JR		 2399static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2400{
2401 struct vcpu_svm *svm = to_svm(vcpu);
2402
2403 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2404 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2405 kvm_lapic_set_tpr(vcpu, cr8);
2406 }
2407}
2408
649d6864
JR		 2409static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2410{
2411 struct vcpu_svm *svm = to_svm(vcpu);
2412 u64 cr8;
2413
2414 if (!irqchip_in_kernel(vcpu->kvm))
2415 return;
2416
2417 cr8 = kvm_get_cr8(vcpu);
2418 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2419 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2420}
2421
80e31d4f
AK		 2422#ifdef CONFIG_X86_64
2423#define R "r"
2424#else
2425#define R "e"
2426#endif
2427
04d2cc77 2428static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2429{
a2fa3e9f 2430 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2431 u16 fs_selector;
2432 u16 gs_selector;
2433 u16 ldt_selector;
d9e368d6 2434
5fdbf976
MT		 2435 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2436 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2437 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2438
e756fc62 2439 pre_svm_run(svm);
6aa8b732 2440
649d6864
JR		 2441 sync_lapic_to_cr8(vcpu);
2442
6aa8b732 2443 save_host_msrs(vcpu);
d6e88aec
AK		 2444 fs_selector = kvm_read_fs();
2445 gs_selector = kvm_read_gs();
2446 ldt_selector = kvm_read_ldt();
a2fa3e9f 2447 svm->host_cr2 = kvm_read_cr2();
3d6368ef
AG		 2448 if (!is_nested(svm))
2449 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2450 /* required for live migration with NPT */
2451 if (npt_enabled)
2452 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2453
04d2cc77
AK		 2454 clgi();
2455
2456 local_irq_enable();
36241b8c 2457
6aa8b732 2458 asm volatile (
80e31d4f
AK		 2459 "push %%"R"bp; \n\t"
2460 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2461 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2462 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2463 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2464 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2465 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2466#ifdef CONFIG_X86_64
fb3f0f51
RR		 2467 "mov %c[r8](%[svm]), %%r8 \n\t"
2468 "mov %c[r9](%[svm]), %%r9 \n\t"
2469 "mov %c[r10](%[svm]), %%r10 \n\t"
2470 "mov %c[r11](%[svm]), %%r11 \n\t"
2471 "mov %c[r12](%[svm]), %%r12 \n\t"
2472 "mov %c[r13](%[svm]), %%r13 \n\t"
2473 "mov %c[r14](%[svm]), %%r14 \n\t"
2474 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2475#endif
2476
6aa8b732 2477 /* Enter guest mode */
80e31d4f
AK		 2478 "push %%"R"ax \n\t"
2479 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2480 __ex(SVM_VMLOAD) "\n\t"
2481 __ex(SVM_VMRUN) "\n\t"
2482 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2483 "pop %%"R"ax \n\t"
6aa8b732
AK		 2484
2485 /* Save guest registers, load host registers */
80e31d4f
AK		 2486 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2487 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2488 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2489 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2490 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2491 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2492#ifdef CONFIG_X86_64
fb3f0f51
RR		 2493 "mov %%r8, %c[r8](%[svm]) \n\t"
2494 "mov %%r9, %c[r9](%[svm]) \n\t"
2495 "mov %%r10, %c[r10](%[svm]) \n\t"
2496 "mov %%r11, %c[r11](%[svm]) \n\t"
2497 "mov %%r12, %c[r12](%[svm]) \n\t"
2498 "mov %%r13, %c[r13](%[svm]) \n\t"
2499 "mov %%r14, %c[r14](%[svm]) \n\t"
2500 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2501#endif
80e31d4f 2502 "pop %%"R"bp"
6aa8b732 2503 :
fb3f0f51 2504 : [svm]"a"(svm),
6aa8b732 2505 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2506 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2507 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2508 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2509 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2510 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2511 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2512#ifdef CONFIG_X86_64
ad312c7c
ZX		 2513 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2514 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2515 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2516 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2517 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2518 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2519 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2520 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2521#endif
54a08c04 2522 : "cc", "memory"
80e31d4f 2523 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2524#ifdef CONFIG_X86_64
54a08c04
LV		 2525 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2526#endif
2527 );
6aa8b732 2528
ad312c7c 2529 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2530 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2531 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2532 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2533
a2fa3e9f 2534 kvm_write_cr2(svm->host_cr2);
6aa8b732 2535
d6e88aec
AK		 2536 kvm_load_fs(fs_selector);
2537 kvm_load_gs(gs_selector);
2538 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2539 load_host_msrs(vcpu);
2540
2541 reload_tss(vcpu);
2542
56ba47dd
AK		 2543 local_irq_disable();
2544
2545 stgi();
2546
d7bf8221
JR		 2547 sync_cr8_to_lapic(vcpu);
2548
a2fa3e9f 2549 svm->next_rip = 0;
6aa8b732
AK		 2550}
2551
80e31d4f
AK		 2552#undef R
2553
6aa8b732
AK		 2554static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2555{
a2fa3e9f
GH		 2556 struct vcpu_svm *svm = to_svm(vcpu);
2557
709ddebf
JR		 2558 if (npt_enabled) {
2559 svm->vmcb->control.nested_cr3 = root;
2560 force_new_asid(vcpu);
2561 return;
2562 }
2563
a2fa3e9f 2564 svm->vmcb->save.cr3 = root;
6aa8b732 2565 force_new_asid(vcpu);
7807fa6c
AL		 2566
2567 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2568 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2569 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2570 vcpu->fpu_active = 0;
2571 }
6aa8b732
AK		 2572}
2573
6aa8b732
AK		 2574static int is_disabled(void)
2575{
6031a61c
JR		 2576 u64 vm_cr;
2577
2578 rdmsrl(MSR_VM_CR, vm_cr);
2579 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2580 return 1;
2581
6aa8b732
AK		 2582 return 0;
2583}
2584
102d8325
IM		 2585static void
2586svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2587{
2588 /*
2589 * Patch in the VMMCALL instruction:
2590 */
2591 hypercall[0] = 0x0f;
2592 hypercall[1] = 0x01;
2593 hypercall[2] = 0xd9;
102d8325
IM		 2594}
2595
002c7f7c
YS		 2596static void svm_check_processor_compat(void *rtn)
2597{
2598 *(int *)rtn = 0;
2599}
2600
774ead3a
AK		 2601static bool svm_cpu_has_accelerated_tpr(void)
2602{
2603 return false;
2604}
2605
67253af5
SY		 2606static int get_npt_level(void)
2607{
2608#ifdef CONFIG_X86_64
2609 return PT64_ROOT_LEVEL;
2610#else
2611 return PT32E_ROOT_LEVEL;
2612#endif
2613}
2614
64d4d521
SY		 2615static int svm_get_mt_mask_shift(void)
2616{
2617 return 0;
2618}
2619
cbdd1bea 2620static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2621 .cpu_has_kvm_support = has_svm,
2622 .disabled_by_bios = is_disabled,
2623 .hardware_setup = svm_hardware_setup,
2624 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2625 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2626 .hardware_enable = svm_hardware_enable,
2627 .hardware_disable = svm_hardware_disable,
774ead3a 2628 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2629
2630 .vcpu_create = svm_create_vcpu,
2631 .vcpu_free = svm_free_vcpu,
04d2cc77 2632 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2633
04d2cc77 2634 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2635 .vcpu_load = svm_vcpu_load,
2636 .vcpu_put = svm_vcpu_put,
2637
2638 .set_guest_debug = svm_guest_debug,
2639 .get_msr = svm_get_msr,
2640 .set_msr = svm_set_msr,
2641 .get_segment_base = svm_get_segment_base,
2642 .get_segment = svm_get_segment,
2643 .set_segment = svm_set_segment,
2e4d2653 2644 .get_cpl = svm_get_cpl,
1747fb71 2645 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2646 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2647 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2648 .set_cr3 = svm_set_cr3,
2649 .set_cr4 = svm_set_cr4,
2650 .set_efer = svm_set_efer,
2651 .get_idt = svm_get_idt,
2652 .set_idt = svm_set_idt,
2653 .get_gdt = svm_get_gdt,
2654 .set_gdt = svm_set_gdt,
2655 .get_dr = svm_get_dr,
2656 .set_dr = svm_set_dr,
6aa8b732
AK		 2657 .get_rflags = svm_get_rflags,
2658 .set_rflags = svm_set_rflags,
2659
6aa8b732 2660 .tlb_flush = svm_flush_tlb,
6aa8b732 2661
6aa8b732 2662 .run = svm_vcpu_run,
04d2cc77 2663 .handle_exit = handle_exit,
6aa8b732 2664 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2665 .patch_hypercall = svm_patch_hypercall,
2a8067f1
ED		 2666 .get_irq = svm_get_irq,
2667 .set_irq = svm_set_irq,
298101da
AK		 2668 .queue_exception = svm_queue_exception,
2669 .exception_injected = svm_exception_injected,
04d2cc77
AK		 2670 .inject_pending_irq = svm_intr_assist,
2671 .inject_pending_vectors = do_interrupt_requests,
78646121 2672 .interrupt_allowed = svm_interrupt_allowed,
cbc94022
IE		 2673
2674 .set_tss_addr = svm_set_tss_addr,
67253af5 2675 .get_tdp_level = get_npt_level,
64d4d521 2676 .get_mt_mask_shift = svm_get_mt_mask_shift,
6aa8b732
AK		 2677};
2678
2679static int __init svm_init(void)
2680{
cb498ea2 2681 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2682 THIS_MODULE);
6aa8b732
AK		 2683}
2684
2685static void __exit svm_exit(void)
2686{
cb498ea2 2687 kvm_exit();
6aa8b732
AK		 2688}
2689
2690module_init(svm_init)
2691module_exit(svm_exit)
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