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KVM: SVM: Sync all control registers on nested vmexit
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
565d0998 50#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 51
410e4d57
JR		 52#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
53#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
54#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
55
24e09cbf
JR		 56#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
57
6c8166a7
AK		 58static const u32 host_save_user_msrs[] = {
59#ifdef CONFIG_X86_64
60 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
61 MSR_FS_BASE,
62#endif
63 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
64};
65
66#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
67
68struct kvm_vcpu;
69
e6aa9abd
JR		 70struct nested_state {
71 struct vmcb *hsave;
72 u64 hsave_msr;
73 u64 vmcb;
74
75 /* These are the merged vectors */
76 u32 *msrpm;
77
78 /* gpa pointers to the real vectors */
79 u64 vmcb_msrpm;
aad42c64 80
cd3ff653
JR		 81 /* A VMEXIT is required but not yet emulated */
82 bool exit_required;
83
aad42c64
JR		 84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read;
86 u16 intercept_cr_write;
87 u16 intercept_dr_read;
88 u16 intercept_dr_write;
89 u32 intercept_exceptions;
90 u64 intercept;
91
e6aa9abd
JR		 92};
93
6c8166a7
AK		 94struct vcpu_svm {
95 struct kvm_vcpu vcpu;
96 struct vmcb *vmcb;
97 unsigned long vmcb_pa;
98 struct svm_cpu_data *svm_data;
99 uint64_t asid_generation;
100 uint64_t sysenter_esp;
101 uint64_t sysenter_eip;
102
103 u64 next_rip;
104
105 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
106 u64 host_gs_base;
6c8166a7
AK		 107
108 u32 *msrpm;
6c8166a7 109
e6aa9abd 110 struct nested_state nested;
6be7d306
JK		 111
112 bool nmi_singlestep;
6c8166a7
AK		 113};
114
709ddebf
JR		 115/* enable NPT for AMD64 and X86 with PAE */
116#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
117static bool npt_enabled = true;
118#else
e3da3acd 119static bool npt_enabled = false;
709ddebf 120#endif
6c7dac72
JR		 121static int npt = 1;
122
123module_param(npt, int, S_IRUGO);
e3da3acd 124
4b6e4dca 125static int nested = 1;
236de055
AG		 126module_param(nested, int, S_IRUGO);
127
44874f84 128static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 129static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 130
410e4d57 131static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 132static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 133static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 134static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
135 bool has_error_code, u32 error_code);
136
a2fa3e9f
GH		 137static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
138{
fb3f0f51 139 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 140}
141
3d6368ef
AG		 142static inline bool is_nested(struct vcpu_svm *svm)
143{
e6aa9abd 144 return svm->nested.vmcb;
3d6368ef
AG		 145}
146
2af9194d
JR		 147static inline void enable_gif(struct vcpu_svm *svm)
148{
149 svm->vcpu.arch.hflags |= HF_GIF_MASK;
150}
151
152static inline void disable_gif(struct vcpu_svm *svm)
153{
154 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
155}
156
157static inline bool gif_set(struct vcpu_svm *svm)
158{
159 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
160}
161
4866d5e3 162static unsigned long iopm_base;
6aa8b732
AK		 163
164struct kvm_ldttss_desc {
165 u16 limit0;
166 u16 base0;
167 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
168 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
169 u32 base3;
170 u32 zero1;
171} __attribute__((packed));
172
173struct svm_cpu_data {
174 int cpu;
175
5008fdf5
AK		 176 u64 asid_generation;
177 u32 max_asid;
178 u32 next_asid;
6aa8b732
AK		 179 struct kvm_ldttss_desc *tss_desc;
180
181 struct page *save_area;
182};
183
184static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 185static uint32_t svm_features;
6aa8b732
AK		 186
187struct svm_init_data {
188 int cpu;
189 int r;
190};
191
192static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
193
9d8f549d 194#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 195#define MSRS_RANGE_SIZE 2048
196#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
197
198#define MAX_INST_SIZE 15
199
80b7706e
JR		 200static inline u32 svm_has(u32 feat)
201{
202 return svm_features & feat;
203}
204
6aa8b732
AK		 205static inline void clgi(void)
206{
4ecac3fd 207 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 208}
209
210static inline void stgi(void)
211{
4ecac3fd 212 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 213}
214
215static inline void invlpga(unsigned long addr, u32 asid)
216{
4ecac3fd 217 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 218}
219
6aa8b732
AK		 220static inline void force_new_asid(struct kvm_vcpu *vcpu)
221{
a2fa3e9f 222 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 223}
224
225static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
226{
227 force_new_asid(vcpu);
228}
229
230static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
231{
709ddebf 232 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 233 efer &= ~EFER_LME;
6aa8b732 234
9962d032 235 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 236 vcpu->arch.efer = efer;
6aa8b732
AK		 237}
238
298101da
AK		 239static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
240 bool has_error_code, u32 error_code)
241{
242 struct vcpu_svm *svm = to_svm(vcpu);
243
cf74a78b
AG		 244 /* If we are within a nested VM we'd better #VMEXIT and let the
245 guest handle the exception */
246 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
247 return;
248
298101da
AK		 249 svm->vmcb->control.event_inj = nr
250 | SVM_EVTINJ_VALID
251 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
252 | SVM_EVTINJ_TYPE_EXEPT;
253 svm->vmcb->control.event_inj_err = error_code;
254}
255
6aa8b732
AK		 256static int is_external_interrupt(u32 info)
257{
258 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
259 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
260}
261
2809f5d2
GC		 262static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
263{
264 struct vcpu_svm *svm = to_svm(vcpu);
265 u32 ret = 0;
266
267 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
268 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
269 return ret & mask;
270}
271
272static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
273{
274 struct vcpu_svm *svm = to_svm(vcpu);
275
276 if (mask == 0)
277 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
278 else
279 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
280
281}
282
6aa8b732
AK		 283static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
284{
a2fa3e9f
GH		 285 struct vcpu_svm *svm = to_svm(vcpu);
286
287 if (!svm->next_rip) {
851ba692 288 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 289 EMULATE_DONE)
290 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 291 return;
292 }
5fdbf976
MT		 293 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
294 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
295 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 296
5fdbf976 297 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 298 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 299}
300
301static int has_svm(void)
302{
63d1142f 303 const char *msg;
6aa8b732 304
63d1142f 305 if (!cpu_has_svm(&msg)) {
ff81ff10 306 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 307 return 0;
308 }
309
6aa8b732
AK		 310 return 1;
311}
312
313static void svm_hardware_disable(void *garbage)
314{
2c8dceeb 315 cpu_svm_disable();
6aa8b732
AK		 316}
317
10474ae8 318static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 319{
320
0fe1e009 321 struct svm_cpu_data *sd;
6aa8b732 322 uint64_t efer;
89a27f4d 323 struct desc_ptr gdt_descr;
6aa8b732
AK		 324 struct desc_struct *gdt;
325 int me = raw_smp_processor_id();
326
10474ae8
AG		 327 rdmsrl(MSR_EFER, efer);
328 if (efer & EFER_SVME)
329 return -EBUSY;
330
6aa8b732 331 if (!has_svm()) {
e6732a5a
ZA		 332 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
333 me);
10474ae8 334 return -EINVAL;
6aa8b732 335 }
0fe1e009 336 sd = per_cpu(svm_data, me);
6aa8b732 337
0fe1e009 338 if (!sd) {
e6732a5a 339 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 340 me);
10474ae8 341 return -EINVAL;
6aa8b732
AK		 342 }
343
0fe1e009
TH		 344 sd->asid_generation = 1;
345 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
346 sd->next_asid = sd->max_asid + 1;
6aa8b732 347
b792c344 348 kvm_get_gdt(&gdt_descr);
89a27f4d 349 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 350 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 351
9962d032 352 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 353
d0316554 354 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 355
356 return 0;
6aa8b732
AK		 357}
358
0da1db75
JR		 359static void svm_cpu_uninit(int cpu)
360{
0fe1e009 361 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 362
0fe1e009 363 if (!sd)
0da1db75
JR		 364 return;
365
366 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 367 __free_page(sd->save_area);
368 kfree(sd);
0da1db75
JR		 369}
370
6aa8b732
AK		 371static int svm_cpu_init(int cpu)
372{
0fe1e009 373 struct svm_cpu_data *sd;
6aa8b732
AK		 374 int r;
375
0fe1e009
TH		 376 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
377 if (!sd)
6aa8b732 378 return -ENOMEM;
0fe1e009
TH		 379 sd->cpu = cpu;
380 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 381 r = -ENOMEM;
0fe1e009 382 if (!sd->save_area)
6aa8b732
AK		 383 goto err_1;
384
0fe1e009 385 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 386
387 return 0;
388
389err_1:
0fe1e009 390 kfree(sd);
6aa8b732
AK		 391 return r;
392
393}
394
bfc733a7
RR		 395static void set_msr_interception(u32 *msrpm, unsigned msr,
396 int read, int write)
6aa8b732
AK		 397{
398 int i;
399
400 for (i = 0; i < NUM_MSR_MAPS; i++) {
401 if (msr >= msrpm_ranges[i] &&
402 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
403 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
404 msrpm_ranges[i]) * 2;
405
406 u32 *base = msrpm + (msr_offset / 32);
407 u32 msr_shift = msr_offset % 32;
408 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
409 *base = (*base & ~(0x3 << msr_shift)) |
410 (mask << msr_shift);
bfc733a7 411 return;
6aa8b732
AK		 412 }
413 }
bfc733a7 414 BUG();
6aa8b732
AK		 415}
416
f65c229c
JR		 417static void svm_vcpu_init_msrpm(u32 *msrpm)
418{
419 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
420
421#ifdef CONFIG_X86_64
422 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
424 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
425 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
426 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
427 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
428#endif
429 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
430 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 431}
432
24e09cbf
JR		 433static void svm_enable_lbrv(struct vcpu_svm *svm)
434{
435 u32 *msrpm = svm->msrpm;
436
437 svm->vmcb->control.lbr_ctl = 1;
438 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
440 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
441 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
442}
443
444static void svm_disable_lbrv(struct vcpu_svm *svm)
445{
446 u32 *msrpm = svm->msrpm;
447
448 svm->vmcb->control.lbr_ctl = 0;
449 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
451 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
452 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
453}
454
6aa8b732
AK		 455static __init int svm_hardware_setup(void)
456{
457 int cpu;
458 struct page *iopm_pages;
f65c229c 459 void *iopm_va;
6aa8b732
AK		 460 int r;
461
6aa8b732
AK		 462 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
463
464 if (!iopm_pages)
465 return -ENOMEM;
c8681339
AL		 466
467 iopm_va = page_address(iopm_pages);
468 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 469 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
470
50a37eb4
JR		 471 if (boot_cpu_has(X86_FEATURE_NX))
472 kvm_enable_efer_bits(EFER_NX);
473
1b2fd70c
AG		 474 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
475 kvm_enable_efer_bits(EFER_FFXSR);
476
236de055
AG		 477 if (nested) {
478 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
479 kvm_enable_efer_bits(EFER_SVME);
480 }
481
3230bb47 482 for_each_possible_cpu(cpu) {
6aa8b732
AK		 483 r = svm_cpu_init(cpu);
484 if (r)
f65c229c 485 goto err;
6aa8b732 486 }
33bd6a0b
JR		 487
488 svm_features = cpuid_edx(SVM_CPUID_FUNC);
489
e3da3acd
JR		 490 if (!svm_has(SVM_FEATURE_NPT))
491 npt_enabled = false;
492
6c7dac72
JR		 493 if (npt_enabled && !npt) {
494 printk(KERN_INFO "kvm: Nested Paging disabled\n");
495 npt_enabled = false;
496 }
497
18552672 498 if (npt_enabled) {
e3da3acd 499 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 500 kvm_enable_tdp();
5f4cb662
JR		 501 } else
502 kvm_disable_tdp();
e3da3acd 503
6aa8b732
AK		 504 return 0;
505
f65c229c 506err:
6aa8b732
AK		 507 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
508 iopm_base = 0;
509 return r;
510}
511
512static __exit void svm_hardware_unsetup(void)
513{
0da1db75
JR		 514 int cpu;
515
3230bb47 516 for_each_possible_cpu(cpu)
0da1db75
JR		 517 svm_cpu_uninit(cpu);
518
6aa8b732 519 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 520 iopm_base = 0;
6aa8b732
AK		 521}
522
523static void init_seg(struct vmcb_seg *seg)
524{
525 seg->selector = 0;
526 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
527 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
528 seg->limit = 0xffff;
529 seg->base = 0;
530}
531
532static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
533{
534 seg->selector = 0;
535 seg->attrib = SVM_SELECTOR_P_MASK | type;
536 seg->limit = 0xffff;
537 seg->base = 0;
538}
539
e6101a96 540static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 541{
e6101a96
JR		 542 struct vmcb_control_area *control = &svm->vmcb->control;
543 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 544
bff78274
AK		 545 svm->vcpu.fpu_active = 1;
546
6aa8b732
AK		 547 control->intercept_cr_read = INTERCEPT_CR0_MASK |
548 INTERCEPT_CR3_MASK |
649d6864 549 INTERCEPT_CR4_MASK;
6aa8b732
AK		 550
551 control->intercept_cr_write = INTERCEPT_CR0_MASK |
552 INTERCEPT_CR3_MASK |
80a8119c
AK		 553 INTERCEPT_CR4_MASK |
554 INTERCEPT_CR8_MASK;
6aa8b732
AK		 555
556 control->intercept_dr_read = INTERCEPT_DR0_MASK |
557 INTERCEPT_DR1_MASK |
558 INTERCEPT_DR2_MASK |
727f5a23
JK		 559 INTERCEPT_DR3_MASK |
560 INTERCEPT_DR4_MASK |
561 INTERCEPT_DR5_MASK |
562 INTERCEPT_DR6_MASK |
563 INTERCEPT_DR7_MASK;
6aa8b732
AK		 564
565 control->intercept_dr_write = INTERCEPT_DR0_MASK |
566 INTERCEPT_DR1_MASK |
567 INTERCEPT_DR2_MASK |
568 INTERCEPT_DR3_MASK |
727f5a23 569 INTERCEPT_DR4_MASK |
6aa8b732 570 INTERCEPT_DR5_MASK |
727f5a23 571 INTERCEPT_DR6_MASK |
6aa8b732
AK		 572 INTERCEPT_DR7_MASK;
573
7aa81cc0 574 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 575 (1 << UD_VECTOR) |
576 (1 << MC_VECTOR);
6aa8b732
AK		 577
578
579 control->intercept = (1ULL << INTERCEPT_INTR) |
580 (1ULL << INTERCEPT_NMI) |
0152527b 581 (1ULL << INTERCEPT_SMI) |
d225157b 582 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 583 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 584 (1ULL << INTERCEPT_INVD) |
6aa8b732 585 (1ULL << INTERCEPT_HLT) |
a7052897 586 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 587 (1ULL << INTERCEPT_INVLPGA) |
588 (1ULL << INTERCEPT_IOIO_PROT) |
589 (1ULL << INTERCEPT_MSR_PROT) |
590 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 591 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 592 (1ULL << INTERCEPT_VMRUN) |
593 (1ULL << INTERCEPT_VMMCALL) |
594 (1ULL << INTERCEPT_VMLOAD) |
595 (1ULL << INTERCEPT_VMSAVE) |
596 (1ULL << INTERCEPT_STGI) |
597 (1ULL << INTERCEPT_CLGI) |
916ce236 598 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 599 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 600 (1ULL << INTERCEPT_MONITOR) |
601 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 602
603 control->iopm_base_pa = iopm_base;
f65c229c 604 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 605 control->tsc_offset = 0;
6aa8b732
AK		 606 control->int_ctl = V_INTR_MASKING_MASK;
607
608 init_seg(&save->es);
609 init_seg(&save->ss);
610 init_seg(&save->ds);
611 init_seg(&save->fs);
612 init_seg(&save->gs);
613
614 save->cs.selector = 0xf000;
615 /* Executable/Readable Code Segment */
616 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
617 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
618 save->cs.limit = 0xffff;
d92899a0
AK		 619 /*
620 * cs.base should really be 0xffff0000, but vmx can't handle that, so
621 * be consistent with it.
622 *
623 * Replace when we have real mode working for vmx.
624 */
625 save->cs.base = 0xf0000;
6aa8b732
AK		 626
627 save->gdtr.limit = 0xffff;
628 save->idtr.limit = 0xffff;
629
630 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
631 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
632
9962d032 633 save->efer = EFER_SVME;
d77c26fc 634 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 635 save->dr7 = 0x400;
636 save->rflags = 2;
637 save->rip = 0x0000fff0;
5fdbf976 638 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 639
18fa000a
EH		 640 /* This is the guest-visible cr0 value.
641 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 642 */
18fa000a
EH		 643 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
644 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
645
66aee91a 646 save->cr4 = X86_CR4_PAE;
6aa8b732 647 /* rdx = ?? */
709ddebf
JR		 648
649 if (npt_enabled) {
650 /* Setup VMCB for Nested Paging */
651 control->nested_ctl = 1;
a7052897
MT		 652 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
653 (1ULL << INTERCEPT_INVLPG));
709ddebf 654 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 655 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
656 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 657 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 658 save->cr3 = 0;
659 save->cr4 = 0;
660 }
a79d2f18 661 force_new_asid(&svm->vcpu);
1371d904 662
e6aa9abd 663 svm->nested.vmcb = 0;
2af9194d
JR		 664 svm->vcpu.arch.hflags = 0;
665
565d0998
ML		 666 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
667 control->pause_filter_count = 3000;
668 control->intercept |= (1ULL << INTERCEPT_PAUSE);
669 }
670
2af9194d 671 enable_gif(svm);
6aa8b732
AK		 672}
673
e00c8cf2 674static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 675{
676 struct vcpu_svm *svm = to_svm(vcpu);
677
e6101a96 678 init_vmcb(svm);
70433389 679
c5af89b6 680 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 681 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 682 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
683 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 684 }
5fdbf976
MT		 685 vcpu->arch.regs_avail = ~0;
686 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 687
688 return 0;
04d2cc77
AK		 689}
690
fb3f0f51 691static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 692{
a2fa3e9f 693 struct vcpu_svm *svm;
6aa8b732 694 struct page *page;
f65c229c 695 struct page *msrpm_pages;
b286d5d8 696 struct page *hsave_page;
3d6368ef 697 struct page *nested_msrpm_pages;
fb3f0f51 698 int err;
6aa8b732 699
c16f862d 700 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 701 if (!svm) {
702 err = -ENOMEM;
703 goto out;
704 }
705
706 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
707 if (err)
708 goto free_svm;
709
b7af4043 710 err = -ENOMEM;
6aa8b732 711 page = alloc_page(GFP_KERNEL);
b7af4043 712 if (!page)
fb3f0f51 713 goto uninit;
6aa8b732 714
f65c229c
JR		 715 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
716 if (!msrpm_pages)
b7af4043 717 goto free_page1;
3d6368ef
AG		 718
719 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
720 if (!nested_msrpm_pages)
b7af4043 721 goto free_page2;
f65c229c 722
b286d5d8
AG		 723 hsave_page = alloc_page(GFP_KERNEL);
724 if (!hsave_page)
b7af4043
TY		 725 goto free_page3;
726
e6aa9abd 727 svm->nested.hsave = page_address(hsave_page);
b286d5d8 728
b7af4043
TY		 729 svm->msrpm = page_address(msrpm_pages);
730 svm_vcpu_init_msrpm(svm->msrpm);
731
e6aa9abd 732 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 733
a2fa3e9f
GH		 734 svm->vmcb = page_address(page);
735 clear_page(svm->vmcb);
736 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
737 svm->asid_generation = 0;
e6101a96 738 init_vmcb(svm);
a2fa3e9f 739
fb3f0f51 740 fx_init(&svm->vcpu);
ad312c7c 741 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 742 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 743 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 744
fb3f0f51 745 return &svm->vcpu;
36241b8c 746
b7af4043
TY		 747free_page3:
748 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
749free_page2:
750 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
751free_page1:
752 __free_page(page);
fb3f0f51
RR		 753uninit:
754 kvm_vcpu_uninit(&svm->vcpu);
755free_svm:
a4770347 756 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 757out:
758 return ERR_PTR(err);
6aa8b732
AK		 759}
760
761static void svm_free_vcpu(struct kvm_vcpu *vcpu)
762{
a2fa3e9f
GH		 763 struct vcpu_svm *svm = to_svm(vcpu);
764
fb3f0f51 765 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 766 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 767 __free_page(virt_to_page(svm->nested.hsave));
768 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 769 kvm_vcpu_uninit(vcpu);
a4770347 770 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 771}
772
15ad7146 773static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 774{
a2fa3e9f 775 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 776 int i;
0cc5064d 777
0cc5064d 778 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 779 u64 delta;
0cc5064d 780
953899b6
JR		 781 if (check_tsc_unstable()) {
782 /*
783 * Make sure that the guest sees a monotonically
784 * increasing TSC.
785 */
786 delta = vcpu->arch.host_tsc - native_read_tsc();
787 svm->vmcb->control.tsc_offset += delta;
788 if (is_nested(svm))
789 svm->nested.hsave->control.tsc_offset += delta;
790 }
0cc5064d 791 vcpu->cpu = cpu;
2f599714 792 kvm_migrate_timers(vcpu);
4b656b12 793 svm->asid_generation = 0;
0cc5064d 794 }
94dfbdb3
AL		 795
796 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 797 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 798}
799
800static void svm_vcpu_put(struct kvm_vcpu *vcpu)
801{
a2fa3e9f 802 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 803 int i;
804
e1beb1d3 805 ++vcpu->stat.host_state_reload;
94dfbdb3 806 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 807 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 808
e935d48e 809 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 810}
811
6aa8b732
AK		 812static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
813{
a2fa3e9f 814 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 815}
816
817static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
818{
a2fa3e9f 819 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 820}
821
6de4f3ad
AK		 822static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
823{
824 switch (reg) {
825 case VCPU_EXREG_PDPTR:
826 BUG_ON(!npt_enabled);
827 load_pdptrs(vcpu, vcpu->arch.cr3);
828 break;
829 default:
830 BUG();
831 }
832}
833
f0b85051
AG		 834static void svm_set_vintr(struct vcpu_svm *svm)
835{
836 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
837}
838
839static void svm_clear_vintr(struct vcpu_svm *svm)
840{
841 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
842}
843
6aa8b732
AK		 844static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
845{
a2fa3e9f 846 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 847
848 switch (seg) {
849 case VCPU_SREG_CS: return &save->cs;
850 case VCPU_SREG_DS: return &save->ds;
851 case VCPU_SREG_ES: return &save->es;
852 case VCPU_SREG_FS: return &save->fs;
853 case VCPU_SREG_GS: return &save->gs;
854 case VCPU_SREG_SS: return &save->ss;
855 case VCPU_SREG_TR: return &save->tr;
856 case VCPU_SREG_LDTR: return &save->ldtr;
857 }
858 BUG();
8b6d44c7 859 return NULL;
6aa8b732
AK		 860}
861
862static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
863{
864 struct vmcb_seg *s = svm_seg(vcpu, seg);
865
866 return s->base;
867}
868
869static void svm_get_segment(struct kvm_vcpu *vcpu,
870 struct kvm_segment *var, int seg)
871{
872 struct vmcb_seg *s = svm_seg(vcpu, seg);
873
874 var->base = s->base;
875 var->limit = s->limit;
876 var->selector = s->selector;
877 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
878 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
879 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
880 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
881 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
882 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
883 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
884 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 885
19bca6ab
AP		 886 /* AMD's VMCB does not have an explicit unusable field, so emulate it
887 * for cross vendor migration purposes by "not present"
888 */
889 var->unusable = !var->present || (var->type == 0);
890
1fbdc7a5
AP		 891 switch (seg) {
892 case VCPU_SREG_CS:
893 /*
894 * SVM always stores 0 for the 'G' bit in the CS selector in
895 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
896 * Intel's VMENTRY has a check on the 'G' bit.
897 */
25022acc 898 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 899 break;
900 case VCPU_SREG_TR:
901 /*
902 * Work around a bug where the busy flag in the tr selector
903 * isn't exposed
904 */
c0d09828 905 var->type |= 0x2;
1fbdc7a5
AP		 906 break;
907 case VCPU_SREG_DS:
908 case VCPU_SREG_ES:
909 case VCPU_SREG_FS:
910 case VCPU_SREG_GS:
911 /*
912 * The accessed bit must always be set in the segment
913 * descriptor cache, although it can be cleared in the
914 * descriptor, the cached bit always remains at 1. Since
915 * Intel has a check on this, set it here to support
916 * cross-vendor migration.
917 */
918 if (!var->unusable)
919 var->type |= 0x1;
920 break;
b586eb02
AP		 921 case VCPU_SREG_SS:
922 /* On AMD CPUs sometimes the DB bit in the segment
923 * descriptor is left as 1, although the whole segment has
924 * been made unusable. Clear it here to pass an Intel VMX
925 * entry check when cross vendor migrating.
926 */
927 if (var->unusable)
928 var->db = 0;
929 break;
1fbdc7a5 930 }
6aa8b732
AK		 931}
932
2e4d2653
IE		 933static int svm_get_cpl(struct kvm_vcpu *vcpu)
934{
935 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
936
937 return save->cpl;
938}
939
89a27f4d 940static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 941{
a2fa3e9f
GH		 942 struct vcpu_svm *svm = to_svm(vcpu);
943
89a27f4d
GN		 944 dt->size = svm->vmcb->save.idtr.limit;
945 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 946}
947
89a27f4d 948static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 949{
a2fa3e9f
GH		 950 struct vcpu_svm *svm = to_svm(vcpu);
951
89a27f4d
GN		 952 svm->vmcb->save.idtr.limit = dt->size;
953 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 954}
955
89a27f4d 956static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 957{
a2fa3e9f
GH		 958 struct vcpu_svm *svm = to_svm(vcpu);
959
89a27f4d
GN		 960 dt->size = svm->vmcb->save.gdtr.limit;
961 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 962}
963
89a27f4d 964static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 965{
a2fa3e9f
GH		 966 struct vcpu_svm *svm = to_svm(vcpu);
967
89a27f4d
GN		 968 svm->vmcb->save.gdtr.limit = dt->size;
969 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 970}
971
e8467fda
AK		 972static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
973{
974}
975
25c4c276 976static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 977{
978}
979
d225157b
AK		 980static void update_cr0_intercept(struct vcpu_svm *svm)
981{
982 ulong gcr0 = svm->vcpu.arch.cr0;
983 u64 *hcr0 = &svm->vmcb->save.cr0;
984
985 if (!svm->vcpu.fpu_active)
986 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
987 else
988 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
989 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
990
991
992 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
993 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
994 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
995 } else {
996 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
997 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
998 }
999}
1000
6aa8b732
AK		 1001static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1002{
a2fa3e9f
GH		 1003 struct vcpu_svm *svm = to_svm(vcpu);
1004
05b3e0c2 1005#ifdef CONFIG_X86_64
f6801dff 1006 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1007 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1008 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1009 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1010 }
1011
d77c26fc 1012 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1013 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1014 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1015 }
1016 }
1017#endif
ad312c7c 1018 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1019
1020 if (!npt_enabled)
1021 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1022
1023 if (!vcpu->fpu_active)
334df50a 1024 cr0 |= X86_CR0_TS;
709ddebf
JR		 1025 /*
1026 * re-enable caching here because the QEMU bios
1027 * does not do it - this results in some delay at
1028 * reboot
1029 */
1030 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1031 svm->vmcb->save.cr0 = cr0;
d225157b 1032 update_cr0_intercept(svm);
6aa8b732
AK		 1033}
1034
1035static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1036{
6394b649 1037 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1038 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1039
1040 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1041 force_new_asid(vcpu);
6394b649 1042
ec077263
JR		 1043 vcpu->arch.cr4 = cr4;
1044 if (!npt_enabled)
1045 cr4 |= X86_CR4_PAE;
6394b649 1046 cr4 |= host_cr4_mce;
ec077263 1047 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1048}
1049
1050static void svm_set_segment(struct kvm_vcpu *vcpu,
1051 struct kvm_segment *var, int seg)
1052{
a2fa3e9f 1053 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1054 struct vmcb_seg *s = svm_seg(vcpu, seg);
1055
1056 s->base = var->base;
1057 s->limit = var->limit;
1058 s->selector = var->selector;
1059 if (var->unusable)
1060 s->attrib = 0;
1061 else {
1062 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1063 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1064 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1065 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1066 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1067 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1068 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1069 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1070 }
1071 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1072 svm->vmcb->save.cpl
1073 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1074 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1075
1076}
1077
44c11430 1078static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1079{
d0bfb940
JK		 1080 struct vcpu_svm *svm = to_svm(vcpu);
1081
d0bfb940
JK		 1082 svm->vmcb->control.intercept_exceptions &=
1083 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1084
6be7d306 1085 if (svm->nmi_singlestep)
44c11430
GN		 1086 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1087
d0bfb940
JK		 1088 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1089 if (vcpu->guest_debug &
1090 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1091 svm->vmcb->control.intercept_exceptions |=
1092 1 << DB_VECTOR;
1093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1094 svm->vmcb->control.intercept_exceptions |=
1095 1 << BP_VECTOR;
1096 } else
1097 vcpu->guest_debug = 0;
44c11430
GN		 1098}
1099
355be0b9 1100static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1101{
44c11430
GN		 1102 struct vcpu_svm *svm = to_svm(vcpu);
1103
ae675ef0
JK		 1104 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1105 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1106 else
1107 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1108
355be0b9 1109 update_db_intercept(vcpu);
6aa8b732
AK		 1110}
1111
1112static void load_host_msrs(struct kvm_vcpu *vcpu)
1113{
94dfbdb3 1114#ifdef CONFIG_X86_64
a2fa3e9f 1115 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1116#endif
6aa8b732
AK		 1117}
1118
1119static void save_host_msrs(struct kvm_vcpu *vcpu)
1120{
94dfbdb3 1121#ifdef CONFIG_X86_64
a2fa3e9f 1122 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1123#endif
6aa8b732
AK		 1124}
1125
0fe1e009 1126static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1127{
0fe1e009
TH		 1128 if (sd->next_asid > sd->max_asid) {
1129 ++sd->asid_generation;
1130 sd->next_asid = 1;
a2fa3e9f 1131 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1132 }
1133
0fe1e009
TH		 1134 svm->asid_generation = sd->asid_generation;
1135 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1136}
1137
c76de350 1138static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1139{
42dbaa5a 1140 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1141
1142 switch (dr) {
1143 case 0 ... 3:
c76de350 1144 *dest = vcpu->arch.db[dr];
42dbaa5a 1145 break;
c76de350
JK		 1146 case 4:
1147 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1148 return EMULATE_FAIL; /* will re-inject UD */
1149 /* fall through */
42dbaa5a
JK		 1150 case 6:
1151 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1152 *dest = vcpu->arch.dr6;
42dbaa5a 1153 else
c76de350 1154 *dest = svm->vmcb->save.dr6;
42dbaa5a 1155 break;
c76de350
JK		 1156 case 5:
1157 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1158 return EMULATE_FAIL; /* will re-inject UD */
1159 /* fall through */
42dbaa5a
JK		 1160 case 7:
1161 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1162 *dest = vcpu->arch.dr7;
42dbaa5a 1163 else
c76de350 1164 *dest = svm->vmcb->save.dr7;
42dbaa5a 1165 break;
42dbaa5a
JK		 1166 }
1167
c76de350 1168 return EMULATE_DONE;
6aa8b732
AK		 1169}
1170
c76de350 1171static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1172{
a2fa3e9f
GH		 1173 struct vcpu_svm *svm = to_svm(vcpu);
1174
6aa8b732
AK		 1175 switch (dr) {
1176 case 0 ... 3:
42dbaa5a
JK		 1177 vcpu->arch.db[dr] = value;
1178 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1179 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1180 break;
1181 case 4:
1182 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1183 return EMULATE_FAIL; /* will re-inject UD */
1184 /* fall through */
42dbaa5a 1185 case 6:
42dbaa5a 1186 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1187 break;
1188 case 5:
1189 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1190 return EMULATE_FAIL; /* will re-inject UD */
1191 /* fall through */
42dbaa5a 1192 case 7:
42dbaa5a
JK		 1193 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1194 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1195 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1196 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1197 }
c76de350 1198 break;
6aa8b732 1199 }
c76de350
JK		 1200
1201 return EMULATE_DONE;
6aa8b732
AK		 1202}
1203
851ba692 1204static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1205{
6aa8b732
AK		 1206 u64 fault_address;
1207 u32 error_code;
6aa8b732 1208
a2fa3e9f
GH		 1209 fault_address = svm->vmcb->control.exit_info_2;
1210 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1211
229456fc 1212 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1213 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1214 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1215 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1216}
1217
851ba692 1218static int db_interception(struct vcpu_svm *svm)
d0bfb940 1219{
851ba692
AK		 1220 struct kvm_run *kvm_run = svm->vcpu.run;
1221
d0bfb940 1222 if (!(svm->vcpu.guest_debug &
44c11430 1223 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1224 !svm->nmi_singlestep) {
d0bfb940
JK		 1225 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1226 return 1;
1227 }
44c11430 1228
6be7d306
JK		 1229 if (svm->nmi_singlestep) {
1230 svm->nmi_singlestep = false;
44c11430
GN		 1231 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1232 svm->vmcb->save.rflags &=
1233 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1234 update_db_intercept(&svm->vcpu);
1235 }
1236
1237 if (svm->vcpu.guest_debug &
1238 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1239 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1240 kvm_run->debug.arch.pc =
1241 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1242 kvm_run->debug.arch.exception = DB_VECTOR;
1243 return 0;
1244 }
1245
1246 return 1;
d0bfb940
JK		 1247}
1248
851ba692 1249static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1250{
851ba692
AK		 1251 struct kvm_run *kvm_run = svm->vcpu.run;
1252
d0bfb940
JK		 1253 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1254 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1255 kvm_run->debug.arch.exception = BP_VECTOR;
1256 return 0;
1257}
1258
851ba692 1259static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1260{
1261 int er;
1262
851ba692 1263 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1264 if (er != EMULATE_DONE)
7ee5d940 1265 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1266 return 1;
1267}
1268
6b52d186 1269static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1270{
6b52d186 1271 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 1272 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
e756fc62 1273 svm->vcpu.fpu_active = 1;
d225157b 1274 update_cr0_intercept(svm);
6b52d186 1275}
a2fa3e9f 1276
6b52d186
AK		 1277static int nm_interception(struct vcpu_svm *svm)
1278{
1279 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1280 return 1;
7807fa6c
AL		 1281}
1282
851ba692 1283static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1284{
1285 /*
1286 * On an #MC intercept the MCE handler is not called automatically in
1287 * the host. So do it by hand here.
1288 */
1289 asm volatile (
1290 "int $0x12\n");
1291 /* not sure if we ever come back to this point */
1292
1293 return 1;
1294}
1295
851ba692 1296static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1297{
851ba692
AK		 1298 struct kvm_run *kvm_run = svm->vcpu.run;
1299
46fe4ddd
JR		 1300 /*
1301 * VMCB is undefined after a SHUTDOWN intercept
1302 * so reinitialize it.
1303 */
a2fa3e9f 1304 clear_page(svm->vmcb);
e6101a96 1305 init_vmcb(svm);
46fe4ddd
JR		 1306
1307 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1308 return 0;
1309}
1310
851ba692 1311static int io_interception(struct vcpu_svm *svm)
6aa8b732 1312{
d77c26fc 1313 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1314 int size, in, string;
039576c0 1315 unsigned port;
6aa8b732 1316
e756fc62 1317 ++svm->vcpu.stat.io_exits;
6aa8b732 1318
a2fa3e9f 1319 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1320
e70669ab
LV		 1321 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1322
1323 if (string) {
3427318f 1324 if (emulate_instruction(&svm->vcpu,
851ba692 1325 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1326 return 0;
1327 return 1;
1328 }
1329
039576c0
AK		 1330 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1331 port = io_info >> 16;
1332 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1333
e93f36bc 1334 skip_emulated_instruction(&svm->vcpu);
851ba692 1335 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1336}
1337
851ba692 1338static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1339{
1340 return 1;
1341}
1342
851ba692 1343static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1344{
1345 ++svm->vcpu.stat.irq_exits;
1346 return 1;
1347}
1348
851ba692 1349static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1350{
1351 return 1;
1352}
1353
851ba692 1354static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1355{
5fdbf976 1356 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1357 skip_emulated_instruction(&svm->vcpu);
1358 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1359}
1360
851ba692 1361static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1362{
5fdbf976 1363 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1364 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1365 kvm_emulate_hypercall(&svm->vcpu);
1366 return 1;
02e235bc
AK		 1367}
1368
c0725420
AG		 1369static int nested_svm_check_permissions(struct vcpu_svm *svm)
1370{
f6801dff 1371 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1372 || !is_paging(&svm->vcpu)) {
1373 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1374 return 1;
1375 }
1376
1377 if (svm->vmcb->save.cpl) {
1378 kvm_inject_gp(&svm->vcpu, 0);
1379 return 1;
1380 }
1381
1382 return 0;
1383}
1384
cf74a78b
AG		 1385static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1386 bool has_error_code, u32 error_code)
1387{
b8e88bc8
JR		 1388 int vmexit;
1389
0295ad7d
JR		 1390 if (!is_nested(svm))
1391 return 0;
cf74a78b 1392
0295ad7d
JR		 1393 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1394 svm->vmcb->control.exit_code_hi = 0;
1395 svm->vmcb->control.exit_info_1 = error_code;
1396 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1397
b8e88bc8
JR		 1398 vmexit = nested_svm_intercept(svm);
1399 if (vmexit == NESTED_EXIT_DONE)
1400 svm->nested.exit_required = true;
1401
1402 return vmexit;
cf74a78b
AG		 1403}
1404
1405static inline int nested_svm_intr(struct vcpu_svm *svm)
1406{
26666957
JR		 1407 if (!is_nested(svm))
1408 return 0;
cf74a78b 1409
26666957
JR		 1410 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1411 return 0;
cf74a78b 1412
26666957
JR		 1413 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1414 return 0;
cf74a78b 1415
26666957
JR		 1416 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1417
cd3ff653
JR		 1418 if (svm->nested.intercept & 1ULL) {
1419 /*
1420 * The #vmexit can't be emulated here directly because this
1421 * code path runs with irqs and preemtion disabled. A
1422 * #vmexit emulation might sleep. Only signal request for
1423 * the #vmexit here.
1424 */
1425 svm->nested.exit_required = true;
236649de 1426 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
26666957 1427 return 1;
cf74a78b
AG		 1428 }
1429
1430 return 0;
1431}
1432
7597f129 1433static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1434{
1435 struct page *page;
1436
34f80cfa 1437 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1438 if (is_error_page(page))
1439 goto error;
1440
7597f129
JR		 1441 *_page = page;
1442
1443 return kmap(page);
34f80cfa
JR		 1444
1445error:
1446 kvm_release_page_clean(page);
1447 kvm_inject_gp(&svm->vcpu, 0);
1448
1449 return NULL;
1450}
1451
7597f129 1452static void nested_svm_unmap(struct page *page)
34f80cfa 1453{
7597f129 1454 kunmap(page);
34f80cfa
JR		 1455 kvm_release_page_dirty(page);
1456}
1457
3d62d9aa 1458static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1459{
4c2161ae 1460 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa 1461 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
7597f129 1462 struct page *page;
3d62d9aa
JR		 1463 bool ret = false;
1464 u32 t0, t1;
1465 u8 *msrpm;
4c2161ae 1466
3d62d9aa
JR		 1467 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1468 return false;
1469
7597f129 1470 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
3d62d9aa
JR		 1471
1472 if (!msrpm)
1473 goto out;
4c2161ae
JR		 1474
1475 switch (msr) {
1476 case 0 ... 0x1fff:
1477 t0 = (msr * 2) % 8;
1478 t1 = msr / 8;
1479 break;
1480 case 0xc0000000 ... 0xc0001fff:
1481 t0 = (8192 + msr - 0xc0000000) * 2;
1482 t1 = (t0 / 8);
1483 t0 %= 8;
1484 break;
1485 case 0xc0010000 ... 0xc0011fff:
1486 t0 = (16384 + msr - 0xc0010000) * 2;
1487 t1 = (t0 / 8);
1488 t0 %= 8;
1489 break;
1490 default:
3d62d9aa
JR		 1491 ret = true;
1492 goto out;
4c2161ae 1493 }
4c2161ae 1494
3d62d9aa
JR		 1495 ret = msrpm[t1] & ((1 << param) << t0);
1496
1497out:
7597f129 1498 nested_svm_unmap(page);
3d62d9aa
JR		 1499
1500 return ret;
4c2161ae
JR		 1501}
1502
410e4d57 1503static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1504{
cf74a78b 1505 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1506
410e4d57
JR		 1507 switch (exit_code) {
1508 case SVM_EXIT_INTR:
1509 case SVM_EXIT_NMI:
1510 return NESTED_EXIT_HOST;
cf74a78b 1511 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1512 case SVM_EXIT_NPF:
1513 if (npt_enabled)
1514 return NESTED_EXIT_HOST;
1515 break;
1516 /* When we're shadowing, trap PFs */
1517 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1518 if (!npt_enabled)
1519 return NESTED_EXIT_HOST;
1520 break;
1521 default:
1522 break;
cf74a78b
AG		 1523 }
1524
410e4d57
JR		 1525 return NESTED_EXIT_CONTINUE;
1526}
1527
1528/*
1529 * If this function returns true, this #vmexit was already handled
1530 */
b8e88bc8 1531static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1532{
1533 u32 exit_code = svm->vmcb->control.exit_code;
1534 int vmexit = NESTED_EXIT_HOST;
1535
cf74a78b 1536 switch (exit_code) {
9c4e40b9 1537 case SVM_EXIT_MSR:
3d62d9aa 1538 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1539 break;
cf74a78b
AG		 1540 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1541 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1542 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1543 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1544 break;
1545 }
1546 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1547 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1548 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1549 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1550 break;
1551 }
1552 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1553 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1554 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1555 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1556 break;
1557 }
1558 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1559 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1560 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1561 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1562 break;
1563 }
1564 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1565 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1566 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1567 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1568 break;
1569 }
1570 default: {
1571 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1572 if (svm->nested.intercept & exit_bits)
410e4d57 1573 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1574 }
1575 }
1576
b8e88bc8
JR		 1577 return vmexit;
1578}
1579
1580static int nested_svm_exit_handled(struct vcpu_svm *svm)
1581{
1582 int vmexit;
1583
1584 vmexit = nested_svm_intercept(svm);
1585
1586 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1587 nested_svm_vmexit(svm);
9c4e40b9
JR		 1588
1589 return vmexit;
cf74a78b
AG		 1590}
1591
0460a979
JR		 1592static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1593{
1594 struct vmcb_control_area *dst = &dst_vmcb->control;
1595 struct vmcb_control_area *from = &from_vmcb->control;
1596
1597 dst->intercept_cr_read = from->intercept_cr_read;
1598 dst->intercept_cr_write = from->intercept_cr_write;
1599 dst->intercept_dr_read = from->intercept_dr_read;
1600 dst->intercept_dr_write = from->intercept_dr_write;
1601 dst->intercept_exceptions = from->intercept_exceptions;
1602 dst->intercept = from->intercept;
1603 dst->iopm_base_pa = from->iopm_base_pa;
1604 dst->msrpm_base_pa = from->msrpm_base_pa;
1605 dst->tsc_offset = from->tsc_offset;
1606 dst->asid = from->asid;
1607 dst->tlb_ctl = from->tlb_ctl;
1608 dst->int_ctl = from->int_ctl;
1609 dst->int_vector = from->int_vector;
1610 dst->int_state = from->int_state;
1611 dst->exit_code = from->exit_code;
1612 dst->exit_code_hi = from->exit_code_hi;
1613 dst->exit_info_1 = from->exit_info_1;
1614 dst->exit_info_2 = from->exit_info_2;
1615 dst->exit_int_info = from->exit_int_info;
1616 dst->exit_int_info_err = from->exit_int_info_err;
1617 dst->nested_ctl = from->nested_ctl;
1618 dst->event_inj = from->event_inj;
1619 dst->event_inj_err = from->event_inj_err;
1620 dst->nested_cr3 = from->nested_cr3;
1621 dst->lbr_ctl = from->lbr_ctl;
1622}
1623
34f80cfa 1624static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1625{
34f80cfa 1626 struct vmcb *nested_vmcb;
e6aa9abd 1627 struct vmcb *hsave = svm->nested.hsave;
33740e40 1628 struct vmcb *vmcb = svm->vmcb;
7597f129 1629 struct page *page;
cf74a78b 1630
17897f36
JR		 1631 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1632 vmcb->control.exit_info_1,
1633 vmcb->control.exit_info_2,
1634 vmcb->control.exit_int_info,
1635 vmcb->control.exit_int_info_err);
1636
7597f129 1637 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1638 if (!nested_vmcb)
1639 return 1;
1640
cf74a78b 1641 /* Give the current vmcb to the guest */
33740e40
JR		 1642 disable_gif(svm);
1643
1644 nested_vmcb->save.es = vmcb->save.es;
1645 nested_vmcb->save.cs = vmcb->save.cs;
1646 nested_vmcb->save.ss = vmcb->save.ss;
1647 nested_vmcb->save.ds = vmcb->save.ds;
1648 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1649 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1650 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1651 if (npt_enabled)
1652 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1653 else
1654 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1655 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1656 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1657 nested_vmcb->save.rflags = vmcb->save.rflags;
1658 nested_vmcb->save.rip = vmcb->save.rip;
1659 nested_vmcb->save.rsp = vmcb->save.rsp;
1660 nested_vmcb->save.rax = vmcb->save.rax;
1661 nested_vmcb->save.dr7 = vmcb->save.dr7;
1662 nested_vmcb->save.dr6 = vmcb->save.dr6;
1663 nested_vmcb->save.cpl = vmcb->save.cpl;
1664
1665 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1666 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1667 nested_vmcb->control.int_state = vmcb->control.int_state;
1668 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1669 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1670 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1671 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1672 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1673 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1674
1675 /*
1676 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1677 * to make sure that we do not lose injected events. So check event_inj
1678 * here and copy it to exit_int_info if it is valid.
1679 * Exit_int_info and event_inj can't be both valid because the case
1680 * below only happens on a VMRUN instruction intercept which has
1681 * no valid exit_int_info set.
1682 */
1683 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1684 struct vmcb_control_area *nc = &nested_vmcb->control;
1685
1686 nc->exit_int_info = vmcb->control.event_inj;
1687 nc->exit_int_info_err = vmcb->control.event_inj_err;
1688 }
1689
33740e40
JR		 1690 nested_vmcb->control.tlb_ctl = 0;
1691 nested_vmcb->control.event_inj = 0;
1692 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1693
1694 /* We always set V_INTR_MASKING and remember the old value in hflags */
1695 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1696 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1697
cf74a78b 1698 /* Restore the original control entries */
0460a979 1699 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1700
219b65dc
AG		 1701 kvm_clear_exception_queue(&svm->vcpu);
1702 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1703
1704 /* Restore selected save entries */
1705 svm->vmcb->save.es = hsave->save.es;
1706 svm->vmcb->save.cs = hsave->save.cs;
1707 svm->vmcb->save.ss = hsave->save.ss;
1708 svm->vmcb->save.ds = hsave->save.ds;
1709 svm->vmcb->save.gdtr = hsave->save.gdtr;
1710 svm->vmcb->save.idtr = hsave->save.idtr;
1711 svm->vmcb->save.rflags = hsave->save.rflags;
1712 svm_set_efer(&svm->vcpu, hsave->save.efer);
1713 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1714 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1715 if (npt_enabled) {
1716 svm->vmcb->save.cr3 = hsave->save.cr3;
1717 svm->vcpu.arch.cr3 = hsave->save.cr3;
1718 } else {
1719 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1720 }
1721 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1722 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1723 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1724 svm->vmcb->save.dr7 = 0;
1725 svm->vmcb->save.cpl = 0;
1726 svm->vmcb->control.exit_int_info = 0;
1727
cf74a78b 1728 /* Exit nested SVM mode */
e6aa9abd 1729 svm->nested.vmcb = 0;
cf74a78b 1730
7597f129 1731 nested_svm_unmap(page);
cf74a78b
AG		 1732
1733 kvm_mmu_reset_context(&svm->vcpu);
1734 kvm_mmu_load(&svm->vcpu);
1735
1736 return 0;
1737}
3d6368ef 1738
9738b2c9 1739static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1740{
9738b2c9 1741 u32 *nested_msrpm;
7597f129 1742 struct page *page;
3d6368ef 1743 int i;
9738b2c9 1744
7597f129 1745 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
9738b2c9
JR		 1746 if (!nested_msrpm)
1747 return false;
1748
3d6368ef 1749 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1750 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1751
e6aa9abd 1752 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1753
7597f129 1754 nested_svm_unmap(page);
9738b2c9
JR		 1755
1756 return true;
3d6368ef
AG		 1757}
1758
9738b2c9 1759static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1760{
9738b2c9 1761 struct vmcb *nested_vmcb;
e6aa9abd 1762 struct vmcb *hsave = svm->nested.hsave;
defbba56 1763 struct vmcb *vmcb = svm->vmcb;
7597f129 1764 struct page *page;
3d6368ef 1765
7597f129 1766 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1767 if (!nested_vmcb)
1768 return false;
1769
3d6368ef 1770 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1771 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef 1772
0ac406de
JR		 1773 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1774 nested_vmcb->save.rip,
1775 nested_vmcb->control.int_ctl,
1776 nested_vmcb->control.event_inj,
1777 nested_vmcb->control.nested_ctl);
1778
3d6368ef 1779 /* Clear internal status */
219b65dc
AG		 1780 kvm_clear_exception_queue(&svm->vcpu);
1781 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1782
1783 /* Save the old vmcb, so we don't need to pick what we save, but
1784 can restore everything when a VMEXIT occurs */
defbba56
JR		 1785 hsave->save.es = vmcb->save.es;
1786 hsave->save.cs = vmcb->save.cs;
1787 hsave->save.ss = vmcb->save.ss;
1788 hsave->save.ds = vmcb->save.ds;
1789 hsave->save.gdtr = vmcb->save.gdtr;
1790 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1791 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1792 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1793 hsave->save.cr4 = svm->vcpu.arch.cr4;
1794 hsave->save.rflags = vmcb->save.rflags;
1795 hsave->save.rip = svm->next_rip;
1796 hsave->save.rsp = vmcb->save.rsp;
1797 hsave->save.rax = vmcb->save.rax;
1798 if (npt_enabled)
1799 hsave->save.cr3 = vmcb->save.cr3;
1800 else
1801 hsave->save.cr3 = svm->vcpu.arch.cr3;
1802
0460a979 1803 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1804
1805 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1806 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1807 else
1808 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1809
1810 /* Load the nested guest state */
1811 svm->vmcb->save.es = nested_vmcb->save.es;
1812 svm->vmcb->save.cs = nested_vmcb->save.cs;
1813 svm->vmcb->save.ss = nested_vmcb->save.ss;
1814 svm->vmcb->save.ds = nested_vmcb->save.ds;
1815 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1816 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1817 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1818 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1819 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1820 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1821 if (npt_enabled) {
1822 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1823 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1824 } else {
1825 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1826 kvm_mmu_reset_context(&svm->vcpu);
1827 }
defbba56 1828 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1829 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1830 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1831 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1832 /* In case we don't even reach vcpu_run, the fields are not updated */
1833 svm->vmcb->save.rax = nested_vmcb->save.rax;
1834 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1835 svm->vmcb->save.rip = nested_vmcb->save.rip;
1836 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1837 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1838 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1839
1840 /* We don't want a nested guest to be more powerful than the guest,
1841 so all intercepts are ORed */
1842 svm->vmcb->control.intercept_cr_read |=
1843 nested_vmcb->control.intercept_cr_read;
1844 svm->vmcb->control.intercept_cr_write |=
1845 nested_vmcb->control.intercept_cr_write;
1846 svm->vmcb->control.intercept_dr_read |=
1847 nested_vmcb->control.intercept_dr_read;
1848 svm->vmcb->control.intercept_dr_write |=
1849 nested_vmcb->control.intercept_dr_write;
1850 svm->vmcb->control.intercept_exceptions |=
1851 nested_vmcb->control.intercept_exceptions;
1852
1853 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1854
e6aa9abd 1855 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1856
aad42c64
JR		 1857 /* cache intercepts */
1858 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1859 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1860 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1861 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1862 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1863 svm->nested.intercept = nested_vmcb->control.intercept;
1864
3d6368ef 1865 force_new_asid(&svm->vcpu);
3d6368ef 1866 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1867 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1868 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1869 else
1870 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1871
3d6368ef
AG		 1872 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1873 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1874 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1875 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1876 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1877
7597f129 1878 nested_svm_unmap(page);
9738b2c9 1879
2af9194d 1880 enable_gif(svm);
3d6368ef 1881
9738b2c9 1882 return true;
3d6368ef
AG		 1883}
1884
9966bf68 1885static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1886{
1887 to_vmcb->save.fs = from_vmcb->save.fs;
1888 to_vmcb->save.gs = from_vmcb->save.gs;
1889 to_vmcb->save.tr = from_vmcb->save.tr;
1890 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1891 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1892 to_vmcb->save.star = from_vmcb->save.star;
1893 to_vmcb->save.lstar = from_vmcb->save.lstar;
1894 to_vmcb->save.cstar = from_vmcb->save.cstar;
1895 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1896 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1897 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1898 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1899}
1900
851ba692 1901static int vmload_interception(struct vcpu_svm *svm)
5542675b 1902{
9966bf68 1903 struct vmcb *nested_vmcb;
7597f129 1904 struct page *page;
9966bf68 1905
5542675b
AG		 1906 if (nested_svm_check_permissions(svm))
1907 return 1;
1908
1909 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1910 skip_emulated_instruction(&svm->vcpu);
1911
7597f129 1912 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 1913 if (!nested_vmcb)
1914 return 1;
1915
1916 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 1917 nested_svm_unmap(page);
5542675b
AG		 1918
1919 return 1;
1920}
1921
851ba692 1922static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1923{
9966bf68 1924 struct vmcb *nested_vmcb;
7597f129 1925 struct page *page;
9966bf68 1926
5542675b
AG		 1927 if (nested_svm_check_permissions(svm))
1928 return 1;
1929
1930 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1931 skip_emulated_instruction(&svm->vcpu);
1932
7597f129 1933 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 1934 if (!nested_vmcb)
1935 return 1;
1936
1937 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 1938 nested_svm_unmap(page);
5542675b
AG		 1939
1940 return 1;
1941}
1942
851ba692 1943static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1944{
3d6368ef
AG		 1945 if (nested_svm_check_permissions(svm))
1946 return 1;
1947
1948 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1949 skip_emulated_instruction(&svm->vcpu);
1950
9738b2c9 1951 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1952 return 1;
1953
9738b2c9 1954 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1955 goto failed;
1956
1957 return 1;
1958
1959failed:
1960
1961 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1962 svm->vmcb->control.exit_code_hi = 0;
1963 svm->vmcb->control.exit_info_1 = 0;
1964 svm->vmcb->control.exit_info_2 = 0;
1965
1966 nested_svm_vmexit(svm);
3d6368ef
AG		 1967
1968 return 1;
1969}
1970
851ba692 1971static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1972{
1973 if (nested_svm_check_permissions(svm))
1974 return 1;
1975
1976 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1977 skip_emulated_instruction(&svm->vcpu);
1978
2af9194d 1979 enable_gif(svm);
1371d904
AG		 1980
1981 return 1;
1982}
1983
851ba692 1984static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1985{
1986 if (nested_svm_check_permissions(svm))
1987 return 1;
1988
1989 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1990 skip_emulated_instruction(&svm->vcpu);
1991
2af9194d 1992 disable_gif(svm);
1371d904
AG		 1993
1994 /* After a CLGI no interrupts should come */
1995 svm_clear_vintr(svm);
1996 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1997
1998 return 1;
1999}
2000
851ba692 2001static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2002{
2003 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2004
ec1ff790
JR		 2005 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2006 vcpu->arch.regs[VCPU_REGS_RAX]);
2007
ff092385
AG		 2008 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2009 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2010
2011 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2012 skip_emulated_instruction(&svm->vcpu);
2013 return 1;
2014}
2015
532a46b9
JR		 2016static int skinit_interception(struct vcpu_svm *svm)
2017{
2018 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2019
2020 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2021 return 1;
2022}
2023
851ba692 2024static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2025{
7ee5d940 2026 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2027 return 1;
2028}
2029
851ba692 2030static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2031{
37817f29 2032 u16 tss_selector;
64a7ec06
GN		 2033 int reason;
2034 int int_type = svm->vmcb->control.exit_int_info &
2035 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2036 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2037 uint32_t type =
2038 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2039 uint32_t idt_v =
2040 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2041
2042 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2043
37817f29
IE		 2044 if (svm->vmcb->control.exit_info_2 &
2045 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2046 reason = TASK_SWITCH_IRET;
2047 else if (svm->vmcb->control.exit_info_2 &
2048 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2049 reason = TASK_SWITCH_JMP;
fe8e7f83 2050 else if (idt_v)
64a7ec06
GN		 2051 reason = TASK_SWITCH_GATE;
2052 else
2053 reason = TASK_SWITCH_CALL;
2054
fe8e7f83
GN		 2055 if (reason == TASK_SWITCH_GATE) {
2056 switch (type) {
2057 case SVM_EXITINTINFO_TYPE_NMI:
2058 svm->vcpu.arch.nmi_injected = false;
2059 break;
2060 case SVM_EXITINTINFO_TYPE_EXEPT:
2061 kvm_clear_exception_queue(&svm->vcpu);
2062 break;
2063 case SVM_EXITINTINFO_TYPE_INTR:
2064 kvm_clear_interrupt_queue(&svm->vcpu);
2065 break;
2066 default:
2067 break;
2068 }
2069 }
64a7ec06 2070
8317c298
GN		 2071 if (reason != TASK_SWITCH_GATE ||
2072 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2073 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2074 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2075 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2076
2077 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2078}
2079
851ba692 2080static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2081{
5fdbf976 2082 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2083 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2084 return 1;
6aa8b732
AK		 2085}
2086
851ba692 2087static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2088{
2089 ++svm->vcpu.stat.nmi_window_exits;
2090 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2091 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2092 return 1;
2093}
2094
851ba692 2095static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2096{
851ba692 2097 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2098 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2099 return 1;
2100}
2101
851ba692 2102static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2103{
851ba692 2104 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2105 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2106 return 1;
2107}
2108
851ba692 2109static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2110{
851ba692
AK		 2111 struct kvm_run *kvm_run = svm->vcpu.run;
2112
0a5fff19
GN		 2113 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2114 /* instruction emulation calls kvm_set_cr8() */
851ba692 2115 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2116 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2117 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2118 return 1;
95ba8273 2119 }
0a5fff19
GN		 2120 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2121 return 1;
1d075434
JR		 2122 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2123 return 0;
2124}
2125
6aa8b732
AK		 2126static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2127{
a2fa3e9f
GH		 2128 struct vcpu_svm *svm = to_svm(vcpu);
2129
6aa8b732 2130 switch (ecx) {
af24a4e4 2131 case MSR_IA32_TSC: {
20824f30 2132 u64 tsc_offset;
6aa8b732 2133
20824f30
JR		 2134 if (is_nested(svm))
2135 tsc_offset = svm->nested.hsave->control.tsc_offset;
2136 else
2137 tsc_offset = svm->vmcb->control.tsc_offset;
2138
2139 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2140 break;
2141 }
0e859cac 2142 case MSR_K6_STAR:
a2fa3e9f 2143 *data = svm->vmcb->save.star;
6aa8b732 2144 break;
0e859cac 2145#ifdef CONFIG_X86_64
6aa8b732 2146 case MSR_LSTAR:
a2fa3e9f 2147 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2148 break;
2149 case MSR_CSTAR:
a2fa3e9f 2150 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2151 break;
2152 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2153 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2154 break;
2155 case MSR_SYSCALL_MASK:
a2fa3e9f 2156 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2157 break;
2158#endif
2159 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2160 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2161 break;
2162 case MSR_IA32_SYSENTER_EIP:
017cb99e 2163 *data = svm->sysenter_eip;
6aa8b732
AK		 2164 break;
2165 case MSR_IA32_SYSENTER_ESP:
017cb99e 2166 *data = svm->sysenter_esp;
6aa8b732 2167 break;
a2938c80
JR		 2168 /* Nobody will change the following 5 values in the VMCB so
2169 we can safely return them on rdmsr. They will always be 0
2170 until LBRV is implemented. */
2171 case MSR_IA32_DEBUGCTLMSR:
2172 *data = svm->vmcb->save.dbgctl;
2173 break;
2174 case MSR_IA32_LASTBRANCHFROMIP:
2175 *data = svm->vmcb->save.br_from;
2176 break;
2177 case MSR_IA32_LASTBRANCHTOIP:
2178 *data = svm->vmcb->save.br_to;
2179 break;
2180 case MSR_IA32_LASTINTFROMIP:
2181 *data = svm->vmcb->save.last_excp_from;
2182 break;
2183 case MSR_IA32_LASTINTTOIP:
2184 *data = svm->vmcb->save.last_excp_to;
2185 break;
b286d5d8 2186 case MSR_VM_HSAVE_PA:
e6aa9abd 2187 *data = svm->nested.hsave_msr;
b286d5d8 2188 break;
eb6f302e
JR		 2189 case MSR_VM_CR:
2190 *data = 0;
2191 break;
c8a73f18
AG		 2192 case MSR_IA32_UCODE_REV:
2193 *data = 0x01000065;
2194 break;
6aa8b732 2195 default:
3bab1f5d 2196 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2197 }
2198 return 0;
2199}
2200
851ba692 2201static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2202{
ad312c7c 2203 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2204 u64 data;
2205
59200273
AK		 2206 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2207 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2208 kvm_inject_gp(&svm->vcpu, 0);
59200273 2209 } else {
229456fc 2210 trace_kvm_msr_read(ecx, data);
af9ca2d7 2211
5fdbf976 2212 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2213 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2214 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2215 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2216 }
2217 return 1;
2218}
2219
2220static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2221{
a2fa3e9f
GH		 2222 struct vcpu_svm *svm = to_svm(vcpu);
2223
6aa8b732 2224 switch (ecx) {
af24a4e4 2225 case MSR_IA32_TSC: {
20824f30
JR		 2226 u64 tsc_offset = data - native_read_tsc();
2227 u64 g_tsc_offset = 0;
2228
2229 if (is_nested(svm)) {
2230 g_tsc_offset = svm->vmcb->control.tsc_offset -
2231 svm->nested.hsave->control.tsc_offset;
2232 svm->nested.hsave->control.tsc_offset = tsc_offset;
2233 }
2234
2235 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2236
6aa8b732
AK		 2237 break;
2238 }
0e859cac 2239 case MSR_K6_STAR:
a2fa3e9f 2240 svm->vmcb->save.star = data;
6aa8b732 2241 break;
49b14f24 2242#ifdef CONFIG_X86_64
6aa8b732 2243 case MSR_LSTAR:
a2fa3e9f 2244 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2245 break;
2246 case MSR_CSTAR:
a2fa3e9f 2247 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2248 break;
2249 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2250 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2251 break;
2252 case MSR_SYSCALL_MASK:
a2fa3e9f 2253 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2254 break;
2255#endif
2256 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2257 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2258 break;
2259 case MSR_IA32_SYSENTER_EIP:
017cb99e 2260 svm->sysenter_eip = data;
a2fa3e9f 2261 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2262 break;
2263 case MSR_IA32_SYSENTER_ESP:
017cb99e 2264 svm->sysenter_esp = data;
a2fa3e9f 2265 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2266 break;
a2938c80 2267 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2268 if (!svm_has(SVM_FEATURE_LBRV)) {
2269 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2270 __func__, data);
24e09cbf
JR		 2271 break;
2272 }
2273 if (data & DEBUGCTL_RESERVED_BITS)
2274 return 1;
2275
2276 svm->vmcb->save.dbgctl = data;
2277 if (data & (1ULL<<0))
2278 svm_enable_lbrv(svm);
2279 else
2280 svm_disable_lbrv(svm);
a2938c80 2281 break;
b286d5d8 2282 case MSR_VM_HSAVE_PA:
e6aa9abd 2283 svm->nested.hsave_msr = data;
62b9abaa 2284 break;
3c5d0a44
AG		 2285 case MSR_VM_CR:
2286 case MSR_VM_IGNNE:
3c5d0a44
AG		 2287 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2288 break;
6aa8b732 2289 default:
3bab1f5d 2290 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2291 }
2292 return 0;
2293}
2294
851ba692 2295static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2296{
ad312c7c 2297 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2298 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2299 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2300
af9ca2d7 2301
5fdbf976 2302 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2303 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2304 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2305 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2306 } else {
2307 trace_kvm_msr_write(ecx, data);
e756fc62 2308 skip_emulated_instruction(&svm->vcpu);
59200273 2309 }
6aa8b732
AK		 2310 return 1;
2311}
2312
851ba692 2313static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2314{
e756fc62 2315 if (svm->vmcb->control.exit_info_1)
851ba692 2316 return wrmsr_interception(svm);
6aa8b732 2317 else
851ba692 2318 return rdmsr_interception(svm);
6aa8b732
AK		 2319}
2320
851ba692 2321static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2322{
851ba692
AK		 2323 struct kvm_run *kvm_run = svm->vcpu.run;
2324
f0b85051 2325 svm_clear_vintr(svm);
85f455f7 2326 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2327 /*
2328 * If the user space waits to inject interrupts, exit as soon as
2329 * possible
2330 */
8061823a
GN		 2331 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2332 kvm_run->request_interrupt_window &&
2333 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2334 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2335 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2336 return 0;
2337 }
2338
2339 return 1;
2340}
2341
565d0998
ML		 2342static int pause_interception(struct vcpu_svm *svm)
2343{
2344 kvm_vcpu_on_spin(&(svm->vcpu));
2345 return 1;
2346}
2347
851ba692 2348static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2349 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2350 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2351 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2352 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2353 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
6aa8b732
AK		 2354 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2355 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2356 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2357 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2358 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2359 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2360 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2361 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2362 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2363 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2364 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2365 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2366 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2367 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2368 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2369 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2370 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2371 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2372 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2373 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2374 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2375 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2376 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2377 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2378 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2379 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2380 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2381 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2382 [SVM_EXIT_SMI] = nop_on_interception,
2383 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2384 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2385 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2386 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2387 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2388 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2389 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2390 [SVM_EXIT_HLT] = halt_interception,
a7052897 2391 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2392 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2393 [SVM_EXIT_IOIO] = io_interception,
2394 [SVM_EXIT_MSR] = msr_interception,
2395 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2396 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2397 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2398 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2399 [SVM_EXIT_VMLOAD] = vmload_interception,
2400 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2401 [SVM_EXIT_STGI] = stgi_interception,
2402 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2403 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2404 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2405 [SVM_EXIT_MONITOR] = invalid_op_interception,
2406 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2407 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2408};
2409
851ba692 2410static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2411{
04d2cc77 2412 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2413 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2414 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2415
229456fc 2416 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2417
cd3ff653
JR		 2418 if (unlikely(svm->nested.exit_required)) {
2419 nested_svm_vmexit(svm);
2420 svm->nested.exit_required = false;
2421
2422 return 1;
2423 }
2424
cf74a78b 2425 if (is_nested(svm)) {
410e4d57
JR		 2426 int vmexit;
2427
d8cabddf
JR		 2428 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2429 svm->vmcb->control.exit_info_1,
2430 svm->vmcb->control.exit_info_2,
2431 svm->vmcb->control.exit_int_info,
2432 svm->vmcb->control.exit_int_info_err);
2433
410e4d57
JR		 2434 vmexit = nested_svm_exit_special(svm);
2435
2436 if (vmexit == NESTED_EXIT_CONTINUE)
2437 vmexit = nested_svm_exit_handled(svm);
2438
2439 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2440 return 1;
cf74a78b
AG		 2441 }
2442
a5c3832d
JR		 2443 svm_complete_interrupts(svm);
2444
888f9f3e 2445 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2446 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2447 if (npt_enabled)
709ddebf 2448 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2449
2450 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2451 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2452 kvm_run->fail_entry.hardware_entry_failure_reason
2453 = svm->vmcb->control.exit_code;
2454 return 0;
2455 }
2456
a2fa3e9f 2457 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2458 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2459 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2460 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2461 "exit_code 0x%x\n",
b8688d51 2462 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2463 exit_code);
2464
9d8f549d 2465 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2466 || !svm_exit_handlers[exit_code]) {
6aa8b732 2467 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2468 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2469 return 0;
2470 }
2471
851ba692 2472 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2473}
2474
2475static void reload_tss(struct kvm_vcpu *vcpu)
2476{
2477 int cpu = raw_smp_processor_id();
2478
0fe1e009
TH		 2479 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2480 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2481 load_TR_desc();
2482}
2483
e756fc62 2484static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2485{
2486 int cpu = raw_smp_processor_id();
2487
0fe1e009 2488 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2489
a2fa3e9f 2490 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2491 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2492 if (svm->asid_generation != sd->asid_generation)
2493 new_asid(svm, sd);
6aa8b732
AK		 2494}
2495
95ba8273
GN		 2496static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2497{
2498 struct vcpu_svm *svm = to_svm(vcpu);
2499
2500 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2501 vcpu->arch.hflags |= HF_NMI_MASK;
2502 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2503 ++vcpu->stat.nmi_injections;
2504}
6aa8b732 2505
85f455f7 2506static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2507{
2508 struct vmcb_control_area *control;
2509
229456fc 2510 trace_kvm_inj_virq(irq);
af9ca2d7 2511
fa89a817 2512 ++svm->vcpu.stat.irq_injections;
e756fc62 2513 control = &svm->vmcb->control;
85f455f7 2514 control->int_vector = irq;
6aa8b732
AK		 2515 control->int_ctl &= ~V_INTR_PRIO_MASK;
2516 control->int_ctl |= V_IRQ_MASK |
2517 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2518}
2519
66fd3f7f 2520static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2521{
2522 struct vcpu_svm *svm = to_svm(vcpu);
2523
2af9194d 2524 BUG_ON(!(gif_set(svm)));
cf74a78b 2525
219b65dc
AG		 2526 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2527 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2528}
2529
95ba8273 2530static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2531{
2532 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2533
95ba8273 2534 if (irr == -1)
aaacfc9a
JR		 2535 return;
2536
95ba8273
GN		 2537 if (tpr >= irr)
2538 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2539}
aaacfc9a 2540
95ba8273
GN		 2541static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2542{
2543 struct vcpu_svm *svm = to_svm(vcpu);
2544 struct vmcb *vmcb = svm->vmcb;
2545 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2546 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2547}
2548
3cfc3092
JK		 2549static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2550{
2551 struct vcpu_svm *svm = to_svm(vcpu);
2552
2553 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2554}
2555
2556static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2557{
2558 struct vcpu_svm *svm = to_svm(vcpu);
2559
2560 if (masked) {
2561 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2562 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2563 } else {
2564 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2565 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2566 }
2567}
2568
78646121
GN		 2569static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2570{
2571 struct vcpu_svm *svm = to_svm(vcpu);
2572 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2573 int ret;
2574
2575 if (!gif_set(svm) ||
2576 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2577 return 0;
2578
2579 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2580
2581 if (is_nested(svm))
2582 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2583
2584 return ret;
78646121
GN		 2585}
2586
9222be18 2587static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2588{
219b65dc 2589 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc
AG		 2590
2591 nested_svm_intr(svm);
2592
2593 /* In case GIF=0 we can't rely on the CPU to tell us when
2594 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2595 * The next time we get that intercept, this function will be
2596 * called again though and we'll get the vintr intercept. */
2af9194d 2597 if (gif_set(svm)) {
219b65dc
AG		 2598 svm_set_vintr(svm);
2599 svm_inject_irq(svm, 0x0);
2600 }
85f455f7
ED		 2601}
2602
95ba8273 2603static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2604{
04d2cc77 2605 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2606
44c11430
GN		 2607 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2608 == HF_NMI_MASK)
2609 return; /* IRET will cause a vm exit */
2610
2611 /* Something prevents NMI from been injected. Single step over
2612 possible problem (IRET or exception injection or interrupt
2613 shadow) */
6be7d306 2614 svm->nmi_singlestep = true;
44c11430
GN		 2615 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2616 update_db_intercept(vcpu);
c1150d8c
DL		 2617}
2618
cbc94022
IE		 2619static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2620{
2621 return 0;
2622}
2623
d9e368d6
AK		 2624static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2625{
2626 force_new_asid(vcpu);
2627}
2628
04d2cc77
AK		 2629static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2630{
2631}
2632
d7bf8221
JR		 2633static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2634{
2635 struct vcpu_svm *svm = to_svm(vcpu);
2636
2637 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2638 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2639 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2640 }
2641}
2642
649d6864
JR		 2643static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2644{
2645 struct vcpu_svm *svm = to_svm(vcpu);
2646 u64 cr8;
2647
649d6864
JR		 2648 cr8 = kvm_get_cr8(vcpu);
2649 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2650 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2651}
2652
9222be18
GN		 2653static void svm_complete_interrupts(struct vcpu_svm *svm)
2654{
2655 u8 vector;
2656 int type;
2657 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2658
44c11430
GN		 2659 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2660 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2661
9222be18
GN		 2662 svm->vcpu.arch.nmi_injected = false;
2663 kvm_clear_exception_queue(&svm->vcpu);
2664 kvm_clear_interrupt_queue(&svm->vcpu);
2665
2666 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2667 return;
2668
2669 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2670 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2671
2672 switch (type) {
2673 case SVM_EXITINTINFO_TYPE_NMI:
2674 svm->vcpu.arch.nmi_injected = true;
2675 break;
2676 case SVM_EXITINTINFO_TYPE_EXEPT:
2677 /* In case of software exception do not reinject an exception
2678 vector, but re-execute and instruction instead */
219b65dc
AG		 2679 if (is_nested(svm))
2680 break;
66fd3f7f 2681 if (kvm_exception_is_soft(vector))
9222be18
GN		 2682 break;
2683 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2684 u32 err = svm->vmcb->control.exit_int_info_err;
2685 kvm_queue_exception_e(&svm->vcpu, vector, err);
2686
2687 } else
2688 kvm_queue_exception(&svm->vcpu, vector);
2689 break;
2690 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2691 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2692 break;
2693 default:
2694 break;
2695 }
2696}
2697
80e31d4f
AK		 2698#ifdef CONFIG_X86_64
2699#define R "r"
2700#else
2701#define R "e"
2702#endif
2703
851ba692 2704static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2705{
a2fa3e9f 2706 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2707 u16 fs_selector;
2708 u16 gs_selector;
2709 u16 ldt_selector;
d9e368d6 2710
cd3ff653
JR		 2711 /*
2712 * A vmexit emulation is required before the vcpu can be executed
2713 * again.
2714 */
2715 if (unlikely(svm->nested.exit_required))
2716 return;
2717
5fdbf976
MT		 2718 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2719 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2720 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2721
e756fc62 2722 pre_svm_run(svm);
6aa8b732 2723
649d6864
JR		 2724 sync_lapic_to_cr8(vcpu);
2725
6aa8b732 2726 save_host_msrs(vcpu);
d6e88aec
AK		 2727 fs_selector = kvm_read_fs();
2728 gs_selector = kvm_read_gs();
2729 ldt_selector = kvm_read_ldt();
cda0ffdd 2730 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2731 /* required for live migration with NPT */
2732 if (npt_enabled)
2733 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2734
04d2cc77
AK		 2735 clgi();
2736
2737 local_irq_enable();
36241b8c 2738
6aa8b732 2739 asm volatile (
80e31d4f
AK		 2740 "push %%"R"bp; \n\t"
2741 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2742 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2743 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2744 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2745 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2746 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2747#ifdef CONFIG_X86_64
fb3f0f51
RR		 2748 "mov %c[r8](%[svm]), %%r8 \n\t"
2749 "mov %c[r9](%[svm]), %%r9 \n\t"
2750 "mov %c[r10](%[svm]), %%r10 \n\t"
2751 "mov %c[r11](%[svm]), %%r11 \n\t"
2752 "mov %c[r12](%[svm]), %%r12 \n\t"
2753 "mov %c[r13](%[svm]), %%r13 \n\t"
2754 "mov %c[r14](%[svm]), %%r14 \n\t"
2755 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2756#endif
2757
6aa8b732 2758 /* Enter guest mode */
80e31d4f
AK		 2759 "push %%"R"ax \n\t"
2760 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2761 __ex(SVM_VMLOAD) "\n\t"
2762 __ex(SVM_VMRUN) "\n\t"
2763 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2764 "pop %%"R"ax \n\t"
6aa8b732
AK		 2765
2766 /* Save guest registers, load host registers */
80e31d4f
AK		 2767 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2768 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2769 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2770 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2771 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2772 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2773#ifdef CONFIG_X86_64
fb3f0f51
RR		 2774 "mov %%r8, %c[r8](%[svm]) \n\t"
2775 "mov %%r9, %c[r9](%[svm]) \n\t"
2776 "mov %%r10, %c[r10](%[svm]) \n\t"
2777 "mov %%r11, %c[r11](%[svm]) \n\t"
2778 "mov %%r12, %c[r12](%[svm]) \n\t"
2779 "mov %%r13, %c[r13](%[svm]) \n\t"
2780 "mov %%r14, %c[r14](%[svm]) \n\t"
2781 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2782#endif
80e31d4f 2783 "pop %%"R"bp"
6aa8b732 2784 :
fb3f0f51 2785 : [svm]"a"(svm),
6aa8b732 2786 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2787 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2788 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2789 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2790 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2791 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2792 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2793#ifdef CONFIG_X86_64
ad312c7c
ZX		 2794 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2795 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2796 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2797 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2798 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2799 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2800 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2801 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2802#endif
54a08c04 2803 : "cc", "memory"
80e31d4f 2804 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2805#ifdef CONFIG_X86_64
54a08c04
LV		 2806 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2807#endif
2808 );
6aa8b732 2809
ad312c7c 2810 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2811 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2812 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2813 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2814
d6e88aec
AK		 2815 kvm_load_fs(fs_selector);
2816 kvm_load_gs(gs_selector);
2817 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2818 load_host_msrs(vcpu);
2819
2820 reload_tss(vcpu);
2821
56ba47dd
AK		 2822 local_irq_disable();
2823
2824 stgi();
2825
d7bf8221
JR		 2826 sync_cr8_to_lapic(vcpu);
2827
a2fa3e9f 2828 svm->next_rip = 0;
9222be18 2829
6de4f3ad
AK		 2830 if (npt_enabled) {
2831 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2832 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2833 }
6aa8b732
AK		 2834}
2835
80e31d4f
AK		 2836#undef R
2837
6aa8b732
AK		 2838static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2839{
a2fa3e9f
GH		 2840 struct vcpu_svm *svm = to_svm(vcpu);
2841
709ddebf
JR		 2842 if (npt_enabled) {
2843 svm->vmcb->control.nested_cr3 = root;
2844 force_new_asid(vcpu);
2845 return;
2846 }
2847
a2fa3e9f 2848 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2849 force_new_asid(vcpu);
2850}
2851
6aa8b732
AK		 2852static int is_disabled(void)
2853{
6031a61c
JR		 2854 u64 vm_cr;
2855
2856 rdmsrl(MSR_VM_CR, vm_cr);
2857 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2858 return 1;
2859
6aa8b732
AK		 2860 return 0;
2861}
2862
102d8325
IM		 2863static void
2864svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2865{
2866 /*
2867 * Patch in the VMMCALL instruction:
2868 */
2869 hypercall[0] = 0x0f;
2870 hypercall[1] = 0x01;
2871 hypercall[2] = 0xd9;
102d8325
IM		 2872}
2873
002c7f7c
YS		 2874static void svm_check_processor_compat(void *rtn)
2875{
2876 *(int *)rtn = 0;
2877}
2878
774ead3a
AK		 2879static bool svm_cpu_has_accelerated_tpr(void)
2880{
2881 return false;
2882}
2883
67253af5
SY		 2884static int get_npt_level(void)
2885{
2886#ifdef CONFIG_X86_64
2887 return PT64_ROOT_LEVEL;
2888#else
2889 return PT32E_ROOT_LEVEL;
2890#endif
2891}
2892
4b12f0de 2893static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2894{
2895 return 0;
2896}
2897
0e851880
SY		 2898static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2899{
2900}
2901
229456fc
MT		 2902static const struct trace_print_flags svm_exit_reasons_str[] = {
2903 { SVM_EXIT_READ_CR0, "read_cr0" },
2904 { SVM_EXIT_READ_CR3, "read_cr3" },
2905 { SVM_EXIT_READ_CR4, "read_cr4" },
2906 { SVM_EXIT_READ_CR8, "read_cr8" },
2907 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2908 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2909 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2910 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2911 { SVM_EXIT_READ_DR0, "read_dr0" },
2912 { SVM_EXIT_READ_DR1, "read_dr1" },
2913 { SVM_EXIT_READ_DR2, "read_dr2" },
2914 { SVM_EXIT_READ_DR3, "read_dr3" },
2915 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2916 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2917 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2918 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2919 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2920 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2921 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2922 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2923 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2924 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2925 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2926 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2927 { SVM_EXIT_INTR, "interrupt" },
2928 { SVM_EXIT_NMI, "nmi" },
2929 { SVM_EXIT_SMI, "smi" },
2930 { SVM_EXIT_INIT, "init" },
2931 { SVM_EXIT_VINTR, "vintr" },
2932 { SVM_EXIT_CPUID, "cpuid" },
2933 { SVM_EXIT_INVD, "invd" },
2934 { SVM_EXIT_HLT, "hlt" },
2935 { SVM_EXIT_INVLPG, "invlpg" },
2936 { SVM_EXIT_INVLPGA, "invlpga" },
2937 { SVM_EXIT_IOIO, "io" },
2938 { SVM_EXIT_MSR, "msr" },
2939 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2940 { SVM_EXIT_SHUTDOWN, "shutdown" },
2941 { SVM_EXIT_VMRUN, "vmrun" },
2942 { SVM_EXIT_VMMCALL, "hypercall" },
2943 { SVM_EXIT_VMLOAD, "vmload" },
2944 { SVM_EXIT_VMSAVE, "vmsave" },
2945 { SVM_EXIT_STGI, "stgi" },
2946 { SVM_EXIT_CLGI, "clgi" },
2947 { SVM_EXIT_SKINIT, "skinit" },
2948 { SVM_EXIT_WBINVD, "wbinvd" },
2949 { SVM_EXIT_MONITOR, "monitor" },
2950 { SVM_EXIT_MWAIT, "mwait" },
2951 { SVM_EXIT_NPF, "npf" },
2952 { -1, NULL }
2953};
2954
17cc3935 2955static int svm_get_lpage_level(void)
344f414f 2956{
17cc3935 2957 return PT_PDPE_LEVEL;
344f414f
JR		 2958}
2959
4e47c7a6
SY		 2960static bool svm_rdtscp_supported(void)
2961{
2962 return false;
2963}
2964
02daab21
AK		 2965static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2966{
2967 struct vcpu_svm *svm = to_svm(vcpu);
2968
d225157b 2969 update_cr0_intercept(svm);
02daab21 2970 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
02daab21
AK		 2971}
2972
cbdd1bea 2973static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2974 .cpu_has_kvm_support = has_svm,
2975 .disabled_by_bios = is_disabled,
2976 .hardware_setup = svm_hardware_setup,
2977 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2978 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2979 .hardware_enable = svm_hardware_enable,
2980 .hardware_disable = svm_hardware_disable,
774ead3a 2981 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2982
2983 .vcpu_create = svm_create_vcpu,
2984 .vcpu_free = svm_free_vcpu,
04d2cc77 2985 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2986
04d2cc77 2987 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2988 .vcpu_load = svm_vcpu_load,
2989 .vcpu_put = svm_vcpu_put,
2990
2991 .set_guest_debug = svm_guest_debug,
2992 .get_msr = svm_get_msr,
2993 .set_msr = svm_set_msr,
2994 .get_segment_base = svm_get_segment_base,
2995 .get_segment = svm_get_segment,
2996 .set_segment = svm_set_segment,
2e4d2653 2997 .get_cpl = svm_get_cpl,
1747fb71 2998 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 2999 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3000 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3001 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3002 .set_cr3 = svm_set_cr3,
3003 .set_cr4 = svm_set_cr4,
3004 .set_efer = svm_set_efer,
3005 .get_idt = svm_get_idt,
3006 .set_idt = svm_set_idt,
3007 .get_gdt = svm_get_gdt,
3008 .set_gdt = svm_set_gdt,
3009 .get_dr = svm_get_dr,
3010 .set_dr = svm_set_dr,
6de4f3ad 3011 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3012 .get_rflags = svm_get_rflags,
3013 .set_rflags = svm_set_rflags,
6b52d186 3014 .fpu_activate = svm_fpu_activate,
02daab21 3015 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3016
6aa8b732 3017 .tlb_flush = svm_flush_tlb,
6aa8b732 3018
6aa8b732 3019 .run = svm_vcpu_run,
04d2cc77 3020 .handle_exit = handle_exit,
6aa8b732 3021 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3022 .set_interrupt_shadow = svm_set_interrupt_shadow,
3023 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3024 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3025 .set_irq = svm_set_irq,
95ba8273 3026 .set_nmi = svm_inject_nmi,
298101da 3027 .queue_exception = svm_queue_exception,
78646121 3028 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3029 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3030 .get_nmi_mask = svm_get_nmi_mask,
3031 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3032 .enable_nmi_window = enable_nmi_window,
3033 .enable_irq_window = enable_irq_window,
3034 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3035
3036 .set_tss_addr = svm_set_tss_addr,
67253af5 3037 .get_tdp_level = get_npt_level,
4b12f0de 3038 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3039
3040 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3041 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3042
3043 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3044
3045 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3046};
3047
3048static int __init svm_init(void)
3049{
cb498ea2 3050 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3051 THIS_MODULE);
6aa8b732
AK		 3052}
3053
3054static void __exit svm_exit(void)
3055{
cb498ea2 3056 kvm_exit();
6aa8b732
AK		 3057}
3058
3059module_init(svm_init)
3060module_exit(svm_exit)
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