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KVM: x86 emulator: during rep emulation decrement ECX only if emulation succeeded
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
66b7138f 50#define SVM_FEATURE_NRIP (1 << 3)
565d0998 51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
4a810181 74 u64 vm_cr_msr;
e6aa9abd
JR		 75 u64 vmcb;
76
77 /* These are the merged vectors */
78 u32 *msrpm;
79
80 /* gpa pointers to the real vectors */
81 u64 vmcb_msrpm;
ce2ac085 82 u64 vmcb_iopm;
aad42c64 83
cd3ff653
JR		 84 /* A VMEXIT is required but not yet emulated */
85 bool exit_required;
86
aad42c64
JR		 87 /* cache for intercepts of the guest */
88 u16 intercept_cr_read;
89 u16 intercept_cr_write;
90 u16 intercept_dr_read;
91 u16 intercept_dr_write;
92 u32 intercept_exceptions;
93 u64 intercept;
94
e6aa9abd
JR		 95};
96
323c3d80
JR		 97#define MSRPM_OFFSETS 16
98static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
99
6c8166a7
AK		 100struct vcpu_svm {
101 struct kvm_vcpu vcpu;
102 struct vmcb *vmcb;
103 unsigned long vmcb_pa;
104 struct svm_cpu_data *svm_data;
105 uint64_t asid_generation;
106 uint64_t sysenter_esp;
107 uint64_t sysenter_eip;
108
109 u64 next_rip;
110
111 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
112 u64 host_gs_base;
6c8166a7
AK		 113
114 u32 *msrpm;
6c8166a7 115
e6aa9abd 116 struct nested_state nested;
6be7d306
JK		 117
118 bool nmi_singlestep;
66b7138f
JK		 119
120 unsigned int3_injected;
121 unsigned long int3_rip;
6c8166a7
AK		 122};
123
455716fa
JR		 124#define MSR_INVALID 0xffffffffU
125
ac72a9b7
JR		 126static struct svm_direct_access_msrs {
127 u32 index; /* Index of the MSR */
128 bool always; /* True if intercept is always on */
129} direct_access_msrs[] = {
130 { .index = MSR_K6_STAR, .always = true },
131 { .index = MSR_IA32_SYSENTER_CS, .always = true },
132#ifdef CONFIG_X86_64
133 { .index = MSR_GS_BASE, .always = true },
134 { .index = MSR_FS_BASE, .always = true },
135 { .index = MSR_KERNEL_GS_BASE, .always = true },
136 { .index = MSR_LSTAR, .always = true },
137 { .index = MSR_CSTAR, .always = true },
138 { .index = MSR_SYSCALL_MASK, .always = true },
139#endif
140 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
141 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
142 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
143 { .index = MSR_IA32_LASTINTTOIP, .always = false },
144 { .index = MSR_INVALID, .always = false },
145};
146
709ddebf
JR		 147/* enable NPT for AMD64 and X86 with PAE */
148#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
149static bool npt_enabled = true;
150#else
e0231715 151static bool npt_enabled;
709ddebf 152#endif
6c7dac72
JR		 153static int npt = 1;
154
155module_param(npt, int, S_IRUGO);
e3da3acd 156
4b6e4dca 157static int nested = 1;
236de055
AG		 158module_param(nested, int, S_IRUGO);
159
44874f84 160static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 161static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 162
410e4d57 163static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 164static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 165static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 166static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
167 bool has_error_code, u32 error_code);
168
a2fa3e9f
GH		 169static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
170{
fb3f0f51 171 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 172}
173
3d6368ef
AG		 174static inline bool is_nested(struct vcpu_svm *svm)
175{
e6aa9abd 176 return svm->nested.vmcb;
3d6368ef
AG		 177}
178
2af9194d
JR		 179static inline void enable_gif(struct vcpu_svm *svm)
180{
181 svm->vcpu.arch.hflags |= HF_GIF_MASK;
182}
183
184static inline void disable_gif(struct vcpu_svm *svm)
185{
186 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
187}
188
189static inline bool gif_set(struct vcpu_svm *svm)
190{
191 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
192}
193
4866d5e3 194static unsigned long iopm_base;
6aa8b732
AK		 195
196struct kvm_ldttss_desc {
197 u16 limit0;
198 u16 base0;
e0231715
JR		 199 unsigned base1:8, type:5, dpl:2, p:1;
200 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 201 u32 base3;
202 u32 zero1;
203} __attribute__((packed));
204
205struct svm_cpu_data {
206 int cpu;
207
5008fdf5
AK		 208 u64 asid_generation;
209 u32 max_asid;
210 u32 next_asid;
6aa8b732
AK		 211 struct kvm_ldttss_desc *tss_desc;
212
213 struct page *save_area;
214};
215
216static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 217static uint32_t svm_features;
6aa8b732
AK		 218
219struct svm_init_data {
220 int cpu;
221 int r;
222};
223
224static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
225
9d8f549d 226#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 227#define MSRS_RANGE_SIZE 2048
228#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
229
455716fa
JR		 230static u32 svm_msrpm_offset(u32 msr)
231{
232 u32 offset;
233 int i;
234
235 for (i = 0; i < NUM_MSR_MAPS; i++) {
236 if (msr < msrpm_ranges[i] ||
237 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
238 continue;
239
240 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
241 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
242
243 /* Now we have the u8 offset - but need the u32 offset */
244 return offset / 4;
245 }
246
247 /* MSR not in any range */
248 return MSR_INVALID;
249}
250
6aa8b732
AK		 251#define MAX_INST_SIZE 15
252
80b7706e
JR		 253static inline u32 svm_has(u32 feat)
254{
255 return svm_features & feat;
256}
257
6aa8b732
AK		 258static inline void clgi(void)
259{
4ecac3fd 260 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 261}
262
263static inline void stgi(void)
264{
4ecac3fd 265 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 266}
267
268static inline void invlpga(unsigned long addr, u32 asid)
269{
e0231715 270 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 271}
272
6aa8b732
AK		 273static inline void force_new_asid(struct kvm_vcpu *vcpu)
274{
a2fa3e9f 275 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 276}
277
278static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
279{
280 force_new_asid(vcpu);
281}
282
283static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
284{
709ddebf 285 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 286 efer &= ~EFER_LME;
6aa8b732 287
9962d032 288 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 289 vcpu->arch.efer = efer;
6aa8b732
AK		 290}
291
6aa8b732
AK		 292static int is_external_interrupt(u32 info)
293{
294 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
295 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
296}
297
2809f5d2
GC		 298static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
299{
300 struct vcpu_svm *svm = to_svm(vcpu);
301 u32 ret = 0;
302
303 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 304 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 305 return ret & mask;
306}
307
308static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
309{
310 struct vcpu_svm *svm = to_svm(vcpu);
311
312 if (mask == 0)
313 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
314 else
315 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
316
317}
318
6aa8b732
AK		 319static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
320{
a2fa3e9f
GH		 321 struct vcpu_svm *svm = to_svm(vcpu);
322
323 if (!svm->next_rip) {
851ba692 324 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 325 EMULATE_DONE)
326 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 327 return;
328 }
5fdbf976
MT		 329 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
330 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
331 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 332
5fdbf976 333 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 334 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 335}
336
116a4752
JK		 337static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
338 bool has_error_code, u32 error_code)
339{
340 struct vcpu_svm *svm = to_svm(vcpu);
341
e0231715
JR		 342 /*
343 * If we are within a nested VM we'd better #VMEXIT and let the guest
344 * handle the exception
345 */
116a4752
JK		 346 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
347 return;
348
66b7138f
JK		 349 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
350 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
351
352 /*
353 * For guest debugging where we have to reinject #BP if some
354 * INT3 is guest-owned:
355 * Emulate nRIP by moving RIP forward. Will fail if injection
356 * raises a fault that is not intercepted. Still better than
357 * failing in all cases.
358 */
359 skip_emulated_instruction(&svm->vcpu);
360 rip = kvm_rip_read(&svm->vcpu);
361 svm->int3_rip = rip + svm->vmcb->save.cs.base;
362 svm->int3_injected = rip - old_rip;
363 }
364
116a4752
JK		 365 svm->vmcb->control.event_inj = nr
366 | SVM_EVTINJ_VALID
367 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
368 | SVM_EVTINJ_TYPE_EXEPT;
369 svm->vmcb->control.event_inj_err = error_code;
370}
371
6aa8b732
AK		 372static int has_svm(void)
373{
63d1142f 374 const char *msg;
6aa8b732 375
63d1142f 376 if (!cpu_has_svm(&msg)) {
ff81ff10 377 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 378 return 0;
379 }
380
6aa8b732
AK		 381 return 1;
382}
383
384static void svm_hardware_disable(void *garbage)
385{
2c8dceeb 386 cpu_svm_disable();
6aa8b732
AK		 387}
388
10474ae8 389static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 390{
391
0fe1e009 392 struct svm_cpu_data *sd;
6aa8b732 393 uint64_t efer;
89a27f4d 394 struct desc_ptr gdt_descr;
6aa8b732
AK		 395 struct desc_struct *gdt;
396 int me = raw_smp_processor_id();
397
10474ae8
AG		 398 rdmsrl(MSR_EFER, efer);
399 if (efer & EFER_SVME)
400 return -EBUSY;
401
6aa8b732 402 if (!has_svm()) {
e6732a5a
ZA		 403 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
404 me);
10474ae8 405 return -EINVAL;
6aa8b732 406 }
0fe1e009 407 sd = per_cpu(svm_data, me);
6aa8b732 408
0fe1e009 409 if (!sd) {
e6732a5a 410 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 411 me);
10474ae8 412 return -EINVAL;
6aa8b732
AK		 413 }
414
0fe1e009
TH		 415 sd->asid_generation = 1;
416 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
417 sd->next_asid = sd->max_asid + 1;
6aa8b732 418
d6ab1ed4 419 native_store_gdt(&gdt_descr);
89a27f4d 420 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 421 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 422
9962d032 423 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 424
d0316554 425 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 426
427 return 0;
6aa8b732
AK		 428}
429
0da1db75
JR		 430static void svm_cpu_uninit(int cpu)
431{
0fe1e009 432 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 433
0fe1e009 434 if (!sd)
0da1db75
JR		 435 return;
436
437 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 438 __free_page(sd->save_area);
439 kfree(sd);
0da1db75
JR		 440}
441
6aa8b732
AK		 442static int svm_cpu_init(int cpu)
443{
0fe1e009 444 struct svm_cpu_data *sd;
6aa8b732
AK		 445 int r;
446
0fe1e009
TH		 447 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
448 if (!sd)
6aa8b732 449 return -ENOMEM;
0fe1e009
TH		 450 sd->cpu = cpu;
451 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 452 r = -ENOMEM;
0fe1e009 453 if (!sd->save_area)
6aa8b732
AK		 454 goto err_1;
455
0fe1e009 456 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 457
458 return 0;
459
460err_1:
0fe1e009 461 kfree(sd);
6aa8b732
AK		 462 return r;
463
464}
465
ac72a9b7
JR		 466static bool valid_msr_intercept(u32 index)
467{
468 int i;
469
470 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
471 if (direct_access_msrs[i].index == index)
472 return true;
473
474 return false;
475}
476
bfc733a7
RR		 477static void set_msr_interception(u32 *msrpm, unsigned msr,
478 int read, int write)
6aa8b732 479{
455716fa
JR		 480 u8 bit_read, bit_write;
481 unsigned long tmp;
482 u32 offset;
6aa8b732 483
ac72a9b7
JR		 484 /*
485 * If this warning triggers extend the direct_access_msrs list at the
486 * beginning of the file
487 */
488 WARN_ON(!valid_msr_intercept(msr));
489
455716fa
JR		 490 offset = svm_msrpm_offset(msr);
491 bit_read = 2 * (msr & 0x0f);
492 bit_write = 2 * (msr & 0x0f) + 1;
493 tmp = msrpm[offset];
494
495 BUG_ON(offset == MSR_INVALID);
496
497 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
498 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
499
500 msrpm[offset] = tmp;
6aa8b732
AK		 501}
502
f65c229c
JR		 503static void svm_vcpu_init_msrpm(u32 *msrpm)
504{
ac72a9b7
JR		 505 int i;
506
f65c229c
JR		 507 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
508
ac72a9b7
JR		 509 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
510 if (!direct_access_msrs[i].always)
511 continue;
512
513 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
514 }
f65c229c
JR		 515}
516
323c3d80
JR		 517static void add_msr_offset(u32 offset)
518{
519 int i;
520
521 for (i = 0; i < MSRPM_OFFSETS; ++i) {
522
523 /* Offset already in list? */
524 if (msrpm_offsets[i] == offset)
525 return;
526
527 /* Slot used by another offset? */
528 if (msrpm_offsets[i] != MSR_INVALID)
529 continue;
530
531 /* Add offset to list */
532 msrpm_offsets[i] = offset;
533
534 return;
535 }
536
537 /*
538 * If this BUG triggers the msrpm_offsets table has an overflow. Just
539 * increase MSRPM_OFFSETS in this case.
540 */
541 BUG();
542}
543
544static void init_msrpm_offsets(void)
545{
546 int i;
547
548 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
549
550 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
551 u32 offset;
552
553 offset = svm_msrpm_offset(direct_access_msrs[i].index);
554 BUG_ON(offset == MSR_INVALID);
555
556 add_msr_offset(offset);
557 }
558}
559
24e09cbf
JR		 560static void svm_enable_lbrv(struct vcpu_svm *svm)
561{
562 u32 *msrpm = svm->msrpm;
563
564 svm->vmcb->control.lbr_ctl = 1;
565 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
566 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
567 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
568 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
569}
570
571static void svm_disable_lbrv(struct vcpu_svm *svm)
572{
573 u32 *msrpm = svm->msrpm;
574
575 svm->vmcb->control.lbr_ctl = 0;
576 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
577 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
578 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
579 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
580}
581
6aa8b732
AK		 582static __init int svm_hardware_setup(void)
583{
584 int cpu;
585 struct page *iopm_pages;
f65c229c 586 void *iopm_va;
6aa8b732
AK		 587 int r;
588
6aa8b732
AK		 589 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
590
591 if (!iopm_pages)
592 return -ENOMEM;
c8681339
AL		 593
594 iopm_va = page_address(iopm_pages);
595 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 596 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
597
323c3d80
JR		 598 init_msrpm_offsets();
599
50a37eb4
JR		 600 if (boot_cpu_has(X86_FEATURE_NX))
601 kvm_enable_efer_bits(EFER_NX);
602
1b2fd70c
AG		 603 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
604 kvm_enable_efer_bits(EFER_FFXSR);
605
236de055
AG		 606 if (nested) {
607 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
608 kvm_enable_efer_bits(EFER_SVME);
609 }
610
3230bb47 611 for_each_possible_cpu(cpu) {
6aa8b732
AK		 612 r = svm_cpu_init(cpu);
613 if (r)
f65c229c 614 goto err;
6aa8b732 615 }
33bd6a0b
JR		 616
617 svm_features = cpuid_edx(SVM_CPUID_FUNC);
618
e3da3acd
JR		 619 if (!svm_has(SVM_FEATURE_NPT))
620 npt_enabled = false;
621
6c7dac72
JR		 622 if (npt_enabled && !npt) {
623 printk(KERN_INFO "kvm: Nested Paging disabled\n");
624 npt_enabled = false;
625 }
626
18552672 627 if (npt_enabled) {
e3da3acd 628 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 629 kvm_enable_tdp();
5f4cb662
JR		 630 } else
631 kvm_disable_tdp();
e3da3acd 632
6aa8b732
AK		 633 return 0;
634
f65c229c 635err:
6aa8b732
AK		 636 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
637 iopm_base = 0;
638 return r;
639}
640
641static __exit void svm_hardware_unsetup(void)
642{
0da1db75
JR		 643 int cpu;
644
3230bb47 645 for_each_possible_cpu(cpu)
0da1db75
JR		 646 svm_cpu_uninit(cpu);
647
6aa8b732 648 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 649 iopm_base = 0;
6aa8b732
AK		 650}
651
652static void init_seg(struct vmcb_seg *seg)
653{
654 seg->selector = 0;
655 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 656 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 657 seg->limit = 0xffff;
658 seg->base = 0;
659}
660
661static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
662{
663 seg->selector = 0;
664 seg->attrib = SVM_SELECTOR_P_MASK | type;
665 seg->limit = 0xffff;
666 seg->base = 0;
667}
668
e6101a96 669static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 670{
e6101a96
JR		 671 struct vmcb_control_area *control = &svm->vmcb->control;
672 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 673
bff78274
AK		 674 svm->vcpu.fpu_active = 1;
675
e0231715 676 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 677 INTERCEPT_CR3_MASK |
649d6864 678 INTERCEPT_CR4_MASK;
6aa8b732 679
e0231715 680 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 681 INTERCEPT_CR3_MASK |
80a8119c
AK		 682 INTERCEPT_CR4_MASK |
683 INTERCEPT_CR8_MASK;
6aa8b732 684
e0231715 685 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 686 INTERCEPT_DR1_MASK |
687 INTERCEPT_DR2_MASK |
727f5a23
JK		 688 INTERCEPT_DR3_MASK |
689 INTERCEPT_DR4_MASK |
690 INTERCEPT_DR5_MASK |
691 INTERCEPT_DR6_MASK |
692 INTERCEPT_DR7_MASK;
6aa8b732 693
e0231715 694 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 695 INTERCEPT_DR1_MASK |
696 INTERCEPT_DR2_MASK |
697 INTERCEPT_DR3_MASK |
727f5a23 698 INTERCEPT_DR4_MASK |
6aa8b732 699 INTERCEPT_DR5_MASK |
727f5a23 700 INTERCEPT_DR6_MASK |
6aa8b732
AK		 701 INTERCEPT_DR7_MASK;
702
7aa81cc0 703 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 704 (1 << UD_VECTOR) |
705 (1 << MC_VECTOR);
6aa8b732
AK		 706
707
e0231715 708 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 709 (1ULL << INTERCEPT_NMI) |
0152527b 710 (1ULL << INTERCEPT_SMI) |
d225157b 711 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 712 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 713 (1ULL << INTERCEPT_INVD) |
6aa8b732 714 (1ULL << INTERCEPT_HLT) |
a7052897 715 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 716 (1ULL << INTERCEPT_INVLPGA) |
717 (1ULL << INTERCEPT_IOIO_PROT) |
718 (1ULL << INTERCEPT_MSR_PROT) |
719 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 720 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 721 (1ULL << INTERCEPT_VMRUN) |
722 (1ULL << INTERCEPT_VMMCALL) |
723 (1ULL << INTERCEPT_VMLOAD) |
724 (1ULL << INTERCEPT_VMSAVE) |
725 (1ULL << INTERCEPT_STGI) |
726 (1ULL << INTERCEPT_CLGI) |
916ce236 727 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 728 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 729 (1ULL << INTERCEPT_MONITOR) |
730 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 731
732 control->iopm_base_pa = iopm_base;
f65c229c 733 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 734 control->tsc_offset = 0;
6aa8b732
AK		 735 control->int_ctl = V_INTR_MASKING_MASK;
736
737 init_seg(&save->es);
738 init_seg(&save->ss);
739 init_seg(&save->ds);
740 init_seg(&save->fs);
741 init_seg(&save->gs);
742
743 save->cs.selector = 0xf000;
744 /* Executable/Readable Code Segment */
745 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
746 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
747 save->cs.limit = 0xffff;
d92899a0
AK		 748 /*
749 * cs.base should really be 0xffff0000, but vmx can't handle that, so
750 * be consistent with it.
751 *
752 * Replace when we have real mode working for vmx.
753 */
754 save->cs.base = 0xf0000;
6aa8b732
AK		 755
756 save->gdtr.limit = 0xffff;
757 save->idtr.limit = 0xffff;
758
759 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
760 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
761
9962d032 762 save->efer = EFER_SVME;
d77c26fc 763 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 764 save->dr7 = 0x400;
765 save->rflags = 2;
766 save->rip = 0x0000fff0;
5fdbf976 767 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 768
e0231715
JR		 769 /*
770 * This is the guest-visible cr0 value.
18fa000a 771 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 772 */
18fa000a
EH		 773 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
774 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
775
66aee91a 776 save->cr4 = X86_CR4_PAE;
6aa8b732 777 /* rdx = ?? */
709ddebf
JR		 778
779 if (npt_enabled) {
780 /* Setup VMCB for Nested Paging */
781 control->nested_ctl = 1;
a7052897
MT		 782 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
783 (1ULL << INTERCEPT_INVLPG));
709ddebf 784 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 785 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
786 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 787 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 788 save->cr3 = 0;
789 save->cr4 = 0;
790 }
a79d2f18 791 force_new_asid(&svm->vcpu);
1371d904 792
e6aa9abd 793 svm->nested.vmcb = 0;
2af9194d
JR		 794 svm->vcpu.arch.hflags = 0;
795
565d0998
ML		 796 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
797 control->pause_filter_count = 3000;
798 control->intercept |= (1ULL << INTERCEPT_PAUSE);
799 }
800
2af9194d 801 enable_gif(svm);
6aa8b732
AK		 802}
803
e00c8cf2 804static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 805{
806 struct vcpu_svm *svm = to_svm(vcpu);
807
e6101a96 808 init_vmcb(svm);
70433389 809
c5af89b6 810 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 811 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 812 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
813 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 814 }
5fdbf976
MT		 815 vcpu->arch.regs_avail = ~0;
816 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 817
818 return 0;
04d2cc77
AK		 819}
820
fb3f0f51 821static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 822{
a2fa3e9f 823 struct vcpu_svm *svm;
6aa8b732 824 struct page *page;
f65c229c 825 struct page *msrpm_pages;
b286d5d8 826 struct page *hsave_page;
3d6368ef 827 struct page *nested_msrpm_pages;
fb3f0f51 828 int err;
6aa8b732 829
c16f862d 830 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 831 if (!svm) {
832 err = -ENOMEM;
833 goto out;
834 }
835
836 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
837 if (err)
838 goto free_svm;
839
b7af4043 840 err = -ENOMEM;
6aa8b732 841 page = alloc_page(GFP_KERNEL);
b7af4043 842 if (!page)
fb3f0f51 843 goto uninit;
6aa8b732 844
f65c229c
JR		 845 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
846 if (!msrpm_pages)
b7af4043 847 goto free_page1;
3d6368ef
AG		 848
849 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
850 if (!nested_msrpm_pages)
b7af4043 851 goto free_page2;
f65c229c 852
b286d5d8
AG		 853 hsave_page = alloc_page(GFP_KERNEL);
854 if (!hsave_page)
b7af4043
TY		 855 goto free_page3;
856
e6aa9abd 857 svm->nested.hsave = page_address(hsave_page);
b286d5d8 858
b7af4043
TY		 859 svm->msrpm = page_address(msrpm_pages);
860 svm_vcpu_init_msrpm(svm->msrpm);
861
e6aa9abd 862 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 863 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 864
a2fa3e9f
GH		 865 svm->vmcb = page_address(page);
866 clear_page(svm->vmcb);
867 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
868 svm->asid_generation = 0;
e6101a96 869 init_vmcb(svm);
a2fa3e9f 870
fb3f0f51 871 fx_init(&svm->vcpu);
ad312c7c 872 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 873 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 874 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 875
fb3f0f51 876 return &svm->vcpu;
36241b8c 877
b7af4043
TY		 878free_page3:
879 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
880free_page2:
881 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
882free_page1:
883 __free_page(page);
fb3f0f51
RR		 884uninit:
885 kvm_vcpu_uninit(&svm->vcpu);
886free_svm:
a4770347 887 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 888out:
889 return ERR_PTR(err);
6aa8b732
AK		 890}
891
892static void svm_free_vcpu(struct kvm_vcpu *vcpu)
893{
a2fa3e9f
GH		 894 struct vcpu_svm *svm = to_svm(vcpu);
895
fb3f0f51 896 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 897 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 898 __free_page(virt_to_page(svm->nested.hsave));
899 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 900 kvm_vcpu_uninit(vcpu);
a4770347 901 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 902}
903
15ad7146 904static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 905{
a2fa3e9f 906 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 907 int i;
0cc5064d 908
0cc5064d 909 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 910 u64 delta;
0cc5064d 911
953899b6
JR		 912 if (check_tsc_unstable()) {
913 /*
914 * Make sure that the guest sees a monotonically
915 * increasing TSC.
916 */
917 delta = vcpu->arch.host_tsc - native_read_tsc();
918 svm->vmcb->control.tsc_offset += delta;
919 if (is_nested(svm))
920 svm->nested.hsave->control.tsc_offset += delta;
921 }
0cc5064d 922 vcpu->cpu = cpu;
2f599714 923 kvm_migrate_timers(vcpu);
4b656b12 924 svm->asid_generation = 0;
0cc5064d 925 }
94dfbdb3
AL		 926
927 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 928 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 929}
930
931static void svm_vcpu_put(struct kvm_vcpu *vcpu)
932{
a2fa3e9f 933 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 934 int i;
935
e1beb1d3 936 ++vcpu->stat.host_state_reload;
94dfbdb3 937 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 938 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 939
e935d48e 940 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 941}
942
6aa8b732
AK		 943static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
944{
a2fa3e9f 945 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 946}
947
948static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
949{
a2fa3e9f 950 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 951}
952
6de4f3ad
AK		 953static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
954{
955 switch (reg) {
956 case VCPU_EXREG_PDPTR:
957 BUG_ON(!npt_enabled);
958 load_pdptrs(vcpu, vcpu->arch.cr3);
959 break;
960 default:
961 BUG();
962 }
963}
964
f0b85051
AG		 965static void svm_set_vintr(struct vcpu_svm *svm)
966{
967 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
968}
969
970static void svm_clear_vintr(struct vcpu_svm *svm)
971{
972 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
973}
974
6aa8b732
AK		 975static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
976{
a2fa3e9f 977 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 978
979 switch (seg) {
980 case VCPU_SREG_CS: return &save->cs;
981 case VCPU_SREG_DS: return &save->ds;
982 case VCPU_SREG_ES: return &save->es;
983 case VCPU_SREG_FS: return &save->fs;
984 case VCPU_SREG_GS: return &save->gs;
985 case VCPU_SREG_SS: return &save->ss;
986 case VCPU_SREG_TR: return &save->tr;
987 case VCPU_SREG_LDTR: return &save->ldtr;
988 }
989 BUG();
8b6d44c7 990 return NULL;
6aa8b732
AK		 991}
992
993static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
994{
995 struct vmcb_seg *s = svm_seg(vcpu, seg);
996
997 return s->base;
998}
999
1000static void svm_get_segment(struct kvm_vcpu *vcpu,
1001 struct kvm_segment *var, int seg)
1002{
1003 struct vmcb_seg *s = svm_seg(vcpu, seg);
1004
1005 var->base = s->base;
1006 var->limit = s->limit;
1007 var->selector = s->selector;
1008 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1009 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1010 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1011 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1012 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1013 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1014 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1015 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1016
e0231715
JR		 1017 /*
1018 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1019 * for cross vendor migration purposes by "not present"
1020 */
1021 var->unusable = !var->present || (var->type == 0);
1022
1fbdc7a5
AP		 1023 switch (seg) {
1024 case VCPU_SREG_CS:
1025 /*
1026 * SVM always stores 0 for the 'G' bit in the CS selector in
1027 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1028 * Intel's VMENTRY has a check on the 'G' bit.
1029 */
25022acc 1030 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1031 break;
1032 case VCPU_SREG_TR:
1033 /*
1034 * Work around a bug where the busy flag in the tr selector
1035 * isn't exposed
1036 */
c0d09828 1037 var->type |= 0x2;
1fbdc7a5
AP		 1038 break;
1039 case VCPU_SREG_DS:
1040 case VCPU_SREG_ES:
1041 case VCPU_SREG_FS:
1042 case VCPU_SREG_GS:
1043 /*
1044 * The accessed bit must always be set in the segment
1045 * descriptor cache, although it can be cleared in the
1046 * descriptor, the cached bit always remains at 1. Since
1047 * Intel has a check on this, set it here to support
1048 * cross-vendor migration.
1049 */
1050 if (!var->unusable)
1051 var->type |= 0x1;
1052 break;
b586eb02 1053 case VCPU_SREG_SS:
e0231715
JR		 1054 /*
1055 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1056 * descriptor is left as 1, although the whole segment has
1057 * been made unusable. Clear it here to pass an Intel VMX
1058 * entry check when cross vendor migrating.
1059 */
1060 if (var->unusable)
1061 var->db = 0;
1062 break;
1fbdc7a5 1063 }
6aa8b732
AK		 1064}
1065
2e4d2653
IE		 1066static int svm_get_cpl(struct kvm_vcpu *vcpu)
1067{
1068 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1069
1070 return save->cpl;
1071}
1072
89a27f4d 1073static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1074{
a2fa3e9f
GH		 1075 struct vcpu_svm *svm = to_svm(vcpu);
1076
89a27f4d
GN		 1077 dt->size = svm->vmcb->save.idtr.limit;
1078 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1079}
1080
89a27f4d 1081static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1082{
a2fa3e9f
GH		 1083 struct vcpu_svm *svm = to_svm(vcpu);
1084
89a27f4d
GN		 1085 svm->vmcb->save.idtr.limit = dt->size;
1086 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1087}
1088
89a27f4d 1089static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1090{
a2fa3e9f
GH		 1091 struct vcpu_svm *svm = to_svm(vcpu);
1092
89a27f4d
GN		 1093 dt->size = svm->vmcb->save.gdtr.limit;
1094 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1095}
1096
89a27f4d 1097static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1098{
a2fa3e9f
GH		 1099 struct vcpu_svm *svm = to_svm(vcpu);
1100
89a27f4d
GN		 1101 svm->vmcb->save.gdtr.limit = dt->size;
1102 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1103}
1104
e8467fda
AK		 1105static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1106{
1107}
1108
25c4c276 1109static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1110{
1111}
1112
d225157b
AK		 1113static void update_cr0_intercept(struct vcpu_svm *svm)
1114{
66a562f7 1115 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1116 ulong gcr0 = svm->vcpu.arch.cr0;
1117 u64 *hcr0 = &svm->vmcb->save.cr0;
1118
1119 if (!svm->vcpu.fpu_active)
1120 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1121 else
1122 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1123 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1124
1125
1126 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1127 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1128 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1129 if (is_nested(svm)) {
1130 struct vmcb *hsave = svm->nested.hsave;
1131
1132 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1133 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1134 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1135 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1136 }
d225157b
AK		 1137 } else {
1138 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1139 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1140 if (is_nested(svm)) {
1141 struct vmcb *hsave = svm->nested.hsave;
1142
1143 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1144 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1145 }
d225157b
AK		 1146 }
1147}
1148
6aa8b732
AK		 1149static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1150{
a2fa3e9f
GH		 1151 struct vcpu_svm *svm = to_svm(vcpu);
1152
7f5d8b56
JR		 1153 if (is_nested(svm)) {
1154 /*
1155 * We are here because we run in nested mode, the host kvm
1156 * intercepts cr0 writes but the l1 hypervisor does not.
1157 * But the L1 hypervisor may intercept selective cr0 writes.
1158 * This needs to be checked here.
1159 */
1160 unsigned long old, new;
1161
1162 /* Remove bits that would trigger a real cr0 write intercept */
1163 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1164 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1165
1166 if (old == new) {
1167 /* cr0 write with ts and mp unchanged */
1168 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1169 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1170 return;
1171 }
1172 }
1173
05b3e0c2 1174#ifdef CONFIG_X86_64
f6801dff 1175 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1176 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1177 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1178 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1179 }
1180
d77c26fc 1181 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1182 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1183 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1184 }
1185 }
1186#endif
ad312c7c 1187 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1188
1189 if (!npt_enabled)
1190 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1191
1192 if (!vcpu->fpu_active)
334df50a 1193 cr0 |= X86_CR0_TS;
709ddebf
JR		 1194 /*
1195 * re-enable caching here because the QEMU bios
1196 * does not do it - this results in some delay at
1197 * reboot
1198 */
1199 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1200 svm->vmcb->save.cr0 = cr0;
d225157b 1201 update_cr0_intercept(svm);
6aa8b732
AK		 1202}
1203
1204static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1205{
6394b649 1206 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1207 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1208
1209 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1210 force_new_asid(vcpu);
6394b649 1211
ec077263
JR		 1212 vcpu->arch.cr4 = cr4;
1213 if (!npt_enabled)
1214 cr4 |= X86_CR4_PAE;
6394b649 1215 cr4 |= host_cr4_mce;
ec077263 1216 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1217}
1218
1219static void svm_set_segment(struct kvm_vcpu *vcpu,
1220 struct kvm_segment *var, int seg)
1221{
a2fa3e9f 1222 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1223 struct vmcb_seg *s = svm_seg(vcpu, seg);
1224
1225 s->base = var->base;
1226 s->limit = var->limit;
1227 s->selector = var->selector;
1228 if (var->unusable)
1229 s->attrib = 0;
1230 else {
1231 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1232 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1233 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1234 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1235 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1236 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1237 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1238 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1239 }
1240 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1241 svm->vmcb->save.cpl
1242 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1243 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1244
1245}
1246
44c11430 1247static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1248{
d0bfb940
JK		 1249 struct vcpu_svm *svm = to_svm(vcpu);
1250
d0bfb940
JK		 1251 svm->vmcb->control.intercept_exceptions &=
1252 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1253
6be7d306 1254 if (svm->nmi_singlestep)
44c11430
GN		 1255 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1256
d0bfb940
JK		 1257 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1258 if (vcpu->guest_debug &
1259 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1260 svm->vmcb->control.intercept_exceptions |=
1261 1 << DB_VECTOR;
1262 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1263 svm->vmcb->control.intercept_exceptions |=
1264 1 << BP_VECTOR;
1265 } else
1266 vcpu->guest_debug = 0;
44c11430
GN		 1267}
1268
355be0b9 1269static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1270{
44c11430
GN		 1271 struct vcpu_svm *svm = to_svm(vcpu);
1272
ae675ef0
JK		 1273 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1274 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1275 else
1276 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1277
355be0b9 1278 update_db_intercept(vcpu);
6aa8b732
AK		 1279}
1280
1281static void load_host_msrs(struct kvm_vcpu *vcpu)
1282{
94dfbdb3 1283#ifdef CONFIG_X86_64
a2fa3e9f 1284 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1285#endif
6aa8b732
AK		 1286}
1287
1288static void save_host_msrs(struct kvm_vcpu *vcpu)
1289{
94dfbdb3 1290#ifdef CONFIG_X86_64
a2fa3e9f 1291 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1292#endif
6aa8b732
AK		 1293}
1294
0fe1e009 1295static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1296{
0fe1e009
TH		 1297 if (sd->next_asid > sd->max_asid) {
1298 ++sd->asid_generation;
1299 sd->next_asid = 1;
a2fa3e9f 1300 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1301 }
1302
0fe1e009
TH		 1303 svm->asid_generation = sd->asid_generation;
1304 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1305}
1306
c76de350 1307static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1308{
42dbaa5a 1309 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1310
1311 switch (dr) {
1312 case 0 ... 3:
c76de350 1313 *dest = vcpu->arch.db[dr];
42dbaa5a 1314 break;
c76de350
JK		 1315 case 4:
1316 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1317 return EMULATE_FAIL; /* will re-inject UD */
1318 /* fall through */
42dbaa5a
JK		 1319 case 6:
1320 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1321 *dest = vcpu->arch.dr6;
42dbaa5a 1322 else
c76de350 1323 *dest = svm->vmcb->save.dr6;
42dbaa5a 1324 break;
c76de350
JK		 1325 case 5:
1326 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1327 return EMULATE_FAIL; /* will re-inject UD */
1328 /* fall through */
42dbaa5a
JK		 1329 case 7:
1330 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1331 *dest = vcpu->arch.dr7;
42dbaa5a 1332 else
c76de350 1333 *dest = svm->vmcb->save.dr7;
42dbaa5a 1334 break;
42dbaa5a
JK		 1335 }
1336
c76de350 1337 return EMULATE_DONE;
6aa8b732
AK		 1338}
1339
c76de350 1340static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1341{
a2fa3e9f
GH		 1342 struct vcpu_svm *svm = to_svm(vcpu);
1343
6aa8b732
AK		 1344 switch (dr) {
1345 case 0 ... 3:
42dbaa5a
JK		 1346 vcpu->arch.db[dr] = value;
1347 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1348 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1349 break;
1350 case 4:
1351 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1352 return EMULATE_FAIL; /* will re-inject UD */
1353 /* fall through */
42dbaa5a 1354 case 6:
42dbaa5a 1355 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1356 break;
1357 case 5:
1358 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1359 return EMULATE_FAIL; /* will re-inject UD */
1360 /* fall through */
42dbaa5a 1361 case 7:
42dbaa5a
JK		 1362 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1363 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1364 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1365 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1366 }
c76de350 1367 break;
6aa8b732 1368 }
c76de350
JK		 1369
1370 return EMULATE_DONE;
6aa8b732
AK		 1371}
1372
851ba692 1373static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1374{
6aa8b732
AK		 1375 u64 fault_address;
1376 u32 error_code;
6aa8b732 1377
a2fa3e9f
GH		 1378 fault_address = svm->vmcb->control.exit_info_2;
1379 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1380
229456fc 1381 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1382 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1383 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1384 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1385}
1386
851ba692 1387static int db_interception(struct vcpu_svm *svm)
d0bfb940 1388{
851ba692
AK		 1389 struct kvm_run *kvm_run = svm->vcpu.run;
1390
d0bfb940 1391 if (!(svm->vcpu.guest_debug &
44c11430 1392 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1393 !svm->nmi_singlestep) {
d0bfb940
JK		 1394 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1395 return 1;
1396 }
44c11430 1397
6be7d306
JK		 1398 if (svm->nmi_singlestep) {
1399 svm->nmi_singlestep = false;
44c11430
GN		 1400 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1401 svm->vmcb->save.rflags &=
1402 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1403 update_db_intercept(&svm->vcpu);
1404 }
1405
1406 if (svm->vcpu.guest_debug &
e0231715 1407 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1408 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1409 kvm_run->debug.arch.pc =
1410 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1411 kvm_run->debug.arch.exception = DB_VECTOR;
1412 return 0;
1413 }
1414
1415 return 1;
d0bfb940
JK		 1416}
1417
851ba692 1418static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1419{
851ba692
AK		 1420 struct kvm_run *kvm_run = svm->vcpu.run;
1421
d0bfb940
JK		 1422 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1423 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1424 kvm_run->debug.arch.exception = BP_VECTOR;
1425 return 0;
1426}
1427
851ba692 1428static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1429{
1430 int er;
1431
851ba692 1432 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1433 if (er != EMULATE_DONE)
7ee5d940 1434 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1435 return 1;
1436}
1437
6b52d186 1438static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1439{
6b52d186 1440 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1441 u32 excp;
1442
1443 if (is_nested(svm)) {
1444 u32 h_excp, n_excp;
1445
1446 h_excp = svm->nested.hsave->control.intercept_exceptions;
1447 n_excp = svm->nested.intercept_exceptions;
1448 h_excp &= ~(1 << NM_VECTOR);
1449 excp = h_excp | n_excp;
1450 } else {
1451 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1452 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1453 }
1454
1455 svm->vmcb->control.intercept_exceptions = excp;
1456
e756fc62 1457 svm->vcpu.fpu_active = 1;
d225157b 1458 update_cr0_intercept(svm);
6b52d186 1459}
a2fa3e9f 1460
6b52d186
AK		 1461static int nm_interception(struct vcpu_svm *svm)
1462{
1463 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1464 return 1;
7807fa6c
AL		 1465}
1466
851ba692 1467static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1468{
1469 /*
1470 * On an #MC intercept the MCE handler is not called automatically in
1471 * the host. So do it by hand here.
1472 */
1473 asm volatile (
1474 "int $0x12\n");
1475 /* not sure if we ever come back to this point */
1476
1477 return 1;
1478}
1479
851ba692 1480static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1481{
851ba692
AK		 1482 struct kvm_run *kvm_run = svm->vcpu.run;
1483
46fe4ddd
JR		 1484 /*
1485 * VMCB is undefined after a SHUTDOWN intercept
1486 * so reinitialize it.
1487 */
a2fa3e9f 1488 clear_page(svm->vmcb);
e6101a96 1489 init_vmcb(svm);
46fe4ddd
JR		 1490
1491 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1492 return 0;
1493}
1494
851ba692 1495static int io_interception(struct vcpu_svm *svm)
6aa8b732 1496{
d77c26fc 1497 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1498 int size, in, string;
039576c0 1499 unsigned port;
6aa8b732 1500
e756fc62 1501 ++svm->vcpu.stat.io_exits;
6aa8b732 1502
a2fa3e9f 1503 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1504
e70669ab
LV		 1505 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1506
1507 if (string) {
3427318f 1508 if (emulate_instruction(&svm->vcpu,
851ba692 1509 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1510 return 0;
1511 return 1;
1512 }
1513
039576c0
AK		 1514 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1515 port = io_info >> 16;
1516 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1517
e93f36bc 1518 skip_emulated_instruction(&svm->vcpu);
851ba692 1519 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1520}
1521
851ba692 1522static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1523{
1524 return 1;
1525}
1526
851ba692 1527static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1528{
1529 ++svm->vcpu.stat.irq_exits;
1530 return 1;
1531}
1532
851ba692 1533static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1534{
1535 return 1;
1536}
1537
851ba692 1538static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1539{
5fdbf976 1540 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1541 skip_emulated_instruction(&svm->vcpu);
1542 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1543}
1544
851ba692 1545static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1546{
5fdbf976 1547 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1548 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1549 kvm_emulate_hypercall(&svm->vcpu);
1550 return 1;
02e235bc
AK		 1551}
1552
c0725420
AG		 1553static int nested_svm_check_permissions(struct vcpu_svm *svm)
1554{
f6801dff 1555 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1556 || !is_paging(&svm->vcpu)) {
1557 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1558 return 1;
1559 }
1560
1561 if (svm->vmcb->save.cpl) {
1562 kvm_inject_gp(&svm->vcpu, 0);
1563 return 1;
1564 }
1565
1566 return 0;
1567}
1568
cf74a78b
AG		 1569static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1570 bool has_error_code, u32 error_code)
1571{
b8e88bc8
JR		 1572 int vmexit;
1573
0295ad7d
JR		 1574 if (!is_nested(svm))
1575 return 0;
cf74a78b 1576
0295ad7d
JR		 1577 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1578 svm->vmcb->control.exit_code_hi = 0;
1579 svm->vmcb->control.exit_info_1 = error_code;
1580 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1581
b8e88bc8
JR		 1582 vmexit = nested_svm_intercept(svm);
1583 if (vmexit == NESTED_EXIT_DONE)
1584 svm->nested.exit_required = true;
1585
1586 return vmexit;
cf74a78b
AG		 1587}
1588
8fe54654
JR		 1589/* This function returns true if it is save to enable the irq window */
1590static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1591{
26666957 1592 if (!is_nested(svm))
8fe54654 1593 return true;
cf74a78b 1594
26666957 1595 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1596 return true;
cf74a78b 1597
26666957 1598 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1599 return false;
cf74a78b 1600
197717d5
JR		 1601 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1602 svm->vmcb->control.exit_info_1 = 0;
1603 svm->vmcb->control.exit_info_2 = 0;
26666957 1604
cd3ff653
JR		 1605 if (svm->nested.intercept & 1ULL) {
1606 /*
1607 * The #vmexit can't be emulated here directly because this
1608 * code path runs with irqs and preemtion disabled. A
1609 * #vmexit emulation might sleep. Only signal request for
1610 * the #vmexit here.
1611 */
1612 svm->nested.exit_required = true;
236649de 1613 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1614 return false;
cf74a78b
AG		 1615 }
1616
8fe54654 1617 return true;
cf74a78b
AG		 1618}
1619
887f500c
JR		 1620/* This function returns true if it is save to enable the nmi window */
1621static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1622{
1623 if (!is_nested(svm))
1624 return true;
1625
1626 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1627 return true;
1628
1629 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1630 svm->nested.exit_required = true;
1631
1632 return false;
1633}
1634
7597f129 1635static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1636{
1637 struct page *page;
1638
6c3bd3d7
JR		 1639 might_sleep();
1640
34f80cfa 1641 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1642 if (is_error_page(page))
1643 goto error;
1644
7597f129
JR		 1645 *_page = page;
1646
1647 return kmap(page);
34f80cfa
JR		 1648
1649error:
1650 kvm_release_page_clean(page);
1651 kvm_inject_gp(&svm->vcpu, 0);
1652
1653 return NULL;
1654}
1655
7597f129 1656static void nested_svm_unmap(struct page *page)
34f80cfa 1657{
7597f129 1658 kunmap(page);
34f80cfa
JR		 1659 kvm_release_page_dirty(page);
1660}
1661
ce2ac085
JR		 1662static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1663{
1664 unsigned port;
1665 u8 val, bit;
1666 u64 gpa;
1667
1668 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1669 return NESTED_EXIT_HOST;
1670
1671 port = svm->vmcb->control.exit_info_1 >> 16;
1672 gpa = svm->nested.vmcb_iopm + (port / 8);
1673 bit = port % 8;
1674 val = 0;
1675
1676 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1677 val &= (1 << bit);
1678
1679 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1680}
1681
d2477826 1682static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1683{
0d6b3537
JR		 1684 u32 offset, msr, value;
1685 int write, mask;
4c2161ae 1686
3d62d9aa 1687 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1688 return NESTED_EXIT_HOST;
3d62d9aa 1689
0d6b3537
JR		 1690 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1691 offset = svm_msrpm_offset(msr);
1692 write = svm->vmcb->control.exit_info_1 & 1;
1693 mask = 1 << ((2 * (msr & 0xf)) + write);
4c2161ae 1694
0d6b3537
JR		 1695 if (offset == MSR_INVALID)
1696 return NESTED_EXIT_DONE;
3d62d9aa 1697
0d6b3537
JR		 1698 /* Offset is in 32 bit units but need in 8 bit units */
1699 offset *= 4;
1700
1701 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1702 return NESTED_EXIT_DONE;
1703
1704 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1705}
1706
410e4d57 1707static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1708{
cf74a78b 1709 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1710
410e4d57
JR		 1711 switch (exit_code) {
1712 case SVM_EXIT_INTR:
1713 case SVM_EXIT_NMI:
1714 return NESTED_EXIT_HOST;
410e4d57 1715 case SVM_EXIT_NPF:
e0231715 1716 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1717 if (npt_enabled)
1718 return NESTED_EXIT_HOST;
1719 break;
410e4d57 1720 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1721 /* When we're shadowing, trap PFs */
410e4d57
JR		 1722 if (!npt_enabled)
1723 return NESTED_EXIT_HOST;
1724 break;
66a562f7
JR		 1725 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1726 nm_interception(svm);
1727 break;
410e4d57
JR		 1728 default:
1729 break;
cf74a78b
AG		 1730 }
1731
410e4d57
JR		 1732 return NESTED_EXIT_CONTINUE;
1733}
1734
1735/*
1736 * If this function returns true, this #vmexit was already handled
1737 */
b8e88bc8 1738static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1739{
1740 u32 exit_code = svm->vmcb->control.exit_code;
1741 int vmexit = NESTED_EXIT_HOST;
1742
cf74a78b 1743 switch (exit_code) {
9c4e40b9 1744 case SVM_EXIT_MSR:
3d62d9aa 1745 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1746 break;
ce2ac085
JR		 1747 case SVM_EXIT_IOIO:
1748 vmexit = nested_svm_intercept_ioio(svm);
1749 break;
cf74a78b
AG		 1750 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1751 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1752 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1753 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1754 break;
1755 }
1756 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1757 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1758 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1759 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1760 break;
1761 }
1762 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1763 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1764 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1765 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1766 break;
1767 }
1768 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1769 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1770 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1771 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1772 break;
1773 }
1774 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1775 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1776 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1777 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1778 break;
1779 }
1780 default: {
1781 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1782 if (svm->nested.intercept & exit_bits)
410e4d57 1783 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1784 }
1785 }
1786
b8e88bc8
JR		 1787 return vmexit;
1788}
1789
1790static int nested_svm_exit_handled(struct vcpu_svm *svm)
1791{
1792 int vmexit;
1793
1794 vmexit = nested_svm_intercept(svm);
1795
1796 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1797 nested_svm_vmexit(svm);
9c4e40b9
JR		 1798
1799 return vmexit;
cf74a78b
AG		 1800}
1801
0460a979
JR		 1802static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1803{
1804 struct vmcb_control_area *dst = &dst_vmcb->control;
1805 struct vmcb_control_area *from = &from_vmcb->control;
1806
1807 dst->intercept_cr_read = from->intercept_cr_read;
1808 dst->intercept_cr_write = from->intercept_cr_write;
1809 dst->intercept_dr_read = from->intercept_dr_read;
1810 dst->intercept_dr_write = from->intercept_dr_write;
1811 dst->intercept_exceptions = from->intercept_exceptions;
1812 dst->intercept = from->intercept;
1813 dst->iopm_base_pa = from->iopm_base_pa;
1814 dst->msrpm_base_pa = from->msrpm_base_pa;
1815 dst->tsc_offset = from->tsc_offset;
1816 dst->asid = from->asid;
1817 dst->tlb_ctl = from->tlb_ctl;
1818 dst->int_ctl = from->int_ctl;
1819 dst->int_vector = from->int_vector;
1820 dst->int_state = from->int_state;
1821 dst->exit_code = from->exit_code;
1822 dst->exit_code_hi = from->exit_code_hi;
1823 dst->exit_info_1 = from->exit_info_1;
1824 dst->exit_info_2 = from->exit_info_2;
1825 dst->exit_int_info = from->exit_int_info;
1826 dst->exit_int_info_err = from->exit_int_info_err;
1827 dst->nested_ctl = from->nested_ctl;
1828 dst->event_inj = from->event_inj;
1829 dst->event_inj_err = from->event_inj_err;
1830 dst->nested_cr3 = from->nested_cr3;
1831 dst->lbr_ctl = from->lbr_ctl;
1832}
1833
34f80cfa 1834static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1835{
34f80cfa 1836 struct vmcb *nested_vmcb;
e6aa9abd 1837 struct vmcb *hsave = svm->nested.hsave;
33740e40 1838 struct vmcb *vmcb = svm->vmcb;
7597f129 1839 struct page *page;
cf74a78b 1840
17897f36
JR		 1841 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1842 vmcb->control.exit_info_1,
1843 vmcb->control.exit_info_2,
1844 vmcb->control.exit_int_info,
1845 vmcb->control.exit_int_info_err);
1846
7597f129 1847 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1848 if (!nested_vmcb)
1849 return 1;
1850
06fc7772
JR		 1851 /* Exit nested SVM mode */
1852 svm->nested.vmcb = 0;
1853
cf74a78b 1854 /* Give the current vmcb to the guest */
33740e40
JR		 1855 disable_gif(svm);
1856
1857 nested_vmcb->save.es = vmcb->save.es;
1858 nested_vmcb->save.cs = vmcb->save.cs;
1859 nested_vmcb->save.ss = vmcb->save.ss;
1860 nested_vmcb->save.ds = vmcb->save.ds;
1861 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1862 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1863 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1864 if (npt_enabled)
1865 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1866 else
1867 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1868 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1869 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1870 nested_vmcb->save.rflags = vmcb->save.rflags;
1871 nested_vmcb->save.rip = vmcb->save.rip;
1872 nested_vmcb->save.rsp = vmcb->save.rsp;
1873 nested_vmcb->save.rax = vmcb->save.rax;
1874 nested_vmcb->save.dr7 = vmcb->save.dr7;
1875 nested_vmcb->save.dr6 = vmcb->save.dr6;
1876 nested_vmcb->save.cpl = vmcb->save.cpl;
1877
1878 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1879 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1880 nested_vmcb->control.int_state = vmcb->control.int_state;
1881 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1882 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1883 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1884 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1885 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1886 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1887
1888 /*
1889 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1890 * to make sure that we do not lose injected events. So check event_inj
1891 * here and copy it to exit_int_info if it is valid.
1892 * Exit_int_info and event_inj can't be both valid because the case
1893 * below only happens on a VMRUN instruction intercept which has
1894 * no valid exit_int_info set.
1895 */
1896 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1897 struct vmcb_control_area *nc = &nested_vmcb->control;
1898
1899 nc->exit_int_info = vmcb->control.event_inj;
1900 nc->exit_int_info_err = vmcb->control.event_inj_err;
1901 }
1902
33740e40
JR		 1903 nested_vmcb->control.tlb_ctl = 0;
1904 nested_vmcb->control.event_inj = 0;
1905 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1906
1907 /* We always set V_INTR_MASKING and remember the old value in hflags */
1908 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1909 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1910
cf74a78b 1911 /* Restore the original control entries */
0460a979 1912 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1913
219b65dc
AG		 1914 kvm_clear_exception_queue(&svm->vcpu);
1915 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1916
1917 /* Restore selected save entries */
1918 svm->vmcb->save.es = hsave->save.es;
1919 svm->vmcb->save.cs = hsave->save.cs;
1920 svm->vmcb->save.ss = hsave->save.ss;
1921 svm->vmcb->save.ds = hsave->save.ds;
1922 svm->vmcb->save.gdtr = hsave->save.gdtr;
1923 svm->vmcb->save.idtr = hsave->save.idtr;
1924 svm->vmcb->save.rflags = hsave->save.rflags;
1925 svm_set_efer(&svm->vcpu, hsave->save.efer);
1926 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1927 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1928 if (npt_enabled) {
1929 svm->vmcb->save.cr3 = hsave->save.cr3;
1930 svm->vcpu.arch.cr3 = hsave->save.cr3;
1931 } else {
1932 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1933 }
1934 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1935 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1936 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1937 svm->vmcb->save.dr7 = 0;
1938 svm->vmcb->save.cpl = 0;
1939 svm->vmcb->control.exit_int_info = 0;
1940
7597f129 1941 nested_svm_unmap(page);
cf74a78b
AG		 1942
1943 kvm_mmu_reset_context(&svm->vcpu);
1944 kvm_mmu_load(&svm->vcpu);
1945
1946 return 0;
1947}
3d6368ef 1948
9738b2c9 1949static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1950{
323c3d80
JR		 1951 /*
1952 * This function merges the msr permission bitmaps of kvm and the
1953 * nested vmcb. It is omptimized in that it only merges the parts where
1954 * the kvm msr permission bitmap may contain zero bits
1955 */
3d6368ef 1956 int i;
9738b2c9 1957
323c3d80
JR		 1958 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1959 return true;
9738b2c9 1960
323c3d80
JR		 1961 for (i = 0; i < MSRPM_OFFSETS; i++) {
1962 u32 value, p;
1963 u64 offset;
9738b2c9 1964
323c3d80
JR		 1965 if (msrpm_offsets[i] == 0xffffffff)
1966 break;
3d6368ef 1967
0d6b3537
JR		 1968 p = msrpm_offsets[i];
1969 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 1970
1971 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1972 return false;
1973
1974 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1975 }
1976
1977 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 1978
1979 return true;
3d6368ef
AG		 1980}
1981
9738b2c9 1982static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1983{
9738b2c9 1984 struct vmcb *nested_vmcb;
e6aa9abd 1985 struct vmcb *hsave = svm->nested.hsave;
defbba56 1986 struct vmcb *vmcb = svm->vmcb;
7597f129 1987 struct page *page;
06fc7772
JR		 1988 u64 vmcb_gpa;
1989
1990 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1991
7597f129 1992 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1993 if (!nested_vmcb)
1994 return false;
1995
ecf1405d 1996 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 1997 nested_vmcb->save.rip,
1998 nested_vmcb->control.int_ctl,
1999 nested_vmcb->control.event_inj,
2000 nested_vmcb->control.nested_ctl);
2001
2e554e8d
JR		 2002 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2003 nested_vmcb->control.intercept_cr_write,
2004 nested_vmcb->control.intercept_exceptions,
2005 nested_vmcb->control.intercept);
2006
3d6368ef 2007 /* Clear internal status */
219b65dc
AG		 2008 kvm_clear_exception_queue(&svm->vcpu);
2009 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2010
e0231715
JR		 2011 /*
2012 * Save the old vmcb, so we don't need to pick what we save, but can
2013 * restore everything when a VMEXIT occurs
2014 */
defbba56
JR		 2015 hsave->save.es = vmcb->save.es;
2016 hsave->save.cs = vmcb->save.cs;
2017 hsave->save.ss = vmcb->save.ss;
2018 hsave->save.ds = vmcb->save.ds;
2019 hsave->save.gdtr = vmcb->save.gdtr;
2020 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2021 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2022 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2023 hsave->save.cr4 = svm->vcpu.arch.cr4;
2024 hsave->save.rflags = vmcb->save.rflags;
2025 hsave->save.rip = svm->next_rip;
2026 hsave->save.rsp = vmcb->save.rsp;
2027 hsave->save.rax = vmcb->save.rax;
2028 if (npt_enabled)
2029 hsave->save.cr3 = vmcb->save.cr3;
2030 else
2031 hsave->save.cr3 = svm->vcpu.arch.cr3;
2032
0460a979 2033 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2034
2035 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2036 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2037 else
2038 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2039
2040 /* Load the nested guest state */
2041 svm->vmcb->save.es = nested_vmcb->save.es;
2042 svm->vmcb->save.cs = nested_vmcb->save.cs;
2043 svm->vmcb->save.ss = nested_vmcb->save.ss;
2044 svm->vmcb->save.ds = nested_vmcb->save.ds;
2045 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2046 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2047 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2048 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2049 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2050 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2051 if (npt_enabled) {
2052 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2053 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2054 } else
3d6368ef 2055 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2056
2057 /* Guest paging mode is active - reset mmu */
2058 kvm_mmu_reset_context(&svm->vcpu);
2059
defbba56 2060 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2061 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2062 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2063 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2064
3d6368ef
AG		 2065 /* In case we don't even reach vcpu_run, the fields are not updated */
2066 svm->vmcb->save.rax = nested_vmcb->save.rax;
2067 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2068 svm->vmcb->save.rip = nested_vmcb->save.rip;
2069 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2070 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2071 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2072
f7138538 2073 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2074 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2075
aad42c64
JR		 2076 /* cache intercepts */
2077 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2078 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2079 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2080 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2081 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2082 svm->nested.intercept = nested_vmcb->control.intercept;
2083
3d6368ef 2084 force_new_asid(&svm->vcpu);
3d6368ef 2085 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2086 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2087 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2088 else
2089 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2090
88ab24ad
JR		 2091 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2092 /* We only want the cr8 intercept bits of the guest */
2093 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2094 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2095 }
2096
e0231715
JR		 2097 /*
2098 * We don't want a nested guest to be more powerful than the guest, so
2099 * all intercepts are ORed
2100 */
88ab24ad
JR		 2101 svm->vmcb->control.intercept_cr_read |=
2102 nested_vmcb->control.intercept_cr_read;
2103 svm->vmcb->control.intercept_cr_write |=
2104 nested_vmcb->control.intercept_cr_write;
2105 svm->vmcb->control.intercept_dr_read |=
2106 nested_vmcb->control.intercept_dr_read;
2107 svm->vmcb->control.intercept_dr_write |=
2108 nested_vmcb->control.intercept_dr_write;
2109 svm->vmcb->control.intercept_exceptions |=
2110 nested_vmcb->control.intercept_exceptions;
2111
2112 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2113
2114 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2115 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2116 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2117 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2118 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2119 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2120
7597f129 2121 nested_svm_unmap(page);
9738b2c9 2122
06fc7772
JR		 2123 /* nested_vmcb is our indicator if nested SVM is activated */
2124 svm->nested.vmcb = vmcb_gpa;
2125
2af9194d 2126 enable_gif(svm);
3d6368ef 2127
9738b2c9 2128 return true;
3d6368ef
AG		 2129}
2130
9966bf68 2131static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2132{
2133 to_vmcb->save.fs = from_vmcb->save.fs;
2134 to_vmcb->save.gs = from_vmcb->save.gs;
2135 to_vmcb->save.tr = from_vmcb->save.tr;
2136 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2137 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2138 to_vmcb->save.star = from_vmcb->save.star;
2139 to_vmcb->save.lstar = from_vmcb->save.lstar;
2140 to_vmcb->save.cstar = from_vmcb->save.cstar;
2141 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2142 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2143 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2144 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2145}
2146
851ba692 2147static int vmload_interception(struct vcpu_svm *svm)
5542675b 2148{
9966bf68 2149 struct vmcb *nested_vmcb;
7597f129 2150 struct page *page;
9966bf68 2151
5542675b
AG		 2152 if (nested_svm_check_permissions(svm))
2153 return 1;
2154
2155 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2156 skip_emulated_instruction(&svm->vcpu);
2157
7597f129 2158 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2159 if (!nested_vmcb)
2160 return 1;
2161
2162 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2163 nested_svm_unmap(page);
5542675b
AG		 2164
2165 return 1;
2166}
2167
851ba692 2168static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2169{
9966bf68 2170 struct vmcb *nested_vmcb;
7597f129 2171 struct page *page;
9966bf68 2172
5542675b
AG		 2173 if (nested_svm_check_permissions(svm))
2174 return 1;
2175
2176 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2177 skip_emulated_instruction(&svm->vcpu);
2178
7597f129 2179 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2180 if (!nested_vmcb)
2181 return 1;
2182
2183 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2184 nested_svm_unmap(page);
5542675b
AG		 2185
2186 return 1;
2187}
2188
851ba692 2189static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2190{
3d6368ef
AG		 2191 if (nested_svm_check_permissions(svm))
2192 return 1;
2193
2194 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2195 skip_emulated_instruction(&svm->vcpu);
2196
9738b2c9 2197 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2198 return 1;
2199
9738b2c9 2200 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2201 goto failed;
2202
2203 return 1;
2204
2205failed:
2206
2207 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2208 svm->vmcb->control.exit_code_hi = 0;
2209 svm->vmcb->control.exit_info_1 = 0;
2210 svm->vmcb->control.exit_info_2 = 0;
2211
2212 nested_svm_vmexit(svm);
3d6368ef
AG		 2213
2214 return 1;
2215}
2216
851ba692 2217static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2218{
2219 if (nested_svm_check_permissions(svm))
2220 return 1;
2221
2222 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2223 skip_emulated_instruction(&svm->vcpu);
2224
2af9194d 2225 enable_gif(svm);
1371d904
AG		 2226
2227 return 1;
2228}
2229
851ba692 2230static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2231{
2232 if (nested_svm_check_permissions(svm))
2233 return 1;
2234
2235 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2236 skip_emulated_instruction(&svm->vcpu);
2237
2af9194d 2238 disable_gif(svm);
1371d904
AG		 2239
2240 /* After a CLGI no interrupts should come */
2241 svm_clear_vintr(svm);
2242 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2243
2244 return 1;
2245}
2246
851ba692 2247static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2248{
2249 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2250
ec1ff790
JR		 2251 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2252 vcpu->arch.regs[VCPU_REGS_RAX]);
2253
ff092385
AG		 2254 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2255 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2256
2257 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2258 skip_emulated_instruction(&svm->vcpu);
2259 return 1;
2260}
2261
532a46b9
JR		 2262static int skinit_interception(struct vcpu_svm *svm)
2263{
2264 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2265
2266 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2267 return 1;
2268}
2269
851ba692 2270static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2271{
7ee5d940 2272 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2273 return 1;
2274}
2275
851ba692 2276static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2277{
37817f29 2278 u16 tss_selector;
64a7ec06
GN		 2279 int reason;
2280 int int_type = svm->vmcb->control.exit_int_info &
2281 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2282 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2283 uint32_t type =
2284 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2285 uint32_t idt_v =
2286 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2287
2288 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2289
37817f29
IE		 2290 if (svm->vmcb->control.exit_info_2 &
2291 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2292 reason = TASK_SWITCH_IRET;
2293 else if (svm->vmcb->control.exit_info_2 &
2294 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2295 reason = TASK_SWITCH_JMP;
fe8e7f83 2296 else if (idt_v)
64a7ec06
GN		 2297 reason = TASK_SWITCH_GATE;
2298 else
2299 reason = TASK_SWITCH_CALL;
2300
fe8e7f83
GN		 2301 if (reason == TASK_SWITCH_GATE) {
2302 switch (type) {
2303 case SVM_EXITINTINFO_TYPE_NMI:
2304 svm->vcpu.arch.nmi_injected = false;
2305 break;
2306 case SVM_EXITINTINFO_TYPE_EXEPT:
2307 kvm_clear_exception_queue(&svm->vcpu);
2308 break;
2309 case SVM_EXITINTINFO_TYPE_INTR:
2310 kvm_clear_interrupt_queue(&svm->vcpu);
2311 break;
2312 default:
2313 break;
2314 }
2315 }
64a7ec06 2316
8317c298
GN		 2317 if (reason != TASK_SWITCH_GATE ||
2318 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2319 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2320 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2321 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2322
2323 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2324}
2325
851ba692 2326static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2327{
5fdbf976 2328 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2329 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2330 return 1;
6aa8b732
AK		 2331}
2332
851ba692 2333static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2334{
2335 ++svm->vcpu.stat.nmi_window_exits;
2336 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2337 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2338 return 1;
2339}
2340
851ba692 2341static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2342{
851ba692 2343 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2344 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2345 return 1;
2346}
2347
851ba692 2348static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2349{
851ba692 2350 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2351 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2352 return 1;
2353}
2354
851ba692 2355static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2356{
851ba692
AK		 2357 struct kvm_run *kvm_run = svm->vcpu.run;
2358
0a5fff19
GN		 2359 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2360 /* instruction emulation calls kvm_set_cr8() */
851ba692 2361 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2362 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2363 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2364 return 1;
95ba8273 2365 }
0a5fff19
GN		 2366 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2367 return 1;
1d075434
JR		 2368 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2369 return 0;
2370}
2371
6aa8b732
AK		 2372static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2373{
a2fa3e9f
GH		 2374 struct vcpu_svm *svm = to_svm(vcpu);
2375
6aa8b732 2376 switch (ecx) {
af24a4e4 2377 case MSR_IA32_TSC: {
20824f30 2378 u64 tsc_offset;
6aa8b732 2379
20824f30
JR		 2380 if (is_nested(svm))
2381 tsc_offset = svm->nested.hsave->control.tsc_offset;
2382 else
2383 tsc_offset = svm->vmcb->control.tsc_offset;
2384
2385 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2386 break;
2387 }
0e859cac 2388 case MSR_K6_STAR:
a2fa3e9f 2389 *data = svm->vmcb->save.star;
6aa8b732 2390 break;
0e859cac 2391#ifdef CONFIG_X86_64
6aa8b732 2392 case MSR_LSTAR:
a2fa3e9f 2393 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2394 break;
2395 case MSR_CSTAR:
a2fa3e9f 2396 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2397 break;
2398 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2399 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2400 break;
2401 case MSR_SYSCALL_MASK:
a2fa3e9f 2402 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2403 break;
2404#endif
2405 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2406 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2407 break;
2408 case MSR_IA32_SYSENTER_EIP:
017cb99e 2409 *data = svm->sysenter_eip;
6aa8b732
AK		 2410 break;
2411 case MSR_IA32_SYSENTER_ESP:
017cb99e 2412 *data = svm->sysenter_esp;
6aa8b732 2413 break;
e0231715
JR		 2414 /*
2415 * Nobody will change the following 5 values in the VMCB so we can
2416 * safely return them on rdmsr. They will always be 0 until LBRV is
2417 * implemented.
2418 */
a2938c80
JR		 2419 case MSR_IA32_DEBUGCTLMSR:
2420 *data = svm->vmcb->save.dbgctl;
2421 break;
2422 case MSR_IA32_LASTBRANCHFROMIP:
2423 *data = svm->vmcb->save.br_from;
2424 break;
2425 case MSR_IA32_LASTBRANCHTOIP:
2426 *data = svm->vmcb->save.br_to;
2427 break;
2428 case MSR_IA32_LASTINTFROMIP:
2429 *data = svm->vmcb->save.last_excp_from;
2430 break;
2431 case MSR_IA32_LASTINTTOIP:
2432 *data = svm->vmcb->save.last_excp_to;
2433 break;
b286d5d8 2434 case MSR_VM_HSAVE_PA:
e6aa9abd 2435 *data = svm->nested.hsave_msr;
b286d5d8 2436 break;
eb6f302e 2437 case MSR_VM_CR:
4a810181 2438 *data = svm->nested.vm_cr_msr;
eb6f302e 2439 break;
c8a73f18
AG		 2440 case MSR_IA32_UCODE_REV:
2441 *data = 0x01000065;
2442 break;
6aa8b732 2443 default:
3bab1f5d 2444 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2445 }
2446 return 0;
2447}
2448
851ba692 2449static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2450{
ad312c7c 2451 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2452 u64 data;
2453
59200273
AK		 2454 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2455 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2456 kvm_inject_gp(&svm->vcpu, 0);
59200273 2457 } else {
229456fc 2458 trace_kvm_msr_read(ecx, data);
af9ca2d7 2459
5fdbf976 2460 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2461 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2462 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2463 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2464 }
2465 return 1;
2466}
2467
4a810181
JR		 2468static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2469{
2470 struct vcpu_svm *svm = to_svm(vcpu);
2471 int svm_dis, chg_mask;
2472
2473 if (data & ~SVM_VM_CR_VALID_MASK)
2474 return 1;
2475
2476 chg_mask = SVM_VM_CR_VALID_MASK;
2477
2478 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2479 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2480
2481 svm->nested.vm_cr_msr &= ~chg_mask;
2482 svm->nested.vm_cr_msr |= (data & chg_mask);
2483
2484 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2485
2486 /* check for svm_disable while efer.svme is set */
2487 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2488 return 1;
2489
2490 return 0;
2491}
2492
6aa8b732
AK		 2493static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2494{
a2fa3e9f
GH		 2495 struct vcpu_svm *svm = to_svm(vcpu);
2496
6aa8b732 2497 switch (ecx) {
af24a4e4 2498 case MSR_IA32_TSC: {
20824f30
JR		 2499 u64 tsc_offset = data - native_read_tsc();
2500 u64 g_tsc_offset = 0;
2501
2502 if (is_nested(svm)) {
2503 g_tsc_offset = svm->vmcb->control.tsc_offset -
2504 svm->nested.hsave->control.tsc_offset;
2505 svm->nested.hsave->control.tsc_offset = tsc_offset;
2506 }
2507
2508 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2509
6aa8b732
AK		 2510 break;
2511 }
0e859cac 2512 case MSR_K6_STAR:
a2fa3e9f 2513 svm->vmcb->save.star = data;
6aa8b732 2514 break;
49b14f24 2515#ifdef CONFIG_X86_64
6aa8b732 2516 case MSR_LSTAR:
a2fa3e9f 2517 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2518 break;
2519 case MSR_CSTAR:
a2fa3e9f 2520 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2521 break;
2522 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2523 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2524 break;
2525 case MSR_SYSCALL_MASK:
a2fa3e9f 2526 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2527 break;
2528#endif
2529 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2530 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2531 break;
2532 case MSR_IA32_SYSENTER_EIP:
017cb99e 2533 svm->sysenter_eip = data;
a2fa3e9f 2534 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2535 break;
2536 case MSR_IA32_SYSENTER_ESP:
017cb99e 2537 svm->sysenter_esp = data;
a2fa3e9f 2538 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2539 break;
a2938c80 2540 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2541 if (!svm_has(SVM_FEATURE_LBRV)) {
2542 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2543 __func__, data);
24e09cbf
JR		 2544 break;
2545 }
2546 if (data & DEBUGCTL_RESERVED_BITS)
2547 return 1;
2548
2549 svm->vmcb->save.dbgctl = data;
2550 if (data & (1ULL<<0))
2551 svm_enable_lbrv(svm);
2552 else
2553 svm_disable_lbrv(svm);
a2938c80 2554 break;
b286d5d8 2555 case MSR_VM_HSAVE_PA:
e6aa9abd 2556 svm->nested.hsave_msr = data;
62b9abaa 2557 break;
3c5d0a44 2558 case MSR_VM_CR:
4a810181 2559 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2560 case MSR_VM_IGNNE:
3c5d0a44
AG		 2561 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2562 break;
6aa8b732 2563 default:
3bab1f5d 2564 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2565 }
2566 return 0;
2567}
2568
851ba692 2569static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2570{
ad312c7c 2571 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2572 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2573 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2574
af9ca2d7 2575
5fdbf976 2576 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2577 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2578 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2579 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2580 } else {
2581 trace_kvm_msr_write(ecx, data);
e756fc62 2582 skip_emulated_instruction(&svm->vcpu);
59200273 2583 }
6aa8b732
AK		 2584 return 1;
2585}
2586
851ba692 2587static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2588{
e756fc62 2589 if (svm->vmcb->control.exit_info_1)
851ba692 2590 return wrmsr_interception(svm);
6aa8b732 2591 else
851ba692 2592 return rdmsr_interception(svm);
6aa8b732
AK		 2593}
2594
851ba692 2595static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2596{
851ba692
AK		 2597 struct kvm_run *kvm_run = svm->vcpu.run;
2598
f0b85051 2599 svm_clear_vintr(svm);
85f455f7 2600 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2601 /*
2602 * If the user space waits to inject interrupts, exit as soon as
2603 * possible
2604 */
8061823a
GN		 2605 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2606 kvm_run->request_interrupt_window &&
2607 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2608 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2609 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2610 return 0;
2611 }
2612
2613 return 1;
2614}
2615
565d0998
ML		 2616static int pause_interception(struct vcpu_svm *svm)
2617{
2618 kvm_vcpu_on_spin(&(svm->vcpu));
2619 return 1;
2620}
2621
851ba692 2622static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2623 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2624 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2625 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2626 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2627 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2628 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2629 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2630 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2631 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2632 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2633 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2634 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2635 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2636 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2637 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2638 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2639 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2640 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2641 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2642 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2643 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2644 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2645 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2646 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2647 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2648 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2649 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2650 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2651 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2652 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2653 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2654 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2655 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2656 [SVM_EXIT_SMI] = nop_on_interception,
2657 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2658 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2659 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2660 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2661 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2662 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2663 [SVM_EXIT_HLT] = halt_interception,
a7052897 2664 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2665 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2666 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2667 [SVM_EXIT_MSR] = msr_interception,
2668 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2669 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2670 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2671 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2672 [SVM_EXIT_VMLOAD] = vmload_interception,
2673 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2674 [SVM_EXIT_STGI] = stgi_interception,
2675 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2676 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2677 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2678 [SVM_EXIT_MONITOR] = invalid_op_interception,
2679 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2680 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2681};
2682
851ba692 2683static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2684{
04d2cc77 2685 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2686 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2687 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2688
5bfd8b54 2689 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2690
cd3ff653
JR		 2691 if (unlikely(svm->nested.exit_required)) {
2692 nested_svm_vmexit(svm);
2693 svm->nested.exit_required = false;
2694
2695 return 1;
2696 }
2697
cf74a78b 2698 if (is_nested(svm)) {
410e4d57
JR		 2699 int vmexit;
2700
d8cabddf
JR		 2701 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2702 svm->vmcb->control.exit_info_1,
2703 svm->vmcb->control.exit_info_2,
2704 svm->vmcb->control.exit_int_info,
2705 svm->vmcb->control.exit_int_info_err);
2706
410e4d57
JR		 2707 vmexit = nested_svm_exit_special(svm);
2708
2709 if (vmexit == NESTED_EXIT_CONTINUE)
2710 vmexit = nested_svm_exit_handled(svm);
2711
2712 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2713 return 1;
cf74a78b
AG		 2714 }
2715
a5c3832d
JR		 2716 svm_complete_interrupts(svm);
2717
888f9f3e 2718 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2719 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2720 if (npt_enabled)
709ddebf 2721 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2722
2723 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2724 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2725 kvm_run->fail_entry.hardware_entry_failure_reason
2726 = svm->vmcb->control.exit_code;
2727 return 0;
2728 }
2729
a2fa3e9f 2730 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2731 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2732 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2733 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2734 "exit_code 0x%x\n",
b8688d51 2735 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2736 exit_code);
2737
9d8f549d 2738 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2739 || !svm_exit_handlers[exit_code]) {
6aa8b732 2740 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2741 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2742 return 0;
2743 }
2744
851ba692 2745 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2746}
2747
2748static void reload_tss(struct kvm_vcpu *vcpu)
2749{
2750 int cpu = raw_smp_processor_id();
2751
0fe1e009
TH		 2752 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2753 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2754 load_TR_desc();
2755}
2756
e756fc62 2757static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2758{
2759 int cpu = raw_smp_processor_id();
2760
0fe1e009 2761 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2762
a2fa3e9f 2763 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2764 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2765 if (svm->asid_generation != sd->asid_generation)
2766 new_asid(svm, sd);
6aa8b732
AK		 2767}
2768
95ba8273
GN		 2769static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2770{
2771 struct vcpu_svm *svm = to_svm(vcpu);
2772
2773 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2774 vcpu->arch.hflags |= HF_NMI_MASK;
2775 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2776 ++vcpu->stat.nmi_injections;
2777}
6aa8b732 2778
85f455f7 2779static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2780{
2781 struct vmcb_control_area *control;
2782
229456fc 2783 trace_kvm_inj_virq(irq);
af9ca2d7 2784
fa89a817 2785 ++svm->vcpu.stat.irq_injections;
e756fc62 2786 control = &svm->vmcb->control;
85f455f7 2787 control->int_vector = irq;
6aa8b732
AK		 2788 control->int_ctl &= ~V_INTR_PRIO_MASK;
2789 control->int_ctl |= V_IRQ_MASK |
2790 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2791}
2792
66fd3f7f 2793static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2794{
2795 struct vcpu_svm *svm = to_svm(vcpu);
2796
2af9194d 2797 BUG_ON(!(gif_set(svm)));
cf74a78b 2798
219b65dc
AG		 2799 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2800 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2801}
2802
95ba8273 2803static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2804{
2805 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2806
88ab24ad
JR		 2807 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2808 return;
2809
95ba8273 2810 if (irr == -1)
aaacfc9a
JR		 2811 return;
2812
95ba8273
GN		 2813 if (tpr >= irr)
2814 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2815}
aaacfc9a 2816
95ba8273
GN		 2817static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2818{
2819 struct vcpu_svm *svm = to_svm(vcpu);
2820 struct vmcb *vmcb = svm->vmcb;
2821 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2822 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2823}
2824
3cfc3092
JK		 2825static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2826{
2827 struct vcpu_svm *svm = to_svm(vcpu);
2828
2829 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2830}
2831
2832static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2833{
2834 struct vcpu_svm *svm = to_svm(vcpu);
2835
2836 if (masked) {
2837 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2838 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2839 } else {
2840 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2841 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2842 }
2843}
2844
78646121
GN		 2845static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2846{
2847 struct vcpu_svm *svm = to_svm(vcpu);
2848 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2849 int ret;
2850
2851 if (!gif_set(svm) ||
2852 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2853 return 0;
2854
2855 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2856
2857 if (is_nested(svm))
2858 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2859
2860 return ret;
78646121
GN		 2861}
2862
9222be18 2863static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2864{
219b65dc 2865 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2866
e0231715
JR		 2867 /*
2868 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2869 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2870 * get that intercept, this function will be called again though and
2871 * we'll get the vintr intercept.
2872 */
8fe54654 2873 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2874 svm_set_vintr(svm);
2875 svm_inject_irq(svm, 0x0);
2876 }
85f455f7
ED		 2877}
2878
95ba8273 2879static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2880{
04d2cc77 2881 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2882
44c11430
GN		 2883 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2884 == HF_NMI_MASK)
2885 return; /* IRET will cause a vm exit */
2886
e0231715
JR		 2887 /*
2888 * Something prevents NMI from been injected. Single step over possible
2889 * problem (IRET or exception injection or interrupt shadow)
2890 */
887f500c
JR		 2891 if (gif_set(svm) && nested_svm_nmi(svm)) {
2892 svm->nmi_singlestep = true;
2893 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2894 update_db_intercept(vcpu);
2895 }
c1150d8c
DL		 2896}
2897
cbc94022
IE		 2898static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2899{
2900 return 0;
2901}
2902
d9e368d6
AK		 2903static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2904{
2905 force_new_asid(vcpu);
2906}
2907
04d2cc77
AK		 2908static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2909{
2910}
2911
d7bf8221
JR		 2912static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2913{
2914 struct vcpu_svm *svm = to_svm(vcpu);
2915
88ab24ad
JR		 2916 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2917 return;
2918
d7bf8221
JR		 2919 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2920 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2921 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2922 }
2923}
2924
649d6864
JR		 2925static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2926{
2927 struct vcpu_svm *svm = to_svm(vcpu);
2928 u64 cr8;
2929
88ab24ad
JR		 2930 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2931 return;
2932
649d6864
JR		 2933 cr8 = kvm_get_cr8(vcpu);
2934 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2935 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2936}
2937
9222be18
GN		 2938static void svm_complete_interrupts(struct vcpu_svm *svm)
2939{
2940 u8 vector;
2941 int type;
2942 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2943 unsigned int3_injected = svm->int3_injected;
2944
2945 svm->int3_injected = 0;
9222be18 2946
44c11430
GN		 2947 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2948 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2949
9222be18
GN		 2950 svm->vcpu.arch.nmi_injected = false;
2951 kvm_clear_exception_queue(&svm->vcpu);
2952 kvm_clear_interrupt_queue(&svm->vcpu);
2953
2954 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2955 return;
2956
2957 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2958 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2959
2960 switch (type) {
2961 case SVM_EXITINTINFO_TYPE_NMI:
2962 svm->vcpu.arch.nmi_injected = true;
2963 break;
2964 case SVM_EXITINTINFO_TYPE_EXEPT:
219b65dc
AG		 2965 if (is_nested(svm))
2966 break;
66b7138f
JK		 2967 /*
2968 * In case of software exceptions, do not reinject the vector,
2969 * but re-execute the instruction instead. Rewind RIP first
2970 * if we emulated INT3 before.
2971 */
2972 if (kvm_exception_is_soft(vector)) {
2973 if (vector == BP_VECTOR && int3_injected &&
2974 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2975 kvm_rip_write(&svm->vcpu,
2976 kvm_rip_read(&svm->vcpu) -
2977 int3_injected);
9222be18 2978 break;
66b7138f 2979 }
9222be18
GN		 2980 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2981 u32 err = svm->vmcb->control.exit_int_info_err;
2982 kvm_queue_exception_e(&svm->vcpu, vector, err);
2983
2984 } else
2985 kvm_queue_exception(&svm->vcpu, vector);
2986 break;
2987 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2988 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2989 break;
2990 default:
2991 break;
2992 }
2993}
2994
80e31d4f
AK		 2995#ifdef CONFIG_X86_64
2996#define R "r"
2997#else
2998#define R "e"
2999#endif
3000
851ba692 3001static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3002{
a2fa3e9f 3003 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3004 u16 fs_selector;
3005 u16 gs_selector;
3006 u16 ldt_selector;
d9e368d6 3007
cd3ff653
JR		 3008 /*
3009 * A vmexit emulation is required before the vcpu can be executed
3010 * again.
3011 */
3012 if (unlikely(svm->nested.exit_required))
3013 return;
3014
5fdbf976
MT		 3015 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3016 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3017 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3018
e756fc62 3019 pre_svm_run(svm);
6aa8b732 3020
649d6864
JR		 3021 sync_lapic_to_cr8(vcpu);
3022
6aa8b732 3023 save_host_msrs(vcpu);
d6e88aec
AK		 3024 fs_selector = kvm_read_fs();
3025 gs_selector = kvm_read_gs();
3026 ldt_selector = kvm_read_ldt();
cda0ffdd 3027 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 3028 /* required for live migration with NPT */
3029 if (npt_enabled)
3030 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 3031
04d2cc77
AK		 3032 clgi();
3033
3034 local_irq_enable();
36241b8c 3035
6aa8b732 3036 asm volatile (
80e31d4f
AK		 3037 "push %%"R"bp; \n\t"
3038 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3039 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3040 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3041 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3042 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3043 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3044#ifdef CONFIG_X86_64
fb3f0f51
RR		 3045 "mov %c[r8](%[svm]), %%r8 \n\t"
3046 "mov %c[r9](%[svm]), %%r9 \n\t"
3047 "mov %c[r10](%[svm]), %%r10 \n\t"
3048 "mov %c[r11](%[svm]), %%r11 \n\t"
3049 "mov %c[r12](%[svm]), %%r12 \n\t"
3050 "mov %c[r13](%[svm]), %%r13 \n\t"
3051 "mov %c[r14](%[svm]), %%r14 \n\t"
3052 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3053#endif
3054
6aa8b732 3055 /* Enter guest mode */
80e31d4f
AK		 3056 "push %%"R"ax \n\t"
3057 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3058 __ex(SVM_VMLOAD) "\n\t"
3059 __ex(SVM_VMRUN) "\n\t"
3060 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3061 "pop %%"R"ax \n\t"
6aa8b732
AK		 3062
3063 /* Save guest registers, load host registers */
80e31d4f
AK		 3064 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3065 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3066 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3067 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3068 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3069 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3070#ifdef CONFIG_X86_64
fb3f0f51
RR		 3071 "mov %%r8, %c[r8](%[svm]) \n\t"
3072 "mov %%r9, %c[r9](%[svm]) \n\t"
3073 "mov %%r10, %c[r10](%[svm]) \n\t"
3074 "mov %%r11, %c[r11](%[svm]) \n\t"
3075 "mov %%r12, %c[r12](%[svm]) \n\t"
3076 "mov %%r13, %c[r13](%[svm]) \n\t"
3077 "mov %%r14, %c[r14](%[svm]) \n\t"
3078 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3079#endif
80e31d4f 3080 "pop %%"R"bp"
6aa8b732 3081 :
fb3f0f51 3082 : [svm]"a"(svm),
6aa8b732 3083 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3084 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3085 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3086 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3087 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3088 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3089 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3090#ifdef CONFIG_X86_64
ad312c7c
ZX		 3091 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3092 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3093 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3094 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3095 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3096 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3097 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3098 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3099#endif
54a08c04 3100 : "cc", "memory"
80e31d4f 3101 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3102#ifdef CONFIG_X86_64
54a08c04
LV		 3103 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3104#endif
3105 );
6aa8b732 3106
ad312c7c 3107 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3108 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3109 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3110 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3111
d6e88aec
AK		 3112 kvm_load_fs(fs_selector);
3113 kvm_load_gs(gs_selector);
3114 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3115 load_host_msrs(vcpu);
3116
3117 reload_tss(vcpu);
3118
56ba47dd
AK		 3119 local_irq_disable();
3120
3121 stgi();
3122
d7bf8221
JR		 3123 sync_cr8_to_lapic(vcpu);
3124
a2fa3e9f 3125 svm->next_rip = 0;
9222be18 3126
6de4f3ad
AK		 3127 if (npt_enabled) {
3128 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3129 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3130 }
6aa8b732
AK		 3131}
3132
80e31d4f
AK		 3133#undef R
3134
6aa8b732
AK		 3135static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3136{
a2fa3e9f
GH		 3137 struct vcpu_svm *svm = to_svm(vcpu);
3138
709ddebf
JR		 3139 if (npt_enabled) {
3140 svm->vmcb->control.nested_cr3 = root;
3141 force_new_asid(vcpu);
3142 return;
3143 }
3144
a2fa3e9f 3145 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3146 force_new_asid(vcpu);
3147}
3148
6aa8b732
AK		 3149static int is_disabled(void)
3150{
6031a61c
JR		 3151 u64 vm_cr;
3152
3153 rdmsrl(MSR_VM_CR, vm_cr);
3154 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3155 return 1;
3156
6aa8b732
AK		 3157 return 0;
3158}
3159
102d8325
IM		 3160static void
3161svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3162{
3163 /*
3164 * Patch in the VMMCALL instruction:
3165 */
3166 hypercall[0] = 0x0f;
3167 hypercall[1] = 0x01;
3168 hypercall[2] = 0xd9;
102d8325
IM		 3169}
3170
002c7f7c
YS		 3171static void svm_check_processor_compat(void *rtn)
3172{
3173 *(int *)rtn = 0;
3174}
3175
774ead3a
AK		 3176static bool svm_cpu_has_accelerated_tpr(void)
3177{
3178 return false;
3179}
3180
67253af5
SY		 3181static int get_npt_level(void)
3182{
3183#ifdef CONFIG_X86_64
3184 return PT64_ROOT_LEVEL;
3185#else
3186 return PT32E_ROOT_LEVEL;
3187#endif
3188}
3189
4b12f0de 3190static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3191{
3192 return 0;
3193}
3194
0e851880
SY		 3195static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3196{
3197}
3198
229456fc 3199static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3200 { SVM_EXIT_READ_CR0, "read_cr0" },
3201 { SVM_EXIT_READ_CR3, "read_cr3" },
3202 { SVM_EXIT_READ_CR4, "read_cr4" },
3203 { SVM_EXIT_READ_CR8, "read_cr8" },
3204 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3205 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3206 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3207 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3208 { SVM_EXIT_READ_DR0, "read_dr0" },
3209 { SVM_EXIT_READ_DR1, "read_dr1" },
3210 { SVM_EXIT_READ_DR2, "read_dr2" },
3211 { SVM_EXIT_READ_DR3, "read_dr3" },
3212 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3213 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3214 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3215 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3216 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3217 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3218 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3219 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3220 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3221 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3222 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3223 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3224 { SVM_EXIT_INTR, "interrupt" },
3225 { SVM_EXIT_NMI, "nmi" },
3226 { SVM_EXIT_SMI, "smi" },
3227 { SVM_EXIT_INIT, "init" },
3228 { SVM_EXIT_VINTR, "vintr" },
3229 { SVM_EXIT_CPUID, "cpuid" },
3230 { SVM_EXIT_INVD, "invd" },
3231 { SVM_EXIT_HLT, "hlt" },
3232 { SVM_EXIT_INVLPG, "invlpg" },
3233 { SVM_EXIT_INVLPGA, "invlpga" },
3234 { SVM_EXIT_IOIO, "io" },
3235 { SVM_EXIT_MSR, "msr" },
3236 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3237 { SVM_EXIT_SHUTDOWN, "shutdown" },
3238 { SVM_EXIT_VMRUN, "vmrun" },
3239 { SVM_EXIT_VMMCALL, "hypercall" },
3240 { SVM_EXIT_VMLOAD, "vmload" },
3241 { SVM_EXIT_VMSAVE, "vmsave" },
3242 { SVM_EXIT_STGI, "stgi" },
3243 { SVM_EXIT_CLGI, "clgi" },
3244 { SVM_EXIT_SKINIT, "skinit" },
3245 { SVM_EXIT_WBINVD, "wbinvd" },
3246 { SVM_EXIT_MONITOR, "monitor" },
3247 { SVM_EXIT_MWAIT, "mwait" },
3248 { SVM_EXIT_NPF, "npf" },
3249 { -1, NULL }
3250};
3251
17cc3935 3252static int svm_get_lpage_level(void)
344f414f 3253{
17cc3935 3254 return PT_PDPE_LEVEL;
344f414f
JR		 3255}
3256
4e47c7a6
SY		 3257static bool svm_rdtscp_supported(void)
3258{
3259 return false;
3260}
3261
02daab21
AK		 3262static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3263{
3264 struct vcpu_svm *svm = to_svm(vcpu);
3265
02daab21 3266 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3267 if (is_nested(svm))
3268 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3269 update_cr0_intercept(svm);
02daab21
AK		 3270}
3271
cbdd1bea 3272static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3273 .cpu_has_kvm_support = has_svm,
3274 .disabled_by_bios = is_disabled,
3275 .hardware_setup = svm_hardware_setup,
3276 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3277 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3278 .hardware_enable = svm_hardware_enable,
3279 .hardware_disable = svm_hardware_disable,
774ead3a 3280 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3281
3282 .vcpu_create = svm_create_vcpu,
3283 .vcpu_free = svm_free_vcpu,
04d2cc77 3284 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3285
04d2cc77 3286 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3287 .vcpu_load = svm_vcpu_load,
3288 .vcpu_put = svm_vcpu_put,
3289
3290 .set_guest_debug = svm_guest_debug,
3291 .get_msr = svm_get_msr,
3292 .set_msr = svm_set_msr,
3293 .get_segment_base = svm_get_segment_base,
3294 .get_segment = svm_get_segment,
3295 .set_segment = svm_set_segment,
2e4d2653 3296 .get_cpl = svm_get_cpl,
1747fb71 3297 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3298 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3299 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3300 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3301 .set_cr3 = svm_set_cr3,
3302 .set_cr4 = svm_set_cr4,
3303 .set_efer = svm_set_efer,
3304 .get_idt = svm_get_idt,
3305 .set_idt = svm_set_idt,
3306 .get_gdt = svm_get_gdt,
3307 .set_gdt = svm_set_gdt,
3308 .get_dr = svm_get_dr,
3309 .set_dr = svm_set_dr,
6de4f3ad 3310 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3311 .get_rflags = svm_get_rflags,
3312 .set_rflags = svm_set_rflags,
6b52d186 3313 .fpu_activate = svm_fpu_activate,
02daab21 3314 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3315
6aa8b732 3316 .tlb_flush = svm_flush_tlb,
6aa8b732 3317
6aa8b732 3318 .run = svm_vcpu_run,
04d2cc77 3319 .handle_exit = handle_exit,
6aa8b732 3320 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3321 .set_interrupt_shadow = svm_set_interrupt_shadow,
3322 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3323 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3324 .set_irq = svm_set_irq,
95ba8273 3325 .set_nmi = svm_inject_nmi,
298101da 3326 .queue_exception = svm_queue_exception,
78646121 3327 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3328 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3329 .get_nmi_mask = svm_get_nmi_mask,
3330 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3331 .enable_nmi_window = enable_nmi_window,
3332 .enable_irq_window = enable_irq_window,
3333 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3334
3335 .set_tss_addr = svm_set_tss_addr,
67253af5 3336 .get_tdp_level = get_npt_level,
4b12f0de 3337 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3338
3339 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3340 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3341
3342 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3343
3344 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3345};
3346
3347static int __init svm_init(void)
3348{
cb498ea2 3349 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3350 THIS_MODULE);
6aa8b732
AK		 3351}
3352
3353static void __exit svm_exit(void)
3354{
cb498ea2 3355 kvm_exit();
6aa8b732
AK		 3356}
3357
3358module_init(svm_init)
3359module_exit(svm_exit)
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