]>
Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
e495606d | 22 | |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/vmalloc.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
6aa8b732 | 28 | |
e495606d | 29 | #include <asm/desc.h> |
6aa8b732 | 30 | |
63d1142f EH |
31 | #include <asm/virtext.h> |
32 | ||
4ecac3fd AK |
33 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
34 | ||
6aa8b732 AK |
35 | MODULE_AUTHOR("Qumranet"); |
36 | MODULE_LICENSE("GPL"); | |
37 | ||
38 | #define IOPM_ALLOC_ORDER 2 | |
39 | #define MSRPM_ALLOC_ORDER 1 | |
40 | ||
6aa8b732 AK |
41 | #define DR7_GD_MASK (1 << 13) |
42 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
43 | |
44 | #define SEG_TYPE_LDT 2 | |
45 | #define SEG_TYPE_BUSY_TSS16 3 | |
46 | ||
80b7706e JR |
47 | #define SVM_FEATURE_NPT (1 << 0) |
48 | #define SVM_FEATURE_LBRV (1 << 1) | |
94c935a1 | 49 | #define SVM_FEATURE_SVML (1 << 2) |
80b7706e | 50 | |
24e09cbf JR |
51 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
52 | ||
c0725420 AG |
53 | /* Turn on to get debugging output*/ |
54 | /* #define NESTED_DEBUG */ | |
55 | ||
56 | #ifdef NESTED_DEBUG | |
57 | #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args) | |
58 | #else | |
59 | #define nsvm_printk(fmt, args...) do {} while(0) | |
60 | #endif | |
61 | ||
709ddebf JR |
62 | /* enable NPT for AMD64 and X86 with PAE */ |
63 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
64 | static bool npt_enabled = true; | |
65 | #else | |
e3da3acd | 66 | static bool npt_enabled = false; |
709ddebf | 67 | #endif |
6c7dac72 JR |
68 | static int npt = 1; |
69 | ||
70 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 71 | |
04d2cc77 | 72 | static void kvm_reput_irq(struct vcpu_svm *svm); |
44874f84 | 73 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
04d2cc77 | 74 | |
cf74a78b AG |
75 | static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override); |
76 | static int nested_svm_vmexit(struct vcpu_svm *svm); | |
77 | static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb, | |
78 | void *arg2, void *opaque); | |
79 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, | |
80 | bool has_error_code, u32 error_code); | |
81 | ||
a2fa3e9f GH |
82 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
83 | { | |
fb3f0f51 | 84 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
85 | } |
86 | ||
3d6368ef AG |
87 | static inline bool is_nested(struct vcpu_svm *svm) |
88 | { | |
89 | return svm->nested_vmcb; | |
90 | } | |
91 | ||
4866d5e3 | 92 | static unsigned long iopm_base; |
6aa8b732 AK |
93 | |
94 | struct kvm_ldttss_desc { | |
95 | u16 limit0; | |
96 | u16 base0; | |
97 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
98 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
99 | u32 base3; | |
100 | u32 zero1; | |
101 | } __attribute__((packed)); | |
102 | ||
103 | struct svm_cpu_data { | |
104 | int cpu; | |
105 | ||
5008fdf5 AK |
106 | u64 asid_generation; |
107 | u32 max_asid; | |
108 | u32 next_asid; | |
6aa8b732 AK |
109 | struct kvm_ldttss_desc *tss_desc; |
110 | ||
111 | struct page *save_area; | |
112 | }; | |
113 | ||
114 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 115 | static uint32_t svm_features; |
6aa8b732 AK |
116 | |
117 | struct svm_init_data { | |
118 | int cpu; | |
119 | int r; | |
120 | }; | |
121 | ||
122 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
123 | ||
9d8f549d | 124 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
125 | #define MSRS_RANGE_SIZE 2048 |
126 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
127 | ||
128 | #define MAX_INST_SIZE 15 | |
129 | ||
80b7706e JR |
130 | static inline u32 svm_has(u32 feat) |
131 | { | |
132 | return svm_features & feat; | |
133 | } | |
134 | ||
6aa8b732 AK |
135 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
136 | { | |
ad312c7c ZX |
137 | int word_index = __ffs(vcpu->arch.irq_summary); |
138 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
139 | int irq = word_index * BITS_PER_LONG + bit_index; |
140 | ||
ad312c7c ZX |
141 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
142 | if (!vcpu->arch.irq_pending[word_index]) | |
143 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
144 | return irq; |
145 | } | |
146 | ||
147 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
148 | { | |
ad312c7c ZX |
149 | set_bit(irq, vcpu->arch.irq_pending); |
150 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
151 | } |
152 | ||
153 | static inline void clgi(void) | |
154 | { | |
4ecac3fd | 155 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
156 | } |
157 | ||
158 | static inline void stgi(void) | |
159 | { | |
4ecac3fd | 160 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
161 | } |
162 | ||
163 | static inline void invlpga(unsigned long addr, u32 asid) | |
164 | { | |
4ecac3fd | 165 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
166 | } |
167 | ||
168 | static inline unsigned long kvm_read_cr2(void) | |
169 | { | |
170 | unsigned long cr2; | |
171 | ||
172 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
173 | return cr2; | |
174 | } | |
175 | ||
176 | static inline void kvm_write_cr2(unsigned long val) | |
177 | { | |
178 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
179 | } | |
180 | ||
181 | static inline unsigned long read_dr6(void) | |
182 | { | |
183 | unsigned long dr6; | |
184 | ||
185 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
186 | return dr6; | |
187 | } | |
188 | ||
189 | static inline void write_dr6(unsigned long val) | |
190 | { | |
191 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
192 | } | |
193 | ||
194 | static inline unsigned long read_dr7(void) | |
195 | { | |
196 | unsigned long dr7; | |
197 | ||
198 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
199 | return dr7; | |
200 | } | |
201 | ||
202 | static inline void write_dr7(unsigned long val) | |
203 | { | |
204 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
205 | } | |
206 | ||
6aa8b732 AK |
207 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
208 | { | |
a2fa3e9f | 209 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
210 | } |
211 | ||
212 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
213 | { | |
214 | force_new_asid(vcpu); | |
215 | } | |
216 | ||
217 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
218 | { | |
709ddebf | 219 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 220 | efer &= ~EFER_LME; |
6aa8b732 | 221 | |
9962d032 | 222 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
ad312c7c | 223 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
224 | } |
225 | ||
298101da AK |
226 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
227 | bool has_error_code, u32 error_code) | |
228 | { | |
229 | struct vcpu_svm *svm = to_svm(vcpu); | |
230 | ||
cf74a78b AG |
231 | /* If we are within a nested VM we'd better #VMEXIT and let the |
232 | guest handle the exception */ | |
233 | if (nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
234 | return; | |
235 | ||
298101da AK |
236 | svm->vmcb->control.event_inj = nr |
237 | | SVM_EVTINJ_VALID | |
238 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
239 | | SVM_EVTINJ_TYPE_EXEPT; | |
240 | svm->vmcb->control.event_inj_err = error_code; | |
241 | } | |
242 | ||
243 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
244 | { | |
245 | struct vcpu_svm *svm = to_svm(vcpu); | |
246 | ||
247 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
248 | } | |
249 | ||
6aa8b732 AK |
250 | static int is_external_interrupt(u32 info) |
251 | { | |
252 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
253 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
254 | } | |
255 | ||
256 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
257 | { | |
a2fa3e9f GH |
258 | struct vcpu_svm *svm = to_svm(vcpu); |
259 | ||
260 | if (!svm->next_rip) { | |
b8688d51 | 261 | printk(KERN_DEBUG "%s: NOP\n", __func__); |
6aa8b732 AK |
262 | return; |
263 | } | |
5fdbf976 MT |
264 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
265 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
266 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 267 | |
5fdbf976 | 268 | kvm_rip_write(vcpu, svm->next_rip); |
a2fa3e9f | 269 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 270 | |
1371d904 | 271 | vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK); |
6aa8b732 AK |
272 | } |
273 | ||
274 | static int has_svm(void) | |
275 | { | |
63d1142f | 276 | const char *msg; |
6aa8b732 | 277 | |
63d1142f EH |
278 | if (!cpu_has_svm(&msg)) { |
279 | printk(KERN_INFO "has_svn: %s\n", msg); | |
6aa8b732 AK |
280 | return 0; |
281 | } | |
282 | ||
6aa8b732 AK |
283 | return 1; |
284 | } | |
285 | ||
286 | static void svm_hardware_disable(void *garbage) | |
287 | { | |
2c8dceeb | 288 | cpu_svm_disable(); |
6aa8b732 AK |
289 | } |
290 | ||
291 | static void svm_hardware_enable(void *garbage) | |
292 | { | |
293 | ||
294 | struct svm_cpu_data *svm_data; | |
295 | uint64_t efer; | |
6aa8b732 | 296 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
297 | struct desc_struct *gdt; |
298 | int me = raw_smp_processor_id(); | |
299 | ||
300 | if (!has_svm()) { | |
301 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
302 | return; | |
303 | } | |
304 | svm_data = per_cpu(svm_data, me); | |
305 | ||
306 | if (!svm_data) { | |
307 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
308 | me); | |
309 | return; | |
310 | } | |
311 | ||
312 | svm_data->asid_generation = 1; | |
313 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
314 | svm_data->next_asid = svm_data->max_asid + 1; | |
315 | ||
d77c26fc | 316 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
317 | gdt = (struct desc_struct *)gdt_descr.address; |
318 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
319 | ||
320 | rdmsrl(MSR_EFER, efer); | |
9962d032 | 321 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 AK |
322 | |
323 | wrmsrl(MSR_VM_HSAVE_PA, | |
324 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
325 | } | |
326 | ||
0da1db75 JR |
327 | static void svm_cpu_uninit(int cpu) |
328 | { | |
329 | struct svm_cpu_data *svm_data | |
330 | = per_cpu(svm_data, raw_smp_processor_id()); | |
331 | ||
332 | if (!svm_data) | |
333 | return; | |
334 | ||
335 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
336 | __free_page(svm_data->save_area); | |
337 | kfree(svm_data); | |
338 | } | |
339 | ||
6aa8b732 AK |
340 | static int svm_cpu_init(int cpu) |
341 | { | |
342 | struct svm_cpu_data *svm_data; | |
343 | int r; | |
344 | ||
345 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
346 | if (!svm_data) | |
347 | return -ENOMEM; | |
348 | svm_data->cpu = cpu; | |
349 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
350 | r = -ENOMEM; | |
351 | if (!svm_data->save_area) | |
352 | goto err_1; | |
353 | ||
354 | per_cpu(svm_data, cpu) = svm_data; | |
355 | ||
356 | return 0; | |
357 | ||
358 | err_1: | |
359 | kfree(svm_data); | |
360 | return r; | |
361 | ||
362 | } | |
363 | ||
bfc733a7 RR |
364 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
365 | int read, int write) | |
6aa8b732 AK |
366 | { |
367 | int i; | |
368 | ||
369 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
370 | if (msr >= msrpm_ranges[i] && | |
371 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
372 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
373 | msrpm_ranges[i]) * 2; | |
374 | ||
375 | u32 *base = msrpm + (msr_offset / 32); | |
376 | u32 msr_shift = msr_offset % 32; | |
377 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
378 | *base = (*base & ~(0x3 << msr_shift)) | | |
379 | (mask << msr_shift); | |
bfc733a7 | 380 | return; |
6aa8b732 AK |
381 | } |
382 | } | |
bfc733a7 | 383 | BUG(); |
6aa8b732 AK |
384 | } |
385 | ||
f65c229c JR |
386 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
387 | { | |
388 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
389 | ||
390 | #ifdef CONFIG_X86_64 | |
391 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
392 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
393 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
394 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
395 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
396 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
397 | #endif | |
398 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
399 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
400 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); | |
401 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); | |
402 | } | |
403 | ||
24e09cbf JR |
404 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
405 | { | |
406 | u32 *msrpm = svm->msrpm; | |
407 | ||
408 | svm->vmcb->control.lbr_ctl = 1; | |
409 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
410 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
411 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
412 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
413 | } | |
414 | ||
415 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
416 | { | |
417 | u32 *msrpm = svm->msrpm; | |
418 | ||
419 | svm->vmcb->control.lbr_ctl = 0; | |
420 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
421 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
422 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
423 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
424 | } | |
425 | ||
6aa8b732 AK |
426 | static __init int svm_hardware_setup(void) |
427 | { | |
428 | int cpu; | |
429 | struct page *iopm_pages; | |
f65c229c | 430 | void *iopm_va; |
6aa8b732 AK |
431 | int r; |
432 | ||
6aa8b732 AK |
433 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
434 | ||
435 | if (!iopm_pages) | |
436 | return -ENOMEM; | |
c8681339 AL |
437 | |
438 | iopm_va = page_address(iopm_pages); | |
439 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
440 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
441 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
442 | ||
50a37eb4 JR |
443 | if (boot_cpu_has(X86_FEATURE_NX)) |
444 | kvm_enable_efer_bits(EFER_NX); | |
445 | ||
6aa8b732 AK |
446 | for_each_online_cpu(cpu) { |
447 | r = svm_cpu_init(cpu); | |
448 | if (r) | |
f65c229c | 449 | goto err; |
6aa8b732 | 450 | } |
33bd6a0b JR |
451 | |
452 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
453 | ||
e3da3acd JR |
454 | if (!svm_has(SVM_FEATURE_NPT)) |
455 | npt_enabled = false; | |
456 | ||
6c7dac72 JR |
457 | if (npt_enabled && !npt) { |
458 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
459 | npt_enabled = false; | |
460 | } | |
461 | ||
18552672 | 462 | if (npt_enabled) { |
e3da3acd | 463 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 464 | kvm_enable_tdp(); |
5f4cb662 JR |
465 | } else |
466 | kvm_disable_tdp(); | |
e3da3acd | 467 | |
6aa8b732 AK |
468 | return 0; |
469 | ||
f65c229c | 470 | err: |
6aa8b732 AK |
471 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
472 | iopm_base = 0; | |
473 | return r; | |
474 | } | |
475 | ||
476 | static __exit void svm_hardware_unsetup(void) | |
477 | { | |
0da1db75 JR |
478 | int cpu; |
479 | ||
480 | for_each_online_cpu(cpu) | |
481 | svm_cpu_uninit(cpu); | |
482 | ||
6aa8b732 | 483 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 484 | iopm_base = 0; |
6aa8b732 AK |
485 | } |
486 | ||
487 | static void init_seg(struct vmcb_seg *seg) | |
488 | { | |
489 | seg->selector = 0; | |
490 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
491 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
492 | seg->limit = 0xffff; | |
493 | seg->base = 0; | |
494 | } | |
495 | ||
496 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
497 | { | |
498 | seg->selector = 0; | |
499 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
500 | seg->limit = 0xffff; | |
501 | seg->base = 0; | |
502 | } | |
503 | ||
e6101a96 | 504 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 505 | { |
e6101a96 JR |
506 | struct vmcb_control_area *control = &svm->vmcb->control; |
507 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
508 | |
509 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
510 | INTERCEPT_CR3_MASK | | |
649d6864 | 511 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
512 | |
513 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
514 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
515 | INTERCEPT_CR4_MASK | |
516 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
517 | |
518 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
519 | INTERCEPT_DR1_MASK | | |
520 | INTERCEPT_DR2_MASK | | |
521 | INTERCEPT_DR3_MASK; | |
522 | ||
523 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
524 | INTERCEPT_DR1_MASK | | |
525 | INTERCEPT_DR2_MASK | | |
526 | INTERCEPT_DR3_MASK | | |
527 | INTERCEPT_DR5_MASK | | |
528 | INTERCEPT_DR7_MASK; | |
529 | ||
7aa81cc0 | 530 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
531 | (1 << UD_VECTOR) | |
532 | (1 << MC_VECTOR); | |
6aa8b732 AK |
533 | |
534 | ||
535 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
536 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 537 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 | 538 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 539 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 540 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 541 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
542 | (1ULL << INTERCEPT_INVLPGA) | |
543 | (1ULL << INTERCEPT_IOIO_PROT) | | |
544 | (1ULL << INTERCEPT_MSR_PROT) | | |
545 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 546 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
547 | (1ULL << INTERCEPT_VMRUN) | |
548 | (1ULL << INTERCEPT_VMMCALL) | | |
549 | (1ULL << INTERCEPT_VMLOAD) | | |
550 | (1ULL << INTERCEPT_VMSAVE) | | |
551 | (1ULL << INTERCEPT_STGI) | | |
552 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 553 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 554 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
555 | (1ULL << INTERCEPT_MONITOR) | |
556 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
557 | |
558 | control->iopm_base_pa = iopm_base; | |
f65c229c | 559 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 560 | control->tsc_offset = 0; |
6aa8b732 AK |
561 | control->int_ctl = V_INTR_MASKING_MASK; |
562 | ||
563 | init_seg(&save->es); | |
564 | init_seg(&save->ss); | |
565 | init_seg(&save->ds); | |
566 | init_seg(&save->fs); | |
567 | init_seg(&save->gs); | |
568 | ||
569 | save->cs.selector = 0xf000; | |
570 | /* Executable/Readable Code Segment */ | |
571 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
572 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
573 | save->cs.limit = 0xffff; | |
d92899a0 AK |
574 | /* |
575 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
576 | * be consistent with it. | |
577 | * | |
578 | * Replace when we have real mode working for vmx. | |
579 | */ | |
580 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
581 | |
582 | save->gdtr.limit = 0xffff; | |
583 | save->idtr.limit = 0xffff; | |
584 | ||
585 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
586 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
587 | ||
9962d032 | 588 | save->efer = EFER_SVME; |
d77c26fc | 589 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
590 | save->dr7 = 0x400; |
591 | save->rflags = 2; | |
592 | save->rip = 0x0000fff0; | |
5fdbf976 | 593 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 AK |
594 | |
595 | /* | |
596 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
597 | * cache by default. the orderly way is to enable cache in bios. | |
598 | */ | |
707d92fa | 599 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 600 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 601 | /* rdx = ?? */ |
709ddebf JR |
602 | |
603 | if (npt_enabled) { | |
604 | /* Setup VMCB for Nested Paging */ | |
605 | control->nested_ctl = 1; | |
a7052897 MT |
606 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
607 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf JR |
608 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
609 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
610 | INTERCEPT_CR3_MASK); | |
611 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
612 | INTERCEPT_CR3_MASK); | |
613 | save->g_pat = 0x0007040600070406ULL; | |
614 | /* enable caching because the QEMU Bios doesn't enable it */ | |
615 | save->cr0 = X86_CR0_ET; | |
616 | save->cr3 = 0; | |
617 | save->cr4 = 0; | |
618 | } | |
a79d2f18 | 619 | force_new_asid(&svm->vcpu); |
1371d904 | 620 | |
3d6368ef | 621 | svm->nested_vmcb = 0; |
1371d904 | 622 | svm->vcpu.arch.hflags = HF_GIF_MASK; |
6aa8b732 AK |
623 | } |
624 | ||
e00c8cf2 | 625 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
626 | { |
627 | struct vcpu_svm *svm = to_svm(vcpu); | |
628 | ||
e6101a96 | 629 | init_vmcb(svm); |
70433389 AK |
630 | |
631 | if (vcpu->vcpu_id != 0) { | |
5fdbf976 | 632 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
633 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
634 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 635 | } |
5fdbf976 MT |
636 | vcpu->arch.regs_avail = ~0; |
637 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
638 | |
639 | return 0; | |
04d2cc77 AK |
640 | } |
641 | ||
fb3f0f51 | 642 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 643 | { |
a2fa3e9f | 644 | struct vcpu_svm *svm; |
6aa8b732 | 645 | struct page *page; |
f65c229c | 646 | struct page *msrpm_pages; |
b286d5d8 | 647 | struct page *hsave_page; |
3d6368ef | 648 | struct page *nested_msrpm_pages; |
fb3f0f51 | 649 | int err; |
6aa8b732 | 650 | |
c16f862d | 651 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
652 | if (!svm) { |
653 | err = -ENOMEM; | |
654 | goto out; | |
655 | } | |
656 | ||
657 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
658 | if (err) | |
659 | goto free_svm; | |
660 | ||
6aa8b732 | 661 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
662 | if (!page) { |
663 | err = -ENOMEM; | |
664 | goto uninit; | |
665 | } | |
6aa8b732 | 666 | |
f65c229c JR |
667 | err = -ENOMEM; |
668 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
669 | if (!msrpm_pages) | |
670 | goto uninit; | |
3d6368ef AG |
671 | |
672 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
673 | if (!nested_msrpm_pages) | |
674 | goto uninit; | |
675 | ||
f65c229c JR |
676 | svm->msrpm = page_address(msrpm_pages); |
677 | svm_vcpu_init_msrpm(svm->msrpm); | |
678 | ||
b286d5d8 AG |
679 | hsave_page = alloc_page(GFP_KERNEL); |
680 | if (!hsave_page) | |
681 | goto uninit; | |
682 | svm->hsave = page_address(hsave_page); | |
683 | ||
3d6368ef AG |
684 | svm->nested_msrpm = page_address(nested_msrpm_pages); |
685 | ||
a2fa3e9f GH |
686 | svm->vmcb = page_address(page); |
687 | clear_page(svm->vmcb); | |
688 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
689 | svm->asid_generation = 0; | |
690 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
e6101a96 | 691 | init_vmcb(svm); |
a2fa3e9f | 692 | |
fb3f0f51 RR |
693 | fx_init(&svm->vcpu); |
694 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 695 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 696 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 697 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 698 | |
fb3f0f51 | 699 | return &svm->vcpu; |
36241b8c | 700 | |
fb3f0f51 RR |
701 | uninit: |
702 | kvm_vcpu_uninit(&svm->vcpu); | |
703 | free_svm: | |
a4770347 | 704 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
705 | out: |
706 | return ERR_PTR(err); | |
6aa8b732 AK |
707 | } |
708 | ||
709 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
710 | { | |
a2fa3e9f GH |
711 | struct vcpu_svm *svm = to_svm(vcpu); |
712 | ||
fb3f0f51 | 713 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 714 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
b286d5d8 | 715 | __free_page(virt_to_page(svm->hsave)); |
3d6368ef | 716 | __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER); |
fb3f0f51 | 717 | kvm_vcpu_uninit(vcpu); |
a4770347 | 718 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
719 | } |
720 | ||
15ad7146 | 721 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 722 | { |
a2fa3e9f | 723 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 724 | int i; |
0cc5064d | 725 | |
0cc5064d AK |
726 | if (unlikely(cpu != vcpu->cpu)) { |
727 | u64 tsc_this, delta; | |
728 | ||
729 | /* | |
730 | * Make sure that the guest sees a monotonically | |
731 | * increasing TSC. | |
732 | */ | |
733 | rdtscll(tsc_this); | |
ad312c7c | 734 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 735 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 736 | vcpu->cpu = cpu; |
2f599714 | 737 | kvm_migrate_timers(vcpu); |
0cc5064d | 738 | } |
94dfbdb3 AL |
739 | |
740 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 741 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
742 | } |
743 | ||
744 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
745 | { | |
a2fa3e9f | 746 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
747 | int i; |
748 | ||
e1beb1d3 | 749 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 750 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 751 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 752 | |
ad312c7c | 753 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
754 | } |
755 | ||
6aa8b732 AK |
756 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
757 | { | |
a2fa3e9f | 758 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
759 | } |
760 | ||
761 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
762 | { | |
a2fa3e9f | 763 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
764 | } |
765 | ||
f0b85051 AG |
766 | static void svm_set_vintr(struct vcpu_svm *svm) |
767 | { | |
768 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
769 | } | |
770 | ||
771 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
772 | { | |
773 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
774 | } | |
775 | ||
6aa8b732 AK |
776 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
777 | { | |
a2fa3e9f | 778 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
779 | |
780 | switch (seg) { | |
781 | case VCPU_SREG_CS: return &save->cs; | |
782 | case VCPU_SREG_DS: return &save->ds; | |
783 | case VCPU_SREG_ES: return &save->es; | |
784 | case VCPU_SREG_FS: return &save->fs; | |
785 | case VCPU_SREG_GS: return &save->gs; | |
786 | case VCPU_SREG_SS: return &save->ss; | |
787 | case VCPU_SREG_TR: return &save->tr; | |
788 | case VCPU_SREG_LDTR: return &save->ldtr; | |
789 | } | |
790 | BUG(); | |
8b6d44c7 | 791 | return NULL; |
6aa8b732 AK |
792 | } |
793 | ||
794 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
795 | { | |
796 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
797 | ||
798 | return s->base; | |
799 | } | |
800 | ||
801 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
802 | struct kvm_segment *var, int seg) | |
803 | { | |
804 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
805 | ||
806 | var->base = s->base; | |
807 | var->limit = s->limit; | |
808 | var->selector = s->selector; | |
809 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
810 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
811 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
812 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
813 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
814 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
815 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
816 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc AS |
817 | |
818 | /* | |
819 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
820 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
821 | * Intel's VMENTRY has a check on the 'G' bit. | |
822 | */ | |
823 | if (seg == VCPU_SREG_CS) | |
824 | var->g = s->limit > 0xfffff; | |
825 | ||
c0d09828 AS |
826 | /* |
827 | * Work around a bug where the busy flag in the tr selector | |
828 | * isn't exposed | |
829 | */ | |
830 | if (seg == VCPU_SREG_TR) | |
831 | var->type |= 0x2; | |
832 | ||
6aa8b732 AK |
833 | var->unusable = !var->present; |
834 | } | |
835 | ||
2e4d2653 IE |
836 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
837 | { | |
838 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
839 | ||
840 | return save->cpl; | |
841 | } | |
842 | ||
6aa8b732 AK |
843 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
844 | { | |
a2fa3e9f GH |
845 | struct vcpu_svm *svm = to_svm(vcpu); |
846 | ||
847 | dt->limit = svm->vmcb->save.idtr.limit; | |
848 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
849 | } |
850 | ||
851 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
852 | { | |
a2fa3e9f GH |
853 | struct vcpu_svm *svm = to_svm(vcpu); |
854 | ||
855 | svm->vmcb->save.idtr.limit = dt->limit; | |
856 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
857 | } |
858 | ||
859 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
860 | { | |
a2fa3e9f GH |
861 | struct vcpu_svm *svm = to_svm(vcpu); |
862 | ||
863 | dt->limit = svm->vmcb->save.gdtr.limit; | |
864 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
865 | } |
866 | ||
867 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
868 | { | |
a2fa3e9f GH |
869 | struct vcpu_svm *svm = to_svm(vcpu); |
870 | ||
871 | svm->vmcb->save.gdtr.limit = dt->limit; | |
872 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
873 | } |
874 | ||
25c4c276 | 875 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
876 | { |
877 | } | |
878 | ||
6aa8b732 AK |
879 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
880 | { | |
a2fa3e9f GH |
881 | struct vcpu_svm *svm = to_svm(vcpu); |
882 | ||
05b3e0c2 | 883 | #ifdef CONFIG_X86_64 |
ad312c7c | 884 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 885 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 886 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 887 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
888 | } |
889 | ||
d77c26fc | 890 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 891 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 892 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
893 | } |
894 | } | |
895 | #endif | |
709ddebf JR |
896 | if (npt_enabled) |
897 | goto set; | |
898 | ||
ad312c7c | 899 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 900 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
901 | vcpu->fpu_active = 1; |
902 | } | |
903 | ||
ad312c7c | 904 | vcpu->arch.cr0 = cr0; |
707d92fa | 905 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
906 | if (!vcpu->fpu_active) { |
907 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 908 | cr0 |= X86_CR0_TS; |
6b390b63 | 909 | } |
709ddebf JR |
910 | set: |
911 | /* | |
912 | * re-enable caching here because the QEMU bios | |
913 | * does not do it - this results in some delay at | |
914 | * reboot | |
915 | */ | |
916 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 917 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
918 | } |
919 | ||
920 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
921 | { | |
6394b649 | 922 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
923 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
924 | ||
925 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
926 | force_new_asid(vcpu); | |
6394b649 | 927 | |
ec077263 JR |
928 | vcpu->arch.cr4 = cr4; |
929 | if (!npt_enabled) | |
930 | cr4 |= X86_CR4_PAE; | |
6394b649 | 931 | cr4 |= host_cr4_mce; |
ec077263 | 932 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
933 | } |
934 | ||
935 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
936 | struct kvm_segment *var, int seg) | |
937 | { | |
a2fa3e9f | 938 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
939 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
940 | ||
941 | s->base = var->base; | |
942 | s->limit = var->limit; | |
943 | s->selector = var->selector; | |
944 | if (var->unusable) | |
945 | s->attrib = 0; | |
946 | else { | |
947 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
948 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
949 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
950 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
951 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
952 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
953 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
954 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
955 | } | |
956 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
957 | svm->vmcb->save.cpl |
958 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
959 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
960 | ||
961 | } | |
962 | ||
6aa8b732 AK |
963 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) |
964 | { | |
965 | return -EOPNOTSUPP; | |
966 | } | |
967 | ||
2a8067f1 ED |
968 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
969 | { | |
970 | struct vcpu_svm *svm = to_svm(vcpu); | |
971 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
972 | ||
973 | if (is_external_interrupt(exit_int_info)) | |
974 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
975 | return -1; | |
976 | } | |
977 | ||
6aa8b732 AK |
978 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
979 | { | |
94dfbdb3 | 980 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 981 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 982 | #endif |
6aa8b732 AK |
983 | } |
984 | ||
985 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
986 | { | |
94dfbdb3 | 987 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 988 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 989 | #endif |
6aa8b732 AK |
990 | } |
991 | ||
e756fc62 | 992 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
993 | { |
994 | if (svm_data->next_asid > svm_data->max_asid) { | |
995 | ++svm_data->asid_generation; | |
996 | svm_data->next_asid = 1; | |
a2fa3e9f | 997 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
998 | } |
999 | ||
e756fc62 | 1000 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
1001 | svm->asid_generation = svm_data->asid_generation; |
1002 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
1003 | } |
1004 | ||
6aa8b732 AK |
1005 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
1006 | { | |
af9ca2d7 JR |
1007 | unsigned long val = to_svm(vcpu)->db_regs[dr]; |
1008 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); | |
1009 | return val; | |
6aa8b732 AK |
1010 | } |
1011 | ||
1012 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
1013 | int *exception) | |
1014 | { | |
a2fa3e9f GH |
1015 | struct vcpu_svm *svm = to_svm(vcpu); |
1016 | ||
6aa8b732 AK |
1017 | *exception = 0; |
1018 | ||
a2fa3e9f GH |
1019 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
1020 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
1021 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
1022 | *exception = DB_VECTOR; |
1023 | return; | |
1024 | } | |
1025 | ||
1026 | switch (dr) { | |
1027 | case 0 ... 3: | |
a2fa3e9f | 1028 | svm->db_regs[dr] = value; |
6aa8b732 AK |
1029 | return; |
1030 | case 4 ... 5: | |
ad312c7c | 1031 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
1032 | *exception = UD_VECTOR; |
1033 | return; | |
1034 | } | |
1035 | case 7: { | |
1036 | if (value & ~((1ULL << 32) - 1)) { | |
1037 | *exception = GP_VECTOR; | |
1038 | return; | |
1039 | } | |
a2fa3e9f | 1040 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
1041 | return; |
1042 | } | |
1043 | default: | |
1044 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
b8688d51 | 1045 | __func__, dr); |
6aa8b732 AK |
1046 | *exception = UD_VECTOR; |
1047 | return; | |
1048 | } | |
1049 | } | |
1050 | ||
e756fc62 | 1051 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1052 | { |
a2fa3e9f | 1053 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 1054 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
1055 | u64 fault_address; |
1056 | u32 error_code; | |
577bdc49 | 1057 | bool event_injection = false; |
6aa8b732 | 1058 | |
85f455f7 | 1059 | if (!irqchip_in_kernel(kvm) && |
577bdc49 AK |
1060 | is_external_interrupt(exit_int_info)) { |
1061 | event_injection = true; | |
e756fc62 | 1062 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
577bdc49 | 1063 | } |
6aa8b732 | 1064 | |
a2fa3e9f GH |
1065 | fault_address = svm->vmcb->control.exit_info_2; |
1066 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 JR |
1067 | |
1068 | if (!npt_enabled) | |
1069 | KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code, | |
1070 | (u32)fault_address, (u32)(fault_address >> 32), | |
1071 | handler); | |
d2ebb410 JR |
1072 | else |
1073 | KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code, | |
1074 | (u32)fault_address, (u32)(fault_address >> 32), | |
1075 | handler); | |
44874f84 JR |
1076 | /* |
1077 | * FIXME: Tis shouldn't be necessary here, but there is a flush | |
1078 | * missing in the MMU code. Until we find this bug, flush the | |
1079 | * complete TLB here on an NPF | |
1080 | */ | |
1081 | if (npt_enabled) | |
1082 | svm_flush_tlb(&svm->vcpu); | |
af9ca2d7 | 1083 | |
48d15039 | 1084 | if (!npt_enabled && event_injection) |
577bdc49 | 1085 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); |
3067714c | 1086 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1087 | } |
1088 | ||
7aa81cc0 AL |
1089 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1090 | { | |
1091 | int er; | |
1092 | ||
571008da | 1093 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1094 | if (er != EMULATE_DONE) |
7ee5d940 | 1095 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1096 | return 1; |
1097 | } | |
1098 | ||
e756fc62 | 1099 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 1100 | { |
a2fa3e9f | 1101 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1102 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1103 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1104 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1105 | |
1106 | return 1; | |
7807fa6c AL |
1107 | } |
1108 | ||
53371b50 JR |
1109 | static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1110 | { | |
1111 | /* | |
1112 | * On an #MC intercept the MCE handler is not called automatically in | |
1113 | * the host. So do it by hand here. | |
1114 | */ | |
1115 | asm volatile ( | |
1116 | "int $0x12\n"); | |
1117 | /* not sure if we ever come back to this point */ | |
1118 | ||
1119 | return 1; | |
1120 | } | |
1121 | ||
e756fc62 | 1122 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
1123 | { |
1124 | /* | |
1125 | * VMCB is undefined after a SHUTDOWN intercept | |
1126 | * so reinitialize it. | |
1127 | */ | |
a2fa3e9f | 1128 | clear_page(svm->vmcb); |
e6101a96 | 1129 | init_vmcb(svm); |
46fe4ddd JR |
1130 | |
1131 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1132 | return 0; | |
1133 | } | |
1134 | ||
e756fc62 | 1135 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1136 | { |
d77c26fc | 1137 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1138 | int size, down, in, string, rep; |
1139 | unsigned port; | |
6aa8b732 | 1140 | |
e756fc62 | 1141 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1142 | |
a2fa3e9f | 1143 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1144 | |
e70669ab LV |
1145 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1146 | ||
1147 | if (string) { | |
3427318f LV |
1148 | if (emulate_instruction(&svm->vcpu, |
1149 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1150 | return 0; |
1151 | return 1; | |
1152 | } | |
1153 | ||
039576c0 AK |
1154 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1155 | port = io_info >> 16; | |
1156 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1157 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1158 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1159 | |
e93f36bc | 1160 | skip_emulated_instruction(&svm->vcpu); |
3090dd73 | 1161 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1162 | } |
1163 | ||
c47f098d JR |
1164 | static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1165 | { | |
af9ca2d7 | 1166 | KVMTRACE_0D(NMI, &svm->vcpu, handler); |
c47f098d JR |
1167 | return 1; |
1168 | } | |
1169 | ||
a0698055 JR |
1170 | static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1171 | { | |
1172 | ++svm->vcpu.stat.irq_exits; | |
af9ca2d7 | 1173 | KVMTRACE_0D(INTR, &svm->vcpu, handler); |
a0698055 JR |
1174 | return 1; |
1175 | } | |
1176 | ||
e756fc62 | 1177 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1178 | { |
1179 | return 1; | |
1180 | } | |
1181 | ||
e756fc62 | 1182 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1183 | { |
5fdbf976 | 1184 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1185 | skip_emulated_instruction(&svm->vcpu); |
1186 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1187 | } |
1188 | ||
e756fc62 | 1189 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1190 | { |
5fdbf976 | 1191 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1192 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1193 | kvm_emulate_hypercall(&svm->vcpu); |
1194 | return 1; | |
02e235bc AK |
1195 | } |
1196 | ||
c0725420 AG |
1197 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1198 | { | |
1199 | if (!(svm->vcpu.arch.shadow_efer & EFER_SVME) | |
1200 | || !is_paging(&svm->vcpu)) { | |
1201 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1202 | return 1; | |
1203 | } | |
1204 | ||
1205 | if (svm->vmcb->save.cpl) { | |
1206 | kvm_inject_gp(&svm->vcpu, 0); | |
1207 | return 1; | |
1208 | } | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
cf74a78b AG |
1213 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1214 | bool has_error_code, u32 error_code) | |
1215 | { | |
1216 | if (is_nested(svm)) { | |
1217 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; | |
1218 | svm->vmcb->control.exit_code_hi = 0; | |
1219 | svm->vmcb->control.exit_info_1 = error_code; | |
1220 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1221 | if (nested_svm_exit_handled(svm, false)) { | |
1222 | nsvm_printk("VMexit -> EXCP 0x%x\n", nr); | |
1223 | ||
1224 | nested_svm_vmexit(svm); | |
1225 | return 1; | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | static inline int nested_svm_intr(struct vcpu_svm *svm) | |
1233 | { | |
1234 | if (is_nested(svm)) { | |
1235 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1236 | return 0; | |
1237 | ||
1238 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) | |
1239 | return 0; | |
1240 | ||
1241 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; | |
1242 | ||
1243 | if (nested_svm_exit_handled(svm, false)) { | |
1244 | nsvm_printk("VMexit -> INTR\n"); | |
1245 | nested_svm_vmexit(svm); | |
1246 | return 1; | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
c0725420 AG |
1253 | static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa) |
1254 | { | |
1255 | struct page *page; | |
1256 | ||
1257 | down_read(¤t->mm->mmap_sem); | |
1258 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); | |
1259 | up_read(¤t->mm->mmap_sem); | |
1260 | ||
1261 | if (is_error_page(page)) { | |
1262 | printk(KERN_INFO "%s: could not find page at 0x%llx\n", | |
1263 | __func__, gpa); | |
1264 | kvm_release_page_clean(page); | |
1265 | kvm_inject_gp(&svm->vcpu, 0); | |
1266 | return NULL; | |
1267 | } | |
1268 | return page; | |
1269 | } | |
1270 | ||
1271 | static int nested_svm_do(struct vcpu_svm *svm, | |
1272 | u64 arg1_gpa, u64 arg2_gpa, void *opaque, | |
1273 | int (*handler)(struct vcpu_svm *svm, | |
1274 | void *arg1, | |
1275 | void *arg2, | |
1276 | void *opaque)) | |
1277 | { | |
1278 | struct page *arg1_page; | |
1279 | struct page *arg2_page = NULL; | |
1280 | void *arg1; | |
1281 | void *arg2 = NULL; | |
1282 | int retval; | |
1283 | ||
1284 | arg1_page = nested_svm_get_page(svm, arg1_gpa); | |
1285 | if(arg1_page == NULL) | |
1286 | return 1; | |
1287 | ||
1288 | if (arg2_gpa) { | |
1289 | arg2_page = nested_svm_get_page(svm, arg2_gpa); | |
1290 | if(arg2_page == NULL) { | |
1291 | kvm_release_page_clean(arg1_page); | |
1292 | return 1; | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | arg1 = kmap_atomic(arg1_page, KM_USER0); | |
1297 | if (arg2_gpa) | |
1298 | arg2 = kmap_atomic(arg2_page, KM_USER1); | |
1299 | ||
1300 | retval = handler(svm, arg1, arg2, opaque); | |
1301 | ||
1302 | kunmap_atomic(arg1, KM_USER0); | |
1303 | if (arg2_gpa) | |
1304 | kunmap_atomic(arg2, KM_USER1); | |
1305 | ||
1306 | kvm_release_page_dirty(arg1_page); | |
1307 | if (arg2_gpa) | |
1308 | kvm_release_page_dirty(arg2_page); | |
1309 | ||
1310 | return retval; | |
1311 | } | |
1312 | ||
cf74a78b AG |
1313 | static int nested_svm_exit_handled_real(struct vcpu_svm *svm, |
1314 | void *arg1, | |
1315 | void *arg2, | |
1316 | void *opaque) | |
1317 | { | |
1318 | struct vmcb *nested_vmcb = (struct vmcb *)arg1; | |
1319 | bool kvm_overrides = *(bool *)opaque; | |
1320 | u32 exit_code = svm->vmcb->control.exit_code; | |
1321 | ||
1322 | if (kvm_overrides) { | |
1323 | switch (exit_code) { | |
1324 | case SVM_EXIT_INTR: | |
1325 | case SVM_EXIT_NMI: | |
1326 | return 0; | |
1327 | /* For now we are always handling NPFs when using them */ | |
1328 | case SVM_EXIT_NPF: | |
1329 | if (npt_enabled) | |
1330 | return 0; | |
1331 | break; | |
1332 | /* When we're shadowing, trap PFs */ | |
1333 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: | |
1334 | if (!npt_enabled) | |
1335 | return 0; | |
1336 | break; | |
1337 | default: | |
1338 | break; | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | switch (exit_code) { | |
1343 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { | |
1344 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); | |
1345 | if (nested_vmcb->control.intercept_cr_read & cr_bits) | |
1346 | return 1; | |
1347 | break; | |
1348 | } | |
1349 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: { | |
1350 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0); | |
1351 | if (nested_vmcb->control.intercept_cr_write & cr_bits) | |
1352 | return 1; | |
1353 | break; | |
1354 | } | |
1355 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: { | |
1356 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0); | |
1357 | if (nested_vmcb->control.intercept_dr_read & dr_bits) | |
1358 | return 1; | |
1359 | break; | |
1360 | } | |
1361 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: { | |
1362 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0); | |
1363 | if (nested_vmcb->control.intercept_dr_write & dr_bits) | |
1364 | return 1; | |
1365 | break; | |
1366 | } | |
1367 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1368 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
1369 | if (nested_vmcb->control.intercept_exceptions & excp_bits) | |
1370 | return 1; | |
1371 | break; | |
1372 | } | |
1373 | default: { | |
1374 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
1375 | nsvm_printk("exit code: 0x%x\n", exit_code); | |
1376 | if (nested_vmcb->control.intercept & exit_bits) | |
1377 | return 1; | |
1378 | } | |
1379 | } | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm, | |
1385 | void *arg1, void *arg2, | |
1386 | void *opaque) | |
1387 | { | |
1388 | struct vmcb *nested_vmcb = (struct vmcb *)arg1; | |
1389 | u8 *msrpm = (u8 *)arg2; | |
1390 | u32 t0, t1; | |
1391 | u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; | |
1392 | u32 param = svm->vmcb->control.exit_info_1 & 1; | |
1393 | ||
1394 | if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT))) | |
1395 | return 0; | |
1396 | ||
1397 | switch(msr) { | |
1398 | case 0 ... 0x1fff: | |
1399 | t0 = (msr * 2) % 8; | |
1400 | t1 = msr / 8; | |
1401 | break; | |
1402 | case 0xc0000000 ... 0xc0001fff: | |
1403 | t0 = (8192 + msr - 0xc0000000) * 2; | |
1404 | t1 = (t0 / 8); | |
1405 | t0 %= 8; | |
1406 | break; | |
1407 | case 0xc0010000 ... 0xc0011fff: | |
1408 | t0 = (16384 + msr - 0xc0010000) * 2; | |
1409 | t1 = (t0 / 8); | |
1410 | t0 %= 8; | |
1411 | break; | |
1412 | default: | |
1413 | return 1; | |
1414 | break; | |
1415 | } | |
1416 | if (msrpm[t1] & ((1 << param) << t0)) | |
1417 | return 1; | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override) | |
1423 | { | |
1424 | bool k = kvm_override; | |
1425 | ||
1426 | switch (svm->vmcb->control.exit_code) { | |
1427 | case SVM_EXIT_MSR: | |
1428 | return nested_svm_do(svm, svm->nested_vmcb, | |
1429 | svm->nested_vmcb_msrpm, NULL, | |
1430 | nested_svm_exit_handled_msr); | |
1431 | default: break; | |
1432 | } | |
1433 | ||
1434 | return nested_svm_do(svm, svm->nested_vmcb, 0, &k, | |
1435 | nested_svm_exit_handled_real); | |
1436 | } | |
1437 | ||
1438 | static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1, | |
1439 | void *arg2, void *opaque) | |
1440 | { | |
1441 | struct vmcb *nested_vmcb = (struct vmcb *)arg1; | |
1442 | struct vmcb *hsave = svm->hsave; | |
1443 | u64 nested_save[] = { nested_vmcb->save.cr0, | |
1444 | nested_vmcb->save.cr3, | |
1445 | nested_vmcb->save.cr4, | |
1446 | nested_vmcb->save.efer, | |
1447 | nested_vmcb->control.intercept_cr_read, | |
1448 | nested_vmcb->control.intercept_cr_write, | |
1449 | nested_vmcb->control.intercept_dr_read, | |
1450 | nested_vmcb->control.intercept_dr_write, | |
1451 | nested_vmcb->control.intercept_exceptions, | |
1452 | nested_vmcb->control.intercept, | |
1453 | nested_vmcb->control.msrpm_base_pa, | |
1454 | nested_vmcb->control.iopm_base_pa, | |
1455 | nested_vmcb->control.tsc_offset }; | |
1456 | ||
1457 | /* Give the current vmcb to the guest */ | |
1458 | memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb)); | |
1459 | nested_vmcb->save.cr0 = nested_save[0]; | |
1460 | if (!npt_enabled) | |
1461 | nested_vmcb->save.cr3 = nested_save[1]; | |
1462 | nested_vmcb->save.cr4 = nested_save[2]; | |
1463 | nested_vmcb->save.efer = nested_save[3]; | |
1464 | nested_vmcb->control.intercept_cr_read = nested_save[4]; | |
1465 | nested_vmcb->control.intercept_cr_write = nested_save[5]; | |
1466 | nested_vmcb->control.intercept_dr_read = nested_save[6]; | |
1467 | nested_vmcb->control.intercept_dr_write = nested_save[7]; | |
1468 | nested_vmcb->control.intercept_exceptions = nested_save[8]; | |
1469 | nested_vmcb->control.intercept = nested_save[9]; | |
1470 | nested_vmcb->control.msrpm_base_pa = nested_save[10]; | |
1471 | nested_vmcb->control.iopm_base_pa = nested_save[11]; | |
1472 | nested_vmcb->control.tsc_offset = nested_save[12]; | |
1473 | ||
1474 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
1475 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1476 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
1477 | ||
1478 | if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) && | |
1479 | (nested_vmcb->control.int_vector)) { | |
1480 | nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n", | |
1481 | nested_vmcb->control.int_vector); | |
1482 | } | |
1483 | ||
1484 | /* Restore the original control entries */ | |
1485 | svm->vmcb->control = hsave->control; | |
1486 | ||
1487 | /* Kill any pending exceptions */ | |
1488 | if (svm->vcpu.arch.exception.pending == true) | |
1489 | nsvm_printk("WARNING: Pending Exception\n"); | |
1490 | svm->vcpu.arch.exception.pending = false; | |
1491 | ||
1492 | /* Restore selected save entries */ | |
1493 | svm->vmcb->save.es = hsave->save.es; | |
1494 | svm->vmcb->save.cs = hsave->save.cs; | |
1495 | svm->vmcb->save.ss = hsave->save.ss; | |
1496 | svm->vmcb->save.ds = hsave->save.ds; | |
1497 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
1498 | svm->vmcb->save.idtr = hsave->save.idtr; | |
1499 | svm->vmcb->save.rflags = hsave->save.rflags; | |
1500 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
1501 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
1502 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
1503 | if (npt_enabled) { | |
1504 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
1505 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
1506 | } else { | |
1507 | kvm_set_cr3(&svm->vcpu, hsave->save.cr3); | |
1508 | } | |
1509 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
1510 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
1511 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
1512 | svm->vmcb->save.dr7 = 0; | |
1513 | svm->vmcb->save.cpl = 0; | |
1514 | svm->vmcb->control.exit_int_info = 0; | |
1515 | ||
1516 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
1517 | /* Exit nested SVM mode */ | |
1518 | svm->nested_vmcb = 0; | |
1519 | ||
1520 | return 0; | |
1521 | } | |
1522 | ||
1523 | static int nested_svm_vmexit(struct vcpu_svm *svm) | |
1524 | { | |
1525 | nsvm_printk("VMexit\n"); | |
1526 | if (nested_svm_do(svm, svm->nested_vmcb, 0, | |
1527 | NULL, nested_svm_vmexit_real)) | |
1528 | return 1; | |
1529 | ||
1530 | kvm_mmu_reset_context(&svm->vcpu); | |
1531 | kvm_mmu_load(&svm->vcpu); | |
1532 | ||
1533 | return 0; | |
1534 | } | |
3d6368ef AG |
1535 | |
1536 | static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1, | |
1537 | void *arg2, void *opaque) | |
1538 | { | |
1539 | int i; | |
1540 | u32 *nested_msrpm = (u32*)arg1; | |
1541 | for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++) | |
1542 | svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i]; | |
1543 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm); | |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
1548 | static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1, | |
1549 | void *arg2, void *opaque) | |
1550 | { | |
1551 | struct vmcb *nested_vmcb = (struct vmcb *)arg1; | |
1552 | struct vmcb *hsave = svm->hsave; | |
1553 | ||
1554 | /* nested_vmcb is our indicator if nested SVM is activated */ | |
1555 | svm->nested_vmcb = svm->vmcb->save.rax; | |
1556 | ||
1557 | /* Clear internal status */ | |
1558 | svm->vcpu.arch.exception.pending = false; | |
1559 | ||
1560 | /* Save the old vmcb, so we don't need to pick what we save, but | |
1561 | can restore everything when a VMEXIT occurs */ | |
1562 | memcpy(hsave, svm->vmcb, sizeof(struct vmcb)); | |
1563 | /* We need to remember the original CR3 in the SPT case */ | |
1564 | if (!npt_enabled) | |
1565 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
1566 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
1567 | hsave->save.rip = svm->next_rip; | |
1568 | ||
1569 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
1570 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
1571 | else | |
1572 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
1573 | ||
1574 | /* Load the nested guest state */ | |
1575 | svm->vmcb->save.es = nested_vmcb->save.es; | |
1576 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
1577 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
1578 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
1579 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
1580 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
1581 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
1582 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
1583 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
1584 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
1585 | if (npt_enabled) { | |
1586 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
1587 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
1588 | } else { | |
1589 | kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); | |
1590 | kvm_mmu_reset_context(&svm->vcpu); | |
1591 | } | |
1592 | svm->vmcb->save.cr2 = nested_vmcb->save.cr2; | |
1593 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); | |
1594 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
1595 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
1596 | /* In case we don't even reach vcpu_run, the fields are not updated */ | |
1597 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
1598 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
1599 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
1600 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
1601 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
1602 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
1603 | ||
1604 | /* We don't want a nested guest to be more powerful than the guest, | |
1605 | so all intercepts are ORed */ | |
1606 | svm->vmcb->control.intercept_cr_read |= | |
1607 | nested_vmcb->control.intercept_cr_read; | |
1608 | svm->vmcb->control.intercept_cr_write |= | |
1609 | nested_vmcb->control.intercept_cr_write; | |
1610 | svm->vmcb->control.intercept_dr_read |= | |
1611 | nested_vmcb->control.intercept_dr_read; | |
1612 | svm->vmcb->control.intercept_dr_write |= | |
1613 | nested_vmcb->control.intercept_dr_write; | |
1614 | svm->vmcb->control.intercept_exceptions |= | |
1615 | nested_vmcb->control.intercept_exceptions; | |
1616 | ||
1617 | svm->vmcb->control.intercept |= nested_vmcb->control.intercept; | |
1618 | ||
1619 | svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa; | |
1620 | ||
1621 | force_new_asid(&svm->vcpu); | |
1622 | svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info; | |
1623 | svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err; | |
1624 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; | |
1625 | if (nested_vmcb->control.int_ctl & V_IRQ_MASK) { | |
1626 | nsvm_printk("nSVM Injecting Interrupt: 0x%x\n", | |
1627 | nested_vmcb->control.int_ctl); | |
1628 | } | |
1629 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) | |
1630 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
1631 | else | |
1632 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
1633 | ||
1634 | nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n", | |
1635 | nested_vmcb->control.exit_int_info, | |
1636 | nested_vmcb->control.int_state); | |
1637 | ||
1638 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; | |
1639 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
1640 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
1641 | if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID) | |
1642 | nsvm_printk("Injecting Event: 0x%x\n", | |
1643 | nested_vmcb->control.event_inj); | |
1644 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; | |
1645 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
1646 | ||
1647 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
1648 | ||
1649 | return 0; | |
1650 | } | |
1651 | ||
5542675b AG |
1652 | static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
1653 | { | |
1654 | to_vmcb->save.fs = from_vmcb->save.fs; | |
1655 | to_vmcb->save.gs = from_vmcb->save.gs; | |
1656 | to_vmcb->save.tr = from_vmcb->save.tr; | |
1657 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
1658 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
1659 | to_vmcb->save.star = from_vmcb->save.star; | |
1660 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
1661 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
1662 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
1663 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
1664 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
1665 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
1666 | ||
1667 | return 1; | |
1668 | } | |
1669 | ||
1670 | static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb, | |
1671 | void *arg2, void *opaque) | |
1672 | { | |
1673 | return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb); | |
1674 | } | |
1675 | ||
1676 | static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb, | |
1677 | void *arg2, void *opaque) | |
1678 | { | |
1679 | return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb); | |
1680 | } | |
1681 | ||
1682 | static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) | |
1683 | { | |
1684 | if (nested_svm_check_permissions(svm)) | |
1685 | return 1; | |
1686 | ||
1687 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1688 | skip_emulated_instruction(&svm->vcpu); | |
1689 | ||
1690 | nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload); | |
1691 | ||
1692 | return 1; | |
1693 | } | |
1694 | ||
1695 | static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) | |
1696 | { | |
1697 | if (nested_svm_check_permissions(svm)) | |
1698 | return 1; | |
1699 | ||
1700 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1701 | skip_emulated_instruction(&svm->vcpu); | |
1702 | ||
1703 | nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave); | |
1704 | ||
1705 | return 1; | |
1706 | } | |
1707 | ||
3d6368ef AG |
1708 | static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1709 | { | |
1710 | nsvm_printk("VMrun\n"); | |
1711 | if (nested_svm_check_permissions(svm)) | |
1712 | return 1; | |
1713 | ||
1714 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1715 | skip_emulated_instruction(&svm->vcpu); | |
1716 | ||
1717 | if (nested_svm_do(svm, svm->vmcb->save.rax, 0, | |
1718 | NULL, nested_svm_vmrun)) | |
1719 | return 1; | |
1720 | ||
1721 | if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0, | |
1722 | NULL, nested_svm_vmrun_msrpm)) | |
1723 | return 1; | |
1724 | ||
1725 | return 1; | |
1726 | } | |
1727 | ||
1371d904 AG |
1728 | static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1729 | { | |
1730 | if (nested_svm_check_permissions(svm)) | |
1731 | return 1; | |
1732 | ||
1733 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1734 | skip_emulated_instruction(&svm->vcpu); | |
1735 | ||
1736 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
1737 | ||
1738 | return 1; | |
1739 | } | |
1740 | ||
1741 | static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) | |
1742 | { | |
1743 | if (nested_svm_check_permissions(svm)) | |
1744 | return 1; | |
1745 | ||
1746 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1747 | skip_emulated_instruction(&svm->vcpu); | |
1748 | ||
1749 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
1750 | ||
1751 | /* After a CLGI no interrupts should come */ | |
1752 | svm_clear_vintr(svm); | |
1753 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
1754 | ||
1755 | return 1; | |
1756 | } | |
1757 | ||
e756fc62 RR |
1758 | static int invalid_op_interception(struct vcpu_svm *svm, |
1759 | struct kvm_run *kvm_run) | |
6aa8b732 | 1760 | { |
7ee5d940 | 1761 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1762 | return 1; |
1763 | } | |
1764 | ||
e756fc62 RR |
1765 | static int task_switch_interception(struct vcpu_svm *svm, |
1766 | struct kvm_run *kvm_run) | |
6aa8b732 | 1767 | { |
37817f29 IE |
1768 | u16 tss_selector; |
1769 | ||
1770 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
1771 | if (svm->vmcb->control.exit_info_2 & | |
1772 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
1773 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1774 | TASK_SWITCH_IRET); | |
1775 | if (svm->vmcb->control.exit_info_2 & | |
1776 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
1777 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1778 | TASK_SWITCH_JMP); | |
1779 | return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL); | |
6aa8b732 AK |
1780 | } |
1781 | ||
e756fc62 | 1782 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1783 | { |
5fdbf976 | 1784 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1785 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1786 | return 1; |
6aa8b732 AK |
1787 | } |
1788 | ||
a7052897 MT |
1789 | static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1790 | { | |
1791 | if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE) | |
1792 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); | |
1793 | return 1; | |
1794 | } | |
1795 | ||
e756fc62 RR |
1796 | static int emulate_on_interception(struct vcpu_svm *svm, |
1797 | struct kvm_run *kvm_run) | |
6aa8b732 | 1798 | { |
3427318f | 1799 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 1800 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
1801 | return 1; |
1802 | } | |
1803 | ||
1d075434 JR |
1804 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1805 | { | |
1806 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1807 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1808 | return 1; | |
1809 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1810 | return 0; | |
1811 | } | |
1812 | ||
6aa8b732 AK |
1813 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1814 | { | |
a2fa3e9f GH |
1815 | struct vcpu_svm *svm = to_svm(vcpu); |
1816 | ||
6aa8b732 | 1817 | switch (ecx) { |
6aa8b732 AK |
1818 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1819 | u64 tsc; | |
1820 | ||
1821 | rdtscll(tsc); | |
a2fa3e9f | 1822 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1823 | break; |
1824 | } | |
0e859cac | 1825 | case MSR_K6_STAR: |
a2fa3e9f | 1826 | *data = svm->vmcb->save.star; |
6aa8b732 | 1827 | break; |
0e859cac | 1828 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1829 | case MSR_LSTAR: |
a2fa3e9f | 1830 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1831 | break; |
1832 | case MSR_CSTAR: | |
a2fa3e9f | 1833 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1834 | break; |
1835 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1836 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1837 | break; |
1838 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1839 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1840 | break; |
1841 | #endif | |
1842 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1843 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1844 | break; |
1845 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1846 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1847 | break; |
1848 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1849 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1850 | break; |
a2938c80 JR |
1851 | /* Nobody will change the following 5 values in the VMCB so |
1852 | we can safely return them on rdmsr. They will always be 0 | |
1853 | until LBRV is implemented. */ | |
1854 | case MSR_IA32_DEBUGCTLMSR: | |
1855 | *data = svm->vmcb->save.dbgctl; | |
1856 | break; | |
1857 | case MSR_IA32_LASTBRANCHFROMIP: | |
1858 | *data = svm->vmcb->save.br_from; | |
1859 | break; | |
1860 | case MSR_IA32_LASTBRANCHTOIP: | |
1861 | *data = svm->vmcb->save.br_to; | |
1862 | break; | |
1863 | case MSR_IA32_LASTINTFROMIP: | |
1864 | *data = svm->vmcb->save.last_excp_from; | |
1865 | break; | |
1866 | case MSR_IA32_LASTINTTOIP: | |
1867 | *data = svm->vmcb->save.last_excp_to; | |
1868 | break; | |
b286d5d8 AG |
1869 | case MSR_VM_HSAVE_PA: |
1870 | *data = svm->hsave_msr; | |
1871 | break; | |
eb6f302e JR |
1872 | case MSR_VM_CR: |
1873 | *data = 0; | |
1874 | break; | |
6aa8b732 | 1875 | default: |
3bab1f5d | 1876 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1877 | } |
1878 | return 0; | |
1879 | } | |
1880 | ||
e756fc62 | 1881 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1882 | { |
ad312c7c | 1883 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1884 | u64 data; |
1885 | ||
e756fc62 | 1886 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1887 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1888 | else { |
af9ca2d7 JR |
1889 | KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data, |
1890 | (u32)(data >> 32), handler); | |
1891 | ||
5fdbf976 | 1892 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 1893 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 1894 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1895 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1896 | } |
1897 | return 1; | |
1898 | } | |
1899 | ||
1900 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1901 | { | |
a2fa3e9f GH |
1902 | struct vcpu_svm *svm = to_svm(vcpu); |
1903 | ||
6aa8b732 | 1904 | switch (ecx) { |
6aa8b732 AK |
1905 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1906 | u64 tsc; | |
1907 | ||
1908 | rdtscll(tsc); | |
a2fa3e9f | 1909 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1910 | break; |
1911 | } | |
0e859cac | 1912 | case MSR_K6_STAR: |
a2fa3e9f | 1913 | svm->vmcb->save.star = data; |
6aa8b732 | 1914 | break; |
49b14f24 | 1915 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1916 | case MSR_LSTAR: |
a2fa3e9f | 1917 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1918 | break; |
1919 | case MSR_CSTAR: | |
a2fa3e9f | 1920 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1921 | break; |
1922 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1923 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1924 | break; |
1925 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1926 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1927 | break; |
1928 | #endif | |
1929 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1930 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1931 | break; |
1932 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1933 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1934 | break; |
1935 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1936 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1937 | break; |
a2938c80 | 1938 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
1939 | if (!svm_has(SVM_FEATURE_LBRV)) { |
1940 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 1941 | __func__, data); |
24e09cbf JR |
1942 | break; |
1943 | } | |
1944 | if (data & DEBUGCTL_RESERVED_BITS) | |
1945 | return 1; | |
1946 | ||
1947 | svm->vmcb->save.dbgctl = data; | |
1948 | if (data & (1ULL<<0)) | |
1949 | svm_enable_lbrv(svm); | |
1950 | else | |
1951 | svm_disable_lbrv(svm); | |
a2938c80 | 1952 | break; |
62b9abaa JR |
1953 | case MSR_K7_EVNTSEL0: |
1954 | case MSR_K7_EVNTSEL1: | |
1955 | case MSR_K7_EVNTSEL2: | |
1956 | case MSR_K7_EVNTSEL3: | |
14ae51b6 CL |
1957 | case MSR_K7_PERFCTR0: |
1958 | case MSR_K7_PERFCTR1: | |
1959 | case MSR_K7_PERFCTR2: | |
1960 | case MSR_K7_PERFCTR3: | |
62b9abaa | 1961 | /* |
14ae51b6 CL |
1962 | * Just discard all writes to the performance counters; this |
1963 | * should keep both older linux and windows 64-bit guests | |
1964 | * happy | |
62b9abaa | 1965 | */ |
14ae51b6 CL |
1966 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data); |
1967 | ||
b286d5d8 AG |
1968 | break; |
1969 | case MSR_VM_HSAVE_PA: | |
1970 | svm->hsave_msr = data; | |
62b9abaa | 1971 | break; |
6aa8b732 | 1972 | default: |
3bab1f5d | 1973 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1974 | } |
1975 | return 0; | |
1976 | } | |
1977 | ||
e756fc62 | 1978 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1979 | { |
ad312c7c | 1980 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 1981 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 1982 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 JR |
1983 | |
1984 | KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32), | |
1985 | handler); | |
1986 | ||
5fdbf976 | 1987 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1988 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1989 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1990 | else |
e756fc62 | 1991 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1992 | return 1; |
1993 | } | |
1994 | ||
e756fc62 | 1995 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1996 | { |
e756fc62 RR |
1997 | if (svm->vmcb->control.exit_info_1) |
1998 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1999 | else |
e756fc62 | 2000 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
2001 | } |
2002 | ||
e756fc62 | 2003 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
2004 | struct kvm_run *kvm_run) |
2005 | { | |
af9ca2d7 JR |
2006 | KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler); |
2007 | ||
f0b85051 | 2008 | svm_clear_vintr(svm); |
85f455f7 | 2009 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2010 | /* |
2011 | * If the user space waits to inject interrupts, exit as soon as | |
2012 | * possible | |
2013 | */ | |
2014 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 2015 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 2016 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2017 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2018 | return 0; | |
2019 | } | |
2020 | ||
2021 | return 1; | |
2022 | } | |
2023 | ||
e756fc62 | 2024 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
2025 | struct kvm_run *kvm_run) = { |
2026 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
2027 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2028 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 2029 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
2030 | /* for now: */ |
2031 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
2032 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
2033 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 2034 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
2035 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
2036 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
2037 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2038 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
2039 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
2040 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2041 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2042 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
2043 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
2044 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 2045 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 2046 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 2047 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 2048 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 2049 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 2050 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2051 | [SVM_EXIT_SMI] = nop_on_interception, |
2052 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2053 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
2054 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
2055 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 2056 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 | 2057 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2058 | [SVM_EXIT_INVLPG] = invlpg_interception, |
6aa8b732 AK |
2059 | [SVM_EXIT_INVLPGA] = invalid_op_interception, |
2060 | [SVM_EXIT_IOIO] = io_interception, | |
2061 | [SVM_EXIT_MSR] = msr_interception, | |
2062 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2063 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2064 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2065 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2066 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2067 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2068 | [SVM_EXIT_STGI] = stgi_interception, |
2069 | [SVM_EXIT_CLGI] = clgi_interception, | |
6aa8b732 | 2070 | [SVM_EXIT_SKINIT] = invalid_op_interception, |
cf5a94d1 | 2071 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2072 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2073 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2074 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2075 | }; |
2076 | ||
04d2cc77 | 2077 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 2078 | { |
04d2cc77 | 2079 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 2080 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 2081 | |
af9ca2d7 JR |
2082 | KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip, |
2083 | (u32)((u64)svm->vmcb->save.rip >> 32), entryexit); | |
2084 | ||
cf74a78b AG |
2085 | if (is_nested(svm)) { |
2086 | nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n", | |
2087 | exit_code, svm->vmcb->control.exit_info_1, | |
2088 | svm->vmcb->control.exit_info_2, svm->vmcb->save.rip); | |
2089 | if (nested_svm_exit_handled(svm, true)) { | |
2090 | nested_svm_vmexit(svm); | |
2091 | nsvm_printk("-> #VMEXIT\n"); | |
2092 | return 1; | |
2093 | } | |
2094 | } | |
2095 | ||
709ddebf JR |
2096 | if (npt_enabled) { |
2097 | int mmu_reload = 0; | |
2098 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
2099 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
2100 | mmu_reload = 1; | |
2101 | } | |
2102 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
2103 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
2104 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
2105 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
2106 | kvm_inject_gp(vcpu, 0); | |
2107 | return 1; | |
2108 | } | |
2109 | } | |
2110 | if (mmu_reload) { | |
2111 | kvm_mmu_reset_context(vcpu); | |
2112 | kvm_mmu_load(vcpu); | |
2113 | } | |
2114 | } | |
2115 | ||
04d2cc77 AK |
2116 | kvm_reput_irq(svm); |
2117 | ||
2118 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
2119 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2120 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2121 | = svm->vmcb->control.exit_code; | |
2122 | return 0; | |
2123 | } | |
2124 | ||
a2fa3e9f | 2125 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf JR |
2126 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
2127 | exit_code != SVM_EXIT_NPF) | |
6aa8b732 AK |
2128 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
2129 | "exit_code 0x%x\n", | |
b8688d51 | 2130 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
2131 | exit_code); |
2132 | ||
9d8f549d | 2133 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 2134 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 2135 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 2136 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
2137 | return 0; |
2138 | } | |
2139 | ||
e756fc62 | 2140 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
2141 | } |
2142 | ||
2143 | static void reload_tss(struct kvm_vcpu *vcpu) | |
2144 | { | |
2145 | int cpu = raw_smp_processor_id(); | |
2146 | ||
2147 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 2148 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
2149 | load_TR_desc(); |
2150 | } | |
2151 | ||
e756fc62 | 2152 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
2153 | { |
2154 | int cpu = raw_smp_processor_id(); | |
2155 | ||
2156 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
2157 | ||
a2fa3e9f | 2158 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 2159 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 2160 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 2161 | new_asid(svm, svm_data); |
6aa8b732 AK |
2162 | } |
2163 | ||
2164 | ||
85f455f7 | 2165 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
2166 | { |
2167 | struct vmcb_control_area *control; | |
2168 | ||
af9ca2d7 JR |
2169 | KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler); |
2170 | ||
fa89a817 | 2171 | ++svm->vcpu.stat.irq_injections; |
e756fc62 | 2172 | control = &svm->vmcb->control; |
85f455f7 | 2173 | control->int_vector = irq; |
6aa8b732 AK |
2174 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
2175 | control->int_ctl |= V_IRQ_MASK | | |
2176 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
2177 | } | |
2178 | ||
2a8067f1 ED |
2179 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
2180 | { | |
2181 | struct vcpu_svm *svm = to_svm(vcpu); | |
2182 | ||
cf74a78b AG |
2183 | nested_svm_intr(svm); |
2184 | ||
2a8067f1 ED |
2185 | svm_inject_irq(svm, irq); |
2186 | } | |
2187 | ||
aaacfc9a JR |
2188 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
2189 | { | |
2190 | struct vcpu_svm *svm = to_svm(vcpu); | |
2191 | struct vmcb *vmcb = svm->vmcb; | |
2192 | int max_irr, tpr; | |
2193 | ||
2194 | if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr) | |
2195 | return; | |
2196 | ||
2197 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
2198 | ||
2199 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
2200 | if (max_irr == -1) | |
2201 | return; | |
2202 | ||
2203 | tpr = kvm_lapic_get_cr8(vcpu) << 4; | |
2204 | ||
2205 | if (tpr >= (max_irr & 0xf0)) | |
2206 | vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
2207 | } | |
2208 | ||
04d2cc77 | 2209 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 2210 | { |
04d2cc77 | 2211 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
2212 | struct vmcb *vmcb = svm->vmcb; |
2213 | int intr_vector = -1; | |
2214 | ||
2215 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
2216 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
2217 | intr_vector = vmcb->control.exit_int_info & | |
2218 | SVM_EVTINJ_VEC_MASK; | |
2219 | vmcb->control.exit_int_info = 0; | |
2220 | svm_inject_irq(svm, intr_vector); | |
aaacfc9a | 2221 | goto out; |
85f455f7 ED |
2222 | } |
2223 | ||
2224 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
aaacfc9a | 2225 | goto out; |
85f455f7 | 2226 | |
1b9778da | 2227 | if (!kvm_cpu_has_interrupt(vcpu)) |
aaacfc9a | 2228 | goto out; |
85f455f7 | 2229 | |
cf74a78b AG |
2230 | if (nested_svm_intr(svm)) |
2231 | goto out; | |
2232 | ||
1371d904 AG |
2233 | if (!(svm->vcpu.arch.hflags & HF_GIF_MASK)) |
2234 | goto out; | |
2235 | ||
85f455f7 ED |
2236 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || |
2237 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
2238 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
2239 | /* unable to deliver irq, set pending irq */ | |
f0b85051 | 2240 | svm_set_vintr(svm); |
85f455f7 | 2241 | svm_inject_irq(svm, 0x0); |
aaacfc9a | 2242 | goto out; |
85f455f7 ED |
2243 | } |
2244 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 2245 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 2246 | svm_inject_irq(svm, intr_vector); |
aaacfc9a JR |
2247 | out: |
2248 | update_cr8_intercept(vcpu); | |
85f455f7 ED |
2249 | } |
2250 | ||
2251 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
2252 | { | |
e756fc62 | 2253 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 2254 | |
7017fc3d ED |
2255 | if ((control->int_ctl & V_IRQ_MASK) |
2256 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 2257 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 2258 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 2259 | } |
c1150d8c | 2260 | |
ad312c7c | 2261 | svm->vcpu.arch.interrupt_window_open = |
1371d904 AG |
2262 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
2263 | (svm->vcpu.arch.hflags & HF_GIF_MASK); | |
c1150d8c DL |
2264 | } |
2265 | ||
85f455f7 ED |
2266 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
2267 | { | |
2268 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
2269 | int word_index = __ffs(vcpu->arch.irq_summary); |
2270 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
2271 | int irq = word_index * BITS_PER_LONG + bit_index; |
2272 | ||
ad312c7c ZX |
2273 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
2274 | if (!vcpu->arch.irq_pending[word_index]) | |
2275 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
2276 | svm_inject_irq(svm, irq); |
2277 | } | |
2278 | ||
04d2cc77 | 2279 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
2280 | struct kvm_run *kvm_run) |
2281 | { | |
04d2cc77 | 2282 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 2283 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 2284 | |
cf74a78b AG |
2285 | if (nested_svm_intr(svm)) |
2286 | return; | |
2287 | ||
ad312c7c | 2288 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 2289 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
1371d904 AG |
2290 | (svm->vmcb->save.rflags & X86_EFLAGS_IF) && |
2291 | (svm->vcpu.arch.hflags & HF_GIF_MASK)); | |
c1150d8c | 2292 | |
ad312c7c | 2293 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
2294 | /* |
2295 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
2296 | */ | |
85f455f7 | 2297 | svm_do_inject_vector(svm); |
c1150d8c DL |
2298 | |
2299 | /* | |
2300 | * Interrupts blocked. Wait for unblock. | |
2301 | */ | |
ad312c7c ZX |
2302 | if (!svm->vcpu.arch.interrupt_window_open && |
2303 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
f0b85051 AG |
2304 | svm_set_vintr(svm); |
2305 | else | |
2306 | svm_clear_vintr(svm); | |
c1150d8c DL |
2307 | } |
2308 | ||
cbc94022 IE |
2309 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2310 | { | |
2311 | return 0; | |
2312 | } | |
2313 | ||
6aa8b732 AK |
2314 | static void save_db_regs(unsigned long *db_regs) |
2315 | { | |
5aff458e AK |
2316 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
2317 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
2318 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
2319 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
2320 | } |
2321 | ||
2322 | static void load_db_regs(unsigned long *db_regs) | |
2323 | { | |
5aff458e AK |
2324 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
2325 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
2326 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
2327 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
2328 | } |
2329 | ||
d9e368d6 AK |
2330 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
2331 | { | |
2332 | force_new_asid(vcpu); | |
2333 | } | |
2334 | ||
04d2cc77 AK |
2335 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
2336 | { | |
2337 | } | |
2338 | ||
d7bf8221 JR |
2339 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
2340 | { | |
2341 | struct vcpu_svm *svm = to_svm(vcpu); | |
2342 | ||
2343 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
2344 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
2345 | kvm_lapic_set_tpr(vcpu, cr8); | |
2346 | } | |
2347 | } | |
2348 | ||
649d6864 JR |
2349 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
2350 | { | |
2351 | struct vcpu_svm *svm = to_svm(vcpu); | |
2352 | u64 cr8; | |
2353 | ||
2354 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2355 | return; | |
2356 | ||
2357 | cr8 = kvm_get_cr8(vcpu); | |
2358 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
2359 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
2360 | } | |
2361 | ||
80e31d4f AK |
2362 | #ifdef CONFIG_X86_64 |
2363 | #define R "r" | |
2364 | #else | |
2365 | #define R "e" | |
2366 | #endif | |
2367 | ||
04d2cc77 | 2368 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 2369 | { |
a2fa3e9f | 2370 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2371 | u16 fs_selector; |
2372 | u16 gs_selector; | |
2373 | u16 ldt_selector; | |
d9e368d6 | 2374 | |
5fdbf976 MT |
2375 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
2376 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
2377 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
2378 | ||
e756fc62 | 2379 | pre_svm_run(svm); |
6aa8b732 | 2380 | |
649d6864 JR |
2381 | sync_lapic_to_cr8(vcpu); |
2382 | ||
6aa8b732 | 2383 | save_host_msrs(vcpu); |
d6e88aec AK |
2384 | fs_selector = kvm_read_fs(); |
2385 | gs_selector = kvm_read_gs(); | |
2386 | ldt_selector = kvm_read_ldt(); | |
a2fa3e9f GH |
2387 | svm->host_cr2 = kvm_read_cr2(); |
2388 | svm->host_dr6 = read_dr6(); | |
2389 | svm->host_dr7 = read_dr7(); | |
3d6368ef AG |
2390 | if (!is_nested(svm)) |
2391 | svm->vmcb->save.cr2 = vcpu->arch.cr2; | |
709ddebf JR |
2392 | /* required for live migration with NPT */ |
2393 | if (npt_enabled) | |
2394 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 2395 | |
a2fa3e9f | 2396 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 2397 | write_dr7(0); |
a2fa3e9f GH |
2398 | save_db_regs(svm->host_db_regs); |
2399 | load_db_regs(svm->db_regs); | |
6aa8b732 | 2400 | } |
36241b8c | 2401 | |
04d2cc77 AK |
2402 | clgi(); |
2403 | ||
2404 | local_irq_enable(); | |
36241b8c | 2405 | |
6aa8b732 | 2406 | asm volatile ( |
80e31d4f AK |
2407 | "push %%"R"bp; \n\t" |
2408 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
2409 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
2410 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
2411 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
2412 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
2413 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 2414 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2415 | "mov %c[r8](%[svm]), %%r8 \n\t" |
2416 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
2417 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
2418 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
2419 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
2420 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
2421 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
2422 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
2423 | #endif |
2424 | ||
6aa8b732 | 2425 | /* Enter guest mode */ |
80e31d4f AK |
2426 | "push %%"R"ax \n\t" |
2427 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
2428 | __ex(SVM_VMLOAD) "\n\t" |
2429 | __ex(SVM_VMRUN) "\n\t" | |
2430 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 2431 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
2432 | |
2433 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
2434 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
2435 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
2436 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
2437 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
2438 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
2439 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 2440 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2441 | "mov %%r8, %c[r8](%[svm]) \n\t" |
2442 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
2443 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
2444 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
2445 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
2446 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
2447 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
2448 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 2449 | #endif |
80e31d4f | 2450 | "pop %%"R"bp" |
6aa8b732 | 2451 | : |
fb3f0f51 | 2452 | : [svm]"a"(svm), |
6aa8b732 | 2453 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
2454 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
2455 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
2456 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
2457 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
2458 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
2459 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 2460 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2461 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
2462 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
2463 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
2464 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
2465 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
2466 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
2467 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
2468 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 2469 | #endif |
54a08c04 | 2470 | : "cc", "memory" |
80e31d4f | 2471 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 2472 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
2473 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
2474 | #endif | |
2475 | ); | |
6aa8b732 | 2476 | |
a2fa3e9f GH |
2477 | if ((svm->vmcb->save.dr7 & 0xff)) |
2478 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 2479 | |
ad312c7c | 2480 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5fdbf976 MT |
2481 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
2482 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
2483 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
6aa8b732 | 2484 | |
a2fa3e9f GH |
2485 | write_dr6(svm->host_dr6); |
2486 | write_dr7(svm->host_dr7); | |
2487 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 | 2488 | |
d6e88aec AK |
2489 | kvm_load_fs(fs_selector); |
2490 | kvm_load_gs(gs_selector); | |
2491 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
2492 | load_host_msrs(vcpu); |
2493 | ||
2494 | reload_tss(vcpu); | |
2495 | ||
56ba47dd AK |
2496 | local_irq_disable(); |
2497 | ||
2498 | stgi(); | |
2499 | ||
d7bf8221 JR |
2500 | sync_cr8_to_lapic(vcpu); |
2501 | ||
a2fa3e9f | 2502 | svm->next_rip = 0; |
6aa8b732 AK |
2503 | } |
2504 | ||
80e31d4f AK |
2505 | #undef R |
2506 | ||
6aa8b732 AK |
2507 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
2508 | { | |
a2fa3e9f GH |
2509 | struct vcpu_svm *svm = to_svm(vcpu); |
2510 | ||
709ddebf JR |
2511 | if (npt_enabled) { |
2512 | svm->vmcb->control.nested_cr3 = root; | |
2513 | force_new_asid(vcpu); | |
2514 | return; | |
2515 | } | |
2516 | ||
a2fa3e9f | 2517 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 2518 | force_new_asid(vcpu); |
7807fa6c AL |
2519 | |
2520 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
2521 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
2522 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
2523 | vcpu->fpu_active = 0; |
2524 | } | |
6aa8b732 AK |
2525 | } |
2526 | ||
6aa8b732 AK |
2527 | static int is_disabled(void) |
2528 | { | |
6031a61c JR |
2529 | u64 vm_cr; |
2530 | ||
2531 | rdmsrl(MSR_VM_CR, vm_cr); | |
2532 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
2533 | return 1; | |
2534 | ||
6aa8b732 AK |
2535 | return 0; |
2536 | } | |
2537 | ||
102d8325 IM |
2538 | static void |
2539 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2540 | { | |
2541 | /* | |
2542 | * Patch in the VMMCALL instruction: | |
2543 | */ | |
2544 | hypercall[0] = 0x0f; | |
2545 | hypercall[1] = 0x01; | |
2546 | hypercall[2] = 0xd9; | |
102d8325 IM |
2547 | } |
2548 | ||
002c7f7c YS |
2549 | static void svm_check_processor_compat(void *rtn) |
2550 | { | |
2551 | *(int *)rtn = 0; | |
2552 | } | |
2553 | ||
774ead3a AK |
2554 | static bool svm_cpu_has_accelerated_tpr(void) |
2555 | { | |
2556 | return false; | |
2557 | } | |
2558 | ||
67253af5 SY |
2559 | static int get_npt_level(void) |
2560 | { | |
2561 | #ifdef CONFIG_X86_64 | |
2562 | return PT64_ROOT_LEVEL; | |
2563 | #else | |
2564 | return PT32E_ROOT_LEVEL; | |
2565 | #endif | |
2566 | } | |
2567 | ||
64d4d521 SY |
2568 | static int svm_get_mt_mask_shift(void) |
2569 | { | |
2570 | return 0; | |
2571 | } | |
2572 | ||
cbdd1bea | 2573 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
2574 | .cpu_has_kvm_support = has_svm, |
2575 | .disabled_by_bios = is_disabled, | |
2576 | .hardware_setup = svm_hardware_setup, | |
2577 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 2578 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
2579 | .hardware_enable = svm_hardware_enable, |
2580 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 2581 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
2582 | |
2583 | .vcpu_create = svm_create_vcpu, | |
2584 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 2585 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 2586 | |
04d2cc77 | 2587 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
2588 | .vcpu_load = svm_vcpu_load, |
2589 | .vcpu_put = svm_vcpu_put, | |
2590 | ||
2591 | .set_guest_debug = svm_guest_debug, | |
2592 | .get_msr = svm_get_msr, | |
2593 | .set_msr = svm_set_msr, | |
2594 | .get_segment_base = svm_get_segment_base, | |
2595 | .get_segment = svm_get_segment, | |
2596 | .set_segment = svm_set_segment, | |
2e4d2653 | 2597 | .get_cpl = svm_get_cpl, |
1747fb71 | 2598 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 2599 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 2600 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
2601 | .set_cr3 = svm_set_cr3, |
2602 | .set_cr4 = svm_set_cr4, | |
2603 | .set_efer = svm_set_efer, | |
2604 | .get_idt = svm_get_idt, | |
2605 | .set_idt = svm_set_idt, | |
2606 | .get_gdt = svm_get_gdt, | |
2607 | .set_gdt = svm_set_gdt, | |
2608 | .get_dr = svm_get_dr, | |
2609 | .set_dr = svm_set_dr, | |
6aa8b732 AK |
2610 | .get_rflags = svm_get_rflags, |
2611 | .set_rflags = svm_set_rflags, | |
2612 | ||
6aa8b732 | 2613 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 2614 | |
6aa8b732 | 2615 | .run = svm_vcpu_run, |
04d2cc77 | 2616 | .handle_exit = handle_exit, |
6aa8b732 | 2617 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 2618 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
2619 | .get_irq = svm_get_irq, |
2620 | .set_irq = svm_set_irq, | |
298101da AK |
2621 | .queue_exception = svm_queue_exception, |
2622 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
2623 | .inject_pending_irq = svm_intr_assist, |
2624 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
2625 | |
2626 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 2627 | .get_tdp_level = get_npt_level, |
64d4d521 | 2628 | .get_mt_mask_shift = svm_get_mt_mask_shift, |
6aa8b732 AK |
2629 | }; |
2630 | ||
2631 | static int __init svm_init(void) | |
2632 | { | |
cb498ea2 | 2633 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 2634 | THIS_MODULE); |
6aa8b732 AK |
2635 | } |
2636 | ||
2637 | static void __exit svm_exit(void) | |
2638 | { | |
cb498ea2 | 2639 | kvm_exit(); |
6aa8b732 AK |
2640 | } |
2641 | ||
2642 | module_init(svm_init) | |
2643 | module_exit(svm_exit) |