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KVM: x86/mmu: Reuse the current root if possible for fast switch
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / vmx / vmx.c
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20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732
AK		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * Copyright (C) 2006 Qumranet, Inc.
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
6aa8b732
AK		 14 */
15
199b118a
SC		 16#include <linux/frame.h>
17#include <linux/highmem.h>
18#include <linux/hrtimer.h>
19#include <linux/kernel.h>
edf88417 20#include <linux/kvm_host.h>
6aa8b732 21#include <linux/module.h>
c7addb90 22#include <linux/moduleparam.h>
e9bda3b3 23#include <linux/mod_devicetable.h>
199b118a 24#include <linux/mm.h>
199b118a 25#include <linux/sched.h>
b284909a 26#include <linux/sched/smt.h>
5a0e3ad6 27#include <linux/slab.h>
cafd6659 28#include <linux/tboot.h>
199b118a 29#include <linux/trace_events.h>
e495606d 30
199b118a 31#include <asm/apic.h>
fd8ca6da 32#include <asm/asm.h>
28b835d6 33#include <asm/cpu.h>
199b118a 34#include <asm/debugreg.h>
3b3be0d1 35#include <asm/desc.h>
952f07ec 36#include <asm/fpu/internal.h>
199b118a 37#include <asm/io.h>
efc64404 38#include <asm/irq_remapping.h>
199b118a
SC		 39#include <asm/kexec.h>
40#include <asm/perf_event.h>
41#include <asm/mce.h>
d6e41f11 42#include <asm/mmu_context.h>
773e8a04 43#include <asm/mshyperv.h>
199b118a
SC		 44#include <asm/spec-ctrl.h>
45#include <asm/virtext.h>
46#include <asm/vmx.h>
6aa8b732 47
3077c191 48#include "capabilities.h"
199b118a 49#include "cpuid.h"
4cebd747 50#include "evmcs.h"
199b118a
SC		 51#include "irq.h"
52#include "kvm_cache_regs.h"
53#include "lapic.h"
54#include "mmu.h"
55d2375e 55#include "nested.h"
89b0c9f5 56#include "ops.h"
25462f7f 57#include "pmu.h"
199b118a 58#include "trace.h"
cb1d474b 59#include "vmcs.h"
609363cf 60#include "vmcs12.h"
89b0c9f5 61#include "vmx.h"
199b118a 62#include "x86.h"
229456fc 63
6aa8b732
AK		 64MODULE_AUTHOR("Qumranet");
65MODULE_LICENSE("GPL");
66
e9bda3b3
JT		 67static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
69 {}
70};
71MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
72
2c4fd91d 73bool __read_mostly enable_vpid = 1;
736caefe 74module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 75
d02fcf50
PB		 76static bool __read_mostly enable_vnmi = 1;
77module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
78
2c4fd91d 79bool __read_mostly flexpriority_enabled = 1;
736caefe 80module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 81
2c4fd91d 82bool __read_mostly enable_ept = 1;
736caefe 83module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 84
2c4fd91d 85bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 86module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
88
2c4fd91d 89bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 90module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
91
a27685c3 92static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 93module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 94
476bc001 95static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 96module_param(fasteoi, bool, S_IRUGO);
97
a4443267 98bool __read_mostly enable_apicv = 1;
01e439be 99module_param(enable_apicv, bool, S_IRUGO);
83d4c286 100
801d3424
NHE		 101/*
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
105 */
1e58e5e5 106static bool __read_mostly nested = 1;
801d3424
NHE		 107module_param(nested, bool, S_IRUGO);
108
2c4fd91d 109bool __read_mostly enable_pml = 1;
843e4330
KH		 110module_param_named(pml, enable_pml, bool, S_IRUGO);
111
6f2f8453
PB		 112static bool __read_mostly dump_invalid_vmcs = 0;
113module_param(dump_invalid_vmcs, bool, 0644);
114
904e14fb
PB		 115#define MSR_BITMAP_MODE_X2APIC 1
116#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 117
64903d61
HZ		 118#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
119
64672c95
YJ		 120/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
121static int __read_mostly cpu_preemption_timer_multi;
122static bool __read_mostly enable_preemption_timer = 1;
123#ifdef CONFIG_X86_64
124module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
125#endif
126
3de6347b 127#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 128#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
129#define KVM_VM_CR0_ALWAYS_ON \
130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 132#define KVM_CR4_GUEST_OWNED_BITS \
133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 135
5dc1f044 136#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 137#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
138#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
139
78ac8b47
AK		 140#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
141
bf8c55d8
CP		 142#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
145 RTIT_STATUS_BYTECNT))
146
147#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
149
4b8d54f9
ZE		 150/*
151 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
152 * ple_gap: upper bound on the amount of time between two successive
153 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 154 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 155 * ple_window: upper bound on the amount of time a guest is allowed to execute
156 * in a PAUSE loop. Tests indicate that most spinlocks are held for
157 * less than 2^12 cycles
158 * Time is measured based on a counter that runs at the same rate as the TSC,
159 * refer SDM volume 3b section 21.6.13 & 22.1.3.
160 */
c8e88717 161static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 162module_param(ple_gap, uint, 0444);
b4a2d31d 163
7fbc85a5
BM		 164static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
165module_param(ple_window, uint, 0444);
4b8d54f9 166
b4a2d31d 167/* Default doubles per-vcpu window every exit. */
c8e88717 168static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 169module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 170
171/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 172static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 173module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 174
175/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 176static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177module_param(ple_window_max, uint, 0444);
b4a2d31d 178
f99e3daf
CP		 179/* Default is SYSTEM mode, 1 for host-guest mode */
180int __read_mostly pt_mode = PT_MODE_SYSTEM;
181module_param(pt_mode, int, S_IRUGO);
182
a399477e 183static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 184static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 185static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 186
7db92e16
TG		 187/* Storage for pre module init parameter parsing */
188static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 189
190static const struct {
191 const char *option;
0027ff2a 192 bool for_parse;
a399477e 193} vmentry_l1d_param[] = {
0027ff2a
PB		 194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
196 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 200};
201
7db92e16
TG		 202#define L1D_CACHE_ORDER 4
203static void *vmx_l1d_flush_pages;
204
205static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 206{
7db92e16 207 struct page *page;
288d152c 208 unsigned int i;
a399477e 209
19a36d32
WL		 210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
212 return 0;
213 }
214
7db92e16
TG		 215 if (!enable_ept) {
216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
217 return 0;
a399477e
KRW		 218 }
219
d806afa4
YW		 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
221 u64 msr;
222
223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
226 return 0;
227 }
228 }
8e0b2b91 229
d90a7a0e
JK		 230 /* If set to auto use the default l1tf mitigation method */
231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
232 switch (l1tf_mitigation) {
233 case L1TF_MITIGATION_OFF:
234 l1tf = VMENTER_L1D_FLUSH_NEVER;
235 break;
236 case L1TF_MITIGATION_FLUSH_NOWARN:
237 case L1TF_MITIGATION_FLUSH:
238 case L1TF_MITIGATION_FLUSH_NOSMT:
239 l1tf = VMENTER_L1D_FLUSH_COND;
240 break;
241 case L1TF_MITIGATION_FULL:
242 case L1TF_MITIGATION_FULL_FORCE:
243 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
244 break;
245 }
246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 }
249
7db92e16
TG		 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 252 /*
253 * This allocation for vmx_l1d_flush_pages is not tied to a VM
254 * lifetime and so should not be charged to a memcg.
255 */
7db92e16
TG		 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
257 if (!page)
258 return -ENOMEM;
259 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 260
261 /*
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
265 */
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
268 PAGE_SIZE);
269 }
7db92e16
TG		 270 }
271
272 l1tf_vmx_mitigation = l1tf;
273
895ae47f
TG		 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
276 else
277 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 278
427362a1
NS		 279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 281 else
427362a1 282 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 283 return 0;
284}
285
286static int vmentry_l1d_flush_parse(const char *s)
287{
288 unsigned int i;
289
290 if (s) {
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
294 return i;
7db92e16
TG		 295 }
296 }
a399477e
KRW		 297 return -EINVAL;
298}
299
7db92e16
TG		 300static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301{
dd4bfa73 302 int l1tf, ret;
7db92e16 303
7db92e16
TG		 304 l1tf = vmentry_l1d_flush_parse(s);
305 if (l1tf < 0)
306 return l1tf;
307
0027ff2a
PB		 308 if (!boot_cpu_has(X86_BUG_L1TF))
309 return 0;
310
7db92e16
TG		 311 /*
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
315 * established.
316 */
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
319 return 0;
320 }
321
dd4bfa73
TG		 322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
325 return ret;
7db92e16
TG		 326}
327
a399477e
KRW		 328static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
329{
0027ff2a
PB		 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
332
7db92e16 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 334}
335
336static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
339};
895ae47f 340module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 341
d99e4152
GN		 342static bool guest_state_valid(struct kvm_vcpu *vcpu);
343static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 344static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 345 u32 msr, int type);
75880a01 346
453eafbe
SC		 347void vmx_vmexit(void);
348
52a9fcbc
SC		 349#define vmx_insn_failed(fmt...) \
350do { \
351 WARN_ONCE(1, fmt); \
352 pr_warn_ratelimited(fmt); \
353} while (0)
354
6e202097
SC		 355asmlinkage void vmread_error(unsigned long field, bool fault)
356{
357 if (fault)
358 kvm_spurious_fault();
359 else
360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
361}
362
52a9fcbc
SC		 363noinline void vmwrite_error(unsigned long field, unsigned long value)
364{
365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
367}
368
369noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
370{
371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
372}
373
374noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
375{
376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
377}
378
379noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
380{
381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
382 ext, vpid, gva);
383}
384
385noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
386{
387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
388 ext, eptp, gpa);
389}
390
6aa8b732 391static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 392DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 393/*
394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
396 */
397static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 398
bf9f6ac8
FW		 399/*
400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
401 * can find which vCPU should be waken up.
402 */
403static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
404static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
405
2384d2b3
SY		 406static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
407static DEFINE_SPINLOCK(vmx_vpid_lock);
408
3077c191
SC		 409struct vmcs_config vmcs_config;
410struct vmx_capability vmx_capability;
d56f546d 411
6aa8b732
AK		 412#define VMX_SEGMENT_FIELD(seg) \
413 [VCPU_SREG_##seg] = { \
414 .selector = GUEST_##seg##_SELECTOR, \
415 .base = GUEST_##seg##_BASE, \
416 .limit = GUEST_##seg##_LIMIT, \
417 .ar_bytes = GUEST_##seg##_AR_BYTES, \
418 }
419
772e0318 420static const struct kvm_vmx_segment_field {
6aa8b732
AK		 421 unsigned selector;
422 unsigned base;
423 unsigned limit;
424 unsigned ar_bytes;
425} kvm_vmx_segment_fields[] = {
426 VMX_SEGMENT_FIELD(CS),
427 VMX_SEGMENT_FIELD(DS),
428 VMX_SEGMENT_FIELD(ES),
429 VMX_SEGMENT_FIELD(FS),
430 VMX_SEGMENT_FIELD(GS),
431 VMX_SEGMENT_FIELD(SS),
432 VMX_SEGMENT_FIELD(TR),
433 VMX_SEGMENT_FIELD(LDTR),
434};
435
cf3646eb 436u64 host_efer;
2342080c 437static unsigned long host_idt_base;
26bb0981 438
4d56c8a7 439/*
898a811f
JM		 440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
441 * will emulate SYSCALL in legacy mode if the vendor string in guest
442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
443 * support this emulation, IA32_STAR must always be included in
444 * vmx_msr_index[], even in i386 builds.
4d56c8a7 445 */
cf3646eb 446const u32 vmx_msr_index[] = {
05b3e0c2 447#ifdef CONFIG_X86_64
44ea2b17 448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 449#endif
8c06585d 450 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
c11f83e0 451 MSR_IA32_TSX_CTRL,
6aa8b732 452};
6aa8b732 453
773e8a04
VK		 454#if IS_ENABLED(CONFIG_HYPERV)
455static bool __read_mostly enlightened_vmcs = true;
456module_param(enlightened_vmcs, bool, 0444);
457
877ad952
TL		 458/* check_ept_pointer() should be under protection of ept_pointer_lock. */
459static void check_ept_pointer_match(struct kvm *kvm)
460{
461 struct kvm_vcpu *vcpu;
462 u64 tmp_eptp = INVALID_PAGE;
463 int i;
464
465 kvm_for_each_vcpu(i, vcpu, kvm) {
466 if (!VALID_PAGE(tmp_eptp)) {
467 tmp_eptp = to_vmx(vcpu)->ept_pointer;
468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
469 to_kvm_vmx(kvm)->ept_pointers_match
470 = EPT_POINTERS_MISMATCH;
471 return;
472 }
473 }
474
475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
476}
477
8997f657 478static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 479 void *data)
480{
481 struct kvm_tlb_range *range = data;
482
483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
484 range->pages);
485}
486
487static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
489{
490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
491
492 /*
493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
494 * of the base of EPT PML4 table, strip off EPT configuration
495 * information.
496 */
497 if (range)
498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
499 kvm_fill_hv_flush_list_func, (void *)range);
500 else
501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
502}
503
504static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
505 struct kvm_tlb_range *range)
877ad952 506{
a5c214da 507 struct kvm_vcpu *vcpu;
b7c1c226 508 int ret = 0, i;
877ad952
TL		 509
510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
511
512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
513 check_ept_pointer_match(kvm);
514
515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 516 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 517 /* If ept_pointer is invalid pointer, bypass flush request. */
518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
519 ret |= __hv_remote_flush_tlb_with_range(
520 kvm, vcpu, range);
53963a70 521 }
a5c214da 522 } else {
1f3a3e46
LT		 523 ret = __hv_remote_flush_tlb_with_range(kvm,
524 kvm_get_vcpu(kvm, 0), range);
877ad952 525 }
877ad952 526
877ad952
TL		 527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
528 return ret;
529}
1f3a3e46
LT		 530static int hv_remote_flush_tlb(struct kvm *kvm)
531{
532 return hv_remote_flush_tlb_with_range(kvm, NULL);
533}
534
6f6a657c
VK		 535static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
536{
537 struct hv_enlightened_vmcs *evmcs;
538 struct hv_partition_assist_pg **p_hv_pa_pg =
539 &vcpu->kvm->arch.hyperv.hv_pa_pg;
540 /*
541 * Synthetic VM-Exit is not enabled in current code and so All
542 * evmcs in singe VM shares same assist page.
543 */
cab01850 544 if (!*p_hv_pa_pg)
6f6a657c 545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
cab01850
VK		 546
547 if (!*p_hv_pa_pg)
548 return -ENOMEM;
6f6a657c
VK		 549
550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
551
552 evmcs->partition_assist_page =
553 __pa(*p_hv_pa_pg);
cab01850 554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
6f6a657c
VK		 555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
556
6f6a657c
VK		 557 return 0;
558}
559
773e8a04
VK		 560#endif /* IS_ENABLED(CONFIG_HYPERV) */
561
64672c95
YJ		 562/*
563 * Comment's format: document - errata name - stepping - processor name.
564 * Refer from
565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
566 */
567static u32 vmx_preemption_cpu_tfms[] = {
568/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
5690x000206E6,
570/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
571/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
572/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5730x00020652,
574/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5750x00020655,
576/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
577/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
578/*
579 * 320767.pdf - AAP86 - B1 -
580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
581 */
5820x000106E5,
583/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5840x000106A0,
585/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5860x000106A1,
587/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5880x000106A4,
589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5920x000106A5,
3d82c565
WH		 593 /* Xeon E3-1220 V2 */
5940x000306A8,
64672c95
YJ		 595};
596
597static inline bool cpu_has_broken_vmx_preemption_timer(void)
598{
599 u32 eax = cpuid_eax(0x00000001), i;
600
601 /* Clear the reserved bits */
602 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 604 if (eax == vmx_preemption_cpu_tfms[i])
605 return true;
606
607 return false;
608}
609
35754c98 610static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 611{
35754c98 612 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 613}
614
04547156
SY		 615static inline bool report_flexpriority(void)
616{
617 return flexpriority_enabled;
618}
619
97b7ead3 620static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 621{
622 int i;
623
a2fa3e9f 624 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 626 return i;
627 return -1;
628}
629
97b7ead3 630struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 631{
632 int i;
633
8b9cf98c 634 i = __find_msr_index(vmx, msr);
a75beee6 635 if (i >= 0)
a2fa3e9f 636 return &vmx->guest_msrs[i];
8b6d44c7 637 return NULL;
7725f0ba
AK		 638}
639
b07a5c53
PB		 640static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
641{
642 int ret = 0;
643
644 u64 old_msr_data = msr->data;
645 msr->data = data;
646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
647 preempt_disable();
648 ret = kvm_set_shared_msr(msr->index, msr->data,
649 msr->mask);
650 preempt_enable();
651 if (ret)
652 msr->data = old_msr_data;
653 }
654 return ret;
655}
656
7c97fcb3
SC		 657void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
658{
659 vmcs_clear(loaded_vmcs->vmcs);
660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
661 vmcs_clear(loaded_vmcs->shadow_vmcs);
662 loaded_vmcs->cpu = -1;
663 loaded_vmcs->launched = 0;
664}
665
2965faa5 666#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 667/*
668 * This bitmap is used to indicate whether the vmclear
669 * operation is enabled on all cpus. All disabled by
670 * default.
671 */
672static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
673
674static inline void crash_enable_local_vmclear(int cpu)
675{
676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
677}
678
679static inline void crash_disable_local_vmclear(int cpu)
680{
681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
682}
683
684static inline int crash_local_vmclear_enabled(int cpu)
685{
686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
687}
688
689static void crash_vmclear_local_loaded_vmcss(void)
690{
691 int cpu = raw_smp_processor_id();
692 struct loaded_vmcs *v;
693
694 if (!crash_local_vmclear_enabled(cpu))
695 return;
696
697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
698 loaded_vmcss_on_cpu_link)
699 vmcs_clear(v->vmcs);
700}
701#else
702static inline void crash_enable_local_vmclear(int cpu) { }
703static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 704#endif /* CONFIG_KEXEC_CORE */
8f536b76 705
d462b819 706static void __loaded_vmcs_clear(void *arg)
6aa8b732 707{
d462b819 708 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 709 int cpu = raw_smp_processor_id();
6aa8b732 710
d462b819
NHE		 711 if (loaded_vmcs->cpu != cpu)
712 return; /* vcpu migration can race with cpu offline */
713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 714 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 715 crash_disable_local_vmclear(cpu);
d462b819 716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 717
718 /*
719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
720 * is before setting loaded_vmcs->vcpu to -1 which is done in
721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
722 * then adds the vmcs into percpu list before it is deleted.
723 */
724 smp_wmb();
725
d462b819 726 loaded_vmcs_init(loaded_vmcs);
8f536b76 727 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 728}
729
89b0c9f5 730void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 731{
e6c7d321
XG		 732 int cpu = loaded_vmcs->cpu;
733
734 if (cpu != -1)
735 smp_call_function_single(cpu,
736 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 737}
738
2fb92db1
AK		 739static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
740 unsigned field)
741{
742 bool ret;
743 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
744
cb3c1e2f
SC		 745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
2fb92db1
AK		 747 vmx->segment_cache.bitmask = 0;
748 }
749 ret = vmx->segment_cache.bitmask & mask;
750 vmx->segment_cache.bitmask |= mask;
751 return ret;
752}
753
754static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
755{
756 u16 *p = &vmx->segment_cache.seg[seg].selector;
757
758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
760 return *p;
761}
762
763static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
764{
765 ulong *p = &vmx->segment_cache.seg[seg].base;
766
767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
769 return *p;
770}
771
772static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
773{
774 u32 *p = &vmx->segment_cache.seg[seg].limit;
775
776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
778 return *p;
779}
780
781static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
782{
783 u32 *p = &vmx->segment_cache.seg[seg].ar;
784
785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
787 return *p;
788}
789
97b7ead3 790void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 791{
792 u32 eb;
793
fd7373cc 794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 795 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 796 /*
797 * Guest access to VMware backdoor ports could legitimately
798 * trigger #GP because of TSS I/O permission bitmap.
799 * We intercept those #GP and allow access to them anyway
800 * as VMware does.
801 */
802 if (enable_vmware_backdoor)
803 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 804 if ((vcpu->guest_debug &
805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
807 eb |= 1u << BP_VECTOR;
7ffd92c5 808 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 809 eb = ~0;
089d034e 810 if (enable_ept)
1439442c 811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 812
813 /* When we are running a nested L2 guest and L1 specified for it a
814 * certain exception bitmap, we must trap the same exceptions and pass
815 * them to L1. When running L2, we will only handle the exceptions
816 * specified above if L1 did not want them.
817 */
818 if (is_guest_mode(vcpu))
819 eb |= get_vmcs12(vcpu)->exception_bitmap;
820
abd3f2d6
AK		 821 vmcs_write32(EXCEPTION_BITMAP, eb);
822}
823
d28b387f
KA		 824/*
825 * Check if MSR is intercepted for currently loaded MSR bitmap.
826 */
827static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
828{
829 unsigned long *msr_bitmap;
830 int f = sizeof(unsigned long);
831
832 if (!cpu_has_vmx_msr_bitmap())
833 return true;
834
835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
836
837 if (msr <= 0x1fff) {
838 return !!test_bit(msr, msr_bitmap + 0x800 / f);
839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
840 msr &= 0x1fff;
841 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
842 }
843
844 return true;
845}
846
2961e876
GN		 847static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
848 unsigned long entry, unsigned long exit)
8bf00a52 849{
2961e876
GN		 850 vm_entry_controls_clearbit(vmx, entry);
851 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 852}
853
662f1d1d 854int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
ca83b4a7
KRW		 855{
856 unsigned int i;
857
858 for (i = 0; i < m->nr; ++i) {
859 if (m->val[i].index == msr)
860 return i;
861 }
862 return -ENOENT;
863}
864
61d2ef2c
AK		 865static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
866{
ca83b4a7 867 int i;
61d2ef2c
AK		 868 struct msr_autoload *m = &vmx->msr_autoload;
869
8bf00a52
GN		 870 switch (msr) {
871 case MSR_EFER:
c73da3fc 872 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 873 clear_atomic_switch_msr_special(vmx,
874 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 875 VM_EXIT_LOAD_IA32_EFER);
876 return;
877 }
878 break;
879 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 880 if (cpu_has_load_perf_global_ctrl()) {
2961e876 881 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
884 return;
885 }
886 break;
110312c8 887 }
ef0fbcac 888 i = vmx_find_msr_index(&m->guest, msr);
ca83b4a7 889 if (i < 0)
31907093 890 goto skip_guest;
33966dd6 891 --m->guest.nr;
33966dd6 892 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 894
31907093 895skip_guest:
ef0fbcac 896 i = vmx_find_msr_index(&m->host, msr);
31907093 897 if (i < 0)
61d2ef2c 898 return;
31907093
KRW		 899
900 --m->host.nr;
901 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 903}
904
2961e876
GN		 905static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
906 unsigned long entry, unsigned long exit,
907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
908 u64 guest_val, u64 host_val)
8bf00a52
GN		 909{
910 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 911 if (host_val_vmcs != HOST_IA32_EFER)
912 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 913 vm_entry_controls_setbit(vmx, entry);
914 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 915}
916
61d2ef2c 917static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 918 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 919{
989e3992 920 int i, j = 0;
61d2ef2c
AK		 921 struct msr_autoload *m = &vmx->msr_autoload;
922
8bf00a52
GN		 923 switch (msr) {
924 case MSR_EFER:
c73da3fc 925 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 926 add_atomic_switch_msr_special(vmx,
927 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 928 VM_EXIT_LOAD_IA32_EFER,
929 GUEST_IA32_EFER,
930 HOST_IA32_EFER,
931 guest_val, host_val);
932 return;
933 }
934 break;
935 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 936 if (cpu_has_load_perf_global_ctrl()) {
2961e876 937 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
940 GUEST_IA32_PERF_GLOBAL_CTRL,
941 HOST_IA32_PERF_GLOBAL_CTRL,
942 guest_val, host_val);
943 return;
944 }
945 break;
7099e2e1
RK		 946 case MSR_IA32_PEBS_ENABLE:
947 /* PEBS needs a quiescent period after being disabled (to write
948 * a record). Disabling PEBS through VMX MSR swapping doesn't
949 * provide that period, so a CPU could write host's record into
950 * guest's memory.
951 */
952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 953 }
954
ef0fbcac 955 i = vmx_find_msr_index(&m->guest, msr);
989e3992 956 if (!entry_only)
ef0fbcac 957 j = vmx_find_msr_index(&m->host, msr);
61d2ef2c 958
7cfe0526
AL		 959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
60266204 961 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 962 "Can't add msr %x\n", msr);
963 return;
61d2ef2c 964 }
31907093 965 if (i < 0) {
ca83b4a7 966 i = m->guest.nr++;
33966dd6 967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 968 }
989e3992
KRW		 969 m->guest.val[i].index = msr;
970 m->guest.val[i].value = guest_val;
971
972 if (entry_only)
973 return;
61d2ef2c 974
31907093
KRW		 975 if (j < 0) {
976 j = m->host.nr++;
33966dd6 977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 978 }
31907093
KRW		 979 m->host.val[j].index = msr;
980 m->host.val[j].value = host_val;
61d2ef2c
AK		 981}
982
92c0d900 983static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 984{
844a5fe2
PB		 985 u64 guest_efer = vmx->vcpu.arch.efer;
986 u64 ignore_bits = 0;
987
9167ab79
PB		 988 /* Shadow paging assumes NX to be available. */
989 if (!enable_ept)
990 guest_efer |= EFER_NX;
3a34a881 991
51c6cf66 992 /*
844a5fe2 993 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 994 */
844a5fe2 995 ignore_bits |= EFER_SCE;
51c6cf66
AK		 996#ifdef CONFIG_X86_64
997 ignore_bits |= EFER_LMA | EFER_LME;
998 /* SCE is meaningful only in long mode on Intel */
999 if (guest_efer & EFER_LMA)
1000 ignore_bits &= ~(u64)EFER_SCE;
1001#endif
84ad33ef 1002
f6577a5f
AL		 1003 /*
1004 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1005 * On CPUs that support "load IA32_EFER", always switch EFER
1006 * atomically, since it's faster than switching it manually.
1007 */
c73da3fc 1008 if (cpu_has_load_ia32_efer() ||
f6577a5f 1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1010 if (!(guest_efer & EFER_LMA))
1011 guest_efer &= ~EFER_LME;
54b98bff
AL		 1012 if (guest_efer != host_efer)
1013 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 1014 guest_efer, host_efer, false);
02343cf2
SC		 1015 else
1016 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 1017 return false;
844a5fe2 1018 } else {
02343cf2
SC		 1019 clear_atomic_switch_msr(vmx, MSR_EFER);
1020
844a5fe2
PB		 1021 guest_efer &= ~ignore_bits;
1022 guest_efer |= host_efer & ignore_bits;
1023
1024 vmx->guest_msrs[efer_offset].data = guest_efer;
1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 1026
844a5fe2
PB		 1027 return true;
1028 }
51c6cf66
AK		 1029}
1030
e28baead
AL		 1031#ifdef CONFIG_X86_32
1032/*
1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1034 * VMCS rather than the segment table. KVM uses this helper to figure
1035 * out the current bases to poke them into the VMCS before entry.
1036 */
2d49ec72
GN		 1037static unsigned long segment_base(u16 selector)
1038{
8c2e41f7 1039 struct desc_struct *table;
2d49ec72
GN		 1040 unsigned long v;
1041
8c2e41f7 1042 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1043 return 0;
1044
45fc8757 1045 table = get_current_gdt_ro();
2d49ec72 1046
8c2e41f7 1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 1048 u16 ldt_selector = kvm_read_ldt();
1049
8c2e41f7 1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1051 return 0;
1052
8c2e41f7 1053 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 1054 }
8c2e41f7 1055 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 1056 return v;
1057}
e28baead 1058#endif
2d49ec72 1059
e348ac7c
SC		 1060static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1061{
1062 return (pt_mode == PT_MODE_HOST_GUEST) &&
1063 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1064}
1065
2ef444f1
CP		 1066static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1067{
1068 u32 i;
1069
1070 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1071 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1072 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1073 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1074 for (i = 0; i < addr_range; i++) {
1075 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1076 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1077 }
1078}
1079
1080static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1081{
1082 u32 i;
1083
1084 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1085 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1086 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1087 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1088 for (i = 0; i < addr_range; i++) {
1089 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1090 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1091 }
1092}
1093
1094static void pt_guest_enter(struct vcpu_vmx *vmx)
1095{
1096 if (pt_mode == PT_MODE_SYSTEM)
1097 return;
1098
2ef444f1 1099 /*
b08c2896
CP		 1100 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1101 * Save host state before VM entry.
2ef444f1 1102 */
b08c2896 1103 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1104 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1105 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1106 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1107 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1108 }
1109}
1110
1111static void pt_guest_exit(struct vcpu_vmx *vmx)
1112{
1113 if (pt_mode == PT_MODE_SYSTEM)
1114 return;
1115
1116 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1117 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1118 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1119 }
1120
1121 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1122 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1123}
1124
13b964a2
SC		 1125void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1126 unsigned long fs_base, unsigned long gs_base)
1127{
1128 if (unlikely(fs_sel != host->fs_sel)) {
1129 if (!(fs_sel & 7))
1130 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1131 else
1132 vmcs_write16(HOST_FS_SELECTOR, 0);
1133 host->fs_sel = fs_sel;
1134 }
1135 if (unlikely(gs_sel != host->gs_sel)) {
1136 if (!(gs_sel & 7))
1137 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1138 else
1139 vmcs_write16(HOST_GS_SELECTOR, 0);
1140 host->gs_sel = gs_sel;
1141 }
1142 if (unlikely(fs_base != host->fs_base)) {
1143 vmcs_writel(HOST_FS_BASE, fs_base);
1144 host->fs_base = fs_base;
1145 }
1146 if (unlikely(gs_base != host->gs_base)) {
1147 vmcs_writel(HOST_GS_BASE, gs_base);
1148 host->gs_base = gs_base;
1149 }
1150}
1151
97b7ead3 1152void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1153{
04d2cc77 1154 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1155 struct vmcs_host_state *host_state;
51e8a8cc 1156#ifdef CONFIG_X86_64
35060ed6 1157 int cpu = raw_smp_processor_id();
51e8a8cc 1158#endif
e368b875
SC		 1159 unsigned long fs_base, gs_base;
1160 u16 fs_sel, gs_sel;
26bb0981 1161 int i;
04d2cc77 1162
d264ee0c
SC		 1163 vmx->req_immediate_exit = false;
1164
f48b4711
LA		 1165 /*
1166 * Note that guest MSRs to be saved/restored can also be changed
1167 * when guest state is loaded. This happens when guest transitions
1168 * to/from long-mode by setting MSR_EFER.LMA.
1169 */
b464f57e
PB		 1170 if (!vmx->guest_msrs_ready) {
1171 vmx->guest_msrs_ready = true;
f48b4711
LA		 1172 for (i = 0; i < vmx->save_nmsrs; ++i)
1173 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1174 vmx->guest_msrs[i].data,
1175 vmx->guest_msrs[i].mask);
1176
1177 }
c9dfd3fb 1178
1179 if (vmx->nested.need_vmcs12_to_shadow_sync)
1180 nested_sync_vmcs12_to_shadow(vcpu);
1181
b464f57e 1182 if (vmx->guest_state_loaded)
33ed6329
AK		 1183 return;
1184
b464f57e 1185 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1186
33ed6329
AK		 1187 /*
1188 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1189 * allow segment selectors with cpl > 0 or ti == 1.
1190 */
d7ee039e 1191 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1192
1193#ifdef CONFIG_X86_64
d7ee039e
SC		 1194 savesegment(ds, host_state->ds_sel);
1195 savesegment(es, host_state->es_sel);
e368b875
SC		 1196
1197 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1198 if (likely(is_64bit_mm(current->mm))) {
1199 save_fsgs_for_kvm();
e368b875
SC		 1200 fs_sel = current->thread.fsindex;
1201 gs_sel = current->thread.gsindex;
b062b794 1202 fs_base = current->thread.fsbase;
e368b875 1203 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1204 } else {
e368b875
SC		 1205 savesegment(fs, fs_sel);
1206 savesegment(gs, gs_sel);
b062b794 1207 fs_base = read_msr(MSR_FS_BASE);
e368b875 1208 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1209 }
b2da15ac 1210
4679b61f 1211 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1212#else
e368b875
SC		 1213 savesegment(fs, fs_sel);
1214 savesegment(gs, gs_sel);
1215 fs_base = segment_base(fs_sel);
1216 gs_base = segment_base(gs_sel);
707c0874 1217#endif
e368b875 1218
13b964a2 1219 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
b464f57e 1220 vmx->guest_state_loaded = true;
33ed6329
AK		 1221}
1222
6d6095bd 1223static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1224{
d7ee039e
SC		 1225 struct vmcs_host_state *host_state;
1226
b464f57e 1227 if (!vmx->guest_state_loaded)
33ed6329
AK		 1228 return;
1229
b464f57e 1230 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1231
e1beb1d3 1232 ++vmx->vcpu.stat.host_state_reload;
bd9966de 1233
c8770e7b 1234#ifdef CONFIG_X86_64
4679b61f 1235 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1236#endif
d7ee039e
SC		 1237 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1238 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1239#ifdef CONFIG_X86_64
d7ee039e 1240 load_gs_index(host_state->gs_sel);
9581d442 1241#else
d7ee039e 1242 loadsegment(gs, host_state->gs_sel);
33ed6329 1243#endif
33ed6329 1244 }
d7ee039e
SC		 1245 if (host_state->fs_sel & 7)
1246 loadsegment(fs, host_state->fs_sel);
b2da15ac 1247#ifdef CONFIG_X86_64
d7ee039e
SC		 1248 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1249 loadsegment(ds, host_state->ds_sel);
1250 loadsegment(es, host_state->es_sel);
b2da15ac 1251 }
b2da15ac 1252#endif
b7ffc44d 1253 invalidate_tss_limit();
44ea2b17 1254#ifdef CONFIG_X86_64
c8770e7b 1255 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1256#endif
45fc8757 1257 load_fixmap_gdt(raw_smp_processor_id());
b464f57e
PB		 1258 vmx->guest_state_loaded = false;
1259 vmx->guest_msrs_ready = false;
33ed6329
AK		 1260}
1261
678e315e
SC		 1262#ifdef CONFIG_X86_64
1263static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1264{
4679b61f 1265 preempt_disable();
b464f57e 1266 if (vmx->guest_state_loaded)
4679b61f
PB		 1267 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1268 preempt_enable();
678e315e 1269 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1270}
1271
678e315e
SC		 1272static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1273{
4679b61f 1274 preempt_disable();
b464f57e 1275 if (vmx->guest_state_loaded)
4679b61f
PB		 1276 wrmsrl(MSR_KERNEL_GS_BASE, data);
1277 preempt_enable();
678e315e
SC		 1278 vmx->msr_guest_kernel_gs_base = data;
1279}
1280#endif
1281
28b835d6
FW		 1282static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1283{
1284 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1285 struct pi_desc old, new;
1286 unsigned int dest;
1287
31afb2ea
PB		 1288 /*
1289 * In case of hot-plug or hot-unplug, we may have to undo
1290 * vmx_vcpu_pi_put even if there is no assigned device. And we
1291 * always keep PI.NDST up to date for simplicity: it makes the
1292 * code easier, and CPU migration is not a fast path.
1293 */
1294 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1295 return;
1296
132194ff
JM		 1297 /*
1298 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1299 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1300 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1301 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1302 * correctly.
1303 */
1304 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1305 pi_clear_sn(pi_desc);
1306 goto after_clear_sn;
1307 }
1308
31afb2ea 1309 /* The full case. */
28b835d6
FW		 1310 do {
1311 old.control = new.control = pi_desc->control;
1312
31afb2ea 1313 dest = cpu_physical_id(cpu);
28b835d6 1314
31afb2ea
PB		 1315 if (x2apic_enabled())
1316 new.ndst = dest;
1317 else
1318 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1319
28b835d6 1320 new.sn = 0;
c0a1666b
PB		 1321 } while (cmpxchg64(&pi_desc->control, old.control,
1322 new.control) != old.control);
c112b5f5 1323
132194ff
JM		 1324after_clear_sn:
1325
c112b5f5
LK		 1326 /*
1327 * Clear SN before reading the bitmap. The VT-d firmware
1328 * writes the bitmap and reads SN atomically (5.2.3 in the
1329 * spec), so it doesn't really have a memory barrier that
1330 * pairs with this, but we cannot do that and we need one.
1331 */
1332 smp_mb__after_atomic();
1333
29881b6e 1334 if (!pi_is_pir_empty(pi_desc))
c112b5f5 1335 pi_set_on(pi_desc);
28b835d6 1336}
1be0e61c 1337
8ef863e6 1338void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1339{
a2fa3e9f 1340 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1341 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1342
b80c76ec 1343 if (!already_loaded) {
fe0e80be 1344 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1345 local_irq_disable();
8f536b76 1346 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1347
1348 /*
1349 * Read loaded_vmcs->cpu should be before fetching
1350 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1351 * See the comments in __loaded_vmcs_clear().
1352 */
1353 smp_rmb();
1354
d462b819
NHE		 1355 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1356 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1357 crash_enable_local_vmclear(cpu);
92fe13be 1358 local_irq_enable();
b80c76ec
JM		 1359 }
1360
1361 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1362 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1363 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1364 indirect_branch_prediction_barrier();
b80c76ec
JM		 1365 }
1366
1367 if (!already_loaded) {
59c58ceb 1368 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1369 unsigned long sysenter_esp;
1370
1371 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1372
6aa8b732
AK		 1373 /*
1374 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1375 * processors. See 22.2.4.
6aa8b732 1376 */
e0c23063 1377 vmcs_writel(HOST_TR_BASE,
72f5e08d 1378 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1379 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732
AK		 1380
1381 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1382 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1383
d462b819 1384 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1385 }
28b835d6 1386
2680d6da
OH		 1387 /* Setup TSC multiplier */
1388 if (kvm_has_tsc_control &&
c95ba92a
PF		 1389 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1390 decache_tsc_multiplier(vmx);
8ef863e6
SC		 1391}
1392
1393/*
1394 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1395 * vcpu mutex is already taken.
1396 */
1397void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1398{
1399 struct vcpu_vmx *vmx = to_vmx(vcpu);
1400
1401 vmx_vcpu_load_vmcs(vcpu, cpu);
2680d6da 1402
28b835d6 1403 vmx_vcpu_pi_load(vcpu, cpu);
8ef863e6 1404
1be0e61c 1405 vmx->host_pkru = read_pkru();
74c55931 1406 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1407}
1408
1409static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1410{
1411 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1412
1413 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1414 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1415 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1416 return;
1417
1418 /* Set SN when the vCPU is preempted */
1419 if (vcpu->preempted)
1420 pi_set_sn(pi_desc);
6aa8b732
AK		 1421}
1422
13b964a2 1423static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1424{
28b835d6
FW		 1425 vmx_vcpu_pi_put(vcpu);
1426
6d6095bd 1427 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1428}
1429
f244deed
WL		 1430static bool emulation_required(struct kvm_vcpu *vcpu)
1431{
1432 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1433}
1434
97b7ead3 1435unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1436{
e7bddc52 1437 struct vcpu_vmx *vmx = to_vmx(vcpu);
78ac8b47 1438 unsigned long rflags, save_rflags;
345dcaa8 1439
cb3c1e2f
SC		 1440 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1441 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
6de12732 1442 rflags = vmcs_readl(GUEST_RFLAGS);
e7bddc52 1443 if (vmx->rmode.vm86_active) {
6de12732 1444 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
e7bddc52 1445 save_rflags = vmx->rmode.save_rflags;
6de12732
AK		 1446 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1447 }
e7bddc52 1448 vmx->rflags = rflags;
78ac8b47 1449 }
e7bddc52 1450 return vmx->rflags;
6aa8b732
AK		 1451}
1452
97b7ead3 1453void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1454{
e7bddc52 1455 struct vcpu_vmx *vmx = to_vmx(vcpu);
491c1ad1 1456 unsigned long old_rflags;
f244deed 1457
491c1ad1 1458 if (enable_unrestricted_guest) {
cb3c1e2f 1459 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
491c1ad1
SC		 1460 vmx->rflags = rflags;
1461 vmcs_writel(GUEST_RFLAGS, rflags);
1462 return;
1463 }
1464
1465 old_rflags = vmx_get_rflags(vcpu);
e7bddc52
SC		 1466 vmx->rflags = rflags;
1467 if (vmx->rmode.vm86_active) {
1468 vmx->rmode.save_rflags = rflags;
053de044 1469 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1470 }
6aa8b732 1471 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed 1472
e7bddc52
SC		 1473 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1474 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1475}
1476
97b7ead3 1477u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1478{
1479 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1480 int ret = 0;
1481
1482 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1483 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1484 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1485 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1486
37ccdcbe 1487 return ret;
2809f5d2
GC		 1488}
1489
97b7ead3 1490void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1491{
1492 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1493 u32 interruptibility = interruptibility_old;
1494
1495 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1496
48005f64 1497 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1498 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1499 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1500 interruptibility |= GUEST_INTR_STATE_STI;
1501
1502 if ((interruptibility != interruptibility_old))
1503 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1504}
1505
bf8c55d8
CP		 1506static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1507{
1508 struct vcpu_vmx *vmx = to_vmx(vcpu);
1509 unsigned long value;
1510
1511 /*
1512 * Any MSR write that attempts to change bits marked reserved will
1513 * case a #GP fault.
1514 */
1515 if (data & vmx->pt_desc.ctl_bitmask)
1516 return 1;
1517
1518 /*
1519 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1520 * result in a #GP unless the same write also clears TraceEn.
1521 */
1522 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1523 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1524 return 1;
1525
1526 /*
1527 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1528 * and FabricEn would cause #GP, if
1529 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1530 */
1531 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1532 !(data & RTIT_CTL_FABRIC_EN) &&
1533 !intel_pt_validate_cap(vmx->pt_desc.caps,
1534 PT_CAP_single_range_output))
1535 return 1;
1536
1537 /*
1538 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1539 * utilize encodings marked reserved will casue a #GP fault.
1540 */
1541 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1542 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1543 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1544 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1545 return 1;
1546 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1547 PT_CAP_cycle_thresholds);
1548 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1549 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1550 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1551 return 1;
1552 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1553 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1554 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1555 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1556 return 1;
1557
1558 /*
1559 * If ADDRx_CFG is reserved or the encodings is >2 will
1560 * cause a #GP fault.
1561 */
1562 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1563 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1564 return 1;
1565 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1566 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1567 return 1;
1568 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1569 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1570 return 1;
1571 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1572 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1573 return 1;
1574
1575 return 0;
1576}
1577
1957aa63 1578static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1579{
1580 unsigned long rip;
6aa8b732 1581
1957aa63
SC		 1582 /*
1583 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1584 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1585 * set when EPT misconfig occurs. In practice, real hardware updates
1586 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1587 * (namely Hyper-V) don't set it due to it being undefined behavior,
1588 * i.e. we end up advancing IP with some random value.
1589 */
1590 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1591 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1592 rip = kvm_rip_read(vcpu);
1593 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1594 kvm_rip_write(vcpu, rip);
1595 } else {
1596 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1597 return 0;
1598 }
6aa8b732 1599
2809f5d2
GC		 1600 /* skipping an emulated instruction also counts */
1601 vmx_set_interrupt_shadow(vcpu, 0);
f8ea7c60 1602
60fc3d02 1603 return 1;
f8ea7c60
VK		 1604}
1605
5ef8acbd
OU		 1606
1607/*
1608 * Recognizes a pending MTF VM-exit and records the nested state for later
1609 * delivery.
1610 */
1611static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1612{
1613 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1614 struct vcpu_vmx *vmx = to_vmx(vcpu);
1615
1616 if (!is_guest_mode(vcpu))
1617 return;
1618
1619 /*
1620 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1621 * T-bit traps. As instruction emulation is completed (i.e. at the
1622 * instruction boundary), any #DB exception pending delivery must be a
1623 * debug-trap. Record the pending MTF state to be delivered in
1624 * vmx_check_nested_events().
1625 */
1626 if (nested_cpu_has_mtf(vmcs12) &&
1627 (!vcpu->arch.exception.pending ||
1628 vcpu->arch.exception.nr == DB_VECTOR))
1629 vmx->nested.mtf_pending = true;
1630 else
1631 vmx->nested.mtf_pending = false;
1632}
1633
1634static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1635{
1636 vmx_update_emulated_instruction(vcpu);
1637 return skip_emulated_instruction(vcpu);
1638}
1639
caa057a2
WL		 1640static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1641{
1642 /*
1643 * Ensure that we clear the HLT state in the VMCS. We don't need to
1644 * explicitly skip the instruction because if the HLT state is set,
1645 * then the instruction is already executing and RIP has already been
1646 * advanced.
1647 */
1648 if (kvm_hlt_in_guest(vcpu->kvm) &&
1649 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1650 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1651}
1652
cfcd20e5 1653static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1654{
77ab6db0 1655 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1656 unsigned nr = vcpu->arch.exception.nr;
1657 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1658 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1659 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1660
da998b46
JM		 1661 kvm_deliver_exception_payload(vcpu);
1662
8ab2d2e2 1663 if (has_error_code) {
77ab6db0 1664 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1665 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1666 }
77ab6db0 1667
7ffd92c5 1668 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1669 int inc_eip = 0;
1670 if (kvm_exception_is_soft(nr))
1671 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 1672 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
77ab6db0
JK		 1673 return;
1674 }
1675
add5ff7a
SC		 1676 WARN_ON_ONCE(vmx->emulation_required);
1677
66fd3f7f
GN		 1678 if (kvm_exception_is_soft(nr)) {
1679 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1680 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1681 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1682 } else
1683 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1684
1685 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1686
1687 vmx_clear_hlt(vcpu);
298101da
AK		 1688}
1689
4e47c7a6
SY		 1690static bool vmx_rdtscp_supported(void)
1691{
1692 return cpu_has_vmx_rdtscp();
1693}
1694
ad756a16
MJ		 1695static bool vmx_invpcid_supported(void)
1696{
eb4b248e 1697 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1698}
1699
a75beee6
ED		 1700/*
1701 * Swap MSR entry in host/guest MSR entry array.
1702 */
8b9cf98c 1703static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1704{
26bb0981 1705 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1706
1707 tmp = vmx->guest_msrs[to];
1708 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1709 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1710}
1711
e38aea3e
AK		 1712/*
1713 * Set up the vmcs to automatically save and restore system
1714 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1715 * mode, as fiddling with msrs is very expensive.
1716 */
8b9cf98c 1717static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1718{
26bb0981 1719 int save_nmsrs, index;
e38aea3e 1720
a75beee6
ED		 1721 save_nmsrs = 0;
1722#ifdef CONFIG_X86_64
84c8c5b8
JM		 1723 /*
1724 * The SYSCALL MSRs are only needed on long mode guests, and only
1725 * when EFER.SCE is set.
1726 */
1727 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1728 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1729 if (index >= 0)
8b9cf98c
RR		 1730 move_msr_up(vmx, index, save_nmsrs++);
1731 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1732 if (index >= 0)
8b9cf98c 1733 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1734 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1735 if (index >= 0)
8b9cf98c 1736 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1737 }
1738#endif
92c0d900
AK		 1739 index = __find_msr_index(vmx, MSR_EFER);
1740 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1741 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1742 index = __find_msr_index(vmx, MSR_TSC_AUX);
1743 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1744 move_msr_up(vmx, index, save_nmsrs++);
c11f83e0
PB		 1745 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1746 if (index >= 0)
1747 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1748
26bb0981 1749 vmx->save_nmsrs = save_nmsrs;
b464f57e 1750 vmx->guest_msrs_ready = false;
5897297b 1751
8d14695f 1752 if (cpu_has_vmx_msr_bitmap())
904e14fb 1753 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1754}
1755
e79f245d 1756static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1757{
e79f245d 1758 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1759
e79f245d 1760 if (is_guest_mode(vcpu) &&
5e3d394f 1761 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
e79f245d
KA		 1762 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1763
1764 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1765}
1766
326e7425 1767static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1768{
45c3af97
PB		 1769 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1770 u64 g_tsc_offset = 0;
1771
1772 /*
1773 * We're here if L1 chose not to trap WRMSR to TSC. According
1774 * to the spec, this should set L1's TSC; The offset that L1
1775 * set for L2 remains unchanged, and still needs to be added
1776 * to the newly set TSC to get L2's TSC.
1777 */
1778 if (is_guest_mode(vcpu) &&
5e3d394f 1779 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
45c3af97 1780 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1781
45c3af97
PB		 1782 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1783 vcpu->arch.tsc_offset - g_tsc_offset,
1784 offset);
1785 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1786 return offset + g_tsc_offset;
6aa8b732
AK		 1787}
1788
801d3424
NHE		 1789/*
1790 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1791 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1792 * all guests if the "nested" module option is off, and can also be disabled
1793 * for a single guest by disabling its VMX cpuid bit.
1794 */
7c97fcb3 1795bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1796{
d6321d49 1797 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1798}
1799
55d2375e
SC		 1800static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1801 uint64_t val)
62cc6b9d 1802{
55d2375e 1803 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1804
55d2375e 1805 return !(val & ~valid_bits);
62cc6b9d
DM		 1806}
1807
55d2375e 1808static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1809{
55d2375e
SC		 1810 switch (msr->index) {
1811 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1812 if (!nested)
1813 return 1;
1814 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1815 default:
1816 return 1;
1817 }
62cc6b9d
DM		 1818}
1819
55d2375e
SC		 1820/*
1821 * Reads an msr value (of 'msr_index') into 'pdata'.
1822 * Returns 0 on success, non-0 otherwise.
1823 * Assumes vcpu_load() was already called.
1824 */
1825static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1826{
55d2375e
SC		 1827 struct vcpu_vmx *vmx = to_vmx(vcpu);
1828 struct shared_msr_entry *msr;
bf8c55d8 1829 u32 index;
62cc6b9d 1830
55d2375e
SC		 1831 switch (msr_info->index) {
1832#ifdef CONFIG_X86_64
1833 case MSR_FS_BASE:
1834 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1835 break;
55d2375e
SC		 1836 case MSR_GS_BASE:
1837 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1838 break;
55d2375e
SC		 1839 case MSR_KERNEL_GS_BASE:
1840 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1841 break;
55d2375e
SC		 1842#endif
1843 case MSR_EFER:
1844 return kvm_get_msr_common(vcpu, msr_info);
c11f83e0
PB		 1845 case MSR_IA32_TSX_CTRL:
1846 if (!msr_info->host_initiated &&
1847 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1848 return 1;
1849 goto find_shared_msr;
6e3ba4ab
TX		 1850 case MSR_IA32_UMWAIT_CONTROL:
1851 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1852 return 1;
1853
1854 msr_info->data = vmx->msr_ia32_umwait_control;
1855 break;
55d2375e
SC		 1856 case MSR_IA32_SPEC_CTRL:
1857 if (!msr_info->host_initiated &&
1858 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1859 return 1;
1860
1861 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1862 break;
6aa8b732 1863 case MSR_IA32_SYSENTER_CS:
609e36d3 1864 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1865 break;
1866 case MSR_IA32_SYSENTER_EIP:
609e36d3 1867 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1868 break;
1869 case MSR_IA32_SYSENTER_ESP:
609e36d3 1870 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1871 break;
0dd376e7 1872 case MSR_IA32_BNDCFGS:
691bd434 1873 if (!kvm_mpx_supported() ||
d6321d49
RK		 1874 (!msr_info->host_initiated &&
1875 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1876 return 1;
609e36d3 1877 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1878 break;
c45dcc71
AR		 1879 case MSR_IA32_MCG_EXT_CTL:
1880 if (!msr_info->host_initiated &&
a6cb099a 1881 !(vmx->msr_ia32_feature_control &
32ad73db 1882 FEAT_CTL_LMCE_ENABLED))
cae50139 1883 return 1;
c45dcc71
AR		 1884 msr_info->data = vcpu->arch.mcg_ext_ctl;
1885 break;
32ad73db 1886 case MSR_IA32_FEAT_CTL:
a6cb099a 1887 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1888 break;
1889 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1890 if (!nested_vmx_allowed(vcpu))
1891 return 1;
31de3d25
VK		 1892 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1893 &msr_info->data))
1894 return 1;
1895 /*
1896 * Enlightened VMCS v1 doesn't have certain fields, but buggy
1897 * Hyper-V versions are still trying to use corresponding
1898 * features when they are exposed. Filter out the essential
1899 * minimum.
1900 */
1901 if (!msr_info->host_initiated &&
1902 vmx->nested.enlightened_vmcs_enabled)
1903 nested_evmcs_filter_control_msr(msr_info->index,
1904 &msr_info->data);
1905 break;
bf8c55d8
CP		 1906 case MSR_IA32_RTIT_CTL:
1907 if (pt_mode != PT_MODE_HOST_GUEST)
1908 return 1;
1909 msr_info->data = vmx->pt_desc.guest.ctl;
1910 break;
1911 case MSR_IA32_RTIT_STATUS:
1912 if (pt_mode != PT_MODE_HOST_GUEST)
1913 return 1;
1914 msr_info->data = vmx->pt_desc.guest.status;
1915 break;
1916 case MSR_IA32_RTIT_CR3_MATCH:
1917 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1918 !intel_pt_validate_cap(vmx->pt_desc.caps,
1919 PT_CAP_cr3_filtering))
1920 return 1;
1921 msr_info->data = vmx->pt_desc.guest.cr3_match;
1922 break;
1923 case MSR_IA32_RTIT_OUTPUT_BASE:
1924 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1925 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1926 PT_CAP_topa_output) &&
1927 !intel_pt_validate_cap(vmx->pt_desc.caps,
1928 PT_CAP_single_range_output)))
1929 return 1;
1930 msr_info->data = vmx->pt_desc.guest.output_base;
1931 break;
1932 case MSR_IA32_RTIT_OUTPUT_MASK:
1933 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1934 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1935 PT_CAP_topa_output) &&
1936 !intel_pt_validate_cap(vmx->pt_desc.caps,
1937 PT_CAP_single_range_output)))
1938 return 1;
1939 msr_info->data = vmx->pt_desc.guest.output_mask;
1940 break;
1941 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1942 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1943 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1944 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1945 PT_CAP_num_address_ranges)))
1946 return 1;
1947 if (index % 2)
1948 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1949 else
1950 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1951 break;
4e47c7a6 1952 case MSR_TSC_AUX:
d6321d49
RK		 1953 if (!msr_info->host_initiated &&
1954 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1955 return 1;
c11f83e0 1956 goto find_shared_msr;
6aa8b732 1957 default:
c11f83e0 1958 find_shared_msr:
a6cb099a 1959 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1960 if (msr) {
609e36d3 1961 msr_info->data = msr->data;
3bab1f5d 1962 break;
6aa8b732 1963 }
609e36d3 1964 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1965 }
1966
6aa8b732
AK		 1967 return 0;
1968}
1969
1970/*
311497e0 1971 * Writes msr value into the appropriate "register".
6aa8b732
AK		 1972 * Returns 0 on success, non-0 otherwise.
1973 * Assumes vcpu_load() was already called.
1974 */
8fe8ab46 1975static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1976{
a2fa3e9f 1977 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1978 struct shared_msr_entry *msr;
2cc51560 1979 int ret = 0;
8fe8ab46
WA		 1980 u32 msr_index = msr_info->index;
1981 u64 data = msr_info->data;
bf8c55d8 1982 u32 index;
2cc51560 1983
6aa8b732 1984 switch (msr_index) {
3bab1f5d 1985 case MSR_EFER:
8fe8ab46 1986 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1987 break;
16175a79 1988#ifdef CONFIG_X86_64
6aa8b732 1989 case MSR_FS_BASE:
2fb92db1 1990 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1991 vmcs_writel(GUEST_FS_BASE, data);
1992 break;
1993 case MSR_GS_BASE:
2fb92db1 1994 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1995 vmcs_writel(GUEST_GS_BASE, data);
1996 break;
44ea2b17 1997 case MSR_KERNEL_GS_BASE:
678e315e 1998 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1999 break;
6aa8b732
AK		 2000#endif
2001 case MSR_IA32_SYSENTER_CS:
de70d279
SC		 2002 if (is_guest_mode(vcpu))
2003 get_vmcs12(vcpu)->guest_sysenter_cs = data;
6aa8b732
AK		 2004 vmcs_write32(GUEST_SYSENTER_CS, data);
2005 break;
2006 case MSR_IA32_SYSENTER_EIP:
de70d279
SC		 2007 if (is_guest_mode(vcpu))
2008 get_vmcs12(vcpu)->guest_sysenter_eip = data;
f5b42c33 2009 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2010 break;
2011 case MSR_IA32_SYSENTER_ESP:
de70d279
SC		 2012 if (is_guest_mode(vcpu))
2013 get_vmcs12(vcpu)->guest_sysenter_esp = data;
f5b42c33 2014 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2015 break;
699a1ac2
SC		 2016 case MSR_IA32_DEBUGCTLMSR:
2017 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2018 VM_EXIT_SAVE_DEBUG_CONTROLS)
2019 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2020
2021 ret = kvm_set_msr_common(vcpu, msr_info);
2022 break;
2023
0dd376e7 2024 case MSR_IA32_BNDCFGS:
691bd434 2025 if (!kvm_mpx_supported() ||
d6321d49
RK		 2026 (!msr_info->host_initiated &&
2027 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 2028 return 1;
fd8cb433 2029 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 2030 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 2031 return 1;
0dd376e7
LJ		 2032 vmcs_write64(GUEST_BNDCFGS, data);
2033 break;
6e3ba4ab
TX		 2034 case MSR_IA32_UMWAIT_CONTROL:
2035 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2036 return 1;
2037
2038 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2039 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2040 return 1;
2041
2042 vmx->msr_ia32_umwait_control = data;
2043 break;
d28b387f
KA		 2044 case MSR_IA32_SPEC_CTRL:
2045 if (!msr_info->host_initiated &&
d28b387f
KA		 2046 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2047 return 1;
2048
6441fa61 2049 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
d28b387f
KA		 2050 return 1;
2051
2052 vmx->spec_ctrl = data;
d28b387f
KA		 2053 if (!data)
2054 break;
2055
2056 /*
2057 * For non-nested:
2058 * When it's written (to non-zero) for the first time, pass
2059 * it through.
2060 *
2061 * For nested:
2062 * The handling of the MSR bitmap for L2 guests is done in
4d516fe7 2063 * nested_vmx_prepare_msr_bitmap. We should not touch the
d28b387f
KA		 2064 * vmcs02.msr_bitmap here since it gets completely overwritten
2065 * in the merging. We update the vmcs01 here for L1 as well
2066 * since it will end up touching the MSR anyway now.
2067 */
2068 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2069 MSR_IA32_SPEC_CTRL,
2070 MSR_TYPE_RW);
2071 break;
c11f83e0
PB		 2072 case MSR_IA32_TSX_CTRL:
2073 if (!msr_info->host_initiated &&
2074 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2075 return 1;
2076 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2077 return 1;
2078 goto find_shared_msr;
15d45071
AR		 2079 case MSR_IA32_PRED_CMD:
2080 if (!msr_info->host_initiated &&
15d45071
AR		 2081 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2082 return 1;
2083
2084 if (data & ~PRED_CMD_IBPB)
2085 return 1;
6441fa61
PB		 2086 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2087 return 1;
15d45071
AR		 2088 if (!data)
2089 break;
2090
2091 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2092
2093 /*
2094 * For non-nested:
2095 * When it's written (to non-zero) for the first time, pass
2096 * it through.
2097 *
2098 * For nested:
2099 * The handling of the MSR bitmap for L2 guests is done in
4d516fe7 2100 * nested_vmx_prepare_msr_bitmap. We should not touch the
15d45071
AR		 2101 * vmcs02.msr_bitmap here since it gets completely overwritten
2102 * in the merging.
2103 */
2104 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2105 MSR_TYPE_W);
2106 break;
468d472f 2107 case MSR_IA32_CR_PAT:
d28f4290
SC		 2108 if (!kvm_pat_valid(data))
2109 return 1;
2110
142e4be7
SC		 2111 if (is_guest_mode(vcpu) &&
2112 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2113 get_vmcs12(vcpu)->guest_ia32_pat = data;
2114
468d472f
SY		 2115 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2116 vmcs_write64(GUEST_IA32_PAT, data);
2117 vcpu->arch.pat = data;
2118 break;
2119 }
8fe8ab46 2120 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2121 break;
ba904635
WA		 2122 case MSR_IA32_TSC_ADJUST:
2123 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2124 break;
c45dcc71
AR		 2125 case MSR_IA32_MCG_EXT_CTL:
2126 if ((!msr_info->host_initiated &&
2127 !(to_vmx(vcpu)->msr_ia32_feature_control &
32ad73db 2128 FEAT_CTL_LMCE_ENABLED)) ||
c45dcc71
AR		 2129 (data & ~MCG_EXT_CTL_LMCE_EN))
2130 return 1;
2131 vcpu->arch.mcg_ext_ctl = data;
2132 break;
32ad73db 2133 case MSR_IA32_FEAT_CTL:
37e4c997 2134 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 2135 (to_vmx(vcpu)->msr_ia32_feature_control &
32ad73db 2136 FEAT_CTL_LOCKED && !msr_info->host_initiated))
cae50139 2137 return 1;
3b84080b 2138 vmx->msr_ia32_feature_control = data;
cae50139
JK		 2139 if (msr_info->host_initiated && data == 0)
2140 vmx_leave_nested(vcpu);
2141 break;
2142 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 2143 if (!msr_info->host_initiated)
2144 return 1; /* they are read-only */
2145 if (!nested_vmx_allowed(vcpu))
2146 return 1;
2147 return vmx_set_vmx_msr(vcpu, msr_index, data);
bf8c55d8
CP		 2148 case MSR_IA32_RTIT_CTL:
2149 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 2150 vmx_rtit_ctl_check(vcpu, data) ||
2151 vmx->nested.vmxon)
bf8c55d8
CP		 2152 return 1;
2153 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2154 vmx->pt_desc.guest.ctl = data;
b08c2896 2155 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 2156 break;
2157 case MSR_IA32_RTIT_STATUS:
e348ac7c
SC		 2158 if (!pt_can_write_msr(vmx))
2159 return 1;
2160 if (data & MSR_IA32_RTIT_STATUS_MASK)
bf8c55d8
CP		 2161 return 1;
2162 vmx->pt_desc.guest.status = data;
2163 break;
2164 case MSR_IA32_RTIT_CR3_MATCH:
e348ac7c
SC		 2165 if (!pt_can_write_msr(vmx))
2166 return 1;
2167 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2168 PT_CAP_cr3_filtering))
bf8c55d8
CP		 2169 return 1;
2170 vmx->pt_desc.guest.cr3_match = data;
2171 break;
2172 case MSR_IA32_RTIT_OUTPUT_BASE:
e348ac7c
SC		 2173 if (!pt_can_write_msr(vmx))
2174 return 1;
2175 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2176 PT_CAP_topa_output) &&
2177 !intel_pt_validate_cap(vmx->pt_desc.caps,
2178 PT_CAP_single_range_output))
2179 return 1;
2180 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
bf8c55d8
CP		 2181 return 1;
2182 vmx->pt_desc.guest.output_base = data;
2183 break;
2184 case MSR_IA32_RTIT_OUTPUT_MASK:
e348ac7c
SC		 2185 if (!pt_can_write_msr(vmx))
2186 return 1;
2187 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2188 PT_CAP_topa_output) &&
2189 !intel_pt_validate_cap(vmx->pt_desc.caps,
2190 PT_CAP_single_range_output))
bf8c55d8
CP		 2191 return 1;
2192 vmx->pt_desc.guest.output_mask = data;
2193 break;
2194 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
e348ac7c
SC		 2195 if (!pt_can_write_msr(vmx))
2196 return 1;
bf8c55d8 2197 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
e348ac7c
SC		 2198 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2199 PT_CAP_num_address_ranges))
bf8c55d8 2200 return 1;
fe6ed369 2201 if (is_noncanonical_address(data, vcpu))
bf8c55d8
CP		 2202 return 1;
2203 if (index % 2)
2204 vmx->pt_desc.guest.addr_b[index / 2] = data;
2205 else
2206 vmx->pt_desc.guest.addr_a[index / 2] = data;
2207 break;
4e47c7a6 2208 case MSR_TSC_AUX:
d6321d49
RK		 2209 if (!msr_info->host_initiated &&
2210 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2211 return 1;
2212 /* Check reserved bit, higher 32 bits should be zero */
2213 if ((data >> 32) != 0)
2214 return 1;
c11f83e0
PB		 2215 goto find_shared_msr;
2216
6aa8b732 2217 default:
c11f83e0 2218 find_shared_msr:
8b9cf98c 2219 msr = find_msr_entry(vmx, msr_index);
b07a5c53
PB		 2220 if (msr)
2221 ret = vmx_set_guest_msr(vmx, msr, data);
2222 else
2223 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2224 }
2225
2cc51560 2226 return ret;
6aa8b732
AK		 2227}
2228
5fdbf976 2229static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2230{
cb3c1e2f
SC		 2231 kvm_register_mark_available(vcpu, reg);
2232
5fdbf976
MT		 2233 switch (reg) {
2234 case VCPU_REGS_RSP:
2235 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2236 break;
2237 case VCPU_REGS_RIP:
2238 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2239 break;
6de4f3ad
AK		 2240 case VCPU_EXREG_PDPTR:
2241 if (enable_ept)
2242 ept_save_pdptrs(vcpu);
2243 break;
34059c25
SC		 2244 case VCPU_EXREG_CR3:
2245 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2246 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2247 break;
5fdbf976 2248 default:
34059c25 2249 WARN_ON_ONCE(1);
5fdbf976
MT		 2250 break;
2251 }
6aa8b732
AK		 2252}
2253
6aa8b732
AK		 2254static __init int cpu_has_kvm_support(void)
2255{
6210e37b 2256 return cpu_has_vmx();
6aa8b732
AK		 2257}
2258
2259static __init int vmx_disabled_by_bios(void)
2260{
a4d0b2fd
SC		 2261 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2262 !boot_cpu_has(X86_FEATURE_VMX);
6aa8b732
AK		 2263}
2264
7725b894
DX		 2265static void kvm_cpu_vmxon(u64 addr)
2266{
fe0e80be 2267 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2268 intel_pt_handle_vmx(1);
2269
4b1e5478 2270 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2271}
2272
13a34e06 2273static int hardware_enable(void)
6aa8b732
AK		 2274{
2275 int cpu = raw_smp_processor_id();
2276 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 2277
1e02ce4c 2278 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2279 return -EBUSY;
2280
773e8a04
VK		 2281 /*
2282 * This can happen if we hot-added a CPU but failed to allocate
2283 * VP assist page for it.
2284 */
2285 if (static_branch_unlikely(&enable_evmcs) &&
2286 !hv_get_vp_assist_page(cpu))
2287 return -EFAULT;
2288
d462b819 2289 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2290 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2291 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2292
2293 /*
2294 * Now we can enable the vmclear operation in kdump
2295 * since the loaded_vmcss_on_cpu list on this cpu
2296 * has been initialized.
2297 *
2298 * Though the cpu is not in VMX operation now, there
2299 * is no problem to enable the vmclear operation
2300 * for the loaded_vmcss_on_cpu list is empty!
2301 */
2302 crash_enable_local_vmclear(cpu);
2303
fe0e80be 2304 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2305 if (enable_ept)
2306 ept_sync_global();
10474ae8
AG		 2307
2308 return 0;
6aa8b732
AK		 2309}
2310
d462b819 2311static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2312{
2313 int cpu = raw_smp_processor_id();
d462b819 2314 struct loaded_vmcs *v, *n;
543e4243 2315
d462b819
NHE		 2316 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2317 loaded_vmcss_on_cpu_link)
2318 __loaded_vmcs_clear(v);
543e4243
AK		 2319}
2320
710ff4a8
EH		 2321
2322/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2323 * tricks.
2324 */
2325static void kvm_cpu_vmxoff(void)
6aa8b732 2326{
4b1e5478 2327 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2328
2329 intel_pt_handle_vmx(0);
fe0e80be 2330 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2331}
2332
13a34e06 2333static void hardware_disable(void)
710ff4a8 2334{
fe0e80be
DH		 2335 vmclear_local_loaded_vmcss();
2336 kvm_cpu_vmxoff();
710ff4a8
EH		 2337}
2338
1c3d14fe 2339static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2340 u32 msr, u32 *result)
1c3d14fe
YS		 2341{
2342 u32 vmx_msr_low, vmx_msr_high;
2343 u32 ctl = ctl_min | ctl_opt;
2344
2345 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2346
2347 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2348 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2349
2350 /* Ensure minimum (required) set of control bits are supported. */
2351 if (ctl_min & ~ctl)
002c7f7c 2352 return -EIO;
1c3d14fe
YS		 2353
2354 *result = ctl;
2355 return 0;
2356}
2357
7caaa711
SC		 2358static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2359 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2360{
2361 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2362 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2363 u32 _pin_based_exec_control = 0;
2364 u32 _cpu_based_exec_control = 0;
f78e0e2e 2365 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2366 u32 _vmexit_control = 0;
2367 u32 _vmentry_control = 0;
2368
1389309c 2369 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2370 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2371#ifdef CONFIG_X86_64
2372 CPU_BASED_CR8_LOAD_EXITING |
2373 CPU_BASED_CR8_STORE_EXITING |
2374#endif
d56f546d
SY		 2375 CPU_BASED_CR3_LOAD_EXITING |
2376 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2377 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2378 CPU_BASED_MOV_DR_EXITING |
5e3d394f 2379 CPU_BASED_USE_TSC_OFFSETTING |
4d5422ce
WL		 2380 CPU_BASED_MWAIT_EXITING |
2381 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2382 CPU_BASED_INVLPG_EXITING |
2383 CPU_BASED_RDPMC_EXITING;
443381a8 2384
f78e0e2e 2385 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2386 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2387 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2388 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2389 &_cpu_based_exec_control) < 0)
002c7f7c 2390 return -EIO;
6e5d865c
YS		 2391#ifdef CONFIG_X86_64
2392 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2393 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2394 ~CPU_BASED_CR8_STORE_EXITING;
2395#endif
f78e0e2e 2396 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2397 min2 = 0;
2398 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2399 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2400 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2401 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2402 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2403 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2404 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2405 SECONDARY_EXEC_DESC |
ad756a16 2406 SECONDARY_EXEC_RDTSCP |
83d4c286 2407 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2408 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2409 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2410 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2411 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2412 SECONDARY_EXEC_RDSEED_EXITING |
2413 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2414 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2415 SECONDARY_EXEC_TSC_SCALING |
e69e72fa 2416 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
f99e3daf
CP		 2417 SECONDARY_EXEC_PT_USE_GPA |
2418 SECONDARY_EXEC_PT_CONCEAL_VMX |
0b665d30
SC		 2419 SECONDARY_EXEC_ENABLE_VMFUNC |
2420 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2421 if (adjust_vmx_controls(min2, opt2,
2422 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2423 &_cpu_based_2nd_exec_control) < 0)
2424 return -EIO;
2425 }
2426#ifndef CONFIG_X86_64
2427 if (!(_cpu_based_2nd_exec_control &
2428 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2429 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2430#endif
83d4c286
YZ		 2431
2432 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2433 _cpu_based_2nd_exec_control &= ~(
8d14695f 2434 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2435 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2436 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2437
61f1dd90 2438 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2439 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2440
d56f546d 2441 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2442 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2443 enabled */
5fff7d27
GN		 2444 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2445 CPU_BASED_CR3_STORE_EXITING |
2446 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2447 } else if (vmx_cap->ept) {
2448 vmx_cap->ept = 0;
61f1dd90
WL		 2449 pr_warn_once("EPT CAP should not exist if not support "
2450 "1-setting enable EPT VM-execution control\n");
2451 }
2452 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2453 vmx_cap->vpid) {
2454 vmx_cap->vpid = 0;
61f1dd90
WL		 2455 pr_warn_once("VPID CAP should not exist if not support "
2456 "1-setting enable VPID VM-execution control\n");
d56f546d 2457 }
1c3d14fe 2458
91fa0f8e 2459 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2460#ifdef CONFIG_X86_64
2461 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2462#endif
c73da3fc 2463 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2464 VM_EXIT_LOAD_IA32_PAT |
2465 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2466 VM_EXIT_CLEAR_BNDCFGS |
2467 VM_EXIT_PT_CONCEAL_PIP |
2468 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2469 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2470 &_vmexit_control) < 0)
002c7f7c 2471 return -EIO;
1c3d14fe 2472
8a1b4392
PB		 2473 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2474 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2475 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2476 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2477 &_pin_based_exec_control) < 0)
2478 return -EIO;
2479
1c17c3e6
PB		 2480 if (cpu_has_broken_vmx_preemption_timer())
2481 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2482 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2483 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2484 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2485
c845f9c6 2486 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2487 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2488 VM_ENTRY_LOAD_IA32_PAT |
2489 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2490 VM_ENTRY_LOAD_BNDCFGS |
2491 VM_ENTRY_PT_CONCEAL_PIP |
2492 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2493 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2494 &_vmentry_control) < 0)
002c7f7c 2495 return -EIO;
6aa8b732 2496
c73da3fc
SC		 2497 /*
2498 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2499 * can't be used due to an errata where VM Exit may incorrectly clear
2500 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2501 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2502 */
2503 if (boot_cpu_data.x86 == 0x6) {
2504 switch (boot_cpu_data.x86_model) {
2505 case 26: /* AAK155 */
2506 case 30: /* AAP115 */
2507 case 37: /* AAT100 */
2508 case 44: /* BC86,AAY89,BD102 */
2509 case 46: /* BA97 */
85ba2b16 2510 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2511 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2512 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2513 "does not work properly. Using workaround\n");
2514 break;
2515 default:
2516 break;
2517 }
2518 }
2519
2520
c68876fd 2521 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2522
2523 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2524 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2525 return -EIO;
1c3d14fe
YS		 2526
2527#ifdef CONFIG_X86_64
2528 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2529 if (vmx_msr_high & (1u<<16))
002c7f7c 2530 return -EIO;
1c3d14fe
YS		 2531#endif
2532
2533 /* Require Write-Back (WB) memory type for VMCS accesses. */
2534 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2535 return -EIO;
1c3d14fe 2536
002c7f7c 2537 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2538 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2539 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2540
2307af1c 2541 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2542
002c7f7c
YS		 2543 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2544 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2545 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2546 vmcs_conf->vmexit_ctrl = _vmexit_control;
2547 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2548
773e8a04
VK		 2549 if (static_branch_unlikely(&enable_evmcs))
2550 evmcs_sanitize_exec_ctrls(vmcs_conf);
2551
1c3d14fe 2552 return 0;
c68876fd 2553}
6aa8b732 2554
41836839 2555struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2556{
2557 int node = cpu_to_node(cpu);
2558 struct page *pages;
2559 struct vmcs *vmcs;
2560
41836839 2561 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2562 if (!pages)
2563 return NULL;
2564 vmcs = page_address(pages);
1c3d14fe 2565 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2566
2567 /* KVM supports Enlightened VMCS v1 only */
2568 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2569 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2570 else
392b2f25 2571 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2572
491a6038
LA		 2573 if (shadow)
2574 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2575 return vmcs;
2576}
2577
89b0c9f5 2578void free_vmcs(struct vmcs *vmcs)
6aa8b732 2579{
1c3d14fe 2580 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2581}
2582
d462b819
NHE		 2583/*
2584 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2585 */
89b0c9f5 2586void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2587{
2588 if (!loaded_vmcs->vmcs)
2589 return;
2590 loaded_vmcs_clear(loaded_vmcs);
2591 free_vmcs(loaded_vmcs->vmcs);
2592 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2593 if (loaded_vmcs->msr_bitmap)
2594 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2595 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2596}
2597
89b0c9f5 2598int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2599{
491a6038 2600 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2601 if (!loaded_vmcs->vmcs)
2602 return -ENOMEM;
2603
2604 loaded_vmcs->shadow_vmcs = NULL;
804939ea 2605 loaded_vmcs->hv_timer_soft_disabled = false;
f21f165e 2606 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2607
2608 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2609 loaded_vmcs->msr_bitmap = (unsigned long *)
2610 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2611 if (!loaded_vmcs->msr_bitmap)
2612 goto out_vmcs;
2613 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2614
1f008e11
AB		 2615 if (IS_ENABLED(CONFIG_HYPERV) &&
2616 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2617 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2618 struct hv_enlightened_vmcs *evmcs =
2619 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2620
2621 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2622 }
904e14fb 2623 }
d7ee039e
SC		 2624
2625 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
3af80fec
SC		 2626 memset(&loaded_vmcs->controls_shadow, 0,
2627 sizeof(struct vmcs_controls_shadow));
d7ee039e 2628
f21f165e 2629 return 0;
904e14fb
PB		 2630
2631out_vmcs:
2632 free_loaded_vmcs(loaded_vmcs);
2633 return -ENOMEM;
f21f165e
PB		 2634}
2635
39959588 2636static void free_kvm_area(void)
6aa8b732
AK		 2637{
2638 int cpu;
2639
3230bb47 2640 for_each_possible_cpu(cpu) {
6aa8b732 2641 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2642 per_cpu(vmxarea, cpu) = NULL;
2643 }
6aa8b732
AK		 2644}
2645
6aa8b732
AK		 2646static __init int alloc_kvm_area(void)
2647{
2648 int cpu;
2649
3230bb47 2650 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2651 struct vmcs *vmcs;
2652
41836839 2653 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2654 if (!vmcs) {
2655 free_kvm_area();
2656 return -ENOMEM;
2657 }
2658
2307af1c
LA		 2659 /*
2660 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2661 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2662 * revision_id reported by MSR_IA32_VMX_BASIC.
2663 *
312a4661 2664 * However, even though not explicitly documented by
2307af1c
LA		 2665 * TLFS, VMXArea passed as VMXON argument should
2666 * still be marked with revision_id reported by
2667 * physical CPU.
2668 */
2669 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2670 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2671
6aa8b732
AK		 2672 per_cpu(vmxarea, cpu) = vmcs;
2673 }
2674 return 0;
2675}
2676
91b0aa2c 2677static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2678 struct kvm_segment *save)
6aa8b732 2679{
d99e4152
GN		 2680 if (!emulate_invalid_guest_state) {
2681 /*
2682 * CS and SS RPL should be equal during guest entry according
2683 * to VMX spec, but in reality it is not always so. Since vcpu
2684 * is in the middle of the transition from real mode to
2685 * protected mode it is safe to assume that RPL 0 is a good
2686 * default value.
2687 */
2688 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2689 save->selector &= ~SEGMENT_RPL_MASK;
2690 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2691 save->s = 1;
6aa8b732 2692 }
d99e4152 2693 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2694}
2695
2696static void enter_pmode(struct kvm_vcpu *vcpu)
2697{
2698 unsigned long flags;
a89a8fb9 2699 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2700
d99e4152
GN		 2701 /*
2702 * Update real mode segment cache. It may be not up-to-date if sement
2703 * register was written while vcpu was in a guest mode.
2704 */
2705 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2706 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2707 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2708 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2709 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2710 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2711
7ffd92c5 2712 vmx->rmode.vm86_active = 0;
6aa8b732 2713
f5f7b2fe 2714 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2715
2716 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2717 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2718 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2719 vmcs_writel(GUEST_RFLAGS, flags);
2720
66aee91a
RR		 2721 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2722 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2723
2724 update_exception_bitmap(vcpu);
2725
91b0aa2c
GN		 2726 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2727 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2728 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2729 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2730 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2731 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2732}
2733
f5f7b2fe 2734static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2735{
772e0318 2736 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2737 struct kvm_segment var = *save;
2738
2739 var.dpl = 0x3;
2740 if (seg == VCPU_SREG_CS)
2741 var.type = 0x3;
2742
2743 if (!emulate_invalid_guest_state) {
2744 var.selector = var.base >> 4;
2745 var.base = var.base & 0xffff0;
2746 var.limit = 0xffff;
2747 var.g = 0;
2748 var.db = 0;
2749 var.present = 1;
2750 var.s = 1;
2751 var.l = 0;
2752 var.unusable = 0;
2753 var.type = 0x3;
2754 var.avl = 0;
2755 if (save->base & 0xf)
2756 printk_once(KERN_WARNING "kvm: segment base is not "
2757 "paragraph aligned when entering "
2758 "protected mode (seg=%d)", seg);
2759 }
6aa8b732 2760
d99e4152 2761 vmcs_write16(sf->selector, var.selector);
96794e4e 2762 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2763 vmcs_write32(sf->limit, var.limit);
2764 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2765}
2766
2767static void enter_rmode(struct kvm_vcpu *vcpu)
2768{
2769 unsigned long flags;
a89a8fb9 2770 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2771 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2772
f5f7b2fe
AK		 2773 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2774 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2775 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2776 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2777 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2778 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2779 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2780
7ffd92c5 2781 vmx->rmode.vm86_active = 1;
6aa8b732 2782
776e58ea
GN		 2783 /*
2784 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2785 * vcpu. Warn the user that an update is overdue.
776e58ea 2786 */
40bbb9d0 2787 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2788 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2789 "called before entering vcpu\n");
776e58ea 2790
2fb92db1
AK		 2791 vmx_segment_cache_clear(vmx);
2792
40bbb9d0 2793 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2794 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2795 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2796
2797 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2798 vmx->rmode.save_rflags = flags;
6aa8b732 2799
053de044 2800 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2801
2802 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2803 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2804 update_exception_bitmap(vcpu);
2805
d99e4152
GN		 2806 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2807 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2808 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2809 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2810 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2811 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2812
8668a3c4 2813 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2814}
2815
97b7ead3 2816void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2817{
2818 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2819 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2820
2821 if (!msr)
2822 return;
401d10de 2823
f6801dff 2824 vcpu->arch.efer = efer;
401d10de 2825 if (efer & EFER_LMA) {
2961e876 2826 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2827 msr->data = efer;
2828 } else {
2961e876 2829 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2830
2831 msr->data = efer & ~EFER_LME;
2832 }
2833 setup_msrs(vmx);
2834}
2835
05b3e0c2 2836#ifdef CONFIG_X86_64
6aa8b732
AK		 2837
2838static void enter_lmode(struct kvm_vcpu *vcpu)
2839{
2840 u32 guest_tr_ar;
2841
2fb92db1
AK		 2842 vmx_segment_cache_clear(to_vmx(vcpu));
2843
6aa8b732 2844 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2845 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2846 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2847 __func__);
6aa8b732 2848 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2849 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2850 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2851 }
da38f438 2852 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2853}
2854
2855static void exit_lmode(struct kvm_vcpu *vcpu)
2856{
2961e876 2857 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2858 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2859}
2860
2861#endif
2862
faff8758
JS		 2863static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2864{
2865 int vpid = to_vmx(vcpu)->vpid;
2866
2867 if (!vpid_sync_vcpu_addr(vpid, addr))
2868 vpid_sync_context(vpid);
2869
2870 /*
2871 * If VPIDs are not supported or enabled, then the above is a no-op.
2872 * But we don't really need a TLB flush in that case anyway, because
2873 * each VM entry/exit includes an implicit flush when VPID is 0.
2874 */
2875}
2876
e8467fda
AK		 2877static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2878{
2879 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2880
2881 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2882 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2883}
2884
25c4c276 2885static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2886{
fc78f519
AK		 2887 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2888
2889 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2890 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2891}
2892
1439442c
SY		 2893static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2894{
d0d538b9
GN		 2895 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2896
cb3c1e2f 2897 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
6de4f3ad
AK		 2898 return;
2899
bf03d4f9 2900 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2901 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2902 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2903 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2904 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2905 }
2906}
2907
97b7ead3 2908void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2909{
d0d538b9
GN		 2910 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2911
bf03d4f9 2912 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2913 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2914 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2915 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2916 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2917 }
6de4f3ad 2918
cb3c1e2f 2919 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
8f5d549f
AK		 2920}
2921
1439442c
SY		 2922static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2923 unsigned long cr0,
2924 struct kvm_vcpu *vcpu)
2925{
2183f564
SC		 2926 struct vcpu_vmx *vmx = to_vmx(vcpu);
2927
cb3c1e2f 2928 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
34059c25 2929 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
1439442c
SY		 2930 if (!(cr0 & X86_CR0_PG)) {
2931 /* From paging/starting to nonpaging */
2183f564
SC		 2932 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2933 CPU_BASED_CR3_STORE_EXITING);
1439442c 2934 vcpu->arch.cr0 = cr0;
fc78f519 2935 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2936 } else if (!is_paging(vcpu)) {
2937 /* From nonpaging to paging */
2183f564
SC		 2938 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2939 CPU_BASED_CR3_STORE_EXITING);
1439442c 2940 vcpu->arch.cr0 = cr0;
fc78f519 2941 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2942 }
95eb84a7
SY		 2943
2944 if (!(cr0 & X86_CR0_WP))
2945 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2946}
2947
97b7ead3 2948void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2949{
7ffd92c5 2950 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2951 unsigned long hw_cr0;
2952
3de6347b 2953 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2954 if (enable_unrestricted_guest)
5037878e 2955 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2956 else {
5037878e 2957 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2958
218e763f
GN		 2959 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2960 enter_pmode(vcpu);
6aa8b732 2961
218e763f
GN		 2962 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2963 enter_rmode(vcpu);
2964 }
6aa8b732 2965
05b3e0c2 2966#ifdef CONFIG_X86_64
f6801dff 2967 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2968 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2969 enter_lmode(vcpu);
707d92fa 2970 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2971 exit_lmode(vcpu);
2972 }
2973#endif
2974
b4d18517 2975 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2976 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2977
6aa8b732 2978 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2979 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2980 vcpu->arch.cr0 = cr0;
14168786
GN		 2981
2982 /* depends on vcpu->arch.cr0 to be set to a new value */
2983 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2984}
2985
855feb67
YZ		 2986static int get_ept_level(struct kvm_vcpu *vcpu)
2987{
148d735e
SC		 2988 /* Nested EPT currently only supports 4-level walks. */
2989 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
2990 return 4;
855feb67
YZ		 2991 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2992 return 5;
2993 return 4;
2994}
2995
89b0c9f5 2996u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2997{
855feb67
YZ		 2998 u64 eptp = VMX_EPTP_MT_WB;
2999
3000 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 3001
995f00a6
PF		 3002 if (enable_ept_ad_bits &&
3003 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 3004 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 3005 eptp |= (root_hpa & PAGE_MASK);
3006
3007 return eptp;
3008}
3009
97b7ead3 3010void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 3011{
877ad952 3012 struct kvm *kvm = vcpu->kvm;
04f11ef4 3013 bool update_guest_cr3 = true;
1439442c
SY		 3014 unsigned long guest_cr3;
3015 u64 eptp;
3016
3017 guest_cr3 = cr3;
089d034e 3018 if (enable_ept) {
995f00a6 3019 eptp = construct_eptp(vcpu, cr3);
1439442c 3020 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 3021
3022 if (kvm_x86_ops->tlb_remote_flush) {
3023 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3024 to_vmx(vcpu)->ept_pointer = eptp;
3025 to_kvm_vmx(kvm)->ept_pointers_match
3026 = EPT_POINTERS_CHECK;
3027 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3028 }
3029
04f11ef4
SC		 3030 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3031 if (is_guest_mode(vcpu))
3032 update_guest_cr3 = false;
b17b7436 3033 else if (!enable_unrestricted_guest && !is_paging(vcpu))
877ad952 3034 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
b17b7436
SC		 3035 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3036 guest_cr3 = vcpu->arch.cr3;
3037 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3038 update_guest_cr3 = false;
7c93be44 3039 ept_load_pdptrs(vcpu);
1439442c
SY		 3040 }
3041
04f11ef4
SC		 3042 if (update_guest_cr3)
3043 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3044}
3045
97b7ead3 3046int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3047{
fe7f895d 3048 struct vcpu_vmx *vmx = to_vmx(vcpu);
085e68ee
BS		 3049 /*
3050 * Pass through host's Machine Check Enable value to hw_cr4, which
3051 * is in force while we are in guest mode. Do not let guests control
3052 * this bit, even if host CR4.MCE == 0.
3053 */
5dc1f044
SC		 3054 unsigned long hw_cr4;
3055
3056 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3057 if (enable_unrestricted_guest)
3058 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
fe7f895d 3059 else if (vmx->rmode.vm86_active)
5dc1f044
SC		 3060 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3061 else
3062 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 3063
64f7a115
SC		 3064 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3065 if (cr4 & X86_CR4_UMIP) {
fe7f895d 3066 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
64f7a115
SC		 3067 hw_cr4 &= ~X86_CR4_UMIP;
3068 } else if (!is_guest_mode(vcpu) ||
fe7f895d
SC		 3069 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3070 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3071 }
64f7a115 3072 }
0367f205 3073
5e1746d6
NHE		 3074 if (cr4 & X86_CR4_VMXE) {
3075 /*
3076 * To use VMXON (and later other VMX instructions), a guest
3077 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3078 * So basically the check on whether to allow nested VMX
5bea5123
PB		 3079 * is here. We operate under the default treatment of SMM,
3080 * so VMX cannot be enabled under SMM.
5e1746d6 3081 */
5bea5123 3082 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 3083 return 1;
1a0d74e6 3084 }
3899152c 3085
fe7f895d 3086 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 3087 return 1;
3088
ad312c7c 3089 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 3090
3091 if (!enable_unrestricted_guest) {
3092 if (enable_ept) {
3093 if (!is_paging(vcpu)) {
3094 hw_cr4 &= ~X86_CR4_PAE;
3095 hw_cr4 |= X86_CR4_PSE;
3096 } else if (!(cr4 & X86_CR4_PAE)) {
3097 hw_cr4 &= ~X86_CR4_PAE;
3098 }
bc23008b 3099 }
1439442c 3100
656ec4a4 3101 /*
ddba2628
HH		 3102 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3103 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3104 * to be manually disabled when guest switches to non-paging
3105 * mode.
3106 *
3107 * If !enable_unrestricted_guest, the CPU is always running
3108 * with CR0.PG=1 and CR4 needs to be modified.
3109 * If enable_unrestricted_guest, the CPU automatically
3110 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 3111 */
5dc1f044
SC		 3112 if (!is_paging(vcpu))
3113 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3114 }
656ec4a4 3115
1439442c
SY		 3116 vmcs_writel(CR4_READ_SHADOW, cr4);
3117 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3118 return 0;
6aa8b732
AK		 3119}
3120
97b7ead3 3121void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 3122{
a9179499 3123 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3124 u32 ar;
3125
c6ad1153 3126 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3127 *var = vmx->rmode.segs[seg];
a9179499 3128 if (seg == VCPU_SREG_TR
2fb92db1 3129 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3130 return;
1390a28b
AK		 3131 var->base = vmx_read_guest_seg_base(vmx, seg);
3132 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3133 return;
a9179499 3134 }
2fb92db1
AK		 3135 var->base = vmx_read_guest_seg_base(vmx, seg);
3136 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3137 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3138 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3139 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3140 var->type = ar & 15;
3141 var->s = (ar >> 4) & 1;
3142 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3143 /*
3144 * Some userspaces do not preserve unusable property. Since usable
3145 * segment has to be present according to VMX spec we can use present
3146 * property to amend userspace bug by making unusable segment always
3147 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3148 * segment as unusable.
3149 */
3150 var->present = !var->unusable;
6aa8b732
AK		 3151 var->avl = (ar >> 12) & 1;
3152 var->l = (ar >> 13) & 1;
3153 var->db = (ar >> 14) & 1;
3154 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3155}
3156
a9179499
AK		 3157static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3158{
a9179499
AK		 3159 struct kvm_segment s;
3160
3161 if (to_vmx(vcpu)->rmode.vm86_active) {
3162 vmx_get_segment(vcpu, &s, seg);
3163 return s.base;
3164 }
2fb92db1 3165 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3166}
3167
97b7ead3 3168int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3169{
b09408d0
MT		 3170 struct vcpu_vmx *vmx = to_vmx(vcpu);
3171
ae9fedc7 3172 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3173 return 0;
ae9fedc7
PB		 3174 else {
3175 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3176 return VMX_AR_DPL(ar);
69c73028 3177 }
69c73028
AK		 3178}
3179
653e3108 3180static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3181{
6aa8b732
AK		 3182 u32 ar;
3183
f0495f9b 3184 if (var->unusable || !var->present)
6aa8b732
AK		 3185 ar = 1 << 16;
3186 else {
3187 ar = var->type & 15;
3188 ar |= (var->s & 1) << 4;
3189 ar |= (var->dpl & 3) << 5;
3190 ar |= (var->present & 1) << 7;
3191 ar |= (var->avl & 1) << 12;
3192 ar |= (var->l & 1) << 13;
3193 ar |= (var->db & 1) << 14;
3194 ar |= (var->g & 1) << 15;
3195 }
653e3108
AK		 3196
3197 return ar;
3198}
3199
97b7ead3 3200void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3201{
7ffd92c5 3202 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3203 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3204
2fb92db1
AK		 3205 vmx_segment_cache_clear(vmx);
3206
1ecd50a9
GN		 3207 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3208 vmx->rmode.segs[seg] = *var;
3209 if (seg == VCPU_SREG_TR)
3210 vmcs_write16(sf->selector, var->selector);
3211 else if (var->s)
3212 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3213 goto out;
653e3108 3214 }
1ecd50a9 3215
653e3108
AK		 3216 vmcs_writel(sf->base, var->base);
3217 vmcs_write32(sf->limit, var->limit);
3218 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3219
3220 /*
3221 * Fix the "Accessed" bit in AR field of segment registers for older
3222 * qemu binaries.
3223 * IA32 arch specifies that at the time of processor reset the
3224 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3225 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3226 * state vmexit when "unrestricted guest" mode is turned on.
3227 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3228 * tree. Newer qemu binaries with that qemu fix would not need this
3229 * kvm hack.
3230 */
3231 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3232 var->type |= 0x1; /* Accessed */
3a624e29 3233
f924d66d 3234 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3235
3236out:
98eb2f8b 3237 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3238}
3239
6aa8b732
AK		 3240static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3241{
2fb92db1 3242 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3243
3244 *db = (ar >> 14) & 1;
3245 *l = (ar >> 13) & 1;
3246}
3247
89a27f4d 3248static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3249{
89a27f4d
GN		 3250 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3251 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3252}
3253
89a27f4d 3254static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3255{
89a27f4d
GN		 3256 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3257 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3258}
3259
89a27f4d 3260static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3261{
89a27f4d
GN		 3262 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3263 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3264}
3265
89a27f4d 3266static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3267{
89a27f4d
GN		 3268 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3269 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3270}
3271
648dfaa7
MG		 3272static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3273{
3274 struct kvm_segment var;
3275 u32 ar;
3276
3277 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3278 var.dpl = 0x3;
0647f4aa
GN		 3279 if (seg == VCPU_SREG_CS)
3280 var.type = 0x3;
648dfaa7
MG		 3281 ar = vmx_segment_access_rights(&var);
3282
3283 if (var.base != (var.selector << 4))
3284 return false;
89efbed0 3285 if (var.limit != 0xffff)
648dfaa7 3286 return false;
07f42f5f 3287 if (ar != 0xf3)
648dfaa7
MG		 3288 return false;
3289
3290 return true;
3291}
3292
3293static bool code_segment_valid(struct kvm_vcpu *vcpu)
3294{
3295 struct kvm_segment cs;
3296 unsigned int cs_rpl;
3297
3298 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3299 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3300
1872a3f4
AK		 3301 if (cs.unusable)
3302 return false;
4d283ec9 3303 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3304 return false;
3305 if (!cs.s)
3306 return false;
4d283ec9 3307 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3308 if (cs.dpl > cs_rpl)
3309 return false;
1872a3f4 3310 } else {
648dfaa7
MG		 3311 if (cs.dpl != cs_rpl)
3312 return false;
3313 }
3314 if (!cs.present)
3315 return false;
3316
3317 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3318 return true;
3319}
3320
3321static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3322{
3323 struct kvm_segment ss;
3324 unsigned int ss_rpl;
3325
3326 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3327 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3328
1872a3f4
AK		 3329 if (ss.unusable)
3330 return true;
3331 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3332 return false;
3333 if (!ss.s)
3334 return false;
3335 if (ss.dpl != ss_rpl) /* DPL != RPL */
3336 return false;
3337 if (!ss.present)
3338 return false;
3339
3340 return true;
3341}
3342
3343static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3344{
3345 struct kvm_segment var;
3346 unsigned int rpl;
3347
3348 vmx_get_segment(vcpu, &var, seg);
b32a9918 3349 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3350
1872a3f4
AK		 3351 if (var.unusable)
3352 return true;
648dfaa7
MG		 3353 if (!var.s)
3354 return false;
3355 if (!var.present)
3356 return false;
4d283ec9 3357 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3358 if (var.dpl < rpl) /* DPL < RPL */
3359 return false;
3360 }
3361
3362 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3363 * rights flags
3364 */
3365 return true;
3366}
3367
3368static bool tr_valid(struct kvm_vcpu *vcpu)
3369{
3370 struct kvm_segment tr;
3371
3372 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3373
1872a3f4
AK		 3374 if (tr.unusable)
3375 return false;
b32a9918 3376 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3377 return false;
1872a3f4 3378 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3379 return false;
3380 if (!tr.present)
3381 return false;
3382
3383 return true;
3384}
3385
3386static bool ldtr_valid(struct kvm_vcpu *vcpu)
3387{
3388 struct kvm_segment ldtr;
3389
3390 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3391
1872a3f4
AK		 3392 if (ldtr.unusable)
3393 return true;
b32a9918 3394 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3395 return false;
3396 if (ldtr.type != 2)
3397 return false;
3398 if (!ldtr.present)
3399 return false;
3400
3401 return true;
3402}
3403
3404static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3405{
3406 struct kvm_segment cs, ss;
3407
3408 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3409 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3410
b32a9918
NA		 3411 return ((cs.selector & SEGMENT_RPL_MASK) ==
3412 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3413}
3414
3415/*
3416 * Check if guest state is valid. Returns true if valid, false if
3417 * not.
3418 * We assume that registers are always usable
3419 */
3420static bool guest_state_valid(struct kvm_vcpu *vcpu)
3421{
c5e97c80
GN		 3422 if (enable_unrestricted_guest)
3423 return true;
3424
648dfaa7 3425 /* real mode guest state checks */
f13882d8 3426 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3427 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3428 return false;
3429 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3430 return false;
3431 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3432 return false;
3433 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3434 return false;
3435 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3436 return false;
3437 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3438 return false;
3439 } else {
3440 /* protected mode guest state checks */
3441 if (!cs_ss_rpl_check(vcpu))
3442 return false;
3443 if (!code_segment_valid(vcpu))
3444 return false;
3445 if (!stack_segment_valid(vcpu))
3446 return false;
3447 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3448 return false;
3449 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3450 return false;
3451 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3452 return false;
3453 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3454 return false;
3455 if (!tr_valid(vcpu))
3456 return false;
3457 if (!ldtr_valid(vcpu))
3458 return false;
3459 }
3460 /* TODO:
3461 * - Add checks on RIP
3462 * - Add checks on RFLAGS
3463 */
3464
3465 return true;
3466}
3467
d77c26fc 3468static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3469{
40dcaa9f 3470 gfn_t fn;
195aefde 3471 u16 data = 0;
1f755a82 3472 int idx, r;
6aa8b732 3473
40dcaa9f 3474 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3475 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3476 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3477 if (r < 0)
10589a46 3478 goto out;
195aefde 3479 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3480 r = kvm_write_guest_page(kvm, fn++, &data,
3481 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3482 if (r < 0)
10589a46 3483 goto out;
195aefde
IE		 3484 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3485 if (r < 0)
10589a46 3486 goto out;
195aefde
IE		 3487 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3488 if (r < 0)
10589a46 3489 goto out;
195aefde 3490 data = ~0;
10589a46
MT		 3491 r = kvm_write_guest_page(kvm, fn, &data,
3492 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3493 sizeof(u8));
10589a46 3494out:
40dcaa9f 3495 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3496 return r;
6aa8b732
AK		 3497}
3498
b7ebfb05
SY		 3499static int init_rmode_identity_map(struct kvm *kvm)
3500{
40bbb9d0 3501 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
2a5755bb 3502 int i, r = 0;
ba049e93 3503 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3504 u32 tmp;
3505
40bbb9d0 3506 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3507 mutex_lock(&kvm->slots_lock);
3508
40bbb9d0 3509 if (likely(kvm_vmx->ept_identity_pagetable_done))
2a5755bb 3510 goto out;
a255d479 3511
40bbb9d0
SC		 3512 if (!kvm_vmx->ept_identity_map_addr)
3513 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3514 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3515
d8a6e365 3516 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3517 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3518 if (r < 0)
2a5755bb 3519 goto out;
a255d479 3520
b7ebfb05
SY		 3521 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3522 if (r < 0)
3523 goto out;
3524 /* Set up identity-mapping pagetable for EPT in real mode */
3525 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3526 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3527 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3528 r = kvm_write_guest_page(kvm, identity_map_pfn,
3529 &tmp, i * sizeof(tmp), sizeof(tmp));
3530 if (r < 0)
3531 goto out;
3532 }
40bbb9d0 3533 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3534
b7ebfb05 3535out:
a255d479 3536 mutex_unlock(&kvm->slots_lock);
f51770ed 3537 return r;
b7ebfb05
SY		 3538}
3539
6aa8b732
AK		 3540static void seg_setup(int seg)
3541{
772e0318 3542 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3543 unsigned int ar;
6aa8b732
AK		 3544
3545 vmcs_write16(sf->selector, 0);
3546 vmcs_writel(sf->base, 0);
3547 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3548 ar = 0x93;
3549 if (seg == VCPU_SREG_CS)
3550 ar |= 0x08; /* code segment */
3a624e29
NK		 3551
3552 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3553}
3554
f78e0e2e
SY		 3555static int alloc_apic_access_page(struct kvm *kvm)
3556{
4484141a 3557 struct page *page;
f78e0e2e
SY		 3558 int r = 0;
3559
79fac95e 3560 mutex_lock(&kvm->slots_lock);
c24ae0dc 3561 if (kvm->arch.apic_access_page_done)
f78e0e2e 3562 goto out;
1d8007bd
PB		 3563 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3564 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3565 if (r)
3566 goto out;
72dc67a6 3567
73a6d941 3568 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3569 if (is_error_page(page)) {
3570 r = -EFAULT;
3571 goto out;
3572 }
3573
c24ae0dc
TC		 3574 /*
3575 * Do not pin the page in memory, so that memory hot-unplug
3576 * is able to migrate it.
3577 */
3578 put_page(page);
3579 kvm->arch.apic_access_page_done = true;
f78e0e2e 3580out:
79fac95e 3581 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3582 return r;
3583}
3584
97b7ead3 3585int allocate_vpid(void)
2384d2b3
SY		 3586{
3587 int vpid;
3588
919818ab 3589 if (!enable_vpid)
991e7a0e 3590 return 0;
2384d2b3
SY		 3591 spin_lock(&vmx_vpid_lock);
3592 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3593 if (vpid < VMX_NR_VPIDS)
2384d2b3 3594 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3595 else
3596 vpid = 0;
2384d2b3 3597 spin_unlock(&vmx_vpid_lock);
991e7a0e 3598 return vpid;
2384d2b3
SY		 3599}
3600
97b7ead3 3601void free_vpid(int vpid)
cdbecfc3 3602{
991e7a0e 3603 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3604 return;
3605 spin_lock(&vmx_vpid_lock);
991e7a0e 3606 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3607 spin_unlock(&vmx_vpid_lock);
3608}
3609
1e4329ee 3610static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3611 u32 msr, int type)
25c5f225 3612{
3e7c73e9 3613 int f = sizeof(unsigned long);
25c5f225
SY		 3614
3615 if (!cpu_has_vmx_msr_bitmap())
3616 return;
3617
ceef7d10
VK		 3618 if (static_branch_unlikely(&enable_evmcs))
3619 evmcs_touch_msr_bitmap();
3620
25c5f225
SY		 3621 /*
3622 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3623 * have the write-low and read-high bitmap offsets the wrong way round.
3624 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3625 */
25c5f225 3626 if (msr <= 0x1fff) {
8d14695f
YZ		 3627 if (type & MSR_TYPE_R)
3628 /* read-low */
3629 __clear_bit(msr, msr_bitmap + 0x000 / f);
3630
3631 if (type & MSR_TYPE_W)
3632 /* write-low */
3633 __clear_bit(msr, msr_bitmap + 0x800 / f);
3634
25c5f225
SY		 3635 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3636 msr &= 0x1fff;
8d14695f
YZ		 3637 if (type & MSR_TYPE_R)
3638 /* read-high */
3639 __clear_bit(msr, msr_bitmap + 0x400 / f);
3640
3641 if (type & MSR_TYPE_W)
3642 /* write-high */
3643 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3644
3645 }
3646}
3647
1e4329ee 3648static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3649 u32 msr, int type)
3650{
3651 int f = sizeof(unsigned long);
3652
3653 if (!cpu_has_vmx_msr_bitmap())
3654 return;
3655
ceef7d10
VK		 3656 if (static_branch_unlikely(&enable_evmcs))
3657 evmcs_touch_msr_bitmap();
3658
904e14fb
PB		 3659 /*
3660 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3661 * have the write-low and read-high bitmap offsets the wrong way round.
3662 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3663 */
3664 if (msr <= 0x1fff) {
3665 if (type & MSR_TYPE_R)
3666 /* read-low */
3667 __set_bit(msr, msr_bitmap + 0x000 / f);
3668
3669 if (type & MSR_TYPE_W)
3670 /* write-low */
3671 __set_bit(msr, msr_bitmap + 0x800 / f);
3672
3673 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3674 msr &= 0x1fff;
3675 if (type & MSR_TYPE_R)
3676 /* read-high */
3677 __set_bit(msr, msr_bitmap + 0x400 / f);
3678
3679 if (type & MSR_TYPE_W)
3680 /* write-high */
3681 __set_bit(msr, msr_bitmap + 0xc00 / f);
3682
3683 }
3684}
3685
1e4329ee 3686static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3687 u32 msr, int type, bool value)
3688{
3689 if (value)
3690 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3691 else
3692 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3693}
3694
904e14fb 3695static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3696{
904e14fb
PB		 3697 u8 mode = 0;
3698
3699 if (cpu_has_secondary_exec_ctrls() &&
fe7f895d 3700 (secondary_exec_controls_get(to_vmx(vcpu)) &
904e14fb
PB		 3701 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3702 mode |= MSR_BITMAP_MODE_X2APIC;
3703 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3704 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3705 }
3706
904e14fb 3707 return mode;
8d14695f
YZ		 3708}
3709
904e14fb
PB		 3710static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3711 u8 mode)
8d14695f 3712{
904e14fb
PB		 3713 int msr;
3714
3715 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3716 unsigned word = msr / BITS_PER_LONG;
3717 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3718 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3719 }
3720
3721 if (mode & MSR_BITMAP_MODE_X2APIC) {
3722 /*
3723 * TPR reads and writes can be virtualized even if virtual interrupt
3724 * delivery is not in use.
3725 */
3726 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3727 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3728 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3729 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3730 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3731 }
f6e90f9e 3732 }
5897297b
AK		 3733}
3734
97b7ead3 3735void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3736{
3737 struct vcpu_vmx *vmx = to_vmx(vcpu);
3738 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3739 u8 mode = vmx_msr_bitmap_mode(vcpu);
3740 u8 changed = mode ^ vmx->msr_bitmap_mode;
3741
3742 if (!changed)
3743 return;
3744
904e14fb
PB		 3745 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3746 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3747
3748 vmx->msr_bitmap_mode = mode;
3749}
3750
b08c2896
CP		 3751void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3752{
3753 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3754 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3755 u32 i;
3756
3757 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3758 MSR_TYPE_RW, flag);
3759 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3760 MSR_TYPE_RW, flag);
3761 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3762 MSR_TYPE_RW, flag);
3763 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3764 MSR_TYPE_RW, flag);
3765 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3766 vmx_set_intercept_for_msr(msr_bitmap,
3767 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3768 vmx_set_intercept_for_msr(msr_bitmap,
3769 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3770 }
3771}
3772
e6c67d8c
LA		 3773static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3774{
3775 struct vcpu_vmx *vmx = to_vmx(vcpu);
3776 void *vapic_page;
3777 u32 vppr;
3778 int rvi;
3779
3780 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3781 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
96c66e87 3782 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
e6c67d8c
LA		 3783 return false;
3784
7e712684 3785 rvi = vmx_get_rvi();
e6c67d8c 3786
96c66e87 3787 vapic_page = vmx->nested.virtual_apic_map.hva;
e6c67d8c 3788 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
e6c67d8c
LA		 3789
3790 return ((rvi & 0xf0) > (vppr & 0xf0));
3791}
3792
06a5524f
WV		 3793static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3794 bool nested)
21bc8dc5
RK		 3795{
3796#ifdef CONFIG_SMP
06a5524f
WV		 3797 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3798
21bc8dc5 3799 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3800 /*
5753743f
HZ		 3801 * The vector of interrupt to be delivered to vcpu had
3802 * been set in PIR before this function.
3803 *
3804 * Following cases will be reached in this block, and
3805 * we always send a notification event in all cases as
3806 * explained below.
3807 *
3808 * Case 1: vcpu keeps in non-root mode. Sending a
3809 * notification event posts the interrupt to vcpu.
3810 *
3811 * Case 2: vcpu exits to root mode and is still
3812 * runnable. PIR will be synced to vIRR before the
3813 * next vcpu entry. Sending a notification event in
3814 * this case has no effect, as vcpu is not in root
3815 * mode.
28b835d6 3816 *
5753743f
HZ		 3817 * Case 3: vcpu exits to root mode and is blocked.
3818 * vcpu_block() has already synced PIR to vIRR and
3819 * never blocks vcpu if vIRR is not cleared. Therefore,
3820 * a blocked vcpu here does not wait for any requested
3821 * interrupts in PIR, and sending a notification event
3822 * which has no effect is safe here.
28b835d6 3823 */
28b835d6 3824
06a5524f 3825 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3826 return true;
3827 }
3828#endif
3829 return false;
3830}
3831
705699a1
WV		 3832static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3833 int vector)
3834{
3835 struct vcpu_vmx *vmx = to_vmx(vcpu);
3836
3837 if (is_guest_mode(vcpu) &&
3838 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3839 /*
3840 * If a posted intr is not recognized by hardware,
3841 * we will accomplish it in the next vmentry.
3842 */
3843 vmx->nested.pi_pending = true;
3844 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3845 /* the PIR and ON have been set by L1. */
3846 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3847 kvm_vcpu_kick(vcpu);
705699a1
WV		 3848 return 0;
3849 }
3850 return -1;
3851}
a20ed54d
YZ		 3852/*
3853 * Send interrupt to vcpu via posted interrupt way.
3854 * 1. If target vcpu is running(non-root mode), send posted interrupt
3855 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3856 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3857 * interrupt from PIR in next vmentry.
3858 */
91a5f413 3859static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
a20ed54d
YZ		 3860{
3861 struct vcpu_vmx *vmx = to_vmx(vcpu);
3862 int r;
3863
705699a1
WV		 3864 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3865 if (!r)
91a5f413
VK		 3866 return 0;
3867
3868 if (!vcpu->arch.apicv_active)
3869 return -1;
705699a1 3870
a20ed54d 3871 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
91a5f413 3872 return 0;
a20ed54d 3873
b95234c8
PB		 3874 /* If a previous notification has sent the IPI, nothing to do. */
3875 if (pi_test_and_set_on(&vmx->pi_desc))
91a5f413 3876 return 0;
b95234c8 3877
06a5524f 3878 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d 3879 kvm_vcpu_kick(vcpu);
91a5f413
VK		 3880
3881 return 0;
a20ed54d
YZ		 3882}
3883
a3a8ff8e
NHE		 3884/*
3885 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3886 * will not change in the lifetime of the guest.
3887 * Note that host-state that does change is set elsewhere. E.g., host-state
3888 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3889 */
97b7ead3 3890void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3891{
3892 u32 low32, high32;
3893 unsigned long tmpl;
d6e41f11 3894 unsigned long cr0, cr3, cr4;
a3a8ff8e 3895
04ac88ab
AL		 3896 cr0 = read_cr0();
3897 WARN_ON(cr0 & X86_CR0_TS);
3898 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3899
3900 /*
3901 * Save the most likely value for this task's CR3 in the VMCS.
3902 * We can't use __get_current_cr3_fast() because we're not atomic.
3903 */
6c690ee1 3904 cr3 = __read_cr3();
d6e41f11 3905 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3906 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3907
d974baa3 3908 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3909 cr4 = cr4_read_shadow();
d974baa3 3910 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3911 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3912
a3a8ff8e 3913 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3914#ifdef CONFIG_X86_64
3915 /*
3916 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3917 * vmx_prepare_switch_to_host(), in case userspace uses
3918 * the null selectors too (the expected case).
b2da15ac
AK		 3919 */
3920 vmcs_write16(HOST_DS_SELECTOR, 0);
3921 vmcs_write16(HOST_ES_SELECTOR, 0);
3922#else
a3a8ff8e
NHE		 3923 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3924 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3925#endif
a3a8ff8e
NHE		 3926 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3927 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3928
2342080c 3929 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
a3a8ff8e 3930
453eafbe 3931 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3932
3933 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3934 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3935 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3936 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3937
3938 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3939 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3940 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3941 }
5a5e8a15 3942
c73da3fc 3943 if (cpu_has_load_ia32_efer())
5a5e8a15 3944 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3945}
3946
97b7ead3 3947void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3948{
3949 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3950 if (enable_ept)
3951 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3952 if (is_guest_mode(&vmx->vcpu))
3953 vmx->vcpu.arch.cr4_guest_owned_bits &=
3954 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3955 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3956}
3957
c075c3e4 3958u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
01e439be
YZ		 3959{
3960 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3961
d62caabb 3962 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3963 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3964
3965 if (!enable_vnmi)
3966 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3967
804939ea
SC		 3968 if (!enable_preemption_timer)
3969 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3970
01e439be
YZ		 3971 return pin_based_exec_ctrl;
3972}
3973
d62caabb
AS		 3974static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3975{
3976 struct vcpu_vmx *vmx = to_vmx(vcpu);
3977
c5f2c766 3978 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3979 if (cpu_has_secondary_exec_ctrls()) {
3980 if (kvm_vcpu_apicv_active(vcpu))
fe7f895d 3981 secondary_exec_controls_setbit(vmx,
3ce424e4
RK		 3982 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3983 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3984 else
fe7f895d 3985 secondary_exec_controls_clearbit(vmx,
3ce424e4
RK		 3986 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3987 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3988 }
3989
3990 if (cpu_has_vmx_msr_bitmap())
904e14fb 3991 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3992}
3993
89b0c9f5
SC		 3994u32 vmx_exec_control(struct vcpu_vmx *vmx)
3995{
3996 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3997
3998 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3999 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4000
4001 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4002 exec_control &= ~CPU_BASED_TPR_SHADOW;
4003#ifdef CONFIG_X86_64
4004 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4005 CPU_BASED_CR8_LOAD_EXITING;
4006#endif
4007 }
4008 if (!enable_ept)
4009 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4010 CPU_BASED_CR3_LOAD_EXITING |
4011 CPU_BASED_INVLPG_EXITING;
4012 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4013 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4014 CPU_BASED_MONITOR_EXITING);
4015 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4016 exec_control &= ~CPU_BASED_HLT_EXITING;
4017 return exec_control;
4018}
4019
4020
80154d77 4021static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 4022{
80154d77
PB		 4023 struct kvm_vcpu *vcpu = &vmx->vcpu;
4024
bf8179a0 4025 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 4026
f99e3daf
CP		 4027 if (pt_mode == PT_MODE_SYSTEM)
4028 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 4029 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 4030 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4031 if (vmx->vpid == 0)
4032 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4033 if (!enable_ept) {
4034 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4035 enable_unrestricted_guest = 0;
4036 }
4037 if (!enable_unrestricted_guest)
4038 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 4039 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 4040 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 4041 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 4042 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4043 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4044 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 4045
4046 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4047 * in vmx_set_cr4. */
4048 exec_control &= ~SECONDARY_EXEC_DESC;
4049
abc4fc58
AG		 4050 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4051 (handle_vmptrld).
4052 We can NOT enable shadow_vmcs here because we don't have yet
4053 a current VMCS12
4054 */
4055 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 4056
4057 if (!enable_pml)
4058 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 4059
3db13480
PB		 4060 if (vmx_xsaves_supported()) {
4061 /* Exposing XSAVES only when XSAVE is exposed */
4062 bool xsaves_enabled =
96be4e06 4063 boot_cpu_has(X86_FEATURE_XSAVE) &&
3db13480
PB		 4064 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4065 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4066
7204160e
AL		 4067 vcpu->arch.xsaves_enabled = xsaves_enabled;
4068
3db13480
PB		 4069 if (!xsaves_enabled)
4070 exec_control &= ~SECONDARY_EXEC_XSAVES;
4071
4072 if (nested) {
4073 if (xsaves_enabled)
6677f3da 4074 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 4075 SECONDARY_EXEC_XSAVES;
4076 else
6677f3da 4077 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 4078 ~SECONDARY_EXEC_XSAVES;
4079 }
4080 }
4081
80154d77
PB		 4082 if (vmx_rdtscp_supported()) {
4083 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4084 if (!rdtscp_enabled)
4085 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4086
4087 if (nested) {
4088 if (rdtscp_enabled)
6677f3da 4089 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4090 SECONDARY_EXEC_RDTSCP;
4091 else
6677f3da 4092 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4093 ~SECONDARY_EXEC_RDTSCP;
4094 }
4095 }
4096
4097 if (vmx_invpcid_supported()) {
4098 /* Exposing INVPCID only when PCID is exposed */
4099 bool invpcid_enabled =
4100 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4101 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4102
4103 if (!invpcid_enabled) {
4104 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4105 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4106 }
4107
4108 if (nested) {
4109 if (invpcid_enabled)
6677f3da 4110 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4111 SECONDARY_EXEC_ENABLE_INVPCID;
4112 else
6677f3da 4113 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4114 ~SECONDARY_EXEC_ENABLE_INVPCID;
4115 }
4116 }
4117
45ec368c
JM		 4118 if (vmx_rdrand_supported()) {
4119 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4120 if (rdrand_enabled)
736fdf72 4121 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4122
4123 if (nested) {
4124 if (rdrand_enabled)
6677f3da 4125 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4126 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 4127 else
6677f3da 4128 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4129 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4130 }
4131 }
4132
75f4fc8d
JM		 4133 if (vmx_rdseed_supported()) {
4134 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4135 if (rdseed_enabled)
736fdf72 4136 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4137
4138 if (nested) {
4139 if (rdseed_enabled)
6677f3da 4140 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4141 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 4142 else
6677f3da 4143 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4144 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4145 }
4146 }
4147
e69e72fa
TX		 4148 if (vmx_waitpkg_supported()) {
4149 bool waitpkg_enabled =
4150 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4151
4152 if (!waitpkg_enabled)
4153 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4154
4155 if (nested) {
4156 if (waitpkg_enabled)
4157 vmx->nested.msrs.secondary_ctls_high |=
4158 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4159 else
4160 vmx->nested.msrs.secondary_ctls_high &=
4161 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4162 }
4163 }
4164
80154d77 4165 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 4166}
4167
ce88decf
XG		 4168static void ept_set_mmio_spte_mask(void)
4169{
4170 /*
4171 * EPT Misconfigurations can be generated if the value of bits 2:0
4172 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 4173 */
dcdca5fe 4174 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4af77151 4175 VMX_EPT_MISCONFIG_WX_VALUE, 0);
ce88decf
XG		 4176}
4177
f53cd63c 4178#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 4179
944c3464 4180/*
1b84292b
XL		 4181 * Noting that the initialization of Guest-state Area of VMCS is in
4182 * vmx_vcpu_reset().
944c3464 4183 */
1b84292b 4184static void init_vmcs(struct vcpu_vmx *vmx)
944c3464 4185{
944c3464 4186 if (nested)
1b84292b 4187 nested_vmx_set_vmcs_shadowing_bitmap();
944c3464 4188
25c5f225 4189 if (cpu_has_vmx_msr_bitmap())
904e14fb 4190 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4191
6aa8b732
AK		 4192 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4193
6aa8b732 4194 /* Control */
3af80fec 4195 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4196
3af80fec 4197 exec_controls_set(vmx, vmx_exec_control(vmx));
6aa8b732 4198
dfa169bb 4199 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4200 vmx_compute_secondary_exec_control(vmx);
3af80fec 4201 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
dfa169bb 4202 }
f78e0e2e 4203
d62caabb 4204 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4205 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4206 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4207 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4208 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4209
4210 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4211
0bcf261c 4212 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4213 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4214 }
4215
b31c114b 4216 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4217 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4218 vmx->ple_window = ple_window;
4219 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4220 }
4221
c3707958
XG		 4222 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4223 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4224 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4225
9581d442
AK		 4226 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4227 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4228 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4229 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4230 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4231
2a499e49
BD		 4232 if (cpu_has_vmx_vmfunc())
4233 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4234
2cc51560
ED		 4235 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4237 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4238 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4239 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4240
74545705
RK		 4241 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4242 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4243
3af80fec 4244 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4245
4246 /* 22.2.1, 20.8.1 */
3af80fec 4247 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
1c3d14fe 4248
bd7e5b08
PB		 4249 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4250 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4251
bf8179a0 4252 set_cr4_guest_host_mask(vmx);
e00c8cf2 4253
35fbe0d4
XL		 4254 if (vmx->vpid != 0)
4255 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4256
f53cd63c
WL		 4257 if (vmx_xsaves_supported())
4258 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4259
4e59516a 4260 if (enable_pml) {
4e59516a
PF		 4261 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4262 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4263 }
0b665d30
SC		 4264
4265 if (cpu_has_vmx_encls_vmexit())
4266 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4267
4268 if (pt_mode == PT_MODE_HOST_GUEST) {
4269 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4270 /* Bit[6~0] are forced to 1, writes are ignored. */
4271 vmx->pt_desc.guest.output_mask = 0x7F;
4272 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4273 }
e00c8cf2
AK		 4274}
4275
d28bc9dd 4276static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4277{
4278 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4279 struct msr_data apic_base_msr;
d28bc9dd 4280 u64 cr0;
e00c8cf2 4281
7ffd92c5 4282 vmx->rmode.vm86_active = 0;
d28b387f 4283 vmx->spec_ctrl = 0;
e00c8cf2 4284
6e3ba4ab
TX		 4285 vmx->msr_ia32_umwait_control = 0;
4286
ad312c7c 4287 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
95c06540 4288 vmx->hv_deadline_tsc = -1;
d28bc9dd
NA		 4289 kvm_set_cr8(vcpu, 0);
4290
4291 if (!init_event) {
4292 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4293 MSR_IA32_APICBASE_ENABLE;
4294 if (kvm_vcpu_is_reset_bsp(vcpu))
4295 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4296 apic_base_msr.host_initiated = true;
4297 kvm_set_apic_base(vcpu, &apic_base_msr);
4298 }
e00c8cf2 4299
2fb92db1
AK		 4300 vmx_segment_cache_clear(vmx);
4301
5706be0d 4302 seg_setup(VCPU_SREG_CS);
66450a21 4303 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4304 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4305
4306 seg_setup(VCPU_SREG_DS);
4307 seg_setup(VCPU_SREG_ES);
4308 seg_setup(VCPU_SREG_FS);
4309 seg_setup(VCPU_SREG_GS);
4310 seg_setup(VCPU_SREG_SS);
4311
4312 vmcs_write16(GUEST_TR_SELECTOR, 0);
4313 vmcs_writel(GUEST_TR_BASE, 0);
4314 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4315 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4316
4317 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4318 vmcs_writel(GUEST_LDTR_BASE, 0);
4319 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4320 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4321
d28bc9dd
NA		 4322 if (!init_event) {
4323 vmcs_write32(GUEST_SYSENTER_CS, 0);
4324 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4325 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4326 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4327 }
e00c8cf2 4328
c37c2873 4329 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4330 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4331
e00c8cf2
AK		 4332 vmcs_writel(GUEST_GDTR_BASE, 0);
4333 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4334
4335 vmcs_writel(GUEST_IDTR_BASE, 0);
4336 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4337
443381a8 4338 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4339 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4340 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4341 if (kvm_mpx_supported())
4342 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4343
e00c8cf2
AK		 4344 setup_msrs(vmx);
4345
6aa8b732
AK		 4346 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4347
d28bc9dd 4348 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4349 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4350 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4351 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4352 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4353 vmcs_write32(TPR_THRESHOLD, 0);
4354 }
4355
a73896cb 4356 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4357
d28bc9dd 4358 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4359 vmx->vcpu.arch.cr0 = cr0;
f2463247 4360 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4361 vmx_set_cr4(vcpu, 0);
5690891b 4362 vmx_set_efer(vcpu, 0);
bd7e5b08 4363
d28bc9dd 4364 update_exception_bitmap(vcpu);
6aa8b732 4365
dd5f5341 4366 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4367 if (init_event)
4368 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4369}
4370
55d2375e 4371static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4372{
9dadc2f9 4373 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
3b86cd99
JK		 4374}
4375
c9a7953f 4376static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4377{
d02fcf50 4378 if (!enable_vnmi ||
8a1b4392 4379 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4380 enable_irq_window(vcpu);
4381 return;
4382 }
3b86cd99 4383
4e2a0bc5 4384 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
3b86cd99
JK		 4385}
4386
66fd3f7f 4387static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4388{
9c8cba37 4389 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4390 uint32_t intr;
4391 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4392
229456fc 4393 trace_kvm_inj_virq(irq);
2714d1d3 4394
fa89a817 4395 ++vcpu->stat.irq_injections;
7ffd92c5 4396 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4397 int inc_eip = 0;
4398 if (vcpu->arch.interrupt.soft)
4399 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 4400 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
85f455f7
ED		 4401 return;
4402 }
66fd3f7f
GN		 4403 intr = irq | INTR_INFO_VALID_MASK;
4404 if (vcpu->arch.interrupt.soft) {
4405 intr |= INTR_TYPE_SOFT_INTR;
4406 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4407 vmx->vcpu.arch.event_exit_inst_len);
4408 } else
4409 intr |= INTR_TYPE_EXT_INTR;
4410 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4411
4412 vmx_clear_hlt(vcpu);
85f455f7
ED		 4413}
4414
f08864b4
SY		 4415static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4416{
66a5a347
JK		 4417 struct vcpu_vmx *vmx = to_vmx(vcpu);
4418
d02fcf50 4419 if (!enable_vnmi) {
8a1b4392
PB		 4420 /*
4421 * Tracking the NMI-blocked state in software is built upon
4422 * finding the next open IRQ window. This, in turn, depends on
4423 * well-behaving guests: They have to keep IRQs disabled at
4424 * least as long as the NMI handler runs. Otherwise we may
4425 * cause NMI nesting, maybe breaking the guest. But as this is
4426 * highly unlikely, we can live with the residual risk.
4427 */
4428 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4429 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4430 }
4431
4c4a6f79
PB		 4432 ++vcpu->stat.nmi_injections;
4433 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4434
7ffd92c5 4435 if (vmx->rmode.vm86_active) {
9497e1f2 4436 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
66a5a347
JK		 4437 return;
4438 }
c5a6d5f7 4439
f08864b4
SY		 4440 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4441 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4442
4443 vmx_clear_hlt(vcpu);
f08864b4
SY		 4444}
4445
97b7ead3 4446bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4447{
4c4a6f79
PB		 4448 struct vcpu_vmx *vmx = to_vmx(vcpu);
4449 bool masked;
4450
d02fcf50 4451 if (!enable_vnmi)
8a1b4392 4452 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4453 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4454 return false;
4c4a6f79
PB		 4455 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4456 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4457 return masked;
3cfc3092
JK		 4458}
4459
97b7ead3 4460void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4461{
4462 struct vcpu_vmx *vmx = to_vmx(vcpu);
4463
d02fcf50 4464 if (!enable_vnmi) {
8a1b4392
PB		 4465 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4466 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4467 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4468 }
4469 } else {
4470 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4471 if (masked)
4472 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4473 GUEST_INTR_STATE_NMI);
4474 else
4475 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4476 GUEST_INTR_STATE_NMI);
4477 }
3cfc3092
JK		 4478}
4479
2505dc9f
JK		 4480static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4481{
b6b8a145
JK		 4482 if (to_vmx(vcpu)->nested.nested_run_pending)
4483 return 0;
ea8ceb83 4484
d02fcf50 4485 if (!enable_vnmi &&
8a1b4392
PB		 4486 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4487 return 0;
4488
2505dc9f
JK		 4489 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4490 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4491 | GUEST_INTR_STATE_NMI));
4492}
4493
78646121
GN		 4494static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4495{
b6b8a145
JK		 4496 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4497 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4498 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4499 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4500}
4501
cbc94022
IE		 4502static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4503{
4504 int ret;
cbc94022 4505
f7eaeb0a
SC		 4506 if (enable_unrestricted_guest)
4507 return 0;
4508
6a3c623b
PX		 4509 mutex_lock(&kvm->slots_lock);
4510 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4511 PAGE_SIZE * 3);
4512 mutex_unlock(&kvm->slots_lock);
4513
cbc94022
IE		 4514 if (ret)
4515 return ret;
40bbb9d0 4516 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4517 return init_rmode_tss(kvm);
cbc94022
IE		 4518}
4519
2ac52ab8
SC		 4520static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4521{
40bbb9d0 4522 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4523 return 0;
4524}
4525
0ca1b4f4 4526static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4527{
77ab6db0 4528 switch (vec) {
77ab6db0 4529 case BP_VECTOR:
c573cd22
JK		 4530 /*
4531 * Update instruction length as we may reinject the exception
4532 * from user space while in guest debugging mode.
4533 */
4534 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4535 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4536 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4537 return false;
4538 /* fall through */
4539 case DB_VECTOR:
4540 if (vcpu->guest_debug &
4541 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4542 return false;
d0bfb940
JK		 4543 /* fall through */
4544 case DE_VECTOR:
77ab6db0
JK		 4545 case OF_VECTOR:
4546 case BR_VECTOR:
4547 case UD_VECTOR:
4548 case DF_VECTOR:
4549 case SS_VECTOR:
4550 case GP_VECTOR:
4551 case MF_VECTOR:
0ca1b4f4 4552 return true;
77ab6db0 4553 }
0ca1b4f4
GN		 4554 return false;
4555}
4556
4557static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4558 int vec, u32 err_code)
4559{
4560 /*
4561 * Instruction with address size override prefix opcode 0x67
4562 * Cause the #SS fault with 0 error code in VM86 mode.
4563 */
4564 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
60fc3d02 4565 if (kvm_emulate_instruction(vcpu, 0)) {
0ca1b4f4
GN		 4566 if (vcpu->arch.halt_request) {
4567 vcpu->arch.halt_request = 0;
5cb56059 4568 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4569 }
4570 return 1;
4571 }
4572 return 0;
4573 }
4574
4575 /*
4576 * Forward all other exceptions that are valid in real mode.
4577 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4578 * the required debugging infrastructure rework.
4579 */
4580 kvm_queue_exception(vcpu, vec);
4581 return 1;
6aa8b732
AK		 4582}
4583
a0861c02
AK		 4584/*
4585 * Trigger machine check on the host. We assume all the MSRs are already set up
4586 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4587 * We pass a fake environment to the machine check handler because we want
4588 * the guest to be always treated like user space, no matter what context
4589 * it used internally.
4590 */
4591static void kvm_machine_check(void)
4592{
4593#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4594 struct pt_regs regs = {
4595 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4596 .flags = X86_EFLAGS_IF,
4597 };
4598
4599 do_machine_check(&regs, 0);
4600#endif
4601}
4602
851ba692 4603static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02 4604{
95b5a48c 4605 /* handled by vmx_vcpu_run() */
a0861c02
AK		 4606 return 1;
4607}
4608
95b5a48c 4609static int handle_exception_nmi(struct kvm_vcpu *vcpu)
6aa8b732 4610{
1155f76a 4611 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4612 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4613 u32 intr_info, ex_no, error_code;
42dbaa5a 4614 unsigned long cr2, rip, dr6;
6aa8b732 4615 u32 vect_info;
6aa8b732 4616
1155f76a 4617 vect_info = vmx->idt_vectoring_info;
88786475 4618 intr_info = vmx->exit_intr_info;
6aa8b732 4619
2ea72039 4620 if (is_machine_check(intr_info) || is_nmi(intr_info))
95b5a48c 4621 return 1; /* handled by handle_exception_nmi_irqoff() */
2ab455cc 4622
082d06ed
WL		 4623 if (is_invalid_opcode(intr_info))
4624 return handle_ud(vcpu);
7aa81cc0 4625
6aa8b732 4626 error_code = 0;
2e11384c 4627 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4628 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4629
9e869480
LA		 4630 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4631 WARN_ON_ONCE(!enable_vmware_backdoor);
a6c6ed1e
SC		 4632
4633 /*
4634 * VMware backdoor emulation on #GP interception only handles
4635 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4636 * error code on #GP.
4637 */
4638 if (error_code) {
4639 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4640 return 1;
4641 }
60fc3d02 4642 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9e869480
LA		 4643 }
4644
bf4ca23e
XG		 4645 /*
4646 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4647 * MMIO, it is better to report an internal error.
4648 * See the comments in vmx_handle_exit.
4649 */
4650 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4651 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4652 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4653 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4654 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4655 vcpu->run->internal.data[0] = vect_info;
4656 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4657 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4658 return 0;
4659 }
4660
6aa8b732
AK		 4661 if (is_page_fault(intr_info)) {
4662 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4663 /* EPT won't cause page fault directly */
4664 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4665 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4666 }
4667
d0bfb940 4668 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4669
4670 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4671 return handle_rmode_exception(vcpu, ex_no, error_code);
4672
42dbaa5a 4673 switch (ex_no) {
54a20552
EN		 4674 case AC_VECTOR:
4675 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4676 return 1;
42dbaa5a
JK		 4677 case DB_VECTOR:
4678 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4679 if (!(vcpu->guest_debug &
4680 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1fc5d194 4681 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4682 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4683 if (is_icebp(intr_info))
1957aa63 4684 WARN_ON(!skip_emulated_instruction(vcpu));
fd2a445a 4685
42dbaa5a
JK		 4686 kvm_queue_exception(vcpu, DB_VECTOR);
4687 return 1;
4688 }
4689 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4690 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4691 /* fall through */
4692 case BP_VECTOR:
c573cd22
JK		 4693 /*
4694 * Update instruction length as we may reinject #BP from
4695 * user space while in guest debugging mode. Reading it for
4696 * #DB as well causes no harm, it is not used in that case.
4697 */
4698 vmx->vcpu.arch.event_exit_inst_len =
4699 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4700 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4701 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4702 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4703 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4704 break;
4705 default:
d0bfb940
JK		 4706 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4707 kvm_run->ex.exception = ex_no;
4708 kvm_run->ex.error_code = error_code;
42dbaa5a 4709 break;
6aa8b732 4710 }
6aa8b732
AK		 4711 return 0;
4712}
4713
f399e60c 4714static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4715{
1165f5fe 4716 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4717 return 1;
4718}
4719
851ba692 4720static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4721{
851ba692 4722 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4723 vcpu->mmio_needed = 0;
988ad74f
AK		 4724 return 0;
4725}
6aa8b732 4726
851ba692 4727static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4728{
bfdaab09 4729 unsigned long exit_qualification;
dca7f128 4730 int size, in, string;
039576c0 4731 unsigned port;
6aa8b732 4732
bfdaab09 4733 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4734 string = (exit_qualification & 16) != 0;
e70669ab 4735
cf8f70bf 4736 ++vcpu->stat.io_exits;
e70669ab 4737
432baf60 4738 if (string)
60fc3d02 4739 return kvm_emulate_instruction(vcpu, 0);
e70669ab 4740
cf8f70bf
GN		 4741 port = exit_qualification >> 16;
4742 size = (exit_qualification & 7) + 1;
432baf60 4743 in = (exit_qualification & 8) != 0;
cf8f70bf 4744
dca7f128 4745 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4746}
4747
102d8325
IM		 4748static void
4749vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4750{
4751 /*
4752 * Patch in the VMCALL instruction:
4753 */
4754 hypercall[0] = 0x0f;
4755 hypercall[1] = 0x01;
4756 hypercall[2] = 0xc1;
102d8325
IM		 4757}
4758
0fa06071 4759/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4760static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4761{
eeadf9e7 4762 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4763 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4764 unsigned long orig_val = val;
4765
eeadf9e7
NHE		 4766 /*
4767 * We get here when L2 changed cr0 in a way that did not change
4768 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4769 * but did change L0 shadowed bits. So we first calculate the
4770 * effective cr0 value that L1 would like to write into the
4771 * hardware. It consists of the L2-owned bits from the new
4772 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4773 */
1a0d74e6
JK		 4774 val = (val & ~vmcs12->cr0_guest_host_mask) |
4775 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4776
3899152c 4777 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4778 return 1;
1a0d74e6
JK		 4779
4780 if (kvm_set_cr0(vcpu, val))
4781 return 1;
4782 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4783 return 0;
1a0d74e6
JK		 4784 } else {
4785 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4786 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4787 return 1;
3899152c 4788
eeadf9e7 4789 return kvm_set_cr0(vcpu, val);
1a0d74e6 4790 }
eeadf9e7
NHE		 4791}
4792
4793static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4794{
4795 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4796 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4797 unsigned long orig_val = val;
4798
4799 /* analogously to handle_set_cr0 */
4800 val = (val & ~vmcs12->cr4_guest_host_mask) |
4801 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4802 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4803 return 1;
1a0d74e6 4804 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4805 return 0;
4806 } else
4807 return kvm_set_cr4(vcpu, val);
4808}
4809
0367f205
PB		 4810static int handle_desc(struct kvm_vcpu *vcpu)
4811{
4812 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
60fc3d02 4813 return kvm_emulate_instruction(vcpu, 0);
0367f205
PB		 4814}
4815
851ba692 4816static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4817{
229456fc 4818 unsigned long exit_qualification, val;
6aa8b732
AK		 4819 int cr;
4820 int reg;
49a9b07e 4821 int err;
6affcbed 4822 int ret;
6aa8b732 4823
bfdaab09 4824 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4825 cr = exit_qualification & 15;
4826 reg = (exit_qualification >> 8) & 15;
4827 switch ((exit_qualification >> 4) & 3) {
4828 case 0: /* mov to cr */
1e32c079 4829 val = kvm_register_readl(vcpu, reg);
229456fc 4830 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4831 switch (cr) {
4832 case 0:
eeadf9e7 4833 err = handle_set_cr0(vcpu, val);
6affcbed 4834 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4835 case 3:
e1de91cc 4836 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4837 err = kvm_set_cr3(vcpu, val);
6affcbed 4838 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4839 case 4:
eeadf9e7 4840 err = handle_set_cr4(vcpu, val);
6affcbed 4841 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4842 case 8: {
4843 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4844 u8 cr8 = (u8)val;
eea1cff9 4845 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4846 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4847 if (lapic_in_kernel(vcpu))
6affcbed 4848 return ret;
0a5fff19 4849 if (cr8_prev <= cr8)
6affcbed
KH		 4850 return ret;
4851 /*
4852 * TODO: we might be squashing a
4853 * KVM_GUESTDBG_SINGLESTEP-triggered
4854 * KVM_EXIT_DEBUG here.
4855 */
851ba692 4856 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4857 return 0;
4858 }
4b8073e4 4859 }
6aa8b732 4860 break;
25c4c276 4861 case 2: /* clts */
bd7e5b08
PB		 4862 WARN_ONCE(1, "Guest should always own CR0.TS");
4863 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4864 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4865 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4866 case 1: /*mov from cr*/
4867 switch (cr) {
4868 case 3:
e1de91cc 4869 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4870 val = kvm_read_cr3(vcpu);
4871 kvm_register_write(vcpu, reg, val);
4872 trace_kvm_cr_read(cr, val);
6affcbed 4873 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4874 case 8:
229456fc
MT		 4875 val = kvm_get_cr8(vcpu);
4876 kvm_register_write(vcpu, reg, val);
4877 trace_kvm_cr_read(cr, val);
6affcbed 4878 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4879 }
4880 break;
4881 case 3: /* lmsw */
a1f83a74 4882 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4883 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4884 kvm_lmsw(vcpu, val);
6aa8b732 4885
6affcbed 4886 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4887 default:
4888 break;
4889 }
851ba692 4890 vcpu->run->exit_reason = 0;
a737f256 4891 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4892 (int)(exit_qualification >> 4) & 3, cr);
4893 return 0;
4894}
4895
851ba692 4896static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4897{
bfdaab09 4898 unsigned long exit_qualification;
16f8a6f9
NA		 4899 int dr, dr7, reg;
4900
4901 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4902 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4903
4904 /* First, if DR does not exist, trigger UD */
4905 if (!kvm_require_dr(vcpu, dr))
4906 return 1;
6aa8b732 4907
f2483415 4908 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4909 if (!kvm_require_cpl(vcpu, 0))
4910 return 1;
16f8a6f9
NA		 4911 dr7 = vmcs_readl(GUEST_DR7);
4912 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4913 /*
4914 * As the vm-exit takes precedence over the debug trap, we
4915 * need to emulate the latter, either for the host or the
4916 * guest debugging itself.
4917 */
4918 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4919 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4920 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4921 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4922 vcpu->run->debug.arch.exception = DB_VECTOR;
4923 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4924 return 0;
4925 } else {
1fc5d194 4926 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4927 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4928 kvm_queue_exception(vcpu, DB_VECTOR);
4929 return 1;
4930 }
4931 }
4932
81908bf4 4933 if (vcpu->guest_debug == 0) {
2183f564 4934 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4935
4936 /*
4937 * No more DR vmexits; force a reload of the debug registers
4938 * and reenter on this instruction. The next vmexit will
4939 * retrieve the full state of the debug registers.
4940 */
4941 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4942 return 1;
4943 }
4944
42dbaa5a
JK		 4945 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4946 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4947 unsigned long val;
4c4d563b
JK		 4948
4949 if (kvm_get_dr(vcpu, dr, &val))
4950 return 1;
4951 kvm_register_write(vcpu, reg, val);
020df079 4952 } else
5777392e 4953 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4954 return 1;
4955
6affcbed 4956 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4957}
4958
73aaf249
JK		 4959static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4960{
4961 return vcpu->arch.dr6;
4962}
4963
4964static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4965{
4966}
4967
81908bf4
PB		 4968static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4969{
81908bf4
PB		 4970 get_debugreg(vcpu->arch.db[0], 0);
4971 get_debugreg(vcpu->arch.db[1], 1);
4972 get_debugreg(vcpu->arch.db[2], 2);
4973 get_debugreg(vcpu->arch.db[3], 3);
4974 get_debugreg(vcpu->arch.dr6, 6);
4975 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4976
4977 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2183f564 4978 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4979}
4980
020df079
GN		 4981static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4982{
4983 vmcs_writel(GUEST_DR7, val);
4984}
4985
851ba692 4986static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4987{
eb90f341 4988 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4989 return 1;
4990}
4991
851ba692 4992static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4993{
9dadc2f9 4994 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
2714d1d3 4995
3842d135
AK		 4996 kvm_make_request(KVM_REQ_EVENT, vcpu);
4997
a26bf12a 4998 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4999 return 1;
5000}
5001
851ba692 5002static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5003{
0d9c055e 5004 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 5005}
5006
ec25d5e6
GN		 5007static int handle_invd(struct kvm_vcpu *vcpu)
5008{
60fc3d02 5009 return kvm_emulate_instruction(vcpu, 0);
ec25d5e6
GN		 5010}
5011
851ba692 5012static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5013{
f9c617f6 5014 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5015
5016 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 5017 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 5018}
5019
fee84b07
AK		 5020static int handle_rdpmc(struct kvm_vcpu *vcpu)
5021{
5022 int err;
5023
5024 err = kvm_rdpmc(vcpu);
6affcbed 5025 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 5026}
5027
851ba692 5028static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5029{
6affcbed 5030 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5031}
5032
2acf923e
DC		 5033static int handle_xsetbv(struct kvm_vcpu *vcpu)
5034{
5035 u64 new_bv = kvm_read_edx_eax(vcpu);
de3cd117 5036 u32 index = kvm_rcx_read(vcpu);
2acf923e
DC		 5037
5038 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 5039 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 5040 return 1;
5041}
5042
851ba692 5043static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5044{
58fbbf26
KT		 5045 if (likely(fasteoi)) {
5046 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5047 int access_type, offset;
5048
5049 access_type = exit_qualification & APIC_ACCESS_TYPE;
5050 offset = exit_qualification & APIC_ACCESS_OFFSET;
5051 /*
5052 * Sane guest uses MOV to write EOI, with written value
5053 * not cared. So make a short-circuit here by avoiding
5054 * heavy instruction emulation.
5055 */
5056 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5057 (offset == APIC_EOI)) {
5058 kvm_lapic_set_eoi(vcpu);
6affcbed 5059 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 5060 }
5061 }
60fc3d02 5062 return kvm_emulate_instruction(vcpu, 0);
f78e0e2e
SY		 5063}
5064
c7c9c56c
YZ		 5065static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5066{
5067 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5068 int vector = exit_qualification & 0xff;
5069
5070 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5071 kvm_apic_set_eoi_accelerated(vcpu, vector);
5072 return 1;
5073}
5074
83d4c286
YZ		 5075static int handle_apic_write(struct kvm_vcpu *vcpu)
5076{
5077 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5078 u32 offset = exit_qualification & 0xfff;
5079
5080 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5081 kvm_apic_write_nodecode(vcpu, offset);
5082 return 1;
5083}
5084
851ba692 5085static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5086{
60637aac 5087 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5088 unsigned long exit_qualification;
e269fb21
JK		 5089 bool has_error_code = false;
5090 u32 error_code = 0;
37817f29 5091 u16 tss_selector;
7f3d35fd 5092 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5093
5094 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5095 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5096 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5097
5098 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5099
5100 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5101 if (reason == TASK_SWITCH_GATE && idt_v) {
5102 switch (type) {
5103 case INTR_TYPE_NMI_INTR:
5104 vcpu->arch.nmi_injected = false;
654f06fc 5105 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5106 break;
5107 case INTR_TYPE_EXT_INTR:
66fd3f7f 5108 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5109 kvm_clear_interrupt_queue(vcpu);
5110 break;
5111 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5112 if (vmx->idt_vectoring_info &
5113 VECTORING_INFO_DELIVER_CODE_MASK) {
5114 has_error_code = true;
5115 error_code =
5116 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5117 }
5118 /* fall through */
64a7ec06
GN		 5119 case INTR_TYPE_SOFT_EXCEPTION:
5120 kvm_clear_exception_queue(vcpu);
5121 break;
5122 default:
5123 break;
5124 }
60637aac 5125 }
37817f29
IE		 5126 tss_selector = exit_qualification;
5127
64a7ec06
GN		 5128 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5129 type != INTR_TYPE_EXT_INTR &&
5130 type != INTR_TYPE_NMI_INTR))
1957aa63 5131 WARN_ON(!skip_emulated_instruction(vcpu));
64a7ec06 5132
42dbaa5a
JK		 5133 /*
5134 * TODO: What about debug traps on tss switch?
5135 * Are we supposed to inject them and update dr6?
5136 */
1051778f
SC		 5137 return kvm_task_switch(vcpu, tss_selector,
5138 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
60fc3d02 5139 reason, has_error_code, error_code);
37817f29
IE		 5140}
5141
851ba692 5142static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5143{
f9c617f6 5144 unsigned long exit_qualification;
1439442c 5145 gpa_t gpa;
eebed243 5146 u64 error_code;
1439442c 5147
f9c617f6 5148 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5149
0be9c7a8
GN		 5150 /*
5151 * EPT violation happened while executing iret from NMI,
5152 * "blocked by NMI" bit has to be set before next VM entry.
5153 * There are errata that may cause this bit to not be set:
5154 * AAK134, BY25.
5155 */
bcd1c294 5156 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5157 enable_vnmi &&
bcd1c294 5158 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5159 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5160
1439442c 5161 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5162 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5163
27959a44 5164 /* Is it a read fault? */
ab22a473 5165 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5166 ? PFERR_USER_MASK : 0;
5167 /* Is it a write fault? */
ab22a473 5168 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5169 ? PFERR_WRITE_MASK : 0;
5170 /* Is it a fetch fault? */
ab22a473 5171 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5172 ? PFERR_FETCH_MASK : 0;
5173 /* ept page table entry is present? */
5174 error_code |= (exit_qualification &
5175 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5176 EPT_VIOLATION_EXECUTABLE))
5177 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5178
eebed243
PB		 5179 error_code |= (exit_qualification & 0x100) != 0 ?
5180 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5181
25d92081 5182 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5183 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5184}
5185
851ba692 5186static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5187{
68f89400
MT		 5188 gpa_t gpa;
5189
9034e6e8
PB		 5190 /*
5191 * A nested guest cannot optimize MMIO vmexits, because we have an
5192 * nGPA here instead of the required GPA.
5193 */
68f89400 5194 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5195 if (!is_guest_mode(vcpu) &&
5196 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5197 trace_kvm_fast_mmio(gpa);
1957aa63 5198 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 5199 }
68f89400 5200
c75d0edc 5201 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5202}
5203
851ba692 5204static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5205{
d02fcf50 5206 WARN_ON_ONCE(!enable_vnmi);
4e2a0bc5 5207 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
f08864b4 5208 ++vcpu->stat.nmi_window_exits;
3842d135 5209 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5210
5211 return 1;
5212}
5213
80ced186 5214static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5215{
8b3079a5 5216 struct vcpu_vmx *vmx = to_vmx(vcpu);
49e9d557 5217 bool intr_window_requested;
b8405c18 5218 unsigned count = 130;
49e9d557 5219
2bb8cafe
SC		 5220 /*
5221 * We should never reach the point where we are emulating L2
5222 * due to invalid guest state as that means we incorrectly
5223 * allowed a nested VMEntry with an invalid vmcs12.
5224 */
5225 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5226
2183f564 5227 intr_window_requested = exec_controls_get(vmx) &
9dadc2f9 5228 CPU_BASED_INTR_WINDOW_EXITING;
ea953ef0 5229
98eb2f8b 5230 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5231 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5232 return handle_interrupt_window(&vmx->vcpu);
5233
72875d8a 5234 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5235 return 1;
5236
60fc3d02 5237 if (!kvm_emulate_instruction(vcpu, 0))
8fff2710 5238 return 0;
1d5a4d9b 5239
add5ff7a 5240 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
8fff2710
SC		 5241 vcpu->arch.exception.pending) {
5242 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5243 vcpu->run->internal.suberror =
5244 KVM_INTERNAL_ERROR_EMULATION;
5245 vcpu->run->internal.ndata = 0;
5246 return 0;
5247 }
ea953ef0 5248
8d76c49e
GN		 5249 if (vcpu->arch.halt_request) {
5250 vcpu->arch.halt_request = 0;
8fff2710 5251 return kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5252 }
5253
8fff2710
SC		 5254 /*
5255 * Note, return 1 and not 0, vcpu_run() is responsible for
5256 * morphing the pending signal into the proper return code.
5257 */
ea953ef0 5258 if (signal_pending(current))
8fff2710
SC		 5259 return 1;
5260
ea953ef0
MG		 5261 if (need_resched())
5262 schedule();
5263 }
5264
8fff2710 5265 return 1;
b4a2d31d
RK		 5266}
5267
5268static void grow_ple_window(struct kvm_vcpu *vcpu)
5269{
5270 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5271 unsigned int old = vmx->ple_window;
b4a2d31d 5272
c8e88717
BM		 5273 vmx->ple_window = __grow_ple_window(old, ple_window,
5274 ple_window_grow,
5275 ple_window_max);
b4a2d31d 5276
4f75bcc3 5277 if (vmx->ple_window != old) {
b4a2d31d 5278 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5279 trace_kvm_ple_window_update(vcpu->vcpu_id,
5280 vmx->ple_window, old);
5281 }
b4a2d31d
RK		 5282}
5283
5284static void shrink_ple_window(struct kvm_vcpu *vcpu)
5285{
5286 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5287 unsigned int old = vmx->ple_window;
b4a2d31d 5288
c8e88717
BM		 5289 vmx->ple_window = __shrink_ple_window(old, ple_window,
5290 ple_window_shrink,
5291 ple_window);
b4a2d31d 5292
4f75bcc3 5293 if (vmx->ple_window != old) {
b4a2d31d 5294 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5295 trace_kvm_ple_window_update(vcpu->vcpu_id,
5296 vmx->ple_window, old);
5297 }
b4a2d31d
RK		 5298}
5299
bf9f6ac8
FW		 5300/*
5301 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5302 */
5303static void wakeup_handler(void)
5304{
5305 struct kvm_vcpu *vcpu;
5306 int cpu = smp_processor_id();
5307
5308 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5309 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5310 blocked_vcpu_list) {
5311 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5312
5313 if (pi_test_on(pi_desc) == 1)
5314 kvm_vcpu_kick(vcpu);
5315 }
5316 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5317}
5318
e01bca2f 5319static void vmx_enable_tdp(void)
f160c7b7
JS		 5320{
5321 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5322 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5323 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5324 0ull, VMX_EPT_EXECUTABLE_MASK,
5325 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5326 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5327
5328 ept_set_mmio_spte_mask();
5329 kvm_enable_tdp();
5330}
5331
4b8d54f9
ZE		 5332/*
5333 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5334 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5335 */
9fb41ba8 5336static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5337{
b31c114b 5338 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5339 grow_ple_window(vcpu);
5340
de63ad4c
LM		 5341 /*
5342 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5343 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5344 * never set PAUSE_EXITING and just set PLE if supported,
5345 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5346 */
5347 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5348 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5349}
5350
87c00572 5351static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5352{
6affcbed 5353 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5354}
5355
87c00572
GS		 5356static int handle_mwait(struct kvm_vcpu *vcpu)
5357{
5358 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5359 return handle_nop(vcpu);
5360}
5361
45ec368c
JM		 5362static int handle_invalid_op(struct kvm_vcpu *vcpu)
5363{
5364 kvm_queue_exception(vcpu, UD_VECTOR);
5365 return 1;
5366}
5367
5f3d45e7
MD		 5368static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5369{
5370 return 1;
5371}
5372
87c00572
GS		 5373static int handle_monitor(struct kvm_vcpu *vcpu)
5374{
5375 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5376 return handle_nop(vcpu);
5377}
5378
55d2375e 5379static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5380{
55d2375e
SC		 5381 u32 vmx_instruction_info;
5382 unsigned long type;
5383 bool pcid_enabled;
5384 gva_t gva;
5385 struct x86_exception e;
5386 unsigned i;
5387 unsigned long roots_to_free = 0;
5388 struct {
5389 u64 pcid;
5390 u64 gla;
5391 } operand;
f9eb4af6 5392
55d2375e 5393 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5394 kvm_queue_exception(vcpu, UD_VECTOR);
5395 return 1;
5396 }
5397
55d2375e
SC		 5398 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5399 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5400
5401 if (type > 3) {
5402 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5403 return 1;
5404 }
5405
55d2375e
SC		 5406 /* According to the Intel instruction reference, the memory operand
5407 * is read even if it isn't needed (e.g., for type==all)
5408 */
3573e22c 5409 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
fdb28619
EK		 5410 vmx_instruction_info, false,
5411 sizeof(operand), &gva))
3573e22c
BD		 5412 return 1;
5413
55d2375e 5414 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5415 kvm_inject_page_fault(vcpu, &e);
5416 return 1;
5417 }
5418
55d2375e
SC		 5419 if (operand.pcid >> 12 != 0) {
5420 kvm_inject_gp(vcpu, 0);
5421 return 1;
abfc52c6 5422 }
e29acc55 5423
55d2375e 5424 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5425
55d2375e
SC		 5426 switch (type) {
5427 case INVPCID_TYPE_INDIV_ADDR:
5428 if ((!pcid_enabled && (operand.pcid != 0)) ||
5429 is_noncanonical_address(operand.gla, vcpu)) {
5430 kvm_inject_gp(vcpu, 0);
5431 return 1;
5432 }
5433 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5434 return kvm_skip_emulated_instruction(vcpu);
61ada748 5435
55d2375e
SC		 5436 case INVPCID_TYPE_SINGLE_CTXT:
5437 if (!pcid_enabled && (operand.pcid != 0)) {
5438 kvm_inject_gp(vcpu, 0);
5439 return 1;
5440 }
e29acc55 5441
55d2375e
SC		 5442 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5443 kvm_mmu_sync_roots(vcpu);
5444 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5445 }
e29acc55 5446
55d2375e
SC		 5447 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5448 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5449 == operand.pcid)
5450 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5451
55d2375e
SC		 5452 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5453 /*
5454 * If neither the current cr3 nor any of the prev_roots use the
5455 * given PCID, then nothing needs to be done here because a
5456 * resync will happen anyway before switching to any other CR3.
5457 */
e29acc55 5458
55d2375e 5459 return kvm_skip_emulated_instruction(vcpu);
61ada748 5460
55d2375e
SC		 5461 case INVPCID_TYPE_ALL_NON_GLOBAL:
5462 /*
5463 * Currently, KVM doesn't mark global entries in the shadow
5464 * page tables, so a non-global flush just degenerates to a
5465 * global flush. If needed, we could optimize this later by
5466 * keeping track of global entries in shadow page tables.
5467 */
e29acc55 5468
55d2375e
SC		 5469 /* fall-through */
5470 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5471 kvm_mmu_unload(vcpu);
5472 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5473
55d2375e
SC		 5474 default:
5475 BUG(); /* We have already checked above that type <= 3 */
5476 }
e29acc55
JM		 5477}
5478
55d2375e 5479static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5480{
55d2375e 5481 unsigned long exit_qualification;
b3897a49 5482
55d2375e 5483 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5484
55d2375e 5485 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5486
5487 /*
55d2375e
SC		 5488 * PML buffer FULL happened while executing iret from NMI,
5489 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5490 */
55d2375e
SC		 5491 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5492 enable_vnmi &&
5493 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5494 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5495 GUEST_INTR_STATE_NMI);
e49fcb8b 5496
55d2375e
SC		 5497 /*
5498 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5499 * here.., and there's no userspace involvement needed for PML.
5500 */
ec378aee
NHE		 5501 return 1;
5502}
5503
55d2375e 5504static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5505{
804939ea
SC		 5506 struct vcpu_vmx *vmx = to_vmx(vcpu);
5507
5508 if (!vmx->req_immediate_exit &&
5509 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
55d2375e 5510 kvm_lapic_expired_hv_timer(vcpu);
804939ea 5511
55d2375e 5512 return 1;
8ca44e88
DM		 5513}
5514
55d2375e
SC		 5515/*
5516 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5517 * are overwritten by nested_vmx_setup() when nested=1.
5518 */
5519static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5520{
55d2375e
SC		 5521 kvm_queue_exception(vcpu, UD_VECTOR);
5522 return 1;
b8bbab92
VK		 5523}
5524
55d2375e 5525static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5526{
55d2375e
SC		 5527 /*
5528 * SGX virtualization is not yet supported. There is no software
5529 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5530 * to prevent the guest from executing ENCLS.
5531 */
5532 kvm_queue_exception(vcpu, UD_VECTOR);
5533 return 1;
e7953d7f
AG		 5534}
5535
ec378aee 5536/*
55d2375e
SC		 5537 * The exit handlers return 1 if the exit was handled fully and guest execution
5538 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5539 * to be done to userspace and return 0.
ec378aee 5540 */
55d2375e 5541static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
95b5a48c 5542 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
55d2375e
SC		 5543 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5544 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5545 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5546 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5547 [EXIT_REASON_CR_ACCESS] = handle_cr,
5548 [EXIT_REASON_DR_ACCESS] = handle_dr,
f399e60c
AA		 5549 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5550 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5551 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
9dadc2f9 5552 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
f399e60c 5553 [EXIT_REASON_HLT] = kvm_emulate_halt,
55d2375e
SC		 5554 [EXIT_REASON_INVD] = handle_invd,
5555 [EXIT_REASON_INVLPG] = handle_invlpg,
5556 [EXIT_REASON_RDPMC] = handle_rdpmc,
5557 [EXIT_REASON_VMCALL] = handle_vmcall,
5558 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5559 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5560 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5561 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5562 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5563 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5564 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5565 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5566 [EXIT_REASON_VMON] = handle_vmx_instruction,
5567 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5568 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5569 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5570 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5571 [EXIT_REASON_WBINVD] = handle_wbinvd,
5572 [EXIT_REASON_XSETBV] = handle_xsetbv,
5573 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5574 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5575 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5576 [EXIT_REASON_LDTR_TR] = handle_desc,
5577 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5578 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5579 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5580 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5581 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5582 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5583 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5584 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5585 [EXIT_REASON_RDRAND] = handle_invalid_op,
5586 [EXIT_REASON_RDSEED] = handle_invalid_op,
55d2375e
SC		 5587 [EXIT_REASON_PML_FULL] = handle_pml_full,
5588 [EXIT_REASON_INVPCID] = handle_invpcid,
5589 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5590 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5591 [EXIT_REASON_ENCLS] = handle_encls,
5592};
b8bbab92 5593
55d2375e
SC		 5594static const int kvm_vmx_max_exit_handlers =
5595 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5596
55d2375e 5597static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5598{
55d2375e
SC		 5599 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5600 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5601}
5602
55d2375e 5603static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5604{
55d2375e
SC		 5605 if (vmx->pml_pg) {
5606 __free_page(vmx->pml_pg);
5607 vmx->pml_pg = NULL;
b8bbab92 5608 }
27d6c865
NHE		 5609}
5610
55d2375e 5611static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5612{
55d2375e
SC		 5613 struct vcpu_vmx *vmx = to_vmx(vcpu);
5614 u64 *pml_buf;
5615 u16 pml_idx;
cd232ad0 5616
55d2375e 5617 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5618
55d2375e
SC		 5619 /* Do nothing if PML buffer is empty */
5620 if (pml_idx == (PML_ENTITY_NUM - 1))
5621 return;
cd232ad0 5622
55d2375e
SC		 5623 /* PML index always points to next available PML buffer entity */
5624 if (pml_idx >= PML_ENTITY_NUM)
5625 pml_idx = 0;
5626 else
5627 pml_idx++;
945679e3 5628
55d2375e
SC		 5629 pml_buf = page_address(vmx->pml_pg);
5630 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5631 u64 gpa;
945679e3 5632
55d2375e
SC		 5633 gpa = pml_buf[pml_idx];
5634 WARN_ON(gpa & (PAGE_SIZE - 1));
5635 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5636 }
5637
55d2375e
SC		 5638 /* reset PML index */
5639 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5640}
5641
f4160e45 5642/*
55d2375e
SC		 5643 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5644 * Called before reporting dirty_bitmap to userspace.
f4160e45 5645 */
55d2375e 5646static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5647{
55d2375e
SC		 5648 int i;
5649 struct kvm_vcpu *vcpu;
49f705c5 5650 /*
55d2375e
SC		 5651 * We only need to kick vcpu out of guest mode here, as PML buffer
5652 * is flushed at beginning of all VMEXITs, and it's obvious that only
5653 * vcpus running in guest are possible to have unflushed GPAs in PML
5654 * buffer.
49f705c5 5655 */
55d2375e
SC		 5656 kvm_for_each_vcpu(i, vcpu, kvm)
5657 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5658}
5659
55d2375e 5660static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5661{
55d2375e
SC		 5662 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5663 name, vmcs_read16(sel),
5664 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5665 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5666 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5667}
5668
55d2375e 5669static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5670{
55d2375e
SC		 5671 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5672 name, vmcs_read32(limit),
5673 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5674}
5675
69090810 5676void dump_vmcs(void)
63846663 5677{
6f2f8453
PB		 5678 u32 vmentry_ctl, vmexit_ctl;
5679 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5680 unsigned long cr4;
5681 u64 efer;
55d2375e 5682 int i, n;
63846663 5683
6f2f8453
PB		 5684 if (!dump_invalid_vmcs) {
5685 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5686 return;
5687 }
5688
5689 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5690 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5691 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5692 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5693 cr4 = vmcs_readl(GUEST_CR4);
5694 efer = vmcs_read64(GUEST_IA32_EFER);
5695 secondary_exec_control = 0;
55d2375e
SC		 5696 if (cpu_has_secondary_exec_ctrls())
5697 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5698
55d2375e
SC		 5699 pr_err("*** Guest State ***\n");
5700 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5701 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5702 vmcs_readl(CR0_GUEST_HOST_MASK));
5703 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5704 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5705 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5706 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5707 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5708 {
5709 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5710 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5711 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5712 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5713 }
55d2375e
SC		 5714 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5715 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5716 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5717 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5718 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5719 vmcs_readl(GUEST_SYSENTER_ESP),
5720 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5721 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5722 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5723 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5724 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5725 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5726 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5727 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5728 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5729 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5730 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5731 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5732 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5733 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5734 efer, vmcs_read64(GUEST_IA32_PAT));
5735 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5736 vmcs_read64(GUEST_IA32_DEBUGCTL),
5737 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5738 if (cpu_has_load_perf_global_ctrl() &&
5739 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5740 pr_err("PerfGlobCtl = 0x%016llx\n",
5741 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5742 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5743 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5744 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5745 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5746 vmcs_read32(GUEST_ACTIVITY_STATE));
5747 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5748 pr_err("InterruptStatus = %04x\n",
5749 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5750
55d2375e
SC		 5751 pr_err("*** Host State ***\n");
5752 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5753 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5754 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5755 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5756 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5757 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5758 vmcs_read16(HOST_TR_SELECTOR));
5759 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5760 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5761 vmcs_readl(HOST_TR_BASE));
5762 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5763 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5764 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5765 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5766 vmcs_readl(HOST_CR4));
5767 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5768 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5769 vmcs_read32(HOST_IA32_SYSENTER_CS),
5770 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5771 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5772 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5773 vmcs_read64(HOST_IA32_EFER),
5774 vmcs_read64(HOST_IA32_PAT));
5775 if (cpu_has_load_perf_global_ctrl() &&
5776 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5777 pr_err("PerfGlobCtl = 0x%016llx\n",
5778 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5779
55d2375e
SC		 5780 pr_err("*** Control State ***\n");
5781 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5782 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5783 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5784 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5785 vmcs_read32(EXCEPTION_BITMAP),
5786 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5787 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5788 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5789 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5790 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5791 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5792 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5793 vmcs_read32(VM_EXIT_INTR_INFO),
5794 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5795 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5796 pr_err(" reason=%08x qualification=%016lx\n",
5797 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5798 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5799 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5800 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5801 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5802 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5803 pr_err("TSC Multiplier = 0x%016llx\n",
5804 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5805 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5806 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5807 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5808 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5809 }
d6a85c32 5810 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9d609649
PB		 5811 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5812 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
d6a85c32 5813 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
9d609649 5814 }
55d2375e
SC		 5815 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5816 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5817 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5818 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5819 n = vmcs_read32(CR3_TARGET_COUNT);
5820 for (i = 0; i + 1 < n; i += 4)
5821 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5822 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5823 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5824 if (i < n)
5825 pr_err("CR3 target%u=%016lx\n",
5826 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5827 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5828 pr_err("PLE Gap=%08x Window=%08x\n",
5829 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5830 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5831 pr_err("Virtual processor ID = 0x%04x\n",
5832 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5833}
5834
55d2375e
SC		 5835/*
5836 * The guest has exited. See if we can fix it or if we need userspace
5837 * assistance.
5838 */
1e9e2622
WL		 5839static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5840 enum exit_fastpath_completion exit_fastpath)
ff651cb6 5841{
55d2375e
SC		 5842 struct vcpu_vmx *vmx = to_vmx(vcpu);
5843 u32 exit_reason = vmx->exit_reason;
5844 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5845
55d2375e 5846 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5847
55d2375e
SC		 5848 /*
5849 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5850 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5851 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5852 * mode as if vcpus is in root mode, the PML buffer must has been
5853 * flushed already.
5854 */
5855 if (enable_pml)
5856 vmx_flush_pml_buffer(vcpu);
1dc35dac 5857
55d2375e
SC		 5858 /* If guest state is invalid, start emulating */
5859 if (vmx->emulation_required)
5860 return handle_invalid_guest_state(vcpu);
1dc35dac 5861
55d2375e
SC		 5862 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5863 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5864
55d2375e
SC		 5865 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5866 dump_vmcs();
5867 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5868 vcpu->run->fail_entry.hardware_entry_failure_reason
5869 = exit_reason;
5870 return 0;
9ed38ffa
LP		 5871 }
5872
55d2375e 5873 if (unlikely(vmx->fail)) {
3b20e03a 5874 dump_vmcs();
55d2375e
SC		 5875 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5876 vcpu->run->fail_entry.hardware_entry_failure_reason
5877 = vmcs_read32(VM_INSTRUCTION_ERROR);
5878 return 0;
5879 }
50c28f21 5880
55d2375e
SC		 5881 /*
5882 * Note:
5883 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5884 * delivery event since it indicates guest is accessing MMIO.
5885 * The vm-exit can be triggered again after return to guest that
5886 * will cause infinite loop.
5887 */
5888 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5889 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5890 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5891 exit_reason != EXIT_REASON_PML_FULL &&
5892 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5893 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5894 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5895 vcpu->run->internal.ndata = 3;
5896 vcpu->run->internal.data[0] = vectoring_info;
5897 vcpu->run->internal.data[1] = exit_reason;
5898 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5899 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5900 vcpu->run->internal.ndata++;
5901 vcpu->run->internal.data[3] =
5902 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5903 }
5904 return 0;
5905 }
50c28f21 5906
55d2375e
SC		 5907 if (unlikely(!enable_vnmi &&
5908 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5909 if (vmx_interrupt_allowed(vcpu)) {
5910 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5911 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5912 vcpu->arch.nmi_pending) {
5913 /*
5914 * This CPU don't support us in finding the end of an
5915 * NMI-blocked window if the guest runs with IRQs
5916 * disabled. So we pull the trigger after 1 s of
5917 * futile waiting, but inform the user about this.
5918 */
5919 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5920 "state on VCPU %d after 1 s timeout\n",
5921 __func__, vcpu->vcpu_id);
5922 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5923 }
5924 }
50c28f21 5925
1e9e2622
WL		 5926 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5927 kvm_skip_emulated_instruction(vcpu);
5928 return 1;
c926f2f7
MP		 5929 }
5930
5931 if (exit_reason >= kvm_vmx_max_exit_handlers)
5932 goto unexpected_vmexit;
4289d272 5933#ifdef CONFIG_RETPOLINE
c926f2f7
MP		 5934 if (exit_reason == EXIT_REASON_MSR_WRITE)
5935 return kvm_emulate_wrmsr(vcpu);
5936 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5937 return handle_preemption_timer(vcpu);
5938 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5939 return handle_interrupt_window(vcpu);
5940 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5941 return handle_external_interrupt(vcpu);
5942 else if (exit_reason == EXIT_REASON_HLT)
5943 return kvm_emulate_halt(vcpu);
5944 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5945 return handle_ept_misconfig(vcpu);
4289d272 5946#endif
c926f2f7
MP		 5947
5948 exit_reason = array_index_nospec(exit_reason,
5949 kvm_vmx_max_exit_handlers);
5950 if (!kvm_vmx_exit_handlers[exit_reason])
5951 goto unexpected_vmexit;
5952
5953 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5954
5955unexpected_vmexit:
5956 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
5957 dump_vmcs();
5958 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5959 vcpu->run->internal.suberror =
7396d337 5960 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
c926f2f7
MP		 5961 vcpu->run->internal.ndata = 1;
5962 vcpu->run->internal.data[0] = exit_reason;
5963 return 0;
9ed38ffa
LP		 5964}
5965
efebf0aa 5966/*
55d2375e
SC		 5967 * Software based L1D cache flush which is used when microcode providing
5968 * the cache control MSR is not loaded.
efebf0aa 5969 *
55d2375e
SC		 5970 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5971 * flush it is required to read in 64 KiB because the replacement algorithm
5972 * is not exactly LRU. This could be sized at runtime via topology
5973 * information but as all relevant affected CPUs have 32KiB L1D cache size
5974 * there is no point in doing so.
efebf0aa 5975 */
55d2375e 5976static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5977{
55d2375e 5978 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5979
5980 /*
55d2375e
SC		 5981 * This code is only executed when the the flush mode is 'cond' or
5982 * 'always'
25a2e4fe 5983 */
55d2375e
SC		 5984 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5985 bool flush_l1d;
25a2e4fe 5986
55d2375e
SC		 5987 /*
5988 * Clear the per-vcpu flush bit, it gets set again
5989 * either from vcpu_run() or from one of the unsafe
5990 * VMEXIT handlers.
5991 */
5992 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5993 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5994
55d2375e
SC		 5995 /*
5996 * Clear the per-cpu flush bit, it gets set again from
5997 * the interrupt handlers.
5998 */
5999 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6000 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 6001
55d2375e
SC		 6002 if (!flush_l1d)
6003 return;
6004 }
09abe320 6005
55d2375e 6006 vcpu->stat.l1d_flush++;
25a2e4fe 6007
55d2375e
SC		 6008 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6009 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6010 return;
6011 }
25a2e4fe 6012
55d2375e
SC		 6013 asm volatile(
6014 /* First ensure the pages are in the TLB */
6015 "xorl %%eax, %%eax\n"
6016 ".Lpopulate_tlb:\n\t"
6017 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6018 "addl $4096, %%eax\n\t"
6019 "cmpl %%eax, %[size]\n\t"
6020 "jne .Lpopulate_tlb\n\t"
6021 "xorl %%eax, %%eax\n\t"
6022 "cpuid\n\t"
6023 /* Now fill the cache */
6024 "xorl %%eax, %%eax\n"
6025 ".Lfill_cache:\n"
6026 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6027 "addl $64, %%eax\n\t"
6028 "cmpl %%eax, %[size]\n\t"
6029 "jne .Lfill_cache\n\t"
6030 "lfence\n"
6031 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6032 [size] "r" (size)
6033 : "eax", "ebx", "ecx", "edx");
09abe320 6034}
25a2e4fe 6035
55d2375e 6036static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 6037{
55d2375e 6038 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
132f4f7e 6039 int tpr_threshold;
09abe320 6040
55d2375e
SC		 6041 if (is_guest_mode(vcpu) &&
6042 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6043 return;
25a2e4fe 6044
132f4f7e 6045 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
02d496cf
LA		 6046 if (is_guest_mode(vcpu))
6047 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6048 else
6049 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
8665c3f9
PB		 6050}
6051
55d2375e 6052void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 6053{
fe7f895d 6054 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6055 u32 sec_exec_control;
8665c3f9 6056
55d2375e
SC		 6057 if (!lapic_in_kernel(vcpu))
6058 return;
9314006d 6059
55d2375e
SC		 6060 if (!flexpriority_enabled &&
6061 !cpu_has_vmx_virtualize_x2apic_mode())
6062 return;
705699a1 6063
55d2375e
SC		 6064 /* Postpone execution until vmcs01 is the current VMCS. */
6065 if (is_guest_mode(vcpu)) {
fe7f895d 6066 vmx->nested.change_vmcs01_virtual_apic_mode = true;
55d2375e 6067 return;
6beb7bd5 6068 }
fe3ef05c 6069
fe7f895d 6070 sec_exec_control = secondary_exec_controls_get(vmx);
55d2375e
SC		 6071 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6072 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 6073
55d2375e
SC		 6074 switch (kvm_get_apic_mode(vcpu)) {
6075 case LAPIC_MODE_INVALID:
6076 WARN_ONCE(true, "Invalid local APIC state");
6077 case LAPIC_MODE_DISABLED:
6078 break;
6079 case LAPIC_MODE_XAPIC:
6080 if (flexpriority_enabled) {
6081 sec_exec_control |=
6082 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6083 vmx_flush_tlb(vcpu, true);
6084 }
6085 break;
6086 case LAPIC_MODE_X2APIC:
6087 if (cpu_has_vmx_virtualize_x2apic_mode())
6088 sec_exec_control |=
6089 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6090 break;
09abe320 6091 }
fe7f895d 6092 secondary_exec_controls_set(vmx, sec_exec_control);
09abe320 6093
55d2375e
SC		 6094 vmx_update_msr_bitmap(vcpu);
6095}
0238ea91 6096
55d2375e
SC		 6097static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6098{
6099 if (!is_guest_mode(vcpu)) {
6100 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6101 vmx_flush_tlb(vcpu, true);
6102 }
6103}
fe3ef05c 6104
55d2375e
SC		 6105static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6106{
6107 u16 status;
6108 u8 old;
32c7acf0 6109
55d2375e
SC		 6110 if (max_isr == -1)
6111 max_isr = 0;
608406e2 6112
55d2375e
SC		 6113 status = vmcs_read16(GUEST_INTR_STATUS);
6114 old = status >> 8;
6115 if (max_isr != old) {
6116 status &= 0xff;
6117 status |= max_isr << 8;
6118 vmcs_write16(GUEST_INTR_STATUS, status);
6119 }
6120}
6beb7bd5 6121
55d2375e
SC		 6122static void vmx_set_rvi(int vector)
6123{
6124 u16 status;
6125 u8 old;
0b665d30 6126
55d2375e
SC		 6127 if (vector == -1)
6128 vector = 0;
fe3ef05c 6129
55d2375e
SC		 6130 status = vmcs_read16(GUEST_INTR_STATUS);
6131 old = (u8)status & 0xff;
6132 if ((u8)vector != old) {
6133 status &= ~0xff;
6134 status |= (u8)vector;
6135 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6136 }
55d2375e 6137}
09abe320 6138
55d2375e
SC		 6139static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6140{
09abe320 6141 /*
55d2375e
SC		 6142 * When running L2, updating RVI is only relevant when
6143 * vmcs12 virtual-interrupt-delivery enabled.
6144 * However, it can be enabled only when L1 also
6145 * intercepts external-interrupts and in that case
6146 * we should not update vmcs02 RVI but instead intercept
6147 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6148 */
55d2375e
SC		 6149 if (!is_guest_mode(vcpu))
6150 vmx_set_rvi(max_irr);
6151}
fe3ef05c 6152
55d2375e
SC		 6153static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6154{
6155 struct vcpu_vmx *vmx = to_vmx(vcpu);
6156 int max_irr;
6157 bool max_irr_updated;
a7c0b07d 6158
55d2375e
SC		 6159 WARN_ON(!vcpu->arch.apicv_active);
6160 if (pi_test_on(&vmx->pi_desc)) {
6161 pi_clear_on(&vmx->pi_desc);
6162 /*
d9ff2744 6163 * IOMMU can write to PID.ON, so the barrier matters even on UP.
55d2375e
SC		 6164 * But on x86 this is just a compiler barrier anyway.
6165 */
6166 smp_mb__after_atomic();
6167 max_irr_updated =
6168 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6169
6170 /*
55d2375e
SC		 6171 * If we are running L2 and L1 has a new pending interrupt
6172 * which can be injected, we should re-evaluate
6173 * what should be done with this new L1 interrupt.
6174 * If L1 intercepts external-interrupts, we should
6175 * exit from L2 to L1. Otherwise, interrupt should be
6176 * delivered directly to L2.
c4ebd629 6177 */
55d2375e
SC		 6178 if (is_guest_mode(vcpu) && max_irr_updated) {
6179 if (nested_exit_on_intr(vcpu))
6180 kvm_vcpu_exiting_guest_mode(vcpu);
6181 else
6182 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6183 }
55d2375e
SC		 6184 } else {
6185 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6186 }
55d2375e
SC		 6187 vmx_hwapic_irr_update(vcpu, max_irr);
6188 return max_irr;
6189}
a7c0b07d 6190
17e433b5
WL		 6191static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6192{
9482ae45
JM		 6193 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6194
6195 return pi_test_on(pi_desc) ||
29881b6e 6196 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
17e433b5
WL		 6197}
6198
55d2375e
SC		 6199static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6200{
6201 if (!kvm_vcpu_apicv_active(vcpu))
6202 return;
25a2e4fe 6203
55d2375e
SC		 6204 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6205 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6206 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6207 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6208}
6209
55d2375e 6210static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6211{
6212 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6213
55d2375e
SC		 6214 pi_clear_on(&vmx->pi_desc);
6215 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6216}
8665c3f9 6217
95b5a48c 6218static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
55d2375e 6219{
beb8d93b 6220 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6221
55d2375e 6222 /* if exit due to PF check for async PF */
d71f5e03 6223 if (is_page_fault(vmx->exit_intr_info)) {
55d2375e 6224 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
55d2375e 6225 /* Handle machine checks before interrupts are enabled */
d71f5e03 6226 } else if (is_machine_check(vmx->exit_intr_info)) {
55d2375e 6227 kvm_machine_check();
55d2375e 6228 /* We need to handle NMIs before interrupts are enabled */
d71f5e03 6229 } else if (is_nmi(vmx->exit_intr_info)) {
55d2375e
SC		 6230 kvm_before_interrupt(&vmx->vcpu);
6231 asm("int $2");
6232 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6233 }
55d2375e 6234}
fe3ef05c 6235
95b5a48c 6236static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
55d2375e 6237{
49def500
SC		 6238 unsigned int vector;
6239 unsigned long entry;
55d2375e 6240#ifdef CONFIG_X86_64
49def500 6241 unsigned long tmp;
55d2375e 6242#endif
49def500
SC		 6243 gate_desc *desc;
6244 u32 intr_info;
fe3ef05c 6245
49def500
SC		 6246 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6247 if (WARN_ONCE(!is_external_intr(intr_info),
6248 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6249 return;
6250
6251 vector = intr_info & INTR_INFO_VECTOR_MASK;
2342080c 6252 desc = (gate_desc *)host_idt_base + vector;
49def500
SC		 6253 entry = gate_offset(desc);
6254
165072b0
SC		 6255 kvm_before_interrupt(vcpu);
6256
49def500 6257 asm volatile(
55d2375e 6258#ifdef CONFIG_X86_64
49def500
SC		 6259 "mov %%" _ASM_SP ", %[sp]\n\t"
6260 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6261 "push $%c[ss]\n\t"
6262 "push %[sp]\n\t"
55d2375e 6263#endif
49def500
SC		 6264 "pushf\n\t"
6265 __ASM_SIZE(push) " $%c[cs]\n\t"
6266 CALL_NOSPEC
6267 :
55d2375e 6268#ifdef CONFIG_X86_64
49def500 6269 [sp]"=&r"(tmp),
55d2375e 6270#endif
49def500
SC		 6271 ASM_CALL_CONSTRAINT
6272 :
6273 THUNK_TARGET(entry),
6274 [ss]"i"(__KERNEL_DS),
6275 [cs]"i"(__KERNEL_CS)
6276 );
165072b0
SC		 6277
6278 kvm_after_interrupt(vcpu);
55d2375e 6279}
95b5a48c
SC		 6280STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6281
1e9e2622
WL		 6282static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6283 enum exit_fastpath_completion *exit_fastpath)
95b5a48c
SC		 6284{
6285 struct vcpu_vmx *vmx = to_vmx(vcpu);
6286
6287 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6288 handle_external_interrupt_irqoff(vcpu);
6289 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6290 handle_exception_nmi_irqoff(vmx);
1e9e2622
WL		 6291 else if (!is_guest_mode(vcpu) &&
6292 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6293 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
95b5a48c 6294}
5a6a9748 6295
55d2375e
SC		 6296static bool vmx_has_emulated_msr(int index)
6297{
6298 switch (index) {
6299 case MSR_IA32_SMBASE:
6300 /*
6301 * We cannot do SMM unless we can run the guest in big
6302 * real mode.
6303 */
6304 return enable_unrestricted_guest || emulate_invalid_guest_state;
95c5c7c7
PB		 6305 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6306 return nested;
55d2375e
SC		 6307 case MSR_AMD64_VIRT_SPEC_CTRL:
6308 /* This is AMD only. */
6309 return false;
6310 default:
6311 return true;
3184a995 6312 }
55d2375e 6313}
2bb8cafe 6314
86f5201d
CP		 6315static bool vmx_pt_supported(void)
6316{
6317 return pt_mode == PT_MODE_HOST_GUEST;
6318}
6319
55d2375e
SC		 6320static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6321{
6322 u32 exit_intr_info;
6323 bool unblock_nmi;
6324 u8 vector;
6325 bool idtv_info_valid;
7ca29de2 6326
55d2375e 6327 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6328
55d2375e
SC		 6329 if (enable_vnmi) {
6330 if (vmx->loaded_vmcs->nmi_known_unmasked)
6331 return;
6332 /*
6333 * Can't use vmx->exit_intr_info since we're not sure what
6334 * the exit reason is.
6335 */
6336 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6337 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6338 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6339 /*
6340 * SDM 3: 27.7.1.2 (September 2008)
6341 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6342 * a guest IRET fault.
6343 * SDM 3: 23.2.2 (September 2008)
6344 * Bit 12 is undefined in any of the following cases:
6345 * If the VM exit sets the valid bit in the IDT-vectoring
6346 * information field.
6347 * If the VM exit is due to a double fault.
6348 */
6349 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6350 vector != DF_VECTOR && !idtv_info_valid)
6351 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6352 GUEST_INTR_STATE_NMI);
6353 else
6354 vmx->loaded_vmcs->nmi_known_unmasked =
6355 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6356 & GUEST_INTR_STATE_NMI);
6357 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6358 vmx->loaded_vmcs->vnmi_blocked_time +=
6359 ktime_to_ns(ktime_sub(ktime_get(),
6360 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6361}
6362
55d2375e
SC		 6363static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6364 u32 idt_vectoring_info,
6365 int instr_len_field,
6366 int error_code_field)
0c7f650e 6367{
55d2375e
SC		 6368 u8 vector;
6369 int type;
6370 bool idtv_info_valid;
0c7f650e 6371
55d2375e 6372 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6373
55d2375e
SC		 6374 vcpu->arch.nmi_injected = false;
6375 kvm_clear_exception_queue(vcpu);
6376 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6377
55d2375e
SC		 6378 if (!idtv_info_valid)
6379 return;
c7c2c709 6380
55d2375e 6381 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6382
55d2375e
SC		 6383 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6384 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6385
55d2375e
SC		 6386 switch (type) {
6387 case INTR_TYPE_NMI_INTR:
6388 vcpu->arch.nmi_injected = true;
6389 /*
6390 * SDM 3: 27.7.1.2 (September 2008)
6391 * Clear bit "block by NMI" before VM entry if a NMI
6392 * delivery faulted.
6393 */
6394 vmx_set_nmi_mask(vcpu, false);
6395 break;
6396 case INTR_TYPE_SOFT_EXCEPTION:
6397 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6398 /* fall through */
6399 case INTR_TYPE_HARD_EXCEPTION:
6400 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6401 u32 err = vmcs_read32(error_code_field);
6402 kvm_requeue_exception_e(vcpu, vector, err);
6403 } else
6404 kvm_requeue_exception(vcpu, vector);
6405 break;
6406 case INTR_TYPE_SOFT_INTR:
6407 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6408 /* fall through */
6409 case INTR_TYPE_EXT_INTR:
6410 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6411 break;
6412 default:
6413 break;
0447378a 6414 }
ca0bde28
JM		 6415}
6416
55d2375e 6417static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6418{
55d2375e
SC		 6419 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6420 VM_EXIT_INSTRUCTION_LEN,
6421 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6422}
6423
55d2375e 6424static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6425{
55d2375e
SC		 6426 __vmx_complete_interrupts(vcpu,
6427 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6428 VM_ENTRY_INSTRUCTION_LEN,
6429 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6430
55d2375e 6431 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6432}
6433
55d2375e 6434static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6435{
55d2375e
SC		 6436 int i, nr_msrs;
6437 struct perf_guest_switch_msr *msrs;
7c177938 6438
55d2375e 6439 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6440
55d2375e
SC		 6441 if (!msrs)
6442 return;
f1b026a3 6443
55d2375e
SC		 6444 for (i = 0; i < nr_msrs; i++)
6445 if (msrs[i].host == msrs[i].guest)
6446 clear_atomic_switch_msr(vmx, msrs[i].msr);
6447 else
6448 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6449 msrs[i].host, false);
ca0bde28 6450}
52017608 6451
6e3ba4ab
TX		 6452static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6453{
6454 u32 host_umwait_control;
6455
6456 if (!vmx_has_waitpkg(vmx))
6457 return;
6458
6459 host_umwait_control = get_umwait_control_msr();
6460
6461 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6462 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6463 vmx->msr_ia32_umwait_control,
6464 host_umwait_control, false);
6465 else
6466 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6467}
6468
55d2375e 6469static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6470{
6471 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6472 u64 tscl;
6473 u32 delta_tsc;
52017608 6474
55d2375e 6475 if (vmx->req_immediate_exit) {
804939ea
SC		 6476 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6477 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6478 } else if (vmx->hv_deadline_tsc != -1) {
55d2375e
SC		 6479 tscl = rdtsc();
6480 if (vmx->hv_deadline_tsc > tscl)
6481 /* set_hv_timer ensures the delta fits in 32-bits */
6482 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6483 cpu_preemption_timer_multi);
6484 else
6485 delta_tsc = 0;
858e25c0 6486
804939ea
SC		 6487 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6488 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6489 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6490 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6491 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
7f7f1ba3 6492 }
858e25c0
JM		 6493}
6494
c09b03eb 6495void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6496{
c09b03eb
SC		 6497 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6498 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6499 vmcs_writel(HOST_RSP, host_rsp);
6500 }
5ad6ece8 6501}
5f3d5799 6502
fc2ba5a2 6503bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6504
6505static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6506{
6507 struct vcpu_vmx *vmx = to_vmx(vcpu);
6508 unsigned long cr3, cr4;
6509
6510 /* Record the guest's net vcpu time for enforced NMI injections. */
6511 if (unlikely(!enable_vnmi &&
6512 vmx->loaded_vmcs->soft_vnmi_blocked))
6513 vmx->loaded_vmcs->entry_time = ktime_get();
6514
6515 /* Don't enter VMX if guest state is invalid, let the exit handler
6516 start emulation until we arrive back to a valid state */
6517 if (vmx->emulation_required)
6518 return;
6519
6520 if (vmx->ple_window_dirty) {
6521 vmx->ple_window_dirty = false;
6522 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6523 }
6524
c9dfd3fb 6525 /*
6526 * We did this in prepare_switch_to_guest, because it needs to
6527 * be within srcu_read_lock.
6528 */
6529 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
5ad6ece8 6530
cb3c1e2f 6531 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
5ad6ece8 6532 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
cb3c1e2f 6533 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
5ad6ece8
SC		 6534 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6535
6536 cr3 = __get_current_cr3_fast();
6537 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6538 vmcs_writel(HOST_CR3, cr3);
6539 vmx->loaded_vmcs->host_state.cr3 = cr3;
6540 }
6541
6542 cr4 = cr4_read_shadow();
6543 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6544 vmcs_writel(HOST_CR4, cr4);
6545 vmx->loaded_vmcs->host_state.cr4 = cr4;
6546 }
6547
6548 /* When single-stepping over STI and MOV SS, we must clear the
6549 * corresponding interruptibility bits in the guest state. Otherwise
6550 * vmentry fails as it then expects bit 14 (BS) in pending debug
6551 * exceptions being set, but that's not correct for the guest debugging
6552 * case. */
6553 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6554 vmx_set_interrupt_shadow(vcpu, 0);
6555
139a12cf 6556 kvm_load_guest_xsave_state(vcpu);
1811d979 6557
5ad6ece8
SC		 6558 if (static_cpu_has(X86_FEATURE_PKU) &&
6559 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6560 vcpu->arch.pkru != vmx->host_pkru)
6561 __write_pkru(vcpu->arch.pkru);
6562
6563 pt_guest_enter(vmx);
6564
6565 atomic_switch_perf_msrs(vmx);
6e3ba4ab 6566 atomic_switch_umwait_control_msr(vmx);
5ad6ece8 6567
804939ea
SC		 6568 if (enable_preemption_timer)
6569 vmx_update_hv_timer(vcpu);
5ad6ece8 6570
b6c4bc65
WL		 6571 if (lapic_in_kernel(vcpu) &&
6572 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6573 kvm_wait_lapic_expire(vcpu);
6574
5ad6ece8
SC		 6575 /*
6576 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6577 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6578 * is no need to worry about the conditional branch over the wrmsr
6579 * being speculatively taken.
6580 */
6581 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6582
fa4bff16 6583 /* L1D Flush includes CPU buffer clear to mitigate MDS */
c823dd5c
SC		 6584 if (static_branch_unlikely(&vmx_l1d_should_flush))
6585 vmx_l1d_flush(vcpu);
fa4bff16
LT		 6586 else if (static_branch_unlikely(&mds_user_clear))
6587 mds_clear_cpu_buffers();
c823dd5c
SC		 6588
6589 if (vcpu->arch.cr2 != read_cr2())
6590 write_cr2(vcpu->arch.cr2);
6591
fc2ba5a2
SC		 6592 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6593 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6594
6595 vcpu->arch.cr2 = read_cr2();
b6b8a145 6596
55d2375e
SC		 6597 /*
6598 * We do not use IBRS in the kernel. If this vCPU has used the
6599 * SPEC_CTRL MSR it may have left it on; save the value and
6600 * turn it off. This is much more efficient than blindly adding
6601 * it to the atomic save/restore list. Especially as the former
6602 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6603 *
6604 * For non-nested case:
6605 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6606 * save it.
6607 *
6608 * For nested case:
6609 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6610 * save it.
6611 */
6612 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6613 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6614
55d2375e 6615 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6616
55d2375e
SC		 6617 /* All fields are clean at this point */
6618 if (static_branch_unlikely(&enable_evmcs))
6619 current_evmcs->hv_clean_fields |=
6620 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6621
6f6a657c
VK		 6622 if (static_branch_unlikely(&enable_evmcs))
6623 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6624
55d2375e
SC		 6625 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6626 if (vmx->host_debugctlmsr)
6627 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6628
55d2375e
SC		 6629#ifndef CONFIG_X86_64
6630 /*
6631 * The sysexit path does not restore ds/es, so we must set them to
6632 * a reasonable value ourselves.
6633 *
6634 * We can't defer this to vmx_prepare_switch_to_host() since that
6635 * function may be executed in interrupt context, which saves and
6636 * restore segments around it, nullifying its effect.
6637 */
6638 loadsegment(ds, __USER_DS);
6639 loadsegment(es, __USER_DS);
6640#endif
4704d0be 6641
55d2375e
SC		 6642 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6643 | (1 << VCPU_EXREG_RFLAGS)
6644 | (1 << VCPU_EXREG_PDPTR)
6645 | (1 << VCPU_EXREG_SEGMENTS)
6646 | (1 << VCPU_EXREG_CR3));
6647 vcpu->arch.regs_dirty = 0;
7854cbca 6648
2ef444f1
CP		 6649 pt_guest_exit(vmx);
6650
3633cfc3 6651 /*
55d2375e
SC		 6652 * eager fpu is enabled if PKEY is supported and CR4 is switched
6653 * back on host, so it is safe to read guest PKRU from current
6654 * XSAVE.
3633cfc3 6655 */
55d2375e
SC		 6656 if (static_cpu_has(X86_FEATURE_PKU) &&
6657 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
c806e887 6658 vcpu->arch.pkru = rdpkru();
55d2375e
SC		 6659 if (vcpu->arch.pkru != vmx->host_pkru)
6660 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6661 }
6662
139a12cf 6663 kvm_load_host_xsave_state(vcpu);
1811d979 6664
55d2375e
SC		 6665 vmx->nested.nested_run_pending = 0;
6666 vmx->idt_vectoring_info = 0;
119a9c01 6667
55d2375e 6668 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
beb8d93b
SC		 6669 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6670 kvm_machine_check();
6671
55d2375e
SC		 6672 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6673 return;
608406e2 6674
55d2375e
SC		 6675 vmx->loaded_vmcs->launched = 1;
6676 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6677
55d2375e
SC		 6678 vmx_recover_nmi_blocking(vmx);
6679 vmx_complete_interrupts(vmx);
6680}
2996fca0 6681
55d2375e 6682static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6683{
55d2375e 6684 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6685
55d2375e
SC		 6686 if (enable_pml)
6687 vmx_destroy_pml_buffer(vmx);
6688 free_vpid(vmx->vpid);
55d2375e
SC		 6689 nested_vmx_free_vcpu(vcpu);
6690 free_loaded_vmcs(vmx->loaded_vmcs);
55d2375e 6691}
4704d0be 6692
987b2594 6693static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
55d2375e 6694{
41836839 6695 struct vcpu_vmx *vmx;
55d2375e 6696 unsigned long *msr_bitmap;
34109c04 6697 int i, cpu, err;
4704d0be 6698
a9dd6f09
SC		 6699 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6700 vmx = to_vmx(vcpu);
d9a710e5 6701
55d2375e 6702 err = -ENOMEM;
b666a4b6 6703
55d2375e 6704 vmx->vpid = allocate_vpid();
7cdc2d62 6705
5f3d5799 6706 /*
55d2375e
SC		 6707 * If PML is turned on, failure on enabling PML just results in failure
6708 * of creating the vcpu, therefore we can simplify PML logic (by
6709 * avoiding dealing with cases, such as enabling PML partially on vcpus
67b0ae43 6710 * for the guest), etc.
5f3d5799 6711 */
55d2375e 6712 if (enable_pml) {
41836839 6713 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e 6714 if (!vmx->pml_pg)
987b2594 6715 goto free_vpid;
55d2375e 6716 }
4704d0be 6717
7d73710d 6718 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
4704d0be 6719
4be53410
XL		 6720 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6721 u32 index = vmx_msr_index[i];
6722 u32 data_low, data_high;
6723 int j = vmx->nmsrs;
6724
6725 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6726 continue;
6727 if (wrmsr_safe(index, data_low, data_high) < 0)
6728 continue;
46f4f0aa 6729
4be53410
XL		 6730 vmx->guest_msrs[j].index = i;
6731 vmx->guest_msrs[j].data = 0;
46f4f0aa
PB		 6732 switch (index) {
6733 case MSR_IA32_TSX_CTRL:
6734 /*
6735 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6736 * let's avoid changing CPUID bits under the host
6737 * kernel's feet.
6738 */
6739 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6740 break;
6741 default:
6742 vmx->guest_msrs[j].mask = -1ull;
6743 break;
6744 }
4be53410
XL		 6745 ++vmx->nmsrs;
6746 }
6747
55d2375e
SC		 6748 err = alloc_loaded_vmcs(&vmx->vmcs01);
6749 if (err < 0)
7d73710d 6750 goto free_pml;
cb61de2f 6751
55d2375e 6752 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6753 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6754 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6755 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6756 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6757 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6758 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6759 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
987b2594 6760 if (kvm_cstate_in_guest(vcpu->kvm)) {
b5170063
WL		 6761 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6762 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6763 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6764 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6765 }
55d2375e 6766 vmx->msr_bitmap_mode = 0;
4704d0be 6767
55d2375e
SC		 6768 vmx->loaded_vmcs = &vmx->vmcs01;
6769 cpu = get_cpu();
34109c04
SC		 6770 vmx_vcpu_load(vcpu, cpu);
6771 vcpu->cpu = cpu;
1b84292b 6772 init_vmcs(vmx);
34109c04 6773 vmx_vcpu_put(vcpu);
55d2375e 6774 put_cpu();
34109c04 6775 if (cpu_need_virtualize_apic_accesses(vcpu)) {
987b2594 6776 err = alloc_apic_access_page(vcpu->kvm);
55d2375e
SC		 6777 if (err)
6778 goto free_vmcs;
6779 }
6780
6781 if (enable_ept && !enable_unrestricted_guest) {
987b2594 6782 err = init_rmode_identity_map(vcpu->kvm);
55d2375e
SC		 6783 if (err)
6784 goto free_vmcs;
6785 }
4704d0be 6786
55d2375e
SC		 6787 if (nested)
6788 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
a4443267 6789 vmx_capability.ept);
55d2375e
SC		 6790 else
6791 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6792
55d2375e
SC		 6793 vmx->nested.posted_intr_nv = -1;
6794 vmx->nested.current_vmptr = -1ull;
bd18bffc 6795
bab0c318 6796 vcpu->arch.microcode_version = 0x100000000ULL;
32ad73db 6797 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
feaf0c7d 6798
6f1e03bc 6799 /*
55d2375e
SC		 6800 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6801 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6802 */
55d2375e
SC		 6803 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6804 vmx->pi_desc.sn = 1;
4704d0be 6805
53963a70
LT		 6806 vmx->ept_pointer = INVALID_PAGE;
6807
a9dd6f09 6808 return 0;
4704d0be 6809
55d2375e
SC		 6810free_vmcs:
6811 free_loaded_vmcs(vmx->loaded_vmcs);
55d2375e
SC		 6812free_pml:
6813 vmx_destroy_pml_buffer(vmx);
987b2594 6814free_vpid:
55d2375e 6815 free_vpid(vmx->vpid);
a9dd6f09 6816 return err;
55d2375e 6817}
36be0b9d 6818
65fd4cb6
TG		 6819#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6820#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
21feb4eb 6821
55d2375e
SC		 6822static int vmx_vm_init(struct kvm *kvm)
6823{
6824 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6825
55d2375e
SC		 6826 if (!ple_gap)
6827 kvm->arch.pause_in_guest = true;
3af18d9c 6828
55d2375e
SC		 6829 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6830 switch (l1tf_mitigation) {
6831 case L1TF_MITIGATION_OFF:
6832 case L1TF_MITIGATION_FLUSH_NOWARN:
6833 /* 'I explicitly don't care' is set */
6834 break;
6835 case L1TF_MITIGATION_FLUSH:
6836 case L1TF_MITIGATION_FLUSH_NOSMT:
6837 case L1TF_MITIGATION_FULL:
6838 /*
6839 * Warn upon starting the first VM in a potentially
6840 * insecure environment.
6841 */
b284909a 6842 if (sched_smt_active())
55d2375e
SC		 6843 pr_warn_once(L1TF_MSG_SMT);
6844 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6845 pr_warn_once(L1TF_MSG_L1D);
6846 break;
6847 case L1TF_MITIGATION_FULL_FORCE:
6848 /* Flush is enforced */
6849 break;
6850 }
6851 }
4e19c36f 6852 kvm_apicv_init(kvm, enable_apicv);
55d2375e 6853 return 0;
4704d0be
NHE		 6854}
6855
f257d6dc 6856static int __init vmx_check_processor_compat(void)
bd18bffc 6857{
55d2375e
SC		 6858 struct vmcs_config vmcs_conf;
6859 struct vmx_capability vmx_cap;
bd18bffc 6860
ff10e22e
SC		 6861 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6862 !this_cpu_has(X86_FEATURE_VMX)) {
6863 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6864 return -EIO;
6865 }
6866
55d2375e 6867 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
f257d6dc 6868 return -EIO;
55d2375e 6869 if (nested)
a4443267 6870 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
55d2375e
SC		 6871 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6872 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6873 smp_processor_id());
f257d6dc 6874 return -EIO;
bd18bffc 6875 }
f257d6dc 6876 return 0;
bd18bffc
SC		 6877}
6878
55d2375e 6879static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6880{
55d2375e
SC		 6881 u8 cache;
6882 u64 ipat = 0;
bd18bffc 6883
222f06e7
CW		 6884 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6885 * memory aliases with conflicting memory types and sometimes MCEs.
6886 * We have to be careful as to what are honored and when.
6887 *
6888 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
6889 * UC. The effective memory type is UC or WC depending on guest PAT.
6890 * This was historically the source of MCEs and we want to be
6891 * conservative.
6892 *
6893 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6894 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
6895 * EPT memory type is set to WB. The effective memory type is forced
6896 * WB.
6897 *
6898 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
6899 * EPT memory type is used to emulate guest CD/MTRR.
bd18bffc 6900 */
222f06e7 6901
55d2375e
SC		 6902 if (is_mmio) {
6903 cache = MTRR_TYPE_UNCACHABLE;
6904 goto exit;
6905 }
bd18bffc 6906
55d2375e
SC		 6907 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6908 ipat = VMX_EPT_IPAT_BIT;
6909 cache = MTRR_TYPE_WRBACK;
6910 goto exit;
6911 }
bd18bffc 6912
55d2375e
SC		 6913 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6914 ipat = VMX_EPT_IPAT_BIT;
6915 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6916 cache = MTRR_TYPE_WRBACK;
6917 else
6918 cache = MTRR_TYPE_UNCACHABLE;
6919 goto exit;
6920 }
bd18bffc 6921
55d2375e 6922 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6923
55d2375e
SC		 6924exit:
6925 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6926}
bd18bffc 6927
55d2375e
SC		 6928static int vmx_get_lpage_level(void)
6929{
6930 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6931 return PT_DIRECTORY_LEVEL;
6932 else
6933 /* For shadow and EPT supported 1GB page */
6934 return PT_PDPE_LEVEL;
6935}
bd18bffc 6936
fe7f895d 6937static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
55d2375e 6938{
bd18bffc 6939 /*
55d2375e
SC		 6940 * These bits in the secondary execution controls field
6941 * are dynamic, the others are mostly based on the hypervisor
6942 * architecture and the guest's CPUID. Do not touch the
6943 * dynamic bits.
bd18bffc 6944 */
55d2375e
SC		 6945 u32 mask =
6946 SECONDARY_EXEC_SHADOW_VMCS |
6947 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6948 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6949 SECONDARY_EXEC_DESC;
bd18bffc 6950
fe7f895d
SC		 6951 u32 new_ctl = vmx->secondary_exec_control;
6952 u32 cur_ctl = secondary_exec_controls_get(vmx);
bd18bffc 6953
fe7f895d 6954 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6955}
6956
4704d0be 6957/*
55d2375e
SC		 6958 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6959 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6960 */
55d2375e 6961static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6962{
6963 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6964 struct kvm_cpuid_entry2 *entry;
4704d0be 6965
55d2375e
SC		 6966 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6967 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6968
55d2375e
SC		 6969#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6970 if (entry && (entry->_reg & (_cpuid_mask))) \
6971 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6972} while (0)
ff651cb6 6973
55d2375e 6974 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
87382003
SC		 6975 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
6976 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
6977 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
6978 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
6979 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
6980 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
6981 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
6982 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
6983 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
6984 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
6985 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
6986 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
6987 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
6988 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
61ada748 6989
55d2375e 6990 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
87382003
SC		 6991 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
6992 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
6993 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
6994 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
6995 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
6996 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
cf3215d9 6997
55d2375e
SC		 6998#undef cr4_fixed1_update
6999}
36c3cc42 7000
55d2375e
SC		 7001static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7002{
7003 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 7004
55d2375e
SC		 7005 if (kvm_mpx_supported()) {
7006 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 7007
55d2375e
SC		 7008 if (mpx_enabled) {
7009 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7010 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7011 } else {
7012 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7013 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7014 }
dccbfcf5 7015 }
55d2375e 7016}
4704d0be 7017
6c0f0bba
LK		 7018static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7019{
7020 struct vcpu_vmx *vmx = to_vmx(vcpu);
7021 struct kvm_cpuid_entry2 *best = NULL;
7022 int i;
7023
7024 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7025 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7026 if (!best)
7027 return;
7028 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7029 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7030 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7031 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7032 }
7033
7034 /* Get the number of configurable Address Ranges for filtering */
7035 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7036 PT_CAP_num_address_ranges);
7037
7038 /* Initialize and clear the no dependency bits */
7039 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7040 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7041
7042 /*
7043 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7044 * will inject an #GP
7045 */
7046 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7047 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7048
7049 /*
7050 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7051 * PSBFreq can be set
7052 */
7053 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7054 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7055 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7056
7057 /*
7058 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7059 * MTCFreq can be set
7060 */
7061 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7062 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7063 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7064
7065 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7066 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7067 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7068 RTIT_CTL_PTW_EN);
7069
7070 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7071 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7072 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7073
7074 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7075 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7076 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7077
7078 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7079 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7080 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7081
7082 /* unmask address range configure area */
7083 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 7084 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 7085}
7086
55d2375e
SC		 7087static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7088{
7089 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 7090
7204160e
AL		 7091 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7092 vcpu->arch.xsaves_enabled = false;
7093
55d2375e
SC		 7094 if (cpu_has_secondary_exec_ctrls()) {
7095 vmx_compute_secondary_exec_control(vmx);
fe7f895d 7096 vmcs_set_secondary_exec_control(vmx);
705699a1 7097 }
4704d0be 7098
55d2375e
SC		 7099 if (nested_vmx_allowed(vcpu))
7100 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
32ad73db
SC		 7101 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7102 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
55d2375e
SC		 7103 else
7104 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
32ad73db
SC		 7105 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7106 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
4f350c6d 7107
55d2375e
SC		 7108 if (nested_vmx_allowed(vcpu)) {
7109 nested_vmx_cr_fixed1_bits_update(vcpu);
7110 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 7111 }
6c0f0bba
LK		 7112
7113 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7114 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7115 update_intel_pt_cfg(vcpu);
b07a5c53
PB		 7116
7117 if (boot_cpu_has(X86_FEATURE_RTM)) {
7118 struct shared_msr_entry *msr;
7119 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7120 if (msr) {
7121 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7122 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7123 }
7124 }
55d2375e 7125}
09abb5e3 7126
55d2375e
SC		 7127static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7128{
7129 if (func == 1 && nested)
87382003 7130 entry->ecx |= feature_bit(VMX);
4704d0be
NHE		 7131}
7132
55d2375e 7133static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 7134{
55d2375e 7135 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 7136}
7137
35a57134
OU		 7138static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7139 struct x86_instruction_info *info)
7140{
7141 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7142 unsigned short port;
7143 bool intercept;
7144 int size;
7145
7146 if (info->intercept == x86_intercept_in ||
7147 info->intercept == x86_intercept_ins) {
7148 port = info->src_val;
7149 size = info->dst_bytes;
7150 } else {
7151 port = info->dst_val;
7152 size = info->src_bytes;
7153 }
7154
7155 /*
7156 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7157 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7158 * control.
7159 *
7160 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7161 */
7162 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7163 intercept = nested_cpu_has(vmcs12,
7164 CPU_BASED_UNCOND_IO_EXITING);
7165 else
7166 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7167
7168 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7169}
7170
8a76d7f2
JR		 7171static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7172 struct x86_instruction_info *info,
7173 enum x86_intercept_stage stage)
7174{
fb6d4d34
PB		 7175 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7176 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7177
35a57134 7178 switch (info->intercept) {
fb6d4d34
PB		 7179 /*
7180 * RDPID causes #UD if disabled through secondary execution controls.
7181 * Because it is marked as EmulateOnUD, we need to intercept it here.
7182 */
35a57134
OU		 7183 case x86_intercept_rdtscp:
7184 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7185 ctxt->exception.vector = UD_VECTOR;
7186 ctxt->exception.error_code_valid = false;
7187 return X86EMUL_PROPAGATE_FAULT;
7188 }
7189 break;
7190
7191 case x86_intercept_in:
7192 case x86_intercept_ins:
7193 case x86_intercept_out:
7194 case x86_intercept_outs:
7195 return vmx_check_intercept_io(vcpu, info);
fb6d4d34
PB		 7196
7197 /* TODO: check more intercepts... */
35a57134
OU		 7198 default:
7199 break;
7200 }
7201
07721fee 7202 return X86EMUL_UNHANDLEABLE;
8a76d7f2
JR		 7203}
7204
64672c95
YJ		 7205#ifdef CONFIG_X86_64
7206/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7207static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7208 u64 divisor, u64 *result)
7209{
7210 u64 low = a << shift, high = a >> (64 - shift);
7211
7212 /* To avoid the overflow on divq */
7213 if (high >= divisor)
7214 return 1;
7215
7216 /* Low hold the result, high hold rem which is discarded */
7217 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7218 "rm" (divisor), "0" (low), "1" (high));
7219 *result = low;
7220
7221 return 0;
7222}
7223
f9927982
SC		 7224static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7225 bool *expired)
64672c95 7226{
386c6ddb 7227 struct vcpu_vmx *vmx;
c5ce8235 7228 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
39497d76 7229 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
386c6ddb 7230
0c5f81da
WL		 7231 if (kvm_mwait_in_guest(vcpu->kvm) ||
7232 kvm_can_post_timer_interrupt(vcpu))
386c6ddb
KA		 7233 return -EOPNOTSUPP;
7234
7235 vmx = to_vmx(vcpu);
7236 tscl = rdtsc();
7237 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7238 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
39497d76
SC		 7239 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7240 ktimer->timer_advance_ns);
c5ce8235
WL		 7241
7242 if (delta_tsc > lapic_timer_advance_cycles)
7243 delta_tsc -= lapic_timer_advance_cycles;
7244 else
7245 delta_tsc = 0;
64672c95
YJ		 7246
7247 /* Convert to host delta tsc if tsc scaling is enabled */
7248 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
0967fa1c 7249 delta_tsc && u64_shl_div_u64(delta_tsc,
64672c95 7250 kvm_tsc_scaling_ratio_frac_bits,
0967fa1c 7251 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
64672c95
YJ		 7252 return -ERANGE;
7253
7254 /*
7255 * If the delta tsc can't fit in the 32 bit after the multi shift,
7256 * we can't use the preemption timer.
7257 * It's possible that it fits on later vmentries, but checking
7258 * on every vmentry is costly so we just use an hrtimer.
7259 */
7260 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7261 return -ERANGE;
7262
7263 vmx->hv_deadline_tsc = tscl + delta_tsc;
f9927982
SC		 7264 *expired = !delta_tsc;
7265 return 0;
64672c95
YJ		 7266}
7267
7268static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7269{
f459a707 7270 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7271}
7272#endif
7273
48d89b92 7274static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7275{
b31c114b 7276 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7277 shrink_ple_window(vcpu);
ae97a3b8
RK		 7278}
7279
843e4330
KH		 7280static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7281 struct kvm_memory_slot *slot)
7282{
7283 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7284 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7285}
7286
7287static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7288 struct kvm_memory_slot *slot)
7289{
7290 kvm_mmu_slot_set_dirty(kvm, slot);
7291}
7292
7293static void vmx_flush_log_dirty(struct kvm *kvm)
7294{
7295 kvm_flush_pml_buffers(kvm);
7296}
7297
c5f983f6
BD		 7298static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7299{
7300 struct vmcs12 *vmcs12;
7301 struct vcpu_vmx *vmx = to_vmx(vcpu);
3d5f6beb 7302 gpa_t gpa, dst;
c5f983f6
BD		 7303
7304 if (is_guest_mode(vcpu)) {
7305 WARN_ON_ONCE(vmx->nested.pml_full);
7306
7307 /*
7308 * Check if PML is enabled for the nested guest.
7309 * Whether eptp bit 6 is set is already checked
7310 * as part of A/D emulation.
7311 */
7312 vmcs12 = get_vmcs12(vcpu);
7313 if (!nested_cpu_has_pml(vmcs12))
7314 return 0;
7315
4769886b 7316 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7317 vmx->nested.pml_full = true;
7318 return 1;
7319 }
7320
7321 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
3d5f6beb 7322 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
c5f983f6 7323
3d5f6beb
KA		 7324 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7325 offset_in_page(dst), sizeof(gpa)))
c5f983f6
BD		 7326 return 0;
7327
3d5f6beb 7328 vmcs12->guest_pml_index--;
c5f983f6
BD		 7329 }
7330
7331 return 0;
7332}
7333
843e4330
KH		 7334static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7335 struct kvm_memory_slot *memslot,
7336 gfn_t offset, unsigned long mask)
7337{
7338 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7339}
7340
cd39e117
PB		 7341static void __pi_post_block(struct kvm_vcpu *vcpu)
7342{
7343 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7344 struct pi_desc old, new;
7345 unsigned int dest;
cd39e117
PB		 7346
7347 do {
7348 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7349 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7350 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7351
7352 dest = cpu_physical_id(vcpu->cpu);
7353
7354 if (x2apic_enabled())
7355 new.ndst = dest;
7356 else
7357 new.ndst = (dest << 8) & 0xFF00;
7358
cd39e117
PB		 7359 /* set 'NV' to 'notification vector' */
7360 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7361 } while (cmpxchg64(&pi_desc->control, old.control,
7362 new.control) != old.control);
cd39e117 7363
8b306e2f
PB		 7364 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7365 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7366 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7367 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7368 vcpu->pre_pcpu = -1;
7369 }
7370}
7371
bf9f6ac8
FW		 7372/*
7373 * This routine does the following things for vCPU which is going
7374 * to be blocked if VT-d PI is enabled.
7375 * - Store the vCPU to the wakeup list, so when interrupts happen
7376 * we can find the right vCPU to wake up.
7377 * - Change the Posted-interrupt descriptor as below:
7378 * 'NDST' <-- vcpu->pre_pcpu
7379 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7380 * - If 'ON' is set during this process, which means at least one
7381 * interrupt is posted for this vCPU, we cannot block it, in
7382 * this case, return 1, otherwise, return 0.
7383 *
7384 */
bc22512b 7385static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7386{
bf9f6ac8
FW		 7387 unsigned int dest;
7388 struct pi_desc old, new;
7389 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7390
7391 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7392 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7393 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7394 return 0;
7395
8b306e2f
PB		 7396 WARN_ON(irqs_disabled());
7397 local_irq_disable();
7398 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7399 vcpu->pre_pcpu = vcpu->cpu;
7400 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7401 list_add_tail(&vcpu->blocked_vcpu_list,
7402 &per_cpu(blocked_vcpu_on_cpu,
7403 vcpu->pre_pcpu));
7404 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7405 }
bf9f6ac8
FW		 7406
7407 do {
7408 old.control = new.control = pi_desc->control;
7409
bf9f6ac8
FW		 7410 WARN((pi_desc->sn == 1),
7411 "Warning: SN field of posted-interrupts "
7412 "is set before blocking\n");
7413
7414 /*
7415 * Since vCPU can be preempted during this process,
7416 * vcpu->cpu could be different with pre_pcpu, we
7417 * need to set pre_pcpu as the destination of wakeup
7418 * notification event, then we can find the right vCPU
7419 * to wakeup in wakeup handler if interrupts happen
7420 * when the vCPU is in blocked state.
7421 */
7422 dest = cpu_physical_id(vcpu->pre_pcpu);
7423
7424 if (x2apic_enabled())
7425 new.ndst = dest;
7426 else
7427 new.ndst = (dest << 8) & 0xFF00;
7428
7429 /* set 'NV' to 'wakeup vector' */
7430 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7431 } while (cmpxchg64(&pi_desc->control, old.control,
7432 new.control) != old.control);
bf9f6ac8 7433
8b306e2f
PB		 7434 /* We should not block the vCPU if an interrupt is posted for it. */
7435 if (pi_test_on(pi_desc) == 1)
7436 __pi_post_block(vcpu);
7437
7438 local_irq_enable();
7439 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7440}
7441
bc22512b
YJ		 7442static int vmx_pre_block(struct kvm_vcpu *vcpu)
7443{
7444 if (pi_pre_block(vcpu))
7445 return 1;
7446
64672c95
YJ		 7447 if (kvm_lapic_hv_timer_in_use(vcpu))
7448 kvm_lapic_switch_to_sw_timer(vcpu);
7449
bc22512b
YJ		 7450 return 0;
7451}
7452
7453static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7454{
8b306e2f 7455 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7456 return;
7457
8b306e2f
PB		 7458 WARN_ON(irqs_disabled());
7459 local_irq_disable();
cd39e117 7460 __pi_post_block(vcpu);
8b306e2f 7461 local_irq_enable();
bf9f6ac8
FW		 7462}
7463
bc22512b
YJ		 7464static void vmx_post_block(struct kvm_vcpu *vcpu)
7465{
64672c95
YJ		 7466 if (kvm_x86_ops->set_hv_timer)
7467 kvm_lapic_switch_to_hv_timer(vcpu);
7468
bc22512b
YJ		 7469 pi_post_block(vcpu);
7470}
7471
efc64404
FW		 7472/*
7473 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7474 *
7475 * @kvm: kvm
7476 * @host_irq: host irq of the interrupt
7477 * @guest_irq: gsi of the interrupt
7478 * @set: set or unset PI
7479 * returns 0 on success, < 0 on failure
7480 */
7481static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7482 uint32_t guest_irq, bool set)
7483{
7484 struct kvm_kernel_irq_routing_entry *e;
7485 struct kvm_irq_routing_table *irq_rt;
7486 struct kvm_lapic_irq irq;
7487 struct kvm_vcpu *vcpu;
7488 struct vcpu_data vcpu_info;
3a8b0677 7489 int idx, ret = 0;
efc64404
FW		 7490
7491 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7492 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7493 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7494 return 0;
7495
7496 idx = srcu_read_lock(&kvm->irq_srcu);
7497 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7498 if (guest_irq >= irq_rt->nr_rt_entries ||
7499 hlist_empty(&irq_rt->map[guest_irq])) {
7500 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7501 guest_irq, irq_rt->nr_rt_entries);
7502 goto out;
7503 }
efc64404
FW		 7504
7505 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7506 if (e->type != KVM_IRQ_ROUTING_MSI)
7507 continue;
7508 /*
7509 * VT-d PI cannot support posting multicast/broadcast
7510 * interrupts to a vCPU, we still use interrupt remapping
7511 * for these kind of interrupts.
7512 *
7513 * For lowest-priority interrupts, we only support
7514 * those with single CPU as the destination, e.g. user
7515 * configures the interrupts via /proc/irq or uses
7516 * irqbalance to make the interrupts single-CPU.
7517 *
7518 * We will support full lowest-priority interrupt later.
fdcf7562
AG		 7519 *
7520 * In addition, we can only inject generic interrupts using
7521 * the PI mechanism, refuse to route others through it.
efc64404
FW		 7522 */
7523
37131313 7524 kvm_set_msi_irq(kvm, e, &irq);
fdcf7562
AG		 7525 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7526 !kvm_irq_is_postable(&irq)) {
23a1c257
FW		 7527 /*
7528 * Make sure the IRTE is in remapped mode if
7529 * we don't handle it in posted mode.
7530 */
7531 ret = irq_set_vcpu_affinity(host_irq, NULL);
7532 if (ret < 0) {
7533 printk(KERN_INFO
7534 "failed to back to remapped mode, irq: %u\n",
7535 host_irq);
7536 goto out;
7537 }
7538
efc64404 7539 continue;
23a1c257 7540 }
efc64404
FW		 7541
7542 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7543 vcpu_info.vector = irq.vector;
7544
2698d82e 7545 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7546 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7547
7548 if (set)
7549 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7550 else
efc64404 7551 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7552
7553 if (ret < 0) {
7554 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7555 __func__);
7556 goto out;
7557 }
7558 }
7559
7560 ret = 0;
7561out:
7562 srcu_read_unlock(&kvm->irq_srcu, idx);
7563 return ret;
7564}
7565
c45dcc71
AR		 7566static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7567{
7568 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7569 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
32ad73db 7570 FEAT_CTL_LMCE_ENABLED;
c45dcc71
AR		 7571 else
7572 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
32ad73db 7573 ~FEAT_CTL_LMCE_ENABLED;
c45dcc71
AR		 7574}
7575
72d7b374
LP		 7576static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7577{
72e9cbdb
LP		 7578 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7579 if (to_vmx(vcpu)->nested.nested_run_pending)
7580 return 0;
72d7b374
LP		 7581 return 1;
7582}
7583
0234bf88
LP		 7584static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7585{
72e9cbdb
LP		 7586 struct vcpu_vmx *vmx = to_vmx(vcpu);
7587
7588 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7589 if (vmx->nested.smm.guest_mode)
7590 nested_vmx_vmexit(vcpu, -1, 0, 0);
7591
7592 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7593 vmx->nested.vmxon = false;
caa057a2 7594 vmx_clear_hlt(vcpu);
0234bf88
LP		 7595 return 0;
7596}
7597
ed19321f 7598static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7599{
72e9cbdb
LP		 7600 struct vcpu_vmx *vmx = to_vmx(vcpu);
7601 int ret;
7602
7603 if (vmx->nested.smm.vmxon) {
7604 vmx->nested.vmxon = true;
7605 vmx->nested.smm.vmxon = false;
7606 }
7607
7608 if (vmx->nested.smm.guest_mode) {
a633e41e 7609 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7610 if (ret)
7611 return ret;
7612
7613 vmx->nested.smm.guest_mode = false;
7614 }
0234bf88
LP		 7615 return 0;
7616}
7617
cc3d967f
LP		 7618static int enable_smi_window(struct kvm_vcpu *vcpu)
7619{
7620 return 0;
7621}
7622
05d5a486
SB		 7623static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7624{
9481b7f1 7625 return false;
05d5a486
SB		 7626}
7627
4b9852f4
LA		 7628static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7629{
7630 return to_vmx(vcpu)->nested.vmxon;
7631}
7632
a3203381
SC		 7633static __init int hardware_setup(void)
7634{
7635 unsigned long host_bndcfgs;
2342080c 7636 struct desc_ptr dt;
a3203381
SC		 7637 int r, i;
7638
7639 rdmsrl_safe(MSR_EFER, &host_efer);
7640
2342080c
SC		 7641 store_idt(&dt);
7642 host_idt_base = dt.address;
7643
a3203381
SC		 7644 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7645 kvm_define_shared_msr(i, vmx_msr_index[i]);
7646
7647 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7648 return -EIO;
7649
7650 if (boot_cpu_has(X86_FEATURE_NX))
7651 kvm_enable_efer_bits(EFER_NX);
7652
7653 if (boot_cpu_has(X86_FEATURE_MPX)) {
7654 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7655 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7656 }
7657
a3203381
SC		 7658 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7659 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7660 enable_vpid = 0;
7661
7662 if (!cpu_has_vmx_ept() ||
7663 !cpu_has_vmx_ept_4levels() ||
7664 !cpu_has_vmx_ept_mt_wb() ||
7665 !cpu_has_vmx_invept_global())
7666 enable_ept = 0;
7667
7668 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7669 enable_ept_ad_bits = 0;
7670
7671 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7672 enable_unrestricted_guest = 0;
7673
7674 if (!cpu_has_vmx_flexpriority())
7675 flexpriority_enabled = 0;
7676
7677 if (!cpu_has_virtual_nmis())
7678 enable_vnmi = 0;
7679
7680 /*
7681 * set_apic_access_page_addr() is used to reload apic access
7682 * page upon invalidation. No need to do anything if not
7683 * using the APIC_ACCESS_ADDR VMCS field.
7684 */
7685 if (!flexpriority_enabled)
7686 kvm_x86_ops->set_apic_access_page_addr = NULL;
7687
7688 if (!cpu_has_vmx_tpr_shadow())
7689 kvm_x86_ops->update_cr8_intercept = NULL;
7690
7691 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7692 kvm_disable_largepages();
7693
7694#if IS_ENABLED(CONFIG_HYPERV)
7695 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7696 && enable_ept) {
7697 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7698 kvm_x86_ops->tlb_remote_flush_with_range =
7699 hv_remote_flush_tlb_with_range;
7700 }
a3203381
SC		 7701#endif
7702
7703 if (!cpu_has_vmx_ple()) {
7704 ple_gap = 0;
7705 ple_window = 0;
7706 ple_window_grow = 0;
7707 ple_window_max = 0;
7708 ple_window_shrink = 0;
7709 }
7710
7711 if (!cpu_has_vmx_apicv()) {
7712 enable_apicv = 0;
7713 kvm_x86_ops->sync_pir_to_irr = NULL;
7714 }
7715
7716 if (cpu_has_vmx_tsc_scaling()) {
7717 kvm_has_tsc_control = true;
7718 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7719 kvm_tsc_scaling_ratio_frac_bits = 48;
7720 }
7721
7722 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7723
7724 if (enable_ept)
7725 vmx_enable_tdp();
7726 else
7727 kvm_disable_tdp();
7728
a3203381
SC		 7729 /*
7730 * Only enable PML when hardware supports PML feature, and both EPT
7731 * and EPT A/D bit features are enabled -- PML depends on them to work.
7732 */
7733 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7734 enable_pml = 0;
7735
7736 if (!enable_pml) {
7737 kvm_x86_ops->slot_enable_log_dirty = NULL;
7738 kvm_x86_ops->slot_disable_log_dirty = NULL;
7739 kvm_x86_ops->flush_log_dirty = NULL;
7740 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7741 }
7742
7743 if (!cpu_has_vmx_preemption_timer())
804939ea 7744 enable_preemption_timer = false;
a3203381 7745
804939ea
SC		 7746 if (enable_preemption_timer) {
7747 u64 use_timer_freq = 5000ULL * 1000 * 1000;
a3203381
SC		 7748 u64 vmx_msr;
7749
7750 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7751 cpu_preemption_timer_multi =
7752 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
804939ea
SC		 7753
7754 if (tsc_khz)
7755 use_timer_freq = (u64)tsc_khz * 1000;
7756 use_timer_freq >>= cpu_preemption_timer_multi;
7757
7758 /*
7759 * KVM "disables" the preemption timer by setting it to its max
7760 * value. Don't use the timer if it might cause spurious exits
7761 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7762 */
7763 if (use_timer_freq > 0xffffffffu / 10)
7764 enable_preemption_timer = false;
7765 }
7766
7767 if (!enable_preemption_timer) {
a3203381
SC		 7768 kvm_x86_ops->set_hv_timer = NULL;
7769 kvm_x86_ops->cancel_hv_timer = NULL;
804939ea 7770 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
a3203381
SC		 7771 }
7772
a3203381 7773 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7774
7775 kvm_mce_cap_supported |= MCG_LMCE_P;
7776
f99e3daf
CP		 7777 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7778 return -EINVAL;
7779 if (!enable_ept || !cpu_has_vmx_intel_pt())
7780 pt_mode = PT_MODE_SYSTEM;
7781
a3203381 7782 if (nested) {
3e8eaccc 7783 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
a4443267 7784 vmx_capability.ept);
3e8eaccc 7785
e4027cfa 7786 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7787 if (r)
7788 return r;
7789 }
7790
7791 r = alloc_kvm_area();
7792 if (r)
7793 nested_vmx_hardware_unsetup();
7794 return r;
7795}
7796
7797static __exit void hardware_unsetup(void)
7798{
7799 if (nested)
7800 nested_vmx_hardware_unsetup();
7801
7802 free_kvm_area();
7803}
7804
ef8efd7a
SS		 7805static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7806{
f4fdc0a2
SS		 7807 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7808 BIT(APICV_INHIBIT_REASON_HYPERV);
ef8efd7a
SS		 7809
7810 return supported & BIT(bit);
7811}
7812
404f6aac 7813static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7814 .cpu_has_kvm_support = cpu_has_kvm_support,
7815 .disabled_by_bios = vmx_disabled_by_bios,
7816 .hardware_setup = hardware_setup,
7817 .hardware_unsetup = hardware_unsetup,
002c7f7c 7818 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7819 .hardware_enable = hardware_enable,
7820 .hardware_disable = hardware_disable,
04547156 7821 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7822 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7823
562b6b08 7824 .vm_size = sizeof(struct kvm_vmx),
b31c114b
WL		 7825 .vm_init = vmx_vm_init,
7826
6aa8b732
AK		 7827 .vcpu_create = vmx_create_vcpu,
7828 .vcpu_free = vmx_free_vcpu,
04d2cc77 7829 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7830
6d6095bd 7831 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7832 .vcpu_load = vmx_vcpu_load,
7833 .vcpu_put = vmx_vcpu_put,
7834
a96036b8 7835 .update_bp_intercept = update_exception_bitmap,
801e459a 7836 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7837 .get_msr = vmx_get_msr,
7838 .set_msr = vmx_set_msr,
7839 .get_segment_base = vmx_get_segment_base,
7840 .get_segment = vmx_get_segment,
7841 .set_segment = vmx_set_segment,
2e4d2653 7842 .get_cpl = vmx_get_cpl,
6aa8b732 7843 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7844 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 7845 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7846 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7847 .set_cr3 = vmx_set_cr3,
7848 .set_cr4 = vmx_set_cr4,
6aa8b732 7849 .set_efer = vmx_set_efer,
6aa8b732
AK		 7850 .get_idt = vmx_get_idt,
7851 .set_idt = vmx_set_idt,
7852 .get_gdt = vmx_get_gdt,
7853 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7854 .get_dr6 = vmx_get_dr6,
7855 .set_dr6 = vmx_set_dr6,
020df079 7856 .set_dr7 = vmx_set_dr7,
81908bf4 7857 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7858 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7859 .get_rflags = vmx_get_rflags,
7860 .set_rflags = vmx_set_rflags,
be94f6b7 7861
6aa8b732 7862 .tlb_flush = vmx_flush_tlb,
faff8758 7863 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7864
6aa8b732 7865 .run = vmx_vcpu_run,
6062d012 7866 .handle_exit = vmx_handle_exit,
5ef8acbd
OU		 7867 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7868 .update_emulated_instruction = vmx_update_emulated_instruction,
2809f5d2
GC		 7869 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7870 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7871 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7872 .set_irq = vmx_inject_irq,
95ba8273 7873 .set_nmi = vmx_inject_nmi,
298101da 7874 .queue_exception = vmx_queue_exception,
b463a6f7 7875 .cancel_injection = vmx_cancel_injection,
78646121 7876 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7877 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7878 .get_nmi_mask = vmx_get_nmi_mask,
7879 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7880 .enable_nmi_window = enable_nmi_window,
7881 .enable_irq_window = enable_irq_window,
7882 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7883 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7884 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb 7885 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7886 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7887 .apicv_post_state_restore = vmx_apicv_post_state_restore,
ef8efd7a 7888 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
c7c9c56c
YZ		 7889 .hwapic_irr_update = vmx_hwapic_irr_update,
7890 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7891 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7892 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7893 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
17e433b5 7894 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
95ba8273 7895
cbc94022 7896 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7897 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7898 .get_tdp_level = get_ept_level,
4b12f0de 7899 .get_mt_mask = vmx_get_mt_mask,
229456fc 7900
586f9607 7901 .get_exit_info = vmx_get_exit_info,
586f9607 7902
17cc3935 7903 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7904
7905 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7906
7907 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7908 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7909
7910 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7911
7912 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7913
e79f245d 7914 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7915 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7916
7917 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7918
7919 .check_intercept = vmx_check_intercept,
95b5a48c 7920 .handle_exit_irqoff = vmx_handle_exit_irqoff,
da8999d3 7921 .mpx_supported = vmx_mpx_supported,
55412b2e 7922 .xsaves_supported = vmx_xsaves_supported,
66336cab 7923 .umip_emulated = vmx_umip_emulated,
86f5201d 7924 .pt_supported = vmx_pt_supported,
a47970ed 7925 .pku_supported = vmx_pku_supported,
b6b8a145 7926
d264ee0c 7927 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7928
7929 .sched_in = vmx_sched_in,
843e4330
KH		 7930
7931 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7932 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7933 .flush_log_dirty = vmx_flush_log_dirty,
7934 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7935 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7936
bf9f6ac8
FW		 7937 .pre_block = vmx_pre_block,
7938 .post_block = vmx_post_block,
7939
25462f7f 7940 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7941
7942 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7943
7944#ifdef CONFIG_X86_64
7945 .set_hv_timer = vmx_set_hv_timer,
7946 .cancel_hv_timer = vmx_cancel_hv_timer,
7947#endif
c45dcc71
AR		 7948
7949 .setup_mce = vmx_setup_mce,
0234bf88 7950
72d7b374 7951 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7952 .pre_enter_smm = vmx_pre_enter_smm,
7953 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7954 .enable_smi_window = enable_smi_window,
57b119da 7955
e4027cfa
SC		 7956 .check_nested_events = NULL,
7957 .get_nested_state = NULL,
7958 .set_nested_state = NULL,
7959 .get_vmcs12_pages = NULL,
7960 .nested_enable_evmcs = NULL,
ea152987 7961 .nested_get_evmcs_version = NULL,
05d5a486 7962 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
4b9852f4 7963 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
6aa8b732
AK		 7964};
7965
72c6d2db 7966static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7967{
7968 if (vmx_l1d_flush_pages) {
7969 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7970 vmx_l1d_flush_pages = NULL;
7971 }
72c6d2db
TG		 7972 /* Restore state so sysfs ignores VMX */
7973 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7974}
7975
a7b9020b
TG		 7976static void vmx_exit(void)
7977{
7978#ifdef CONFIG_KEXEC_CORE
7979 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7980 synchronize_rcu();
7981#endif
7982
7983 kvm_exit();
7984
7985#if IS_ENABLED(CONFIG_HYPERV)
7986 if (static_branch_unlikely(&enable_evmcs)) {
7987 int cpu;
7988 struct hv_vp_assist_page *vp_ap;
7989 /*
7990 * Reset everything to support using non-enlightened VMCS
7991 * access later (e.g. when we reload the module with
7992 * enlightened_vmcs=0)
7993 */
7994 for_each_online_cpu(cpu) {
7995 vp_ap = hv_get_vp_assist_page(cpu);
7996
7997 if (!vp_ap)
7998 continue;
7999
6f6a657c 8000 vp_ap->nested_control.features.directhypercall = 0;
a7b9020b
TG		 8001 vp_ap->current_nested_vmcs = 0;
8002 vp_ap->enlighten_vmentry = 0;
8003 }
8004
8005 static_branch_disable(&enable_evmcs);
8006 }
8007#endif
8008 vmx_cleanup_l1d_flush();
8009}
8010module_exit(vmx_exit);
8011
6aa8b732
AK		 8012static int __init vmx_init(void)
8013{
773e8a04
VK		 8014 int r;
8015
8016#if IS_ENABLED(CONFIG_HYPERV)
8017 /*
8018 * Enlightened VMCS usage should be recommended and the host needs
8019 * to support eVMCS v1 or above. We can also disable eVMCS support
8020 * with module parameter.
8021 */
8022 if (enlightened_vmcs &&
8023 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8024 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8025 KVM_EVMCS_VERSION) {
8026 int cpu;
8027
8028 /* Check that we have assist pages on all online CPUs */
8029 for_each_online_cpu(cpu) {
8030 if (!hv_get_vp_assist_page(cpu)) {
8031 enlightened_vmcs = false;
8032 break;
8033 }
8034 }
8035
8036 if (enlightened_vmcs) {
8037 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8038 static_branch_enable(&enable_evmcs);
8039 }
6f6a657c
VK		 8040
8041 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8042 vmx_x86_ops.enable_direct_tlbflush
8043 = hv_enable_direct_tlbflush;
8044
773e8a04
VK		 8045 } else {
8046 enlightened_vmcs = false;
8047 }
8048#endif
8049
8050 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 8051 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8052 if (r)
34a1cd60 8053 return r;
25c5f225 8054
a7b9020b 8055 /*
7db92e16
TG		 8056 * Must be called after kvm_init() so enable_ept is properly set
8057 * up. Hand the parameter mitigation value in which was stored in
8058 * the pre module init parser. If no parameter was given, it will
8059 * contain 'auto' which will be turned into the default 'cond'
8060 * mitigation mode.
8061 */
19a36d32
WL		 8062 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8063 if (r) {
8064 vmx_exit();
8065 return r;
a47dd5f0 8066 }
25c5f225 8067
2965faa5 8068#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 8069 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8070 crash_vmclear_local_loaded_vmcss);
8071#endif
21ebf53b 8072 vmx_check_vmcs12_offsets();
8f536b76 8073
fdef3ad1 8074 return 0;
6aa8b732 8075}
a7b9020b 8076module_init(vmx_init);
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