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KVM: hyperv: Fix some typos in vcpu unimpl info
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / vmx / vmx.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732
AK		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * Copyright (C) 2006 Qumranet, Inc.
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
6aa8b732
AK		 14 */
15
199b118a
SC		 16#include <linux/frame.h>
17#include <linux/highmem.h>
18#include <linux/hrtimer.h>
19#include <linux/kernel.h>
edf88417 20#include <linux/kvm_host.h>
6aa8b732 21#include <linux/module.h>
c7addb90 22#include <linux/moduleparam.h>
e9bda3b3 23#include <linux/mod_devicetable.h>
199b118a 24#include <linux/mm.h>
199b118a 25#include <linux/sched.h>
b284909a 26#include <linux/sched/smt.h>
5a0e3ad6 27#include <linux/slab.h>
cafd6659 28#include <linux/tboot.h>
199b118a 29#include <linux/trace_events.h>
e495606d 30
199b118a 31#include <asm/apic.h>
fd8ca6da 32#include <asm/asm.h>
28b835d6 33#include <asm/cpu.h>
199b118a 34#include <asm/debugreg.h>
3b3be0d1 35#include <asm/desc.h>
952f07ec 36#include <asm/fpu/internal.h>
199b118a 37#include <asm/io.h>
efc64404 38#include <asm/irq_remapping.h>
199b118a
SC		 39#include <asm/kexec.h>
40#include <asm/perf_event.h>
41#include <asm/mce.h>
d6e41f11 42#include <asm/mmu_context.h>
773e8a04 43#include <asm/mshyperv.h>
199b118a
SC		 44#include <asm/spec-ctrl.h>
45#include <asm/virtext.h>
46#include <asm/vmx.h>
6aa8b732 47
3077c191 48#include "capabilities.h"
199b118a 49#include "cpuid.h"
4cebd747 50#include "evmcs.h"
199b118a
SC		 51#include "irq.h"
52#include "kvm_cache_regs.h"
53#include "lapic.h"
54#include "mmu.h"
55d2375e 55#include "nested.h"
89b0c9f5 56#include "ops.h"
25462f7f 57#include "pmu.h"
199b118a 58#include "trace.h"
cb1d474b 59#include "vmcs.h"
609363cf 60#include "vmcs12.h"
89b0c9f5 61#include "vmx.h"
199b118a 62#include "x86.h"
229456fc 63
6aa8b732
AK		 64MODULE_AUTHOR("Qumranet");
65MODULE_LICENSE("GPL");
66
e9bda3b3
JT		 67static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
69 {}
70};
71MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
72
2c4fd91d 73bool __read_mostly enable_vpid = 1;
736caefe 74module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 75
d02fcf50
PB		 76static bool __read_mostly enable_vnmi = 1;
77module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
78
2c4fd91d 79bool __read_mostly flexpriority_enabled = 1;
736caefe 80module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 81
2c4fd91d 82bool __read_mostly enable_ept = 1;
736caefe 83module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 84
2c4fd91d 85bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 86module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
88
2c4fd91d 89bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 90module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
91
a27685c3 92static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 93module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 94
476bc001 95static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 96module_param(fasteoi, bool, S_IRUGO);
97
5a71785d 98static bool __read_mostly enable_apicv = 1;
01e439be 99module_param(enable_apicv, bool, S_IRUGO);
83d4c286 100
801d3424
NHE		 101/*
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
105 */
1e58e5e5 106static bool __read_mostly nested = 1;
801d3424
NHE		 107module_param(nested, bool, S_IRUGO);
108
2c4fd91d 109bool __read_mostly enable_pml = 1;
843e4330
KH		 110module_param_named(pml, enable_pml, bool, S_IRUGO);
111
6f2f8453
PB		 112static bool __read_mostly dump_invalid_vmcs = 0;
113module_param(dump_invalid_vmcs, bool, 0644);
114
904e14fb
PB		 115#define MSR_BITMAP_MODE_X2APIC 1
116#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 117
64903d61
HZ		 118#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
119
64672c95
YJ		 120/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
121static int __read_mostly cpu_preemption_timer_multi;
122static bool __read_mostly enable_preemption_timer = 1;
123#ifdef CONFIG_X86_64
124module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
125#endif
126
3de6347b 127#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 128#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
129#define KVM_VM_CR0_ALWAYS_ON \
130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 132#define KVM_CR4_GUEST_OWNED_BITS \
133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 135
5dc1f044 136#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 137#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
138#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
139
78ac8b47
AK		 140#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
141
bf8c55d8
CP		 142#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
145 RTIT_STATUS_BYTECNT))
146
147#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
149
4b8d54f9
ZE		 150/*
151 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
152 * ple_gap: upper bound on the amount of time between two successive
153 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 154 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 155 * ple_window: upper bound on the amount of time a guest is allowed to execute
156 * in a PAUSE loop. Tests indicate that most spinlocks are held for
157 * less than 2^12 cycles
158 * Time is measured based on a counter that runs at the same rate as the TSC,
159 * refer SDM volume 3b section 21.6.13 & 22.1.3.
160 */
c8e88717 161static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 162module_param(ple_gap, uint, 0444);
b4a2d31d 163
7fbc85a5
BM		 164static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
165module_param(ple_window, uint, 0444);
4b8d54f9 166
b4a2d31d 167/* Default doubles per-vcpu window every exit. */
c8e88717 168static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 169module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 170
171/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 172static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 173module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 174
175/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 176static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177module_param(ple_window_max, uint, 0444);
b4a2d31d 178
f99e3daf
CP		 179/* Default is SYSTEM mode, 1 for host-guest mode */
180int __read_mostly pt_mode = PT_MODE_SYSTEM;
181module_param(pt_mode, int, S_IRUGO);
182
a399477e 183static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 184static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 185static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 186
7db92e16
TG		 187/* Storage for pre module init parameter parsing */
188static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 189
190static const struct {
191 const char *option;
0027ff2a 192 bool for_parse;
a399477e 193} vmentry_l1d_param[] = {
0027ff2a
PB		 194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
196 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 200};
201
7db92e16
TG		 202#define L1D_CACHE_ORDER 4
203static void *vmx_l1d_flush_pages;
204
205static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 206{
7db92e16 207 struct page *page;
288d152c 208 unsigned int i;
a399477e 209
19a36d32
WL		 210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
212 return 0;
213 }
214
7db92e16
TG		 215 if (!enable_ept) {
216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
217 return 0;
a399477e
KRW		 218 }
219
d806afa4
YW		 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
221 u64 msr;
222
223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
226 return 0;
227 }
228 }
8e0b2b91 229
d90a7a0e
JK		 230 /* If set to auto use the default l1tf mitigation method */
231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
232 switch (l1tf_mitigation) {
233 case L1TF_MITIGATION_OFF:
234 l1tf = VMENTER_L1D_FLUSH_NEVER;
235 break;
236 case L1TF_MITIGATION_FLUSH_NOWARN:
237 case L1TF_MITIGATION_FLUSH:
238 case L1TF_MITIGATION_FLUSH_NOSMT:
239 l1tf = VMENTER_L1D_FLUSH_COND;
240 break;
241 case L1TF_MITIGATION_FULL:
242 case L1TF_MITIGATION_FULL_FORCE:
243 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
244 break;
245 }
246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 }
249
7db92e16
TG		 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 252 /*
253 * This allocation for vmx_l1d_flush_pages is not tied to a VM
254 * lifetime and so should not be charged to a memcg.
255 */
7db92e16
TG		 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
257 if (!page)
258 return -ENOMEM;
259 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 260
261 /*
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
265 */
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
268 PAGE_SIZE);
269 }
7db92e16
TG		 270 }
271
272 l1tf_vmx_mitigation = l1tf;
273
895ae47f
TG		 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
276 else
277 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 278
427362a1
NS		 279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 281 else
427362a1 282 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 283 return 0;
284}
285
286static int vmentry_l1d_flush_parse(const char *s)
287{
288 unsigned int i;
289
290 if (s) {
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
294 return i;
7db92e16
TG		 295 }
296 }
a399477e
KRW		 297 return -EINVAL;
298}
299
7db92e16
TG		 300static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301{
dd4bfa73 302 int l1tf, ret;
7db92e16 303
7db92e16
TG		 304 l1tf = vmentry_l1d_flush_parse(s);
305 if (l1tf < 0)
306 return l1tf;
307
0027ff2a
PB		 308 if (!boot_cpu_has(X86_BUG_L1TF))
309 return 0;
310
7db92e16
TG		 311 /*
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
315 * established.
316 */
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
319 return 0;
320 }
321
dd4bfa73
TG		 322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
325 return ret;
7db92e16
TG		 326}
327
a399477e
KRW		 328static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
329{
0027ff2a
PB		 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
332
7db92e16 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 334}
335
336static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
339};
895ae47f 340module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 341
d99e4152
GN		 342static bool guest_state_valid(struct kvm_vcpu *vcpu);
343static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 344static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 345 u32 msr, int type);
75880a01 346
453eafbe
SC		 347void vmx_vmexit(void);
348
52a9fcbc
SC		 349#define vmx_insn_failed(fmt...) \
350do { \
351 WARN_ONCE(1, fmt); \
352 pr_warn_ratelimited(fmt); \
353} while (0)
354
6e202097
SC		 355asmlinkage void vmread_error(unsigned long field, bool fault)
356{
357 if (fault)
358 kvm_spurious_fault();
359 else
360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
361}
362
52a9fcbc
SC		 363noinline void vmwrite_error(unsigned long field, unsigned long value)
364{
365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
367}
368
369noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
370{
371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
372}
373
374noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
375{
376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
377}
378
379noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
380{
381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
382 ext, vpid, gva);
383}
384
385noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
386{
387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
388 ext, eptp, gpa);
389}
390
6aa8b732 391static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 392DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 393/*
394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
396 */
397static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 398
bf9f6ac8
FW		 399/*
400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
401 * can find which vCPU should be waken up.
402 */
403static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
404static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
405
2384d2b3
SY		 406static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
407static DEFINE_SPINLOCK(vmx_vpid_lock);
408
3077c191
SC		 409struct vmcs_config vmcs_config;
410struct vmx_capability vmx_capability;
d56f546d 411
6aa8b732
AK		 412#define VMX_SEGMENT_FIELD(seg) \
413 [VCPU_SREG_##seg] = { \
414 .selector = GUEST_##seg##_SELECTOR, \
415 .base = GUEST_##seg##_BASE, \
416 .limit = GUEST_##seg##_LIMIT, \
417 .ar_bytes = GUEST_##seg##_AR_BYTES, \
418 }
419
772e0318 420static const struct kvm_vmx_segment_field {
6aa8b732
AK		 421 unsigned selector;
422 unsigned base;
423 unsigned limit;
424 unsigned ar_bytes;
425} kvm_vmx_segment_fields[] = {
426 VMX_SEGMENT_FIELD(CS),
427 VMX_SEGMENT_FIELD(DS),
428 VMX_SEGMENT_FIELD(ES),
429 VMX_SEGMENT_FIELD(FS),
430 VMX_SEGMENT_FIELD(GS),
431 VMX_SEGMENT_FIELD(SS),
432 VMX_SEGMENT_FIELD(TR),
433 VMX_SEGMENT_FIELD(LDTR),
434};
435
cf3646eb 436u64 host_efer;
2342080c 437static unsigned long host_idt_base;
26bb0981 438
4d56c8a7 439/*
898a811f
JM		 440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
441 * will emulate SYSCALL in legacy mode if the vendor string in guest
442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
443 * support this emulation, IA32_STAR must always be included in
444 * vmx_msr_index[], even in i386 builds.
4d56c8a7 445 */
cf3646eb 446const u32 vmx_msr_index[] = {
05b3e0c2 447#ifdef CONFIG_X86_64
44ea2b17 448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 449#endif
8c06585d 450 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
c11f83e0 451 MSR_IA32_TSX_CTRL,
6aa8b732 452};
6aa8b732 453
773e8a04
VK		 454#if IS_ENABLED(CONFIG_HYPERV)
455static bool __read_mostly enlightened_vmcs = true;
456module_param(enlightened_vmcs, bool, 0444);
457
877ad952
TL		 458/* check_ept_pointer() should be under protection of ept_pointer_lock. */
459static void check_ept_pointer_match(struct kvm *kvm)
460{
461 struct kvm_vcpu *vcpu;
462 u64 tmp_eptp = INVALID_PAGE;
463 int i;
464
465 kvm_for_each_vcpu(i, vcpu, kvm) {
466 if (!VALID_PAGE(tmp_eptp)) {
467 tmp_eptp = to_vmx(vcpu)->ept_pointer;
468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
469 to_kvm_vmx(kvm)->ept_pointers_match
470 = EPT_POINTERS_MISMATCH;
471 return;
472 }
473 }
474
475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
476}
477
8997f657 478static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 479 void *data)
480{
481 struct kvm_tlb_range *range = data;
482
483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
484 range->pages);
485}
486
487static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
489{
490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
491
492 /*
493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
494 * of the base of EPT PML4 table, strip off EPT configuration
495 * information.
496 */
497 if (range)
498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
499 kvm_fill_hv_flush_list_func, (void *)range);
500 else
501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
502}
503
504static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
505 struct kvm_tlb_range *range)
877ad952 506{
a5c214da 507 struct kvm_vcpu *vcpu;
b7c1c226 508 int ret = 0, i;
877ad952
TL		 509
510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
511
512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
513 check_ept_pointer_match(kvm);
514
515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 516 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 517 /* If ept_pointer is invalid pointer, bypass flush request. */
518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
519 ret |= __hv_remote_flush_tlb_with_range(
520 kvm, vcpu, range);
53963a70 521 }
a5c214da 522 } else {
1f3a3e46
LT		 523 ret = __hv_remote_flush_tlb_with_range(kvm,
524 kvm_get_vcpu(kvm, 0), range);
877ad952 525 }
877ad952 526
877ad952
TL		 527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
528 return ret;
529}
1f3a3e46
LT		 530static int hv_remote_flush_tlb(struct kvm *kvm)
531{
532 return hv_remote_flush_tlb_with_range(kvm, NULL);
533}
534
6f6a657c
VK		 535static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
536{
537 struct hv_enlightened_vmcs *evmcs;
538 struct hv_partition_assist_pg **p_hv_pa_pg =
539 &vcpu->kvm->arch.hyperv.hv_pa_pg;
540 /*
541 * Synthetic VM-Exit is not enabled in current code and so All
542 * evmcs in singe VM shares same assist page.
543 */
cab01850 544 if (!*p_hv_pa_pg)
6f6a657c 545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
cab01850
VK		 546
547 if (!*p_hv_pa_pg)
548 return -ENOMEM;
6f6a657c
VK		 549
550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
551
552 evmcs->partition_assist_page =
553 __pa(*p_hv_pa_pg);
cab01850 554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
6f6a657c
VK		 555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
556
6f6a657c
VK		 557 return 0;
558}
559
773e8a04
VK		 560#endif /* IS_ENABLED(CONFIG_HYPERV) */
561
64672c95
YJ		 562/*
563 * Comment's format: document - errata name - stepping - processor name.
564 * Refer from
565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
566 */
567static u32 vmx_preemption_cpu_tfms[] = {
568/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
5690x000206E6,
570/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
571/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
572/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5730x00020652,
574/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5750x00020655,
576/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
577/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
578/*
579 * 320767.pdf - AAP86 - B1 -
580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
581 */
5820x000106E5,
583/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5840x000106A0,
585/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5860x000106A1,
587/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5880x000106A4,
589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5920x000106A5,
3d82c565
WH		 593 /* Xeon E3-1220 V2 */
5940x000306A8,
64672c95
YJ		 595};
596
597static inline bool cpu_has_broken_vmx_preemption_timer(void)
598{
599 u32 eax = cpuid_eax(0x00000001), i;
600
601 /* Clear the reserved bits */
602 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 604 if (eax == vmx_preemption_cpu_tfms[i])
605 return true;
606
607 return false;
608}
609
35754c98 610static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 611{
35754c98 612 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 613}
614
04547156
SY		 615static inline bool report_flexpriority(void)
616{
617 return flexpriority_enabled;
618}
619
97b7ead3 620static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 621{
622 int i;
623
a2fa3e9f 624 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 626 return i;
627 return -1;
628}
629
97b7ead3 630struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 631{
632 int i;
633
8b9cf98c 634 i = __find_msr_index(vmx, msr);
a75beee6 635 if (i >= 0)
a2fa3e9f 636 return &vmx->guest_msrs[i];
8b6d44c7 637 return NULL;
7725f0ba
AK		 638}
639
b07a5c53
PB		 640static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
641{
642 int ret = 0;
643
644 u64 old_msr_data = msr->data;
645 msr->data = data;
646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
647 preempt_disable();
648 ret = kvm_set_shared_msr(msr->index, msr->data,
649 msr->mask);
650 preempt_enable();
651 if (ret)
652 msr->data = old_msr_data;
653 }
654 return ret;
655}
656
7c97fcb3
SC		 657void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
658{
659 vmcs_clear(loaded_vmcs->vmcs);
660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
661 vmcs_clear(loaded_vmcs->shadow_vmcs);
662 loaded_vmcs->cpu = -1;
663 loaded_vmcs->launched = 0;
664}
665
2965faa5 666#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 667/*
668 * This bitmap is used to indicate whether the vmclear
669 * operation is enabled on all cpus. All disabled by
670 * default.
671 */
672static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
673
674static inline void crash_enable_local_vmclear(int cpu)
675{
676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
677}
678
679static inline void crash_disable_local_vmclear(int cpu)
680{
681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
682}
683
684static inline int crash_local_vmclear_enabled(int cpu)
685{
686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
687}
688
689static void crash_vmclear_local_loaded_vmcss(void)
690{
691 int cpu = raw_smp_processor_id();
692 struct loaded_vmcs *v;
693
694 if (!crash_local_vmclear_enabled(cpu))
695 return;
696
697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
698 loaded_vmcss_on_cpu_link)
699 vmcs_clear(v->vmcs);
700}
701#else
702static inline void crash_enable_local_vmclear(int cpu) { }
703static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 704#endif /* CONFIG_KEXEC_CORE */
8f536b76 705
d462b819 706static void __loaded_vmcs_clear(void *arg)
6aa8b732 707{
d462b819 708 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 709 int cpu = raw_smp_processor_id();
6aa8b732 710
d462b819
NHE		 711 if (loaded_vmcs->cpu != cpu)
712 return; /* vcpu migration can race with cpu offline */
713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 714 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 715 crash_disable_local_vmclear(cpu);
d462b819 716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 717
718 /*
719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
720 * is before setting loaded_vmcs->vcpu to -1 which is done in
721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
722 * then adds the vmcs into percpu list before it is deleted.
723 */
724 smp_wmb();
725
d462b819 726 loaded_vmcs_init(loaded_vmcs);
8f536b76 727 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 728}
729
89b0c9f5 730void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 731{
e6c7d321
XG		 732 int cpu = loaded_vmcs->cpu;
733
734 if (cpu != -1)
735 smp_call_function_single(cpu,
736 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 737}
738
2fb92db1
AK		 739static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
740 unsigned field)
741{
742 bool ret;
743 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
744
cb3c1e2f
SC		 745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
2fb92db1
AK		 747 vmx->segment_cache.bitmask = 0;
748 }
749 ret = vmx->segment_cache.bitmask & mask;
750 vmx->segment_cache.bitmask |= mask;
751 return ret;
752}
753
754static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
755{
756 u16 *p = &vmx->segment_cache.seg[seg].selector;
757
758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
760 return *p;
761}
762
763static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
764{
765 ulong *p = &vmx->segment_cache.seg[seg].base;
766
767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
769 return *p;
770}
771
772static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
773{
774 u32 *p = &vmx->segment_cache.seg[seg].limit;
775
776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
778 return *p;
779}
780
781static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
782{
783 u32 *p = &vmx->segment_cache.seg[seg].ar;
784
785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
787 return *p;
788}
789
97b7ead3 790void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 791{
792 u32 eb;
793
fd7373cc 794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 795 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 796 /*
797 * Guest access to VMware backdoor ports could legitimately
798 * trigger #GP because of TSS I/O permission bitmap.
799 * We intercept those #GP and allow access to them anyway
800 * as VMware does.
801 */
802 if (enable_vmware_backdoor)
803 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 804 if ((vcpu->guest_debug &
805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
807 eb |= 1u << BP_VECTOR;
7ffd92c5 808 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 809 eb = ~0;
089d034e 810 if (enable_ept)
1439442c 811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 812
813 /* When we are running a nested L2 guest and L1 specified for it a
814 * certain exception bitmap, we must trap the same exceptions and pass
815 * them to L1. When running L2, we will only handle the exceptions
816 * specified above if L1 did not want them.
817 */
818 if (is_guest_mode(vcpu))
819 eb |= get_vmcs12(vcpu)->exception_bitmap;
820
abd3f2d6
AK		 821 vmcs_write32(EXCEPTION_BITMAP, eb);
822}
823
d28b387f
KA		 824/*
825 * Check if MSR is intercepted for currently loaded MSR bitmap.
826 */
827static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
828{
829 unsigned long *msr_bitmap;
830 int f = sizeof(unsigned long);
831
832 if (!cpu_has_vmx_msr_bitmap())
833 return true;
834
835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
836
837 if (msr <= 0x1fff) {
838 return !!test_bit(msr, msr_bitmap + 0x800 / f);
839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
840 msr &= 0x1fff;
841 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
842 }
843
844 return true;
845}
846
2961e876
GN		 847static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
848 unsigned long entry, unsigned long exit)
8bf00a52 849{
2961e876
GN		 850 vm_entry_controls_clearbit(vmx, entry);
851 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 852}
853
662f1d1d 854int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
ca83b4a7
KRW		 855{
856 unsigned int i;
857
858 for (i = 0; i < m->nr; ++i) {
859 if (m->val[i].index == msr)
860 return i;
861 }
862 return -ENOENT;
863}
864
61d2ef2c
AK		 865static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
866{
ca83b4a7 867 int i;
61d2ef2c
AK		 868 struct msr_autoload *m = &vmx->msr_autoload;
869
8bf00a52
GN		 870 switch (msr) {
871 case MSR_EFER:
c73da3fc 872 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 873 clear_atomic_switch_msr_special(vmx,
874 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 875 VM_EXIT_LOAD_IA32_EFER);
876 return;
877 }
878 break;
879 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 880 if (cpu_has_load_perf_global_ctrl()) {
2961e876 881 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
884 return;
885 }
886 break;
110312c8 887 }
ef0fbcac 888 i = vmx_find_msr_index(&m->guest, msr);
ca83b4a7 889 if (i < 0)
31907093 890 goto skip_guest;
33966dd6 891 --m->guest.nr;
33966dd6 892 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 894
31907093 895skip_guest:
ef0fbcac 896 i = vmx_find_msr_index(&m->host, msr);
31907093 897 if (i < 0)
61d2ef2c 898 return;
31907093
KRW		 899
900 --m->host.nr;
901 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 903}
904
2961e876
GN		 905static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
906 unsigned long entry, unsigned long exit,
907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
908 u64 guest_val, u64 host_val)
8bf00a52
GN		 909{
910 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 911 if (host_val_vmcs != HOST_IA32_EFER)
912 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 913 vm_entry_controls_setbit(vmx, entry);
914 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 915}
916
61d2ef2c 917static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 918 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 919{
989e3992 920 int i, j = 0;
61d2ef2c
AK		 921 struct msr_autoload *m = &vmx->msr_autoload;
922
8bf00a52
GN		 923 switch (msr) {
924 case MSR_EFER:
c73da3fc 925 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 926 add_atomic_switch_msr_special(vmx,
927 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 928 VM_EXIT_LOAD_IA32_EFER,
929 GUEST_IA32_EFER,
930 HOST_IA32_EFER,
931 guest_val, host_val);
932 return;
933 }
934 break;
935 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 936 if (cpu_has_load_perf_global_ctrl()) {
2961e876 937 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
940 GUEST_IA32_PERF_GLOBAL_CTRL,
941 HOST_IA32_PERF_GLOBAL_CTRL,
942 guest_val, host_val);
943 return;
944 }
945 break;
7099e2e1
RK		 946 case MSR_IA32_PEBS_ENABLE:
947 /* PEBS needs a quiescent period after being disabled (to write
948 * a record). Disabling PEBS through VMX MSR swapping doesn't
949 * provide that period, so a CPU could write host's record into
950 * guest's memory.
951 */
952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 953 }
954
ef0fbcac 955 i = vmx_find_msr_index(&m->guest, msr);
989e3992 956 if (!entry_only)
ef0fbcac 957 j = vmx_find_msr_index(&m->host, msr);
61d2ef2c 958
7cfe0526
AL		 959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
60266204 961 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 962 "Can't add msr %x\n", msr);
963 return;
61d2ef2c 964 }
31907093 965 if (i < 0) {
ca83b4a7 966 i = m->guest.nr++;
33966dd6 967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 968 }
989e3992
KRW		 969 m->guest.val[i].index = msr;
970 m->guest.val[i].value = guest_val;
971
972 if (entry_only)
973 return;
61d2ef2c 974
31907093
KRW		 975 if (j < 0) {
976 j = m->host.nr++;
33966dd6 977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 978 }
31907093
KRW		 979 m->host.val[j].index = msr;
980 m->host.val[j].value = host_val;
61d2ef2c
AK		 981}
982
92c0d900 983static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 984{
844a5fe2
PB		 985 u64 guest_efer = vmx->vcpu.arch.efer;
986 u64 ignore_bits = 0;
987
9167ab79
PB		 988 /* Shadow paging assumes NX to be available. */
989 if (!enable_ept)
990 guest_efer |= EFER_NX;
3a34a881 991
51c6cf66 992 /*
844a5fe2 993 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 994 */
844a5fe2 995 ignore_bits |= EFER_SCE;
51c6cf66
AK		 996#ifdef CONFIG_X86_64
997 ignore_bits |= EFER_LMA | EFER_LME;
998 /* SCE is meaningful only in long mode on Intel */
999 if (guest_efer & EFER_LMA)
1000 ignore_bits &= ~(u64)EFER_SCE;
1001#endif
84ad33ef 1002
f6577a5f
AL		 1003 /*
1004 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1005 * On CPUs that support "load IA32_EFER", always switch EFER
1006 * atomically, since it's faster than switching it manually.
1007 */
c73da3fc 1008 if (cpu_has_load_ia32_efer() ||
f6577a5f 1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1010 if (!(guest_efer & EFER_LMA))
1011 guest_efer &= ~EFER_LME;
54b98bff
AL		 1012 if (guest_efer != host_efer)
1013 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 1014 guest_efer, host_efer, false);
02343cf2
SC		 1015 else
1016 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 1017 return false;
844a5fe2 1018 } else {
02343cf2
SC		 1019 clear_atomic_switch_msr(vmx, MSR_EFER);
1020
844a5fe2
PB		 1021 guest_efer &= ~ignore_bits;
1022 guest_efer |= host_efer & ignore_bits;
1023
1024 vmx->guest_msrs[efer_offset].data = guest_efer;
1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 1026
844a5fe2
PB		 1027 return true;
1028 }
51c6cf66
AK		 1029}
1030
e28baead
AL		 1031#ifdef CONFIG_X86_32
1032/*
1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1034 * VMCS rather than the segment table. KVM uses this helper to figure
1035 * out the current bases to poke them into the VMCS before entry.
1036 */
2d49ec72
GN		 1037static unsigned long segment_base(u16 selector)
1038{
8c2e41f7 1039 struct desc_struct *table;
2d49ec72
GN		 1040 unsigned long v;
1041
8c2e41f7 1042 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1043 return 0;
1044
45fc8757 1045 table = get_current_gdt_ro();
2d49ec72 1046
8c2e41f7 1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 1048 u16 ldt_selector = kvm_read_ldt();
1049
8c2e41f7 1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1051 return 0;
1052
8c2e41f7 1053 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 1054 }
8c2e41f7 1055 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 1056 return v;
1057}
e28baead 1058#endif
2d49ec72 1059
2ef444f1
CP		 1060static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1061{
1062 u32 i;
1063
1064 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1065 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1066 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1067 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1068 for (i = 0; i < addr_range; i++) {
1069 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1070 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1071 }
1072}
1073
1074static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1075{
1076 u32 i;
1077
1078 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1079 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1080 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1081 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1082 for (i = 0; i < addr_range; i++) {
1083 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1084 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1085 }
1086}
1087
1088static void pt_guest_enter(struct vcpu_vmx *vmx)
1089{
1090 if (pt_mode == PT_MODE_SYSTEM)
1091 return;
1092
2ef444f1 1093 /*
b08c2896
CP		 1094 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1095 * Save host state before VM entry.
2ef444f1 1096 */
b08c2896 1097 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1098 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1099 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1100 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1101 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1102 }
1103}
1104
1105static void pt_guest_exit(struct vcpu_vmx *vmx)
1106{
1107 if (pt_mode == PT_MODE_SYSTEM)
1108 return;
1109
1110 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1111 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1112 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1113 }
1114
1115 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1116 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1117}
1118
13b964a2
SC		 1119void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1120 unsigned long fs_base, unsigned long gs_base)
1121{
1122 if (unlikely(fs_sel != host->fs_sel)) {
1123 if (!(fs_sel & 7))
1124 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1125 else
1126 vmcs_write16(HOST_FS_SELECTOR, 0);
1127 host->fs_sel = fs_sel;
1128 }
1129 if (unlikely(gs_sel != host->gs_sel)) {
1130 if (!(gs_sel & 7))
1131 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1132 else
1133 vmcs_write16(HOST_GS_SELECTOR, 0);
1134 host->gs_sel = gs_sel;
1135 }
1136 if (unlikely(fs_base != host->fs_base)) {
1137 vmcs_writel(HOST_FS_BASE, fs_base);
1138 host->fs_base = fs_base;
1139 }
1140 if (unlikely(gs_base != host->gs_base)) {
1141 vmcs_writel(HOST_GS_BASE, gs_base);
1142 host->gs_base = gs_base;
1143 }
1144}
1145
97b7ead3 1146void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1147{
04d2cc77 1148 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1149 struct vmcs_host_state *host_state;
51e8a8cc 1150#ifdef CONFIG_X86_64
35060ed6 1151 int cpu = raw_smp_processor_id();
51e8a8cc 1152#endif
e368b875
SC		 1153 unsigned long fs_base, gs_base;
1154 u16 fs_sel, gs_sel;
26bb0981 1155 int i;
04d2cc77 1156
d264ee0c
SC		 1157 vmx->req_immediate_exit = false;
1158
f48b4711
LA		 1159 /*
1160 * Note that guest MSRs to be saved/restored can also be changed
1161 * when guest state is loaded. This happens when guest transitions
1162 * to/from long-mode by setting MSR_EFER.LMA.
1163 */
b464f57e
PB		 1164 if (!vmx->guest_msrs_ready) {
1165 vmx->guest_msrs_ready = true;
f48b4711
LA		 1166 for (i = 0; i < vmx->save_nmsrs; ++i)
1167 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1168 vmx->guest_msrs[i].data,
1169 vmx->guest_msrs[i].mask);
1170
1171 }
b464f57e 1172 if (vmx->guest_state_loaded)
33ed6329
AK		 1173 return;
1174
b464f57e 1175 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1176
33ed6329
AK		 1177 /*
1178 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1179 * allow segment selectors with cpl > 0 or ti == 1.
1180 */
d7ee039e 1181 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1182
1183#ifdef CONFIG_X86_64
d7ee039e
SC		 1184 savesegment(ds, host_state->ds_sel);
1185 savesegment(es, host_state->es_sel);
e368b875
SC		 1186
1187 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1188 if (likely(is_64bit_mm(current->mm))) {
1189 save_fsgs_for_kvm();
e368b875
SC		 1190 fs_sel = current->thread.fsindex;
1191 gs_sel = current->thread.gsindex;
b062b794 1192 fs_base = current->thread.fsbase;
e368b875 1193 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1194 } else {
e368b875
SC		 1195 savesegment(fs, fs_sel);
1196 savesegment(gs, gs_sel);
b062b794 1197 fs_base = read_msr(MSR_FS_BASE);
e368b875 1198 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1199 }
b2da15ac 1200
4679b61f 1201 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1202#else
e368b875
SC		 1203 savesegment(fs, fs_sel);
1204 savesegment(gs, gs_sel);
1205 fs_base = segment_base(fs_sel);
1206 gs_base = segment_base(gs_sel);
707c0874 1207#endif
e368b875 1208
13b964a2 1209 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
b464f57e 1210 vmx->guest_state_loaded = true;
33ed6329
AK		 1211}
1212
6d6095bd 1213static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1214{
d7ee039e
SC		 1215 struct vmcs_host_state *host_state;
1216
b464f57e 1217 if (!vmx->guest_state_loaded)
33ed6329
AK		 1218 return;
1219
b464f57e 1220 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1221
e1beb1d3 1222 ++vmx->vcpu.stat.host_state_reload;
bd9966de 1223
c8770e7b 1224#ifdef CONFIG_X86_64
4679b61f 1225 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1226#endif
d7ee039e
SC		 1227 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1228 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1229#ifdef CONFIG_X86_64
d7ee039e 1230 load_gs_index(host_state->gs_sel);
9581d442 1231#else
d7ee039e 1232 loadsegment(gs, host_state->gs_sel);
33ed6329 1233#endif
33ed6329 1234 }
d7ee039e
SC		 1235 if (host_state->fs_sel & 7)
1236 loadsegment(fs, host_state->fs_sel);
b2da15ac 1237#ifdef CONFIG_X86_64
d7ee039e
SC		 1238 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1239 loadsegment(ds, host_state->ds_sel);
1240 loadsegment(es, host_state->es_sel);
b2da15ac 1241 }
b2da15ac 1242#endif
b7ffc44d 1243 invalidate_tss_limit();
44ea2b17 1244#ifdef CONFIG_X86_64
c8770e7b 1245 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1246#endif
45fc8757 1247 load_fixmap_gdt(raw_smp_processor_id());
b464f57e
PB		 1248 vmx->guest_state_loaded = false;
1249 vmx->guest_msrs_ready = false;
33ed6329
AK		 1250}
1251
678e315e
SC		 1252#ifdef CONFIG_X86_64
1253static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1254{
4679b61f 1255 preempt_disable();
b464f57e 1256 if (vmx->guest_state_loaded)
4679b61f
PB		 1257 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1258 preempt_enable();
678e315e 1259 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1260}
1261
678e315e
SC		 1262static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1263{
4679b61f 1264 preempt_disable();
b464f57e 1265 if (vmx->guest_state_loaded)
4679b61f
PB		 1266 wrmsrl(MSR_KERNEL_GS_BASE, data);
1267 preempt_enable();
678e315e
SC		 1268 vmx->msr_guest_kernel_gs_base = data;
1269}
1270#endif
1271
28b835d6
FW		 1272static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1273{
1274 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1275 struct pi_desc old, new;
1276 unsigned int dest;
1277
31afb2ea
PB		 1278 /*
1279 * In case of hot-plug or hot-unplug, we may have to undo
1280 * vmx_vcpu_pi_put even if there is no assigned device. And we
1281 * always keep PI.NDST up to date for simplicity: it makes the
1282 * code easier, and CPU migration is not a fast path.
1283 */
1284 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1285 return;
1286
132194ff
JM		 1287 /*
1288 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1289 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1290 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1291 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1292 * correctly.
1293 */
1294 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1295 pi_clear_sn(pi_desc);
1296 goto after_clear_sn;
1297 }
1298
31afb2ea 1299 /* The full case. */
28b835d6
FW		 1300 do {
1301 old.control = new.control = pi_desc->control;
1302
31afb2ea 1303 dest = cpu_physical_id(cpu);
28b835d6 1304
31afb2ea
PB		 1305 if (x2apic_enabled())
1306 new.ndst = dest;
1307 else
1308 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1309
28b835d6 1310 new.sn = 0;
c0a1666b
PB		 1311 } while (cmpxchg64(&pi_desc->control, old.control,
1312 new.control) != old.control);
c112b5f5 1313
132194ff
JM		 1314after_clear_sn:
1315
c112b5f5
LK		 1316 /*
1317 * Clear SN before reading the bitmap. The VT-d firmware
1318 * writes the bitmap and reads SN atomically (5.2.3 in the
1319 * spec), so it doesn't really have a memory barrier that
1320 * pairs with this, but we cannot do that and we need one.
1321 */
1322 smp_mb__after_atomic();
1323
29881b6e 1324 if (!pi_is_pir_empty(pi_desc))
c112b5f5 1325 pi_set_on(pi_desc);
28b835d6 1326}
1be0e61c 1327
8ef863e6 1328void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1329{
a2fa3e9f 1330 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1331 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1332
b80c76ec 1333 if (!already_loaded) {
fe0e80be 1334 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1335 local_irq_disable();
8f536b76 1336 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1337
1338 /*
1339 * Read loaded_vmcs->cpu should be before fetching
1340 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1341 * See the comments in __loaded_vmcs_clear().
1342 */
1343 smp_rmb();
1344
d462b819
NHE		 1345 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1346 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1347 crash_enable_local_vmclear(cpu);
92fe13be 1348 local_irq_enable();
b80c76ec
JM		 1349 }
1350
1351 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1352 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1353 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1354 indirect_branch_prediction_barrier();
b80c76ec
JM		 1355 }
1356
1357 if (!already_loaded) {
59c58ceb 1358 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1359 unsigned long sysenter_esp;
1360
1361 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1362
6aa8b732
AK		 1363 /*
1364 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1365 * processors. See 22.2.4.
6aa8b732 1366 */
e0c23063 1367 vmcs_writel(HOST_TR_BASE,
72f5e08d 1368 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1369 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732
AK		 1370
1371 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1372 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1373
d462b819 1374 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1375 }
28b835d6 1376
2680d6da
OH		 1377 /* Setup TSC multiplier */
1378 if (kvm_has_tsc_control &&
c95ba92a
PF		 1379 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1380 decache_tsc_multiplier(vmx);
8ef863e6
SC		 1381}
1382
1383/*
1384 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1385 * vcpu mutex is already taken.
1386 */
1387void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1388{
1389 struct vcpu_vmx *vmx = to_vmx(vcpu);
1390
1391 vmx_vcpu_load_vmcs(vcpu, cpu);
2680d6da 1392
28b835d6 1393 vmx_vcpu_pi_load(vcpu, cpu);
8ef863e6 1394
1be0e61c 1395 vmx->host_pkru = read_pkru();
74c55931 1396 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1397}
1398
1399static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1400{
1401 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1402
1403 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1404 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1405 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1406 return;
1407
1408 /* Set SN when the vCPU is preempted */
1409 if (vcpu->preempted)
1410 pi_set_sn(pi_desc);
6aa8b732
AK		 1411}
1412
13b964a2 1413static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1414{
28b835d6
FW		 1415 vmx_vcpu_pi_put(vcpu);
1416
6d6095bd 1417 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1418}
1419
f244deed
WL		 1420static bool emulation_required(struct kvm_vcpu *vcpu)
1421{
1422 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1423}
1424
edcafe3c
AK		 1425static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1426
97b7ead3 1427unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1428{
e7bddc52 1429 struct vcpu_vmx *vmx = to_vmx(vcpu);
78ac8b47 1430 unsigned long rflags, save_rflags;
345dcaa8 1431
cb3c1e2f
SC		 1432 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1433 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
6de12732 1434 rflags = vmcs_readl(GUEST_RFLAGS);
e7bddc52 1435 if (vmx->rmode.vm86_active) {
6de12732 1436 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
e7bddc52 1437 save_rflags = vmx->rmode.save_rflags;
6de12732
AK		 1438 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1439 }
e7bddc52 1440 vmx->rflags = rflags;
78ac8b47 1441 }
e7bddc52 1442 return vmx->rflags;
6aa8b732
AK		 1443}
1444
97b7ead3 1445void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1446{
e7bddc52 1447 struct vcpu_vmx *vmx = to_vmx(vcpu);
491c1ad1 1448 unsigned long old_rflags;
f244deed 1449
491c1ad1 1450 if (enable_unrestricted_guest) {
cb3c1e2f 1451 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
491c1ad1
SC		 1452 vmx->rflags = rflags;
1453 vmcs_writel(GUEST_RFLAGS, rflags);
1454 return;
1455 }
1456
1457 old_rflags = vmx_get_rflags(vcpu);
e7bddc52
SC		 1458 vmx->rflags = rflags;
1459 if (vmx->rmode.vm86_active) {
1460 vmx->rmode.save_rflags = rflags;
053de044 1461 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1462 }
6aa8b732 1463 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed 1464
e7bddc52
SC		 1465 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1466 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1467}
1468
97b7ead3 1469u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1470{
1471 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1472 int ret = 0;
1473
1474 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1475 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1476 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1477 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1478
37ccdcbe 1479 return ret;
2809f5d2
GC		 1480}
1481
97b7ead3 1482void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1483{
1484 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1485 u32 interruptibility = interruptibility_old;
1486
1487 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1488
48005f64 1489 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1490 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1491 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1492 interruptibility |= GUEST_INTR_STATE_STI;
1493
1494 if ((interruptibility != interruptibility_old))
1495 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1496}
1497
bf8c55d8
CP		 1498static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1499{
1500 struct vcpu_vmx *vmx = to_vmx(vcpu);
1501 unsigned long value;
1502
1503 /*
1504 * Any MSR write that attempts to change bits marked reserved will
1505 * case a #GP fault.
1506 */
1507 if (data & vmx->pt_desc.ctl_bitmask)
1508 return 1;
1509
1510 /*
1511 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1512 * result in a #GP unless the same write also clears TraceEn.
1513 */
1514 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1515 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1516 return 1;
1517
1518 /*
1519 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1520 * and FabricEn would cause #GP, if
1521 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1522 */
1523 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1524 !(data & RTIT_CTL_FABRIC_EN) &&
1525 !intel_pt_validate_cap(vmx->pt_desc.caps,
1526 PT_CAP_single_range_output))
1527 return 1;
1528
1529 /*
1530 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1531 * utilize encodings marked reserved will casue a #GP fault.
1532 */
1533 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1534 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1535 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1536 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1537 return 1;
1538 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1539 PT_CAP_cycle_thresholds);
1540 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1541 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1542 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1543 return 1;
1544 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1545 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1546 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1547 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1548 return 1;
1549
1550 /*
1551 * If ADDRx_CFG is reserved or the encodings is >2 will
1552 * cause a #GP fault.
1553 */
1554 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1555 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1556 return 1;
1557 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1558 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1559 return 1;
1560 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1561 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1562 return 1;
1563 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1564 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1565 return 1;
1566
1567 return 0;
1568}
1569
1957aa63 1570static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1571{
1572 unsigned long rip;
6aa8b732 1573
1957aa63
SC		 1574 /*
1575 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1576 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1577 * set when EPT misconfig occurs. In practice, real hardware updates
1578 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1579 * (namely Hyper-V) don't set it due to it being undefined behavior,
1580 * i.e. we end up advancing IP with some random value.
1581 */
1582 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1583 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1584 rip = kvm_rip_read(vcpu);
1585 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1586 kvm_rip_write(vcpu, rip);
1587 } else {
1588 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1589 return 0;
1590 }
6aa8b732 1591
2809f5d2
GC		 1592 /* skipping an emulated instruction also counts */
1593 vmx_set_interrupt_shadow(vcpu, 0);
f8ea7c60 1594
60fc3d02 1595 return 1;
f8ea7c60
VK		 1596}
1597
caa057a2
WL		 1598static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1599{
1600 /*
1601 * Ensure that we clear the HLT state in the VMCS. We don't need to
1602 * explicitly skip the instruction because if the HLT state is set,
1603 * then the instruction is already executing and RIP has already been
1604 * advanced.
1605 */
1606 if (kvm_hlt_in_guest(vcpu->kvm) &&
1607 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1608 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1609}
1610
cfcd20e5 1611static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1612{
77ab6db0 1613 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1614 unsigned nr = vcpu->arch.exception.nr;
1615 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1616 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1617 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1618
da998b46
JM		 1619 kvm_deliver_exception_payload(vcpu);
1620
8ab2d2e2 1621 if (has_error_code) {
77ab6db0 1622 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1623 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1624 }
77ab6db0 1625
7ffd92c5 1626 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1627 int inc_eip = 0;
1628 if (kvm_exception_is_soft(nr))
1629 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 1630 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
77ab6db0
JK		 1631 return;
1632 }
1633
add5ff7a
SC		 1634 WARN_ON_ONCE(vmx->emulation_required);
1635
66fd3f7f
GN		 1636 if (kvm_exception_is_soft(nr)) {
1637 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1638 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1639 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1640 } else
1641 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1642
1643 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1644
1645 vmx_clear_hlt(vcpu);
298101da
AK		 1646}
1647
4e47c7a6
SY		 1648static bool vmx_rdtscp_supported(void)
1649{
1650 return cpu_has_vmx_rdtscp();
1651}
1652
ad756a16
MJ		 1653static bool vmx_invpcid_supported(void)
1654{
eb4b248e 1655 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1656}
1657
a75beee6
ED		 1658/*
1659 * Swap MSR entry in host/guest MSR entry array.
1660 */
8b9cf98c 1661static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1662{
26bb0981 1663 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1664
1665 tmp = vmx->guest_msrs[to];
1666 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1667 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1668}
1669
e38aea3e
AK		 1670/*
1671 * Set up the vmcs to automatically save and restore system
1672 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1673 * mode, as fiddling with msrs is very expensive.
1674 */
8b9cf98c 1675static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1676{
26bb0981 1677 int save_nmsrs, index;
e38aea3e 1678
a75beee6
ED		 1679 save_nmsrs = 0;
1680#ifdef CONFIG_X86_64
84c8c5b8
JM		 1681 /*
1682 * The SYSCALL MSRs are only needed on long mode guests, and only
1683 * when EFER.SCE is set.
1684 */
1685 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1686 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1687 if (index >= 0)
8b9cf98c
RR		 1688 move_msr_up(vmx, index, save_nmsrs++);
1689 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1690 if (index >= 0)
8b9cf98c 1691 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1692 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1693 if (index >= 0)
8b9cf98c 1694 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1695 }
1696#endif
92c0d900
AK		 1697 index = __find_msr_index(vmx, MSR_EFER);
1698 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1699 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1700 index = __find_msr_index(vmx, MSR_TSC_AUX);
1701 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1702 move_msr_up(vmx, index, save_nmsrs++);
c11f83e0
PB		 1703 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1704 if (index >= 0)
1705 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1706
26bb0981 1707 vmx->save_nmsrs = save_nmsrs;
b464f57e 1708 vmx->guest_msrs_ready = false;
5897297b 1709
8d14695f 1710 if (cpu_has_vmx_msr_bitmap())
904e14fb 1711 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1712}
1713
e79f245d 1714static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1715{
e79f245d 1716 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1717
e79f245d 1718 if (is_guest_mode(vcpu) &&
5e3d394f 1719 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
e79f245d
KA		 1720 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1721
1722 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1723}
1724
326e7425 1725static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1726{
45c3af97
PB		 1727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1728 u64 g_tsc_offset = 0;
1729
1730 /*
1731 * We're here if L1 chose not to trap WRMSR to TSC. According
1732 * to the spec, this should set L1's TSC; The offset that L1
1733 * set for L2 remains unchanged, and still needs to be added
1734 * to the newly set TSC to get L2's TSC.
1735 */
1736 if (is_guest_mode(vcpu) &&
5e3d394f 1737 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
45c3af97 1738 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1739
45c3af97
PB		 1740 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1741 vcpu->arch.tsc_offset - g_tsc_offset,
1742 offset);
1743 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1744 return offset + g_tsc_offset;
6aa8b732
AK		 1745}
1746
801d3424
NHE		 1747/*
1748 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1749 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1750 * all guests if the "nested" module option is off, and can also be disabled
1751 * for a single guest by disabling its VMX cpuid bit.
1752 */
7c97fcb3 1753bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1754{
d6321d49 1755 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1756}
1757
55d2375e
SC		 1758static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1759 uint64_t val)
62cc6b9d 1760{
55d2375e 1761 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1762
55d2375e 1763 return !(val & ~valid_bits);
62cc6b9d
DM		 1764}
1765
55d2375e 1766static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1767{
55d2375e
SC		 1768 switch (msr->index) {
1769 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1770 if (!nested)
1771 return 1;
1772 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1773 default:
1774 return 1;
1775 }
62cc6b9d
DM		 1776}
1777
55d2375e
SC		 1778/*
1779 * Reads an msr value (of 'msr_index') into 'pdata'.
1780 * Returns 0 on success, non-0 otherwise.
1781 * Assumes vcpu_load() was already called.
1782 */
1783static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1784{
55d2375e
SC		 1785 struct vcpu_vmx *vmx = to_vmx(vcpu);
1786 struct shared_msr_entry *msr;
bf8c55d8 1787 u32 index;
62cc6b9d 1788
55d2375e
SC		 1789 switch (msr_info->index) {
1790#ifdef CONFIG_X86_64
1791 case MSR_FS_BASE:
1792 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1793 break;
55d2375e
SC		 1794 case MSR_GS_BASE:
1795 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1796 break;
55d2375e
SC		 1797 case MSR_KERNEL_GS_BASE:
1798 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1799 break;
55d2375e
SC		 1800#endif
1801 case MSR_EFER:
1802 return kvm_get_msr_common(vcpu, msr_info);
c11f83e0
PB		 1803 case MSR_IA32_TSX_CTRL:
1804 if (!msr_info->host_initiated &&
1805 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1806 return 1;
1807 goto find_shared_msr;
6e3ba4ab
TX		 1808 case MSR_IA32_UMWAIT_CONTROL:
1809 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1810 return 1;
1811
1812 msr_info->data = vmx->msr_ia32_umwait_control;
1813 break;
55d2375e
SC		 1814 case MSR_IA32_SPEC_CTRL:
1815 if (!msr_info->host_initiated &&
1816 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1817 return 1;
1818
1819 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1820 break;
6aa8b732 1821 case MSR_IA32_SYSENTER_CS:
609e36d3 1822 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1823 break;
1824 case MSR_IA32_SYSENTER_EIP:
609e36d3 1825 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1826 break;
1827 case MSR_IA32_SYSENTER_ESP:
609e36d3 1828 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1829 break;
0dd376e7 1830 case MSR_IA32_BNDCFGS:
691bd434 1831 if (!kvm_mpx_supported() ||
d6321d49
RK		 1832 (!msr_info->host_initiated &&
1833 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1834 return 1;
609e36d3 1835 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1836 break;
c45dcc71
AR		 1837 case MSR_IA32_MCG_EXT_CTL:
1838 if (!msr_info->host_initiated &&
a6cb099a 1839 !(vmx->msr_ia32_feature_control &
c45dcc71 1840 FEATURE_CONTROL_LMCE))
cae50139 1841 return 1;
c45dcc71
AR		 1842 msr_info->data = vcpu->arch.mcg_ext_ctl;
1843 break;
cae50139 1844 case MSR_IA32_FEATURE_CONTROL:
a6cb099a 1845 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1846 break;
1847 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1848 if (!nested_vmx_allowed(vcpu))
1849 return 1;
6677f3da
PB		 1850 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1851 &msr_info->data);
bf8c55d8
CP		 1852 case MSR_IA32_RTIT_CTL:
1853 if (pt_mode != PT_MODE_HOST_GUEST)
1854 return 1;
1855 msr_info->data = vmx->pt_desc.guest.ctl;
1856 break;
1857 case MSR_IA32_RTIT_STATUS:
1858 if (pt_mode != PT_MODE_HOST_GUEST)
1859 return 1;
1860 msr_info->data = vmx->pt_desc.guest.status;
1861 break;
1862 case MSR_IA32_RTIT_CR3_MATCH:
1863 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1864 !intel_pt_validate_cap(vmx->pt_desc.caps,
1865 PT_CAP_cr3_filtering))
1866 return 1;
1867 msr_info->data = vmx->pt_desc.guest.cr3_match;
1868 break;
1869 case MSR_IA32_RTIT_OUTPUT_BASE:
1870 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1871 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1872 PT_CAP_topa_output) &&
1873 !intel_pt_validate_cap(vmx->pt_desc.caps,
1874 PT_CAP_single_range_output)))
1875 return 1;
1876 msr_info->data = vmx->pt_desc.guest.output_base;
1877 break;
1878 case MSR_IA32_RTIT_OUTPUT_MASK:
1879 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1880 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1881 PT_CAP_topa_output) &&
1882 !intel_pt_validate_cap(vmx->pt_desc.caps,
1883 PT_CAP_single_range_output)))
1884 return 1;
1885 msr_info->data = vmx->pt_desc.guest.output_mask;
1886 break;
1887 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1888 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1889 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1890 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1891 PT_CAP_num_address_ranges)))
1892 return 1;
1893 if (index % 2)
1894 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1895 else
1896 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1897 break;
4e47c7a6 1898 case MSR_TSC_AUX:
d6321d49
RK		 1899 if (!msr_info->host_initiated &&
1900 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1901 return 1;
c11f83e0 1902 goto find_shared_msr;
6aa8b732 1903 default:
c11f83e0 1904 find_shared_msr:
a6cb099a 1905 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1906 if (msr) {
609e36d3 1907 msr_info->data = msr->data;
3bab1f5d 1908 break;
6aa8b732 1909 }
609e36d3 1910 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1911 }
1912
6aa8b732
AK		 1913 return 0;
1914}
1915
1916/*
1917 * Writes msr value into into the appropriate "register".
1918 * Returns 0 on success, non-0 otherwise.
1919 * Assumes vcpu_load() was already called.
1920 */
8fe8ab46 1921static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1922{
a2fa3e9f 1923 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1924 struct shared_msr_entry *msr;
2cc51560 1925 int ret = 0;
8fe8ab46
WA		 1926 u32 msr_index = msr_info->index;
1927 u64 data = msr_info->data;
bf8c55d8 1928 u32 index;
2cc51560 1929
6aa8b732 1930 switch (msr_index) {
3bab1f5d 1931 case MSR_EFER:
8fe8ab46 1932 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1933 break;
16175a79 1934#ifdef CONFIG_X86_64
6aa8b732 1935 case MSR_FS_BASE:
2fb92db1 1936 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1937 vmcs_writel(GUEST_FS_BASE, data);
1938 break;
1939 case MSR_GS_BASE:
2fb92db1 1940 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1941 vmcs_writel(GUEST_GS_BASE, data);
1942 break;
44ea2b17 1943 case MSR_KERNEL_GS_BASE:
678e315e 1944 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1945 break;
6aa8b732
AK		 1946#endif
1947 case MSR_IA32_SYSENTER_CS:
de70d279
SC		 1948 if (is_guest_mode(vcpu))
1949 get_vmcs12(vcpu)->guest_sysenter_cs = data;
6aa8b732
AK		 1950 vmcs_write32(GUEST_SYSENTER_CS, data);
1951 break;
1952 case MSR_IA32_SYSENTER_EIP:
de70d279
SC		 1953 if (is_guest_mode(vcpu))
1954 get_vmcs12(vcpu)->guest_sysenter_eip = data;
f5b42c33 1955 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1956 break;
1957 case MSR_IA32_SYSENTER_ESP:
de70d279
SC		 1958 if (is_guest_mode(vcpu))
1959 get_vmcs12(vcpu)->guest_sysenter_esp = data;
f5b42c33 1960 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1961 break;
699a1ac2
SC		 1962 case MSR_IA32_DEBUGCTLMSR:
1963 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1964 VM_EXIT_SAVE_DEBUG_CONTROLS)
1965 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1966
1967 ret = kvm_set_msr_common(vcpu, msr_info);
1968 break;
1969
0dd376e7 1970 case MSR_IA32_BNDCFGS:
691bd434 1971 if (!kvm_mpx_supported() ||
d6321d49
RK		 1972 (!msr_info->host_initiated &&
1973 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1974 return 1;
fd8cb433 1975 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 1976 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 1977 return 1;
0dd376e7
LJ		 1978 vmcs_write64(GUEST_BNDCFGS, data);
1979 break;
6e3ba4ab
TX		 1980 case MSR_IA32_UMWAIT_CONTROL:
1981 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1982 return 1;
1983
1984 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1985 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1986 return 1;
1987
1988 vmx->msr_ia32_umwait_control = data;
1989 break;
d28b387f
KA		 1990 case MSR_IA32_SPEC_CTRL:
1991 if (!msr_info->host_initiated &&
d28b387f
KA		 1992 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1993 return 1;
1994
1995 /* The STIBP bit doesn't fault even if it's not advertised */
9f65fb29 1996 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
d28b387f
KA		 1997 return 1;
1998
1999 vmx->spec_ctrl = data;
2000
2001 if (!data)
2002 break;
2003
2004 /*
2005 * For non-nested:
2006 * When it's written (to non-zero) for the first time, pass
2007 * it through.
2008 *
2009 * For nested:
2010 * The handling of the MSR bitmap for L2 guests is done in
4d516fe7 2011 * nested_vmx_prepare_msr_bitmap. We should not touch the
d28b387f
KA		 2012 * vmcs02.msr_bitmap here since it gets completely overwritten
2013 * in the merging. We update the vmcs01 here for L1 as well
2014 * since it will end up touching the MSR anyway now.
2015 */
2016 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2017 MSR_IA32_SPEC_CTRL,
2018 MSR_TYPE_RW);
2019 break;
c11f83e0
PB		 2020 case MSR_IA32_TSX_CTRL:
2021 if (!msr_info->host_initiated &&
2022 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2023 return 1;
2024 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2025 return 1;
2026 goto find_shared_msr;
15d45071
AR		 2027 case MSR_IA32_PRED_CMD:
2028 if (!msr_info->host_initiated &&
15d45071
AR		 2029 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2030 return 1;
2031
2032 if (data & ~PRED_CMD_IBPB)
2033 return 1;
2034
2035 if (!data)
2036 break;
2037
2038 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2039
2040 /*
2041 * For non-nested:
2042 * When it's written (to non-zero) for the first time, pass
2043 * it through.
2044 *
2045 * For nested:
2046 * The handling of the MSR bitmap for L2 guests is done in
4d516fe7 2047 * nested_vmx_prepare_msr_bitmap. We should not touch the
15d45071
AR		 2048 * vmcs02.msr_bitmap here since it gets completely overwritten
2049 * in the merging.
2050 */
2051 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2052 MSR_TYPE_W);
2053 break;
468d472f 2054 case MSR_IA32_CR_PAT:
d28f4290
SC		 2055 if (!kvm_pat_valid(data))
2056 return 1;
2057
142e4be7
SC		 2058 if (is_guest_mode(vcpu) &&
2059 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2060 get_vmcs12(vcpu)->guest_ia32_pat = data;
2061
468d472f
SY		 2062 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2063 vmcs_write64(GUEST_IA32_PAT, data);
2064 vcpu->arch.pat = data;
2065 break;
2066 }
8fe8ab46 2067 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2068 break;
ba904635
WA		 2069 case MSR_IA32_TSC_ADJUST:
2070 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2071 break;
c45dcc71
AR		 2072 case MSR_IA32_MCG_EXT_CTL:
2073 if ((!msr_info->host_initiated &&
2074 !(to_vmx(vcpu)->msr_ia32_feature_control &
2075 FEATURE_CONTROL_LMCE)) ||
2076 (data & ~MCG_EXT_CTL_LMCE_EN))
2077 return 1;
2078 vcpu->arch.mcg_ext_ctl = data;
2079 break;
cae50139 2080 case MSR_IA32_FEATURE_CONTROL:
37e4c997 2081 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 2082 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK		 2083 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2084 return 1;
3b84080b 2085 vmx->msr_ia32_feature_control = data;
cae50139
JK		 2086 if (msr_info->host_initiated && data == 0)
2087 vmx_leave_nested(vcpu);
2088 break;
2089 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 2090 if (!msr_info->host_initiated)
2091 return 1; /* they are read-only */
2092 if (!nested_vmx_allowed(vcpu))
2093 return 1;
2094 return vmx_set_vmx_msr(vcpu, msr_index, data);
bf8c55d8
CP		 2095 case MSR_IA32_RTIT_CTL:
2096 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 2097 vmx_rtit_ctl_check(vcpu, data) ||
2098 vmx->nested.vmxon)
bf8c55d8
CP		 2099 return 1;
2100 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2101 vmx->pt_desc.guest.ctl = data;
b08c2896 2102 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 2103 break;
2104 case MSR_IA32_RTIT_STATUS:
2105 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2106 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2107 (data & MSR_IA32_RTIT_STATUS_MASK))
2108 return 1;
2109 vmx->pt_desc.guest.status = data;
2110 break;
2111 case MSR_IA32_RTIT_CR3_MATCH:
2112 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2113 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2114 !intel_pt_validate_cap(vmx->pt_desc.caps,
2115 PT_CAP_cr3_filtering))
2116 return 1;
2117 vmx->pt_desc.guest.cr3_match = data;
2118 break;
2119 case MSR_IA32_RTIT_OUTPUT_BASE:
2120 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2121 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2122 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2123 PT_CAP_topa_output) &&
2124 !intel_pt_validate_cap(vmx->pt_desc.caps,
2125 PT_CAP_single_range_output)) ||
2126 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2127 return 1;
2128 vmx->pt_desc.guest.output_base = data;
2129 break;
2130 case MSR_IA32_RTIT_OUTPUT_MASK:
2131 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2132 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2133 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2134 PT_CAP_topa_output) &&
2135 !intel_pt_validate_cap(vmx->pt_desc.caps,
2136 PT_CAP_single_range_output)))
2137 return 1;
2138 vmx->pt_desc.guest.output_mask = data;
2139 break;
2140 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2141 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2142 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2143 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2144 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2145 PT_CAP_num_address_ranges)))
2146 return 1;
2147 if (index % 2)
2148 vmx->pt_desc.guest.addr_b[index / 2] = data;
2149 else
2150 vmx->pt_desc.guest.addr_a[index / 2] = data;
2151 break;
4e47c7a6 2152 case MSR_TSC_AUX:
d6321d49
RK		 2153 if (!msr_info->host_initiated &&
2154 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2155 return 1;
2156 /* Check reserved bit, higher 32 bits should be zero */
2157 if ((data >> 32) != 0)
2158 return 1;
c11f83e0
PB		 2159 goto find_shared_msr;
2160
6aa8b732 2161 default:
c11f83e0 2162 find_shared_msr:
8b9cf98c 2163 msr = find_msr_entry(vmx, msr_index);
b07a5c53
PB		 2164 if (msr)
2165 ret = vmx_set_guest_msr(vmx, msr, data);
2166 else
2167 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2168 }
2169
2cc51560 2170 return ret;
6aa8b732
AK		 2171}
2172
5fdbf976 2173static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2174{
cb3c1e2f
SC		 2175 kvm_register_mark_available(vcpu, reg);
2176
5fdbf976
MT		 2177 switch (reg) {
2178 case VCPU_REGS_RSP:
2179 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2180 break;
2181 case VCPU_REGS_RIP:
2182 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2183 break;
6de4f3ad
AK		 2184 case VCPU_EXREG_PDPTR:
2185 if (enable_ept)
2186 ept_save_pdptrs(vcpu);
2187 break;
34059c25
SC		 2188 case VCPU_EXREG_CR3:
2189 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2190 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2191 break;
5fdbf976 2192 default:
34059c25 2193 WARN_ON_ONCE(1);
5fdbf976
MT		 2194 break;
2195 }
6aa8b732
AK		 2196}
2197
6aa8b732
AK		 2198static __init int cpu_has_kvm_support(void)
2199{
6210e37b 2200 return cpu_has_vmx();
6aa8b732
AK		 2201}
2202
2203static __init int vmx_disabled_by_bios(void)
2204{
2205 u64 msr;
2206
2207 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2208 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2209 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2210 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2211 && tboot_enabled())
2212 return 1;
23f3e991 2213 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2214 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2215 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2216 && !tboot_enabled()) {
2217 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2218 "activate TXT before enabling KVM\n");
cafd6659 2219 return 1;
f9335afe 2220 }
23f3e991
JC		 2221 /* launched w/o TXT and VMX disabled */
2222 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2223 && !tboot_enabled())
2224 return 1;
cafd6659
SW		 2225 }
2226
2227 return 0;
6aa8b732
AK		 2228}
2229
7725b894
DX		 2230static void kvm_cpu_vmxon(u64 addr)
2231{
fe0e80be 2232 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2233 intel_pt_handle_vmx(1);
2234
4b1e5478 2235 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2236}
2237
13a34e06 2238static int hardware_enable(void)
6aa8b732
AK		 2239{
2240 int cpu = raw_smp_processor_id();
2241 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2242 u64 old, test_bits;
6aa8b732 2243
1e02ce4c 2244 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2245 return -EBUSY;
2246
773e8a04
VK		 2247 /*
2248 * This can happen if we hot-added a CPU but failed to allocate
2249 * VP assist page for it.
2250 */
2251 if (static_branch_unlikely(&enable_evmcs) &&
2252 !hv_get_vp_assist_page(cpu))
2253 return -EFAULT;
2254
d462b819 2255 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2256 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2257 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2258
2259 /*
2260 * Now we can enable the vmclear operation in kdump
2261 * since the loaded_vmcss_on_cpu list on this cpu
2262 * has been initialized.
2263 *
2264 * Though the cpu is not in VMX operation now, there
2265 * is no problem to enable the vmclear operation
2266 * for the loaded_vmcss_on_cpu list is empty!
2267 */
2268 crash_enable_local_vmclear(cpu);
2269
6aa8b732 2270 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2271
2272 test_bits = FEATURE_CONTROL_LOCKED;
2273 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2274 if (tboot_enabled())
2275 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2276
2277 if ((old & test_bits) != test_bits) {
6aa8b732 2278 /* enable and lock */
cafd6659
SW		 2279 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2280 }
fe0e80be 2281 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2282 if (enable_ept)
2283 ept_sync_global();
10474ae8
AG		 2284
2285 return 0;
6aa8b732
AK		 2286}
2287
d462b819 2288static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2289{
2290 int cpu = raw_smp_processor_id();
d462b819 2291 struct loaded_vmcs *v, *n;
543e4243 2292
d462b819
NHE		 2293 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2294 loaded_vmcss_on_cpu_link)
2295 __loaded_vmcs_clear(v);
543e4243
AK		 2296}
2297
710ff4a8
EH		 2298
2299/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2300 * tricks.
2301 */
2302static void kvm_cpu_vmxoff(void)
6aa8b732 2303{
4b1e5478 2304 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2305
2306 intel_pt_handle_vmx(0);
fe0e80be 2307 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2308}
2309
13a34e06 2310static void hardware_disable(void)
710ff4a8 2311{
fe0e80be
DH		 2312 vmclear_local_loaded_vmcss();
2313 kvm_cpu_vmxoff();
710ff4a8
EH		 2314}
2315
1c3d14fe 2316static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2317 u32 msr, u32 *result)
1c3d14fe
YS		 2318{
2319 u32 vmx_msr_low, vmx_msr_high;
2320 u32 ctl = ctl_min | ctl_opt;
2321
2322 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2323
2324 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2325 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2326
2327 /* Ensure minimum (required) set of control bits are supported. */
2328 if (ctl_min & ~ctl)
002c7f7c 2329 return -EIO;
1c3d14fe
YS		 2330
2331 *result = ctl;
2332 return 0;
2333}
2334
7caaa711
SC		 2335static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2336 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2337{
2338 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2339 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2340 u32 _pin_based_exec_control = 0;
2341 u32 _cpu_based_exec_control = 0;
f78e0e2e 2342 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2343 u32 _vmexit_control = 0;
2344 u32 _vmentry_control = 0;
2345
1389309c 2346 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2347 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2348#ifdef CONFIG_X86_64
2349 CPU_BASED_CR8_LOAD_EXITING |
2350 CPU_BASED_CR8_STORE_EXITING |
2351#endif
d56f546d
SY		 2352 CPU_BASED_CR3_LOAD_EXITING |
2353 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2354 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2355 CPU_BASED_MOV_DR_EXITING |
5e3d394f 2356 CPU_BASED_USE_TSC_OFFSETTING |
4d5422ce
WL		 2357 CPU_BASED_MWAIT_EXITING |
2358 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2359 CPU_BASED_INVLPG_EXITING |
2360 CPU_BASED_RDPMC_EXITING;
443381a8 2361
f78e0e2e 2362 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2363 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2364 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2365 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2366 &_cpu_based_exec_control) < 0)
002c7f7c 2367 return -EIO;
6e5d865c
YS		 2368#ifdef CONFIG_X86_64
2369 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2370 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2371 ~CPU_BASED_CR8_STORE_EXITING;
2372#endif
f78e0e2e 2373 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2374 min2 = 0;
2375 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2376 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2377 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2378 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2379 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2380 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2381 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2382 SECONDARY_EXEC_DESC |
ad756a16 2383 SECONDARY_EXEC_RDTSCP |
83d4c286 2384 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2385 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2386 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2387 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2388 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2389 SECONDARY_EXEC_RDSEED_EXITING |
2390 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2391 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2392 SECONDARY_EXEC_TSC_SCALING |
e69e72fa 2393 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
f99e3daf
CP		 2394 SECONDARY_EXEC_PT_USE_GPA |
2395 SECONDARY_EXEC_PT_CONCEAL_VMX |
0b665d30
SC		 2396 SECONDARY_EXEC_ENABLE_VMFUNC |
2397 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2398 if (adjust_vmx_controls(min2, opt2,
2399 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2400 &_cpu_based_2nd_exec_control) < 0)
2401 return -EIO;
2402 }
2403#ifndef CONFIG_X86_64
2404 if (!(_cpu_based_2nd_exec_control &
2405 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2406 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2407#endif
83d4c286
YZ		 2408
2409 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2410 _cpu_based_2nd_exec_control &= ~(
8d14695f 2411 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2412 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2413 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2414
61f1dd90 2415 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2416 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2417
d56f546d 2418 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2419 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2420 enabled */
5fff7d27
GN		 2421 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2422 CPU_BASED_CR3_STORE_EXITING |
2423 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2424 } else if (vmx_cap->ept) {
2425 vmx_cap->ept = 0;
61f1dd90
WL		 2426 pr_warn_once("EPT CAP should not exist if not support "
2427 "1-setting enable EPT VM-execution control\n");
2428 }
2429 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2430 vmx_cap->vpid) {
2431 vmx_cap->vpid = 0;
61f1dd90
WL		 2432 pr_warn_once("VPID CAP should not exist if not support "
2433 "1-setting enable VPID VM-execution control\n");
d56f546d 2434 }
1c3d14fe 2435
91fa0f8e 2436 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2437#ifdef CONFIG_X86_64
2438 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2439#endif
c73da3fc 2440 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2441 VM_EXIT_LOAD_IA32_PAT |
2442 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2443 VM_EXIT_CLEAR_BNDCFGS |
2444 VM_EXIT_PT_CONCEAL_PIP |
2445 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2446 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2447 &_vmexit_control) < 0)
002c7f7c 2448 return -EIO;
1c3d14fe 2449
8a1b4392
PB		 2450 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2451 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2452 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2453 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2454 &_pin_based_exec_control) < 0)
2455 return -EIO;
2456
1c17c3e6
PB		 2457 if (cpu_has_broken_vmx_preemption_timer())
2458 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2459 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2460 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2461 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2462
c845f9c6 2463 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2464 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2465 VM_ENTRY_LOAD_IA32_PAT |
2466 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2467 VM_ENTRY_LOAD_BNDCFGS |
2468 VM_ENTRY_PT_CONCEAL_PIP |
2469 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2470 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2471 &_vmentry_control) < 0)
002c7f7c 2472 return -EIO;
6aa8b732 2473
c73da3fc
SC		 2474 /*
2475 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2476 * can't be used due to an errata where VM Exit may incorrectly clear
2477 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2478 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2479 */
2480 if (boot_cpu_data.x86 == 0x6) {
2481 switch (boot_cpu_data.x86_model) {
2482 case 26: /* AAK155 */
2483 case 30: /* AAP115 */
2484 case 37: /* AAT100 */
2485 case 44: /* BC86,AAY89,BD102 */
2486 case 46: /* BA97 */
85ba2b16 2487 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2488 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2489 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2490 "does not work properly. Using workaround\n");
2491 break;
2492 default:
2493 break;
2494 }
2495 }
2496
2497
c68876fd 2498 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2499
2500 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2501 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2502 return -EIO;
1c3d14fe
YS		 2503
2504#ifdef CONFIG_X86_64
2505 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2506 if (vmx_msr_high & (1u<<16))
002c7f7c 2507 return -EIO;
1c3d14fe
YS		 2508#endif
2509
2510 /* Require Write-Back (WB) memory type for VMCS accesses. */
2511 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2512 return -EIO;
1c3d14fe 2513
002c7f7c 2514 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2515 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2516 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2517
2307af1c 2518 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2519
002c7f7c
YS		 2520 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2521 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2522 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2523 vmcs_conf->vmexit_ctrl = _vmexit_control;
2524 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2525
773e8a04
VK		 2526 if (static_branch_unlikely(&enable_evmcs))
2527 evmcs_sanitize_exec_ctrls(vmcs_conf);
2528
1c3d14fe 2529 return 0;
c68876fd 2530}
6aa8b732 2531
41836839 2532struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2533{
2534 int node = cpu_to_node(cpu);
2535 struct page *pages;
2536 struct vmcs *vmcs;
2537
41836839 2538 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2539 if (!pages)
2540 return NULL;
2541 vmcs = page_address(pages);
1c3d14fe 2542 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2543
2544 /* KVM supports Enlightened VMCS v1 only */
2545 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2546 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2547 else
392b2f25 2548 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2549
491a6038
LA		 2550 if (shadow)
2551 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2552 return vmcs;
2553}
2554
89b0c9f5 2555void free_vmcs(struct vmcs *vmcs)
6aa8b732 2556{
1c3d14fe 2557 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2558}
2559
d462b819
NHE		 2560/*
2561 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2562 */
89b0c9f5 2563void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2564{
2565 if (!loaded_vmcs->vmcs)
2566 return;
2567 loaded_vmcs_clear(loaded_vmcs);
2568 free_vmcs(loaded_vmcs->vmcs);
2569 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2570 if (loaded_vmcs->msr_bitmap)
2571 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2572 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2573}
2574
89b0c9f5 2575int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2576{
491a6038 2577 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2578 if (!loaded_vmcs->vmcs)
2579 return -ENOMEM;
2580
2581 loaded_vmcs->shadow_vmcs = NULL;
804939ea 2582 loaded_vmcs->hv_timer_soft_disabled = false;
f21f165e 2583 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2584
2585 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2586 loaded_vmcs->msr_bitmap = (unsigned long *)
2587 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2588 if (!loaded_vmcs->msr_bitmap)
2589 goto out_vmcs;
2590 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2591
1f008e11
AB		 2592 if (IS_ENABLED(CONFIG_HYPERV) &&
2593 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2594 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2595 struct hv_enlightened_vmcs *evmcs =
2596 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2597
2598 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2599 }
904e14fb 2600 }
d7ee039e
SC		 2601
2602 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
3af80fec
SC		 2603 memset(&loaded_vmcs->controls_shadow, 0,
2604 sizeof(struct vmcs_controls_shadow));
d7ee039e 2605
f21f165e 2606 return 0;
904e14fb
PB		 2607
2608out_vmcs:
2609 free_loaded_vmcs(loaded_vmcs);
2610 return -ENOMEM;
f21f165e
PB		 2611}
2612
39959588 2613static void free_kvm_area(void)
6aa8b732
AK		 2614{
2615 int cpu;
2616
3230bb47 2617 for_each_possible_cpu(cpu) {
6aa8b732 2618 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2619 per_cpu(vmxarea, cpu) = NULL;
2620 }
6aa8b732
AK		 2621}
2622
6aa8b732
AK		 2623static __init int alloc_kvm_area(void)
2624{
2625 int cpu;
2626
3230bb47 2627 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2628 struct vmcs *vmcs;
2629
41836839 2630 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2631 if (!vmcs) {
2632 free_kvm_area();
2633 return -ENOMEM;
2634 }
2635
2307af1c
LA		 2636 /*
2637 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2638 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2639 * revision_id reported by MSR_IA32_VMX_BASIC.
2640 *
312a4661 2641 * However, even though not explicitly documented by
2307af1c
LA		 2642 * TLFS, VMXArea passed as VMXON argument should
2643 * still be marked with revision_id reported by
2644 * physical CPU.
2645 */
2646 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2647 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2648
6aa8b732
AK		 2649 per_cpu(vmxarea, cpu) = vmcs;
2650 }
2651 return 0;
2652}
2653
91b0aa2c 2654static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2655 struct kvm_segment *save)
6aa8b732 2656{
d99e4152
GN		 2657 if (!emulate_invalid_guest_state) {
2658 /*
2659 * CS and SS RPL should be equal during guest entry according
2660 * to VMX spec, but in reality it is not always so. Since vcpu
2661 * is in the middle of the transition from real mode to
2662 * protected mode it is safe to assume that RPL 0 is a good
2663 * default value.
2664 */
2665 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2666 save->selector &= ~SEGMENT_RPL_MASK;
2667 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2668 save->s = 1;
6aa8b732 2669 }
d99e4152 2670 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2671}
2672
2673static void enter_pmode(struct kvm_vcpu *vcpu)
2674{
2675 unsigned long flags;
a89a8fb9 2676 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2677
d99e4152
GN		 2678 /*
2679 * Update real mode segment cache. It may be not up-to-date if sement
2680 * register was written while vcpu was in a guest mode.
2681 */
2682 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2683 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2684 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2685 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2686 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2687 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2688
7ffd92c5 2689 vmx->rmode.vm86_active = 0;
6aa8b732 2690
2fb92db1
AK		 2691 vmx_segment_cache_clear(vmx);
2692
f5f7b2fe 2693 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2694
2695 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2696 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2697 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2698 vmcs_writel(GUEST_RFLAGS, flags);
2699
66aee91a
RR		 2700 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2701 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2702
2703 update_exception_bitmap(vcpu);
2704
91b0aa2c
GN		 2705 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2706 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2707 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2708 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2709 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2710 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2711}
2712
f5f7b2fe 2713static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2714{
772e0318 2715 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2716 struct kvm_segment var = *save;
2717
2718 var.dpl = 0x3;
2719 if (seg == VCPU_SREG_CS)
2720 var.type = 0x3;
2721
2722 if (!emulate_invalid_guest_state) {
2723 var.selector = var.base >> 4;
2724 var.base = var.base & 0xffff0;
2725 var.limit = 0xffff;
2726 var.g = 0;
2727 var.db = 0;
2728 var.present = 1;
2729 var.s = 1;
2730 var.l = 0;
2731 var.unusable = 0;
2732 var.type = 0x3;
2733 var.avl = 0;
2734 if (save->base & 0xf)
2735 printk_once(KERN_WARNING "kvm: segment base is not "
2736 "paragraph aligned when entering "
2737 "protected mode (seg=%d)", seg);
2738 }
6aa8b732 2739
d99e4152 2740 vmcs_write16(sf->selector, var.selector);
96794e4e 2741 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2742 vmcs_write32(sf->limit, var.limit);
2743 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2744}
2745
2746static void enter_rmode(struct kvm_vcpu *vcpu)
2747{
2748 unsigned long flags;
a89a8fb9 2749 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2750 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2751
f5f7b2fe
AK		 2752 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2753 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2754 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2757 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2758 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2759
7ffd92c5 2760 vmx->rmode.vm86_active = 1;
6aa8b732 2761
776e58ea
GN		 2762 /*
2763 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2764 * vcpu. Warn the user that an update is overdue.
776e58ea 2765 */
40bbb9d0 2766 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2767 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2768 "called before entering vcpu\n");
776e58ea 2769
2fb92db1
AK		 2770 vmx_segment_cache_clear(vmx);
2771
40bbb9d0 2772 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2773 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2774 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2775
2776 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2777 vmx->rmode.save_rflags = flags;
6aa8b732 2778
053de044 2779 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2780
2781 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2782 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2783 update_exception_bitmap(vcpu);
2784
d99e4152
GN		 2785 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2786 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2787 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2788 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2789 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2790 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2791
8668a3c4 2792 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2793}
2794
97b7ead3 2795void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2796{
2797 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2798 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2799
2800 if (!msr)
2801 return;
401d10de 2802
f6801dff 2803 vcpu->arch.efer = efer;
401d10de 2804 if (efer & EFER_LMA) {
2961e876 2805 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2806 msr->data = efer;
2807 } else {
2961e876 2808 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2809
2810 msr->data = efer & ~EFER_LME;
2811 }
2812 setup_msrs(vmx);
2813}
2814
05b3e0c2 2815#ifdef CONFIG_X86_64
6aa8b732
AK		 2816
2817static void enter_lmode(struct kvm_vcpu *vcpu)
2818{
2819 u32 guest_tr_ar;
2820
2fb92db1
AK		 2821 vmx_segment_cache_clear(to_vmx(vcpu));
2822
6aa8b732 2823 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2824 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2825 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2826 __func__);
6aa8b732 2827 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2828 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2829 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2830 }
da38f438 2831 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2832}
2833
2834static void exit_lmode(struct kvm_vcpu *vcpu)
2835{
2961e876 2836 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2837 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2838}
2839
2840#endif
2841
faff8758
JS		 2842static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2843{
2844 int vpid = to_vmx(vcpu)->vpid;
2845
2846 if (!vpid_sync_vcpu_addr(vpid, addr))
2847 vpid_sync_context(vpid);
2848
2849 /*
2850 * If VPIDs are not supported or enabled, then the above is a no-op.
2851 * But we don't really need a TLB flush in that case anyway, because
2852 * each VM entry/exit includes an implicit flush when VPID is 0.
2853 */
2854}
2855
e8467fda
AK		 2856static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2857{
2858 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2859
2860 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2861 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2862}
2863
25c4c276 2864static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2865{
fc78f519
AK		 2866 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2867
2868 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2869 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2870}
2871
1439442c
SY		 2872static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2873{
d0d538b9
GN		 2874 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2875
cb3c1e2f 2876 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
6de4f3ad
AK		 2877 return;
2878
bf03d4f9 2879 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2880 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2881 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2882 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2883 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2884 }
2885}
2886
97b7ead3 2887void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2888{
d0d538b9
GN		 2889 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2890
bf03d4f9 2891 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2892 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2893 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2894 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2895 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2896 }
6de4f3ad 2897
cb3c1e2f 2898 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
8f5d549f
AK		 2899}
2900
1439442c
SY		 2901static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2902 unsigned long cr0,
2903 struct kvm_vcpu *vcpu)
2904{
2183f564
SC		 2905 struct vcpu_vmx *vmx = to_vmx(vcpu);
2906
cb3c1e2f 2907 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
34059c25 2908 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
1439442c
SY		 2909 if (!(cr0 & X86_CR0_PG)) {
2910 /* From paging/starting to nonpaging */
2183f564
SC		 2911 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2912 CPU_BASED_CR3_STORE_EXITING);
1439442c 2913 vcpu->arch.cr0 = cr0;
fc78f519 2914 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2915 } else if (!is_paging(vcpu)) {
2916 /* From nonpaging to paging */
2183f564
SC		 2917 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2918 CPU_BASED_CR3_STORE_EXITING);
1439442c 2919 vcpu->arch.cr0 = cr0;
fc78f519 2920 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2921 }
95eb84a7
SY		 2922
2923 if (!(cr0 & X86_CR0_WP))
2924 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2925}
2926
97b7ead3 2927void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2928{
7ffd92c5 2929 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2930 unsigned long hw_cr0;
2931
3de6347b 2932 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2933 if (enable_unrestricted_guest)
5037878e 2934 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2935 else {
5037878e 2936 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2937
218e763f
GN		 2938 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2939 enter_pmode(vcpu);
6aa8b732 2940
218e763f
GN		 2941 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2942 enter_rmode(vcpu);
2943 }
6aa8b732 2944
05b3e0c2 2945#ifdef CONFIG_X86_64
f6801dff 2946 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2947 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2948 enter_lmode(vcpu);
707d92fa 2949 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2950 exit_lmode(vcpu);
2951 }
2952#endif
2953
b4d18517 2954 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2955 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2956
6aa8b732 2957 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2958 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2959 vcpu->arch.cr0 = cr0;
14168786
GN		 2960
2961 /* depends on vcpu->arch.cr0 to be set to a new value */
2962 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2963}
2964
855feb67
YZ		 2965static int get_ept_level(struct kvm_vcpu *vcpu)
2966{
2967 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2968 return 5;
2969 return 4;
2970}
2971
89b0c9f5 2972u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2973{
855feb67
YZ		 2974 u64 eptp = VMX_EPTP_MT_WB;
2975
2976 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 2977
995f00a6
PF		 2978 if (enable_ept_ad_bits &&
2979 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 2980 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 2981 eptp |= (root_hpa & PAGE_MASK);
2982
2983 return eptp;
2984}
2985
97b7ead3 2986void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 2987{
877ad952 2988 struct kvm *kvm = vcpu->kvm;
04f11ef4 2989 bool update_guest_cr3 = true;
1439442c
SY		 2990 unsigned long guest_cr3;
2991 u64 eptp;
2992
2993 guest_cr3 = cr3;
089d034e 2994 if (enable_ept) {
995f00a6 2995 eptp = construct_eptp(vcpu, cr3);
1439442c 2996 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 2997
2998 if (kvm_x86_ops->tlb_remote_flush) {
2999 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3000 to_vmx(vcpu)->ept_pointer = eptp;
3001 to_kvm_vmx(kvm)->ept_pointers_match
3002 = EPT_POINTERS_CHECK;
3003 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3004 }
3005
04f11ef4
SC		 3006 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3007 if (is_guest_mode(vcpu))
3008 update_guest_cr3 = false;
b17b7436 3009 else if (!enable_unrestricted_guest && !is_paging(vcpu))
877ad952 3010 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
b17b7436
SC		 3011 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3012 guest_cr3 = vcpu->arch.cr3;
3013 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3014 update_guest_cr3 = false;
7c93be44 3015 ept_load_pdptrs(vcpu);
1439442c
SY		 3016 }
3017
04f11ef4
SC		 3018 if (update_guest_cr3)
3019 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3020}
3021
97b7ead3 3022int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3023{
fe7f895d 3024 struct vcpu_vmx *vmx = to_vmx(vcpu);
085e68ee
BS		 3025 /*
3026 * Pass through host's Machine Check Enable value to hw_cr4, which
3027 * is in force while we are in guest mode. Do not let guests control
3028 * this bit, even if host CR4.MCE == 0.
3029 */
5dc1f044
SC		 3030 unsigned long hw_cr4;
3031
3032 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3033 if (enable_unrestricted_guest)
3034 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
fe7f895d 3035 else if (vmx->rmode.vm86_active)
5dc1f044
SC		 3036 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3037 else
3038 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 3039
64f7a115
SC		 3040 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3041 if (cr4 & X86_CR4_UMIP) {
fe7f895d 3042 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
64f7a115
SC		 3043 hw_cr4 &= ~X86_CR4_UMIP;
3044 } else if (!is_guest_mode(vcpu) ||
fe7f895d
SC		 3045 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3046 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3047 }
64f7a115 3048 }
0367f205 3049
5e1746d6
NHE		 3050 if (cr4 & X86_CR4_VMXE) {
3051 /*
3052 * To use VMXON (and later other VMX instructions), a guest
3053 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3054 * So basically the check on whether to allow nested VMX
5bea5123
PB		 3055 * is here. We operate under the default treatment of SMM,
3056 * so VMX cannot be enabled under SMM.
5e1746d6 3057 */
5bea5123 3058 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 3059 return 1;
1a0d74e6 3060 }
3899152c 3061
fe7f895d 3062 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 3063 return 1;
3064
ad312c7c 3065 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 3066
3067 if (!enable_unrestricted_guest) {
3068 if (enable_ept) {
3069 if (!is_paging(vcpu)) {
3070 hw_cr4 &= ~X86_CR4_PAE;
3071 hw_cr4 |= X86_CR4_PSE;
3072 } else if (!(cr4 & X86_CR4_PAE)) {
3073 hw_cr4 &= ~X86_CR4_PAE;
3074 }
bc23008b 3075 }
1439442c 3076
656ec4a4 3077 /*
ddba2628
HH		 3078 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3079 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3080 * to be manually disabled when guest switches to non-paging
3081 * mode.
3082 *
3083 * If !enable_unrestricted_guest, the CPU is always running
3084 * with CR0.PG=1 and CR4 needs to be modified.
3085 * If enable_unrestricted_guest, the CPU automatically
3086 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 3087 */
5dc1f044
SC		 3088 if (!is_paging(vcpu))
3089 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3090 }
656ec4a4 3091
1439442c
SY		 3092 vmcs_writel(CR4_READ_SHADOW, cr4);
3093 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3094 return 0;
6aa8b732
AK		 3095}
3096
97b7ead3 3097void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 3098{
a9179499 3099 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3100 u32 ar;
3101
c6ad1153 3102 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3103 *var = vmx->rmode.segs[seg];
a9179499 3104 if (seg == VCPU_SREG_TR
2fb92db1 3105 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3106 return;
1390a28b
AK		 3107 var->base = vmx_read_guest_seg_base(vmx, seg);
3108 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3109 return;
a9179499 3110 }
2fb92db1
AK		 3111 var->base = vmx_read_guest_seg_base(vmx, seg);
3112 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3113 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3114 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3115 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3116 var->type = ar & 15;
3117 var->s = (ar >> 4) & 1;
3118 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3119 /*
3120 * Some userspaces do not preserve unusable property. Since usable
3121 * segment has to be present according to VMX spec we can use present
3122 * property to amend userspace bug by making unusable segment always
3123 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3124 * segment as unusable.
3125 */
3126 var->present = !var->unusable;
6aa8b732
AK		 3127 var->avl = (ar >> 12) & 1;
3128 var->l = (ar >> 13) & 1;
3129 var->db = (ar >> 14) & 1;
3130 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3131}
3132
a9179499
AK		 3133static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3134{
a9179499
AK		 3135 struct kvm_segment s;
3136
3137 if (to_vmx(vcpu)->rmode.vm86_active) {
3138 vmx_get_segment(vcpu, &s, seg);
3139 return s.base;
3140 }
2fb92db1 3141 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3142}
3143
97b7ead3 3144int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3145{
b09408d0
MT		 3146 struct vcpu_vmx *vmx = to_vmx(vcpu);
3147
ae9fedc7 3148 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3149 return 0;
ae9fedc7
PB		 3150 else {
3151 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3152 return VMX_AR_DPL(ar);
69c73028 3153 }
69c73028
AK		 3154}
3155
653e3108 3156static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3157{
6aa8b732
AK		 3158 u32 ar;
3159
f0495f9b 3160 if (var->unusable || !var->present)
6aa8b732
AK		 3161 ar = 1 << 16;
3162 else {
3163 ar = var->type & 15;
3164 ar |= (var->s & 1) << 4;
3165 ar |= (var->dpl & 3) << 5;
3166 ar |= (var->present & 1) << 7;
3167 ar |= (var->avl & 1) << 12;
3168 ar |= (var->l & 1) << 13;
3169 ar |= (var->db & 1) << 14;
3170 ar |= (var->g & 1) << 15;
3171 }
653e3108
AK		 3172
3173 return ar;
3174}
3175
97b7ead3 3176void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3177{
7ffd92c5 3178 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3179 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3180
2fb92db1
AK		 3181 vmx_segment_cache_clear(vmx);
3182
1ecd50a9
GN		 3183 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3184 vmx->rmode.segs[seg] = *var;
3185 if (seg == VCPU_SREG_TR)
3186 vmcs_write16(sf->selector, var->selector);
3187 else if (var->s)
3188 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3189 goto out;
653e3108 3190 }
1ecd50a9 3191
653e3108
AK		 3192 vmcs_writel(sf->base, var->base);
3193 vmcs_write32(sf->limit, var->limit);
3194 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3195
3196 /*
3197 * Fix the "Accessed" bit in AR field of segment registers for older
3198 * qemu binaries.
3199 * IA32 arch specifies that at the time of processor reset the
3200 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3201 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3202 * state vmexit when "unrestricted guest" mode is turned on.
3203 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3204 * tree. Newer qemu binaries with that qemu fix would not need this
3205 * kvm hack.
3206 */
3207 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3208 var->type |= 0x1; /* Accessed */
3a624e29 3209
f924d66d 3210 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3211
3212out:
98eb2f8b 3213 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3214}
3215
6aa8b732
AK		 3216static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3217{
2fb92db1 3218 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3219
3220 *db = (ar >> 14) & 1;
3221 *l = (ar >> 13) & 1;
3222}
3223
89a27f4d 3224static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3225{
89a27f4d
GN		 3226 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3227 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3228}
3229
89a27f4d 3230static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3231{
89a27f4d
GN		 3232 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3233 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3234}
3235
89a27f4d 3236static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3237{
89a27f4d
GN		 3238 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3239 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3240}
3241
89a27f4d 3242static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3243{
89a27f4d
GN		 3244 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3245 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3246}
3247
648dfaa7
MG		 3248static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3249{
3250 struct kvm_segment var;
3251 u32 ar;
3252
3253 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3254 var.dpl = 0x3;
0647f4aa
GN		 3255 if (seg == VCPU_SREG_CS)
3256 var.type = 0x3;
648dfaa7
MG		 3257 ar = vmx_segment_access_rights(&var);
3258
3259 if (var.base != (var.selector << 4))
3260 return false;
89efbed0 3261 if (var.limit != 0xffff)
648dfaa7 3262 return false;
07f42f5f 3263 if (ar != 0xf3)
648dfaa7
MG		 3264 return false;
3265
3266 return true;
3267}
3268
3269static bool code_segment_valid(struct kvm_vcpu *vcpu)
3270{
3271 struct kvm_segment cs;
3272 unsigned int cs_rpl;
3273
3274 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3275 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3276
1872a3f4
AK		 3277 if (cs.unusable)
3278 return false;
4d283ec9 3279 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3280 return false;
3281 if (!cs.s)
3282 return false;
4d283ec9 3283 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3284 if (cs.dpl > cs_rpl)
3285 return false;
1872a3f4 3286 } else {
648dfaa7
MG		 3287 if (cs.dpl != cs_rpl)
3288 return false;
3289 }
3290 if (!cs.present)
3291 return false;
3292
3293 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3294 return true;
3295}
3296
3297static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3298{
3299 struct kvm_segment ss;
3300 unsigned int ss_rpl;
3301
3302 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3303 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3304
1872a3f4
AK		 3305 if (ss.unusable)
3306 return true;
3307 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3308 return false;
3309 if (!ss.s)
3310 return false;
3311 if (ss.dpl != ss_rpl) /* DPL != RPL */
3312 return false;
3313 if (!ss.present)
3314 return false;
3315
3316 return true;
3317}
3318
3319static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3320{
3321 struct kvm_segment var;
3322 unsigned int rpl;
3323
3324 vmx_get_segment(vcpu, &var, seg);
b32a9918 3325 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3326
1872a3f4
AK		 3327 if (var.unusable)
3328 return true;
648dfaa7
MG		 3329 if (!var.s)
3330 return false;
3331 if (!var.present)
3332 return false;
4d283ec9 3333 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3334 if (var.dpl < rpl) /* DPL < RPL */
3335 return false;
3336 }
3337
3338 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3339 * rights flags
3340 */
3341 return true;
3342}
3343
3344static bool tr_valid(struct kvm_vcpu *vcpu)
3345{
3346 struct kvm_segment tr;
3347
3348 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3349
1872a3f4
AK		 3350 if (tr.unusable)
3351 return false;
b32a9918 3352 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3353 return false;
1872a3f4 3354 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3355 return false;
3356 if (!tr.present)
3357 return false;
3358
3359 return true;
3360}
3361
3362static bool ldtr_valid(struct kvm_vcpu *vcpu)
3363{
3364 struct kvm_segment ldtr;
3365
3366 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3367
1872a3f4
AK		 3368 if (ldtr.unusable)
3369 return true;
b32a9918 3370 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3371 return false;
3372 if (ldtr.type != 2)
3373 return false;
3374 if (!ldtr.present)
3375 return false;
3376
3377 return true;
3378}
3379
3380static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3381{
3382 struct kvm_segment cs, ss;
3383
3384 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3385 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3386
b32a9918
NA		 3387 return ((cs.selector & SEGMENT_RPL_MASK) ==
3388 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3389}
3390
3391/*
3392 * Check if guest state is valid. Returns true if valid, false if
3393 * not.
3394 * We assume that registers are always usable
3395 */
3396static bool guest_state_valid(struct kvm_vcpu *vcpu)
3397{
c5e97c80
GN		 3398 if (enable_unrestricted_guest)
3399 return true;
3400
648dfaa7 3401 /* real mode guest state checks */
f13882d8 3402 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3403 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3404 return false;
3405 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3406 return false;
3407 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3408 return false;
3409 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3410 return false;
3411 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3412 return false;
3413 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3414 return false;
3415 } else {
3416 /* protected mode guest state checks */
3417 if (!cs_ss_rpl_check(vcpu))
3418 return false;
3419 if (!code_segment_valid(vcpu))
3420 return false;
3421 if (!stack_segment_valid(vcpu))
3422 return false;
3423 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3424 return false;
3425 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3426 return false;
3427 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3428 return false;
3429 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3430 return false;
3431 if (!tr_valid(vcpu))
3432 return false;
3433 if (!ldtr_valid(vcpu))
3434 return false;
3435 }
3436 /* TODO:
3437 * - Add checks on RIP
3438 * - Add checks on RFLAGS
3439 */
3440
3441 return true;
3442}
3443
d77c26fc 3444static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3445{
40dcaa9f 3446 gfn_t fn;
195aefde 3447 u16 data = 0;
1f755a82 3448 int idx, r;
6aa8b732 3449
40dcaa9f 3450 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3451 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3452 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3453 if (r < 0)
10589a46 3454 goto out;
195aefde 3455 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3456 r = kvm_write_guest_page(kvm, fn++, &data,
3457 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3458 if (r < 0)
10589a46 3459 goto out;
195aefde
IE		 3460 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3461 if (r < 0)
10589a46 3462 goto out;
195aefde
IE		 3463 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3464 if (r < 0)
10589a46 3465 goto out;
195aefde 3466 data = ~0;
10589a46
MT		 3467 r = kvm_write_guest_page(kvm, fn, &data,
3468 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3469 sizeof(u8));
10589a46 3470out:
40dcaa9f 3471 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3472 return r;
6aa8b732
AK		 3473}
3474
b7ebfb05
SY		 3475static int init_rmode_identity_map(struct kvm *kvm)
3476{
40bbb9d0 3477 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
f51770ed 3478 int i, idx, r = 0;
ba049e93 3479 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3480 u32 tmp;
3481
40bbb9d0 3482 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3483 mutex_lock(&kvm->slots_lock);
3484
40bbb9d0 3485 if (likely(kvm_vmx->ept_identity_pagetable_done))
a255d479 3486 goto out2;
a255d479 3487
40bbb9d0
SC		 3488 if (!kvm_vmx->ept_identity_map_addr)
3489 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3490 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3491
d8a6e365 3492 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3493 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3494 if (r < 0)
a255d479
TC		 3495 goto out2;
3496
40dcaa9f 3497 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3498 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3499 if (r < 0)
3500 goto out;
3501 /* Set up identity-mapping pagetable for EPT in real mode */
3502 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3503 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3504 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3505 r = kvm_write_guest_page(kvm, identity_map_pfn,
3506 &tmp, i * sizeof(tmp), sizeof(tmp));
3507 if (r < 0)
3508 goto out;
3509 }
40bbb9d0 3510 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3511
b7ebfb05 3512out:
40dcaa9f 3513 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3514
3515out2:
3516 mutex_unlock(&kvm->slots_lock);
f51770ed 3517 return r;
b7ebfb05
SY		 3518}
3519
6aa8b732
AK		 3520static void seg_setup(int seg)
3521{
772e0318 3522 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3523 unsigned int ar;
6aa8b732
AK		 3524
3525 vmcs_write16(sf->selector, 0);
3526 vmcs_writel(sf->base, 0);
3527 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3528 ar = 0x93;
3529 if (seg == VCPU_SREG_CS)
3530 ar |= 0x08; /* code segment */
3a624e29
NK		 3531
3532 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3533}
3534
f78e0e2e
SY		 3535static int alloc_apic_access_page(struct kvm *kvm)
3536{
4484141a 3537 struct page *page;
f78e0e2e
SY		 3538 int r = 0;
3539
79fac95e 3540 mutex_lock(&kvm->slots_lock);
c24ae0dc 3541 if (kvm->arch.apic_access_page_done)
f78e0e2e 3542 goto out;
1d8007bd
PB		 3543 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3544 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3545 if (r)
3546 goto out;
72dc67a6 3547
73a6d941 3548 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3549 if (is_error_page(page)) {
3550 r = -EFAULT;
3551 goto out;
3552 }
3553
c24ae0dc
TC		 3554 /*
3555 * Do not pin the page in memory, so that memory hot-unplug
3556 * is able to migrate it.
3557 */
3558 put_page(page);
3559 kvm->arch.apic_access_page_done = true;
f78e0e2e 3560out:
79fac95e 3561 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3562 return r;
3563}
3564
97b7ead3 3565int allocate_vpid(void)
2384d2b3
SY		 3566{
3567 int vpid;
3568
919818ab 3569 if (!enable_vpid)
991e7a0e 3570 return 0;
2384d2b3
SY		 3571 spin_lock(&vmx_vpid_lock);
3572 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3573 if (vpid < VMX_NR_VPIDS)
2384d2b3 3574 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3575 else
3576 vpid = 0;
2384d2b3 3577 spin_unlock(&vmx_vpid_lock);
991e7a0e 3578 return vpid;
2384d2b3
SY		 3579}
3580
97b7ead3 3581void free_vpid(int vpid)
cdbecfc3 3582{
991e7a0e 3583 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3584 return;
3585 spin_lock(&vmx_vpid_lock);
991e7a0e 3586 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3587 spin_unlock(&vmx_vpid_lock);
3588}
3589
1e4329ee 3590static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3591 u32 msr, int type)
25c5f225 3592{
3e7c73e9 3593 int f = sizeof(unsigned long);
25c5f225
SY		 3594
3595 if (!cpu_has_vmx_msr_bitmap())
3596 return;
3597
ceef7d10
VK		 3598 if (static_branch_unlikely(&enable_evmcs))
3599 evmcs_touch_msr_bitmap();
3600
25c5f225
SY		 3601 /*
3602 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3603 * have the write-low and read-high bitmap offsets the wrong way round.
3604 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3605 */
25c5f225 3606 if (msr <= 0x1fff) {
8d14695f
YZ		 3607 if (type & MSR_TYPE_R)
3608 /* read-low */
3609 __clear_bit(msr, msr_bitmap + 0x000 / f);
3610
3611 if (type & MSR_TYPE_W)
3612 /* write-low */
3613 __clear_bit(msr, msr_bitmap + 0x800 / f);
3614
25c5f225
SY		 3615 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3616 msr &= 0x1fff;
8d14695f
YZ		 3617 if (type & MSR_TYPE_R)
3618 /* read-high */
3619 __clear_bit(msr, msr_bitmap + 0x400 / f);
3620
3621 if (type & MSR_TYPE_W)
3622 /* write-high */
3623 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3624
3625 }
3626}
3627
1e4329ee 3628static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3629 u32 msr, int type)
3630{
3631 int f = sizeof(unsigned long);
3632
3633 if (!cpu_has_vmx_msr_bitmap())
3634 return;
3635
ceef7d10
VK		 3636 if (static_branch_unlikely(&enable_evmcs))
3637 evmcs_touch_msr_bitmap();
3638
904e14fb
PB		 3639 /*
3640 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3641 * have the write-low and read-high bitmap offsets the wrong way round.
3642 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3643 */
3644 if (msr <= 0x1fff) {
3645 if (type & MSR_TYPE_R)
3646 /* read-low */
3647 __set_bit(msr, msr_bitmap + 0x000 / f);
3648
3649 if (type & MSR_TYPE_W)
3650 /* write-low */
3651 __set_bit(msr, msr_bitmap + 0x800 / f);
3652
3653 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3654 msr &= 0x1fff;
3655 if (type & MSR_TYPE_R)
3656 /* read-high */
3657 __set_bit(msr, msr_bitmap + 0x400 / f);
3658
3659 if (type & MSR_TYPE_W)
3660 /* write-high */
3661 __set_bit(msr, msr_bitmap + 0xc00 / f);
3662
3663 }
3664}
3665
1e4329ee 3666static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3667 u32 msr, int type, bool value)
3668{
3669 if (value)
3670 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3671 else
3672 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3673}
3674
904e14fb 3675static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3676{
904e14fb
PB		 3677 u8 mode = 0;
3678
3679 if (cpu_has_secondary_exec_ctrls() &&
fe7f895d 3680 (secondary_exec_controls_get(to_vmx(vcpu)) &
904e14fb
PB		 3681 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3682 mode |= MSR_BITMAP_MODE_X2APIC;
3683 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3684 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3685 }
3686
904e14fb 3687 return mode;
8d14695f
YZ		 3688}
3689
904e14fb
PB		 3690static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3691 u8 mode)
8d14695f 3692{
904e14fb
PB		 3693 int msr;
3694
3695 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3696 unsigned word = msr / BITS_PER_LONG;
3697 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3698 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3699 }
3700
3701 if (mode & MSR_BITMAP_MODE_X2APIC) {
3702 /*
3703 * TPR reads and writes can be virtualized even if virtual interrupt
3704 * delivery is not in use.
3705 */
3706 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3707 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3708 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3709 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3710 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3711 }
f6e90f9e 3712 }
5897297b
AK		 3713}
3714
97b7ead3 3715void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3716{
3717 struct vcpu_vmx *vmx = to_vmx(vcpu);
3718 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3719 u8 mode = vmx_msr_bitmap_mode(vcpu);
3720 u8 changed = mode ^ vmx->msr_bitmap_mode;
3721
3722 if (!changed)
3723 return;
3724
904e14fb
PB		 3725 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3726 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3727
3728 vmx->msr_bitmap_mode = mode;
3729}
3730
b08c2896
CP		 3731void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3732{
3733 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3734 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3735 u32 i;
3736
3737 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3738 MSR_TYPE_RW, flag);
3739 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3740 MSR_TYPE_RW, flag);
3741 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3742 MSR_TYPE_RW, flag);
3743 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3744 MSR_TYPE_RW, flag);
3745 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3746 vmx_set_intercept_for_msr(msr_bitmap,
3747 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3748 vmx_set_intercept_for_msr(msr_bitmap,
3749 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3750 }
3751}
3752
2cf9af0b 3753static bool vmx_get_enable_apicv(struct kvm *kvm)
d50ab6c1 3754{
d62caabb 3755 return enable_apicv;
d50ab6c1
PB		 3756}
3757
e6c67d8c
LA		 3758static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3759{
3760 struct vcpu_vmx *vmx = to_vmx(vcpu);
3761 void *vapic_page;
3762 u32 vppr;
3763 int rvi;
3764
3765 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3766 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
96c66e87 3767 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
e6c67d8c
LA		 3768 return false;
3769
7e712684 3770 rvi = vmx_get_rvi();
e6c67d8c 3771
96c66e87 3772 vapic_page = vmx->nested.virtual_apic_map.hva;
e6c67d8c 3773 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
e6c67d8c
LA		 3774
3775 return ((rvi & 0xf0) > (vppr & 0xf0));
3776}
3777
06a5524f
WV		 3778static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3779 bool nested)
21bc8dc5
RK		 3780{
3781#ifdef CONFIG_SMP
06a5524f
WV		 3782 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3783
21bc8dc5 3784 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3785 /*
5753743f
HZ		 3786 * The vector of interrupt to be delivered to vcpu had
3787 * been set in PIR before this function.
3788 *
3789 * Following cases will be reached in this block, and
3790 * we always send a notification event in all cases as
3791 * explained below.
3792 *
3793 * Case 1: vcpu keeps in non-root mode. Sending a
3794 * notification event posts the interrupt to vcpu.
3795 *
3796 * Case 2: vcpu exits to root mode and is still
3797 * runnable. PIR will be synced to vIRR before the
3798 * next vcpu entry. Sending a notification event in
3799 * this case has no effect, as vcpu is not in root
3800 * mode.
28b835d6 3801 *
5753743f
HZ		 3802 * Case 3: vcpu exits to root mode and is blocked.
3803 * vcpu_block() has already synced PIR to vIRR and
3804 * never blocks vcpu if vIRR is not cleared. Therefore,
3805 * a blocked vcpu here does not wait for any requested
3806 * interrupts in PIR, and sending a notification event
3807 * which has no effect is safe here.
28b835d6 3808 */
28b835d6 3809
06a5524f 3810 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3811 return true;
3812 }
3813#endif
3814 return false;
3815}
3816
705699a1
WV		 3817static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3818 int vector)
3819{
3820 struct vcpu_vmx *vmx = to_vmx(vcpu);
3821
3822 if (is_guest_mode(vcpu) &&
3823 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3824 /*
3825 * If a posted intr is not recognized by hardware,
3826 * we will accomplish it in the next vmentry.
3827 */
3828 vmx->nested.pi_pending = true;
3829 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3830 /* the PIR and ON have been set by L1. */
3831 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3832 kvm_vcpu_kick(vcpu);
705699a1
WV		 3833 return 0;
3834 }
3835 return -1;
3836}
a20ed54d
YZ		 3837/*
3838 * Send interrupt to vcpu via posted interrupt way.
3839 * 1. If target vcpu is running(non-root mode), send posted interrupt
3840 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3841 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3842 * interrupt from PIR in next vmentry.
3843 */
3844static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3845{
3846 struct vcpu_vmx *vmx = to_vmx(vcpu);
3847 int r;
3848
705699a1
WV		 3849 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3850 if (!r)
3851 return;
3852
a20ed54d
YZ		 3853 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3854 return;
3855
b95234c8
PB		 3856 /* If a previous notification has sent the IPI, nothing to do. */
3857 if (pi_test_and_set_on(&vmx->pi_desc))
3858 return;
3859
06a5524f 3860 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ		 3861 kvm_vcpu_kick(vcpu);
3862}
3863
a3a8ff8e
NHE		 3864/*
3865 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3866 * will not change in the lifetime of the guest.
3867 * Note that host-state that does change is set elsewhere. E.g., host-state
3868 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3869 */
97b7ead3 3870void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3871{
3872 u32 low32, high32;
3873 unsigned long tmpl;
d6e41f11 3874 unsigned long cr0, cr3, cr4;
a3a8ff8e 3875
04ac88ab
AL		 3876 cr0 = read_cr0();
3877 WARN_ON(cr0 & X86_CR0_TS);
3878 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3879
3880 /*
3881 * Save the most likely value for this task's CR3 in the VMCS.
3882 * We can't use __get_current_cr3_fast() because we're not atomic.
3883 */
6c690ee1 3884 cr3 = __read_cr3();
d6e41f11 3885 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3886 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3887
d974baa3 3888 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3889 cr4 = cr4_read_shadow();
d974baa3 3890 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3891 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3892
a3a8ff8e 3893 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3894#ifdef CONFIG_X86_64
3895 /*
3896 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3897 * vmx_prepare_switch_to_host(), in case userspace uses
3898 * the null selectors too (the expected case).
b2da15ac
AK		 3899 */
3900 vmcs_write16(HOST_DS_SELECTOR, 0);
3901 vmcs_write16(HOST_ES_SELECTOR, 0);
3902#else
a3a8ff8e
NHE		 3903 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3904 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3905#endif
a3a8ff8e
NHE		 3906 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3907 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3908
2342080c 3909 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
a3a8ff8e 3910
453eafbe 3911 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3912
3913 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3914 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3915 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3916 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3917
3918 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3919 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3920 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3921 }
5a5e8a15 3922
c73da3fc 3923 if (cpu_has_load_ia32_efer())
5a5e8a15 3924 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3925}
3926
97b7ead3 3927void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3928{
3929 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3930 if (enable_ept)
3931 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3932 if (is_guest_mode(&vmx->vcpu))
3933 vmx->vcpu.arch.cr4_guest_owned_bits &=
3934 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3935 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3936}
3937
c075c3e4 3938u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
01e439be
YZ		 3939{
3940 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3941
d62caabb 3942 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3943 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3944
3945 if (!enable_vnmi)
3946 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3947
804939ea
SC		 3948 if (!enable_preemption_timer)
3949 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3950
01e439be
YZ		 3951 return pin_based_exec_ctrl;
3952}
3953
d62caabb
AS		 3954static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3955{
3956 struct vcpu_vmx *vmx = to_vmx(vcpu);
3957
c5f2c766 3958 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3959 if (cpu_has_secondary_exec_ctrls()) {
3960 if (kvm_vcpu_apicv_active(vcpu))
fe7f895d 3961 secondary_exec_controls_setbit(vmx,
3ce424e4
RK		 3962 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3963 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3964 else
fe7f895d 3965 secondary_exec_controls_clearbit(vmx,
3ce424e4
RK		 3966 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3967 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3968 }
3969
3970 if (cpu_has_vmx_msr_bitmap())
904e14fb 3971 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3972}
3973
89b0c9f5
SC		 3974u32 vmx_exec_control(struct vcpu_vmx *vmx)
3975{
3976 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3977
3978 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3979 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3980
3981 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3982 exec_control &= ~CPU_BASED_TPR_SHADOW;
3983#ifdef CONFIG_X86_64
3984 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3985 CPU_BASED_CR8_LOAD_EXITING;
3986#endif
3987 }
3988 if (!enable_ept)
3989 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3990 CPU_BASED_CR3_LOAD_EXITING |
3991 CPU_BASED_INVLPG_EXITING;
3992 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3993 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3994 CPU_BASED_MONITOR_EXITING);
3995 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3996 exec_control &= ~CPU_BASED_HLT_EXITING;
3997 return exec_control;
3998}
3999
4000
80154d77 4001static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 4002{
80154d77
PB		 4003 struct kvm_vcpu *vcpu = &vmx->vcpu;
4004
bf8179a0 4005 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 4006
f99e3daf
CP		 4007 if (pt_mode == PT_MODE_SYSTEM)
4008 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 4009 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 4010 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4011 if (vmx->vpid == 0)
4012 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4013 if (!enable_ept) {
4014 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4015 enable_unrestricted_guest = 0;
4016 }
4017 if (!enable_unrestricted_guest)
4018 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 4019 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 4020 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 4021 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 4022 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4023 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4024 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 4025
4026 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4027 * in vmx_set_cr4. */
4028 exec_control &= ~SECONDARY_EXEC_DESC;
4029
abc4fc58
AG		 4030 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4031 (handle_vmptrld).
4032 We can NOT enable shadow_vmcs here because we don't have yet
4033 a current VMCS12
4034 */
4035 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 4036
4037 if (!enable_pml)
4038 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 4039
3db13480
PB		 4040 if (vmx_xsaves_supported()) {
4041 /* Exposing XSAVES only when XSAVE is exposed */
4042 bool xsaves_enabled =
4043 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4044 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4045
7204160e
AL		 4046 vcpu->arch.xsaves_enabled = xsaves_enabled;
4047
3db13480
PB		 4048 if (!xsaves_enabled)
4049 exec_control &= ~SECONDARY_EXEC_XSAVES;
4050
4051 if (nested) {
4052 if (xsaves_enabled)
6677f3da 4053 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 4054 SECONDARY_EXEC_XSAVES;
4055 else
6677f3da 4056 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 4057 ~SECONDARY_EXEC_XSAVES;
4058 }
4059 }
4060
80154d77
PB		 4061 if (vmx_rdtscp_supported()) {
4062 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4063 if (!rdtscp_enabled)
4064 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4065
4066 if (nested) {
4067 if (rdtscp_enabled)
6677f3da 4068 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4069 SECONDARY_EXEC_RDTSCP;
4070 else
6677f3da 4071 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4072 ~SECONDARY_EXEC_RDTSCP;
4073 }
4074 }
4075
4076 if (vmx_invpcid_supported()) {
4077 /* Exposing INVPCID only when PCID is exposed */
4078 bool invpcid_enabled =
4079 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4080 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4081
4082 if (!invpcid_enabled) {
4083 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4084 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4085 }
4086
4087 if (nested) {
4088 if (invpcid_enabled)
6677f3da 4089 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4090 SECONDARY_EXEC_ENABLE_INVPCID;
4091 else
6677f3da 4092 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4093 ~SECONDARY_EXEC_ENABLE_INVPCID;
4094 }
4095 }
4096
45ec368c
JM		 4097 if (vmx_rdrand_supported()) {
4098 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4099 if (rdrand_enabled)
736fdf72 4100 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4101
4102 if (nested) {
4103 if (rdrand_enabled)
6677f3da 4104 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4105 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 4106 else
6677f3da 4107 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4108 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4109 }
4110 }
4111
75f4fc8d
JM		 4112 if (vmx_rdseed_supported()) {
4113 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4114 if (rdseed_enabled)
736fdf72 4115 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4116
4117 if (nested) {
4118 if (rdseed_enabled)
6677f3da 4119 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4120 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 4121 else
6677f3da 4122 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4123 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4124 }
4125 }
4126
e69e72fa
TX		 4127 if (vmx_waitpkg_supported()) {
4128 bool waitpkg_enabled =
4129 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4130
4131 if (!waitpkg_enabled)
4132 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4133
4134 if (nested) {
4135 if (waitpkg_enabled)
4136 vmx->nested.msrs.secondary_ctls_high |=
4137 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4138 else
4139 vmx->nested.msrs.secondary_ctls_high &=
4140 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4141 }
4142 }
4143
80154d77 4144 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 4145}
4146
ce88decf
XG		 4147static void ept_set_mmio_spte_mask(void)
4148{
4149 /*
4150 * EPT Misconfigurations can be generated if the value of bits 2:0
4151 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 4152 */
dcdca5fe 4153 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4af77151 4154 VMX_EPT_MISCONFIG_WX_VALUE, 0);
ce88decf
XG		 4155}
4156
f53cd63c 4157#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 4158
944c3464 4159/*
1b84292b
XL		 4160 * Noting that the initialization of Guest-state Area of VMCS is in
4161 * vmx_vcpu_reset().
944c3464 4162 */
1b84292b 4163static void init_vmcs(struct vcpu_vmx *vmx)
944c3464 4164{
944c3464 4165 if (nested)
1b84292b 4166 nested_vmx_set_vmcs_shadowing_bitmap();
944c3464 4167
25c5f225 4168 if (cpu_has_vmx_msr_bitmap())
904e14fb 4169 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4170
6aa8b732
AK		 4171 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4172
6aa8b732 4173 /* Control */
3af80fec 4174 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4175
3af80fec 4176 exec_controls_set(vmx, vmx_exec_control(vmx));
6aa8b732 4177
dfa169bb 4178 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4179 vmx_compute_secondary_exec_control(vmx);
3af80fec 4180 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
dfa169bb 4181 }
f78e0e2e 4182
d62caabb 4183 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4184 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4185 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4186 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4187 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4188
4189 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4190
0bcf261c 4191 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4192 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4193 }
4194
b31c114b 4195 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4196 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4197 vmx->ple_window = ple_window;
4198 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4199 }
4200
c3707958
XG		 4201 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4202 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4203 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4204
9581d442
AK		 4205 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4206 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4207 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4208 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4209 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4210
2a499e49
BD		 4211 if (cpu_has_vmx_vmfunc())
4212 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4213
2cc51560
ED		 4214 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4215 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4216 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4217 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4218 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4219
74545705
RK		 4220 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4221 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4222
3af80fec 4223 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4224
4225 /* 22.2.1, 20.8.1 */
3af80fec 4226 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
1c3d14fe 4227
bd7e5b08
PB		 4228 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4229 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4230
bf8179a0 4231 set_cr4_guest_host_mask(vmx);
e00c8cf2 4232
35fbe0d4
XL		 4233 if (vmx->vpid != 0)
4234 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4235
f53cd63c
WL		 4236 if (vmx_xsaves_supported())
4237 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4238
4e59516a 4239 if (enable_pml) {
4e59516a
PF		 4240 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4241 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4242 }
0b665d30
SC		 4243
4244 if (cpu_has_vmx_encls_vmexit())
4245 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4246
4247 if (pt_mode == PT_MODE_HOST_GUEST) {
4248 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4249 /* Bit[6~0] are forced to 1, writes are ignored. */
4250 vmx->pt_desc.guest.output_mask = 0x7F;
4251 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4252 }
e00c8cf2
AK		 4253}
4254
d28bc9dd 4255static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4256{
4257 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4258 struct msr_data apic_base_msr;
d28bc9dd 4259 u64 cr0;
e00c8cf2 4260
7ffd92c5 4261 vmx->rmode.vm86_active = 0;
d28b387f 4262 vmx->spec_ctrl = 0;
e00c8cf2 4263
6e3ba4ab
TX		 4264 vmx->msr_ia32_umwait_control = 0;
4265
518e7b94 4266 vcpu->arch.microcode_version = 0x100000000ULL;
ad312c7c 4267 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
95c06540 4268 vmx->hv_deadline_tsc = -1;
d28bc9dd
NA		 4269 kvm_set_cr8(vcpu, 0);
4270
4271 if (!init_event) {
4272 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4273 MSR_IA32_APICBASE_ENABLE;
4274 if (kvm_vcpu_is_reset_bsp(vcpu))
4275 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4276 apic_base_msr.host_initiated = true;
4277 kvm_set_apic_base(vcpu, &apic_base_msr);
4278 }
e00c8cf2 4279
2fb92db1
AK		 4280 vmx_segment_cache_clear(vmx);
4281
5706be0d 4282 seg_setup(VCPU_SREG_CS);
66450a21 4283 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4284 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4285
4286 seg_setup(VCPU_SREG_DS);
4287 seg_setup(VCPU_SREG_ES);
4288 seg_setup(VCPU_SREG_FS);
4289 seg_setup(VCPU_SREG_GS);
4290 seg_setup(VCPU_SREG_SS);
4291
4292 vmcs_write16(GUEST_TR_SELECTOR, 0);
4293 vmcs_writel(GUEST_TR_BASE, 0);
4294 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4295 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4296
4297 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4298 vmcs_writel(GUEST_LDTR_BASE, 0);
4299 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4300 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4301
d28bc9dd
NA		 4302 if (!init_event) {
4303 vmcs_write32(GUEST_SYSENTER_CS, 0);
4304 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4305 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4306 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4307 }
e00c8cf2 4308
c37c2873 4309 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4310 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4311
e00c8cf2
AK		 4312 vmcs_writel(GUEST_GDTR_BASE, 0);
4313 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4314
4315 vmcs_writel(GUEST_IDTR_BASE, 0);
4316 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4317
443381a8 4318 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4319 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4320 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4321 if (kvm_mpx_supported())
4322 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4323
e00c8cf2
AK		 4324 setup_msrs(vmx);
4325
6aa8b732
AK		 4326 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4327
d28bc9dd 4328 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4329 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4330 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4331 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4332 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4333 vmcs_write32(TPR_THRESHOLD, 0);
4334 }
4335
a73896cb 4336 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4337
d28bc9dd 4338 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4339 vmx->vcpu.arch.cr0 = cr0;
f2463247 4340 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4341 vmx_set_cr4(vcpu, 0);
5690891b 4342 vmx_set_efer(vcpu, 0);
bd7e5b08 4343
d28bc9dd 4344 update_exception_bitmap(vcpu);
6aa8b732 4345
dd5f5341 4346 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4347 if (init_event)
4348 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4349}
4350
55d2375e 4351static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4352{
9dadc2f9 4353 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
3b86cd99
JK		 4354}
4355
c9a7953f 4356static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4357{
d02fcf50 4358 if (!enable_vnmi ||
8a1b4392 4359 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4360 enable_irq_window(vcpu);
4361 return;
4362 }
3b86cd99 4363
4e2a0bc5 4364 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
3b86cd99
JK		 4365}
4366
66fd3f7f 4367static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4368{
9c8cba37 4369 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4370 uint32_t intr;
4371 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4372
229456fc 4373 trace_kvm_inj_virq(irq);
2714d1d3 4374
fa89a817 4375 ++vcpu->stat.irq_injections;
7ffd92c5 4376 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4377 int inc_eip = 0;
4378 if (vcpu->arch.interrupt.soft)
4379 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 4380 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
85f455f7
ED		 4381 return;
4382 }
66fd3f7f
GN		 4383 intr = irq | INTR_INFO_VALID_MASK;
4384 if (vcpu->arch.interrupt.soft) {
4385 intr |= INTR_TYPE_SOFT_INTR;
4386 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4387 vmx->vcpu.arch.event_exit_inst_len);
4388 } else
4389 intr |= INTR_TYPE_EXT_INTR;
4390 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4391
4392 vmx_clear_hlt(vcpu);
85f455f7
ED		 4393}
4394
f08864b4
SY		 4395static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4396{
66a5a347
JK		 4397 struct vcpu_vmx *vmx = to_vmx(vcpu);
4398
d02fcf50 4399 if (!enable_vnmi) {
8a1b4392
PB		 4400 /*
4401 * Tracking the NMI-blocked state in software is built upon
4402 * finding the next open IRQ window. This, in turn, depends on
4403 * well-behaving guests: They have to keep IRQs disabled at
4404 * least as long as the NMI handler runs. Otherwise we may
4405 * cause NMI nesting, maybe breaking the guest. But as this is
4406 * highly unlikely, we can live with the residual risk.
4407 */
4408 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4409 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4410 }
4411
4c4a6f79
PB		 4412 ++vcpu->stat.nmi_injections;
4413 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4414
7ffd92c5 4415 if (vmx->rmode.vm86_active) {
9497e1f2 4416 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
66a5a347
JK		 4417 return;
4418 }
c5a6d5f7 4419
f08864b4
SY		 4420 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4421 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4422
4423 vmx_clear_hlt(vcpu);
f08864b4
SY		 4424}
4425
97b7ead3 4426bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4427{
4c4a6f79
PB		 4428 struct vcpu_vmx *vmx = to_vmx(vcpu);
4429 bool masked;
4430
d02fcf50 4431 if (!enable_vnmi)
8a1b4392 4432 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4433 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4434 return false;
4c4a6f79
PB		 4435 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4436 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4437 return masked;
3cfc3092
JK		 4438}
4439
97b7ead3 4440void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4441{
4442 struct vcpu_vmx *vmx = to_vmx(vcpu);
4443
d02fcf50 4444 if (!enable_vnmi) {
8a1b4392
PB		 4445 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4446 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4447 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4448 }
4449 } else {
4450 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4451 if (masked)
4452 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4453 GUEST_INTR_STATE_NMI);
4454 else
4455 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4456 GUEST_INTR_STATE_NMI);
4457 }
3cfc3092
JK		 4458}
4459
2505dc9f
JK		 4460static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4461{
b6b8a145
JK		 4462 if (to_vmx(vcpu)->nested.nested_run_pending)
4463 return 0;
ea8ceb83 4464
d02fcf50 4465 if (!enable_vnmi &&
8a1b4392
PB		 4466 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4467 return 0;
4468
2505dc9f
JK		 4469 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4470 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4471 | GUEST_INTR_STATE_NMI));
4472}
4473
78646121
GN		 4474static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4475{
b6b8a145
JK		 4476 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4477 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4478 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4479 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4480}
4481
cbc94022
IE		 4482static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4483{
4484 int ret;
cbc94022 4485
f7eaeb0a
SC		 4486 if (enable_unrestricted_guest)
4487 return 0;
4488
1d8007bd
PB		 4489 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4490 PAGE_SIZE * 3);
cbc94022
IE		 4491 if (ret)
4492 return ret;
40bbb9d0 4493 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4494 return init_rmode_tss(kvm);
cbc94022
IE		 4495}
4496
2ac52ab8
SC		 4497static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4498{
40bbb9d0 4499 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4500 return 0;
4501}
4502
0ca1b4f4 4503static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4504{
77ab6db0 4505 switch (vec) {
77ab6db0 4506 case BP_VECTOR:
c573cd22
JK		 4507 /*
4508 * Update instruction length as we may reinject the exception
4509 * from user space while in guest debugging mode.
4510 */
4511 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4512 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4513 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4514 return false;
4515 /* fall through */
4516 case DB_VECTOR:
4517 if (vcpu->guest_debug &
4518 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4519 return false;
d0bfb940
JK		 4520 /* fall through */
4521 case DE_VECTOR:
77ab6db0
JK		 4522 case OF_VECTOR:
4523 case BR_VECTOR:
4524 case UD_VECTOR:
4525 case DF_VECTOR:
4526 case SS_VECTOR:
4527 case GP_VECTOR:
4528 case MF_VECTOR:
0ca1b4f4
GN		 4529 return true;
4530 break;
77ab6db0 4531 }
0ca1b4f4
GN		 4532 return false;
4533}
4534
4535static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4536 int vec, u32 err_code)
4537{
4538 /*
4539 * Instruction with address size override prefix opcode 0x67
4540 * Cause the #SS fault with 0 error code in VM86 mode.
4541 */
4542 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
60fc3d02 4543 if (kvm_emulate_instruction(vcpu, 0)) {
0ca1b4f4
GN		 4544 if (vcpu->arch.halt_request) {
4545 vcpu->arch.halt_request = 0;
5cb56059 4546 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4547 }
4548 return 1;
4549 }
4550 return 0;
4551 }
4552
4553 /*
4554 * Forward all other exceptions that are valid in real mode.
4555 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4556 * the required debugging infrastructure rework.
4557 */
4558 kvm_queue_exception(vcpu, vec);
4559 return 1;
6aa8b732
AK		 4560}
4561
a0861c02
AK		 4562/*
4563 * Trigger machine check on the host. We assume all the MSRs are already set up
4564 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4565 * We pass a fake environment to the machine check handler because we want
4566 * the guest to be always treated like user space, no matter what context
4567 * it used internally.
4568 */
4569static void kvm_machine_check(void)
4570{
4571#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4572 struct pt_regs regs = {
4573 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4574 .flags = X86_EFLAGS_IF,
4575 };
4576
4577 do_machine_check(&regs, 0);
4578#endif
4579}
4580
851ba692 4581static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02 4582{
95b5a48c 4583 /* handled by vmx_vcpu_run() */
a0861c02
AK		 4584 return 1;
4585}
4586
95b5a48c 4587static int handle_exception_nmi(struct kvm_vcpu *vcpu)
6aa8b732 4588{
1155f76a 4589 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4590 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4591 u32 intr_info, ex_no, error_code;
42dbaa5a 4592 unsigned long cr2, rip, dr6;
6aa8b732 4593 u32 vect_info;
6aa8b732 4594
1155f76a 4595 vect_info = vmx->idt_vectoring_info;
88786475 4596 intr_info = vmx->exit_intr_info;
6aa8b732 4597
2ea72039 4598 if (is_machine_check(intr_info) || is_nmi(intr_info))
95b5a48c 4599 return 1; /* handled by handle_exception_nmi_irqoff() */
2ab455cc 4600
082d06ed
WL		 4601 if (is_invalid_opcode(intr_info))
4602 return handle_ud(vcpu);
7aa81cc0 4603
6aa8b732 4604 error_code = 0;
2e11384c 4605 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4606 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4607
9e869480
LA		 4608 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4609 WARN_ON_ONCE(!enable_vmware_backdoor);
a6c6ed1e
SC		 4610
4611 /*
4612 * VMware backdoor emulation on #GP interception only handles
4613 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4614 * error code on #GP.
4615 */
4616 if (error_code) {
4617 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4618 return 1;
4619 }
60fc3d02 4620 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9e869480
LA		 4621 }
4622
bf4ca23e
XG		 4623 /*
4624 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4625 * MMIO, it is better to report an internal error.
4626 * See the comments in vmx_handle_exit.
4627 */
4628 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4629 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4630 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4631 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4632 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4633 vcpu->run->internal.data[0] = vect_info;
4634 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4635 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4636 return 0;
4637 }
4638
6aa8b732
AK		 4639 if (is_page_fault(intr_info)) {
4640 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4641 /* EPT won't cause page fault directly */
4642 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4643 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4644 }
4645
d0bfb940 4646 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4647
4648 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4649 return handle_rmode_exception(vcpu, ex_no, error_code);
4650
42dbaa5a 4651 switch (ex_no) {
54a20552
EN		 4652 case AC_VECTOR:
4653 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4654 return 1;
42dbaa5a
JK		 4655 case DB_VECTOR:
4656 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4657 if (!(vcpu->guest_debug &
4658 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1fc5d194 4659 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4660 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4661 if (is_icebp(intr_info))
1957aa63 4662 WARN_ON(!skip_emulated_instruction(vcpu));
fd2a445a 4663
42dbaa5a
JK		 4664 kvm_queue_exception(vcpu, DB_VECTOR);
4665 return 1;
4666 }
4667 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4668 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4669 /* fall through */
4670 case BP_VECTOR:
c573cd22
JK		 4671 /*
4672 * Update instruction length as we may reinject #BP from
4673 * user space while in guest debugging mode. Reading it for
4674 * #DB as well causes no harm, it is not used in that case.
4675 */
4676 vmx->vcpu.arch.event_exit_inst_len =
4677 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4678 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4679 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4680 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4681 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4682 break;
4683 default:
d0bfb940
JK		 4684 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4685 kvm_run->ex.exception = ex_no;
4686 kvm_run->ex.error_code = error_code;
42dbaa5a 4687 break;
6aa8b732 4688 }
6aa8b732
AK		 4689 return 0;
4690}
4691
f399e60c 4692static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4693{
1165f5fe 4694 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4695 return 1;
4696}
4697
851ba692 4698static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4699{
851ba692 4700 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4701 vcpu->mmio_needed = 0;
988ad74f
AK		 4702 return 0;
4703}
6aa8b732 4704
851ba692 4705static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4706{
bfdaab09 4707 unsigned long exit_qualification;
dca7f128 4708 int size, in, string;
039576c0 4709 unsigned port;
6aa8b732 4710
bfdaab09 4711 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4712 string = (exit_qualification & 16) != 0;
e70669ab 4713
cf8f70bf 4714 ++vcpu->stat.io_exits;
e70669ab 4715
432baf60 4716 if (string)
60fc3d02 4717 return kvm_emulate_instruction(vcpu, 0);
e70669ab 4718
cf8f70bf
GN		 4719 port = exit_qualification >> 16;
4720 size = (exit_qualification & 7) + 1;
432baf60 4721 in = (exit_qualification & 8) != 0;
cf8f70bf 4722
dca7f128 4723 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4724}
4725
102d8325
IM		 4726static void
4727vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4728{
4729 /*
4730 * Patch in the VMCALL instruction:
4731 */
4732 hypercall[0] = 0x0f;
4733 hypercall[1] = 0x01;
4734 hypercall[2] = 0xc1;
102d8325
IM		 4735}
4736
0fa06071 4737/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4738static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4739{
eeadf9e7 4740 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4741 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4742 unsigned long orig_val = val;
4743
eeadf9e7
NHE		 4744 /*
4745 * We get here when L2 changed cr0 in a way that did not change
4746 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4747 * but did change L0 shadowed bits. So we first calculate the
4748 * effective cr0 value that L1 would like to write into the
4749 * hardware. It consists of the L2-owned bits from the new
4750 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4751 */
1a0d74e6
JK		 4752 val = (val & ~vmcs12->cr0_guest_host_mask) |
4753 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4754
3899152c 4755 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4756 return 1;
1a0d74e6
JK		 4757
4758 if (kvm_set_cr0(vcpu, val))
4759 return 1;
4760 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4761 return 0;
1a0d74e6
JK		 4762 } else {
4763 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4764 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4765 return 1;
3899152c 4766
eeadf9e7 4767 return kvm_set_cr0(vcpu, val);
1a0d74e6 4768 }
eeadf9e7
NHE		 4769}
4770
4771static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4772{
4773 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4774 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4775 unsigned long orig_val = val;
4776
4777 /* analogously to handle_set_cr0 */
4778 val = (val & ~vmcs12->cr4_guest_host_mask) |
4779 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4780 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4781 return 1;
1a0d74e6 4782 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4783 return 0;
4784 } else
4785 return kvm_set_cr4(vcpu, val);
4786}
4787
0367f205
PB		 4788static int handle_desc(struct kvm_vcpu *vcpu)
4789{
4790 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
60fc3d02 4791 return kvm_emulate_instruction(vcpu, 0);
0367f205
PB		 4792}
4793
851ba692 4794static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4795{
229456fc 4796 unsigned long exit_qualification, val;
6aa8b732
AK		 4797 int cr;
4798 int reg;
49a9b07e 4799 int err;
6affcbed 4800 int ret;
6aa8b732 4801
bfdaab09 4802 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4803 cr = exit_qualification & 15;
4804 reg = (exit_qualification >> 8) & 15;
4805 switch ((exit_qualification >> 4) & 3) {
4806 case 0: /* mov to cr */
1e32c079 4807 val = kvm_register_readl(vcpu, reg);
229456fc 4808 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4809 switch (cr) {
4810 case 0:
eeadf9e7 4811 err = handle_set_cr0(vcpu, val);
6affcbed 4812 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4813 case 3:
e1de91cc 4814 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4815 err = kvm_set_cr3(vcpu, val);
6affcbed 4816 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4817 case 4:
eeadf9e7 4818 err = handle_set_cr4(vcpu, val);
6affcbed 4819 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4820 case 8: {
4821 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4822 u8 cr8 = (u8)val;
eea1cff9 4823 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4824 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4825 if (lapic_in_kernel(vcpu))
6affcbed 4826 return ret;
0a5fff19 4827 if (cr8_prev <= cr8)
6affcbed
KH		 4828 return ret;
4829 /*
4830 * TODO: we might be squashing a
4831 * KVM_GUESTDBG_SINGLESTEP-triggered
4832 * KVM_EXIT_DEBUG here.
4833 */
851ba692 4834 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4835 return 0;
4836 }
4b8073e4 4837 }
6aa8b732 4838 break;
25c4c276 4839 case 2: /* clts */
bd7e5b08
PB		 4840 WARN_ONCE(1, "Guest should always own CR0.TS");
4841 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4842 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4843 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4844 case 1: /*mov from cr*/
4845 switch (cr) {
4846 case 3:
e1de91cc 4847 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4848 val = kvm_read_cr3(vcpu);
4849 kvm_register_write(vcpu, reg, val);
4850 trace_kvm_cr_read(cr, val);
6affcbed 4851 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4852 case 8:
229456fc
MT		 4853 val = kvm_get_cr8(vcpu);
4854 kvm_register_write(vcpu, reg, val);
4855 trace_kvm_cr_read(cr, val);
6affcbed 4856 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4857 }
4858 break;
4859 case 3: /* lmsw */
a1f83a74 4860 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4861 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4862 kvm_lmsw(vcpu, val);
6aa8b732 4863
6affcbed 4864 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4865 default:
4866 break;
4867 }
851ba692 4868 vcpu->run->exit_reason = 0;
a737f256 4869 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4870 (int)(exit_qualification >> 4) & 3, cr);
4871 return 0;
4872}
4873
851ba692 4874static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4875{
bfdaab09 4876 unsigned long exit_qualification;
16f8a6f9
NA		 4877 int dr, dr7, reg;
4878
4879 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4880 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4881
4882 /* First, if DR does not exist, trigger UD */
4883 if (!kvm_require_dr(vcpu, dr))
4884 return 1;
6aa8b732 4885
f2483415 4886 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4887 if (!kvm_require_cpl(vcpu, 0))
4888 return 1;
16f8a6f9
NA		 4889 dr7 = vmcs_readl(GUEST_DR7);
4890 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4891 /*
4892 * As the vm-exit takes precedence over the debug trap, we
4893 * need to emulate the latter, either for the host or the
4894 * guest debugging itself.
4895 */
4896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4897 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4898 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4899 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4900 vcpu->run->debug.arch.exception = DB_VECTOR;
4901 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4902 return 0;
4903 } else {
1fc5d194 4904 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4905 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4906 kvm_queue_exception(vcpu, DB_VECTOR);
4907 return 1;
4908 }
4909 }
4910
81908bf4 4911 if (vcpu->guest_debug == 0) {
2183f564 4912 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4913
4914 /*
4915 * No more DR vmexits; force a reload of the debug registers
4916 * and reenter on this instruction. The next vmexit will
4917 * retrieve the full state of the debug registers.
4918 */
4919 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4920 return 1;
4921 }
4922
42dbaa5a
JK		 4923 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4924 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4925 unsigned long val;
4c4d563b
JK		 4926
4927 if (kvm_get_dr(vcpu, dr, &val))
4928 return 1;
4929 kvm_register_write(vcpu, reg, val);
020df079 4930 } else
5777392e 4931 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4932 return 1;
4933
6affcbed 4934 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4935}
4936
73aaf249
JK		 4937static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4938{
4939 return vcpu->arch.dr6;
4940}
4941
4942static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4943{
4944}
4945
81908bf4
PB		 4946static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4947{
81908bf4
PB		 4948 get_debugreg(vcpu->arch.db[0], 0);
4949 get_debugreg(vcpu->arch.db[1], 1);
4950 get_debugreg(vcpu->arch.db[2], 2);
4951 get_debugreg(vcpu->arch.db[3], 3);
4952 get_debugreg(vcpu->arch.dr6, 6);
4953 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4954
4955 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2183f564 4956 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4957}
4958
020df079
GN		 4959static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4960{
4961 vmcs_writel(GUEST_DR7, val);
4962}
4963
851ba692 4964static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4965{
eb90f341 4966 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4967 return 1;
4968}
4969
851ba692 4970static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4971{
9dadc2f9 4972 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
2714d1d3 4973
3842d135
AK		 4974 kvm_make_request(KVM_REQ_EVENT, vcpu);
4975
a26bf12a 4976 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4977 return 1;
4978}
4979
851ba692 4980static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4981{
0d9c055e 4982 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 4983}
4984
ec25d5e6
GN		 4985static int handle_invd(struct kvm_vcpu *vcpu)
4986{
60fc3d02 4987 return kvm_emulate_instruction(vcpu, 0);
ec25d5e6
GN		 4988}
4989
851ba692 4990static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4991{
f9c617f6 4992 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4993
4994 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 4995 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 4996}
4997
fee84b07
AK		 4998static int handle_rdpmc(struct kvm_vcpu *vcpu)
4999{
5000 int err;
5001
5002 err = kvm_rdpmc(vcpu);
6affcbed 5003 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 5004}
5005
851ba692 5006static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5007{
6affcbed 5008 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5009}
5010
2acf923e
DC		 5011static int handle_xsetbv(struct kvm_vcpu *vcpu)
5012{
5013 u64 new_bv = kvm_read_edx_eax(vcpu);
de3cd117 5014 u32 index = kvm_rcx_read(vcpu);
2acf923e
DC		 5015
5016 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 5017 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 5018 return 1;
5019}
5020
851ba692 5021static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5022{
58fbbf26
KT		 5023 if (likely(fasteoi)) {
5024 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5025 int access_type, offset;
5026
5027 access_type = exit_qualification & APIC_ACCESS_TYPE;
5028 offset = exit_qualification & APIC_ACCESS_OFFSET;
5029 /*
5030 * Sane guest uses MOV to write EOI, with written value
5031 * not cared. So make a short-circuit here by avoiding
5032 * heavy instruction emulation.
5033 */
5034 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5035 (offset == APIC_EOI)) {
5036 kvm_lapic_set_eoi(vcpu);
6affcbed 5037 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 5038 }
5039 }
60fc3d02 5040 return kvm_emulate_instruction(vcpu, 0);
f78e0e2e
SY		 5041}
5042
c7c9c56c
YZ		 5043static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5044{
5045 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5046 int vector = exit_qualification & 0xff;
5047
5048 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5049 kvm_apic_set_eoi_accelerated(vcpu, vector);
5050 return 1;
5051}
5052
83d4c286
YZ		 5053static int handle_apic_write(struct kvm_vcpu *vcpu)
5054{
5055 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5056 u32 offset = exit_qualification & 0xfff;
5057
5058 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5059 kvm_apic_write_nodecode(vcpu, offset);
5060 return 1;
5061}
5062
851ba692 5063static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5064{
60637aac 5065 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5066 unsigned long exit_qualification;
e269fb21
JK		 5067 bool has_error_code = false;
5068 u32 error_code = 0;
37817f29 5069 u16 tss_selector;
7f3d35fd 5070 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5071
5072 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5073 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5074 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5075
5076 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5077
5078 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5079 if (reason == TASK_SWITCH_GATE && idt_v) {
5080 switch (type) {
5081 case INTR_TYPE_NMI_INTR:
5082 vcpu->arch.nmi_injected = false;
654f06fc 5083 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5084 break;
5085 case INTR_TYPE_EXT_INTR:
66fd3f7f 5086 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5087 kvm_clear_interrupt_queue(vcpu);
5088 break;
5089 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5090 if (vmx->idt_vectoring_info &
5091 VECTORING_INFO_DELIVER_CODE_MASK) {
5092 has_error_code = true;
5093 error_code =
5094 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5095 }
5096 /* fall through */
64a7ec06
GN		 5097 case INTR_TYPE_SOFT_EXCEPTION:
5098 kvm_clear_exception_queue(vcpu);
5099 break;
5100 default:
5101 break;
5102 }
60637aac 5103 }
37817f29
IE		 5104 tss_selector = exit_qualification;
5105
64a7ec06
GN		 5106 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5107 type != INTR_TYPE_EXT_INTR &&
5108 type != INTR_TYPE_NMI_INTR))
1957aa63 5109 WARN_ON(!skip_emulated_instruction(vcpu));
64a7ec06 5110
42dbaa5a
JK		 5111 /*
5112 * TODO: What about debug traps on tss switch?
5113 * Are we supposed to inject them and update dr6?
5114 */
1051778f
SC		 5115 return kvm_task_switch(vcpu, tss_selector,
5116 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
60fc3d02 5117 reason, has_error_code, error_code);
37817f29
IE		 5118}
5119
851ba692 5120static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5121{
f9c617f6 5122 unsigned long exit_qualification;
1439442c 5123 gpa_t gpa;
eebed243 5124 u64 error_code;
1439442c 5125
f9c617f6 5126 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5127
0be9c7a8
GN		 5128 /*
5129 * EPT violation happened while executing iret from NMI,
5130 * "blocked by NMI" bit has to be set before next VM entry.
5131 * There are errata that may cause this bit to not be set:
5132 * AAK134, BY25.
5133 */
bcd1c294 5134 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5135 enable_vnmi &&
bcd1c294 5136 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5137 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5138
1439442c 5139 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5140 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5141
27959a44 5142 /* Is it a read fault? */
ab22a473 5143 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5144 ? PFERR_USER_MASK : 0;
5145 /* Is it a write fault? */
ab22a473 5146 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5147 ? PFERR_WRITE_MASK : 0;
5148 /* Is it a fetch fault? */
ab22a473 5149 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5150 ? PFERR_FETCH_MASK : 0;
5151 /* ept page table entry is present? */
5152 error_code |= (exit_qualification &
5153 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5154 EPT_VIOLATION_EXECUTABLE))
5155 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5156
eebed243
PB		 5157 error_code |= (exit_qualification & 0x100) != 0 ?
5158 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5159
25d92081 5160 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5161 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5162}
5163
851ba692 5164static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5165{
68f89400
MT		 5166 gpa_t gpa;
5167
9034e6e8
PB		 5168 /*
5169 * A nested guest cannot optimize MMIO vmexits, because we have an
5170 * nGPA here instead of the required GPA.
5171 */
68f89400 5172 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5173 if (!is_guest_mode(vcpu) &&
5174 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5175 trace_kvm_fast_mmio(gpa);
1957aa63 5176 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 5177 }
68f89400 5178
c75d0edc 5179 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5180}
5181
851ba692 5182static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5183{
d02fcf50 5184 WARN_ON_ONCE(!enable_vnmi);
4e2a0bc5 5185 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
f08864b4 5186 ++vcpu->stat.nmi_window_exits;
3842d135 5187 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5188
5189 return 1;
5190}
5191
80ced186 5192static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5193{
8b3079a5 5194 struct vcpu_vmx *vmx = to_vmx(vcpu);
49e9d557 5195 bool intr_window_requested;
b8405c18 5196 unsigned count = 130;
49e9d557 5197
2bb8cafe
SC		 5198 /*
5199 * We should never reach the point where we are emulating L2
5200 * due to invalid guest state as that means we incorrectly
5201 * allowed a nested VMEntry with an invalid vmcs12.
5202 */
5203 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5204
2183f564 5205 intr_window_requested = exec_controls_get(vmx) &
9dadc2f9 5206 CPU_BASED_INTR_WINDOW_EXITING;
ea953ef0 5207
98eb2f8b 5208 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5209 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5210 return handle_interrupt_window(&vmx->vcpu);
5211
72875d8a 5212 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5213 return 1;
5214
60fc3d02 5215 if (!kvm_emulate_instruction(vcpu, 0))
8fff2710 5216 return 0;
1d5a4d9b 5217
add5ff7a 5218 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
8fff2710
SC		 5219 vcpu->arch.exception.pending) {
5220 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5221 vcpu->run->internal.suberror =
5222 KVM_INTERNAL_ERROR_EMULATION;
5223 vcpu->run->internal.ndata = 0;
5224 return 0;
5225 }
ea953ef0 5226
8d76c49e
GN		 5227 if (vcpu->arch.halt_request) {
5228 vcpu->arch.halt_request = 0;
8fff2710 5229 return kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5230 }
5231
8fff2710
SC		 5232 /*
5233 * Note, return 1 and not 0, vcpu_run() is responsible for
5234 * morphing the pending signal into the proper return code.
5235 */
ea953ef0 5236 if (signal_pending(current))
8fff2710
SC		 5237 return 1;
5238
ea953ef0
MG		 5239 if (need_resched())
5240 schedule();
5241 }
5242
8fff2710 5243 return 1;
b4a2d31d
RK		 5244}
5245
5246static void grow_ple_window(struct kvm_vcpu *vcpu)
5247{
5248 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5249 unsigned int old = vmx->ple_window;
b4a2d31d 5250
c8e88717
BM		 5251 vmx->ple_window = __grow_ple_window(old, ple_window,
5252 ple_window_grow,
5253 ple_window_max);
b4a2d31d 5254
4f75bcc3 5255 if (vmx->ple_window != old) {
b4a2d31d 5256 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5257 trace_kvm_ple_window_update(vcpu->vcpu_id,
5258 vmx->ple_window, old);
5259 }
b4a2d31d
RK		 5260}
5261
5262static void shrink_ple_window(struct kvm_vcpu *vcpu)
5263{
5264 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5265 unsigned int old = vmx->ple_window;
b4a2d31d 5266
c8e88717
BM		 5267 vmx->ple_window = __shrink_ple_window(old, ple_window,
5268 ple_window_shrink,
5269 ple_window);
b4a2d31d 5270
4f75bcc3 5271 if (vmx->ple_window != old) {
b4a2d31d 5272 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5273 trace_kvm_ple_window_update(vcpu->vcpu_id,
5274 vmx->ple_window, old);
5275 }
b4a2d31d
RK		 5276}
5277
bf9f6ac8
FW		 5278/*
5279 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5280 */
5281static void wakeup_handler(void)
5282{
5283 struct kvm_vcpu *vcpu;
5284 int cpu = smp_processor_id();
5285
5286 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5287 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5288 blocked_vcpu_list) {
5289 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5290
5291 if (pi_test_on(pi_desc) == 1)
5292 kvm_vcpu_kick(vcpu);
5293 }
5294 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5295}
5296
e01bca2f 5297static void vmx_enable_tdp(void)
f160c7b7
JS		 5298{
5299 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5300 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5301 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5302 0ull, VMX_EPT_EXECUTABLE_MASK,
5303 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5304 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5305
5306 ept_set_mmio_spte_mask();
5307 kvm_enable_tdp();
5308}
5309
4b8d54f9
ZE		 5310/*
5311 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5312 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5313 */
9fb41ba8 5314static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5315{
b31c114b 5316 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5317 grow_ple_window(vcpu);
5318
de63ad4c
LM		 5319 /*
5320 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5321 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5322 * never set PAUSE_EXITING and just set PLE if supported,
5323 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5324 */
5325 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5326 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5327}
5328
87c00572 5329static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5330{
6affcbed 5331 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5332}
5333
87c00572
GS		 5334static int handle_mwait(struct kvm_vcpu *vcpu)
5335{
5336 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5337 return handle_nop(vcpu);
5338}
5339
45ec368c
JM		 5340static int handle_invalid_op(struct kvm_vcpu *vcpu)
5341{
5342 kvm_queue_exception(vcpu, UD_VECTOR);
5343 return 1;
5344}
5345
5f3d45e7
MD		 5346static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5347{
5348 return 1;
5349}
5350
87c00572
GS		 5351static int handle_monitor(struct kvm_vcpu *vcpu)
5352{
5353 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5354 return handle_nop(vcpu);
5355}
5356
55d2375e 5357static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5358{
55d2375e
SC		 5359 u32 vmx_instruction_info;
5360 unsigned long type;
5361 bool pcid_enabled;
5362 gva_t gva;
5363 struct x86_exception e;
5364 unsigned i;
5365 unsigned long roots_to_free = 0;
5366 struct {
5367 u64 pcid;
5368 u64 gla;
5369 } operand;
f9eb4af6 5370
55d2375e 5371 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5372 kvm_queue_exception(vcpu, UD_VECTOR);
5373 return 1;
5374 }
5375
55d2375e
SC		 5376 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5377 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5378
5379 if (type > 3) {
5380 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5381 return 1;
5382 }
5383
55d2375e
SC		 5384 /* According to the Intel instruction reference, the memory operand
5385 * is read even if it isn't needed (e.g., for type==all)
5386 */
3573e22c 5387 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
fdb28619
EK		 5388 vmx_instruction_info, false,
5389 sizeof(operand), &gva))
3573e22c
BD		 5390 return 1;
5391
55d2375e 5392 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5393 kvm_inject_page_fault(vcpu, &e);
5394 return 1;
5395 }
5396
55d2375e
SC		 5397 if (operand.pcid >> 12 != 0) {
5398 kvm_inject_gp(vcpu, 0);
5399 return 1;
abfc52c6 5400 }
e29acc55 5401
55d2375e 5402 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5403
55d2375e
SC		 5404 switch (type) {
5405 case INVPCID_TYPE_INDIV_ADDR:
5406 if ((!pcid_enabled && (operand.pcid != 0)) ||
5407 is_noncanonical_address(operand.gla, vcpu)) {
5408 kvm_inject_gp(vcpu, 0);
5409 return 1;
5410 }
5411 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5412 return kvm_skip_emulated_instruction(vcpu);
61ada748 5413
55d2375e
SC		 5414 case INVPCID_TYPE_SINGLE_CTXT:
5415 if (!pcid_enabled && (operand.pcid != 0)) {
5416 kvm_inject_gp(vcpu, 0);
5417 return 1;
5418 }
e29acc55 5419
55d2375e
SC		 5420 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5421 kvm_mmu_sync_roots(vcpu);
5422 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5423 }
e29acc55 5424
55d2375e
SC		 5425 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5426 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5427 == operand.pcid)
5428 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5429
55d2375e
SC		 5430 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5431 /*
5432 * If neither the current cr3 nor any of the prev_roots use the
5433 * given PCID, then nothing needs to be done here because a
5434 * resync will happen anyway before switching to any other CR3.
5435 */
e29acc55 5436
55d2375e 5437 return kvm_skip_emulated_instruction(vcpu);
61ada748 5438
55d2375e
SC		 5439 case INVPCID_TYPE_ALL_NON_GLOBAL:
5440 /*
5441 * Currently, KVM doesn't mark global entries in the shadow
5442 * page tables, so a non-global flush just degenerates to a
5443 * global flush. If needed, we could optimize this later by
5444 * keeping track of global entries in shadow page tables.
5445 */
e29acc55 5446
55d2375e
SC		 5447 /* fall-through */
5448 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5449 kvm_mmu_unload(vcpu);
5450 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5451
55d2375e
SC		 5452 default:
5453 BUG(); /* We have already checked above that type <= 3 */
5454 }
e29acc55
JM		 5455}
5456
55d2375e 5457static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5458{
55d2375e 5459 unsigned long exit_qualification;
b3897a49 5460
55d2375e 5461 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5462
55d2375e 5463 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5464
5465 /*
55d2375e
SC		 5466 * PML buffer FULL happened while executing iret from NMI,
5467 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5468 */
55d2375e
SC		 5469 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5470 enable_vnmi &&
5471 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5472 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5473 GUEST_INTR_STATE_NMI);
e49fcb8b 5474
55d2375e
SC		 5475 /*
5476 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5477 * here.., and there's no userspace involvement needed for PML.
5478 */
ec378aee
NHE		 5479 return 1;
5480}
5481
55d2375e 5482static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5483{
804939ea
SC		 5484 struct vcpu_vmx *vmx = to_vmx(vcpu);
5485
5486 if (!vmx->req_immediate_exit &&
5487 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
55d2375e 5488 kvm_lapic_expired_hv_timer(vcpu);
804939ea 5489
55d2375e 5490 return 1;
8ca44e88
DM		 5491}
5492
55d2375e
SC		 5493/*
5494 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5495 * are overwritten by nested_vmx_setup() when nested=1.
5496 */
5497static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5498{
55d2375e
SC		 5499 kvm_queue_exception(vcpu, UD_VECTOR);
5500 return 1;
b8bbab92
VK		 5501}
5502
55d2375e 5503static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5504{
55d2375e
SC		 5505 /*
5506 * SGX virtualization is not yet supported. There is no software
5507 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5508 * to prevent the guest from executing ENCLS.
5509 */
5510 kvm_queue_exception(vcpu, UD_VECTOR);
5511 return 1;
e7953d7f
AG		 5512}
5513
ec378aee 5514/*
55d2375e
SC		 5515 * The exit handlers return 1 if the exit was handled fully and guest execution
5516 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5517 * to be done to userspace and return 0.
ec378aee 5518 */
55d2375e 5519static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
95b5a48c 5520 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
55d2375e
SC		 5521 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5522 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5523 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5524 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5525 [EXIT_REASON_CR_ACCESS] = handle_cr,
5526 [EXIT_REASON_DR_ACCESS] = handle_dr,
f399e60c
AA		 5527 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5528 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5529 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
9dadc2f9 5530 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
f399e60c 5531 [EXIT_REASON_HLT] = kvm_emulate_halt,
55d2375e
SC		 5532 [EXIT_REASON_INVD] = handle_invd,
5533 [EXIT_REASON_INVLPG] = handle_invlpg,
5534 [EXIT_REASON_RDPMC] = handle_rdpmc,
5535 [EXIT_REASON_VMCALL] = handle_vmcall,
5536 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5537 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5538 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5539 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5540 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5541 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5542 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5543 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5544 [EXIT_REASON_VMON] = handle_vmx_instruction,
5545 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5546 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5547 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5548 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5549 [EXIT_REASON_WBINVD] = handle_wbinvd,
5550 [EXIT_REASON_XSETBV] = handle_xsetbv,
5551 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5552 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5553 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5554 [EXIT_REASON_LDTR_TR] = handle_desc,
5555 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5556 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5557 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5558 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5559 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5560 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5561 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5562 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5563 [EXIT_REASON_RDRAND] = handle_invalid_op,
5564 [EXIT_REASON_RDSEED] = handle_invalid_op,
55d2375e
SC		 5565 [EXIT_REASON_PML_FULL] = handle_pml_full,
5566 [EXIT_REASON_INVPCID] = handle_invpcid,
5567 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5568 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5569 [EXIT_REASON_ENCLS] = handle_encls,
5570};
b8bbab92 5571
55d2375e
SC		 5572static const int kvm_vmx_max_exit_handlers =
5573 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5574
55d2375e 5575static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5576{
55d2375e
SC		 5577 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5578 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5579}
5580
55d2375e 5581static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5582{
55d2375e
SC		 5583 if (vmx->pml_pg) {
5584 __free_page(vmx->pml_pg);
5585 vmx->pml_pg = NULL;
b8bbab92 5586 }
27d6c865
NHE		 5587}
5588
55d2375e 5589static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5590{
55d2375e
SC		 5591 struct vcpu_vmx *vmx = to_vmx(vcpu);
5592 u64 *pml_buf;
5593 u16 pml_idx;
cd232ad0 5594
55d2375e 5595 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5596
55d2375e
SC		 5597 /* Do nothing if PML buffer is empty */
5598 if (pml_idx == (PML_ENTITY_NUM - 1))
5599 return;
cd232ad0 5600
55d2375e
SC		 5601 /* PML index always points to next available PML buffer entity */
5602 if (pml_idx >= PML_ENTITY_NUM)
5603 pml_idx = 0;
5604 else
5605 pml_idx++;
945679e3 5606
55d2375e
SC		 5607 pml_buf = page_address(vmx->pml_pg);
5608 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5609 u64 gpa;
945679e3 5610
55d2375e
SC		 5611 gpa = pml_buf[pml_idx];
5612 WARN_ON(gpa & (PAGE_SIZE - 1));
5613 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5614 }
5615
55d2375e
SC		 5616 /* reset PML index */
5617 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5618}
5619
f4160e45 5620/*
55d2375e
SC		 5621 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5622 * Called before reporting dirty_bitmap to userspace.
f4160e45 5623 */
55d2375e 5624static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5625{
55d2375e
SC		 5626 int i;
5627 struct kvm_vcpu *vcpu;
49f705c5 5628 /*
55d2375e
SC		 5629 * We only need to kick vcpu out of guest mode here, as PML buffer
5630 * is flushed at beginning of all VMEXITs, and it's obvious that only
5631 * vcpus running in guest are possible to have unflushed GPAs in PML
5632 * buffer.
49f705c5 5633 */
55d2375e
SC		 5634 kvm_for_each_vcpu(i, vcpu, kvm)
5635 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5636}
5637
55d2375e 5638static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5639{
55d2375e
SC		 5640 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5641 name, vmcs_read16(sel),
5642 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5643 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5644 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5645}
5646
55d2375e 5647static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5648{
55d2375e
SC		 5649 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5650 name, vmcs_read32(limit),
5651 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5652}
5653
69090810 5654void dump_vmcs(void)
63846663 5655{
6f2f8453
PB		 5656 u32 vmentry_ctl, vmexit_ctl;
5657 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5658 unsigned long cr4;
5659 u64 efer;
55d2375e 5660 int i, n;
63846663 5661
6f2f8453
PB		 5662 if (!dump_invalid_vmcs) {
5663 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5664 return;
5665 }
5666
5667 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5668 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5669 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5670 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5671 cr4 = vmcs_readl(GUEST_CR4);
5672 efer = vmcs_read64(GUEST_IA32_EFER);
5673 secondary_exec_control = 0;
55d2375e
SC		 5674 if (cpu_has_secondary_exec_ctrls())
5675 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5676
55d2375e
SC		 5677 pr_err("*** Guest State ***\n");
5678 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5679 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5680 vmcs_readl(CR0_GUEST_HOST_MASK));
5681 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5682 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5683 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5684 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5685 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5686 {
5687 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5688 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5689 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5690 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5691 }
55d2375e
SC		 5692 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5693 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5694 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5695 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5696 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5697 vmcs_readl(GUEST_SYSENTER_ESP),
5698 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5699 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5700 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5701 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5702 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5703 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5704 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5705 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5706 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5707 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5708 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5709 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5710 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5711 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5712 efer, vmcs_read64(GUEST_IA32_PAT));
5713 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5714 vmcs_read64(GUEST_IA32_DEBUGCTL),
5715 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5716 if (cpu_has_load_perf_global_ctrl() &&
5717 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5718 pr_err("PerfGlobCtl = 0x%016llx\n",
5719 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5720 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5721 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5722 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5723 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5724 vmcs_read32(GUEST_ACTIVITY_STATE));
5725 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5726 pr_err("InterruptStatus = %04x\n",
5727 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5728
55d2375e
SC		 5729 pr_err("*** Host State ***\n");
5730 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5731 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5732 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5733 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5734 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5735 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5736 vmcs_read16(HOST_TR_SELECTOR));
5737 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5738 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5739 vmcs_readl(HOST_TR_BASE));
5740 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5741 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5742 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5743 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5744 vmcs_readl(HOST_CR4));
5745 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5746 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5747 vmcs_read32(HOST_IA32_SYSENTER_CS),
5748 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5749 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5750 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5751 vmcs_read64(HOST_IA32_EFER),
5752 vmcs_read64(HOST_IA32_PAT));
5753 if (cpu_has_load_perf_global_ctrl() &&
5754 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5755 pr_err("PerfGlobCtl = 0x%016llx\n",
5756 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5757
55d2375e
SC		 5758 pr_err("*** Control State ***\n");
5759 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5760 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5761 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5762 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5763 vmcs_read32(EXCEPTION_BITMAP),
5764 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5765 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5766 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5767 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5768 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5769 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5770 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5771 vmcs_read32(VM_EXIT_INTR_INFO),
5772 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5773 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5774 pr_err(" reason=%08x qualification=%016lx\n",
5775 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5776 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5777 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5778 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5779 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5780 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5781 pr_err("TSC Multiplier = 0x%016llx\n",
5782 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5783 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5784 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5785 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5786 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5787 }
d6a85c32 5788 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9d609649
PB		 5789 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5790 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
d6a85c32 5791 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
9d609649 5792 }
55d2375e
SC		 5793 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5794 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5795 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5796 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5797 n = vmcs_read32(CR3_TARGET_COUNT);
5798 for (i = 0; i + 1 < n; i += 4)
5799 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5800 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5801 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5802 if (i < n)
5803 pr_err("CR3 target%u=%016lx\n",
5804 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5805 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5806 pr_err("PLE Gap=%08x Window=%08x\n",
5807 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5808 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5809 pr_err("Virtual processor ID = 0x%04x\n",
5810 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5811}
5812
55d2375e
SC		 5813/*
5814 * The guest has exited. See if we can fix it or if we need userspace
5815 * assistance.
5816 */
1e9e2622
WL		 5817static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5818 enum exit_fastpath_completion exit_fastpath)
ff651cb6 5819{
55d2375e
SC		 5820 struct vcpu_vmx *vmx = to_vmx(vcpu);
5821 u32 exit_reason = vmx->exit_reason;
5822 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5823
55d2375e 5824 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5825
55d2375e
SC		 5826 /*
5827 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5828 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5829 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5830 * mode as if vcpus is in root mode, the PML buffer must has been
5831 * flushed already.
5832 */
5833 if (enable_pml)
5834 vmx_flush_pml_buffer(vcpu);
1dc35dac 5835
55d2375e
SC		 5836 /* If guest state is invalid, start emulating */
5837 if (vmx->emulation_required)
5838 return handle_invalid_guest_state(vcpu);
1dc35dac 5839
55d2375e
SC		 5840 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5841 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5842
55d2375e
SC		 5843 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5844 dump_vmcs();
5845 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5846 vcpu->run->fail_entry.hardware_entry_failure_reason
5847 = exit_reason;
5848 return 0;
9ed38ffa
LP		 5849 }
5850
55d2375e 5851 if (unlikely(vmx->fail)) {
3b20e03a 5852 dump_vmcs();
55d2375e
SC		 5853 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5854 vcpu->run->fail_entry.hardware_entry_failure_reason
5855 = vmcs_read32(VM_INSTRUCTION_ERROR);
5856 return 0;
5857 }
50c28f21 5858
55d2375e
SC		 5859 /*
5860 * Note:
5861 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5862 * delivery event since it indicates guest is accessing MMIO.
5863 * The vm-exit can be triggered again after return to guest that
5864 * will cause infinite loop.
5865 */
5866 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5867 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5868 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5869 exit_reason != EXIT_REASON_PML_FULL &&
5870 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5871 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5872 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5873 vcpu->run->internal.ndata = 3;
5874 vcpu->run->internal.data[0] = vectoring_info;
5875 vcpu->run->internal.data[1] = exit_reason;
5876 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5877 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5878 vcpu->run->internal.ndata++;
5879 vcpu->run->internal.data[3] =
5880 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5881 }
5882 return 0;
5883 }
50c28f21 5884
55d2375e
SC		 5885 if (unlikely(!enable_vnmi &&
5886 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5887 if (vmx_interrupt_allowed(vcpu)) {
5888 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5889 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5890 vcpu->arch.nmi_pending) {
5891 /*
5892 * This CPU don't support us in finding the end of an
5893 * NMI-blocked window if the guest runs with IRQs
5894 * disabled. So we pull the trigger after 1 s of
5895 * futile waiting, but inform the user about this.
5896 */
5897 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5898 "state on VCPU %d after 1 s timeout\n",
5899 __func__, vcpu->vcpu_id);
5900 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5901 }
5902 }
50c28f21 5903
1e9e2622
WL		 5904 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5905 kvm_skip_emulated_instruction(vcpu);
5906 return 1;
5907 } else if (exit_reason < kvm_vmx_max_exit_handlers
4289d272
AA		 5908 && kvm_vmx_exit_handlers[exit_reason]) {
5909#ifdef CONFIG_RETPOLINE
5910 if (exit_reason == EXIT_REASON_MSR_WRITE)
5911 return kvm_emulate_wrmsr(vcpu);
5912 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5913 return handle_preemption_timer(vcpu);
9dadc2f9 5914 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
4289d272
AA		 5915 return handle_interrupt_window(vcpu);
5916 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5917 return handle_external_interrupt(vcpu);
5918 else if (exit_reason == EXIT_REASON_HLT)
5919 return kvm_emulate_halt(vcpu);
5920 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5921 return handle_ept_misconfig(vcpu);
5922#endif
55d2375e 5923 return kvm_vmx_exit_handlers[exit_reason](vcpu);
4289d272 5924 } else {
55d2375e
SC		 5925 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5926 exit_reason);
7396d337
LA		 5927 dump_vmcs();
5928 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5929 vcpu->run->internal.suberror =
5930 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5931 vcpu->run->internal.ndata = 1;
5932 vcpu->run->internal.data[0] = exit_reason;
5933 return 0;
55d2375e 5934 }
9ed38ffa
LP		 5935}
5936
efebf0aa 5937/*
55d2375e
SC		 5938 * Software based L1D cache flush which is used when microcode providing
5939 * the cache control MSR is not loaded.
efebf0aa 5940 *
55d2375e
SC		 5941 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5942 * flush it is required to read in 64 KiB because the replacement algorithm
5943 * is not exactly LRU. This could be sized at runtime via topology
5944 * information but as all relevant affected CPUs have 32KiB L1D cache size
5945 * there is no point in doing so.
efebf0aa 5946 */
55d2375e 5947static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5948{
55d2375e 5949 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5950
5951 /*
55d2375e
SC		 5952 * This code is only executed when the the flush mode is 'cond' or
5953 * 'always'
25a2e4fe 5954 */
55d2375e
SC		 5955 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5956 bool flush_l1d;
25a2e4fe 5957
55d2375e
SC		 5958 /*
5959 * Clear the per-vcpu flush bit, it gets set again
5960 * either from vcpu_run() or from one of the unsafe
5961 * VMEXIT handlers.
5962 */
5963 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5964 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5965
55d2375e
SC		 5966 /*
5967 * Clear the per-cpu flush bit, it gets set again from
5968 * the interrupt handlers.
5969 */
5970 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5971 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 5972
55d2375e
SC		 5973 if (!flush_l1d)
5974 return;
5975 }
09abe320 5976
55d2375e 5977 vcpu->stat.l1d_flush++;
25a2e4fe 5978
55d2375e
SC		 5979 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5980 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5981 return;
5982 }
25a2e4fe 5983
55d2375e
SC		 5984 asm volatile(
5985 /* First ensure the pages are in the TLB */
5986 "xorl %%eax, %%eax\n"
5987 ".Lpopulate_tlb:\n\t"
5988 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5989 "addl $4096, %%eax\n\t"
5990 "cmpl %%eax, %[size]\n\t"
5991 "jne .Lpopulate_tlb\n\t"
5992 "xorl %%eax, %%eax\n\t"
5993 "cpuid\n\t"
5994 /* Now fill the cache */
5995 "xorl %%eax, %%eax\n"
5996 ".Lfill_cache:\n"
5997 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5998 "addl $64, %%eax\n\t"
5999 "cmpl %%eax, %[size]\n\t"
6000 "jne .Lfill_cache\n\t"
6001 "lfence\n"
6002 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6003 [size] "r" (size)
6004 : "eax", "ebx", "ecx", "edx");
09abe320 6005}
25a2e4fe 6006
55d2375e 6007static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 6008{
55d2375e 6009 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
132f4f7e 6010 int tpr_threshold;
09abe320 6011
55d2375e
SC		 6012 if (is_guest_mode(vcpu) &&
6013 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6014 return;
25a2e4fe 6015
132f4f7e 6016 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
02d496cf
LA		 6017 if (is_guest_mode(vcpu))
6018 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6019 else
6020 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
8665c3f9
PB		 6021}
6022
55d2375e 6023void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 6024{
fe7f895d 6025 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6026 u32 sec_exec_control;
8665c3f9 6027
55d2375e
SC		 6028 if (!lapic_in_kernel(vcpu))
6029 return;
9314006d 6030
55d2375e
SC		 6031 if (!flexpriority_enabled &&
6032 !cpu_has_vmx_virtualize_x2apic_mode())
6033 return;
705699a1 6034
55d2375e
SC		 6035 /* Postpone execution until vmcs01 is the current VMCS. */
6036 if (is_guest_mode(vcpu)) {
fe7f895d 6037 vmx->nested.change_vmcs01_virtual_apic_mode = true;
55d2375e 6038 return;
6beb7bd5 6039 }
fe3ef05c 6040
fe7f895d 6041 sec_exec_control = secondary_exec_controls_get(vmx);
55d2375e
SC		 6042 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6043 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 6044
55d2375e
SC		 6045 switch (kvm_get_apic_mode(vcpu)) {
6046 case LAPIC_MODE_INVALID:
6047 WARN_ONCE(true, "Invalid local APIC state");
6048 case LAPIC_MODE_DISABLED:
6049 break;
6050 case LAPIC_MODE_XAPIC:
6051 if (flexpriority_enabled) {
6052 sec_exec_control |=
6053 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6054 vmx_flush_tlb(vcpu, true);
6055 }
6056 break;
6057 case LAPIC_MODE_X2APIC:
6058 if (cpu_has_vmx_virtualize_x2apic_mode())
6059 sec_exec_control |=
6060 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6061 break;
09abe320 6062 }
fe7f895d 6063 secondary_exec_controls_set(vmx, sec_exec_control);
09abe320 6064
55d2375e
SC		 6065 vmx_update_msr_bitmap(vcpu);
6066}
0238ea91 6067
55d2375e
SC		 6068static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6069{
6070 if (!is_guest_mode(vcpu)) {
6071 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6072 vmx_flush_tlb(vcpu, true);
6073 }
6074}
fe3ef05c 6075
55d2375e
SC		 6076static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6077{
6078 u16 status;
6079 u8 old;
32c7acf0 6080
55d2375e
SC		 6081 if (max_isr == -1)
6082 max_isr = 0;
608406e2 6083
55d2375e
SC		 6084 status = vmcs_read16(GUEST_INTR_STATUS);
6085 old = status >> 8;
6086 if (max_isr != old) {
6087 status &= 0xff;
6088 status |= max_isr << 8;
6089 vmcs_write16(GUEST_INTR_STATUS, status);
6090 }
6091}
6beb7bd5 6092
55d2375e
SC		 6093static void vmx_set_rvi(int vector)
6094{
6095 u16 status;
6096 u8 old;
0b665d30 6097
55d2375e
SC		 6098 if (vector == -1)
6099 vector = 0;
fe3ef05c 6100
55d2375e
SC		 6101 status = vmcs_read16(GUEST_INTR_STATUS);
6102 old = (u8)status & 0xff;
6103 if ((u8)vector != old) {
6104 status &= ~0xff;
6105 status |= (u8)vector;
6106 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6107 }
55d2375e 6108}
09abe320 6109
55d2375e
SC		 6110static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6111{
09abe320 6112 /*
55d2375e
SC		 6113 * When running L2, updating RVI is only relevant when
6114 * vmcs12 virtual-interrupt-delivery enabled.
6115 * However, it can be enabled only when L1 also
6116 * intercepts external-interrupts and in that case
6117 * we should not update vmcs02 RVI but instead intercept
6118 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6119 */
55d2375e
SC		 6120 if (!is_guest_mode(vcpu))
6121 vmx_set_rvi(max_irr);
6122}
fe3ef05c 6123
55d2375e
SC		 6124static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6125{
6126 struct vcpu_vmx *vmx = to_vmx(vcpu);
6127 int max_irr;
6128 bool max_irr_updated;
a7c0b07d 6129
55d2375e
SC		 6130 WARN_ON(!vcpu->arch.apicv_active);
6131 if (pi_test_on(&vmx->pi_desc)) {
6132 pi_clear_on(&vmx->pi_desc);
6133 /*
d9ff2744 6134 * IOMMU can write to PID.ON, so the barrier matters even on UP.
55d2375e
SC		 6135 * But on x86 this is just a compiler barrier anyway.
6136 */
6137 smp_mb__after_atomic();
6138 max_irr_updated =
6139 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6140
6141 /*
55d2375e
SC		 6142 * If we are running L2 and L1 has a new pending interrupt
6143 * which can be injected, we should re-evaluate
6144 * what should be done with this new L1 interrupt.
6145 * If L1 intercepts external-interrupts, we should
6146 * exit from L2 to L1. Otherwise, interrupt should be
6147 * delivered directly to L2.
c4ebd629 6148 */
55d2375e
SC		 6149 if (is_guest_mode(vcpu) && max_irr_updated) {
6150 if (nested_exit_on_intr(vcpu))
6151 kvm_vcpu_exiting_guest_mode(vcpu);
6152 else
6153 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6154 }
55d2375e
SC		 6155 } else {
6156 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6157 }
55d2375e
SC		 6158 vmx_hwapic_irr_update(vcpu, max_irr);
6159 return max_irr;
6160}
a7c0b07d 6161
17e433b5
WL		 6162static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6163{
9482ae45
JM		 6164 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6165
6166 return pi_test_on(pi_desc) ||
29881b6e 6167 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
17e433b5
WL		 6168}
6169
55d2375e
SC		 6170static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6171{
6172 if (!kvm_vcpu_apicv_active(vcpu))
6173 return;
25a2e4fe 6174
55d2375e
SC		 6175 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6176 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6177 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6178 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6179}
6180
55d2375e 6181static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6182{
6183 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6184
55d2375e
SC		 6185 pi_clear_on(&vmx->pi_desc);
6186 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6187}
8665c3f9 6188
95b5a48c 6189static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
55d2375e 6190{
beb8d93b 6191 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6192
55d2375e 6193 /* if exit due to PF check for async PF */
beb8d93b 6194 if (is_page_fault(vmx->exit_intr_info))
55d2375e 6195 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 6196
55d2375e 6197 /* Handle machine checks before interrupts are enabled */
beb8d93b 6198 if (is_machine_check(vmx->exit_intr_info))
55d2375e 6199 kvm_machine_check();
fe3ef05c 6200
55d2375e 6201 /* We need to handle NMIs before interrupts are enabled */
beb8d93b 6202 if (is_nmi(vmx->exit_intr_info)) {
55d2375e
SC		 6203 kvm_before_interrupt(&vmx->vcpu);
6204 asm("int $2");
6205 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6206 }
55d2375e 6207}
fe3ef05c 6208
95b5a48c 6209static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
55d2375e 6210{
49def500
SC		 6211 unsigned int vector;
6212 unsigned long entry;
55d2375e 6213#ifdef CONFIG_X86_64
49def500 6214 unsigned long tmp;
55d2375e 6215#endif
49def500
SC		 6216 gate_desc *desc;
6217 u32 intr_info;
fe3ef05c 6218
49def500
SC		 6219 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6220 if (WARN_ONCE(!is_external_intr(intr_info),
6221 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6222 return;
6223
6224 vector = intr_info & INTR_INFO_VECTOR_MASK;
2342080c 6225 desc = (gate_desc *)host_idt_base + vector;
49def500
SC		 6226 entry = gate_offset(desc);
6227
165072b0
SC		 6228 kvm_before_interrupt(vcpu);
6229
49def500 6230 asm volatile(
55d2375e 6231#ifdef CONFIG_X86_64
49def500
SC		 6232 "mov %%" _ASM_SP ", %[sp]\n\t"
6233 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6234 "push $%c[ss]\n\t"
6235 "push %[sp]\n\t"
55d2375e 6236#endif
49def500
SC		 6237 "pushf\n\t"
6238 __ASM_SIZE(push) " $%c[cs]\n\t"
6239 CALL_NOSPEC
6240 :
55d2375e 6241#ifdef CONFIG_X86_64
49def500 6242 [sp]"=&r"(tmp),
55d2375e 6243#endif
49def500
SC		 6244 ASM_CALL_CONSTRAINT
6245 :
6246 THUNK_TARGET(entry),
6247 [ss]"i"(__KERNEL_DS),
6248 [cs]"i"(__KERNEL_CS)
6249 );
165072b0
SC		 6250
6251 kvm_after_interrupt(vcpu);
55d2375e 6252}
95b5a48c
SC		 6253STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6254
1e9e2622
WL		 6255static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6256 enum exit_fastpath_completion *exit_fastpath)
95b5a48c
SC		 6257{
6258 struct vcpu_vmx *vmx = to_vmx(vcpu);
6259
6260 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6261 handle_external_interrupt_irqoff(vcpu);
6262 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6263 handle_exception_nmi_irqoff(vmx);
1e9e2622
WL		 6264 else if (!is_guest_mode(vcpu) &&
6265 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6266 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
95b5a48c 6267}
5a6a9748 6268
55d2375e
SC		 6269static bool vmx_has_emulated_msr(int index)
6270{
6271 switch (index) {
6272 case MSR_IA32_SMBASE:
6273 /*
6274 * We cannot do SMM unless we can run the guest in big
6275 * real mode.
6276 */
6277 return enable_unrestricted_guest || emulate_invalid_guest_state;
95c5c7c7
PB		 6278 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6279 return nested;
55d2375e
SC		 6280 case MSR_AMD64_VIRT_SPEC_CTRL:
6281 /* This is AMD only. */
6282 return false;
6283 default:
6284 return true;
3184a995 6285 }
55d2375e 6286}
2bb8cafe 6287
86f5201d
CP		 6288static bool vmx_pt_supported(void)
6289{
6290 return pt_mode == PT_MODE_HOST_GUEST;
6291}
6292
55d2375e
SC		 6293static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6294{
6295 u32 exit_intr_info;
6296 bool unblock_nmi;
6297 u8 vector;
6298 bool idtv_info_valid;
7ca29de2 6299
55d2375e 6300 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6301
55d2375e
SC		 6302 if (enable_vnmi) {
6303 if (vmx->loaded_vmcs->nmi_known_unmasked)
6304 return;
6305 /*
6306 * Can't use vmx->exit_intr_info since we're not sure what
6307 * the exit reason is.
6308 */
6309 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6310 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6311 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6312 /*
6313 * SDM 3: 27.7.1.2 (September 2008)
6314 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6315 * a guest IRET fault.
6316 * SDM 3: 23.2.2 (September 2008)
6317 * Bit 12 is undefined in any of the following cases:
6318 * If the VM exit sets the valid bit in the IDT-vectoring
6319 * information field.
6320 * If the VM exit is due to a double fault.
6321 */
6322 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6323 vector != DF_VECTOR && !idtv_info_valid)
6324 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6325 GUEST_INTR_STATE_NMI);
6326 else
6327 vmx->loaded_vmcs->nmi_known_unmasked =
6328 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6329 & GUEST_INTR_STATE_NMI);
6330 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6331 vmx->loaded_vmcs->vnmi_blocked_time +=
6332 ktime_to_ns(ktime_sub(ktime_get(),
6333 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6334}
6335
55d2375e
SC		 6336static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6337 u32 idt_vectoring_info,
6338 int instr_len_field,
6339 int error_code_field)
0c7f650e 6340{
55d2375e
SC		 6341 u8 vector;
6342 int type;
6343 bool idtv_info_valid;
0c7f650e 6344
55d2375e 6345 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6346
55d2375e
SC		 6347 vcpu->arch.nmi_injected = false;
6348 kvm_clear_exception_queue(vcpu);
6349 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6350
55d2375e
SC		 6351 if (!idtv_info_valid)
6352 return;
c7c2c709 6353
55d2375e 6354 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6355
55d2375e
SC		 6356 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6357 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6358
55d2375e
SC		 6359 switch (type) {
6360 case INTR_TYPE_NMI_INTR:
6361 vcpu->arch.nmi_injected = true;
6362 /*
6363 * SDM 3: 27.7.1.2 (September 2008)
6364 * Clear bit "block by NMI" before VM entry if a NMI
6365 * delivery faulted.
6366 */
6367 vmx_set_nmi_mask(vcpu, false);
6368 break;
6369 case INTR_TYPE_SOFT_EXCEPTION:
6370 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6371 /* fall through */
6372 case INTR_TYPE_HARD_EXCEPTION:
6373 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6374 u32 err = vmcs_read32(error_code_field);
6375 kvm_requeue_exception_e(vcpu, vector, err);
6376 } else
6377 kvm_requeue_exception(vcpu, vector);
6378 break;
6379 case INTR_TYPE_SOFT_INTR:
6380 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6381 /* fall through */
6382 case INTR_TYPE_EXT_INTR:
6383 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6384 break;
6385 default:
6386 break;
0447378a 6387 }
ca0bde28
JM		 6388}
6389
55d2375e 6390static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6391{
55d2375e
SC		 6392 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6393 VM_EXIT_INSTRUCTION_LEN,
6394 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6395}
6396
55d2375e 6397static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6398{
55d2375e
SC		 6399 __vmx_complete_interrupts(vcpu,
6400 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6401 VM_ENTRY_INSTRUCTION_LEN,
6402 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6403
55d2375e 6404 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6405}
6406
55d2375e 6407static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6408{
55d2375e
SC		 6409 int i, nr_msrs;
6410 struct perf_guest_switch_msr *msrs;
7c177938 6411
55d2375e 6412 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6413
55d2375e
SC		 6414 if (!msrs)
6415 return;
f1b026a3 6416
55d2375e
SC		 6417 for (i = 0; i < nr_msrs; i++)
6418 if (msrs[i].host == msrs[i].guest)
6419 clear_atomic_switch_msr(vmx, msrs[i].msr);
6420 else
6421 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6422 msrs[i].host, false);
ca0bde28 6423}
52017608 6424
6e3ba4ab
TX		 6425static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6426{
6427 u32 host_umwait_control;
6428
6429 if (!vmx_has_waitpkg(vmx))
6430 return;
6431
6432 host_umwait_control = get_umwait_control_msr();
6433
6434 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6435 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6436 vmx->msr_ia32_umwait_control,
6437 host_umwait_control, false);
6438 else
6439 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6440}
6441
55d2375e 6442static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6443{
6444 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6445 u64 tscl;
6446 u32 delta_tsc;
52017608 6447
55d2375e 6448 if (vmx->req_immediate_exit) {
804939ea
SC		 6449 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6450 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6451 } else if (vmx->hv_deadline_tsc != -1) {
55d2375e
SC		 6452 tscl = rdtsc();
6453 if (vmx->hv_deadline_tsc > tscl)
6454 /* set_hv_timer ensures the delta fits in 32-bits */
6455 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6456 cpu_preemption_timer_multi);
6457 else
6458 delta_tsc = 0;
858e25c0 6459
804939ea
SC		 6460 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6461 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6462 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6463 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6464 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
7f7f1ba3 6465 }
858e25c0
JM		 6466}
6467
c09b03eb 6468void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6469{
c09b03eb
SC		 6470 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6471 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6472 vmcs_writel(HOST_RSP, host_rsp);
6473 }
5ad6ece8 6474}
5f3d5799 6475
fc2ba5a2 6476bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6477
6478static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6479{
6480 struct vcpu_vmx *vmx = to_vmx(vcpu);
6481 unsigned long cr3, cr4;
6482
6483 /* Record the guest's net vcpu time for enforced NMI injections. */
6484 if (unlikely(!enable_vnmi &&
6485 vmx->loaded_vmcs->soft_vnmi_blocked))
6486 vmx->loaded_vmcs->entry_time = ktime_get();
6487
6488 /* Don't enter VMX if guest state is invalid, let the exit handler
6489 start emulation until we arrive back to a valid state */
6490 if (vmx->emulation_required)
6491 return;
6492
6493 if (vmx->ple_window_dirty) {
6494 vmx->ple_window_dirty = false;
6495 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6496 }
6497
3731905e
SC		 6498 if (vmx->nested.need_vmcs12_to_shadow_sync)
6499 nested_sync_vmcs12_to_shadow(vcpu);
5ad6ece8 6500
cb3c1e2f 6501 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
5ad6ece8 6502 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
cb3c1e2f 6503 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
5ad6ece8
SC		 6504 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6505
6506 cr3 = __get_current_cr3_fast();
6507 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6508 vmcs_writel(HOST_CR3, cr3);
6509 vmx->loaded_vmcs->host_state.cr3 = cr3;
6510 }
6511
6512 cr4 = cr4_read_shadow();
6513 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6514 vmcs_writel(HOST_CR4, cr4);
6515 vmx->loaded_vmcs->host_state.cr4 = cr4;
6516 }
6517
6518 /* When single-stepping over STI and MOV SS, we must clear the
6519 * corresponding interruptibility bits in the guest state. Otherwise
6520 * vmentry fails as it then expects bit 14 (BS) in pending debug
6521 * exceptions being set, but that's not correct for the guest debugging
6522 * case. */
6523 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6524 vmx_set_interrupt_shadow(vcpu, 0);
6525
139a12cf 6526 kvm_load_guest_xsave_state(vcpu);
1811d979 6527
5ad6ece8
SC		 6528 if (static_cpu_has(X86_FEATURE_PKU) &&
6529 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6530 vcpu->arch.pkru != vmx->host_pkru)
6531 __write_pkru(vcpu->arch.pkru);
6532
6533 pt_guest_enter(vmx);
6534
6535 atomic_switch_perf_msrs(vmx);
6e3ba4ab 6536 atomic_switch_umwait_control_msr(vmx);
5ad6ece8 6537
804939ea
SC		 6538 if (enable_preemption_timer)
6539 vmx_update_hv_timer(vcpu);
5ad6ece8 6540
b6c4bc65
WL		 6541 if (lapic_in_kernel(vcpu) &&
6542 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6543 kvm_wait_lapic_expire(vcpu);
6544
5ad6ece8
SC		 6545 /*
6546 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6547 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6548 * is no need to worry about the conditional branch over the wrmsr
6549 * being speculatively taken.
6550 */
6551 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6552
fa4bff16 6553 /* L1D Flush includes CPU buffer clear to mitigate MDS */
c823dd5c
SC		 6554 if (static_branch_unlikely(&vmx_l1d_should_flush))
6555 vmx_l1d_flush(vcpu);
fa4bff16
LT		 6556 else if (static_branch_unlikely(&mds_user_clear))
6557 mds_clear_cpu_buffers();
c823dd5c
SC		 6558
6559 if (vcpu->arch.cr2 != read_cr2())
6560 write_cr2(vcpu->arch.cr2);
6561
fc2ba5a2
SC		 6562 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6563 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6564
6565 vcpu->arch.cr2 = read_cr2();
b6b8a145 6566
55d2375e
SC		 6567 /*
6568 * We do not use IBRS in the kernel. If this vCPU has used the
6569 * SPEC_CTRL MSR it may have left it on; save the value and
6570 * turn it off. This is much more efficient than blindly adding
6571 * it to the atomic save/restore list. Especially as the former
6572 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6573 *
6574 * For non-nested case:
6575 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6576 * save it.
6577 *
6578 * For nested case:
6579 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6580 * save it.
6581 */
6582 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6583 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6584
55d2375e 6585 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6586
55d2375e
SC		 6587 /* All fields are clean at this point */
6588 if (static_branch_unlikely(&enable_evmcs))
6589 current_evmcs->hv_clean_fields |=
6590 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6591
6f6a657c
VK		 6592 if (static_branch_unlikely(&enable_evmcs))
6593 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6594
55d2375e
SC		 6595 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6596 if (vmx->host_debugctlmsr)
6597 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6598
55d2375e
SC		 6599#ifndef CONFIG_X86_64
6600 /*
6601 * The sysexit path does not restore ds/es, so we must set them to
6602 * a reasonable value ourselves.
6603 *
6604 * We can't defer this to vmx_prepare_switch_to_host() since that
6605 * function may be executed in interrupt context, which saves and
6606 * restore segments around it, nullifying its effect.
6607 */
6608 loadsegment(ds, __USER_DS);
6609 loadsegment(es, __USER_DS);
6610#endif
4704d0be 6611
55d2375e
SC		 6612 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6613 | (1 << VCPU_EXREG_RFLAGS)
6614 | (1 << VCPU_EXREG_PDPTR)
6615 | (1 << VCPU_EXREG_SEGMENTS)
6616 | (1 << VCPU_EXREG_CR3));
6617 vcpu->arch.regs_dirty = 0;
7854cbca 6618
2ef444f1
CP		 6619 pt_guest_exit(vmx);
6620
3633cfc3 6621 /*
55d2375e
SC		 6622 * eager fpu is enabled if PKEY is supported and CR4 is switched
6623 * back on host, so it is safe to read guest PKRU from current
6624 * XSAVE.
3633cfc3 6625 */
55d2375e
SC		 6626 if (static_cpu_has(X86_FEATURE_PKU) &&
6627 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
c806e887 6628 vcpu->arch.pkru = rdpkru();
55d2375e
SC		 6629 if (vcpu->arch.pkru != vmx->host_pkru)
6630 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6631 }
6632
139a12cf 6633 kvm_load_host_xsave_state(vcpu);
1811d979 6634
55d2375e
SC		 6635 vmx->nested.nested_run_pending = 0;
6636 vmx->idt_vectoring_info = 0;
119a9c01 6637
55d2375e 6638 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
beb8d93b
SC		 6639 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6640 kvm_machine_check();
6641
55d2375e
SC		 6642 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6643 return;
608406e2 6644
55d2375e
SC		 6645 vmx->loaded_vmcs->launched = 1;
6646 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6647
55d2375e
SC		 6648 vmx_recover_nmi_blocking(vmx);
6649 vmx_complete_interrupts(vmx);
6650}
2996fca0 6651
55d2375e
SC		 6652static struct kvm *vmx_vm_alloc(void)
6653{
41836839
BG		 6654 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6655 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6656 PAGE_KERNEL);
55d2375e 6657 return &kvm_vmx->kvm;
cf8b84f4
JM		 6658}
6659
55d2375e
SC		 6660static void vmx_vm_free(struct kvm *kvm)
6661{
6f6a657c 6662 kfree(kvm->arch.hyperv.hv_pa_pg);
55d2375e
SC		 6663 vfree(to_kvm_vmx(kvm));
6664}
6665
6666static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6667{
55d2375e 6668 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6669
55d2375e
SC		 6670 if (enable_pml)
6671 vmx_destroy_pml_buffer(vmx);
6672 free_vpid(vmx->vpid);
55d2375e
SC		 6673 nested_vmx_free_vcpu(vcpu);
6674 free_loaded_vmcs(vmx->loaded_vmcs);
55d2375e 6675 kvm_vcpu_uninit(vcpu);
d9a710e5 6676 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
b666a4b6 6677 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
55d2375e
SC		 6678 kmem_cache_free(kvm_vcpu_cache, vmx);
6679}
4704d0be 6680
55d2375e
SC		 6681static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6682{
6683 int err;
41836839 6684 struct vcpu_vmx *vmx;
55d2375e 6685 unsigned long *msr_bitmap;
4be53410 6686 int i, cpu;
7313c698 6687
12b58f4e
SC		 6688 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6689 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6690
41836839 6691 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6692 if (!vmx)
6693 return ERR_PTR(-ENOMEM);
4704d0be 6694
d9a710e5
WL		 6695 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6696 GFP_KERNEL_ACCOUNT);
6697 if (!vmx->vcpu.arch.user_fpu) {
6698 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6699 err = -ENOMEM;
6700 goto free_partial_vcpu;
6701 }
6702
41836839
BG		 6703 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6704 GFP_KERNEL_ACCOUNT);
b666a4b6
MO		 6705 if (!vmx->vcpu.arch.guest_fpu) {
6706 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6707 err = -ENOMEM;
d9a710e5 6708 goto free_user_fpu;
b666a4b6
MO		 6709 }
6710
55d2375e 6711 vmx->vpid = allocate_vpid();
7cdc2d62 6712
55d2375e
SC		 6713 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6714 if (err)
6715 goto free_vcpu;
5f3d5799 6716
55d2375e 6717 err = -ENOMEM;
5f3d5799
JK		 6718
6719 /*
55d2375e
SC		 6720 * If PML is turned on, failure on enabling PML just results in failure
6721 * of creating the vcpu, therefore we can simplify PML logic (by
6722 * avoiding dealing with cases, such as enabling PML partially on vcpus
67b0ae43 6723 * for the guest), etc.
5f3d5799 6724 */
55d2375e 6725 if (enable_pml) {
41836839 6726 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e
SC		 6727 if (!vmx->pml_pg)
6728 goto uninit_vcpu;
6729 }
4704d0be 6730
7d73710d 6731 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
4704d0be 6732
4be53410
XL		 6733 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6734 u32 index = vmx_msr_index[i];
6735 u32 data_low, data_high;
6736 int j = vmx->nmsrs;
6737
6738 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6739 continue;
6740 if (wrmsr_safe(index, data_low, data_high) < 0)
6741 continue;
46f4f0aa 6742
4be53410
XL		 6743 vmx->guest_msrs[j].index = i;
6744 vmx->guest_msrs[j].data = 0;
46f4f0aa
PB		 6745 switch (index) {
6746 case MSR_IA32_TSX_CTRL:
6747 /*
6748 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6749 * let's avoid changing CPUID bits under the host
6750 * kernel's feet.
6751 */
6752 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6753 break;
6754 default:
6755 vmx->guest_msrs[j].mask = -1ull;
6756 break;
6757 }
4be53410
XL		 6758 ++vmx->nmsrs;
6759 }
6760
55d2375e
SC		 6761 err = alloc_loaded_vmcs(&vmx->vmcs01);
6762 if (err < 0)
7d73710d 6763 goto free_pml;
cb61de2f 6764
55d2375e 6765 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6766 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6767 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6768 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6769 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6770 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6771 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6772 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
b5170063
WL		 6773 if (kvm_cstate_in_guest(kvm)) {
6774 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6775 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6776 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6777 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6778 }
55d2375e 6779 vmx->msr_bitmap_mode = 0;
4704d0be 6780
55d2375e
SC		 6781 vmx->loaded_vmcs = &vmx->vmcs01;
6782 cpu = get_cpu();
6783 vmx_vcpu_load(&vmx->vcpu, cpu);
6784 vmx->vcpu.cpu = cpu;
1b84292b 6785 init_vmcs(vmx);
55d2375e
SC		 6786 vmx_vcpu_put(&vmx->vcpu);
6787 put_cpu();
6788 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6789 err = alloc_apic_access_page(kvm);
6790 if (err)
6791 goto free_vmcs;
6792 }
6793
6794 if (enable_ept && !enable_unrestricted_guest) {
6795 err = init_rmode_identity_map(kvm);
6796 if (err)
6797 goto free_vmcs;
6798 }
4704d0be 6799
55d2375e
SC		 6800 if (nested)
6801 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6802 vmx_capability.ept,
6803 kvm_vcpu_apicv_active(&vmx->vcpu));
6804 else
6805 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6806
55d2375e
SC		 6807 vmx->nested.posted_intr_nv = -1;
6808 vmx->nested.current_vmptr = -1ull;
bd18bffc 6809
55d2375e 6810 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
feaf0c7d 6811
6f1e03bc 6812 /*
55d2375e
SC		 6813 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6814 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6815 */
55d2375e
SC		 6816 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6817 vmx->pi_desc.sn = 1;
4704d0be 6818
53963a70
LT		 6819 vmx->ept_pointer = INVALID_PAGE;
6820
55d2375e 6821 return &vmx->vcpu;
4704d0be 6822
55d2375e
SC		 6823free_vmcs:
6824 free_loaded_vmcs(vmx->loaded_vmcs);
55d2375e
SC		 6825free_pml:
6826 vmx_destroy_pml_buffer(vmx);
6827uninit_vcpu:
6828 kvm_vcpu_uninit(&vmx->vcpu);
6829free_vcpu:
6830 free_vpid(vmx->vpid);
b666a4b6 6831 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
d9a710e5
WL		 6832free_user_fpu:
6833 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
b666a4b6 6834free_partial_vcpu:
55d2375e
SC		 6835 kmem_cache_free(kvm_vcpu_cache, vmx);
6836 return ERR_PTR(err);
6837}
36be0b9d 6838
65fd4cb6
TG		 6839#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6840#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
21feb4eb 6841
55d2375e
SC		 6842static int vmx_vm_init(struct kvm *kvm)
6843{
6844 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6845
55d2375e
SC		 6846 if (!ple_gap)
6847 kvm->arch.pause_in_guest = true;
3af18d9c 6848
55d2375e
SC		 6849 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6850 switch (l1tf_mitigation) {
6851 case L1TF_MITIGATION_OFF:
6852 case L1TF_MITIGATION_FLUSH_NOWARN:
6853 /* 'I explicitly don't care' is set */
6854 break;
6855 case L1TF_MITIGATION_FLUSH:
6856 case L1TF_MITIGATION_FLUSH_NOSMT:
6857 case L1TF_MITIGATION_FULL:
6858 /*
6859 * Warn upon starting the first VM in a potentially
6860 * insecure environment.
6861 */
b284909a 6862 if (sched_smt_active())
55d2375e
SC		 6863 pr_warn_once(L1TF_MSG_SMT);
6864 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6865 pr_warn_once(L1TF_MSG_L1D);
6866 break;
6867 case L1TF_MITIGATION_FULL_FORCE:
6868 /* Flush is enforced */
6869 break;
6870 }
6871 }
6872 return 0;
4704d0be
NHE		 6873}
6874
f257d6dc 6875static int __init vmx_check_processor_compat(void)
bd18bffc 6876{
55d2375e
SC		 6877 struct vmcs_config vmcs_conf;
6878 struct vmx_capability vmx_cap;
bd18bffc 6879
55d2375e 6880 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
f257d6dc 6881 return -EIO;
55d2375e
SC		 6882 if (nested)
6883 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6884 enable_apicv);
6885 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6886 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6887 smp_processor_id());
f257d6dc 6888 return -EIO;
bd18bffc 6889 }
f257d6dc 6890 return 0;
bd18bffc
SC		 6891}
6892
55d2375e 6893static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6894{
55d2375e
SC		 6895 u8 cache;
6896 u64 ipat = 0;
bd18bffc 6897
55d2375e
SC		 6898 /* For VT-d and EPT combination
6899 * 1. MMIO: always map as UC
6900 * 2. EPT with VT-d:
6901 * a. VT-d without snooping control feature: can't guarantee the
6902 * result, try to trust guest.
6903 * b. VT-d with snooping control feature: snooping control feature of
6904 * VT-d engine can guarantee the cache correctness. Just set it
6905 * to WB to keep consistent with host. So the same as item 3.
6906 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6907 * consistent with host MTRR
bd18bffc 6908 */
55d2375e
SC		 6909 if (is_mmio) {
6910 cache = MTRR_TYPE_UNCACHABLE;
6911 goto exit;
6912 }
bd18bffc 6913
55d2375e
SC		 6914 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6915 ipat = VMX_EPT_IPAT_BIT;
6916 cache = MTRR_TYPE_WRBACK;
6917 goto exit;
6918 }
bd18bffc 6919
55d2375e
SC		 6920 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6921 ipat = VMX_EPT_IPAT_BIT;
6922 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6923 cache = MTRR_TYPE_WRBACK;
6924 else
6925 cache = MTRR_TYPE_UNCACHABLE;
6926 goto exit;
6927 }
bd18bffc 6928
55d2375e 6929 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6930
55d2375e
SC		 6931exit:
6932 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6933}
bd18bffc 6934
55d2375e
SC		 6935static int vmx_get_lpage_level(void)
6936{
6937 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6938 return PT_DIRECTORY_LEVEL;
6939 else
6940 /* For shadow and EPT supported 1GB page */
6941 return PT_PDPE_LEVEL;
6942}
bd18bffc 6943
fe7f895d 6944static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
55d2375e 6945{
bd18bffc 6946 /*
55d2375e
SC		 6947 * These bits in the secondary execution controls field
6948 * are dynamic, the others are mostly based on the hypervisor
6949 * architecture and the guest's CPUID. Do not touch the
6950 * dynamic bits.
bd18bffc 6951 */
55d2375e
SC		 6952 u32 mask =
6953 SECONDARY_EXEC_SHADOW_VMCS |
6954 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6955 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6956 SECONDARY_EXEC_DESC;
bd18bffc 6957
fe7f895d
SC		 6958 u32 new_ctl = vmx->secondary_exec_control;
6959 u32 cur_ctl = secondary_exec_controls_get(vmx);
bd18bffc 6960
fe7f895d 6961 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6962}
6963
4704d0be 6964/*
55d2375e
SC		 6965 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6966 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6967 */
55d2375e 6968static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6969{
6970 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6971 struct kvm_cpuid_entry2 *entry;
4704d0be 6972
55d2375e
SC		 6973 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6974 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6975
55d2375e
SC		 6976#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6977 if (entry && (entry->_reg & (_cpuid_mask))) \
6978 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6979} while (0)
ff651cb6 6980
55d2375e
SC		 6981 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6982 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6983 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6984 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6985 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6986 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6987 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6988 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6989 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6990 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6991 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6992 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6993 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6994 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6995 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
61ada748 6996
55d2375e
SC		 6997 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6998 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6999 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
7000 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
7001 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
7002 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
c79eb775 7003 cr4_fixed1_update(X86_CR4_LA57, ecx, bit(X86_FEATURE_LA57));
cf3215d9 7004
55d2375e
SC		 7005#undef cr4_fixed1_update
7006}
36c3cc42 7007
55d2375e
SC		 7008static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7009{
7010 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 7011
55d2375e
SC		 7012 if (kvm_mpx_supported()) {
7013 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 7014
55d2375e
SC		 7015 if (mpx_enabled) {
7016 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7017 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7018 } else {
7019 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7020 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7021 }
dccbfcf5 7022 }
55d2375e 7023}
4704d0be 7024
6c0f0bba
LK		 7025static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7026{
7027 struct vcpu_vmx *vmx = to_vmx(vcpu);
7028 struct kvm_cpuid_entry2 *best = NULL;
7029 int i;
7030
7031 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7032 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7033 if (!best)
7034 return;
7035 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7036 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7037 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7038 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7039 }
7040
7041 /* Get the number of configurable Address Ranges for filtering */
7042 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7043 PT_CAP_num_address_ranges);
7044
7045 /* Initialize and clear the no dependency bits */
7046 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7047 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7048
7049 /*
7050 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7051 * will inject an #GP
7052 */
7053 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7054 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7055
7056 /*
7057 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7058 * PSBFreq can be set
7059 */
7060 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7061 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7062 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7063
7064 /*
7065 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7066 * MTCFreq can be set
7067 */
7068 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7069 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7070 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7071
7072 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7073 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7074 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7075 RTIT_CTL_PTW_EN);
7076
7077 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7078 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7079 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7080
7081 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7082 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7083 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7084
7085 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7086 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7087 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7088
7089 /* unmask address range configure area */
7090 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 7091 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 7092}
7093
55d2375e
SC		 7094static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7095{
7096 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 7097
7204160e
AL		 7098 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7099 vcpu->arch.xsaves_enabled = false;
7100
55d2375e
SC		 7101 if (cpu_has_secondary_exec_ctrls()) {
7102 vmx_compute_secondary_exec_control(vmx);
fe7f895d 7103 vmcs_set_secondary_exec_control(vmx);
705699a1 7104 }
4704d0be 7105
55d2375e
SC		 7106 if (nested_vmx_allowed(vcpu))
7107 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
85c9aae9 7108 FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
55d2375e
SC		 7109 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7110 else
7111 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
85c9aae9
JM		 7112 ~(FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
7113 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX);
4f350c6d 7114
55d2375e
SC		 7115 if (nested_vmx_allowed(vcpu)) {
7116 nested_vmx_cr_fixed1_bits_update(vcpu);
7117 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 7118 }
6c0f0bba
LK		 7119
7120 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7121 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7122 update_intel_pt_cfg(vcpu);
b07a5c53
PB		 7123
7124 if (boot_cpu_has(X86_FEATURE_RTM)) {
7125 struct shared_msr_entry *msr;
7126 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7127 if (msr) {
7128 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7129 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7130 }
7131 }
55d2375e 7132}
09abb5e3 7133
55d2375e
SC		 7134static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7135{
7136 if (func == 1 && nested)
7137 entry->ecx |= bit(X86_FEATURE_VMX);
4704d0be
NHE		 7138}
7139
55d2375e 7140static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 7141{
55d2375e 7142 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 7143}
7144
8a76d7f2
JR		 7145static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7146 struct x86_instruction_info *info,
7147 enum x86_intercept_stage stage)
7148{
fb6d4d34
PB		 7149 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7150 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7151
7152 /*
7153 * RDPID causes #UD if disabled through secondary execution controls.
7154 * Because it is marked as EmulateOnUD, we need to intercept it here.
7155 */
7156 if (info->intercept == x86_intercept_rdtscp &&
7157 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7158 ctxt->exception.vector = UD_VECTOR;
7159 ctxt->exception.error_code_valid = false;
7160 return X86EMUL_PROPAGATE_FAULT;
7161 }
7162
7163 /* TODO: check more intercepts... */
8a76d7f2
JR		 7164 return X86EMUL_CONTINUE;
7165}
7166
64672c95
YJ		 7167#ifdef CONFIG_X86_64
7168/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7169static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7170 u64 divisor, u64 *result)
7171{
7172 u64 low = a << shift, high = a >> (64 - shift);
7173
7174 /* To avoid the overflow on divq */
7175 if (high >= divisor)
7176 return 1;
7177
7178 /* Low hold the result, high hold rem which is discarded */
7179 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7180 "rm" (divisor), "0" (low), "1" (high));
7181 *result = low;
7182
7183 return 0;
7184}
7185
f9927982
SC		 7186static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7187 bool *expired)
64672c95 7188{
386c6ddb 7189 struct vcpu_vmx *vmx;
c5ce8235 7190 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
39497d76 7191 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
386c6ddb 7192
0c5f81da
WL		 7193 if (kvm_mwait_in_guest(vcpu->kvm) ||
7194 kvm_can_post_timer_interrupt(vcpu))
386c6ddb
KA		 7195 return -EOPNOTSUPP;
7196
7197 vmx = to_vmx(vcpu);
7198 tscl = rdtsc();
7199 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7200 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
39497d76
SC		 7201 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7202 ktimer->timer_advance_ns);
c5ce8235
WL		 7203
7204 if (delta_tsc > lapic_timer_advance_cycles)
7205 delta_tsc -= lapic_timer_advance_cycles;
7206 else
7207 delta_tsc = 0;
64672c95
YJ		 7208
7209 /* Convert to host delta tsc if tsc scaling is enabled */
7210 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
0967fa1c 7211 delta_tsc && u64_shl_div_u64(delta_tsc,
64672c95 7212 kvm_tsc_scaling_ratio_frac_bits,
0967fa1c 7213 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
64672c95
YJ		 7214 return -ERANGE;
7215
7216 /*
7217 * If the delta tsc can't fit in the 32 bit after the multi shift,
7218 * we can't use the preemption timer.
7219 * It's possible that it fits on later vmentries, but checking
7220 * on every vmentry is costly so we just use an hrtimer.
7221 */
7222 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7223 return -ERANGE;
7224
7225 vmx->hv_deadline_tsc = tscl + delta_tsc;
f9927982
SC		 7226 *expired = !delta_tsc;
7227 return 0;
64672c95
YJ		 7228}
7229
7230static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7231{
f459a707 7232 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7233}
7234#endif
7235
48d89b92 7236static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7237{
b31c114b 7238 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7239 shrink_ple_window(vcpu);
ae97a3b8
RK		 7240}
7241
843e4330
KH		 7242static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7243 struct kvm_memory_slot *slot)
7244{
7245 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7246 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7247}
7248
7249static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7250 struct kvm_memory_slot *slot)
7251{
7252 kvm_mmu_slot_set_dirty(kvm, slot);
7253}
7254
7255static void vmx_flush_log_dirty(struct kvm *kvm)
7256{
7257 kvm_flush_pml_buffers(kvm);
7258}
7259
c5f983f6
BD		 7260static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7261{
7262 struct vmcs12 *vmcs12;
7263 struct vcpu_vmx *vmx = to_vmx(vcpu);
3d5f6beb 7264 gpa_t gpa, dst;
c5f983f6
BD		 7265
7266 if (is_guest_mode(vcpu)) {
7267 WARN_ON_ONCE(vmx->nested.pml_full);
7268
7269 /*
7270 * Check if PML is enabled for the nested guest.
7271 * Whether eptp bit 6 is set is already checked
7272 * as part of A/D emulation.
7273 */
7274 vmcs12 = get_vmcs12(vcpu);
7275 if (!nested_cpu_has_pml(vmcs12))
7276 return 0;
7277
4769886b 7278 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7279 vmx->nested.pml_full = true;
7280 return 1;
7281 }
7282
7283 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
3d5f6beb 7284 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
c5f983f6 7285
3d5f6beb
KA		 7286 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7287 offset_in_page(dst), sizeof(gpa)))
c5f983f6
BD		 7288 return 0;
7289
3d5f6beb 7290 vmcs12->guest_pml_index--;
c5f983f6
BD		 7291 }
7292
7293 return 0;
7294}
7295
843e4330
KH		 7296static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7297 struct kvm_memory_slot *memslot,
7298 gfn_t offset, unsigned long mask)
7299{
7300 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7301}
7302
cd39e117
PB		 7303static void __pi_post_block(struct kvm_vcpu *vcpu)
7304{
7305 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7306 struct pi_desc old, new;
7307 unsigned int dest;
cd39e117
PB		 7308
7309 do {
7310 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7311 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7312 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7313
7314 dest = cpu_physical_id(vcpu->cpu);
7315
7316 if (x2apic_enabled())
7317 new.ndst = dest;
7318 else
7319 new.ndst = (dest << 8) & 0xFF00;
7320
cd39e117
PB		 7321 /* set 'NV' to 'notification vector' */
7322 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7323 } while (cmpxchg64(&pi_desc->control, old.control,
7324 new.control) != old.control);
cd39e117 7325
8b306e2f
PB		 7326 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7327 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7328 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7329 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7330 vcpu->pre_pcpu = -1;
7331 }
7332}
7333
bf9f6ac8
FW		 7334/*
7335 * This routine does the following things for vCPU which is going
7336 * to be blocked if VT-d PI is enabled.
7337 * - Store the vCPU to the wakeup list, so when interrupts happen
7338 * we can find the right vCPU to wake up.
7339 * - Change the Posted-interrupt descriptor as below:
7340 * 'NDST' <-- vcpu->pre_pcpu
7341 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7342 * - If 'ON' is set during this process, which means at least one
7343 * interrupt is posted for this vCPU, we cannot block it, in
7344 * this case, return 1, otherwise, return 0.
7345 *
7346 */
bc22512b 7347static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7348{
bf9f6ac8
FW		 7349 unsigned int dest;
7350 struct pi_desc old, new;
7351 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7352
7353 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7354 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7355 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7356 return 0;
7357
8b306e2f
PB		 7358 WARN_ON(irqs_disabled());
7359 local_irq_disable();
7360 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7361 vcpu->pre_pcpu = vcpu->cpu;
7362 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7363 list_add_tail(&vcpu->blocked_vcpu_list,
7364 &per_cpu(blocked_vcpu_on_cpu,
7365 vcpu->pre_pcpu));
7366 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7367 }
bf9f6ac8
FW		 7368
7369 do {
7370 old.control = new.control = pi_desc->control;
7371
bf9f6ac8
FW		 7372 WARN((pi_desc->sn == 1),
7373 "Warning: SN field of posted-interrupts "
7374 "is set before blocking\n");
7375
7376 /*
7377 * Since vCPU can be preempted during this process,
7378 * vcpu->cpu could be different with pre_pcpu, we
7379 * need to set pre_pcpu as the destination of wakeup
7380 * notification event, then we can find the right vCPU
7381 * to wakeup in wakeup handler if interrupts happen
7382 * when the vCPU is in blocked state.
7383 */
7384 dest = cpu_physical_id(vcpu->pre_pcpu);
7385
7386 if (x2apic_enabled())
7387 new.ndst = dest;
7388 else
7389 new.ndst = (dest << 8) & 0xFF00;
7390
7391 /* set 'NV' to 'wakeup vector' */
7392 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7393 } while (cmpxchg64(&pi_desc->control, old.control,
7394 new.control) != old.control);
bf9f6ac8 7395
8b306e2f
PB		 7396 /* We should not block the vCPU if an interrupt is posted for it. */
7397 if (pi_test_on(pi_desc) == 1)
7398 __pi_post_block(vcpu);
7399
7400 local_irq_enable();
7401 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7402}
7403
bc22512b
YJ		 7404static int vmx_pre_block(struct kvm_vcpu *vcpu)
7405{
7406 if (pi_pre_block(vcpu))
7407 return 1;
7408
64672c95
YJ		 7409 if (kvm_lapic_hv_timer_in_use(vcpu))
7410 kvm_lapic_switch_to_sw_timer(vcpu);
7411
bc22512b
YJ		 7412 return 0;
7413}
7414
7415static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7416{
8b306e2f 7417 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7418 return;
7419
8b306e2f
PB		 7420 WARN_ON(irqs_disabled());
7421 local_irq_disable();
cd39e117 7422 __pi_post_block(vcpu);
8b306e2f 7423 local_irq_enable();
bf9f6ac8
FW		 7424}
7425
bc22512b
YJ		 7426static void vmx_post_block(struct kvm_vcpu *vcpu)
7427{
64672c95
YJ		 7428 if (kvm_x86_ops->set_hv_timer)
7429 kvm_lapic_switch_to_hv_timer(vcpu);
7430
bc22512b
YJ		 7431 pi_post_block(vcpu);
7432}
7433
efc64404
FW		 7434/*
7435 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7436 *
7437 * @kvm: kvm
7438 * @host_irq: host irq of the interrupt
7439 * @guest_irq: gsi of the interrupt
7440 * @set: set or unset PI
7441 * returns 0 on success, < 0 on failure
7442 */
7443static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7444 uint32_t guest_irq, bool set)
7445{
7446 struct kvm_kernel_irq_routing_entry *e;
7447 struct kvm_irq_routing_table *irq_rt;
7448 struct kvm_lapic_irq irq;
7449 struct kvm_vcpu *vcpu;
7450 struct vcpu_data vcpu_info;
3a8b0677 7451 int idx, ret = 0;
efc64404
FW		 7452
7453 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7454 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7455 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7456 return 0;
7457
7458 idx = srcu_read_lock(&kvm->irq_srcu);
7459 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7460 if (guest_irq >= irq_rt->nr_rt_entries ||
7461 hlist_empty(&irq_rt->map[guest_irq])) {
7462 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7463 guest_irq, irq_rt->nr_rt_entries);
7464 goto out;
7465 }
efc64404
FW		 7466
7467 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7468 if (e->type != KVM_IRQ_ROUTING_MSI)
7469 continue;
7470 /*
7471 * VT-d PI cannot support posting multicast/broadcast
7472 * interrupts to a vCPU, we still use interrupt remapping
7473 * for these kind of interrupts.
7474 *
7475 * For lowest-priority interrupts, we only support
7476 * those with single CPU as the destination, e.g. user
7477 * configures the interrupts via /proc/irq or uses
7478 * irqbalance to make the interrupts single-CPU.
7479 *
7480 * We will support full lowest-priority interrupt later.
fdcf7562
AG		 7481 *
7482 * In addition, we can only inject generic interrupts using
7483 * the PI mechanism, refuse to route others through it.
efc64404
FW		 7484 */
7485
37131313 7486 kvm_set_msi_irq(kvm, e, &irq);
fdcf7562
AG		 7487 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7488 !kvm_irq_is_postable(&irq)) {
23a1c257
FW		 7489 /*
7490 * Make sure the IRTE is in remapped mode if
7491 * we don't handle it in posted mode.
7492 */
7493 ret = irq_set_vcpu_affinity(host_irq, NULL);
7494 if (ret < 0) {
7495 printk(KERN_INFO
7496 "failed to back to remapped mode, irq: %u\n",
7497 host_irq);
7498 goto out;
7499 }
7500
efc64404 7501 continue;
23a1c257 7502 }
efc64404
FW		 7503
7504 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7505 vcpu_info.vector = irq.vector;
7506
2698d82e 7507 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7508 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7509
7510 if (set)
7511 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7512 else
efc64404 7513 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7514
7515 if (ret < 0) {
7516 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7517 __func__);
7518 goto out;
7519 }
7520 }
7521
7522 ret = 0;
7523out:
7524 srcu_read_unlock(&kvm->irq_srcu, idx);
7525 return ret;
7526}
7527
c45dcc71
AR		 7528static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7529{
7530 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7531 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7532 FEATURE_CONTROL_LMCE;
7533 else
7534 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7535 ~FEATURE_CONTROL_LMCE;
7536}
7537
72d7b374
LP		 7538static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7539{
72e9cbdb
LP		 7540 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7541 if (to_vmx(vcpu)->nested.nested_run_pending)
7542 return 0;
72d7b374
LP		 7543 return 1;
7544}
7545
0234bf88
LP		 7546static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7547{
72e9cbdb
LP		 7548 struct vcpu_vmx *vmx = to_vmx(vcpu);
7549
7550 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7551 if (vmx->nested.smm.guest_mode)
7552 nested_vmx_vmexit(vcpu, -1, 0, 0);
7553
7554 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7555 vmx->nested.vmxon = false;
caa057a2 7556 vmx_clear_hlt(vcpu);
0234bf88
LP		 7557 return 0;
7558}
7559
ed19321f 7560static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7561{
72e9cbdb
LP		 7562 struct vcpu_vmx *vmx = to_vmx(vcpu);
7563 int ret;
7564
7565 if (vmx->nested.smm.vmxon) {
7566 vmx->nested.vmxon = true;
7567 vmx->nested.smm.vmxon = false;
7568 }
7569
7570 if (vmx->nested.smm.guest_mode) {
a633e41e 7571 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7572 if (ret)
7573 return ret;
7574
7575 vmx->nested.smm.guest_mode = false;
7576 }
0234bf88
LP		 7577 return 0;
7578}
7579
cc3d967f
LP		 7580static int enable_smi_window(struct kvm_vcpu *vcpu)
7581{
7582 return 0;
7583}
7584
05d5a486
SB		 7585static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7586{
9481b7f1 7587 return false;
05d5a486
SB		 7588}
7589
4b9852f4
LA		 7590static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7591{
7592 return to_vmx(vcpu)->nested.vmxon;
7593}
7594
a3203381
SC		 7595static __init int hardware_setup(void)
7596{
7597 unsigned long host_bndcfgs;
2342080c 7598 struct desc_ptr dt;
a3203381
SC		 7599 int r, i;
7600
7601 rdmsrl_safe(MSR_EFER, &host_efer);
7602
2342080c
SC		 7603 store_idt(&dt);
7604 host_idt_base = dt.address;
7605
a3203381
SC		 7606 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7607 kvm_define_shared_msr(i, vmx_msr_index[i]);
7608
7609 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7610 return -EIO;
7611
7612 if (boot_cpu_has(X86_FEATURE_NX))
7613 kvm_enable_efer_bits(EFER_NX);
7614
7615 if (boot_cpu_has(X86_FEATURE_MPX)) {
7616 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7617 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7618 }
7619
a3203381
SC		 7620 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7621 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7622 enable_vpid = 0;
7623
7624 if (!cpu_has_vmx_ept() ||
7625 !cpu_has_vmx_ept_4levels() ||
7626 !cpu_has_vmx_ept_mt_wb() ||
7627 !cpu_has_vmx_invept_global())
7628 enable_ept = 0;
7629
7630 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7631 enable_ept_ad_bits = 0;
7632
7633 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7634 enable_unrestricted_guest = 0;
7635
7636 if (!cpu_has_vmx_flexpriority())
7637 flexpriority_enabled = 0;
7638
7639 if (!cpu_has_virtual_nmis())
7640 enable_vnmi = 0;
7641
7642 /*
7643 * set_apic_access_page_addr() is used to reload apic access
7644 * page upon invalidation. No need to do anything if not
7645 * using the APIC_ACCESS_ADDR VMCS field.
7646 */
7647 if (!flexpriority_enabled)
7648 kvm_x86_ops->set_apic_access_page_addr = NULL;
7649
7650 if (!cpu_has_vmx_tpr_shadow())
7651 kvm_x86_ops->update_cr8_intercept = NULL;
7652
7653 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7654 kvm_disable_largepages();
7655
7656#if IS_ENABLED(CONFIG_HYPERV)
7657 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7658 && enable_ept) {
7659 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7660 kvm_x86_ops->tlb_remote_flush_with_range =
7661 hv_remote_flush_tlb_with_range;
7662 }
a3203381
SC		 7663#endif
7664
7665 if (!cpu_has_vmx_ple()) {
7666 ple_gap = 0;
7667 ple_window = 0;
7668 ple_window_grow = 0;
7669 ple_window_max = 0;
7670 ple_window_shrink = 0;
7671 }
7672
7673 if (!cpu_has_vmx_apicv()) {
7674 enable_apicv = 0;
7675 kvm_x86_ops->sync_pir_to_irr = NULL;
7676 }
7677
7678 if (cpu_has_vmx_tsc_scaling()) {
7679 kvm_has_tsc_control = true;
7680 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7681 kvm_tsc_scaling_ratio_frac_bits = 48;
7682 }
7683
7684 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7685
7686 if (enable_ept)
7687 vmx_enable_tdp();
7688 else
7689 kvm_disable_tdp();
7690
a3203381
SC		 7691 /*
7692 * Only enable PML when hardware supports PML feature, and both EPT
7693 * and EPT A/D bit features are enabled -- PML depends on them to work.
7694 */
7695 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7696 enable_pml = 0;
7697
7698 if (!enable_pml) {
7699 kvm_x86_ops->slot_enable_log_dirty = NULL;
7700 kvm_x86_ops->slot_disable_log_dirty = NULL;
7701 kvm_x86_ops->flush_log_dirty = NULL;
7702 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7703 }
7704
7705 if (!cpu_has_vmx_preemption_timer())
804939ea 7706 enable_preemption_timer = false;
a3203381 7707
804939ea
SC		 7708 if (enable_preemption_timer) {
7709 u64 use_timer_freq = 5000ULL * 1000 * 1000;
a3203381
SC		 7710 u64 vmx_msr;
7711
7712 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7713 cpu_preemption_timer_multi =
7714 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
804939ea
SC		 7715
7716 if (tsc_khz)
7717 use_timer_freq = (u64)tsc_khz * 1000;
7718 use_timer_freq >>= cpu_preemption_timer_multi;
7719
7720 /*
7721 * KVM "disables" the preemption timer by setting it to its max
7722 * value. Don't use the timer if it might cause spurious exits
7723 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7724 */
7725 if (use_timer_freq > 0xffffffffu / 10)
7726 enable_preemption_timer = false;
7727 }
7728
7729 if (!enable_preemption_timer) {
a3203381
SC		 7730 kvm_x86_ops->set_hv_timer = NULL;
7731 kvm_x86_ops->cancel_hv_timer = NULL;
804939ea 7732 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
a3203381
SC		 7733 }
7734
a3203381 7735 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7736
7737 kvm_mce_cap_supported |= MCG_LMCE_P;
7738
f99e3daf
CP		 7739 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7740 return -EINVAL;
7741 if (!enable_ept || !cpu_has_vmx_intel_pt())
7742 pt_mode = PT_MODE_SYSTEM;
7743
a3203381 7744 if (nested) {
3e8eaccc
SC		 7745 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7746 vmx_capability.ept, enable_apicv);
7747
e4027cfa 7748 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7749 if (r)
7750 return r;
7751 }
7752
7753 r = alloc_kvm_area();
7754 if (r)
7755 nested_vmx_hardware_unsetup();
7756 return r;
7757}
7758
7759static __exit void hardware_unsetup(void)
7760{
7761 if (nested)
7762 nested_vmx_hardware_unsetup();
7763
7764 free_kvm_area();
7765}
7766
404f6aac 7767static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7768 .cpu_has_kvm_support = cpu_has_kvm_support,
7769 .disabled_by_bios = vmx_disabled_by_bios,
7770 .hardware_setup = hardware_setup,
7771 .hardware_unsetup = hardware_unsetup,
002c7f7c 7772 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7773 .hardware_enable = hardware_enable,
7774 .hardware_disable = hardware_disable,
04547156 7775 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7776 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7777
b31c114b 7778 .vm_init = vmx_vm_init,
434a1e94
SC		 7779 .vm_alloc = vmx_vm_alloc,
7780 .vm_free = vmx_vm_free,
b31c114b 7781
6aa8b732
AK		 7782 .vcpu_create = vmx_create_vcpu,
7783 .vcpu_free = vmx_free_vcpu,
04d2cc77 7784 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7785
6d6095bd 7786 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7787 .vcpu_load = vmx_vcpu_load,
7788 .vcpu_put = vmx_vcpu_put,
7789
a96036b8 7790 .update_bp_intercept = update_exception_bitmap,
801e459a 7791 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7792 .get_msr = vmx_get_msr,
7793 .set_msr = vmx_set_msr,
7794 .get_segment_base = vmx_get_segment_base,
7795 .get_segment = vmx_get_segment,
7796 .set_segment = vmx_set_segment,
2e4d2653 7797 .get_cpl = vmx_get_cpl,
6aa8b732 7798 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7799 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 7800 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7801 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7802 .set_cr3 = vmx_set_cr3,
7803 .set_cr4 = vmx_set_cr4,
6aa8b732 7804 .set_efer = vmx_set_efer,
6aa8b732
AK		 7805 .get_idt = vmx_get_idt,
7806 .set_idt = vmx_set_idt,
7807 .get_gdt = vmx_get_gdt,
7808 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7809 .get_dr6 = vmx_get_dr6,
7810 .set_dr6 = vmx_set_dr6,
020df079 7811 .set_dr7 = vmx_set_dr7,
81908bf4 7812 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7813 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7814 .get_rflags = vmx_get_rflags,
7815 .set_rflags = vmx_set_rflags,
be94f6b7 7816
6aa8b732 7817 .tlb_flush = vmx_flush_tlb,
faff8758 7818 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7819
6aa8b732 7820 .run = vmx_vcpu_run,
6062d012 7821 .handle_exit = vmx_handle_exit,
1957aa63 7822 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7823 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7824 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7825 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7826 .set_irq = vmx_inject_irq,
95ba8273 7827 .set_nmi = vmx_inject_nmi,
298101da 7828 .queue_exception = vmx_queue_exception,
b463a6f7 7829 .cancel_injection = vmx_cancel_injection,
78646121 7830 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7831 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7832 .get_nmi_mask = vmx_get_nmi_mask,
7833 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7834 .enable_nmi_window = enable_nmi_window,
7835 .enable_irq_window = enable_irq_window,
7836 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7837 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7838 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS		 7839 .get_enable_apicv = vmx_get_enable_apicv,
7840 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7841 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7842 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ		 7843 .hwapic_irr_update = vmx_hwapic_irr_update,
7844 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7845 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7846 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7847 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
17e433b5 7848 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
95ba8273 7849
cbc94022 7850 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7851 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7852 .get_tdp_level = get_ept_level,
4b12f0de 7853 .get_mt_mask = vmx_get_mt_mask,
229456fc 7854
586f9607 7855 .get_exit_info = vmx_get_exit_info,
586f9607 7856
17cc3935 7857 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7858
7859 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7860
7861 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7862 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7863
7864 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7865
7866 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7867
e79f245d 7868 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7869 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7870
7871 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7872
7873 .check_intercept = vmx_check_intercept,
95b5a48c 7874 .handle_exit_irqoff = vmx_handle_exit_irqoff,
da8999d3 7875 .mpx_supported = vmx_mpx_supported,
55412b2e 7876 .xsaves_supported = vmx_xsaves_supported,
66336cab 7877 .umip_emulated = vmx_umip_emulated,
86f5201d 7878 .pt_supported = vmx_pt_supported,
b6b8a145 7879
d264ee0c 7880 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7881
7882 .sched_in = vmx_sched_in,
843e4330
KH		 7883
7884 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7885 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7886 .flush_log_dirty = vmx_flush_log_dirty,
7887 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7888 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7889
bf9f6ac8
FW		 7890 .pre_block = vmx_pre_block,
7891 .post_block = vmx_post_block,
7892
25462f7f 7893 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7894
7895 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7896
7897#ifdef CONFIG_X86_64
7898 .set_hv_timer = vmx_set_hv_timer,
7899 .cancel_hv_timer = vmx_cancel_hv_timer,
7900#endif
c45dcc71
AR		 7901
7902 .setup_mce = vmx_setup_mce,
0234bf88 7903
72d7b374 7904 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7905 .pre_enter_smm = vmx_pre_enter_smm,
7906 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7907 .enable_smi_window = enable_smi_window,
57b119da 7908
e4027cfa
SC		 7909 .check_nested_events = NULL,
7910 .get_nested_state = NULL,
7911 .set_nested_state = NULL,
7912 .get_vmcs12_pages = NULL,
7913 .nested_enable_evmcs = NULL,
ea152987 7914 .nested_get_evmcs_version = NULL,
05d5a486 7915 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
4b9852f4 7916 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
6aa8b732
AK		 7917};
7918
72c6d2db 7919static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7920{
7921 if (vmx_l1d_flush_pages) {
7922 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7923 vmx_l1d_flush_pages = NULL;
7924 }
72c6d2db
TG		 7925 /* Restore state so sysfs ignores VMX */
7926 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7927}
7928
a7b9020b
TG		 7929static void vmx_exit(void)
7930{
7931#ifdef CONFIG_KEXEC_CORE
7932 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7933 synchronize_rcu();
7934#endif
7935
7936 kvm_exit();
7937
7938#if IS_ENABLED(CONFIG_HYPERV)
7939 if (static_branch_unlikely(&enable_evmcs)) {
7940 int cpu;
7941 struct hv_vp_assist_page *vp_ap;
7942 /*
7943 * Reset everything to support using non-enlightened VMCS
7944 * access later (e.g. when we reload the module with
7945 * enlightened_vmcs=0)
7946 */
7947 for_each_online_cpu(cpu) {
7948 vp_ap = hv_get_vp_assist_page(cpu);
7949
7950 if (!vp_ap)
7951 continue;
7952
6f6a657c 7953 vp_ap->nested_control.features.directhypercall = 0;
a7b9020b
TG		 7954 vp_ap->current_nested_vmcs = 0;
7955 vp_ap->enlighten_vmentry = 0;
7956 }
7957
7958 static_branch_disable(&enable_evmcs);
7959 }
7960#endif
7961 vmx_cleanup_l1d_flush();
7962}
7963module_exit(vmx_exit);
7964
6aa8b732
AK		 7965static int __init vmx_init(void)
7966{
773e8a04
VK		 7967 int r;
7968
7969#if IS_ENABLED(CONFIG_HYPERV)
7970 /*
7971 * Enlightened VMCS usage should be recommended and the host needs
7972 * to support eVMCS v1 or above. We can also disable eVMCS support
7973 * with module parameter.
7974 */
7975 if (enlightened_vmcs &&
7976 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7977 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7978 KVM_EVMCS_VERSION) {
7979 int cpu;
7980
7981 /* Check that we have assist pages on all online CPUs */
7982 for_each_online_cpu(cpu) {
7983 if (!hv_get_vp_assist_page(cpu)) {
7984 enlightened_vmcs = false;
7985 break;
7986 }
7987 }
7988
7989 if (enlightened_vmcs) {
7990 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7991 static_branch_enable(&enable_evmcs);
7992 }
6f6a657c
VK		 7993
7994 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7995 vmx_x86_ops.enable_direct_tlbflush
7996 = hv_enable_direct_tlbflush;
7997
773e8a04
VK		 7998 } else {
7999 enlightened_vmcs = false;
8000 }
8001#endif
8002
8003 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 8004 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8005 if (r)
34a1cd60 8006 return r;
25c5f225 8007
a7b9020b 8008 /*
7db92e16
TG		 8009 * Must be called after kvm_init() so enable_ept is properly set
8010 * up. Hand the parameter mitigation value in which was stored in
8011 * the pre module init parser. If no parameter was given, it will
8012 * contain 'auto' which will be turned into the default 'cond'
8013 * mitigation mode.
8014 */
19a36d32
WL		 8015 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8016 if (r) {
8017 vmx_exit();
8018 return r;
a47dd5f0 8019 }
25c5f225 8020
2965faa5 8021#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 8022 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8023 crash_vmclear_local_loaded_vmcss);
8024#endif
21ebf53b 8025 vmx_check_vmcs12_offsets();
8f536b76 8026
fdef3ad1 8027 return 0;
6aa8b732 8028}
a7b9020b 8029module_init(vmx_init);
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