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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
6aa8b732 AK |
14 | */ |
15 | ||
199b118a SC |
16 | #include <linux/highmem.h> |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/kernel.h> | |
edf88417 | 19 | #include <linux/kvm_host.h> |
6aa8b732 | 20 | #include <linux/module.h> |
c7addb90 | 21 | #include <linux/moduleparam.h> |
e9bda3b3 | 22 | #include <linux/mod_devicetable.h> |
199b118a | 23 | #include <linux/mm.h> |
00089c04 | 24 | #include <linux/objtool.h> |
199b118a | 25 | #include <linux/sched.h> |
b284909a | 26 | #include <linux/sched/smt.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
cafd6659 | 28 | #include <linux/tboot.h> |
199b118a | 29 | #include <linux/trace_events.h> |
72c3c0fe | 30 | #include <linux/entry-kvm.h> |
e495606d | 31 | |
199b118a | 32 | #include <asm/apic.h> |
fd8ca6da | 33 | #include <asm/asm.h> |
28b835d6 | 34 | #include <asm/cpu.h> |
ba5bade4 | 35 | #include <asm/cpu_device_id.h> |
199b118a | 36 | #include <asm/debugreg.h> |
3b3be0d1 | 37 | #include <asm/desc.h> |
952f07ec | 38 | #include <asm/fpu/internal.h> |
8c99fa01 | 39 | #include <asm/idtentry.h> |
199b118a | 40 | #include <asm/io.h> |
efc64404 | 41 | #include <asm/irq_remapping.h> |
199b118a SC |
42 | #include <asm/kexec.h> |
43 | #include <asm/perf_event.h> | |
d6e41f11 | 44 | #include <asm/mmu_context.h> |
773e8a04 | 45 | #include <asm/mshyperv.h> |
b10c307f | 46 | #include <asm/mwait.h> |
199b118a SC |
47 | #include <asm/spec-ctrl.h> |
48 | #include <asm/virtext.h> | |
49 | #include <asm/vmx.h> | |
6aa8b732 | 50 | |
3077c191 | 51 | #include "capabilities.h" |
199b118a | 52 | #include "cpuid.h" |
4cebd747 | 53 | #include "evmcs.h" |
199b118a SC |
54 | #include "irq.h" |
55 | #include "kvm_cache_regs.h" | |
56 | #include "lapic.h" | |
57 | #include "mmu.h" | |
55d2375e | 58 | #include "nested.h" |
25462f7f | 59 | #include "pmu.h" |
199b118a | 60 | #include "trace.h" |
cb1d474b | 61 | #include "vmcs.h" |
609363cf | 62 | #include "vmcs12.h" |
89b0c9f5 | 63 | #include "vmx.h" |
199b118a | 64 | #include "x86.h" |
229456fc | 65 | |
6aa8b732 AK |
66 | MODULE_AUTHOR("Qumranet"); |
67 | MODULE_LICENSE("GPL"); | |
68 | ||
575b255c | 69 | #ifdef MODULE |
e9bda3b3 | 70 | static const struct x86_cpu_id vmx_cpu_id[] = { |
320debe5 | 71 | X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL), |
e9bda3b3 JT |
72 | {} |
73 | }; | |
74 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
575b255c | 75 | #endif |
e9bda3b3 | 76 | |
2c4fd91d | 77 | bool __read_mostly enable_vpid = 1; |
736caefe | 78 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 79 | |
d02fcf50 PB |
80 | static bool __read_mostly enable_vnmi = 1; |
81 | module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); | |
82 | ||
2c4fd91d | 83 | bool __read_mostly flexpriority_enabled = 1; |
736caefe | 84 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 85 | |
2c4fd91d | 86 | bool __read_mostly enable_ept = 1; |
736caefe | 87 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 88 | |
2c4fd91d | 89 | bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
90 | module_param_named(unrestricted_guest, |
91 | enable_unrestricted_guest, bool, S_IRUGO); | |
92 | ||
2c4fd91d | 93 | bool __read_mostly enable_ept_ad_bits = 1; |
83c3a331 XH |
94 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); |
95 | ||
a27685c3 | 96 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 97 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 98 | |
476bc001 | 99 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
100 | module_param(fasteoi, bool, S_IRUGO); |
101 | ||
a4443267 | 102 | bool __read_mostly enable_apicv = 1; |
01e439be | 103 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 104 | |
801d3424 NHE |
105 | /* |
106 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
107 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
108 | * use VMX instructions. | |
109 | */ | |
1e58e5e5 | 110 | static bool __read_mostly nested = 1; |
801d3424 NHE |
111 | module_param(nested, bool, S_IRUGO); |
112 | ||
2c4fd91d | 113 | bool __read_mostly enable_pml = 1; |
843e4330 KH |
114 | module_param_named(pml, enable_pml, bool, S_IRUGO); |
115 | ||
6f2f8453 PB |
116 | static bool __read_mostly dump_invalid_vmcs = 0; |
117 | module_param(dump_invalid_vmcs, bool, 0644); | |
118 | ||
904e14fb PB |
119 | #define MSR_BITMAP_MODE_X2APIC 1 |
120 | #define MSR_BITMAP_MODE_X2APIC_APICV 2 | |
904e14fb | 121 | |
64903d61 HZ |
122 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
123 | ||
64672c95 YJ |
124 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
125 | static int __read_mostly cpu_preemption_timer_multi; | |
126 | static bool __read_mostly enable_preemption_timer = 1; | |
127 | #ifdef CONFIG_X86_64 | |
128 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
129 | #endif | |
130 | ||
b96e6506 MG |
131 | extern bool __read_mostly allow_smaller_maxphyaddr; |
132 | module_param(allow_smaller_maxphyaddr, bool, S_IRUGO); | |
133 | ||
3de6347b | 134 | #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) |
1706bd0c SC |
135 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE |
136 | #define KVM_VM_CR0_ALWAYS_ON \ | |
137 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ | |
138 | X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) | |
4c38609a | 139 | |
5dc1f044 | 140 | #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE |
cdc0e244 AK |
141 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
142 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
143 | ||
78ac8b47 AK |
144 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
145 | ||
bf8c55d8 CP |
146 | #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ |
147 | RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ | |
148 | RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ | |
149 | RTIT_STATUS_BYTECNT)) | |
150 | ||
3eb90017 AG |
151 | /* |
152 | * List of MSRs that can be directly passed to the guest. | |
153 | * In addition to these x2apic and PT MSRs are handled specially. | |
154 | */ | |
155 | static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = { | |
156 | MSR_IA32_SPEC_CTRL, | |
157 | MSR_IA32_PRED_CMD, | |
158 | MSR_IA32_TSC, | |
200705df | 159 | #ifdef CONFIG_X86_64 |
3eb90017 AG |
160 | MSR_FS_BASE, |
161 | MSR_GS_BASE, | |
162 | MSR_KERNEL_GS_BASE, | |
200705df | 163 | #endif |
3eb90017 AG |
164 | MSR_IA32_SYSENTER_CS, |
165 | MSR_IA32_SYSENTER_ESP, | |
166 | MSR_IA32_SYSENTER_EIP, | |
167 | MSR_CORE_C1_RES, | |
168 | MSR_CORE_C3_RESIDENCY, | |
169 | MSR_CORE_C6_RESIDENCY, | |
170 | MSR_CORE_C7_RESIDENCY, | |
171 | }; | |
bf8c55d8 | 172 | |
4b8d54f9 ZE |
173 | /* |
174 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
175 | * ple_gap: upper bound on the amount of time between two successive | |
176 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 177 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
178 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
179 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
180 | * less than 2^12 cycles | |
181 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
182 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
183 | */ | |
c8e88717 | 184 | static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; |
a87c99e6 | 185 | module_param(ple_gap, uint, 0444); |
b4a2d31d | 186 | |
7fbc85a5 BM |
187 | static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; |
188 | module_param(ple_window, uint, 0444); | |
4b8d54f9 | 189 | |
b4a2d31d | 190 | /* Default doubles per-vcpu window every exit. */ |
c8e88717 | 191 | static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; |
7fbc85a5 | 192 | module_param(ple_window_grow, uint, 0444); |
b4a2d31d RK |
193 | |
194 | /* Default resets per-vcpu window every exit to ple_window. */ | |
c8e88717 | 195 | static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; |
7fbc85a5 | 196 | module_param(ple_window_shrink, uint, 0444); |
b4a2d31d RK |
197 | |
198 | /* Default is to compute the maximum so we can never overflow. */ | |
7fbc85a5 BM |
199 | static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; |
200 | module_param(ple_window_max, uint, 0444); | |
b4a2d31d | 201 | |
f99e3daf CP |
202 | /* Default is SYSTEM mode, 1 for host-guest mode */ |
203 | int __read_mostly pt_mode = PT_MODE_SYSTEM; | |
204 | module_param(pt_mode, int, S_IRUGO); | |
205 | ||
a399477e | 206 | static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); |
427362a1 | 207 | static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); |
dd4bfa73 | 208 | static DEFINE_MUTEX(vmx_l1d_flush_mutex); |
a399477e | 209 | |
7db92e16 TG |
210 | /* Storage for pre module init parameter parsing */ |
211 | static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; | |
a399477e KRW |
212 | |
213 | static const struct { | |
214 | const char *option; | |
0027ff2a | 215 | bool for_parse; |
a399477e | 216 | } vmentry_l1d_param[] = { |
0027ff2a PB |
217 | [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, |
218 | [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, | |
219 | [VMENTER_L1D_FLUSH_COND] = {"cond", true}, | |
220 | [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, | |
221 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, | |
222 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, | |
a399477e KRW |
223 | }; |
224 | ||
7db92e16 TG |
225 | #define L1D_CACHE_ORDER 4 |
226 | static void *vmx_l1d_flush_pages; | |
227 | ||
228 | static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) | |
a399477e | 229 | { |
7db92e16 | 230 | struct page *page; |
288d152c | 231 | unsigned int i; |
a399477e | 232 | |
19a36d32 WL |
233 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) { |
234 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; | |
235 | return 0; | |
236 | } | |
237 | ||
7db92e16 TG |
238 | if (!enable_ept) { |
239 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; | |
240 | return 0; | |
a399477e KRW |
241 | } |
242 | ||
d806afa4 YW |
243 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { |
244 | u64 msr; | |
245 | ||
246 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); | |
247 | if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { | |
248 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; | |
249 | return 0; | |
250 | } | |
251 | } | |
8e0b2b91 | 252 | |
d90a7a0e JK |
253 | /* If set to auto use the default l1tf mitigation method */ |
254 | if (l1tf == VMENTER_L1D_FLUSH_AUTO) { | |
255 | switch (l1tf_mitigation) { | |
256 | case L1TF_MITIGATION_OFF: | |
257 | l1tf = VMENTER_L1D_FLUSH_NEVER; | |
258 | break; | |
259 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
260 | case L1TF_MITIGATION_FLUSH: | |
261 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
262 | l1tf = VMENTER_L1D_FLUSH_COND; | |
263 | break; | |
264 | case L1TF_MITIGATION_FULL: | |
265 | case L1TF_MITIGATION_FULL_FORCE: | |
266 | l1tf = VMENTER_L1D_FLUSH_ALWAYS; | |
267 | break; | |
268 | } | |
269 | } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { | |
270 | l1tf = VMENTER_L1D_FLUSH_ALWAYS; | |
271 | } | |
272 | ||
7db92e16 TG |
273 | if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && |
274 | !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { | |
41836839 BG |
275 | /* |
276 | * This allocation for vmx_l1d_flush_pages is not tied to a VM | |
277 | * lifetime and so should not be charged to a memcg. | |
278 | */ | |
7db92e16 TG |
279 | page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); |
280 | if (!page) | |
281 | return -ENOMEM; | |
282 | vmx_l1d_flush_pages = page_address(page); | |
288d152c NS |
283 | |
284 | /* | |
285 | * Initialize each page with a different pattern in | |
286 | * order to protect against KSM in the nested | |
287 | * virtualization case. | |
288 | */ | |
289 | for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { | |
290 | memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, | |
291 | PAGE_SIZE); | |
292 | } | |
7db92e16 TG |
293 | } |
294 | ||
295 | l1tf_vmx_mitigation = l1tf; | |
296 | ||
895ae47f TG |
297 | if (l1tf != VMENTER_L1D_FLUSH_NEVER) |
298 | static_branch_enable(&vmx_l1d_should_flush); | |
299 | else | |
300 | static_branch_disable(&vmx_l1d_should_flush); | |
4c6523ec | 301 | |
427362a1 NS |
302 | if (l1tf == VMENTER_L1D_FLUSH_COND) |
303 | static_branch_enable(&vmx_l1d_flush_cond); | |
895ae47f | 304 | else |
427362a1 | 305 | static_branch_disable(&vmx_l1d_flush_cond); |
7db92e16 TG |
306 | return 0; |
307 | } | |
308 | ||
309 | static int vmentry_l1d_flush_parse(const char *s) | |
310 | { | |
311 | unsigned int i; | |
312 | ||
313 | if (s) { | |
314 | for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { | |
0027ff2a PB |
315 | if (vmentry_l1d_param[i].for_parse && |
316 | sysfs_streq(s, vmentry_l1d_param[i].option)) | |
317 | return i; | |
7db92e16 TG |
318 | } |
319 | } | |
a399477e KRW |
320 | return -EINVAL; |
321 | } | |
322 | ||
7db92e16 TG |
323 | static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) |
324 | { | |
dd4bfa73 | 325 | int l1tf, ret; |
7db92e16 | 326 | |
7db92e16 TG |
327 | l1tf = vmentry_l1d_flush_parse(s); |
328 | if (l1tf < 0) | |
329 | return l1tf; | |
330 | ||
0027ff2a PB |
331 | if (!boot_cpu_has(X86_BUG_L1TF)) |
332 | return 0; | |
333 | ||
7db92e16 TG |
334 | /* |
335 | * Has vmx_init() run already? If not then this is the pre init | |
336 | * parameter parsing. In that case just store the value and let | |
337 | * vmx_init() do the proper setup after enable_ept has been | |
338 | * established. | |
339 | */ | |
340 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { | |
341 | vmentry_l1d_flush_param = l1tf; | |
342 | return 0; | |
343 | } | |
344 | ||
dd4bfa73 TG |
345 | mutex_lock(&vmx_l1d_flush_mutex); |
346 | ret = vmx_setup_l1d_flush(l1tf); | |
347 | mutex_unlock(&vmx_l1d_flush_mutex); | |
348 | return ret; | |
7db92e16 TG |
349 | } |
350 | ||
a399477e KRW |
351 | static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) |
352 | { | |
0027ff2a PB |
353 | if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) |
354 | return sprintf(s, "???\n"); | |
355 | ||
7db92e16 | 356 | return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); |
a399477e KRW |
357 | } |
358 | ||
359 | static const struct kernel_param_ops vmentry_l1d_flush_ops = { | |
360 | .set = vmentry_l1d_flush_set, | |
361 | .get = vmentry_l1d_flush_get, | |
362 | }; | |
895ae47f | 363 | module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); |
a399477e | 364 | |
d99e4152 | 365 | static u32 vmx_segment_access_rights(struct kvm_segment *var); |
476c9bd8 | 366 | static __always_inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, |
15d45071 | 367 | u32 msr, int type); |
75880a01 | 368 | |
453eafbe SC |
369 | void vmx_vmexit(void); |
370 | ||
52a9fcbc SC |
371 | #define vmx_insn_failed(fmt...) \ |
372 | do { \ | |
373 | WARN_ONCE(1, fmt); \ | |
374 | pr_warn_ratelimited(fmt); \ | |
375 | } while (0) | |
376 | ||
6e202097 SC |
377 | asmlinkage void vmread_error(unsigned long field, bool fault) |
378 | { | |
379 | if (fault) | |
380 | kvm_spurious_fault(); | |
381 | else | |
382 | vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); | |
383 | } | |
384 | ||
52a9fcbc SC |
385 | noinline void vmwrite_error(unsigned long field, unsigned long value) |
386 | { | |
387 | vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", | |
388 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
389 | } | |
390 | ||
391 | noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) | |
392 | { | |
393 | vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); | |
394 | } | |
395 | ||
396 | noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) | |
397 | { | |
398 | vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); | |
399 | } | |
400 | ||
401 | noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) | |
402 | { | |
403 | vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", | |
404 | ext, vpid, gva); | |
405 | } | |
406 | ||
407 | noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) | |
408 | { | |
409 | vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", | |
410 | ext, eptp, gpa); | |
411 | } | |
412 | ||
6aa8b732 | 413 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
75edce8a | 414 | DEFINE_PER_CPU(struct vmcs *, current_vmcs); |
d462b819 NHE |
415 | /* |
416 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
417 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
418 | */ | |
419 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
6aa8b732 | 420 | |
2384d2b3 SY |
421 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
422 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
423 | ||
3077c191 SC |
424 | struct vmcs_config vmcs_config; |
425 | struct vmx_capability vmx_capability; | |
d56f546d | 426 | |
6aa8b732 AK |
427 | #define VMX_SEGMENT_FIELD(seg) \ |
428 | [VCPU_SREG_##seg] = { \ | |
429 | .selector = GUEST_##seg##_SELECTOR, \ | |
430 | .base = GUEST_##seg##_BASE, \ | |
431 | .limit = GUEST_##seg##_LIMIT, \ | |
432 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
433 | } | |
434 | ||
772e0318 | 435 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
436 | unsigned selector; |
437 | unsigned base; | |
438 | unsigned limit; | |
439 | unsigned ar_bytes; | |
440 | } kvm_vmx_segment_fields[] = { | |
441 | VMX_SEGMENT_FIELD(CS), | |
442 | VMX_SEGMENT_FIELD(DS), | |
443 | VMX_SEGMENT_FIELD(ES), | |
444 | VMX_SEGMENT_FIELD(FS), | |
445 | VMX_SEGMENT_FIELD(GS), | |
446 | VMX_SEGMENT_FIELD(SS), | |
447 | VMX_SEGMENT_FIELD(TR), | |
448 | VMX_SEGMENT_FIELD(LDTR), | |
449 | }; | |
450 | ||
ec0241f3 SC |
451 | static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
452 | { | |
453 | vmx->segment_cache.bitmask = 0; | |
454 | } | |
455 | ||
2342080c | 456 | static unsigned long host_idt_base; |
26bb0981 | 457 | |
4d56c8a7 | 458 | /* |
898a811f JM |
459 | * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm |
460 | * will emulate SYSCALL in legacy mode if the vendor string in guest | |
461 | * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To | |
462 | * support this emulation, IA32_STAR must always be included in | |
14a61b64 | 463 | * vmx_uret_msrs_list[], even in i386 builds. |
4d56c8a7 | 464 | */ |
6a2e0923 | 465 | static const u32 vmx_uret_msrs_list[] = { |
05b3e0c2 | 466 | #ifdef CONFIG_X86_64 |
44ea2b17 | 467 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 468 | #endif |
8c06585d | 469 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
c11f83e0 | 470 | MSR_IA32_TSX_CTRL, |
6aa8b732 | 471 | }; |
6aa8b732 | 472 | |
773e8a04 VK |
473 | #if IS_ENABLED(CONFIG_HYPERV) |
474 | static bool __read_mostly enlightened_vmcs = true; | |
475 | module_param(enlightened_vmcs, bool, 0444); | |
476 | ||
877ad952 TL |
477 | /* check_ept_pointer() should be under protection of ept_pointer_lock. */ |
478 | static void check_ept_pointer_match(struct kvm *kvm) | |
479 | { | |
480 | struct kvm_vcpu *vcpu; | |
481 | u64 tmp_eptp = INVALID_PAGE; | |
482 | int i; | |
483 | ||
484 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
485 | if (!VALID_PAGE(tmp_eptp)) { | |
486 | tmp_eptp = to_vmx(vcpu)->ept_pointer; | |
487 | } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { | |
488 | to_kvm_vmx(kvm)->ept_pointers_match | |
489 | = EPT_POINTERS_MISMATCH; | |
490 | return; | |
491 | } | |
492 | } | |
493 | ||
494 | to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; | |
495 | } | |
496 | ||
8997f657 | 497 | static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, |
1f3a3e46 LT |
498 | void *data) |
499 | { | |
500 | struct kvm_tlb_range *range = data; | |
501 | ||
502 | return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, | |
503 | range->pages); | |
504 | } | |
505 | ||
506 | static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, | |
507 | struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) | |
508 | { | |
509 | u64 ept_pointer = to_vmx(vcpu)->ept_pointer; | |
510 | ||
511 | /* | |
512 | * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address | |
513 | * of the base of EPT PML4 table, strip off EPT configuration | |
514 | * information. | |
515 | */ | |
516 | if (range) | |
517 | return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, | |
518 | kvm_fill_hv_flush_list_func, (void *)range); | |
519 | else | |
520 | return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); | |
521 | } | |
522 | ||
523 | static int hv_remote_flush_tlb_with_range(struct kvm *kvm, | |
524 | struct kvm_tlb_range *range) | |
877ad952 | 525 | { |
a5c214da | 526 | struct kvm_vcpu *vcpu; |
b7c1c226 | 527 | int ret = 0, i; |
877ad952 TL |
528 | |
529 | spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); | |
530 | ||
531 | if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) | |
532 | check_ept_pointer_match(kvm); | |
533 | ||
534 | if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { | |
53963a70 | 535 | kvm_for_each_vcpu(i, vcpu, kvm) { |
1f3a3e46 LT |
536 | /* If ept_pointer is invalid pointer, bypass flush request. */ |
537 | if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) | |
538 | ret |= __hv_remote_flush_tlb_with_range( | |
539 | kvm, vcpu, range); | |
53963a70 | 540 | } |
a5c214da | 541 | } else { |
1f3a3e46 LT |
542 | ret = __hv_remote_flush_tlb_with_range(kvm, |
543 | kvm_get_vcpu(kvm, 0), range); | |
877ad952 | 544 | } |
877ad952 | 545 | |
877ad952 TL |
546 | spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); |
547 | return ret; | |
548 | } | |
1f3a3e46 LT |
549 | static int hv_remote_flush_tlb(struct kvm *kvm) |
550 | { | |
551 | return hv_remote_flush_tlb_with_range(kvm, NULL); | |
552 | } | |
553 | ||
6f6a657c VK |
554 | static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) |
555 | { | |
556 | struct hv_enlightened_vmcs *evmcs; | |
557 | struct hv_partition_assist_pg **p_hv_pa_pg = | |
558 | &vcpu->kvm->arch.hyperv.hv_pa_pg; | |
559 | /* | |
560 | * Synthetic VM-Exit is not enabled in current code and so All | |
561 | * evmcs in singe VM shares same assist page. | |
562 | */ | |
cab01850 | 563 | if (!*p_hv_pa_pg) |
6f6a657c | 564 | *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); |
cab01850 VK |
565 | |
566 | if (!*p_hv_pa_pg) | |
567 | return -ENOMEM; | |
6f6a657c VK |
568 | |
569 | evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; | |
570 | ||
571 | evmcs->partition_assist_page = | |
572 | __pa(*p_hv_pa_pg); | |
cab01850 | 573 | evmcs->hv_vm_id = (unsigned long)vcpu->kvm; |
6f6a657c VK |
574 | evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; |
575 | ||
6f6a657c VK |
576 | return 0; |
577 | } | |
578 | ||
773e8a04 VK |
579 | #endif /* IS_ENABLED(CONFIG_HYPERV) */ |
580 | ||
64672c95 YJ |
581 | /* |
582 | * Comment's format: document - errata name - stepping - processor name. | |
583 | * Refer from | |
584 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
585 | */ | |
586 | static u32 vmx_preemption_cpu_tfms[] = { | |
587 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
588 | 0x000206E6, | |
589 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
590 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
591 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
592 | 0x00020652, | |
593 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
594 | 0x00020655, | |
595 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
596 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
597 | /* | |
598 | * 320767.pdf - AAP86 - B1 - | |
599 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
600 | */ | |
601 | 0x000106E5, | |
602 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
603 | 0x000106A0, | |
604 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
605 | 0x000106A1, | |
606 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
607 | 0x000106A4, | |
608 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
609 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
610 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
611 | 0x000106A5, | |
3d82c565 WH |
612 | /* Xeon E3-1220 V2 */ |
613 | 0x000306A8, | |
64672c95 YJ |
614 | }; |
615 | ||
616 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
617 | { | |
618 | u32 eax = cpuid_eax(0x00000001), i; | |
619 | ||
620 | /* Clear the reserved bits */ | |
621 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 622 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
623 | if (eax == vmx_preemption_cpu_tfms[i]) |
624 | return true; | |
625 | ||
626 | return false; | |
627 | } | |
628 | ||
35754c98 | 629 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 630 | { |
35754c98 | 631 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
632 | } |
633 | ||
04547156 SY |
634 | static inline bool report_flexpriority(void) |
635 | { | |
636 | return flexpriority_enabled; | |
637 | } | |
638 | ||
3eb90017 AG |
639 | static int possible_passthrough_msr_slot(u32 msr) |
640 | { | |
641 | u32 i; | |
642 | ||
643 | for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) | |
644 | if (vmx_possible_passthrough_msrs[i] == msr) | |
645 | return i; | |
646 | ||
647 | return -ENOENT; | |
648 | } | |
649 | ||
650 | static bool is_valid_passthrough_msr(u32 msr) | |
651 | { | |
652 | bool r; | |
653 | ||
654 | switch (msr) { | |
655 | case 0x800 ... 0x8ff: | |
656 | /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */ | |
657 | return true; | |
658 | case MSR_IA32_RTIT_STATUS: | |
659 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
660 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
661 | case MSR_IA32_RTIT_CR3_MATCH: | |
662 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: | |
663 | /* PT MSRs. These are handled in pt_update_intercept_for_msr() */ | |
664 | return true; | |
665 | } | |
666 | ||
667 | r = possible_passthrough_msr_slot(msr) != -ENOENT; | |
668 | ||
669 | WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr); | |
670 | ||
671 | return r; | |
672 | } | |
673 | ||
1e7a4830 | 674 | static inline int __vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
675 | { |
676 | int i; | |
677 | ||
fbc18007 | 678 | for (i = 0; i < vmx->nr_uret_msrs; ++i) |
802145c5 | 679 | if (vmx_uret_msrs_list[vmx->guest_uret_msrs[i].slot] == msr) |
a75beee6 ED |
680 | return i; |
681 | return -1; | |
682 | } | |
683 | ||
d85a8034 | 684 | struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
685 | { |
686 | int i; | |
687 | ||
1e7a4830 | 688 | i = __vmx_find_uret_msr(vmx, msr); |
a75beee6 | 689 | if (i >= 0) |
eb3db1b1 | 690 | return &vmx->guest_uret_msrs[i]; |
8b6d44c7 | 691 | return NULL; |
7725f0ba AK |
692 | } |
693 | ||
7bf662bb SC |
694 | static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx, |
695 | struct vmx_uret_msr *msr, u64 data) | |
b07a5c53 PB |
696 | { |
697 | int ret = 0; | |
698 | ||
699 | u64 old_msr_data = msr->data; | |
700 | msr->data = data; | |
e9bb1ae9 | 701 | if (msr - vmx->guest_uret_msrs < vmx->nr_active_uret_msrs) { |
b07a5c53 | 702 | preempt_disable(); |
802145c5 | 703 | ret = kvm_set_user_return_msr(msr->slot, msr->data, msr->mask); |
b07a5c53 PB |
704 | preempt_enable(); |
705 | if (ret) | |
706 | msr->data = old_msr_data; | |
707 | } | |
708 | return ret; | |
709 | } | |
710 | ||
2965faa5 | 711 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
712 | static void crash_vmclear_local_loaded_vmcss(void) |
713 | { | |
714 | int cpu = raw_smp_processor_id(); | |
715 | struct loaded_vmcs *v; | |
716 | ||
8f536b76 ZY |
717 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), |
718 | loaded_vmcss_on_cpu_link) | |
719 | vmcs_clear(v->vmcs); | |
720 | } | |
2965faa5 | 721 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 722 | |
d462b819 | 723 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 724 | { |
d462b819 | 725 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 726 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 727 | |
d462b819 NHE |
728 | if (loaded_vmcs->cpu != cpu) |
729 | return; /* vcpu migration can race with cpu offline */ | |
730 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 731 | per_cpu(current_vmcs, cpu) = NULL; |
31603d4f SC |
732 | |
733 | vmcs_clear(loaded_vmcs->vmcs); | |
734 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) | |
735 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
736 | ||
d462b819 | 737 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
738 | |
739 | /* | |
31603d4f SC |
740 | * Ensure all writes to loaded_vmcs, including deleting it from its |
741 | * current percpu list, complete before setting loaded_vmcs->vcpu to | |
742 | * -1, otherwise a different cpu can see vcpu == -1 first and add | |
743 | * loaded_vmcs to its percpu list before it's deleted from this cpu's | |
744 | * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs(). | |
5a560f8b XG |
745 | */ |
746 | smp_wmb(); | |
747 | ||
31603d4f SC |
748 | loaded_vmcs->cpu = -1; |
749 | loaded_vmcs->launched = 0; | |
6aa8b732 AK |
750 | } |
751 | ||
89b0c9f5 | 752 | void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 753 | { |
e6c7d321 XG |
754 | int cpu = loaded_vmcs->cpu; |
755 | ||
756 | if (cpu != -1) | |
757 | smp_call_function_single(cpu, | |
758 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
759 | } |
760 | ||
2fb92db1 AK |
761 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, |
762 | unsigned field) | |
763 | { | |
764 | bool ret; | |
765 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
766 | ||
cb3c1e2f SC |
767 | if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { |
768 | kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); | |
2fb92db1 AK |
769 | vmx->segment_cache.bitmask = 0; |
770 | } | |
771 | ret = vmx->segment_cache.bitmask & mask; | |
772 | vmx->segment_cache.bitmask |= mask; | |
773 | return ret; | |
774 | } | |
775 | ||
776 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
777 | { | |
778 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
779 | ||
780 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
781 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
782 | return *p; | |
783 | } | |
784 | ||
785 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
786 | { | |
787 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
788 | ||
789 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
790 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
791 | return *p; | |
792 | } | |
793 | ||
794 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
795 | { | |
796 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
797 | ||
798 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
799 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
800 | return *p; | |
801 | } | |
802 | ||
803 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
804 | { | |
805 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
806 | ||
807 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
808 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
809 | return *p; | |
810 | } | |
811 | ||
97b7ead3 | 812 | void update_exception_bitmap(struct kvm_vcpu *vcpu) |
abd3f2d6 AK |
813 | { |
814 | u32 eb; | |
815 | ||
fd7373cc | 816 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
bd7e5b08 | 817 | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
9e869480 LA |
818 | /* |
819 | * Guest access to VMware backdoor ports could legitimately | |
820 | * trigger #GP because of TSS I/O permission bitmap. | |
821 | * We intercept those #GP and allow access to them anyway | |
822 | * as VMware does. | |
823 | */ | |
824 | if (enable_vmware_backdoor) | |
825 | eb |= (1u << GP_VECTOR); | |
fd7373cc JK |
826 | if ((vcpu->guest_debug & |
827 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
828 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
829 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 830 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 831 | eb = ~0; |
a0c13434 | 832 | if (!vmx_need_pf_intercept(vcpu)) |
49f933d4 | 833 | eb &= ~(1u << PF_VECTOR); |
36cf24e0 NHE |
834 | |
835 | /* When we are running a nested L2 guest and L1 specified for it a | |
836 | * certain exception bitmap, we must trap the same exceptions and pass | |
837 | * them to L1. When running L2, we will only handle the exceptions | |
838 | * specified above if L1 did not want them. | |
839 | */ | |
840 | if (is_guest_mode(vcpu)) | |
841 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
b502e6ec PB |
842 | else { |
843 | /* | |
844 | * If EPT is enabled, #PF is only trapped if MAXPHYADDR is mismatched | |
845 | * between guest and host. In that case we only care about present | |
846 | * faults. For vmcs02, however, PFEC_MASK and PFEC_MATCH are set in | |
847 | * prepare_vmcs02_rare. | |
848 | */ | |
849 | bool selective_pf_trap = enable_ept && (eb & (1u << PF_VECTOR)); | |
850 | int mask = selective_pf_trap ? PFERR_PRESENT_MASK : 0; | |
851 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask); | |
852 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, mask); | |
853 | } | |
36cf24e0 | 854 | |
abd3f2d6 AK |
855 | vmcs_write32(EXCEPTION_BITMAP, eb); |
856 | } | |
857 | ||
d28b387f KA |
858 | /* |
859 | * Check if MSR is intercepted for currently loaded MSR bitmap. | |
860 | */ | |
861 | static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) | |
862 | { | |
863 | unsigned long *msr_bitmap; | |
864 | int f = sizeof(unsigned long); | |
865 | ||
866 | if (!cpu_has_vmx_msr_bitmap()) | |
867 | return true; | |
868 | ||
869 | msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; | |
870 | ||
871 | if (msr <= 0x1fff) { | |
872 | return !!test_bit(msr, msr_bitmap + 0x800 / f); | |
873 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
874 | msr &= 0x1fff; | |
875 | return !!test_bit(msr, msr_bitmap + 0xc00 / f); | |
876 | } | |
877 | ||
878 | return true; | |
879 | } | |
880 | ||
2961e876 GN |
881 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
882 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 883 | { |
2961e876 GN |
884 | vm_entry_controls_clearbit(vmx, entry); |
885 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
886 | } |
887 | ||
a128a934 | 888 | int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr) |
ca83b4a7 KRW |
889 | { |
890 | unsigned int i; | |
891 | ||
892 | for (i = 0; i < m->nr; ++i) { | |
893 | if (m->val[i].index == msr) | |
894 | return i; | |
895 | } | |
896 | return -ENOENT; | |
897 | } | |
898 | ||
61d2ef2c AK |
899 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
900 | { | |
ca83b4a7 | 901 | int i; |
61d2ef2c AK |
902 | struct msr_autoload *m = &vmx->msr_autoload; |
903 | ||
8bf00a52 GN |
904 | switch (msr) { |
905 | case MSR_EFER: | |
c73da3fc | 906 | if (cpu_has_load_ia32_efer()) { |
2961e876 GN |
907 | clear_atomic_switch_msr_special(vmx, |
908 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
909 | VM_EXIT_LOAD_IA32_EFER); |
910 | return; | |
911 | } | |
912 | break; | |
913 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
c73da3fc | 914 | if (cpu_has_load_perf_global_ctrl()) { |
2961e876 | 915 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
916 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
917 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
918 | return; | |
919 | } | |
920 | break; | |
110312c8 | 921 | } |
a128a934 | 922 | i = vmx_find_loadstore_msr_slot(&m->guest, msr); |
ca83b4a7 | 923 | if (i < 0) |
31907093 | 924 | goto skip_guest; |
33966dd6 | 925 | --m->guest.nr; |
33966dd6 | 926 | m->guest.val[i] = m->guest.val[m->guest.nr]; |
33966dd6 | 927 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); |
110312c8 | 928 | |
31907093 | 929 | skip_guest: |
a128a934 | 930 | i = vmx_find_loadstore_msr_slot(&m->host, msr); |
31907093 | 931 | if (i < 0) |
61d2ef2c | 932 | return; |
31907093 KRW |
933 | |
934 | --m->host.nr; | |
935 | m->host.val[i] = m->host.val[m->host.nr]; | |
33966dd6 | 936 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); |
61d2ef2c AK |
937 | } |
938 | ||
2961e876 GN |
939 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
940 | unsigned long entry, unsigned long exit, | |
941 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
942 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
943 | { |
944 | vmcs_write64(guest_val_vmcs, guest_val); | |
5a5e8a15 SC |
945 | if (host_val_vmcs != HOST_IA32_EFER) |
946 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
947 | vm_entry_controls_setbit(vmx, entry); |
948 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
949 | } |
950 | ||
61d2ef2c | 951 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
989e3992 | 952 | u64 guest_val, u64 host_val, bool entry_only) |
61d2ef2c | 953 | { |
989e3992 | 954 | int i, j = 0; |
61d2ef2c AK |
955 | struct msr_autoload *m = &vmx->msr_autoload; |
956 | ||
8bf00a52 GN |
957 | switch (msr) { |
958 | case MSR_EFER: | |
c73da3fc | 959 | if (cpu_has_load_ia32_efer()) { |
2961e876 GN |
960 | add_atomic_switch_msr_special(vmx, |
961 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
962 | VM_EXIT_LOAD_IA32_EFER, |
963 | GUEST_IA32_EFER, | |
964 | HOST_IA32_EFER, | |
965 | guest_val, host_val); | |
966 | return; | |
967 | } | |
968 | break; | |
969 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
c73da3fc | 970 | if (cpu_has_load_perf_global_ctrl()) { |
2961e876 | 971 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
972 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
973 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
974 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
975 | HOST_IA32_PERF_GLOBAL_CTRL, | |
976 | guest_val, host_val); | |
977 | return; | |
978 | } | |
979 | break; | |
7099e2e1 RK |
980 | case MSR_IA32_PEBS_ENABLE: |
981 | /* PEBS needs a quiescent period after being disabled (to write | |
982 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
983 | * provide that period, so a CPU could write host's record into | |
984 | * guest's memory. | |
985 | */ | |
986 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
987 | } |
988 | ||
a128a934 | 989 | i = vmx_find_loadstore_msr_slot(&m->guest, msr); |
989e3992 | 990 | if (!entry_only) |
a128a934 | 991 | j = vmx_find_loadstore_msr_slot(&m->host, msr); |
61d2ef2c | 992 | |
ce833b23 SC |
993 | if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) || |
994 | (j < 0 && m->host.nr == MAX_NR_LOADSTORE_MSRS)) { | |
60266204 | 995 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
996 | "Can't add msr %x\n", msr); |
997 | return; | |
61d2ef2c | 998 | } |
31907093 | 999 | if (i < 0) { |
ca83b4a7 | 1000 | i = m->guest.nr++; |
33966dd6 | 1001 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); |
31907093 | 1002 | } |
989e3992 KRW |
1003 | m->guest.val[i].index = msr; |
1004 | m->guest.val[i].value = guest_val; | |
1005 | ||
1006 | if (entry_only) | |
1007 | return; | |
61d2ef2c | 1008 | |
31907093 KRW |
1009 | if (j < 0) { |
1010 | j = m->host.nr++; | |
33966dd6 | 1011 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); |
61d2ef2c | 1012 | } |
31907093 KRW |
1013 | m->host.val[j].index = msr; |
1014 | m->host.val[j].value = host_val; | |
61d2ef2c AK |
1015 | } |
1016 | ||
86e3e494 | 1017 | static bool update_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 1018 | { |
844a5fe2 PB |
1019 | u64 guest_efer = vmx->vcpu.arch.efer; |
1020 | u64 ignore_bits = 0; | |
86e3e494 | 1021 | int i; |
844a5fe2 | 1022 | |
9167ab79 PB |
1023 | /* Shadow paging assumes NX to be available. */ |
1024 | if (!enable_ept) | |
1025 | guest_efer |= EFER_NX; | |
3a34a881 | 1026 | |
51c6cf66 | 1027 | /* |
844a5fe2 | 1028 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 1029 | */ |
844a5fe2 | 1030 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
1031 | #ifdef CONFIG_X86_64 |
1032 | ignore_bits |= EFER_LMA | EFER_LME; | |
1033 | /* SCE is meaningful only in long mode on Intel */ | |
1034 | if (guest_efer & EFER_LMA) | |
1035 | ignore_bits &= ~(u64)EFER_SCE; | |
1036 | #endif | |
84ad33ef | 1037 | |
f6577a5f AL |
1038 | /* |
1039 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
1040 | * On CPUs that support "load IA32_EFER", always switch EFER | |
1041 | * atomically, since it's faster than switching it manually. | |
1042 | */ | |
c73da3fc | 1043 | if (cpu_has_load_ia32_efer() || |
f6577a5f | 1044 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { |
84ad33ef AK |
1045 | if (!(guest_efer & EFER_LMA)) |
1046 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
1047 | if (guest_efer != host_efer) |
1048 | add_atomic_switch_msr(vmx, MSR_EFER, | |
989e3992 | 1049 | guest_efer, host_efer, false); |
02343cf2 SC |
1050 | else |
1051 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
84ad33ef | 1052 | return false; |
86e3e494 | 1053 | } |
02343cf2 | 1054 | |
86e3e494 SC |
1055 | i = __vmx_find_uret_msr(vmx, MSR_EFER); |
1056 | if (i < 0) | |
1057 | return false; | |
02343cf2 | 1058 | |
86e3e494 | 1059 | clear_atomic_switch_msr(vmx, MSR_EFER); |
844a5fe2 | 1060 | |
86e3e494 SC |
1061 | guest_efer &= ~ignore_bits; |
1062 | guest_efer |= host_efer & ignore_bits; | |
84ad33ef | 1063 | |
86e3e494 SC |
1064 | vmx->guest_uret_msrs[i].data = guest_efer; |
1065 | vmx->guest_uret_msrs[i].mask = ~ignore_bits; | |
1066 | ||
1067 | return true; | |
51c6cf66 AK |
1068 | } |
1069 | ||
e28baead AL |
1070 | #ifdef CONFIG_X86_32 |
1071 | /* | |
1072 | * On 32-bit kernels, VM exits still load the FS and GS bases from the | |
1073 | * VMCS rather than the segment table. KVM uses this helper to figure | |
1074 | * out the current bases to poke them into the VMCS before entry. | |
1075 | */ | |
2d49ec72 GN |
1076 | static unsigned long segment_base(u16 selector) |
1077 | { | |
8c2e41f7 | 1078 | struct desc_struct *table; |
2d49ec72 GN |
1079 | unsigned long v; |
1080 | ||
8c2e41f7 | 1081 | if (!(selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
1082 | return 0; |
1083 | ||
45fc8757 | 1084 | table = get_current_gdt_ro(); |
2d49ec72 | 1085 | |
8c2e41f7 | 1086 | if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
2d49ec72 GN |
1087 | u16 ldt_selector = kvm_read_ldt(); |
1088 | ||
8c2e41f7 | 1089 | if (!(ldt_selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
1090 | return 0; |
1091 | ||
8c2e41f7 | 1092 | table = (struct desc_struct *)segment_base(ldt_selector); |
2d49ec72 | 1093 | } |
8c2e41f7 | 1094 | v = get_desc_base(&table[selector >> 3]); |
2d49ec72 GN |
1095 | return v; |
1096 | } | |
e28baead | 1097 | #endif |
2d49ec72 | 1098 | |
e348ac7c SC |
1099 | static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) |
1100 | { | |
2ef7619d | 1101 | return vmx_pt_mode_is_host_guest() && |
e348ac7c SC |
1102 | !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); |
1103 | } | |
1104 | ||
1cc6cbc3 SC |
1105 | static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base) |
1106 | { | |
1107 | /* The base must be 128-byte aligned and a legal physical address. */ | |
7096cbfb | 1108 | return !kvm_vcpu_is_illegal_gpa(vcpu, base) && !(base & 0x7f); |
1cc6cbc3 SC |
1109 | } |
1110 | ||
2ef444f1 CP |
1111 | static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) |
1112 | { | |
1113 | u32 i; | |
1114 | ||
1115 | wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); | |
1116 | wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); | |
1117 | wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); | |
1118 | wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); | |
1119 | for (i = 0; i < addr_range; i++) { | |
1120 | wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); | |
1121 | wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) | |
1126 | { | |
1127 | u32 i; | |
1128 | ||
1129 | rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); | |
1130 | rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); | |
1131 | rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); | |
1132 | rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); | |
1133 | for (i = 0; i < addr_range; i++) { | |
1134 | rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); | |
1135 | rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); | |
1136 | } | |
1137 | } | |
1138 | ||
1139 | static void pt_guest_enter(struct vcpu_vmx *vmx) | |
1140 | { | |
2ef7619d | 1141 | if (vmx_pt_mode_is_system()) |
2ef444f1 CP |
1142 | return; |
1143 | ||
2ef444f1 | 1144 | /* |
b08c2896 CP |
1145 | * GUEST_IA32_RTIT_CTL is already set in the VMCS. |
1146 | * Save host state before VM entry. | |
2ef444f1 | 1147 | */ |
b08c2896 | 1148 | rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); |
2ef444f1 CP |
1149 | if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { |
1150 | wrmsrl(MSR_IA32_RTIT_CTL, 0); | |
1151 | pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); | |
1152 | pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | static void pt_guest_exit(struct vcpu_vmx *vmx) | |
1157 | { | |
2ef7619d | 1158 | if (vmx_pt_mode_is_system()) |
2ef444f1 CP |
1159 | return; |
1160 | ||
1161 | if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { | |
1162 | pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); | |
1163 | pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); | |
1164 | } | |
1165 | ||
1166 | /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ | |
1167 | wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); | |
1168 | } | |
1169 | ||
13b964a2 SC |
1170 | void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, |
1171 | unsigned long fs_base, unsigned long gs_base) | |
1172 | { | |
1173 | if (unlikely(fs_sel != host->fs_sel)) { | |
1174 | if (!(fs_sel & 7)) | |
1175 | vmcs_write16(HOST_FS_SELECTOR, fs_sel); | |
1176 | else | |
1177 | vmcs_write16(HOST_FS_SELECTOR, 0); | |
1178 | host->fs_sel = fs_sel; | |
1179 | } | |
1180 | if (unlikely(gs_sel != host->gs_sel)) { | |
1181 | if (!(gs_sel & 7)) | |
1182 | vmcs_write16(HOST_GS_SELECTOR, gs_sel); | |
1183 | else | |
1184 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
1185 | host->gs_sel = gs_sel; | |
1186 | } | |
1187 | if (unlikely(fs_base != host->fs_base)) { | |
1188 | vmcs_writel(HOST_FS_BASE, fs_base); | |
1189 | host->fs_base = fs_base; | |
1190 | } | |
1191 | if (unlikely(gs_base != host->gs_base)) { | |
1192 | vmcs_writel(HOST_GS_BASE, gs_base); | |
1193 | host->gs_base = gs_base; | |
1194 | } | |
1195 | } | |
1196 | ||
97b7ead3 | 1197 | void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) |
33ed6329 | 1198 | { |
04d2cc77 | 1199 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d7ee039e | 1200 | struct vmcs_host_state *host_state; |
51e8a8cc | 1201 | #ifdef CONFIG_X86_64 |
35060ed6 | 1202 | int cpu = raw_smp_processor_id(); |
51e8a8cc | 1203 | #endif |
e368b875 SC |
1204 | unsigned long fs_base, gs_base; |
1205 | u16 fs_sel, gs_sel; | |
26bb0981 | 1206 | int i; |
04d2cc77 | 1207 | |
d264ee0c SC |
1208 | vmx->req_immediate_exit = false; |
1209 | ||
f48b4711 LA |
1210 | /* |
1211 | * Note that guest MSRs to be saved/restored can also be changed | |
1212 | * when guest state is loaded. This happens when guest transitions | |
1213 | * to/from long-mode by setting MSR_EFER.LMA. | |
1214 | */ | |
658ece84 SC |
1215 | if (!vmx->guest_uret_msrs_loaded) { |
1216 | vmx->guest_uret_msrs_loaded = true; | |
e9bb1ae9 | 1217 | for (i = 0; i < vmx->nr_active_uret_msrs; ++i) |
802145c5 | 1218 | kvm_set_user_return_msr(vmx->guest_uret_msrs[i].slot, |
eb3db1b1 SC |
1219 | vmx->guest_uret_msrs[i].data, |
1220 | vmx->guest_uret_msrs[i].mask); | |
f48b4711 LA |
1221 | |
1222 | } | |
c9dfd3fb | 1223 | |
1224 | if (vmx->nested.need_vmcs12_to_shadow_sync) | |
1225 | nested_sync_vmcs12_to_shadow(vcpu); | |
1226 | ||
b464f57e | 1227 | if (vmx->guest_state_loaded) |
33ed6329 AK |
1228 | return; |
1229 | ||
b464f57e | 1230 | host_state = &vmx->loaded_vmcs->host_state; |
bd9966de | 1231 | |
33ed6329 AK |
1232 | /* |
1233 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
1234 | * allow segment selectors with cpl > 0 or ti == 1. | |
1235 | */ | |
d7ee039e | 1236 | host_state->ldt_sel = kvm_read_ldt(); |
42b933b5 VK |
1237 | |
1238 | #ifdef CONFIG_X86_64 | |
d7ee039e SC |
1239 | savesegment(ds, host_state->ds_sel); |
1240 | savesegment(es, host_state->es_sel); | |
e368b875 SC |
1241 | |
1242 | gs_base = cpu_kernelmode_gs_base(cpu); | |
b062b794 | 1243 | if (likely(is_64bit_mm(current->mm))) { |
6758034e | 1244 | current_save_fsgs(); |
e368b875 SC |
1245 | fs_sel = current->thread.fsindex; |
1246 | gs_sel = current->thread.gsindex; | |
b062b794 | 1247 | fs_base = current->thread.fsbase; |
e368b875 | 1248 | vmx->msr_host_kernel_gs_base = current->thread.gsbase; |
b062b794 | 1249 | } else { |
e368b875 SC |
1250 | savesegment(fs, fs_sel); |
1251 | savesegment(gs, gs_sel); | |
b062b794 | 1252 | fs_base = read_msr(MSR_FS_BASE); |
e368b875 | 1253 | vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); |
33ed6329 | 1254 | } |
b2da15ac | 1255 | |
4679b61f | 1256 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
4fde8d57 | 1257 | #else |
e368b875 SC |
1258 | savesegment(fs, fs_sel); |
1259 | savesegment(gs, gs_sel); | |
1260 | fs_base = segment_base(fs_sel); | |
1261 | gs_base = segment_base(gs_sel); | |
707c0874 | 1262 | #endif |
e368b875 | 1263 | |
13b964a2 | 1264 | vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); |
b464f57e | 1265 | vmx->guest_state_loaded = true; |
33ed6329 AK |
1266 | } |
1267 | ||
6d6095bd | 1268 | static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) |
33ed6329 | 1269 | { |
d7ee039e SC |
1270 | struct vmcs_host_state *host_state; |
1271 | ||
b464f57e | 1272 | if (!vmx->guest_state_loaded) |
33ed6329 AK |
1273 | return; |
1274 | ||
b464f57e | 1275 | host_state = &vmx->loaded_vmcs->host_state; |
bd9966de | 1276 | |
e1beb1d3 | 1277 | ++vmx->vcpu.stat.host_state_reload; |
bd9966de | 1278 | |
c8770e7b | 1279 | #ifdef CONFIG_X86_64 |
4679b61f | 1280 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
c8770e7b | 1281 | #endif |
d7ee039e SC |
1282 | if (host_state->ldt_sel || (host_state->gs_sel & 7)) { |
1283 | kvm_load_ldt(host_state->ldt_sel); | |
33ed6329 | 1284 | #ifdef CONFIG_X86_64 |
d7ee039e | 1285 | load_gs_index(host_state->gs_sel); |
9581d442 | 1286 | #else |
d7ee039e | 1287 | loadsegment(gs, host_state->gs_sel); |
33ed6329 | 1288 | #endif |
33ed6329 | 1289 | } |
d7ee039e SC |
1290 | if (host_state->fs_sel & 7) |
1291 | loadsegment(fs, host_state->fs_sel); | |
b2da15ac | 1292 | #ifdef CONFIG_X86_64 |
d7ee039e SC |
1293 | if (unlikely(host_state->ds_sel | host_state->es_sel)) { |
1294 | loadsegment(ds, host_state->ds_sel); | |
1295 | loadsegment(es, host_state->es_sel); | |
b2da15ac | 1296 | } |
b2da15ac | 1297 | #endif |
b7ffc44d | 1298 | invalidate_tss_limit(); |
44ea2b17 | 1299 | #ifdef CONFIG_X86_64 |
c8770e7b | 1300 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 1301 | #endif |
45fc8757 | 1302 | load_fixmap_gdt(raw_smp_processor_id()); |
b464f57e | 1303 | vmx->guest_state_loaded = false; |
658ece84 | 1304 | vmx->guest_uret_msrs_loaded = false; |
33ed6329 AK |
1305 | } |
1306 | ||
678e315e SC |
1307 | #ifdef CONFIG_X86_64 |
1308 | static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) | |
a9b21b62 | 1309 | { |
4679b61f | 1310 | preempt_disable(); |
b464f57e | 1311 | if (vmx->guest_state_loaded) |
4679b61f PB |
1312 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
1313 | preempt_enable(); | |
678e315e | 1314 | return vmx->msr_guest_kernel_gs_base; |
a9b21b62 AK |
1315 | } |
1316 | ||
678e315e SC |
1317 | static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) |
1318 | { | |
4679b61f | 1319 | preempt_disable(); |
b464f57e | 1320 | if (vmx->guest_state_loaded) |
4679b61f PB |
1321 | wrmsrl(MSR_KERNEL_GS_BASE, data); |
1322 | preempt_enable(); | |
678e315e SC |
1323 | vmx->msr_guest_kernel_gs_base = data; |
1324 | } | |
1325 | #endif | |
1326 | ||
5c911bef SC |
1327 | void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, |
1328 | struct loaded_vmcs *buddy) | |
6aa8b732 | 1329 | { |
a2fa3e9f | 1330 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b80c76ec | 1331 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
5c911bef | 1332 | struct vmcs *prev; |
6aa8b732 | 1333 | |
b80c76ec | 1334 | if (!already_loaded) { |
fe0e80be | 1335 | loaded_vmcs_clear(vmx->loaded_vmcs); |
92fe13be | 1336 | local_irq_disable(); |
5a560f8b XG |
1337 | |
1338 | /* | |
31603d4f SC |
1339 | * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to |
1340 | * this cpu's percpu list, otherwise it may not yet be deleted | |
1341 | * from its previous cpu's percpu list. Pairs with the | |
1342 | * smb_wmb() in __loaded_vmcs_clear(). | |
5a560f8b XG |
1343 | */ |
1344 | smp_rmb(); | |
1345 | ||
d462b819 NHE |
1346 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
1347 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
92fe13be | 1348 | local_irq_enable(); |
b80c76ec JM |
1349 | } |
1350 | ||
5c911bef SC |
1351 | prev = per_cpu(current_vmcs, cpu); |
1352 | if (prev != vmx->loaded_vmcs->vmcs) { | |
b80c76ec JM |
1353 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; |
1354 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
5c911bef SC |
1355 | |
1356 | /* | |
1357 | * No indirect branch prediction barrier needed when switching | |
1358 | * the active VMCS within a guest, e.g. on nested VM-Enter. | |
1359 | * The L1 VMM can protect itself with retpolines, IBPB or IBRS. | |
1360 | */ | |
1361 | if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev)) | |
1362 | indirect_branch_prediction_barrier(); | |
b80c76ec JM |
1363 | } |
1364 | ||
1365 | if (!already_loaded) { | |
59c58ceb | 1366 | void *gdt = get_current_gdt_ro(); |
b80c76ec JM |
1367 | unsigned long sysenter_esp; |
1368 | ||
eeeb4f67 SC |
1369 | /* |
1370 | * Flush all EPTP/VPID contexts, the new pCPU may have stale | |
1371 | * TLB entries from its previous association with the vCPU. | |
1372 | */ | |
b80c76ec | 1373 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
92fe13be | 1374 | |
6aa8b732 AK |
1375 | /* |
1376 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
e0c23063 | 1377 | * processors. See 22.2.4. |
6aa8b732 | 1378 | */ |
e0c23063 | 1379 | vmcs_writel(HOST_TR_BASE, |
72f5e08d | 1380 | (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); |
59c58ceb | 1381 | vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ |
6aa8b732 AK |
1382 | |
1383 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
1384 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 1385 | |
d462b819 | 1386 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 1387 | } |
28b835d6 | 1388 | |
2680d6da OH |
1389 | /* Setup TSC multiplier */ |
1390 | if (kvm_has_tsc_control && | |
c95ba92a PF |
1391 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
1392 | decache_tsc_multiplier(vmx); | |
8ef863e6 SC |
1393 | } |
1394 | ||
1395 | /* | |
1396 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
1397 | * vcpu mutex is already taken. | |
1398 | */ | |
1af1bb05 | 1399 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
8ef863e6 SC |
1400 | { |
1401 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1402 | ||
5c911bef | 1403 | vmx_vcpu_load_vmcs(vcpu, cpu, NULL); |
2680d6da | 1404 | |
28b835d6 | 1405 | vmx_vcpu_pi_load(vcpu, cpu); |
8ef863e6 | 1406 | |
74c55931 | 1407 | vmx->host_debugctlmsr = get_debugctlmsr(); |
28b835d6 FW |
1408 | } |
1409 | ||
13b964a2 | 1410 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) |
6aa8b732 | 1411 | { |
28b835d6 FW |
1412 | vmx_vcpu_pi_put(vcpu); |
1413 | ||
6d6095bd | 1414 | vmx_prepare_switch_to_host(to_vmx(vcpu)); |
6aa8b732 AK |
1415 | } |
1416 | ||
f244deed WL |
1417 | static bool emulation_required(struct kvm_vcpu *vcpu) |
1418 | { | |
2ba4493a | 1419 | return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu); |
f244deed WL |
1420 | } |
1421 | ||
97b7ead3 | 1422 | unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
6aa8b732 | 1423 | { |
e7bddc52 | 1424 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
78ac8b47 | 1425 | unsigned long rflags, save_rflags; |
345dcaa8 | 1426 | |
cb3c1e2f SC |
1427 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { |
1428 | kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); | |
6de12732 | 1429 | rflags = vmcs_readl(GUEST_RFLAGS); |
e7bddc52 | 1430 | if (vmx->rmode.vm86_active) { |
6de12732 | 1431 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
e7bddc52 | 1432 | save_rflags = vmx->rmode.save_rflags; |
6de12732 AK |
1433 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; |
1434 | } | |
e7bddc52 | 1435 | vmx->rflags = rflags; |
78ac8b47 | 1436 | } |
e7bddc52 | 1437 | return vmx->rflags; |
6aa8b732 AK |
1438 | } |
1439 | ||
97b7ead3 | 1440 | void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
6aa8b732 | 1441 | { |
e7bddc52 | 1442 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
491c1ad1 | 1443 | unsigned long old_rflags; |
f244deed | 1444 | |
bddd82d1 | 1445 | if (is_unrestricted_guest(vcpu)) { |
cb3c1e2f | 1446 | kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); |
491c1ad1 SC |
1447 | vmx->rflags = rflags; |
1448 | vmcs_writel(GUEST_RFLAGS, rflags); | |
1449 | return; | |
1450 | } | |
1451 | ||
1452 | old_rflags = vmx_get_rflags(vcpu); | |
e7bddc52 SC |
1453 | vmx->rflags = rflags; |
1454 | if (vmx->rmode.vm86_active) { | |
1455 | vmx->rmode.save_rflags = rflags; | |
053de044 | 1456 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 1457 | } |
6aa8b732 | 1458 | vmcs_writel(GUEST_RFLAGS, rflags); |
f244deed | 1459 | |
e7bddc52 SC |
1460 | if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) |
1461 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
1462 | } |
1463 | ||
97b7ead3 | 1464 | u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
1465 | { |
1466 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1467 | int ret = 0; | |
1468 | ||
1469 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 1470 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 1471 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 1472 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 1473 | |
37ccdcbe | 1474 | return ret; |
2809f5d2 GC |
1475 | } |
1476 | ||
97b7ead3 | 1477 | void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
2809f5d2 GC |
1478 | { |
1479 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1480 | u32 interruptibility = interruptibility_old; | |
1481 | ||
1482 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
1483 | ||
48005f64 | 1484 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 1485 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 1486 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
1487 | interruptibility |= GUEST_INTR_STATE_STI; |
1488 | ||
1489 | if ((interruptibility != interruptibility_old)) | |
1490 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
1491 | } | |
1492 | ||
bf8c55d8 CP |
1493 | static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) |
1494 | { | |
1495 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1496 | unsigned long value; | |
1497 | ||
1498 | /* | |
1499 | * Any MSR write that attempts to change bits marked reserved will | |
1500 | * case a #GP fault. | |
1501 | */ | |
1502 | if (data & vmx->pt_desc.ctl_bitmask) | |
1503 | return 1; | |
1504 | ||
1505 | /* | |
1506 | * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will | |
1507 | * result in a #GP unless the same write also clears TraceEn. | |
1508 | */ | |
1509 | if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && | |
1510 | ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) | |
1511 | return 1; | |
1512 | ||
1513 | /* | |
1514 | * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit | |
1515 | * and FabricEn would cause #GP, if | |
1516 | * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 | |
1517 | */ | |
1518 | if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && | |
1519 | !(data & RTIT_CTL_FABRIC_EN) && | |
1520 | !intel_pt_validate_cap(vmx->pt_desc.caps, | |
1521 | PT_CAP_single_range_output)) | |
1522 | return 1; | |
1523 | ||
1524 | /* | |
1525 | * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that | |
1526 | * utilize encodings marked reserved will casue a #GP fault. | |
1527 | */ | |
1528 | value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); | |
1529 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && | |
1530 | !test_bit((data & RTIT_CTL_MTC_RANGE) >> | |
1531 | RTIT_CTL_MTC_RANGE_OFFSET, &value)) | |
1532 | return 1; | |
1533 | value = intel_pt_validate_cap(vmx->pt_desc.caps, | |
1534 | PT_CAP_cycle_thresholds); | |
1535 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && | |
1536 | !test_bit((data & RTIT_CTL_CYC_THRESH) >> | |
1537 | RTIT_CTL_CYC_THRESH_OFFSET, &value)) | |
1538 | return 1; | |
1539 | value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); | |
1540 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && | |
1541 | !test_bit((data & RTIT_CTL_PSB_FREQ) >> | |
1542 | RTIT_CTL_PSB_FREQ_OFFSET, &value)) | |
1543 | return 1; | |
1544 | ||
1545 | /* | |
1546 | * If ADDRx_CFG is reserved or the encodings is >2 will | |
1547 | * cause a #GP fault. | |
1548 | */ | |
1549 | value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; | |
1550 | if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) | |
1551 | return 1; | |
1552 | value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; | |
1553 | if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) | |
1554 | return 1; | |
1555 | value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; | |
1556 | if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) | |
1557 | return 1; | |
1558 | value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; | |
1559 | if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) | |
1560 | return 1; | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
09e3e2a1 SC |
1565 | static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len) |
1566 | { | |
1567 | return true; | |
1568 | } | |
1569 | ||
1957aa63 | 1570 | static int skip_emulated_instruction(struct kvm_vcpu *vcpu) |
6aa8b732 | 1571 | { |
fede8076 | 1572 | unsigned long rip, orig_rip; |
6aa8b732 | 1573 | |
1957aa63 SC |
1574 | /* |
1575 | * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on | |
1576 | * undefined behavior: Intel's SDM doesn't mandate the VMCS field be | |
1577 | * set when EPT misconfig occurs. In practice, real hardware updates | |
1578 | * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors | |
1579 | * (namely Hyper-V) don't set it due to it being undefined behavior, | |
1580 | * i.e. we end up advancing IP with some random value. | |
1581 | */ | |
1582 | if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || | |
a6bdda1f | 1583 | to_vmx(vcpu)->exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) { |
fede8076 PB |
1584 | orig_rip = kvm_rip_read(vcpu); |
1585 | rip = orig_rip + vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
1586 | #ifdef CONFIG_X86_64 | |
1587 | /* | |
1588 | * We need to mask out the high 32 bits of RIP if not in 64-bit | |
1589 | * mode, but just finding out that we are in 64-bit mode is | |
1590 | * quite expensive. Only do it if there was a carry. | |
1591 | */ | |
1592 | if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu)) | |
1593 | rip = (u32)rip; | |
1594 | #endif | |
1957aa63 SC |
1595 | kvm_rip_write(vcpu, rip); |
1596 | } else { | |
1597 | if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) | |
1598 | return 0; | |
1599 | } | |
6aa8b732 | 1600 | |
2809f5d2 GC |
1601 | /* skipping an emulated instruction also counts */ |
1602 | vmx_set_interrupt_shadow(vcpu, 0); | |
f8ea7c60 | 1603 | |
60fc3d02 | 1604 | return 1; |
f8ea7c60 VK |
1605 | } |
1606 | ||
5ef8acbd OU |
1607 | /* |
1608 | * Recognizes a pending MTF VM-exit and records the nested state for later | |
1609 | * delivery. | |
1610 | */ | |
1611 | static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu) | |
1612 | { | |
1613 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
1614 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1615 | ||
1616 | if (!is_guest_mode(vcpu)) | |
1617 | return; | |
1618 | ||
1619 | /* | |
1620 | * Per the SDM, MTF takes priority over debug-trap exceptions besides | |
1621 | * T-bit traps. As instruction emulation is completed (i.e. at the | |
1622 | * instruction boundary), any #DB exception pending delivery must be a | |
1623 | * debug-trap. Record the pending MTF state to be delivered in | |
1624 | * vmx_check_nested_events(). | |
1625 | */ | |
1626 | if (nested_cpu_has_mtf(vmcs12) && | |
1627 | (!vcpu->arch.exception.pending || | |
1628 | vcpu->arch.exception.nr == DB_VECTOR)) | |
1629 | vmx->nested.mtf_pending = true; | |
1630 | else | |
1631 | vmx->nested.mtf_pending = false; | |
1632 | } | |
1633 | ||
1634 | static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
1635 | { | |
1636 | vmx_update_emulated_instruction(vcpu); | |
1637 | return skip_emulated_instruction(vcpu); | |
1638 | } | |
1639 | ||
caa057a2 WL |
1640 | static void vmx_clear_hlt(struct kvm_vcpu *vcpu) |
1641 | { | |
1642 | /* | |
1643 | * Ensure that we clear the HLT state in the VMCS. We don't need to | |
1644 | * explicitly skip the instruction because if the HLT state is set, | |
1645 | * then the instruction is already executing and RIP has already been | |
1646 | * advanced. | |
1647 | */ | |
1648 | if (kvm_hlt_in_guest(vcpu->kvm) && | |
1649 | vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) | |
1650 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); | |
1651 | } | |
1652 | ||
cfcd20e5 | 1653 | static void vmx_queue_exception(struct kvm_vcpu *vcpu) |
298101da | 1654 | { |
77ab6db0 | 1655 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
cfcd20e5 WL |
1656 | unsigned nr = vcpu->arch.exception.nr; |
1657 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
cfcd20e5 | 1658 | u32 error_code = vcpu->arch.exception.error_code; |
8ab2d2e2 | 1659 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 1660 | |
da998b46 JM |
1661 | kvm_deliver_exception_payload(vcpu); |
1662 | ||
8ab2d2e2 | 1663 | if (has_error_code) { |
77ab6db0 | 1664 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
1665 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
1666 | } | |
77ab6db0 | 1667 | |
7ffd92c5 | 1668 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
1669 | int inc_eip = 0; |
1670 | if (kvm_exception_is_soft(nr)) | |
1671 | inc_eip = vcpu->arch.event_exit_inst_len; | |
9497e1f2 | 1672 | kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); |
77ab6db0 JK |
1673 | return; |
1674 | } | |
1675 | ||
add5ff7a SC |
1676 | WARN_ON_ONCE(vmx->emulation_required); |
1677 | ||
66fd3f7f GN |
1678 | if (kvm_exception_is_soft(nr)) { |
1679 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
1680 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
1681 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
1682 | } else | |
1683 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
1684 | ||
1685 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
caa057a2 WL |
1686 | |
1687 | vmx_clear_hlt(vcpu); | |
298101da AK |
1688 | } |
1689 | ||
bd65ba82 | 1690 | static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr) |
a75beee6 | 1691 | { |
eb3db1b1 | 1692 | struct vmx_uret_msr tmp; |
bd65ba82 | 1693 | int from, to; |
a2fa3e9f | 1694 | |
bd65ba82 SC |
1695 | from = __vmx_find_uret_msr(vmx, msr); |
1696 | if (from < 0) | |
1697 | return; | |
1698 | to = vmx->nr_active_uret_msrs++; | |
a2fa3e9f | 1699 | |
eb3db1b1 SC |
1700 | tmp = vmx->guest_uret_msrs[to]; |
1701 | vmx->guest_uret_msrs[to] = vmx->guest_uret_msrs[from]; | |
1702 | vmx->guest_uret_msrs[from] = tmp; | |
a75beee6 ED |
1703 | } |
1704 | ||
e38aea3e AK |
1705 | /* |
1706 | * Set up the vmcs to automatically save and restore system | |
1707 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
1708 | * mode, as fiddling with msrs is very expensive. | |
1709 | */ | |
8b9cf98c | 1710 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 1711 | { |
bd65ba82 SC |
1712 | vmx->guest_uret_msrs_loaded = false; |
1713 | vmx->nr_active_uret_msrs = 0; | |
a75beee6 | 1714 | #ifdef CONFIG_X86_64 |
84c8c5b8 JM |
1715 | /* |
1716 | * The SYSCALL MSRs are only needed on long mode guests, and only | |
1717 | * when EFER.SCE is set. | |
1718 | */ | |
1719 | if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { | |
bd65ba82 SC |
1720 | vmx_setup_uret_msr(vmx, MSR_STAR); |
1721 | vmx_setup_uret_msr(vmx, MSR_LSTAR); | |
1722 | vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK); | |
a75beee6 ED |
1723 | } |
1724 | #endif | |
bd65ba82 SC |
1725 | if (update_transition_efer(vmx)) |
1726 | vmx_setup_uret_msr(vmx, MSR_EFER); | |
e38aea3e | 1727 | |
bd65ba82 SC |
1728 | if (guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) |
1729 | vmx_setup_uret_msr(vmx, MSR_TSC_AUX); | |
1730 | ||
1731 | vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL); | |
5897297b | 1732 | |
8d14695f | 1733 | if (cpu_has_vmx_msr_bitmap()) |
904e14fb | 1734 | vmx_update_msr_bitmap(&vmx->vcpu); |
e38aea3e AK |
1735 | } |
1736 | ||
326e7425 | 1737 | static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 1738 | { |
45c3af97 PB |
1739 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
1740 | u64 g_tsc_offset = 0; | |
1741 | ||
1742 | /* | |
1743 | * We're here if L1 chose not to trap WRMSR to TSC. According | |
1744 | * to the spec, this should set L1's TSC; The offset that L1 | |
1745 | * set for L2 remains unchanged, and still needs to be added | |
1746 | * to the newly set TSC to get L2's TSC. | |
1747 | */ | |
1748 | if (is_guest_mode(vcpu) && | |
5e3d394f | 1749 | (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) |
45c3af97 | 1750 | g_tsc_offset = vmcs12->tsc_offset; |
326e7425 | 1751 | |
45c3af97 PB |
1752 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
1753 | vcpu->arch.tsc_offset - g_tsc_offset, | |
1754 | offset); | |
1755 | vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); | |
1756 | return offset + g_tsc_offset; | |
6aa8b732 AK |
1757 | } |
1758 | ||
801d3424 NHE |
1759 | /* |
1760 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
1761 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
1762 | * all guests if the "nested" module option is off, and can also be disabled | |
1763 | * for a single guest by disabling its VMX cpuid bit. | |
1764 | */ | |
7c97fcb3 | 1765 | bool nested_vmx_allowed(struct kvm_vcpu *vcpu) |
801d3424 | 1766 | { |
d6321d49 | 1767 | return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); |
801d3424 NHE |
1768 | } |
1769 | ||
55d2375e SC |
1770 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
1771 | uint64_t val) | |
62cc6b9d | 1772 | { |
55d2375e | 1773 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; |
62cc6b9d | 1774 | |
55d2375e | 1775 | return !(val & ~valid_bits); |
62cc6b9d DM |
1776 | } |
1777 | ||
55d2375e | 1778 | static int vmx_get_msr_feature(struct kvm_msr_entry *msr) |
62cc6b9d | 1779 | { |
55d2375e SC |
1780 | switch (msr->index) { |
1781 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
1782 | if (!nested) | |
1783 | return 1; | |
1784 | return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); | |
27461da3 LX |
1785 | case MSR_IA32_PERF_CAPABILITIES: |
1786 | msr->data = vmx_get_perf_capabilities(); | |
1787 | return 0; | |
55d2375e | 1788 | default: |
12bc2132 | 1789 | return KVM_MSR_RET_INVALID; |
55d2375e | 1790 | } |
62cc6b9d DM |
1791 | } |
1792 | ||
55d2375e SC |
1793 | /* |
1794 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1795 | * Returns 0 on success, non-0 otherwise. | |
1796 | * Assumes vcpu_load() was already called. | |
1797 | */ | |
1798 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) | |
62cc6b9d | 1799 | { |
55d2375e | 1800 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
eb3db1b1 | 1801 | struct vmx_uret_msr *msr; |
bf8c55d8 | 1802 | u32 index; |
62cc6b9d | 1803 | |
55d2375e SC |
1804 | switch (msr_info->index) { |
1805 | #ifdef CONFIG_X86_64 | |
1806 | case MSR_FS_BASE: | |
1807 | msr_info->data = vmcs_readl(GUEST_FS_BASE); | |
62cc6b9d | 1808 | break; |
55d2375e SC |
1809 | case MSR_GS_BASE: |
1810 | msr_info->data = vmcs_readl(GUEST_GS_BASE); | |
62cc6b9d | 1811 | break; |
55d2375e SC |
1812 | case MSR_KERNEL_GS_BASE: |
1813 | msr_info->data = vmx_read_guest_kernel_gs_base(vmx); | |
62cc6b9d | 1814 | break; |
55d2375e SC |
1815 | #endif |
1816 | case MSR_EFER: | |
1817 | return kvm_get_msr_common(vcpu, msr_info); | |
c11f83e0 PB |
1818 | case MSR_IA32_TSX_CTRL: |
1819 | if (!msr_info->host_initiated && | |
1820 | !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) | |
1821 | return 1; | |
eb3db1b1 | 1822 | goto find_uret_msr; |
6e3ba4ab TX |
1823 | case MSR_IA32_UMWAIT_CONTROL: |
1824 | if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) | |
1825 | return 1; | |
1826 | ||
1827 | msr_info->data = vmx->msr_ia32_umwait_control; | |
1828 | break; | |
55d2375e SC |
1829 | case MSR_IA32_SPEC_CTRL: |
1830 | if (!msr_info->host_initiated && | |
39485ed9 | 1831 | !guest_has_spec_ctrl_msr(vcpu)) |
55d2375e SC |
1832 | return 1; |
1833 | ||
1834 | msr_info->data = to_vmx(vcpu)->spec_ctrl; | |
62cc6b9d | 1835 | break; |
6aa8b732 | 1836 | case MSR_IA32_SYSENTER_CS: |
609e36d3 | 1837 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
1838 | break; |
1839 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 1840 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
1841 | break; |
1842 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 1843 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 1844 | break; |
0dd376e7 | 1845 | case MSR_IA32_BNDCFGS: |
691bd434 | 1846 | if (!kvm_mpx_supported() || |
d6321d49 RK |
1847 | (!msr_info->host_initiated && |
1848 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 1849 | return 1; |
609e36d3 | 1850 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 1851 | break; |
c45dcc71 AR |
1852 | case MSR_IA32_MCG_EXT_CTL: |
1853 | if (!msr_info->host_initiated && | |
a6cb099a | 1854 | !(vmx->msr_ia32_feature_control & |
32ad73db | 1855 | FEAT_CTL_LMCE_ENABLED)) |
cae50139 | 1856 | return 1; |
c45dcc71 AR |
1857 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
1858 | break; | |
32ad73db | 1859 | case MSR_IA32_FEAT_CTL: |
a6cb099a | 1860 | msr_info->data = vmx->msr_ia32_feature_control; |
cae50139 JK |
1861 | break; |
1862 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
1863 | if (!nested_vmx_allowed(vcpu)) | |
1864 | return 1; | |
31de3d25 VK |
1865 | if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, |
1866 | &msr_info->data)) | |
1867 | return 1; | |
1868 | /* | |
1869 | * Enlightened VMCS v1 doesn't have certain fields, but buggy | |
1870 | * Hyper-V versions are still trying to use corresponding | |
1871 | * features when they are exposed. Filter out the essential | |
1872 | * minimum. | |
1873 | */ | |
1874 | if (!msr_info->host_initiated && | |
1875 | vmx->nested.enlightened_vmcs_enabled) | |
1876 | nested_evmcs_filter_control_msr(msr_info->index, | |
1877 | &msr_info->data); | |
1878 | break; | |
bf8c55d8 | 1879 | case MSR_IA32_RTIT_CTL: |
2ef7619d | 1880 | if (!vmx_pt_mode_is_host_guest()) |
bf8c55d8 CP |
1881 | return 1; |
1882 | msr_info->data = vmx->pt_desc.guest.ctl; | |
1883 | break; | |
1884 | case MSR_IA32_RTIT_STATUS: | |
2ef7619d | 1885 | if (!vmx_pt_mode_is_host_guest()) |
bf8c55d8 CP |
1886 | return 1; |
1887 | msr_info->data = vmx->pt_desc.guest.status; | |
1888 | break; | |
1889 | case MSR_IA32_RTIT_CR3_MATCH: | |
2ef7619d | 1890 | if (!vmx_pt_mode_is_host_guest() || |
bf8c55d8 CP |
1891 | !intel_pt_validate_cap(vmx->pt_desc.caps, |
1892 | PT_CAP_cr3_filtering)) | |
1893 | return 1; | |
1894 | msr_info->data = vmx->pt_desc.guest.cr3_match; | |
1895 | break; | |
1896 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
2ef7619d | 1897 | if (!vmx_pt_mode_is_host_guest() || |
bf8c55d8 CP |
1898 | (!intel_pt_validate_cap(vmx->pt_desc.caps, |
1899 | PT_CAP_topa_output) && | |
1900 | !intel_pt_validate_cap(vmx->pt_desc.caps, | |
1901 | PT_CAP_single_range_output))) | |
1902 | return 1; | |
1903 | msr_info->data = vmx->pt_desc.guest.output_base; | |
1904 | break; | |
1905 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
2ef7619d | 1906 | if (!vmx_pt_mode_is_host_guest() || |
bf8c55d8 CP |
1907 | (!intel_pt_validate_cap(vmx->pt_desc.caps, |
1908 | PT_CAP_topa_output) && | |
1909 | !intel_pt_validate_cap(vmx->pt_desc.caps, | |
1910 | PT_CAP_single_range_output))) | |
1911 | return 1; | |
1912 | msr_info->data = vmx->pt_desc.guest.output_mask; | |
1913 | break; | |
1914 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: | |
1915 | index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; | |
2ef7619d | 1916 | if (!vmx_pt_mode_is_host_guest() || |
bf8c55d8 CP |
1917 | (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, |
1918 | PT_CAP_num_address_ranges))) | |
1919 | return 1; | |
1920 | if (index % 2) | |
1921 | msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; | |
1922 | else | |
1923 | msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; | |
1924 | break; | |
4e47c7a6 | 1925 | case MSR_TSC_AUX: |
d6321d49 RK |
1926 | if (!msr_info->host_initiated && |
1927 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 | 1928 | return 1; |
eb3db1b1 | 1929 | goto find_uret_msr; |
6aa8b732 | 1930 | default: |
eb3db1b1 | 1931 | find_uret_msr: |
d85a8034 | 1932 | msr = vmx_find_uret_msr(vmx, msr_info->index); |
3bab1f5d | 1933 | if (msr) { |
609e36d3 | 1934 | msr_info->data = msr->data; |
3bab1f5d | 1935 | break; |
6aa8b732 | 1936 | } |
609e36d3 | 1937 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
1938 | } |
1939 | ||
6aa8b732 AK |
1940 | return 0; |
1941 | } | |
1942 | ||
2408500d SC |
1943 | static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu, |
1944 | u64 data) | |
1945 | { | |
1946 | #ifdef CONFIG_X86_64 | |
1947 | if (!guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1948 | return (u32)data; | |
1949 | #endif | |
1950 | return (unsigned long)data; | |
1951 | } | |
1952 | ||
6aa8b732 | 1953 | /* |
311497e0 | 1954 | * Writes msr value into the appropriate "register". |
6aa8b732 AK |
1955 | * Returns 0 on success, non-0 otherwise. |
1956 | * Assumes vcpu_load() was already called. | |
1957 | */ | |
8fe8ab46 | 1958 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 1959 | { |
a2fa3e9f | 1960 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
eb3db1b1 | 1961 | struct vmx_uret_msr *msr; |
2cc51560 | 1962 | int ret = 0; |
8fe8ab46 WA |
1963 | u32 msr_index = msr_info->index; |
1964 | u64 data = msr_info->data; | |
bf8c55d8 | 1965 | u32 index; |
2cc51560 | 1966 | |
6aa8b732 | 1967 | switch (msr_index) { |
3bab1f5d | 1968 | case MSR_EFER: |
8fe8ab46 | 1969 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 1970 | break; |
16175a79 | 1971 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1972 | case MSR_FS_BASE: |
2fb92db1 | 1973 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
1974 | vmcs_writel(GUEST_FS_BASE, data); |
1975 | break; | |
1976 | case MSR_GS_BASE: | |
2fb92db1 | 1977 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
1978 | vmcs_writel(GUEST_GS_BASE, data); |
1979 | break; | |
44ea2b17 | 1980 | case MSR_KERNEL_GS_BASE: |
678e315e | 1981 | vmx_write_guest_kernel_gs_base(vmx, data); |
44ea2b17 | 1982 | break; |
6aa8b732 AK |
1983 | #endif |
1984 | case MSR_IA32_SYSENTER_CS: | |
de70d279 SC |
1985 | if (is_guest_mode(vcpu)) |
1986 | get_vmcs12(vcpu)->guest_sysenter_cs = data; | |
6aa8b732 AK |
1987 | vmcs_write32(GUEST_SYSENTER_CS, data); |
1988 | break; | |
1989 | case MSR_IA32_SYSENTER_EIP: | |
2408500d SC |
1990 | if (is_guest_mode(vcpu)) { |
1991 | data = nested_vmx_truncate_sysenter_addr(vcpu, data); | |
de70d279 | 1992 | get_vmcs12(vcpu)->guest_sysenter_eip = data; |
2408500d | 1993 | } |
f5b42c33 | 1994 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
1995 | break; |
1996 | case MSR_IA32_SYSENTER_ESP: | |
2408500d SC |
1997 | if (is_guest_mode(vcpu)) { |
1998 | data = nested_vmx_truncate_sysenter_addr(vcpu, data); | |
de70d279 | 1999 | get_vmcs12(vcpu)->guest_sysenter_esp = data; |
2408500d | 2000 | } |
f5b42c33 | 2001 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 2002 | break; |
699a1ac2 SC |
2003 | case MSR_IA32_DEBUGCTLMSR: |
2004 | if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & | |
2005 | VM_EXIT_SAVE_DEBUG_CONTROLS) | |
2006 | get_vmcs12(vcpu)->guest_ia32_debugctl = data; | |
2007 | ||
2008 | ret = kvm_set_msr_common(vcpu, msr_info); | |
2009 | break; | |
2010 | ||
0dd376e7 | 2011 | case MSR_IA32_BNDCFGS: |
691bd434 | 2012 | if (!kvm_mpx_supported() || |
d6321d49 RK |
2013 | (!msr_info->host_initiated && |
2014 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 2015 | return 1; |
fd8cb433 | 2016 | if (is_noncanonical_address(data & PAGE_MASK, vcpu) || |
4531662d | 2017 | (data & MSR_IA32_BNDCFGS_RSVD)) |
93c4adc7 | 2018 | return 1; |
0dd376e7 LJ |
2019 | vmcs_write64(GUEST_BNDCFGS, data); |
2020 | break; | |
6e3ba4ab TX |
2021 | case MSR_IA32_UMWAIT_CONTROL: |
2022 | if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) | |
2023 | return 1; | |
2024 | ||
2025 | /* The reserved bit 1 and non-32 bit [63:32] should be zero */ | |
2026 | if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) | |
2027 | return 1; | |
2028 | ||
2029 | vmx->msr_ia32_umwait_control = data; | |
2030 | break; | |
d28b387f KA |
2031 | case MSR_IA32_SPEC_CTRL: |
2032 | if (!msr_info->host_initiated && | |
39485ed9 | 2033 | !guest_has_spec_ctrl_msr(vcpu)) |
d28b387f KA |
2034 | return 1; |
2035 | ||
841c2be0 | 2036 | if (kvm_spec_ctrl_test_value(data)) |
d28b387f KA |
2037 | return 1; |
2038 | ||
2039 | vmx->spec_ctrl = data; | |
d28b387f KA |
2040 | if (!data) |
2041 | break; | |
2042 | ||
2043 | /* | |
2044 | * For non-nested: | |
2045 | * When it's written (to non-zero) for the first time, pass | |
2046 | * it through. | |
2047 | * | |
2048 | * For nested: | |
2049 | * The handling of the MSR bitmap for L2 guests is done in | |
4d516fe7 | 2050 | * nested_vmx_prepare_msr_bitmap. We should not touch the |
d28b387f KA |
2051 | * vmcs02.msr_bitmap here since it gets completely overwritten |
2052 | * in the merging. We update the vmcs01 here for L1 as well | |
2053 | * since it will end up touching the MSR anyway now. | |
2054 | */ | |
476c9bd8 | 2055 | vmx_disable_intercept_for_msr(vcpu, |
d28b387f KA |
2056 | MSR_IA32_SPEC_CTRL, |
2057 | MSR_TYPE_RW); | |
2058 | break; | |
c11f83e0 PB |
2059 | case MSR_IA32_TSX_CTRL: |
2060 | if (!msr_info->host_initiated && | |
2061 | !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) | |
2062 | return 1; | |
2063 | if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) | |
2064 | return 1; | |
eb3db1b1 | 2065 | goto find_uret_msr; |
15d45071 AR |
2066 | case MSR_IA32_PRED_CMD: |
2067 | if (!msr_info->host_initiated && | |
39485ed9 | 2068 | !guest_has_pred_cmd_msr(vcpu)) |
15d45071 AR |
2069 | return 1; |
2070 | ||
2071 | if (data & ~PRED_CMD_IBPB) | |
2072 | return 1; | |
39485ed9 | 2073 | if (!boot_cpu_has(X86_FEATURE_IBPB)) |
6441fa61 | 2074 | return 1; |
15d45071 AR |
2075 | if (!data) |
2076 | break; | |
2077 | ||
2078 | wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); | |
2079 | ||
2080 | /* | |
2081 | * For non-nested: | |
2082 | * When it's written (to non-zero) for the first time, pass | |
2083 | * it through. | |
2084 | * | |
2085 | * For nested: | |
2086 | * The handling of the MSR bitmap for L2 guests is done in | |
4d516fe7 | 2087 | * nested_vmx_prepare_msr_bitmap. We should not touch the |
15d45071 AR |
2088 | * vmcs02.msr_bitmap here since it gets completely overwritten |
2089 | * in the merging. | |
2090 | */ | |
476c9bd8 | 2091 | vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W); |
15d45071 | 2092 | break; |
468d472f | 2093 | case MSR_IA32_CR_PAT: |
d28f4290 SC |
2094 | if (!kvm_pat_valid(data)) |
2095 | return 1; | |
2096 | ||
142e4be7 SC |
2097 | if (is_guest_mode(vcpu) && |
2098 | get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) | |
2099 | get_vmcs12(vcpu)->guest_ia32_pat = data; | |
2100 | ||
468d472f SY |
2101 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
2102 | vmcs_write64(GUEST_IA32_PAT, data); | |
2103 | vcpu->arch.pat = data; | |
2104 | break; | |
2105 | } | |
8fe8ab46 | 2106 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 2107 | break; |
ba904635 WA |
2108 | case MSR_IA32_TSC_ADJUST: |
2109 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 2110 | break; |
c45dcc71 AR |
2111 | case MSR_IA32_MCG_EXT_CTL: |
2112 | if ((!msr_info->host_initiated && | |
2113 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
32ad73db | 2114 | FEAT_CTL_LMCE_ENABLED)) || |
c45dcc71 AR |
2115 | (data & ~MCG_EXT_CTL_LMCE_EN)) |
2116 | return 1; | |
2117 | vcpu->arch.mcg_ext_ctl = data; | |
2118 | break; | |
32ad73db | 2119 | case MSR_IA32_FEAT_CTL: |
37e4c997 | 2120 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 2121 | (to_vmx(vcpu)->msr_ia32_feature_control & |
32ad73db | 2122 | FEAT_CTL_LOCKED && !msr_info->host_initiated)) |
cae50139 | 2123 | return 1; |
3b84080b | 2124 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
2125 | if (msr_info->host_initiated && data == 0) |
2126 | vmx_leave_nested(vcpu); | |
2127 | break; | |
2128 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
2129 | if (!msr_info->host_initiated) |
2130 | return 1; /* they are read-only */ | |
2131 | if (!nested_vmx_allowed(vcpu)) | |
2132 | return 1; | |
2133 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
bf8c55d8 | 2134 | case MSR_IA32_RTIT_CTL: |
2ef7619d | 2135 | if (!vmx_pt_mode_is_host_guest() || |
ee85dec2 LK |
2136 | vmx_rtit_ctl_check(vcpu, data) || |
2137 | vmx->nested.vmxon) | |
bf8c55d8 CP |
2138 | return 1; |
2139 | vmcs_write64(GUEST_IA32_RTIT_CTL, data); | |
2140 | vmx->pt_desc.guest.ctl = data; | |
476c9bd8 | 2141 | pt_update_intercept_for_msr(vcpu); |
bf8c55d8 CP |
2142 | break; |
2143 | case MSR_IA32_RTIT_STATUS: | |
e348ac7c SC |
2144 | if (!pt_can_write_msr(vmx)) |
2145 | return 1; | |
2146 | if (data & MSR_IA32_RTIT_STATUS_MASK) | |
bf8c55d8 CP |
2147 | return 1; |
2148 | vmx->pt_desc.guest.status = data; | |
2149 | break; | |
2150 | case MSR_IA32_RTIT_CR3_MATCH: | |
e348ac7c SC |
2151 | if (!pt_can_write_msr(vmx)) |
2152 | return 1; | |
2153 | if (!intel_pt_validate_cap(vmx->pt_desc.caps, | |
2154 | PT_CAP_cr3_filtering)) | |
bf8c55d8 CP |
2155 | return 1; |
2156 | vmx->pt_desc.guest.cr3_match = data; | |
2157 | break; | |
2158 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
e348ac7c SC |
2159 | if (!pt_can_write_msr(vmx)) |
2160 | return 1; | |
2161 | if (!intel_pt_validate_cap(vmx->pt_desc.caps, | |
2162 | PT_CAP_topa_output) && | |
2163 | !intel_pt_validate_cap(vmx->pt_desc.caps, | |
2164 | PT_CAP_single_range_output)) | |
2165 | return 1; | |
1cc6cbc3 | 2166 | if (!pt_output_base_valid(vcpu, data)) |
bf8c55d8 CP |
2167 | return 1; |
2168 | vmx->pt_desc.guest.output_base = data; | |
2169 | break; | |
2170 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
e348ac7c SC |
2171 | if (!pt_can_write_msr(vmx)) |
2172 | return 1; | |
2173 | if (!intel_pt_validate_cap(vmx->pt_desc.caps, | |
2174 | PT_CAP_topa_output) && | |
2175 | !intel_pt_validate_cap(vmx->pt_desc.caps, | |
2176 | PT_CAP_single_range_output)) | |
bf8c55d8 CP |
2177 | return 1; |
2178 | vmx->pt_desc.guest.output_mask = data; | |
2179 | break; | |
2180 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: | |
e348ac7c SC |
2181 | if (!pt_can_write_msr(vmx)) |
2182 | return 1; | |
bf8c55d8 | 2183 | index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; |
e348ac7c SC |
2184 | if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, |
2185 | PT_CAP_num_address_ranges)) | |
bf8c55d8 | 2186 | return 1; |
fe6ed369 | 2187 | if (is_noncanonical_address(data, vcpu)) |
bf8c55d8 CP |
2188 | return 1; |
2189 | if (index % 2) | |
2190 | vmx->pt_desc.guest.addr_b[index / 2] = data; | |
2191 | else | |
2192 | vmx->pt_desc.guest.addr_a[index / 2] = data; | |
2193 | break; | |
4e47c7a6 | 2194 | case MSR_TSC_AUX: |
d6321d49 RK |
2195 | if (!msr_info->host_initiated && |
2196 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
2197 | return 1; |
2198 | /* Check reserved bit, higher 32 bits should be zero */ | |
2199 | if ((data >> 32) != 0) | |
2200 | return 1; | |
eb3db1b1 | 2201 | goto find_uret_msr; |
c11f83e0 | 2202 | |
6aa8b732 | 2203 | default: |
eb3db1b1 | 2204 | find_uret_msr: |
d85a8034 | 2205 | msr = vmx_find_uret_msr(vmx, msr_index); |
b07a5c53 | 2206 | if (msr) |
7bf662bb | 2207 | ret = vmx_set_guest_uret_msr(vmx, msr, data); |
b07a5c53 PB |
2208 | else |
2209 | ret = kvm_set_msr_common(vcpu, msr_info); | |
6aa8b732 AK |
2210 | } |
2211 | ||
2cc51560 | 2212 | return ret; |
6aa8b732 AK |
2213 | } |
2214 | ||
5fdbf976 | 2215 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 2216 | { |
f98c1e77 SC |
2217 | unsigned long guest_owned_bits; |
2218 | ||
cb3c1e2f SC |
2219 | kvm_register_mark_available(vcpu, reg); |
2220 | ||
5fdbf976 MT |
2221 | switch (reg) { |
2222 | case VCPU_REGS_RSP: | |
2223 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
2224 | break; | |
2225 | case VCPU_REGS_RIP: | |
2226 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
2227 | break; | |
6de4f3ad AK |
2228 | case VCPU_EXREG_PDPTR: |
2229 | if (enable_ept) | |
2230 | ept_save_pdptrs(vcpu); | |
2231 | break; | |
bd31fe49 SC |
2232 | case VCPU_EXREG_CR0: |
2233 | guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
2234 | ||
2235 | vcpu->arch.cr0 &= ~guest_owned_bits; | |
2236 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits; | |
2237 | break; | |
34059c25 | 2238 | case VCPU_EXREG_CR3: |
bddd82d1 KS |
2239 | if (is_unrestricted_guest(vcpu) || |
2240 | (enable_ept && is_paging(vcpu))) | |
34059c25 SC |
2241 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); |
2242 | break; | |
f98c1e77 SC |
2243 | case VCPU_EXREG_CR4: |
2244 | guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; | |
2245 | ||
2246 | vcpu->arch.cr4 &= ~guest_owned_bits; | |
2247 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits; | |
2248 | break; | |
5fdbf976 | 2249 | default: |
34059c25 | 2250 | WARN_ON_ONCE(1); |
5fdbf976 MT |
2251 | break; |
2252 | } | |
6aa8b732 AK |
2253 | } |
2254 | ||
6aa8b732 AK |
2255 | static __init int cpu_has_kvm_support(void) |
2256 | { | |
6210e37b | 2257 | return cpu_has_vmx(); |
6aa8b732 AK |
2258 | } |
2259 | ||
2260 | static __init int vmx_disabled_by_bios(void) | |
2261 | { | |
a4d0b2fd SC |
2262 | return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || |
2263 | !boot_cpu_has(X86_FEATURE_VMX); | |
6aa8b732 AK |
2264 | } |
2265 | ||
4f6ea0a8 | 2266 | static int kvm_cpu_vmxon(u64 vmxon_pointer) |
7725b894 | 2267 | { |
4f6ea0a8 SC |
2268 | u64 msr; |
2269 | ||
fe0e80be | 2270 | cr4_set_bits(X86_CR4_VMXE); |
1c5ac21a AS |
2271 | intel_pt_handle_vmx(1); |
2272 | ||
4f6ea0a8 SC |
2273 | asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t" |
2274 | _ASM_EXTABLE(1b, %l[fault]) | |
2275 | : : [vmxon_pointer] "m"(vmxon_pointer) | |
2276 | : : fault); | |
2277 | return 0; | |
2278 | ||
2279 | fault: | |
2280 | WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n", | |
2281 | rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); | |
2282 | intel_pt_handle_vmx(0); | |
2283 | cr4_clear_bits(X86_CR4_VMXE); | |
2284 | ||
2285 | return -EFAULT; | |
7725b894 DX |
2286 | } |
2287 | ||
13a34e06 | 2288 | static int hardware_enable(void) |
6aa8b732 AK |
2289 | { |
2290 | int cpu = raw_smp_processor_id(); | |
2291 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
4f6ea0a8 | 2292 | int r; |
6aa8b732 | 2293 | |
1e02ce4c | 2294 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
2295 | return -EBUSY; |
2296 | ||
773e8a04 VK |
2297 | /* |
2298 | * This can happen if we hot-added a CPU but failed to allocate | |
2299 | * VP assist page for it. | |
2300 | */ | |
2301 | if (static_branch_unlikely(&enable_evmcs) && | |
2302 | !hv_get_vp_assist_page(cpu)) | |
2303 | return -EFAULT; | |
2304 | ||
4f6ea0a8 SC |
2305 | r = kvm_cpu_vmxon(phys_addr); |
2306 | if (r) | |
2307 | return r; | |
8f536b76 | 2308 | |
fdf288bf DH |
2309 | if (enable_ept) |
2310 | ept_sync_global(); | |
10474ae8 AG |
2311 | |
2312 | return 0; | |
6aa8b732 AK |
2313 | } |
2314 | ||
d462b819 | 2315 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
2316 | { |
2317 | int cpu = raw_smp_processor_id(); | |
d462b819 | 2318 | struct loaded_vmcs *v, *n; |
543e4243 | 2319 | |
d462b819 NHE |
2320 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
2321 | loaded_vmcss_on_cpu_link) | |
2322 | __loaded_vmcs_clear(v); | |
543e4243 AK |
2323 | } |
2324 | ||
710ff4a8 EH |
2325 | |
2326 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
2327 | * tricks. | |
2328 | */ | |
2329 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 2330 | { |
4b1e5478 | 2331 | asm volatile (__ex("vmxoff")); |
1c5ac21a AS |
2332 | |
2333 | intel_pt_handle_vmx(0); | |
fe0e80be | 2334 | cr4_clear_bits(X86_CR4_VMXE); |
6aa8b732 AK |
2335 | } |
2336 | ||
13a34e06 | 2337 | static void hardware_disable(void) |
710ff4a8 | 2338 | { |
fe0e80be DH |
2339 | vmclear_local_loaded_vmcss(); |
2340 | kvm_cpu_vmxoff(); | |
710ff4a8 EH |
2341 | } |
2342 | ||
7a57c09b SC |
2343 | /* |
2344 | * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID | |
2345 | * directly instead of going through cpu_has(), to ensure KVM is trapping | |
2346 | * ENCLS whenever it's supported in hardware. It does not matter whether | |
2347 | * the host OS supports or has enabled SGX. | |
2348 | */ | |
2349 | static bool cpu_has_sgx(void) | |
2350 | { | |
2351 | return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0)); | |
2352 | } | |
2353 | ||
1c3d14fe | 2354 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 2355 | u32 msr, u32 *result) |
1c3d14fe YS |
2356 | { |
2357 | u32 vmx_msr_low, vmx_msr_high; | |
2358 | u32 ctl = ctl_min | ctl_opt; | |
2359 | ||
2360 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
2361 | ||
2362 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
2363 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
2364 | ||
2365 | /* Ensure minimum (required) set of control bits are supported. */ | |
2366 | if (ctl_min & ~ctl) | |
002c7f7c | 2367 | return -EIO; |
1c3d14fe YS |
2368 | |
2369 | *result = ctl; | |
2370 | return 0; | |
2371 | } | |
2372 | ||
7caaa711 SC |
2373 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, |
2374 | struct vmx_capability *vmx_cap) | |
6aa8b732 AK |
2375 | { |
2376 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 2377 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
2378 | u32 _pin_based_exec_control = 0; |
2379 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 2380 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
2381 | u32 _vmexit_control = 0; |
2382 | u32 _vmentry_control = 0; | |
2383 | ||
1389309c | 2384 | memset(vmcs_conf, 0, sizeof(*vmcs_conf)); |
10166744 | 2385 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
2386 | #ifdef CONFIG_X86_64 |
2387 | CPU_BASED_CR8_LOAD_EXITING | | |
2388 | CPU_BASED_CR8_STORE_EXITING | | |
2389 | #endif | |
d56f546d SY |
2390 | CPU_BASED_CR3_LOAD_EXITING | |
2391 | CPU_BASED_CR3_STORE_EXITING | | |
8eb73e2d | 2392 | CPU_BASED_UNCOND_IO_EXITING | |
1c3d14fe | 2393 | CPU_BASED_MOV_DR_EXITING | |
5e3d394f | 2394 | CPU_BASED_USE_TSC_OFFSETTING | |
4d5422ce WL |
2395 | CPU_BASED_MWAIT_EXITING | |
2396 | CPU_BASED_MONITOR_EXITING | | |
fee84b07 AK |
2397 | CPU_BASED_INVLPG_EXITING | |
2398 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 2399 | |
f78e0e2e | 2400 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 2401 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 2402 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
2403 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
2404 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 2405 | return -EIO; |
6e5d865c YS |
2406 | #ifdef CONFIG_X86_64 |
2407 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
2408 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
2409 | ~CPU_BASED_CR8_STORE_EXITING; | |
2410 | #endif | |
f78e0e2e | 2411 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
2412 | min2 = 0; |
2413 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 2414 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 2415 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 2416 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 2417 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 2418 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 2419 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
0367f205 | 2420 | SECONDARY_EXEC_DESC | |
7f3603b6 | 2421 | SECONDARY_EXEC_ENABLE_RDTSCP | |
83d4c286 | 2422 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 2423 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 2424 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 2425 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 2426 | SECONDARY_EXEC_XSAVES | |
736fdf72 DH |
2427 | SECONDARY_EXEC_RDSEED_EXITING | |
2428 | SECONDARY_EXEC_RDRAND_EXITING | | |
8b3e34e4 | 2429 | SECONDARY_EXEC_ENABLE_PML | |
2a499e49 | 2430 | SECONDARY_EXEC_TSC_SCALING | |
e69e72fa | 2431 | SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | |
f99e3daf CP |
2432 | SECONDARY_EXEC_PT_USE_GPA | |
2433 | SECONDARY_EXEC_PT_CONCEAL_VMX | | |
7a57c09b SC |
2434 | SECONDARY_EXEC_ENABLE_VMFUNC; |
2435 | if (cpu_has_sgx()) | |
2436 | opt2 |= SECONDARY_EXEC_ENCLS_EXITING; | |
d56f546d SY |
2437 | if (adjust_vmx_controls(min2, opt2, |
2438 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
2439 | &_cpu_based_2nd_exec_control) < 0) |
2440 | return -EIO; | |
2441 | } | |
2442 | #ifndef CONFIG_X86_64 | |
2443 | if (!(_cpu_based_2nd_exec_control & | |
2444 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
2445 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2446 | #endif | |
83d4c286 YZ |
2447 | |
2448 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
2449 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 2450 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
2451 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2452 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 2453 | |
61f1dd90 | 2454 | rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, |
7caaa711 | 2455 | &vmx_cap->ept, &vmx_cap->vpid); |
61f1dd90 | 2456 | |
d56f546d | 2457 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
2458 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
2459 | enabled */ | |
5fff7d27 GN |
2460 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
2461 | CPU_BASED_CR3_STORE_EXITING | | |
2462 | CPU_BASED_INVLPG_EXITING); | |
7caaa711 SC |
2463 | } else if (vmx_cap->ept) { |
2464 | vmx_cap->ept = 0; | |
61f1dd90 WL |
2465 | pr_warn_once("EPT CAP should not exist if not support " |
2466 | "1-setting enable EPT VM-execution control\n"); | |
2467 | } | |
2468 | if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && | |
7caaa711 SC |
2469 | vmx_cap->vpid) { |
2470 | vmx_cap->vpid = 0; | |
61f1dd90 WL |
2471 | pr_warn_once("VPID CAP should not exist if not support " |
2472 | "1-setting enable VPID VM-execution control\n"); | |
d56f546d | 2473 | } |
1c3d14fe | 2474 | |
91fa0f8e | 2475 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
2476 | #ifdef CONFIG_X86_64 |
2477 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
2478 | #endif | |
c73da3fc | 2479 | opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | |
c73da3fc SC |
2480 | VM_EXIT_LOAD_IA32_PAT | |
2481 | VM_EXIT_LOAD_IA32_EFER | | |
f99e3daf CP |
2482 | VM_EXIT_CLEAR_BNDCFGS | |
2483 | VM_EXIT_PT_CONCEAL_PIP | | |
2484 | VM_EXIT_CLEAR_IA32_RTIT_CTL; | |
1c3d14fe YS |
2485 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
2486 | &_vmexit_control) < 0) | |
002c7f7c | 2487 | return -EIO; |
1c3d14fe | 2488 | |
8a1b4392 PB |
2489 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
2490 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | | |
2491 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
2492 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
2493 | &_pin_based_exec_control) < 0) | |
2494 | return -EIO; | |
2495 | ||
1c17c3e6 PB |
2496 | if (cpu_has_broken_vmx_preemption_timer()) |
2497 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 2498 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 2499 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
2500 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
2501 | ||
c845f9c6 | 2502 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
c73da3fc SC |
2503 | opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | |
2504 | VM_ENTRY_LOAD_IA32_PAT | | |
2505 | VM_ENTRY_LOAD_IA32_EFER | | |
f99e3daf CP |
2506 | VM_ENTRY_LOAD_BNDCFGS | |
2507 | VM_ENTRY_PT_CONCEAL_PIP | | |
2508 | VM_ENTRY_LOAD_IA32_RTIT_CTL; | |
1c3d14fe YS |
2509 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
2510 | &_vmentry_control) < 0) | |
002c7f7c | 2511 | return -EIO; |
6aa8b732 | 2512 | |
c73da3fc SC |
2513 | /* |
2514 | * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they | |
2515 | * can't be used due to an errata where VM Exit may incorrectly clear | |
2516 | * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the | |
2517 | * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. | |
2518 | */ | |
2519 | if (boot_cpu_data.x86 == 0x6) { | |
2520 | switch (boot_cpu_data.x86_model) { | |
2521 | case 26: /* AAK155 */ | |
2522 | case 30: /* AAP115 */ | |
2523 | case 37: /* AAT100 */ | |
2524 | case 44: /* BC86,AAY89,BD102 */ | |
2525 | case 46: /* BA97 */ | |
85ba2b16 | 2526 | _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; |
c73da3fc SC |
2527 | _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; |
2528 | pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
2529 | "does not work properly. Using workaround\n"); | |
2530 | break; | |
2531 | default: | |
2532 | break; | |
2533 | } | |
2534 | } | |
2535 | ||
2536 | ||
c68876fd | 2537 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
2538 | |
2539 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
2540 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 2541 | return -EIO; |
1c3d14fe YS |
2542 | |
2543 | #ifdef CONFIG_X86_64 | |
2544 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
2545 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 2546 | return -EIO; |
1c3d14fe YS |
2547 | #endif |
2548 | ||
2549 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
2550 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 2551 | return -EIO; |
1c3d14fe | 2552 | |
002c7f7c | 2553 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 2554 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 2555 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
773e8a04 | 2556 | |
2307af1c | 2557 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 2558 | |
002c7f7c YS |
2559 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
2560 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 2561 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
2562 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
2563 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 2564 | |
064eedf2 VK |
2565 | #if IS_ENABLED(CONFIG_HYPERV) |
2566 | if (enlightened_vmcs) | |
773e8a04 | 2567 | evmcs_sanitize_exec_ctrls(vmcs_conf); |
064eedf2 | 2568 | #endif |
773e8a04 | 2569 | |
1c3d14fe | 2570 | return 0; |
c68876fd | 2571 | } |
6aa8b732 | 2572 | |
41836839 | 2573 | struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) |
6aa8b732 AK |
2574 | { |
2575 | int node = cpu_to_node(cpu); | |
2576 | struct page *pages; | |
2577 | struct vmcs *vmcs; | |
2578 | ||
41836839 | 2579 | pages = __alloc_pages_node(node, flags, vmcs_config.order); |
6aa8b732 AK |
2580 | if (!pages) |
2581 | return NULL; | |
2582 | vmcs = page_address(pages); | |
1c3d14fe | 2583 | memset(vmcs, 0, vmcs_config.size); |
2307af1c LA |
2584 | |
2585 | /* KVM supports Enlightened VMCS v1 only */ | |
2586 | if (static_branch_unlikely(&enable_evmcs)) | |
392b2f25 | 2587 | vmcs->hdr.revision_id = KVM_EVMCS_VERSION; |
2307af1c | 2588 | else |
392b2f25 | 2589 | vmcs->hdr.revision_id = vmcs_config.revision_id; |
2307af1c | 2590 | |
491a6038 LA |
2591 | if (shadow) |
2592 | vmcs->hdr.shadow_vmcs = 1; | |
6aa8b732 AK |
2593 | return vmcs; |
2594 | } | |
2595 | ||
89b0c9f5 | 2596 | void free_vmcs(struct vmcs *vmcs) |
6aa8b732 | 2597 | { |
1c3d14fe | 2598 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
2599 | } |
2600 | ||
d462b819 NHE |
2601 | /* |
2602 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
2603 | */ | |
89b0c9f5 | 2604 | void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) |
d462b819 NHE |
2605 | { |
2606 | if (!loaded_vmcs->vmcs) | |
2607 | return; | |
2608 | loaded_vmcs_clear(loaded_vmcs); | |
2609 | free_vmcs(loaded_vmcs->vmcs); | |
2610 | loaded_vmcs->vmcs = NULL; | |
904e14fb PB |
2611 | if (loaded_vmcs->msr_bitmap) |
2612 | free_page((unsigned long)loaded_vmcs->msr_bitmap); | |
355f4fb1 | 2613 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
2614 | } |
2615 | ||
89b0c9f5 | 2616 | int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) |
f21f165e | 2617 | { |
491a6038 | 2618 | loaded_vmcs->vmcs = alloc_vmcs(false); |
f21f165e PB |
2619 | if (!loaded_vmcs->vmcs) |
2620 | return -ENOMEM; | |
2621 | ||
d260f9ef SC |
2622 | vmcs_clear(loaded_vmcs->vmcs); |
2623 | ||
f21f165e | 2624 | loaded_vmcs->shadow_vmcs = NULL; |
804939ea | 2625 | loaded_vmcs->hv_timer_soft_disabled = false; |
d260f9ef SC |
2626 | loaded_vmcs->cpu = -1; |
2627 | loaded_vmcs->launched = 0; | |
904e14fb PB |
2628 | |
2629 | if (cpu_has_vmx_msr_bitmap()) { | |
41836839 BG |
2630 | loaded_vmcs->msr_bitmap = (unsigned long *) |
2631 | __get_free_page(GFP_KERNEL_ACCOUNT); | |
904e14fb PB |
2632 | if (!loaded_vmcs->msr_bitmap) |
2633 | goto out_vmcs; | |
2634 | memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); | |
ceef7d10 | 2635 | |
1f008e11 AB |
2636 | if (IS_ENABLED(CONFIG_HYPERV) && |
2637 | static_branch_unlikely(&enable_evmcs) && | |
ceef7d10 VK |
2638 | (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { |
2639 | struct hv_enlightened_vmcs *evmcs = | |
2640 | (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; | |
2641 | ||
2642 | evmcs->hv_enlightenments_control.msr_bitmap = 1; | |
2643 | } | |
904e14fb | 2644 | } |
d7ee039e SC |
2645 | |
2646 | memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); | |
3af80fec SC |
2647 | memset(&loaded_vmcs->controls_shadow, 0, |
2648 | sizeof(struct vmcs_controls_shadow)); | |
d7ee039e | 2649 | |
f21f165e | 2650 | return 0; |
904e14fb PB |
2651 | |
2652 | out_vmcs: | |
2653 | free_loaded_vmcs(loaded_vmcs); | |
2654 | return -ENOMEM; | |
f21f165e PB |
2655 | } |
2656 | ||
39959588 | 2657 | static void free_kvm_area(void) |
6aa8b732 AK |
2658 | { |
2659 | int cpu; | |
2660 | ||
3230bb47 | 2661 | for_each_possible_cpu(cpu) { |
6aa8b732 | 2662 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
2663 | per_cpu(vmxarea, cpu) = NULL; |
2664 | } | |
6aa8b732 AK |
2665 | } |
2666 | ||
6aa8b732 AK |
2667 | static __init int alloc_kvm_area(void) |
2668 | { | |
2669 | int cpu; | |
2670 | ||
3230bb47 | 2671 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
2672 | struct vmcs *vmcs; |
2673 | ||
41836839 | 2674 | vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); |
6aa8b732 AK |
2675 | if (!vmcs) { |
2676 | free_kvm_area(); | |
2677 | return -ENOMEM; | |
2678 | } | |
2679 | ||
2307af1c LA |
2680 | /* |
2681 | * When eVMCS is enabled, alloc_vmcs_cpu() sets | |
2682 | * vmcs->revision_id to KVM_EVMCS_VERSION instead of | |
2683 | * revision_id reported by MSR_IA32_VMX_BASIC. | |
2684 | * | |
312a4661 | 2685 | * However, even though not explicitly documented by |
2307af1c LA |
2686 | * TLFS, VMXArea passed as VMXON argument should |
2687 | * still be marked with revision_id reported by | |
2688 | * physical CPU. | |
2689 | */ | |
2690 | if (static_branch_unlikely(&enable_evmcs)) | |
392b2f25 | 2691 | vmcs->hdr.revision_id = vmcs_config.revision_id; |
2307af1c | 2692 | |
6aa8b732 AK |
2693 | per_cpu(vmxarea, cpu) = vmcs; |
2694 | } | |
2695 | return 0; | |
2696 | } | |
2697 | ||
91b0aa2c | 2698 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 2699 | struct kvm_segment *save) |
6aa8b732 | 2700 | { |
d99e4152 GN |
2701 | if (!emulate_invalid_guest_state) { |
2702 | /* | |
2703 | * CS and SS RPL should be equal during guest entry according | |
2704 | * to VMX spec, but in reality it is not always so. Since vcpu | |
2705 | * is in the middle of the transition from real mode to | |
2706 | * protected mode it is safe to assume that RPL 0 is a good | |
2707 | * default value. | |
2708 | */ | |
2709 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
2710 | save->selector &= ~SEGMENT_RPL_MASK; |
2711 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 2712 | save->s = 1; |
6aa8b732 | 2713 | } |
d99e4152 | 2714 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
2715 | } |
2716 | ||
2717 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
2718 | { | |
2719 | unsigned long flags; | |
a89a8fb9 | 2720 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 2721 | |
d99e4152 GN |
2722 | /* |
2723 | * Update real mode segment cache. It may be not up-to-date if sement | |
2724 | * register was written while vcpu was in a guest mode. | |
2725 | */ | |
2726 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
2727 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
2728 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
2729 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
2730 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
2731 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
2732 | ||
7ffd92c5 | 2733 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 2734 | |
f5f7b2fe | 2735 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
2736 | |
2737 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
2738 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
2739 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
2740 | vmcs_writel(GUEST_RFLAGS, flags); |
2741 | ||
66aee91a RR |
2742 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
2743 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
2744 | |
2745 | update_exception_bitmap(vcpu); | |
2746 | ||
91b0aa2c GN |
2747 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
2748 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
2749 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
2750 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
2751 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
2752 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
2753 | } |
2754 | ||
f5f7b2fe | 2755 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 2756 | { |
772e0318 | 2757 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
2758 | struct kvm_segment var = *save; |
2759 | ||
2760 | var.dpl = 0x3; | |
2761 | if (seg == VCPU_SREG_CS) | |
2762 | var.type = 0x3; | |
2763 | ||
2764 | if (!emulate_invalid_guest_state) { | |
2765 | var.selector = var.base >> 4; | |
2766 | var.base = var.base & 0xffff0; | |
2767 | var.limit = 0xffff; | |
2768 | var.g = 0; | |
2769 | var.db = 0; | |
2770 | var.present = 1; | |
2771 | var.s = 1; | |
2772 | var.l = 0; | |
2773 | var.unusable = 0; | |
2774 | var.type = 0x3; | |
2775 | var.avl = 0; | |
2776 | if (save->base & 0xf) | |
2777 | printk_once(KERN_WARNING "kvm: segment base is not " | |
2778 | "paragraph aligned when entering " | |
2779 | "protected mode (seg=%d)", seg); | |
2780 | } | |
6aa8b732 | 2781 | |
d99e4152 | 2782 | vmcs_write16(sf->selector, var.selector); |
96794e4e | 2783 | vmcs_writel(sf->base, var.base); |
d99e4152 GN |
2784 | vmcs_write32(sf->limit, var.limit); |
2785 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
2786 | } |
2787 | ||
2788 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
2789 | { | |
2790 | unsigned long flags; | |
a89a8fb9 | 2791 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
40bbb9d0 | 2792 | struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); |
6aa8b732 | 2793 | |
f5f7b2fe AK |
2794 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
2795 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
2796 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
2797 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
2798 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
2799 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
2800 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 2801 | |
7ffd92c5 | 2802 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 2803 | |
776e58ea GN |
2804 | /* |
2805 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 2806 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 2807 | */ |
40bbb9d0 | 2808 | if (!kvm_vmx->tss_addr) |
776e58ea GN |
2809 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
2810 | "called before entering vcpu\n"); | |
776e58ea | 2811 | |
2fb92db1 AK |
2812 | vmx_segment_cache_clear(vmx); |
2813 | ||
40bbb9d0 | 2814 | vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); |
6aa8b732 | 2815 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
2816 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
2817 | ||
2818 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 2819 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 2820 | |
053de044 | 2821 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
2822 | |
2823 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 2824 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
2825 | update_exception_bitmap(vcpu); |
2826 | ||
d99e4152 GN |
2827 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
2828 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
2829 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
2830 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
2831 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
2832 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 2833 | |
8668a3c4 | 2834 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
2835 | } |
2836 | ||
72f211ec | 2837 | int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
401d10de AS |
2838 | { |
2839 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
d85a8034 | 2840 | struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER); |
26bb0981 | 2841 | |
72f211ec | 2842 | /* Nothing to do if hardware doesn't support EFER. */ |
26bb0981 | 2843 | if (!msr) |
72f211ec | 2844 | return 0; |
401d10de | 2845 | |
f6801dff | 2846 | vcpu->arch.efer = efer; |
401d10de | 2847 | if (efer & EFER_LMA) { |
2961e876 | 2848 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
2849 | msr->data = efer; |
2850 | } else { | |
2961e876 | 2851 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
2852 | |
2853 | msr->data = efer & ~EFER_LME; | |
2854 | } | |
2855 | setup_msrs(vmx); | |
72f211ec | 2856 | return 0; |
401d10de AS |
2857 | } |
2858 | ||
05b3e0c2 | 2859 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2860 | |
2861 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
2862 | { | |
2863 | u32 guest_tr_ar; | |
2864 | ||
2fb92db1 AK |
2865 | vmx_segment_cache_clear(to_vmx(vcpu)); |
2866 | ||
6aa8b732 | 2867 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 2868 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
2869 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
2870 | __func__); | |
6aa8b732 | 2871 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
2872 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
2873 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 2874 | } |
da38f438 | 2875 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
2876 | } |
2877 | ||
2878 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
2879 | { | |
2961e876 | 2880 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 2881 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
2882 | } |
2883 | ||
2884 | #endif | |
2885 | ||
7780938c | 2886 | static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu) |
5058b692 SC |
2887 | { |
2888 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2889 | ||
2890 | /* | |
7780938c SC |
2891 | * INVEPT must be issued when EPT is enabled, irrespective of VPID, as |
2892 | * the CPU is not required to invalidate guest-physical mappings on | |
2893 | * VM-Entry, even if VPID is disabled. Guest-physical mappings are | |
2894 | * associated with the root EPT structure and not any particular VPID | |
2895 | * (INVVPID also isn't required to invalidate guest-physical mappings). | |
5058b692 SC |
2896 | */ |
2897 | if (enable_ept) { | |
2898 | ept_sync_global(); | |
2899 | } else if (enable_vpid) { | |
2900 | if (cpu_has_vmx_invvpid_global()) { | |
2901 | vpid_sync_vcpu_global(); | |
2902 | } else { | |
2903 | vpid_sync_vcpu_single(vmx->vpid); | |
2904 | vpid_sync_vcpu_single(vmx->nested.vpid02); | |
2905 | } | |
2906 | } | |
2907 | } | |
2908 | ||
33d19ec9 SC |
2909 | static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu) |
2910 | { | |
2a40b900 SC |
2911 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
2912 | u64 root_hpa = mmu->root_hpa; | |
33d19ec9 SC |
2913 | |
2914 | /* No flush required if the current context is invalid. */ | |
2915 | if (!VALID_PAGE(root_hpa)) | |
2916 | return; | |
2917 | ||
2918 | if (enable_ept) | |
2a40b900 SC |
2919 | ept_sync_context(construct_eptp(vcpu, root_hpa, |
2920 | mmu->shadow_root_level)); | |
33d19ec9 SC |
2921 | else if (!is_guest_mode(vcpu)) |
2922 | vpid_sync_context(to_vmx(vcpu)->vpid); | |
2923 | else | |
2924 | vpid_sync_context(nested_get_vpid02(vcpu)); | |
2925 | } | |
2926 | ||
faff8758 JS |
2927 | static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) |
2928 | { | |
faff8758 | 2929 | /* |
ad104b5e SC |
2930 | * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in |
2931 | * vmx_flush_tlb_guest() for an explanation of why this is ok. | |
faff8758 | 2932 | */ |
ad104b5e | 2933 | vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr); |
faff8758 JS |
2934 | } |
2935 | ||
e64419d9 SC |
2936 | static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu) |
2937 | { | |
2938 | /* | |
2939 | * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0 | |
2940 | * or a vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit | |
2941 | * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is | |
2942 | * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed), | |
2943 | * i.e. no explicit INVVPID is necessary. | |
2944 | */ | |
2945 | vpid_sync_context(to_vmx(vcpu)->vpid); | |
2946 | } | |
2947 | ||
43fea4e4 | 2948 | void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1439442c | 2949 | { |
d0d538b9 GN |
2950 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
2951 | ||
cb3c1e2f | 2952 | if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) |
6de4f3ad AK |
2953 | return; |
2954 | ||
bf03d4f9 | 2955 | if (is_pae_paging(vcpu)) { |
d0d538b9 GN |
2956 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
2957 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
2958 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
2959 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
2960 | } |
2961 | } | |
2962 | ||
97b7ead3 | 2963 | void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
8f5d549f | 2964 | { |
d0d538b9 GN |
2965 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
2966 | ||
9932b49e SC |
2967 | if (WARN_ON_ONCE(!is_pae_paging(vcpu))) |
2968 | return; | |
2969 | ||
2970 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); | |
2971 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
2972 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
2973 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
6de4f3ad | 2974 | |
cb3c1e2f | 2975 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
8f5d549f AK |
2976 | } |
2977 | ||
1439442c SY |
2978 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, |
2979 | unsigned long cr0, | |
2980 | struct kvm_vcpu *vcpu) | |
2981 | { | |
2183f564 SC |
2982 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2983 | ||
cb3c1e2f | 2984 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) |
34059c25 | 2985 | vmx_cache_reg(vcpu, VCPU_EXREG_CR3); |
1439442c SY |
2986 | if (!(cr0 & X86_CR0_PG)) { |
2987 | /* From paging/starting to nonpaging */ | |
2183f564 SC |
2988 | exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | |
2989 | CPU_BASED_CR3_STORE_EXITING); | |
1439442c | 2990 | vcpu->arch.cr0 = cr0; |
fc78f519 | 2991 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
2992 | } else if (!is_paging(vcpu)) { |
2993 | /* From nonpaging to paging */ | |
2183f564 SC |
2994 | exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | |
2995 | CPU_BASED_CR3_STORE_EXITING); | |
1439442c | 2996 | vcpu->arch.cr0 = cr0; |
fc78f519 | 2997 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 2998 | } |
95eb84a7 SY |
2999 | |
3000 | if (!(cr0 & X86_CR0_WP)) | |
3001 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
3002 | } |
3003 | ||
97b7ead3 | 3004 | void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
6aa8b732 | 3005 | { |
7ffd92c5 | 3006 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
3007 | unsigned long hw_cr0; |
3008 | ||
3de6347b | 3009 | hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); |
bddd82d1 | 3010 | if (is_unrestricted_guest(vcpu)) |
5037878e | 3011 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 3012 | else { |
5037878e | 3013 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 3014 | |
218e763f GN |
3015 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
3016 | enter_pmode(vcpu); | |
6aa8b732 | 3017 | |
218e763f GN |
3018 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
3019 | enter_rmode(vcpu); | |
3020 | } | |
6aa8b732 | 3021 | |
05b3e0c2 | 3022 | #ifdef CONFIG_X86_64 |
f6801dff | 3023 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 3024 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 3025 | enter_lmode(vcpu); |
707d92fa | 3026 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
3027 | exit_lmode(vcpu); |
3028 | } | |
3029 | #endif | |
3030 | ||
bddd82d1 | 3031 | if (enable_ept && !is_unrestricted_guest(vcpu)) |
1439442c SY |
3032 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
3033 | ||
6aa8b732 | 3034 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 3035 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 3036 | vcpu->arch.cr0 = cr0; |
bd31fe49 | 3037 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR0); |
14168786 GN |
3038 | |
3039 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
3040 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
3041 | } |
3042 | ||
d468d94b | 3043 | static int vmx_get_max_tdp_level(void) |
855feb67 | 3044 | { |
d468d94b | 3045 | if (cpu_has_vmx_ept_5levels()) |
855feb67 YZ |
3046 | return 5; |
3047 | return 4; | |
3048 | } | |
3049 | ||
2a40b900 SC |
3050 | u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa, |
3051 | int root_level) | |
1439442c | 3052 | { |
855feb67 YZ |
3053 | u64 eptp = VMX_EPTP_MT_WB; |
3054 | ||
2a40b900 | 3055 | eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; |
1439442c | 3056 | |
995f00a6 PF |
3057 | if (enable_ept_ad_bits && |
3058 | (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) | |
bb97a016 | 3059 | eptp |= VMX_EPTP_AD_ENABLE_BIT; |
1439442c SY |
3060 | eptp |= (root_hpa & PAGE_MASK); |
3061 | ||
3062 | return eptp; | |
3063 | } | |
3064 | ||
2a40b900 SC |
3065 | static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd, |
3066 | int pgd_level) | |
6aa8b732 | 3067 | { |
877ad952 | 3068 | struct kvm *kvm = vcpu->kvm; |
04f11ef4 | 3069 | bool update_guest_cr3 = true; |
1439442c SY |
3070 | unsigned long guest_cr3; |
3071 | u64 eptp; | |
3072 | ||
089d034e | 3073 | if (enable_ept) { |
2a40b900 | 3074 | eptp = construct_eptp(vcpu, pgd, pgd_level); |
1439442c | 3075 | vmcs_write64(EPT_POINTER, eptp); |
877ad952 | 3076 | |
afaf0b2f | 3077 | if (kvm_x86_ops.tlb_remote_flush) { |
877ad952 TL |
3078 | spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); |
3079 | to_vmx(vcpu)->ept_pointer = eptp; | |
3080 | to_kvm_vmx(kvm)->ept_pointers_match | |
3081 | = EPT_POINTERS_CHECK; | |
3082 | spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); | |
3083 | } | |
3084 | ||
df7e0681 | 3085 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
877ad952 | 3086 | guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; |
b17b7436 SC |
3087 | else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
3088 | guest_cr3 = vcpu->arch.cr3; | |
3089 | else /* vmcs01.GUEST_CR3 is already up-to-date. */ | |
3090 | update_guest_cr3 = false; | |
43fea4e4 | 3091 | vmx_ept_load_pdptrs(vcpu); |
be100ef1 SC |
3092 | } else { |
3093 | guest_cr3 = pgd; | |
1439442c SY |
3094 | } |
3095 | ||
04f11ef4 SC |
3096 | if (update_guest_cr3) |
3097 | vmcs_writel(GUEST_CR3, guest_cr3); | |
6aa8b732 AK |
3098 | } |
3099 | ||
c2fe3cd4 SC |
3100 | static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
3101 | { | |
3102 | /* | |
3103 | * We operate under the default treatment of SMM, so VMX cannot be | |
3104 | * enabled under SMM. Note, whether or not VMXE is allowed at all is | |
ee69c92b | 3105 | * handled by kvm_is_valid_cr4(). |
c2fe3cd4 SC |
3106 | */ |
3107 | if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu)) | |
3108 | return false; | |
3109 | ||
3110 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
3111 | return false; | |
3112 | ||
3113 | return true; | |
3114 | } | |
3115 | ||
3116 | void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
6aa8b732 | 3117 | { |
2259c17f | 3118 | unsigned long old_cr4 = vcpu->arch.cr4; |
fe7f895d | 3119 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
085e68ee BS |
3120 | /* |
3121 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
3122 | * is in force while we are in guest mode. Do not let guests control | |
3123 | * this bit, even if host CR4.MCE == 0. | |
3124 | */ | |
5dc1f044 SC |
3125 | unsigned long hw_cr4; |
3126 | ||
3127 | hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); | |
bddd82d1 | 3128 | if (is_unrestricted_guest(vcpu)) |
5dc1f044 | 3129 | hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; |
fe7f895d | 3130 | else if (vmx->rmode.vm86_active) |
5dc1f044 SC |
3131 | hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; |
3132 | else | |
3133 | hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; | |
1439442c | 3134 | |
64f7a115 SC |
3135 | if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { |
3136 | if (cr4 & X86_CR4_UMIP) { | |
fe7f895d | 3137 | secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); |
64f7a115 SC |
3138 | hw_cr4 &= ~X86_CR4_UMIP; |
3139 | } else if (!is_guest_mode(vcpu) || | |
fe7f895d SC |
3140 | !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { |
3141 | secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); | |
3142 | } | |
64f7a115 | 3143 | } |
0367f205 | 3144 | |
ad312c7c | 3145 | vcpu->arch.cr4 = cr4; |
f98c1e77 | 3146 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR4); |
5dc1f044 | 3147 | |
bddd82d1 | 3148 | if (!is_unrestricted_guest(vcpu)) { |
5dc1f044 SC |
3149 | if (enable_ept) { |
3150 | if (!is_paging(vcpu)) { | |
3151 | hw_cr4 &= ~X86_CR4_PAE; | |
3152 | hw_cr4 |= X86_CR4_PSE; | |
3153 | } else if (!(cr4 & X86_CR4_PAE)) { | |
3154 | hw_cr4 &= ~X86_CR4_PAE; | |
3155 | } | |
bc23008b | 3156 | } |
1439442c | 3157 | |
656ec4a4 | 3158 | /* |
ddba2628 HH |
3159 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
3160 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
3161 | * to be manually disabled when guest switches to non-paging | |
3162 | * mode. | |
3163 | * | |
3164 | * If !enable_unrestricted_guest, the CPU is always running | |
3165 | * with CR0.PG=1 and CR4 needs to be modified. | |
3166 | * If enable_unrestricted_guest, the CPU automatically | |
3167 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 3168 | */ |
5dc1f044 SC |
3169 | if (!is_paging(vcpu)) |
3170 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); | |
3171 | } | |
656ec4a4 | 3172 | |
1439442c SY |
3173 | vmcs_writel(CR4_READ_SHADOW, cr4); |
3174 | vmcs_writel(GUEST_CR4, hw_cr4); | |
2259c17f JM |
3175 | |
3176 | if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) | |
3177 | kvm_update_cpuid_runtime(vcpu); | |
6aa8b732 AK |
3178 | } |
3179 | ||
97b7ead3 | 3180 | void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) |
6aa8b732 | 3181 | { |
a9179499 | 3182 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
3183 | u32 ar; |
3184 | ||
c6ad1153 | 3185 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 3186 | *var = vmx->rmode.segs[seg]; |
a9179499 | 3187 | if (seg == VCPU_SREG_TR |
2fb92db1 | 3188 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 3189 | return; |
1390a28b AK |
3190 | var->base = vmx_read_guest_seg_base(vmx, seg); |
3191 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
3192 | return; | |
a9179499 | 3193 | } |
2fb92db1 AK |
3194 | var->base = vmx_read_guest_seg_base(vmx, seg); |
3195 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
3196 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
3197 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 3198 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
3199 | var->type = ar & 15; |
3200 | var->s = (ar >> 4) & 1; | |
3201 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
3202 | /* |
3203 | * Some userspaces do not preserve unusable property. Since usable | |
3204 | * segment has to be present according to VMX spec we can use present | |
3205 | * property to amend userspace bug by making unusable segment always | |
3206 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
3207 | * segment as unusable. | |
3208 | */ | |
3209 | var->present = !var->unusable; | |
6aa8b732 AK |
3210 | var->avl = (ar >> 12) & 1; |
3211 | var->l = (ar >> 13) & 1; | |
3212 | var->db = (ar >> 14) & 1; | |
3213 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
3214 | } |
3215 | ||
a9179499 AK |
3216 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
3217 | { | |
a9179499 AK |
3218 | struct kvm_segment s; |
3219 | ||
3220 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
3221 | vmx_get_segment(vcpu, &s, seg); | |
3222 | return s.base; | |
3223 | } | |
2fb92db1 | 3224 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
3225 | } |
3226 | ||
97b7ead3 | 3227 | int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 3228 | { |
b09408d0 MT |
3229 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3230 | ||
ae9fedc7 | 3231 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 3232 | return 0; |
ae9fedc7 PB |
3233 | else { |
3234 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 3235 | return VMX_AR_DPL(ar); |
69c73028 | 3236 | } |
69c73028 AK |
3237 | } |
3238 | ||
653e3108 | 3239 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 3240 | { |
6aa8b732 AK |
3241 | u32 ar; |
3242 | ||
f0495f9b | 3243 | if (var->unusable || !var->present) |
6aa8b732 AK |
3244 | ar = 1 << 16; |
3245 | else { | |
3246 | ar = var->type & 15; | |
3247 | ar |= (var->s & 1) << 4; | |
3248 | ar |= (var->dpl & 3) << 5; | |
3249 | ar |= (var->present & 1) << 7; | |
3250 | ar |= (var->avl & 1) << 12; | |
3251 | ar |= (var->l & 1) << 13; | |
3252 | ar |= (var->db & 1) << 14; | |
3253 | ar |= (var->g & 1) << 15; | |
3254 | } | |
653e3108 AK |
3255 | |
3256 | return ar; | |
3257 | } | |
3258 | ||
97b7ead3 | 3259 | void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) |
653e3108 | 3260 | { |
7ffd92c5 | 3261 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 3262 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 3263 | |
2fb92db1 AK |
3264 | vmx_segment_cache_clear(vmx); |
3265 | ||
1ecd50a9 GN |
3266 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
3267 | vmx->rmode.segs[seg] = *var; | |
3268 | if (seg == VCPU_SREG_TR) | |
3269 | vmcs_write16(sf->selector, var->selector); | |
3270 | else if (var->s) | |
3271 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 3272 | goto out; |
653e3108 | 3273 | } |
1ecd50a9 | 3274 | |
653e3108 AK |
3275 | vmcs_writel(sf->base, var->base); |
3276 | vmcs_write32(sf->limit, var->limit); | |
3277 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
3278 | |
3279 | /* | |
3280 | * Fix the "Accessed" bit in AR field of segment registers for older | |
3281 | * qemu binaries. | |
3282 | * IA32 arch specifies that at the time of processor reset the | |
3283 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 3284 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
3285 | * state vmexit when "unrestricted guest" mode is turned on. |
3286 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
3287 | * tree. Newer qemu binaries with that qemu fix would not need this | |
3288 | * kvm hack. | |
3289 | */ | |
bddd82d1 | 3290 | if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR)) |
f924d66d | 3291 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 3292 | |
f924d66d | 3293 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
3294 | |
3295 | out: | |
98eb2f8b | 3296 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
3297 | } |
3298 | ||
6aa8b732 AK |
3299 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
3300 | { | |
2fb92db1 | 3301 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
3302 | |
3303 | *db = (ar >> 14) & 1; | |
3304 | *l = (ar >> 13) & 1; | |
3305 | } | |
3306 | ||
89a27f4d | 3307 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3308 | { |
89a27f4d GN |
3309 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
3310 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
3311 | } |
3312 | ||
89a27f4d | 3313 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3314 | { |
89a27f4d GN |
3315 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
3316 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
3317 | } |
3318 | ||
89a27f4d | 3319 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3320 | { |
89a27f4d GN |
3321 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
3322 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
3323 | } |
3324 | ||
89a27f4d | 3325 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3326 | { |
89a27f4d GN |
3327 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
3328 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
3329 | } |
3330 | ||
648dfaa7 MG |
3331 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
3332 | { | |
3333 | struct kvm_segment var; | |
3334 | u32 ar; | |
3335 | ||
3336 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 3337 | var.dpl = 0x3; |
0647f4aa GN |
3338 | if (seg == VCPU_SREG_CS) |
3339 | var.type = 0x3; | |
648dfaa7 MG |
3340 | ar = vmx_segment_access_rights(&var); |
3341 | ||
3342 | if (var.base != (var.selector << 4)) | |
3343 | return false; | |
89efbed0 | 3344 | if (var.limit != 0xffff) |
648dfaa7 | 3345 | return false; |
07f42f5f | 3346 | if (ar != 0xf3) |
648dfaa7 MG |
3347 | return false; |
3348 | ||
3349 | return true; | |
3350 | } | |
3351 | ||
3352 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
3353 | { | |
3354 | struct kvm_segment cs; | |
3355 | unsigned int cs_rpl; | |
3356 | ||
3357 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 3358 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 3359 | |
1872a3f4 AK |
3360 | if (cs.unusable) |
3361 | return false; | |
4d283ec9 | 3362 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
3363 | return false; |
3364 | if (!cs.s) | |
3365 | return false; | |
4d283ec9 | 3366 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
3367 | if (cs.dpl > cs_rpl) |
3368 | return false; | |
1872a3f4 | 3369 | } else { |
648dfaa7 MG |
3370 | if (cs.dpl != cs_rpl) |
3371 | return false; | |
3372 | } | |
3373 | if (!cs.present) | |
3374 | return false; | |
3375 | ||
3376 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
3377 | return true; | |
3378 | } | |
3379 | ||
3380 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
3381 | { | |
3382 | struct kvm_segment ss; | |
3383 | unsigned int ss_rpl; | |
3384 | ||
3385 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 3386 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 3387 | |
1872a3f4 AK |
3388 | if (ss.unusable) |
3389 | return true; | |
3390 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
3391 | return false; |
3392 | if (!ss.s) | |
3393 | return false; | |
3394 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
3395 | return false; | |
3396 | if (!ss.present) | |
3397 | return false; | |
3398 | ||
3399 | return true; | |
3400 | } | |
3401 | ||
3402 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
3403 | { | |
3404 | struct kvm_segment var; | |
3405 | unsigned int rpl; | |
3406 | ||
3407 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 3408 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 3409 | |
1872a3f4 AK |
3410 | if (var.unusable) |
3411 | return true; | |
648dfaa7 MG |
3412 | if (!var.s) |
3413 | return false; | |
3414 | if (!var.present) | |
3415 | return false; | |
4d283ec9 | 3416 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
3417 | if (var.dpl < rpl) /* DPL < RPL */ |
3418 | return false; | |
3419 | } | |
3420 | ||
3421 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
3422 | * rights flags | |
3423 | */ | |
3424 | return true; | |
3425 | } | |
3426 | ||
3427 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
3428 | { | |
3429 | struct kvm_segment tr; | |
3430 | ||
3431 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
3432 | ||
1872a3f4 AK |
3433 | if (tr.unusable) |
3434 | return false; | |
b32a9918 | 3435 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 3436 | return false; |
1872a3f4 | 3437 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
3438 | return false; |
3439 | if (!tr.present) | |
3440 | return false; | |
3441 | ||
3442 | return true; | |
3443 | } | |
3444 | ||
3445 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
3446 | { | |
3447 | struct kvm_segment ldtr; | |
3448 | ||
3449 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
3450 | ||
1872a3f4 AK |
3451 | if (ldtr.unusable) |
3452 | return true; | |
b32a9918 | 3453 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
3454 | return false; |
3455 | if (ldtr.type != 2) | |
3456 | return false; | |
3457 | if (!ldtr.present) | |
3458 | return false; | |
3459 | ||
3460 | return true; | |
3461 | } | |
3462 | ||
3463 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
3464 | { | |
3465 | struct kvm_segment cs, ss; | |
3466 | ||
3467 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
3468 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
3469 | ||
b32a9918 NA |
3470 | return ((cs.selector & SEGMENT_RPL_MASK) == |
3471 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
3472 | } |
3473 | ||
3474 | /* | |
3475 | * Check if guest state is valid. Returns true if valid, false if | |
3476 | * not. | |
3477 | * We assume that registers are always usable | |
3478 | */ | |
2ba4493a | 3479 | bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu) |
648dfaa7 MG |
3480 | { |
3481 | /* real mode guest state checks */ | |
f13882d8 | 3482 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
3483 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
3484 | return false; | |
3485 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
3486 | return false; | |
3487 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
3488 | return false; | |
3489 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
3490 | return false; | |
3491 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
3492 | return false; | |
3493 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
3494 | return false; | |
3495 | } else { | |
3496 | /* protected mode guest state checks */ | |
3497 | if (!cs_ss_rpl_check(vcpu)) | |
3498 | return false; | |
3499 | if (!code_segment_valid(vcpu)) | |
3500 | return false; | |
3501 | if (!stack_segment_valid(vcpu)) | |
3502 | return false; | |
3503 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
3504 | return false; | |
3505 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
3506 | return false; | |
3507 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
3508 | return false; | |
3509 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
3510 | return false; | |
3511 | if (!tr_valid(vcpu)) | |
3512 | return false; | |
3513 | if (!ldtr_valid(vcpu)) | |
3514 | return false; | |
3515 | } | |
3516 | /* TODO: | |
3517 | * - Add checks on RIP | |
3518 | * - Add checks on RFLAGS | |
3519 | */ | |
3520 | ||
3521 | return true; | |
3522 | } | |
3523 | ||
ff5a983c | 3524 | static int init_rmode_tss(struct kvm *kvm, void __user *ua) |
6aa8b732 | 3525 | { |
ff5a983c PX |
3526 | const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0))); |
3527 | u16 data; | |
3528 | int i; | |
3529 | ||
3530 | for (i = 0; i < 3; i++) { | |
3531 | if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE)) | |
3532 | return -EFAULT; | |
3533 | } | |
6aa8b732 | 3534 | |
195aefde | 3535 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
ff5a983c PX |
3536 | if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16))) |
3537 | return -EFAULT; | |
3538 | ||
195aefde | 3539 | data = ~0; |
ff5a983c PX |
3540 | if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8))) |
3541 | return -EFAULT; | |
3542 | ||
3543 | return 0; | |
6aa8b732 AK |
3544 | } |
3545 | ||
b7ebfb05 SY |
3546 | static int init_rmode_identity_map(struct kvm *kvm) |
3547 | { | |
40bbb9d0 | 3548 | struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); |
2a5755bb | 3549 | int i, r = 0; |
ff5a983c | 3550 | void __user *uaddr; |
b7ebfb05 SY |
3551 | u32 tmp; |
3552 | ||
40bbb9d0 | 3553 | /* Protect kvm_vmx->ept_identity_pagetable_done. */ |
a255d479 TC |
3554 | mutex_lock(&kvm->slots_lock); |
3555 | ||
40bbb9d0 | 3556 | if (likely(kvm_vmx->ept_identity_pagetable_done)) |
2a5755bb | 3557 | goto out; |
a255d479 | 3558 | |
40bbb9d0 SC |
3559 | if (!kvm_vmx->ept_identity_map_addr) |
3560 | kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
a255d479 | 3561 | |
ff5a983c PX |
3562 | uaddr = __x86_set_memory_region(kvm, |
3563 | IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
3564 | kvm_vmx->ept_identity_map_addr, | |
3565 | PAGE_SIZE); | |
3566 | if (IS_ERR(uaddr)) { | |
3567 | r = PTR_ERR(uaddr); | |
2a5755bb | 3568 | goto out; |
ff5a983c | 3569 | } |
a255d479 | 3570 | |
b7ebfb05 SY |
3571 | /* Set up identity-mapping pagetable for EPT in real mode */ |
3572 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
3573 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
3574 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
ff5a983c PX |
3575 | if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) { |
3576 | r = -EFAULT; | |
b7ebfb05 | 3577 | goto out; |
ff5a983c | 3578 | } |
b7ebfb05 | 3579 | } |
40bbb9d0 | 3580 | kvm_vmx->ept_identity_pagetable_done = true; |
f51770ed | 3581 | |
b7ebfb05 | 3582 | out: |
a255d479 | 3583 | mutex_unlock(&kvm->slots_lock); |
f51770ed | 3584 | return r; |
b7ebfb05 SY |
3585 | } |
3586 | ||
6aa8b732 AK |
3587 | static void seg_setup(int seg) |
3588 | { | |
772e0318 | 3589 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 3590 | unsigned int ar; |
6aa8b732 AK |
3591 | |
3592 | vmcs_write16(sf->selector, 0); | |
3593 | vmcs_writel(sf->base, 0); | |
3594 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
3595 | ar = 0x93; |
3596 | if (seg == VCPU_SREG_CS) | |
3597 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
3598 | |
3599 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
3600 | } |
3601 | ||
f78e0e2e SY |
3602 | static int alloc_apic_access_page(struct kvm *kvm) |
3603 | { | |
4484141a | 3604 | struct page *page; |
ff5a983c PX |
3605 | void __user *hva; |
3606 | int ret = 0; | |
f78e0e2e | 3607 | |
79fac95e | 3608 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 3609 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 3610 | goto out; |
ff5a983c PX |
3611 | hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
3612 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
3613 | if (IS_ERR(hva)) { | |
3614 | ret = PTR_ERR(hva); | |
f78e0e2e | 3615 | goto out; |
ff5a983c | 3616 | } |
72dc67a6 | 3617 | |
73a6d941 | 3618 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a | 3619 | if (is_error_page(page)) { |
ff5a983c | 3620 | ret = -EFAULT; |
4484141a XG |
3621 | goto out; |
3622 | } | |
3623 | ||
c24ae0dc TC |
3624 | /* |
3625 | * Do not pin the page in memory, so that memory hot-unplug | |
3626 | * is able to migrate it. | |
3627 | */ | |
3628 | put_page(page); | |
3629 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 3630 | out: |
79fac95e | 3631 | mutex_unlock(&kvm->slots_lock); |
ff5a983c | 3632 | return ret; |
f78e0e2e SY |
3633 | } |
3634 | ||
97b7ead3 | 3635 | int allocate_vpid(void) |
2384d2b3 SY |
3636 | { |
3637 | int vpid; | |
3638 | ||
919818ab | 3639 | if (!enable_vpid) |
991e7a0e | 3640 | return 0; |
2384d2b3 SY |
3641 | spin_lock(&vmx_vpid_lock); |
3642 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 3643 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 3644 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
3645 | else |
3646 | vpid = 0; | |
2384d2b3 | 3647 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 3648 | return vpid; |
2384d2b3 SY |
3649 | } |
3650 | ||
97b7ead3 | 3651 | void free_vpid(int vpid) |
cdbecfc3 | 3652 | { |
991e7a0e | 3653 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
3654 | return; |
3655 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 3656 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
3657 | spin_unlock(&vmx_vpid_lock); |
3658 | } | |
3659 | ||
3eb90017 AG |
3660 | static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr) |
3661 | { | |
3662 | int f = sizeof(unsigned long); | |
3663 | ||
3664 | if (msr <= 0x1fff) | |
3665 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
3666 | else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) | |
3667 | __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f); | |
3668 | } | |
3669 | ||
3670 | static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr) | |
3671 | { | |
3672 | int f = sizeof(unsigned long); | |
3673 | ||
3674 | if (msr <= 0x1fff) | |
3675 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
3676 | else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) | |
3677 | __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f); | |
3678 | } | |
3679 | ||
3680 | static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr) | |
25c5f225 | 3681 | { |
3e7c73e9 | 3682 | int f = sizeof(unsigned long); |
25c5f225 | 3683 | |
3eb90017 AG |
3684 | if (msr <= 0x1fff) |
3685 | __set_bit(msr, msr_bitmap + 0x000 / f); | |
3686 | else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) | |
3687 | __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f); | |
3688 | } | |
3689 | ||
3690 | static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr) | |
3691 | { | |
3692 | int f = sizeof(unsigned long); | |
3693 | ||
3694 | if (msr <= 0x1fff) | |
3695 | __set_bit(msr, msr_bitmap + 0x800 / f); | |
3696 | else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) | |
3697 | __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f); | |
3698 | } | |
3699 | ||
476c9bd8 | 3700 | static __always_inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, |
904e14fb | 3701 | u32 msr, int type) |
25c5f225 | 3702 | { |
476c9bd8 AL |
3703 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3704 | unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; | |
25c5f225 SY |
3705 | |
3706 | if (!cpu_has_vmx_msr_bitmap()) | |
3707 | return; | |
3708 | ||
ceef7d10 VK |
3709 | if (static_branch_unlikely(&enable_evmcs)) |
3710 | evmcs_touch_msr_bitmap(); | |
3711 | ||
25c5f225 | 3712 | /* |
3eb90017 AG |
3713 | * Mark the desired intercept state in shadow bitmap, this is needed |
3714 | * for resync when the MSR filters change. | |
3715 | */ | |
3716 | if (is_valid_passthrough_msr(msr)) { | |
3717 | int idx = possible_passthrough_msr_slot(msr); | |
3718 | ||
3719 | if (idx != -ENOENT) { | |
3720 | if (type & MSR_TYPE_R) | |
3721 | clear_bit(idx, vmx->shadow_msr_intercept.read); | |
3722 | if (type & MSR_TYPE_W) | |
3723 | clear_bit(idx, vmx->shadow_msr_intercept.write); | |
3724 | } | |
3725 | } | |
8d14695f | 3726 | |
3eb90017 AG |
3727 | if ((type & MSR_TYPE_R) && |
3728 | !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) { | |
3729 | vmx_set_msr_bitmap_read(msr_bitmap, msr); | |
3730 | type &= ~MSR_TYPE_R; | |
3731 | } | |
8d14695f | 3732 | |
3eb90017 AG |
3733 | if ((type & MSR_TYPE_W) && |
3734 | !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) { | |
3735 | vmx_set_msr_bitmap_write(msr_bitmap, msr); | |
3736 | type &= ~MSR_TYPE_W; | |
3737 | } | |
8d14695f | 3738 | |
3eb90017 AG |
3739 | if (type & MSR_TYPE_R) |
3740 | vmx_clear_msr_bitmap_read(msr_bitmap, msr); | |
8d14695f | 3741 | |
3eb90017 AG |
3742 | if (type & MSR_TYPE_W) |
3743 | vmx_clear_msr_bitmap_write(msr_bitmap, msr); | |
8d14695f YZ |
3744 | } |
3745 | ||
476c9bd8 | 3746 | static __always_inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, |
904e14fb PB |
3747 | u32 msr, int type) |
3748 | { | |
476c9bd8 AL |
3749 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3750 | unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; | |
904e14fb PB |
3751 | |
3752 | if (!cpu_has_vmx_msr_bitmap()) | |
3753 | return; | |
3754 | ||
ceef7d10 VK |
3755 | if (static_branch_unlikely(&enable_evmcs)) |
3756 | evmcs_touch_msr_bitmap(); | |
3757 | ||
904e14fb | 3758 | /* |
3eb90017 AG |
3759 | * Mark the desired intercept state in shadow bitmap, this is needed |
3760 | * for resync when the MSR filter changes. | |
3761 | */ | |
3762 | if (is_valid_passthrough_msr(msr)) { | |
3763 | int idx = possible_passthrough_msr_slot(msr); | |
3764 | ||
3765 | if (idx != -ENOENT) { | |
3766 | if (type & MSR_TYPE_R) | |
3767 | set_bit(idx, vmx->shadow_msr_intercept.read); | |
3768 | if (type & MSR_TYPE_W) | |
3769 | set_bit(idx, vmx->shadow_msr_intercept.write); | |
3770 | } | |
3771 | } | |
904e14fb | 3772 | |
3eb90017 AG |
3773 | if (type & MSR_TYPE_R) |
3774 | vmx_set_msr_bitmap_read(msr_bitmap, msr); | |
904e14fb | 3775 | |
3eb90017 AG |
3776 | if (type & MSR_TYPE_W) |
3777 | vmx_set_msr_bitmap_write(msr_bitmap, msr); | |
904e14fb PB |
3778 | } |
3779 | ||
476c9bd8 AL |
3780 | static __always_inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, |
3781 | u32 msr, int type, bool value) | |
904e14fb PB |
3782 | { |
3783 | if (value) | |
476c9bd8 | 3784 | vmx_enable_intercept_for_msr(vcpu, msr, type); |
904e14fb | 3785 | else |
476c9bd8 | 3786 | vmx_disable_intercept_for_msr(vcpu, msr, type); |
904e14fb PB |
3787 | } |
3788 | ||
904e14fb | 3789 | static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) |
5897297b | 3790 | { |
904e14fb PB |
3791 | u8 mode = 0; |
3792 | ||
3793 | if (cpu_has_secondary_exec_ctrls() && | |
fe7f895d | 3794 | (secondary_exec_controls_get(to_vmx(vcpu)) & |
904e14fb PB |
3795 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { |
3796 | mode |= MSR_BITMAP_MODE_X2APIC; | |
3797 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) | |
3798 | mode |= MSR_BITMAP_MODE_X2APIC_APICV; | |
3799 | } | |
3800 | ||
904e14fb | 3801 | return mode; |
8d14695f YZ |
3802 | } |
3803 | ||
9389b9d5 | 3804 | static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode) |
8d14695f | 3805 | { |
9389b9d5 SC |
3806 | unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap; |
3807 | unsigned long read_intercept; | |
904e14fb PB |
3808 | int msr; |
3809 | ||
9389b9d5 SC |
3810 | read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; |
3811 | ||
904e14fb | 3812 | for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { |
9389b9d5 SC |
3813 | unsigned int read_idx = msr / BITS_PER_LONG; |
3814 | unsigned int write_idx = read_idx + (0x800 / sizeof(long)); | |
3eb90017 | 3815 | |
9389b9d5 SC |
3816 | msr_bitmap[read_idx] = read_intercept; |
3817 | msr_bitmap[write_idx] = ~0ul; | |
904e14fb | 3818 | } |
9389b9d5 | 3819 | } |
904e14fb | 3820 | |
9389b9d5 SC |
3821 | static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu, u8 mode) |
3822 | { | |
3823 | if (!cpu_has_vmx_msr_bitmap()) | |
3824 | return; | |
3825 | ||
3826 | vmx_reset_x2apic_msrs(vcpu, mode); | |
3827 | ||
3828 | /* | |
3829 | * TPR reads and writes can be virtualized even if virtual interrupt | |
3830 | * delivery is not in use. | |
3831 | */ | |
3832 | vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW, | |
3833 | !(mode & MSR_BITMAP_MODE_X2APIC)); | |
3834 | ||
3835 | if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { | |
3836 | vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW); | |
3837 | vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); | |
3838 | vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); | |
f6e90f9e | 3839 | } |
5897297b AK |
3840 | } |
3841 | ||
97b7ead3 | 3842 | void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) |
904e14fb PB |
3843 | { |
3844 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
904e14fb PB |
3845 | u8 mode = vmx_msr_bitmap_mode(vcpu); |
3846 | u8 changed = mode ^ vmx->msr_bitmap_mode; | |
3847 | ||
3848 | if (!changed) | |
3849 | return; | |
3850 | ||
904e14fb | 3851 | if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) |
3eb90017 | 3852 | vmx_update_msr_bitmap_x2apic(vcpu, mode); |
904e14fb PB |
3853 | |
3854 | vmx->msr_bitmap_mode = mode; | |
3855 | } | |
3856 | ||
476c9bd8 | 3857 | void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu) |
b08c2896 | 3858 | { |
476c9bd8 | 3859 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b08c2896 CP |
3860 | bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); |
3861 | u32 i; | |
3862 | ||
476c9bd8 AL |
3863 | vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag); |
3864 | vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag); | |
3865 | vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag); | |
3866 | vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag); | |
b08c2896 | 3867 | for (i = 0; i < vmx->pt_desc.addr_range; i++) { |
476c9bd8 AL |
3868 | vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); |
3869 | vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); | |
b08c2896 CP |
3870 | } |
3871 | } | |
3872 | ||
e6c67d8c LA |
3873 | static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
3874 | { | |
3875 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3876 | void *vapic_page; | |
3877 | u32 vppr; | |
3878 | int rvi; | |
3879 | ||
3880 | if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || | |
3881 | !nested_cpu_has_vid(get_vmcs12(vcpu)) || | |
96c66e87 | 3882 | WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) |
e6c67d8c LA |
3883 | return false; |
3884 | ||
7e712684 | 3885 | rvi = vmx_get_rvi(); |
e6c67d8c | 3886 | |
96c66e87 | 3887 | vapic_page = vmx->nested.virtual_apic_map.hva; |
e6c67d8c | 3888 | vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); |
e6c67d8c LA |
3889 | |
3890 | return ((rvi & 0xf0) > (vppr & 0xf0)); | |
3891 | } | |
3892 | ||
3eb90017 AG |
3893 | static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu) |
3894 | { | |
3895 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3896 | u32 i; | |
3897 | ||
3898 | /* | |
3899 | * Set intercept permissions for all potentially passed through MSRs | |
3900 | * again. They will automatically get filtered through the MSR filter, | |
3901 | * so we are back in sync after this. | |
3902 | */ | |
3903 | for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) { | |
3904 | u32 msr = vmx_possible_passthrough_msrs[i]; | |
3905 | bool read = test_bit(i, vmx->shadow_msr_intercept.read); | |
3906 | bool write = test_bit(i, vmx->shadow_msr_intercept.write); | |
3907 | ||
3908 | vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read); | |
3909 | vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write); | |
3910 | } | |
3911 | ||
3912 | pt_update_intercept_for_msr(vcpu); | |
3913 | vmx_update_msr_bitmap_x2apic(vcpu, vmx_msr_bitmap_mode(vcpu)); | |
3914 | } | |
3915 | ||
06a5524f WV |
3916 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, |
3917 | bool nested) | |
21bc8dc5 RK |
3918 | { |
3919 | #ifdef CONFIG_SMP | |
06a5524f WV |
3920 | int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; |
3921 | ||
21bc8dc5 | 3922 | if (vcpu->mode == IN_GUEST_MODE) { |
28b835d6 | 3923 | /* |
5753743f HZ |
3924 | * The vector of interrupt to be delivered to vcpu had |
3925 | * been set in PIR before this function. | |
3926 | * | |
3927 | * Following cases will be reached in this block, and | |
3928 | * we always send a notification event in all cases as | |
3929 | * explained below. | |
3930 | * | |
3931 | * Case 1: vcpu keeps in non-root mode. Sending a | |
3932 | * notification event posts the interrupt to vcpu. | |
3933 | * | |
3934 | * Case 2: vcpu exits to root mode and is still | |
3935 | * runnable. PIR will be synced to vIRR before the | |
3936 | * next vcpu entry. Sending a notification event in | |
3937 | * this case has no effect, as vcpu is not in root | |
3938 | * mode. | |
28b835d6 | 3939 | * |
5753743f HZ |
3940 | * Case 3: vcpu exits to root mode and is blocked. |
3941 | * vcpu_block() has already synced PIR to vIRR and | |
3942 | * never blocks vcpu if vIRR is not cleared. Therefore, | |
3943 | * a blocked vcpu here does not wait for any requested | |
3944 | * interrupts in PIR, and sending a notification event | |
3945 | * which has no effect is safe here. | |
28b835d6 | 3946 | */ |
28b835d6 | 3947 | |
06a5524f | 3948 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); |
21bc8dc5 RK |
3949 | return true; |
3950 | } | |
3951 | #endif | |
3952 | return false; | |
3953 | } | |
3954 | ||
705699a1 WV |
3955 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
3956 | int vector) | |
3957 | { | |
3958 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3959 | ||
3960 | if (is_guest_mode(vcpu) && | |
3961 | vector == vmx->nested.posted_intr_nv) { | |
705699a1 WV |
3962 | /* |
3963 | * If a posted intr is not recognized by hardware, | |
3964 | * we will accomplish it in the next vmentry. | |
3965 | */ | |
3966 | vmx->nested.pi_pending = true; | |
3967 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6b697711 LA |
3968 | /* the PIR and ON have been set by L1. */ |
3969 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) | |
3970 | kvm_vcpu_kick(vcpu); | |
705699a1 WV |
3971 | return 0; |
3972 | } | |
3973 | return -1; | |
3974 | } | |
a20ed54d YZ |
3975 | /* |
3976 | * Send interrupt to vcpu via posted interrupt way. | |
3977 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
3978 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
3979 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
3980 | * interrupt from PIR in next vmentry. | |
3981 | */ | |
91a5f413 | 3982 | static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) |
a20ed54d YZ |
3983 | { |
3984 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3985 | int r; | |
3986 | ||
705699a1 WV |
3987 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
3988 | if (!r) | |
91a5f413 VK |
3989 | return 0; |
3990 | ||
3991 | if (!vcpu->arch.apicv_active) | |
3992 | return -1; | |
705699a1 | 3993 | |
a20ed54d | 3994 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
91a5f413 | 3995 | return 0; |
a20ed54d | 3996 | |
b95234c8 PB |
3997 | /* If a previous notification has sent the IPI, nothing to do. */ |
3998 | if (pi_test_and_set_on(&vmx->pi_desc)) | |
91a5f413 | 3999 | return 0; |
b95234c8 | 4000 | |
379a3c8e WL |
4001 | if (vcpu != kvm_get_running_vcpu() && |
4002 | !kvm_vcpu_trigger_posted_interrupt(vcpu, false)) | |
a20ed54d | 4003 | kvm_vcpu_kick(vcpu); |
91a5f413 VK |
4004 | |
4005 | return 0; | |
a20ed54d YZ |
4006 | } |
4007 | ||
a3a8ff8e NHE |
4008 | /* |
4009 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
4010 | * will not change in the lifetime of the guest. | |
4011 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
4012 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
4013 | */ | |
97b7ead3 | 4014 | void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
4015 | { |
4016 | u32 low32, high32; | |
4017 | unsigned long tmpl; | |
d6e41f11 | 4018 | unsigned long cr0, cr3, cr4; |
a3a8ff8e | 4019 | |
04ac88ab AL |
4020 | cr0 = read_cr0(); |
4021 | WARN_ON(cr0 & X86_CR0_TS); | |
4022 | vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ | |
d6e41f11 AL |
4023 | |
4024 | /* | |
4025 | * Save the most likely value for this task's CR3 in the VMCS. | |
4026 | * We can't use __get_current_cr3_fast() because we're not atomic. | |
4027 | */ | |
6c690ee1 | 4028 | cr3 = __read_cr3(); |
d6e41f11 | 4029 | vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ |
d7ee039e | 4030 | vmx->loaded_vmcs->host_state.cr3 = cr3; |
a3a8ff8e | 4031 | |
d974baa3 | 4032 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 4033 | cr4 = cr4_read_shadow(); |
d974baa3 | 4034 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
d7ee039e | 4035 | vmx->loaded_vmcs->host_state.cr4 = cr4; |
d974baa3 | 4036 | |
a3a8ff8e | 4037 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
4038 | #ifdef CONFIG_X86_64 |
4039 | /* | |
4040 | * Load null selectors, so we can avoid reloading them in | |
6d6095bd SC |
4041 | * vmx_prepare_switch_to_host(), in case userspace uses |
4042 | * the null selectors too (the expected case). | |
b2da15ac AK |
4043 | */ |
4044 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
4045 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
4046 | #else | |
a3a8ff8e NHE |
4047 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4048 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 4049 | #endif |
a3a8ff8e NHE |
4050 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4051 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
4052 | ||
2342080c | 4053 | vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ |
a3a8ff8e | 4054 | |
453eafbe | 4055 | vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ |
a3a8ff8e NHE |
4056 | |
4057 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
4058 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
4059 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
4060 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
4061 | ||
4062 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
4063 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
4064 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
4065 | } | |
5a5e8a15 | 4066 | |
c73da3fc | 4067 | if (cpu_has_load_ia32_efer()) |
5a5e8a15 | 4068 | vmcs_write64(HOST_IA32_EFER, host_efer); |
a3a8ff8e NHE |
4069 | } |
4070 | ||
97b7ead3 | 4071 | void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
bf8179a0 | 4072 | { |
2ed41aa6 SC |
4073 | struct kvm_vcpu *vcpu = &vmx->vcpu; |
4074 | ||
4075 | vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS & | |
4076 | ~vcpu->arch.cr4_guest_rsvd_bits; | |
fa71e952 | 4077 | if (!enable_ept) |
2ed41aa6 | 4078 | vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE; |
fe3ef05c | 4079 | if (is_guest_mode(&vmx->vcpu)) |
2ed41aa6 SC |
4080 | vcpu->arch.cr4_guest_owned_bits &= |
4081 | ~get_vmcs12(vcpu)->cr4_guest_host_mask; | |
4082 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits); | |
bf8179a0 NHE |
4083 | } |
4084 | ||
c075c3e4 | 4085 | u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
01e439be YZ |
4086 | { |
4087 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
4088 | ||
d62caabb | 4089 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 4090 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
d02fcf50 PB |
4091 | |
4092 | if (!enable_vnmi) | |
4093 | pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; | |
4094 | ||
804939ea SC |
4095 | if (!enable_preemption_timer) |
4096 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
4097 | ||
01e439be YZ |
4098 | return pin_based_exec_ctrl; |
4099 | } | |
4100 | ||
d62caabb AS |
4101 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
4102 | { | |
4103 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4104 | ||
c5f2c766 | 4105 | pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); |
3ce424e4 RK |
4106 | if (cpu_has_secondary_exec_ctrls()) { |
4107 | if (kvm_vcpu_apicv_active(vcpu)) | |
fe7f895d | 4108 | secondary_exec_controls_setbit(vmx, |
3ce424e4 RK |
4109 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
4110 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
4111 | else | |
fe7f895d | 4112 | secondary_exec_controls_clearbit(vmx, |
3ce424e4 RK |
4113 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
4114 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
4115 | } | |
4116 | ||
4117 | if (cpu_has_vmx_msr_bitmap()) | |
904e14fb | 4118 | vmx_update_msr_bitmap(vcpu); |
d62caabb AS |
4119 | } |
4120 | ||
89b0c9f5 SC |
4121 | u32 vmx_exec_control(struct vcpu_vmx *vmx) |
4122 | { | |
4123 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
4124 | ||
4125 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
4126 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
4127 | ||
4128 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { | |
4129 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
4130 | #ifdef CONFIG_X86_64 | |
4131 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
4132 | CPU_BASED_CR8_LOAD_EXITING; | |
4133 | #endif | |
4134 | } | |
4135 | if (!enable_ept) | |
4136 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
4137 | CPU_BASED_CR3_LOAD_EXITING | | |
4138 | CPU_BASED_INVLPG_EXITING; | |
4139 | if (kvm_mwait_in_guest(vmx->vcpu.kvm)) | |
4140 | exec_control &= ~(CPU_BASED_MWAIT_EXITING | | |
4141 | CPU_BASED_MONITOR_EXITING); | |
4142 | if (kvm_hlt_in_guest(vmx->vcpu.kvm)) | |
4143 | exec_control &= ~CPU_BASED_HLT_EXITING; | |
4144 | return exec_control; | |
4145 | } | |
4146 | ||
8b50b92f SC |
4147 | /* |
4148 | * Adjust a single secondary execution control bit to intercept/allow an | |
4149 | * instruction in the guest. This is usually done based on whether or not a | |
4150 | * feature has been exposed to the guest in order to correctly emulate faults. | |
4151 | */ | |
4152 | static inline void | |
4153 | vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control, | |
4154 | u32 control, bool enabled, bool exiting) | |
4155 | { | |
4156 | /* | |
4157 | * If the control is for an opt-in feature, clear the control if the | |
4158 | * feature is not exposed to the guest, i.e. not enabled. If the | |
4159 | * control is opt-out, i.e. an exiting control, clear the control if | |
4160 | * the feature _is_ exposed to the guest, i.e. exiting/interception is | |
4161 | * disabled for the associated instruction. Note, the caller is | |
4162 | * responsible presetting exec_control to set all supported bits. | |
4163 | */ | |
4164 | if (enabled == exiting) | |
4165 | *exec_control &= ~control; | |
4166 | ||
4167 | /* | |
4168 | * Update the nested MSR settings so that a nested VMM can/can't set | |
4169 | * controls for features that are/aren't exposed to the guest. | |
4170 | */ | |
4171 | if (nested) { | |
4172 | if (enabled) | |
4173 | vmx->nested.msrs.secondary_ctls_high |= control; | |
4174 | else | |
4175 | vmx->nested.msrs.secondary_ctls_high &= ~control; | |
4176 | } | |
4177 | } | |
4178 | ||
4179 | /* | |
4180 | * Wrapper macro for the common case of adjusting a secondary execution control | |
4181 | * based on a single guest CPUID bit, with a dedicated feature bit. This also | |
4182 | * verifies that the control is actually supported by KVM and hardware. | |
4183 | */ | |
4184 | #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \ | |
4185 | ({ \ | |
4186 | bool __enabled; \ | |
4187 | \ | |
4188 | if (cpu_has_vmx_##name()) { \ | |
4189 | __enabled = guest_cpuid_has(&(vmx)->vcpu, \ | |
4190 | X86_FEATURE_##feat_name); \ | |
4191 | vmx_adjust_secondary_exec_control(vmx, exec_control, \ | |
4192 | SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \ | |
4193 | } \ | |
4194 | }) | |
4195 | ||
4196 | /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */ | |
4197 | #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \ | |
4198 | vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false) | |
4199 | ||
4200 | #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \ | |
4201 | vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true) | |
89b0c9f5 | 4202 | |
80154d77 | 4203 | static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) |
bf8179a0 | 4204 | { |
80154d77 PB |
4205 | struct kvm_vcpu *vcpu = &vmx->vcpu; |
4206 | ||
bf8179a0 | 4207 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; |
0367f205 | 4208 | |
2ef7619d | 4209 | if (vmx_pt_mode_is_system()) |
f99e3daf | 4210 | exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); |
80154d77 | 4211 | if (!cpu_need_virtualize_apic_accesses(vcpu)) |
bf8179a0 NHE |
4212 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
4213 | if (vmx->vpid == 0) | |
4214 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
4215 | if (!enable_ept) { | |
4216 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
4217 | enable_unrestricted_guest = 0; | |
4218 | } | |
4219 | if (!enable_unrestricted_guest) | |
4220 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
b31c114b | 4221 | if (kvm_pause_in_guest(vmx->vcpu.kvm)) |
bf8179a0 | 4222 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; |
80154d77 | 4223 | if (!kvm_vcpu_apicv_active(vcpu)) |
c7c9c56c YZ |
4224 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
4225 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 4226 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
0367f205 PB |
4227 | |
4228 | /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, | |
4229 | * in vmx_set_cr4. */ | |
4230 | exec_control &= ~SECONDARY_EXEC_DESC; | |
4231 | ||
abc4fc58 AG |
4232 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
4233 | (handle_vmptrld). | |
4234 | We can NOT enable shadow_vmcs here because we don't have yet | |
4235 | a current VMCS12 | |
4236 | */ | |
4237 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
4238 | |
4239 | if (!enable_pml) | |
4240 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 4241 | |
becdad85 | 4242 | if (cpu_has_vmx_xsaves()) { |
3db13480 PB |
4243 | /* Exposing XSAVES only when XSAVE is exposed */ |
4244 | bool xsaves_enabled = | |
96be4e06 | 4245 | boot_cpu_has(X86_FEATURE_XSAVE) && |
3db13480 PB |
4246 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && |
4247 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); | |
4248 | ||
7204160e AL |
4249 | vcpu->arch.xsaves_enabled = xsaves_enabled; |
4250 | ||
8b50b92f SC |
4251 | vmx_adjust_secondary_exec_control(vmx, &exec_control, |
4252 | SECONDARY_EXEC_XSAVES, | |
4253 | xsaves_enabled, false); | |
45ec368c JM |
4254 | } |
4255 | ||
8b50b92f | 4256 | vmx_adjust_sec_exec_feature(vmx, &exec_control, rdtscp, RDTSCP); |
75f4fc8d | 4257 | |
b936d3eb SC |
4258 | /* |
4259 | * Expose INVPCID if and only if PCID is also exposed to the guest. | |
4260 | * INVPCID takes a #UD when it's disabled in the VMCS, but a #GP or #PF | |
4261 | * if CR4.PCIDE=0. Enumerating CPUID.INVPCID=1 would lead to incorrect | |
4262 | * behavior from the guest perspective (it would expect #GP or #PF). | |
4263 | */ | |
4264 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) | |
4265 | guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); | |
8b50b92f | 4266 | vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID); |
75f4fc8d | 4267 | |
e69e72fa | 4268 | |
8b50b92f SC |
4269 | vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND); |
4270 | vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED); | |
e69e72fa | 4271 | |
8b50b92f SC |
4272 | vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG, |
4273 | ENABLE_USR_WAIT_PAUSE, false); | |
e69e72fa | 4274 | |
80154d77 | 4275 | vmx->secondary_exec_control = exec_control; |
bf8179a0 NHE |
4276 | } |
4277 | ||
ce88decf XG |
4278 | static void ept_set_mmio_spte_mask(void) |
4279 | { | |
4280 | /* | |
4281 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
4282 | * of an EPT paging-structure entry is 110b (write/execute). | |
ce88decf | 4283 | */ |
e7581cac | 4284 | kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 0); |
ce88decf XG |
4285 | } |
4286 | ||
f53cd63c | 4287 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 | 4288 | |
944c3464 | 4289 | /* |
1b84292b XL |
4290 | * Noting that the initialization of Guest-state Area of VMCS is in |
4291 | * vmx_vcpu_reset(). | |
944c3464 | 4292 | */ |
1b84292b | 4293 | static void init_vmcs(struct vcpu_vmx *vmx) |
944c3464 | 4294 | { |
944c3464 | 4295 | if (nested) |
1b84292b | 4296 | nested_vmx_set_vmcs_shadowing_bitmap(); |
944c3464 | 4297 | |
25c5f225 | 4298 | if (cpu_has_vmx_msr_bitmap()) |
904e14fb | 4299 | vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); |
25c5f225 | 4300 | |
6aa8b732 AK |
4301 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
4302 | ||
6aa8b732 | 4303 | /* Control */ |
3af80fec | 4304 | pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); |
6e5d865c | 4305 | |
3af80fec | 4306 | exec_controls_set(vmx, vmx_exec_control(vmx)); |
6aa8b732 | 4307 | |
dfa169bb | 4308 | if (cpu_has_secondary_exec_ctrls()) { |
80154d77 | 4309 | vmx_compute_secondary_exec_control(vmx); |
3af80fec | 4310 | secondary_exec_controls_set(vmx, vmx->secondary_exec_control); |
dfa169bb | 4311 | } |
f78e0e2e | 4312 | |
d62caabb | 4313 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
4314 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
4315 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
4316 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
4317 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
4318 | ||
4319 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 4320 | |
0bcf261c | 4321 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 4322 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
4323 | } |
4324 | ||
b31c114b | 4325 | if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { |
4b8d54f9 | 4326 | vmcs_write32(PLE_GAP, ple_gap); |
a7653ecd RK |
4327 | vmx->ple_window = ple_window; |
4328 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
4329 | } |
4330 | ||
c3707958 XG |
4331 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
4332 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
4333 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
4334 | ||
9581d442 AK |
4335 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
4336 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 4337 | vmx_set_constant_host_state(vmx); |
6aa8b732 AK |
4338 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ |
4339 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
6aa8b732 | 4340 | |
2a499e49 BD |
4341 | if (cpu_has_vmx_vmfunc()) |
4342 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
4343 | ||
2cc51560 ED |
4344 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
4345 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
33966dd6 | 4346 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); |
2cc51560 | 4347 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
33966dd6 | 4348 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); |
6aa8b732 | 4349 | |
74545705 RK |
4350 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
4351 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 4352 | |
3af80fec | 4353 | vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); |
6aa8b732 AK |
4354 | |
4355 | /* 22.2.1, 20.8.1 */ | |
3af80fec | 4356 | vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); |
1c3d14fe | 4357 | |
fa71e952 SC |
4358 | vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS; |
4359 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits); | |
bd7e5b08 | 4360 | |
bf8179a0 | 4361 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 4362 | |
35fbe0d4 XL |
4363 | if (vmx->vpid != 0) |
4364 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
4365 | ||
becdad85 | 4366 | if (cpu_has_vmx_xsaves()) |
f53cd63c WL |
4367 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); |
4368 | ||
4e59516a | 4369 | if (enable_pml) { |
4e59516a PF |
4370 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); |
4371 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
4372 | } | |
0b665d30 SC |
4373 | |
4374 | if (cpu_has_vmx_encls_vmexit()) | |
4375 | vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); | |
2ef444f1 | 4376 | |
2ef7619d | 4377 | if (vmx_pt_mode_is_host_guest()) { |
2ef444f1 CP |
4378 | memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); |
4379 | /* Bit[6~0] are forced to 1, writes are ignored. */ | |
4380 | vmx->pt_desc.guest.output_mask = 0x7F; | |
4381 | vmcs_write64(GUEST_IA32_RTIT_CTL, 0); | |
4382 | } | |
e00c8cf2 AK |
4383 | } |
4384 | ||
d28bc9dd | 4385 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
4386 | { |
4387 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 4388 | struct msr_data apic_base_msr; |
d28bc9dd | 4389 | u64 cr0; |
e00c8cf2 | 4390 | |
7ffd92c5 | 4391 | vmx->rmode.vm86_active = 0; |
d28b387f | 4392 | vmx->spec_ctrl = 0; |
e00c8cf2 | 4393 | |
6e3ba4ab TX |
4394 | vmx->msr_ia32_umwait_control = 0; |
4395 | ||
ad312c7c | 4396 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
95c06540 | 4397 | vmx->hv_deadline_tsc = -1; |
d28bc9dd NA |
4398 | kvm_set_cr8(vcpu, 0); |
4399 | ||
4400 | if (!init_event) { | |
4401 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
4402 | MSR_IA32_APICBASE_ENABLE; | |
4403 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
4404 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
4405 | apic_base_msr.host_initiated = true; | |
4406 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
4407 | } | |
e00c8cf2 | 4408 | |
2fb92db1 AK |
4409 | vmx_segment_cache_clear(vmx); |
4410 | ||
5706be0d | 4411 | seg_setup(VCPU_SREG_CS); |
66450a21 | 4412 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 4413 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
4414 | |
4415 | seg_setup(VCPU_SREG_DS); | |
4416 | seg_setup(VCPU_SREG_ES); | |
4417 | seg_setup(VCPU_SREG_FS); | |
4418 | seg_setup(VCPU_SREG_GS); | |
4419 | seg_setup(VCPU_SREG_SS); | |
4420 | ||
4421 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
4422 | vmcs_writel(GUEST_TR_BASE, 0); | |
4423 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
4424 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
4425 | ||
4426 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
4427 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
4428 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
4429 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
4430 | ||
d28bc9dd NA |
4431 | if (!init_event) { |
4432 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
4433 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
4434 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
4435 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
4436 | } | |
e00c8cf2 | 4437 | |
c37c2873 | 4438 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
66450a21 | 4439 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 4440 | |
e00c8cf2 AK |
4441 | vmcs_writel(GUEST_GDTR_BASE, 0); |
4442 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
4443 | ||
4444 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
4445 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
4446 | ||
443381a8 | 4447 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 4448 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 4449 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
a554d207 WL |
4450 | if (kvm_mpx_supported()) |
4451 | vmcs_write64(GUEST_BNDCFGS, 0); | |
e00c8cf2 | 4452 | |
e00c8cf2 AK |
4453 | setup_msrs(vmx); |
4454 | ||
6aa8b732 AK |
4455 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
4456 | ||
d28bc9dd | 4457 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 4458 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 4459 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 4460 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 4461 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
4462 | vmcs_write32(TPR_THRESHOLD, 0); |
4463 | } | |
4464 | ||
a73896cb | 4465 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 4466 | |
d28bc9dd | 4467 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 4468 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 4469 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 4470 | vmx_set_cr4(vcpu, 0); |
5690891b | 4471 | vmx_set_efer(vcpu, 0); |
bd7e5b08 | 4472 | |
d28bc9dd | 4473 | update_exception_bitmap(vcpu); |
6aa8b732 | 4474 | |
dd5f5341 | 4475 | vpid_sync_context(vmx->vpid); |
caa057a2 WL |
4476 | if (init_event) |
4477 | vmx_clear_hlt(vcpu); | |
6aa8b732 AK |
4478 | } |
4479 | ||
55d2375e | 4480 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 4481 | { |
9dadc2f9 | 4482 | exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); |
3b86cd99 JK |
4483 | } |
4484 | ||
c9a7953f | 4485 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 4486 | { |
d02fcf50 | 4487 | if (!enable_vnmi || |
8a1b4392 | 4488 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
c9a7953f JK |
4489 | enable_irq_window(vcpu); |
4490 | return; | |
4491 | } | |
3b86cd99 | 4492 | |
4e2a0bc5 | 4493 | exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); |
3b86cd99 JK |
4494 | } |
4495 | ||
66fd3f7f | 4496 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 4497 | { |
9c8cba37 | 4498 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
4499 | uint32_t intr; |
4500 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 4501 | |
229456fc | 4502 | trace_kvm_inj_virq(irq); |
2714d1d3 | 4503 | |
fa89a817 | 4504 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 4505 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
4506 | int inc_eip = 0; |
4507 | if (vcpu->arch.interrupt.soft) | |
4508 | inc_eip = vcpu->arch.event_exit_inst_len; | |
9497e1f2 | 4509 | kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); |
85f455f7 ED |
4510 | return; |
4511 | } | |
66fd3f7f GN |
4512 | intr = irq | INTR_INFO_VALID_MASK; |
4513 | if (vcpu->arch.interrupt.soft) { | |
4514 | intr |= INTR_TYPE_SOFT_INTR; | |
4515 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
4516 | vmx->vcpu.arch.event_exit_inst_len); | |
4517 | } else | |
4518 | intr |= INTR_TYPE_EXT_INTR; | |
4519 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
caa057a2 WL |
4520 | |
4521 | vmx_clear_hlt(vcpu); | |
85f455f7 ED |
4522 | } |
4523 | ||
f08864b4 SY |
4524 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
4525 | { | |
66a5a347 JK |
4526 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4527 | ||
d02fcf50 | 4528 | if (!enable_vnmi) { |
8a1b4392 PB |
4529 | /* |
4530 | * Tracking the NMI-blocked state in software is built upon | |
4531 | * finding the next open IRQ window. This, in turn, depends on | |
4532 | * well-behaving guests: They have to keep IRQs disabled at | |
4533 | * least as long as the NMI handler runs. Otherwise we may | |
4534 | * cause NMI nesting, maybe breaking the guest. But as this is | |
4535 | * highly unlikely, we can live with the residual risk. | |
4536 | */ | |
4537 | vmx->loaded_vmcs->soft_vnmi_blocked = 1; | |
4538 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
4539 | } | |
4540 | ||
4c4a6f79 PB |
4541 | ++vcpu->stat.nmi_injections; |
4542 | vmx->loaded_vmcs->nmi_known_unmasked = false; | |
3b86cd99 | 4543 | |
7ffd92c5 | 4544 | if (vmx->rmode.vm86_active) { |
9497e1f2 | 4545 | kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); |
66a5a347 JK |
4546 | return; |
4547 | } | |
c5a6d5f7 | 4548 | |
f08864b4 SY |
4549 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
4550 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
caa057a2 WL |
4551 | |
4552 | vmx_clear_hlt(vcpu); | |
f08864b4 SY |
4553 | } |
4554 | ||
97b7ead3 | 4555 | bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
3cfc3092 | 4556 | { |
4c4a6f79 PB |
4557 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4558 | bool masked; | |
4559 | ||
d02fcf50 | 4560 | if (!enable_vnmi) |
8a1b4392 | 4561 | return vmx->loaded_vmcs->soft_vnmi_blocked; |
4c4a6f79 | 4562 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9d58b931 | 4563 | return false; |
4c4a6f79 PB |
4564 | masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
4565 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
4566 | return masked; | |
3cfc3092 JK |
4567 | } |
4568 | ||
97b7ead3 | 4569 | void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) |
3cfc3092 JK |
4570 | { |
4571 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4572 | ||
d02fcf50 | 4573 | if (!enable_vnmi) { |
8a1b4392 PB |
4574 | if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { |
4575 | vmx->loaded_vmcs->soft_vnmi_blocked = masked; | |
4576 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
4577 | } | |
4578 | } else { | |
4579 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
4580 | if (masked) | |
4581 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
4582 | GUEST_INTR_STATE_NMI); | |
4583 | else | |
4584 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
4585 | GUEST_INTR_STATE_NMI); | |
4586 | } | |
3cfc3092 JK |
4587 | } |
4588 | ||
1b660b6b SC |
4589 | bool vmx_nmi_blocked(struct kvm_vcpu *vcpu) |
4590 | { | |
4591 | if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu)) | |
4592 | return false; | |
4593 | ||
4594 | if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) | |
4595 | return true; | |
4596 | ||
4597 | return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
4598 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | | |
4599 | GUEST_INTR_STATE_NMI)); | |
4600 | } | |
4601 | ||
c9d40913 | 4602 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection) |
2505dc9f | 4603 | { |
b6b8a145 | 4604 | if (to_vmx(vcpu)->nested.nested_run_pending) |
c9d40913 | 4605 | return -EBUSY; |
ea8ceb83 | 4606 | |
c300ab9f PB |
4607 | /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */ |
4608 | if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu)) | |
c9d40913 | 4609 | return -EBUSY; |
c300ab9f | 4610 | |
1b660b6b SC |
4611 | return !vmx_nmi_blocked(vcpu); |
4612 | } | |
429ab576 | 4613 | |
1b660b6b SC |
4614 | bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu) |
4615 | { | |
4616 | if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) | |
88c604b6 | 4617 | return false; |
8a1b4392 | 4618 | |
7ab0abdb | 4619 | return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) || |
1b660b6b SC |
4620 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
4621 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
2505dc9f JK |
4622 | } |
4623 | ||
c9d40913 | 4624 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection) |
78646121 | 4625 | { |
a1c77abb | 4626 | if (to_vmx(vcpu)->nested.nested_run_pending) |
c9d40913 | 4627 | return -EBUSY; |
a1c77abb | 4628 | |
c300ab9f PB |
4629 | /* |
4630 | * An IRQ must not be injected into L2 if it's supposed to VM-Exit, | |
4631 | * e.g. if the IRQ arrived asynchronously after checking nested events. | |
4632 | */ | |
4633 | if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) | |
c9d40913 | 4634 | return -EBUSY; |
c300ab9f | 4635 | |
1b660b6b | 4636 | return !vmx_interrupt_blocked(vcpu); |
78646121 GN |
4637 | } |
4638 | ||
cbc94022 IE |
4639 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
4640 | { | |
ff5a983c | 4641 | void __user *ret; |
cbc94022 | 4642 | |
f7eaeb0a SC |
4643 | if (enable_unrestricted_guest) |
4644 | return 0; | |
4645 | ||
6a3c623b PX |
4646 | mutex_lock(&kvm->slots_lock); |
4647 | ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, | |
4648 | PAGE_SIZE * 3); | |
4649 | mutex_unlock(&kvm->slots_lock); | |
4650 | ||
ff5a983c PX |
4651 | if (IS_ERR(ret)) |
4652 | return PTR_ERR(ret); | |
4653 | ||
40bbb9d0 | 4654 | to_kvm_vmx(kvm)->tss_addr = addr; |
ff5a983c PX |
4655 | |
4656 | return init_rmode_tss(kvm, ret); | |
cbc94022 IE |
4657 | } |
4658 | ||
2ac52ab8 SC |
4659 | static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) |
4660 | { | |
40bbb9d0 | 4661 | to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; |
2ac52ab8 SC |
4662 | return 0; |
4663 | } | |
4664 | ||
0ca1b4f4 | 4665 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 4666 | { |
77ab6db0 | 4667 | switch (vec) { |
77ab6db0 | 4668 | case BP_VECTOR: |
c573cd22 JK |
4669 | /* |
4670 | * Update instruction length as we may reinject the exception | |
4671 | * from user space while in guest debugging mode. | |
4672 | */ | |
4673 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
4674 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 4675 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 | 4676 | return false; |
df561f66 | 4677 | fallthrough; |
0ca1b4f4 | 4678 | case DB_VECTOR: |
a8cfbae5 ML |
4679 | return !(vcpu->guest_debug & |
4680 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)); | |
d0bfb940 | 4681 | case DE_VECTOR: |
77ab6db0 JK |
4682 | case OF_VECTOR: |
4683 | case BR_VECTOR: | |
4684 | case UD_VECTOR: | |
4685 | case DF_VECTOR: | |
4686 | case SS_VECTOR: | |
4687 | case GP_VECTOR: | |
4688 | case MF_VECTOR: | |
0ca1b4f4 | 4689 | return true; |
77ab6db0 | 4690 | } |
0ca1b4f4 GN |
4691 | return false; |
4692 | } | |
4693 | ||
4694 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
4695 | int vec, u32 err_code) | |
4696 | { | |
4697 | /* | |
4698 | * Instruction with address size override prefix opcode 0x67 | |
4699 | * Cause the #SS fault with 0 error code in VM86 mode. | |
4700 | */ | |
4701 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
60fc3d02 | 4702 | if (kvm_emulate_instruction(vcpu, 0)) { |
0ca1b4f4 GN |
4703 | if (vcpu->arch.halt_request) { |
4704 | vcpu->arch.halt_request = 0; | |
5cb56059 | 4705 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
4706 | } |
4707 | return 1; | |
4708 | } | |
4709 | return 0; | |
4710 | } | |
4711 | ||
4712 | /* | |
4713 | * Forward all other exceptions that are valid in real mode. | |
4714 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
4715 | * the required debugging infrastructure rework. | |
4716 | */ | |
4717 | kvm_queue_exception(vcpu, vec); | |
4718 | return 1; | |
6aa8b732 AK |
4719 | } |
4720 | ||
851ba692 | 4721 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 | 4722 | { |
95b5a48c | 4723 | /* handled by vmx_vcpu_run() */ |
a0861c02 AK |
4724 | return 1; |
4725 | } | |
4726 | ||
e6f8b6c1 XL |
4727 | /* |
4728 | * If the host has split lock detection disabled, then #AC is | |
4729 | * unconditionally injected into the guest, which is the pre split lock | |
4730 | * detection behaviour. | |
4731 | * | |
4732 | * If the host has split lock detection enabled then #AC is | |
4733 | * only injected into the guest when: | |
4734 | * - Guest CPL == 3 (user mode) | |
4735 | * - Guest has #AC detection enabled in CR0 | |
4736 | * - Guest EFLAGS has AC bit set | |
4737 | */ | |
4738 | static inline bool guest_inject_ac(struct kvm_vcpu *vcpu) | |
4739 | { | |
4740 | if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
4741 | return true; | |
4742 | ||
4743 | return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) && | |
4744 | (kvm_get_rflags(vcpu) & X86_EFLAGS_AC); | |
4745 | } | |
4746 | ||
95b5a48c | 4747 | static int handle_exception_nmi(struct kvm_vcpu *vcpu) |
6aa8b732 | 4748 | { |
1155f76a | 4749 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 4750 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 4751 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 4752 | unsigned long cr2, rip, dr6; |
6aa8b732 | 4753 | u32 vect_info; |
6aa8b732 | 4754 | |
1155f76a | 4755 | vect_info = vmx->idt_vectoring_info; |
f27ad73a | 4756 | intr_info = vmx_get_intr_info(vcpu); |
6aa8b732 | 4757 | |
2ea72039 | 4758 | if (is_machine_check(intr_info) || is_nmi(intr_info)) |
95b5a48c | 4759 | return 1; /* handled by handle_exception_nmi_irqoff() */ |
2ab455cc | 4760 | |
082d06ed WL |
4761 | if (is_invalid_opcode(intr_info)) |
4762 | return handle_ud(vcpu); | |
7aa81cc0 | 4763 | |
6aa8b732 | 4764 | error_code = 0; |
2e11384c | 4765 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 4766 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e | 4767 | |
9e869480 LA |
4768 | if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { |
4769 | WARN_ON_ONCE(!enable_vmware_backdoor); | |
a6c6ed1e SC |
4770 | |
4771 | /* | |
4772 | * VMware backdoor emulation on #GP interception only handles | |
4773 | * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero | |
4774 | * error code on #GP. | |
4775 | */ | |
4776 | if (error_code) { | |
4777 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
4778 | return 1; | |
4779 | } | |
60fc3d02 | 4780 | return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); |
9e869480 LA |
4781 | } |
4782 | ||
bf4ca23e XG |
4783 | /* |
4784 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
4785 | * MMIO, it is better to report an internal error. | |
4786 | * See the comments in vmx_handle_exit. | |
4787 | */ | |
4788 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
4789 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
4790 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4791 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
1aa561b1 | 4792 | vcpu->run->internal.ndata = 4; |
bf4ca23e XG |
4793 | vcpu->run->internal.data[0] = vect_info; |
4794 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 4795 | vcpu->run->internal.data[2] = error_code; |
8a14fe4f | 4796 | vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu; |
bf4ca23e XG |
4797 | return 0; |
4798 | } | |
4799 | ||
6aa8b732 | 4800 | if (is_page_fault(intr_info)) { |
5addc235 | 4801 | cr2 = vmx_get_exit_qual(vcpu); |
1dbf5d68 MG |
4802 | if (enable_ept && !vcpu->arch.apf.host_apf_flags) { |
4803 | /* | |
4804 | * EPT will cause page fault only if we need to | |
4805 | * detect illegal GPAs. | |
4806 | */ | |
b96e6506 | 4807 | WARN_ON_ONCE(!allow_smaller_maxphyaddr); |
1dbf5d68 MG |
4808 | kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code); |
4809 | return 1; | |
4810 | } else | |
4811 | return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); | |
6aa8b732 AK |
4812 | } |
4813 | ||
d0bfb940 | 4814 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
4815 | |
4816 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
4817 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
4818 | ||
42dbaa5a JK |
4819 | switch (ex_no) { |
4820 | case DB_VECTOR: | |
5addc235 | 4821 | dr6 = vmx_get_exit_qual(vcpu); |
42dbaa5a JK |
4822 | if (!(vcpu->guest_debug & |
4823 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
32d43cd3 | 4824 | if (is_icebp(intr_info)) |
1957aa63 | 4825 | WARN_ON(!skip_emulated_instruction(vcpu)); |
fd2a445a | 4826 | |
4d5523cf | 4827 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
42dbaa5a JK |
4828 | return 1; |
4829 | } | |
13196638 | 4830 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
42dbaa5a | 4831 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); |
df561f66 | 4832 | fallthrough; |
42dbaa5a | 4833 | case BP_VECTOR: |
c573cd22 JK |
4834 | /* |
4835 | * Update instruction length as we may reinject #BP from | |
4836 | * user space while in guest debugging mode. Reading it for | |
4837 | * #DB as well causes no harm, it is not used in that case. | |
4838 | */ | |
4839 | vmx->vcpu.arch.event_exit_inst_len = | |
4840 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 4841 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 4842 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
4843 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
4844 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a | 4845 | break; |
e6f8b6c1 XL |
4846 | case AC_VECTOR: |
4847 | if (guest_inject_ac(vcpu)) { | |
4848 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
4849 | return 1; | |
4850 | } | |
4851 | ||
4852 | /* | |
4853 | * Handle split lock. Depending on detection mode this will | |
4854 | * either warn and disable split lock detection for this | |
4855 | * task or force SIGBUS on it. | |
4856 | */ | |
4857 | if (handle_guest_split_lock(kvm_rip_read(vcpu))) | |
4858 | return 1; | |
4859 | fallthrough; | |
42dbaa5a | 4860 | default: |
d0bfb940 JK |
4861 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
4862 | kvm_run->ex.exception = ex_no; | |
4863 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 4864 | break; |
6aa8b732 | 4865 | } |
6aa8b732 AK |
4866 | return 0; |
4867 | } | |
4868 | ||
f399e60c | 4869 | static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 4870 | { |
1165f5fe | 4871 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
4872 | return 1; |
4873 | } | |
4874 | ||
851ba692 | 4875 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 4876 | { |
851ba692 | 4877 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 4878 | vcpu->mmio_needed = 0; |
988ad74f AK |
4879 | return 0; |
4880 | } | |
6aa8b732 | 4881 | |
851ba692 | 4882 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 4883 | { |
bfdaab09 | 4884 | unsigned long exit_qualification; |
dca7f128 | 4885 | int size, in, string; |
039576c0 | 4886 | unsigned port; |
6aa8b732 | 4887 | |
5addc235 | 4888 | exit_qualification = vmx_get_exit_qual(vcpu); |
039576c0 | 4889 | string = (exit_qualification & 16) != 0; |
e70669ab | 4890 | |
cf8f70bf | 4891 | ++vcpu->stat.io_exits; |
e70669ab | 4892 | |
432baf60 | 4893 | if (string) |
60fc3d02 | 4894 | return kvm_emulate_instruction(vcpu, 0); |
e70669ab | 4895 | |
cf8f70bf GN |
4896 | port = exit_qualification >> 16; |
4897 | size = (exit_qualification & 7) + 1; | |
432baf60 | 4898 | in = (exit_qualification & 8) != 0; |
cf8f70bf | 4899 | |
dca7f128 | 4900 | return kvm_fast_pio(vcpu, size, port, in); |
6aa8b732 AK |
4901 | } |
4902 | ||
102d8325 IM |
4903 | static void |
4904 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
4905 | { | |
4906 | /* | |
4907 | * Patch in the VMCALL instruction: | |
4908 | */ | |
4909 | hypercall[0] = 0x0f; | |
4910 | hypercall[1] = 0x01; | |
4911 | hypercall[2] = 0xc1; | |
102d8325 IM |
4912 | } |
4913 | ||
0fa06071 | 4914 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
4915 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
4916 | { | |
eeadf9e7 | 4917 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
4918 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
4919 | unsigned long orig_val = val; | |
4920 | ||
eeadf9e7 NHE |
4921 | /* |
4922 | * We get here when L2 changed cr0 in a way that did not change | |
4923 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
4924 | * but did change L0 shadowed bits. So we first calculate the |
4925 | * effective cr0 value that L1 would like to write into the | |
4926 | * hardware. It consists of the L2-owned bits from the new | |
4927 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 4928 | */ |
1a0d74e6 JK |
4929 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
4930 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
4931 | ||
3899152c | 4932 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 4933 | return 1; |
1a0d74e6 JK |
4934 | |
4935 | if (kvm_set_cr0(vcpu, val)) | |
4936 | return 1; | |
4937 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 4938 | return 0; |
1a0d74e6 JK |
4939 | } else { |
4940 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 4941 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 4942 | return 1; |
3899152c | 4943 | |
eeadf9e7 | 4944 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 4945 | } |
eeadf9e7 NHE |
4946 | } |
4947 | ||
4948 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
4949 | { | |
4950 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
4951 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
4952 | unsigned long orig_val = val; | |
4953 | ||
4954 | /* analogously to handle_set_cr0 */ | |
4955 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
4956 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
4957 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 4958 | return 1; |
1a0d74e6 | 4959 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
4960 | return 0; |
4961 | } else | |
4962 | return kvm_set_cr4(vcpu, val); | |
4963 | } | |
4964 | ||
0367f205 PB |
4965 | static int handle_desc(struct kvm_vcpu *vcpu) |
4966 | { | |
4967 | WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); | |
60fc3d02 | 4968 | return kvm_emulate_instruction(vcpu, 0); |
0367f205 PB |
4969 | } |
4970 | ||
851ba692 | 4971 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 4972 | { |
229456fc | 4973 | unsigned long exit_qualification, val; |
6aa8b732 AK |
4974 | int cr; |
4975 | int reg; | |
49a9b07e | 4976 | int err; |
6affcbed | 4977 | int ret; |
6aa8b732 | 4978 | |
5addc235 | 4979 | exit_qualification = vmx_get_exit_qual(vcpu); |
6aa8b732 AK |
4980 | cr = exit_qualification & 15; |
4981 | reg = (exit_qualification >> 8) & 15; | |
4982 | switch ((exit_qualification >> 4) & 3) { | |
4983 | case 0: /* mov to cr */ | |
1e32c079 | 4984 | val = kvm_register_readl(vcpu, reg); |
229456fc | 4985 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
4986 | switch (cr) { |
4987 | case 0: | |
eeadf9e7 | 4988 | err = handle_set_cr0(vcpu, val); |
6affcbed | 4989 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 4990 | case 3: |
e1de91cc | 4991 | WARN_ON_ONCE(enable_unrestricted_guest); |
2390218b | 4992 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 4993 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 4994 | case 4: |
eeadf9e7 | 4995 | err = handle_set_cr4(vcpu, val); |
6affcbed | 4996 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
4997 | case 8: { |
4998 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 4999 | u8 cr8 = (u8)val; |
eea1cff9 | 5000 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 5001 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 5002 | if (lapic_in_kernel(vcpu)) |
6affcbed | 5003 | return ret; |
0a5fff19 | 5004 | if (cr8_prev <= cr8) |
6affcbed KH |
5005 | return ret; |
5006 | /* | |
5007 | * TODO: we might be squashing a | |
5008 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
5009 | * KVM_EXIT_DEBUG here. | |
5010 | */ | |
851ba692 | 5011 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
5012 | return 0; |
5013 | } | |
4b8073e4 | 5014 | } |
6aa8b732 | 5015 | break; |
25c4c276 | 5016 | case 2: /* clts */ |
bd7e5b08 PB |
5017 | WARN_ONCE(1, "Guest should always own CR0.TS"); |
5018 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4d4ec087 | 5019 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6affcbed | 5020 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5021 | case 1: /*mov from cr*/ |
5022 | switch (cr) { | |
5023 | case 3: | |
e1de91cc | 5024 | WARN_ON_ONCE(enable_unrestricted_guest); |
9f8fe504 AK |
5025 | val = kvm_read_cr3(vcpu); |
5026 | kvm_register_write(vcpu, reg, val); | |
5027 | trace_kvm_cr_read(cr, val); | |
6affcbed | 5028 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 5029 | case 8: |
229456fc MT |
5030 | val = kvm_get_cr8(vcpu); |
5031 | kvm_register_write(vcpu, reg, val); | |
5032 | trace_kvm_cr_read(cr, val); | |
6affcbed | 5033 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5034 | } |
5035 | break; | |
5036 | case 3: /* lmsw */ | |
a1f83a74 | 5037 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 5038 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 5039 | kvm_lmsw(vcpu, val); |
6aa8b732 | 5040 | |
6affcbed | 5041 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5042 | default: |
5043 | break; | |
5044 | } | |
851ba692 | 5045 | vcpu->run->exit_reason = 0; |
a737f256 | 5046 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
5047 | (int)(exit_qualification >> 4) & 3, cr); |
5048 | return 0; | |
5049 | } | |
5050 | ||
851ba692 | 5051 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5052 | { |
bfdaab09 | 5053 | unsigned long exit_qualification; |
16f8a6f9 NA |
5054 | int dr, dr7, reg; |
5055 | ||
5addc235 | 5056 | exit_qualification = vmx_get_exit_qual(vcpu); |
16f8a6f9 NA |
5057 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; |
5058 | ||
5059 | /* First, if DR does not exist, trigger UD */ | |
5060 | if (!kvm_require_dr(vcpu, dr)) | |
5061 | return 1; | |
6aa8b732 | 5062 | |
f2483415 | 5063 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
5064 | if (!kvm_require_cpl(vcpu, 0)) |
5065 | return 1; | |
16f8a6f9 NA |
5066 | dr7 = vmcs_readl(GUEST_DR7); |
5067 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
5068 | /* |
5069 | * As the vm-exit takes precedence over the debug trap, we | |
5070 | * need to emulate the latter, either for the host or the | |
5071 | * guest debugging itself. | |
5072 | */ | |
5073 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
45981ded | 5074 | vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1; |
16f8a6f9 | 5075 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 5076 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
5077 | vcpu->run->debug.arch.exception = DB_VECTOR; |
5078 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
5079 | return 0; |
5080 | } else { | |
4d5523cf | 5081 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD); |
42dbaa5a JK |
5082 | return 1; |
5083 | } | |
5084 | } | |
5085 | ||
81908bf4 | 5086 | if (vcpu->guest_debug == 0) { |
2183f564 | 5087 | exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
5088 | |
5089 | /* | |
5090 | * No more DR vmexits; force a reload of the debug registers | |
5091 | * and reenter on this instruction. The next vmexit will | |
5092 | * retrieve the full state of the debug registers. | |
5093 | */ | |
5094 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
5095 | return 1; | |
5096 | } | |
5097 | ||
42dbaa5a JK |
5098 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
5099 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 5100 | unsigned long val; |
4c4d563b JK |
5101 | |
5102 | if (kvm_get_dr(vcpu, dr, &val)) | |
5103 | return 1; | |
5104 | kvm_register_write(vcpu, reg, val); | |
020df079 | 5105 | } else |
5777392e | 5106 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
5107 | return 1; |
5108 | ||
6affcbed | 5109 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
5110 | } |
5111 | ||
81908bf4 PB |
5112 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
5113 | { | |
81908bf4 PB |
5114 | get_debugreg(vcpu->arch.db[0], 0); |
5115 | get_debugreg(vcpu->arch.db[1], 1); | |
5116 | get_debugreg(vcpu->arch.db[2], 2); | |
5117 | get_debugreg(vcpu->arch.db[3], 3); | |
5118 | get_debugreg(vcpu->arch.dr6, 6); | |
5119 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
5120 | ||
5121 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
2183f564 | 5122 | exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
5123 | } |
5124 | ||
020df079 GN |
5125 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
5126 | { | |
5127 | vmcs_writel(GUEST_DR7, val); | |
5128 | } | |
5129 | ||
851ba692 | 5130 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 5131 | { |
eb90f341 | 5132 | kvm_apic_update_ppr(vcpu); |
6e5d865c YS |
5133 | return 1; |
5134 | } | |
5135 | ||
851ba692 | 5136 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 5137 | { |
9dadc2f9 | 5138 | exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); |
2714d1d3 | 5139 | |
3842d135 AK |
5140 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5141 | ||
a26bf12a | 5142 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
5143 | return 1; |
5144 | } | |
5145 | ||
851ba692 | 5146 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 5147 | { |
0d9c055e | 5148 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
5149 | } |
5150 | ||
ec25d5e6 GN |
5151 | static int handle_invd(struct kvm_vcpu *vcpu) |
5152 | { | |
28e2b2f1 TL |
5153 | /* Treat an INVD instruction as a NOP and just skip it. */ |
5154 | return kvm_skip_emulated_instruction(vcpu); | |
ec25d5e6 GN |
5155 | } |
5156 | ||
851ba692 | 5157 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 5158 | { |
5addc235 | 5159 | unsigned long exit_qualification = vmx_get_exit_qual(vcpu); |
a7052897 MT |
5160 | |
5161 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 5162 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
5163 | } |
5164 | ||
fee84b07 AK |
5165 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
5166 | { | |
5167 | int err; | |
5168 | ||
5169 | err = kvm_rdpmc(vcpu); | |
6affcbed | 5170 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
5171 | } |
5172 | ||
851ba692 | 5173 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 5174 | { |
6affcbed | 5175 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
5176 | } |
5177 | ||
2acf923e DC |
5178 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
5179 | { | |
5180 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
de3cd117 | 5181 | u32 index = kvm_rcx_read(vcpu); |
2acf923e DC |
5182 | |
5183 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 5184 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
5185 | return 1; |
5186 | } | |
5187 | ||
851ba692 | 5188 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 5189 | { |
58fbbf26 | 5190 | if (likely(fasteoi)) { |
5addc235 | 5191 | unsigned long exit_qualification = vmx_get_exit_qual(vcpu); |
58fbbf26 KT |
5192 | int access_type, offset; |
5193 | ||
5194 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
5195 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
5196 | /* | |
5197 | * Sane guest uses MOV to write EOI, with written value | |
5198 | * not cared. So make a short-circuit here by avoiding | |
5199 | * heavy instruction emulation. | |
5200 | */ | |
5201 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
5202 | (offset == APIC_EOI)) { | |
5203 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 5204 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
5205 | } |
5206 | } | |
60fc3d02 | 5207 | return kvm_emulate_instruction(vcpu, 0); |
f78e0e2e SY |
5208 | } |
5209 | ||
c7c9c56c YZ |
5210 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
5211 | { | |
5addc235 | 5212 | unsigned long exit_qualification = vmx_get_exit_qual(vcpu); |
c7c9c56c YZ |
5213 | int vector = exit_qualification & 0xff; |
5214 | ||
5215 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
5216 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
5217 | return 1; | |
5218 | } | |
5219 | ||
83d4c286 YZ |
5220 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
5221 | { | |
5addc235 | 5222 | unsigned long exit_qualification = vmx_get_exit_qual(vcpu); |
83d4c286 YZ |
5223 | u32 offset = exit_qualification & 0xfff; |
5224 | ||
5225 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
5226 | kvm_apic_write_nodecode(vcpu, offset); | |
5227 | return 1; | |
5228 | } | |
5229 | ||
851ba692 | 5230 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 5231 | { |
60637aac | 5232 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 5233 | unsigned long exit_qualification; |
e269fb21 JK |
5234 | bool has_error_code = false; |
5235 | u32 error_code = 0; | |
37817f29 | 5236 | u16 tss_selector; |
7f3d35fd | 5237 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
5238 | |
5239 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 5240 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 5241 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 | 5242 | |
5addc235 | 5243 | exit_qualification = vmx_get_exit_qual(vcpu); |
37817f29 IE |
5244 | |
5245 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
5246 | if (reason == TASK_SWITCH_GATE && idt_v) { |
5247 | switch (type) { | |
5248 | case INTR_TYPE_NMI_INTR: | |
5249 | vcpu->arch.nmi_injected = false; | |
654f06fc | 5250 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
5251 | break; |
5252 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 5253 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
5254 | kvm_clear_interrupt_queue(vcpu); |
5255 | break; | |
5256 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
5257 | if (vmx->idt_vectoring_info & |
5258 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
5259 | has_error_code = true; | |
5260 | error_code = | |
5261 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
5262 | } | |
df561f66 | 5263 | fallthrough; |
64a7ec06 GN |
5264 | case INTR_TYPE_SOFT_EXCEPTION: |
5265 | kvm_clear_exception_queue(vcpu); | |
5266 | break; | |
5267 | default: | |
5268 | break; | |
5269 | } | |
60637aac | 5270 | } |
37817f29 IE |
5271 | tss_selector = exit_qualification; |
5272 | ||
64a7ec06 GN |
5273 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
5274 | type != INTR_TYPE_EXT_INTR && | |
5275 | type != INTR_TYPE_NMI_INTR)) | |
1957aa63 | 5276 | WARN_ON(!skip_emulated_instruction(vcpu)); |
64a7ec06 | 5277 | |
42dbaa5a JK |
5278 | /* |
5279 | * TODO: What about debug traps on tss switch? | |
5280 | * Are we supposed to inject them and update dr6? | |
5281 | */ | |
1051778f SC |
5282 | return kvm_task_switch(vcpu, tss_selector, |
5283 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, | |
60fc3d02 | 5284 | reason, has_error_code, error_code); |
37817f29 IE |
5285 | } |
5286 | ||
851ba692 | 5287 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 5288 | { |
f9c617f6 | 5289 | unsigned long exit_qualification; |
1439442c | 5290 | gpa_t gpa; |
eebed243 | 5291 | u64 error_code; |
1439442c | 5292 | |
5addc235 | 5293 | exit_qualification = vmx_get_exit_qual(vcpu); |
1439442c | 5294 | |
0be9c7a8 GN |
5295 | /* |
5296 | * EPT violation happened while executing iret from NMI, | |
5297 | * "blocked by NMI" bit has to be set before next VM entry. | |
5298 | * There are errata that may cause this bit to not be set: | |
5299 | * AAK134, BY25. | |
5300 | */ | |
bcd1c294 | 5301 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
d02fcf50 | 5302 | enable_vnmi && |
bcd1c294 | 5303 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
0be9c7a8 GN |
5304 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
5305 | ||
1439442c | 5306 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 5307 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 5308 | |
27959a44 | 5309 | /* Is it a read fault? */ |
ab22a473 | 5310 | error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) |
27959a44 JS |
5311 | ? PFERR_USER_MASK : 0; |
5312 | /* Is it a write fault? */ | |
ab22a473 | 5313 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) |
27959a44 JS |
5314 | ? PFERR_WRITE_MASK : 0; |
5315 | /* Is it a fetch fault? */ | |
ab22a473 | 5316 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) |
27959a44 JS |
5317 | ? PFERR_FETCH_MASK : 0; |
5318 | /* ept page table entry is present? */ | |
5319 | error_code |= (exit_qualification & | |
5320 | (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | | |
5321 | EPT_VIOLATION_EXECUTABLE)) | |
5322 | ? PFERR_PRESENT_MASK : 0; | |
4f5982a5 | 5323 | |
eebed243 PB |
5324 | error_code |= (exit_qualification & 0x100) != 0 ? |
5325 | PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; | |
25d92081 | 5326 | |
25d92081 | 5327 | vcpu->arch.exit_qualification = exit_qualification; |
1dbf5d68 MG |
5328 | |
5329 | /* | |
5330 | * Check that the GPA doesn't exceed physical memory limits, as that is | |
5331 | * a guest page fault. We have to emulate the instruction here, because | |
5332 | * if the illegal address is that of a paging structure, then | |
5333 | * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we | |
5334 | * would also use advanced VM-exit information for EPT violations to | |
5335 | * reconstruct the page fault error code. | |
5336 | */ | |
c0623f5e | 5337 | if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa))) |
1dbf5d68 MG |
5338 | return kvm_emulate_instruction(vcpu, 0); |
5339 | ||
4f5982a5 | 5340 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
5341 | } |
5342 | ||
851ba692 | 5343 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 5344 | { |
68f89400 MT |
5345 | gpa_t gpa; |
5346 | ||
9034e6e8 PB |
5347 | /* |
5348 | * A nested guest cannot optimize MMIO vmexits, because we have an | |
5349 | * nGPA here instead of the required GPA. | |
5350 | */ | |
68f89400 | 5351 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
9034e6e8 PB |
5352 | if (!is_guest_mode(vcpu) && |
5353 | !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { | |
931c33b1 | 5354 | trace_kvm_fast_mmio(gpa); |
1957aa63 | 5355 | return kvm_skip_emulated_instruction(vcpu); |
68c3b4d1 | 5356 | } |
68f89400 | 5357 | |
c75d0edc | 5358 | return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); |
68f89400 MT |
5359 | } |
5360 | ||
851ba692 | 5361 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 | 5362 | { |
d02fcf50 | 5363 | WARN_ON_ONCE(!enable_vnmi); |
4e2a0bc5 | 5364 | exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); |
f08864b4 | 5365 | ++vcpu->stat.nmi_window_exits; |
3842d135 | 5366 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
5367 | |
5368 | return 1; | |
5369 | } | |
5370 | ||
80ced186 | 5371 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 5372 | { |
8b3079a5 | 5373 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
49e9d557 | 5374 | bool intr_window_requested; |
b8405c18 | 5375 | unsigned count = 130; |
49e9d557 | 5376 | |
2183f564 | 5377 | intr_window_requested = exec_controls_get(vmx) & |
9dadc2f9 | 5378 | CPU_BASED_INTR_WINDOW_EXITING; |
ea953ef0 | 5379 | |
98eb2f8b | 5380 | while (vmx->emulation_required && count-- != 0) { |
db438592 | 5381 | if (intr_window_requested && !vmx_interrupt_blocked(vcpu)) |
49e9d557 AK |
5382 | return handle_interrupt_window(&vmx->vcpu); |
5383 | ||
72875d8a | 5384 | if (kvm_test_request(KVM_REQ_EVENT, vcpu)) |
de87dcdd AK |
5385 | return 1; |
5386 | ||
60fc3d02 | 5387 | if (!kvm_emulate_instruction(vcpu, 0)) |
8fff2710 | 5388 | return 0; |
1d5a4d9b | 5389 | |
add5ff7a | 5390 | if (vmx->emulation_required && !vmx->rmode.vm86_active && |
8fff2710 SC |
5391 | vcpu->arch.exception.pending) { |
5392 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5393 | vcpu->run->internal.suberror = | |
5394 | KVM_INTERNAL_ERROR_EMULATION; | |
5395 | vcpu->run->internal.ndata = 0; | |
5396 | return 0; | |
5397 | } | |
ea953ef0 | 5398 | |
8d76c49e GN |
5399 | if (vcpu->arch.halt_request) { |
5400 | vcpu->arch.halt_request = 0; | |
8fff2710 | 5401 | return kvm_vcpu_halt(vcpu); |
8d76c49e GN |
5402 | } |
5403 | ||
8fff2710 | 5404 | /* |
72c3c0fe TG |
5405 | * Note, return 1 and not 0, vcpu_run() will invoke |
5406 | * xfer_to_guest_mode() which will create a proper return | |
5407 | * code. | |
8fff2710 | 5408 | */ |
72c3c0fe | 5409 | if (__xfer_to_guest_mode_work_pending()) |
8fff2710 | 5410 | return 1; |
ea953ef0 MG |
5411 | } |
5412 | ||
8fff2710 | 5413 | return 1; |
b4a2d31d RK |
5414 | } |
5415 | ||
5416 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
5417 | { | |
5418 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
c5c5d6fa | 5419 | unsigned int old = vmx->ple_window; |
b4a2d31d | 5420 | |
c8e88717 BM |
5421 | vmx->ple_window = __grow_ple_window(old, ple_window, |
5422 | ple_window_grow, | |
5423 | ple_window_max); | |
b4a2d31d | 5424 | |
4f75bcc3 | 5425 | if (vmx->ple_window != old) { |
b4a2d31d | 5426 | vmx->ple_window_dirty = true; |
4f75bcc3 PX |
5427 | trace_kvm_ple_window_update(vcpu->vcpu_id, |
5428 | vmx->ple_window, old); | |
5429 | } | |
b4a2d31d RK |
5430 | } |
5431 | ||
5432 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
5433 | { | |
5434 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
c5c5d6fa | 5435 | unsigned int old = vmx->ple_window; |
b4a2d31d | 5436 | |
c8e88717 BM |
5437 | vmx->ple_window = __shrink_ple_window(old, ple_window, |
5438 | ple_window_shrink, | |
5439 | ple_window); | |
b4a2d31d | 5440 | |
4f75bcc3 | 5441 | if (vmx->ple_window != old) { |
b4a2d31d | 5442 | vmx->ple_window_dirty = true; |
4f75bcc3 PX |
5443 | trace_kvm_ple_window_update(vcpu->vcpu_id, |
5444 | vmx->ple_window, old); | |
5445 | } | |
b4a2d31d RK |
5446 | } |
5447 | ||
e01bca2f | 5448 | static void vmx_enable_tdp(void) |
f160c7b7 JS |
5449 | { |
5450 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, | |
5451 | enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, | |
5452 | enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, | |
5453 | 0ull, VMX_EPT_EXECUTABLE_MASK, | |
5454 | cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, | |
d0ec49d4 | 5455 | VMX_EPT_RWX_MASK, 0ull); |
f160c7b7 JS |
5456 | |
5457 | ept_set_mmio_spte_mask(); | |
f160c7b7 JS |
5458 | } |
5459 | ||
4b8d54f9 ZE |
5460 | /* |
5461 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
5462 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
5463 | */ | |
9fb41ba8 | 5464 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 5465 | { |
b31c114b | 5466 | if (!kvm_pause_in_guest(vcpu->kvm)) |
b4a2d31d RK |
5467 | grow_ple_window(vcpu); |
5468 | ||
de63ad4c LM |
5469 | /* |
5470 | * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" | |
5471 | * VM-execution control is ignored if CPL > 0. OTOH, KVM | |
5472 | * never set PAUSE_EXITING and just set PLE if supported, | |
5473 | * so the vcpu must be CPL=0 if it gets a PAUSE exit. | |
5474 | */ | |
5475 | kvm_vcpu_on_spin(vcpu, true); | |
6affcbed | 5476 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
5477 | } |
5478 | ||
87c00572 | 5479 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 5480 | { |
6affcbed | 5481 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
5482 | } |
5483 | ||
87c00572 GS |
5484 | static int handle_mwait(struct kvm_vcpu *vcpu) |
5485 | { | |
5486 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
5487 | return handle_nop(vcpu); | |
5488 | } | |
5489 | ||
45ec368c JM |
5490 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
5491 | { | |
5492 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5493 | return 1; | |
5494 | } | |
5495 | ||
5f3d45e7 MD |
5496 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
5497 | { | |
5498 | return 1; | |
5499 | } | |
5500 | ||
87c00572 GS |
5501 | static int handle_monitor(struct kvm_vcpu *vcpu) |
5502 | { | |
5503 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
5504 | return handle_nop(vcpu); | |
5505 | } | |
5506 | ||
55d2375e | 5507 | static int handle_invpcid(struct kvm_vcpu *vcpu) |
19677e32 | 5508 | { |
55d2375e SC |
5509 | u32 vmx_instruction_info; |
5510 | unsigned long type; | |
55d2375e | 5511 | gva_t gva; |
55d2375e SC |
5512 | struct { |
5513 | u64 pcid; | |
5514 | u64 gla; | |
5515 | } operand; | |
f9eb4af6 | 5516 | |
55d2375e | 5517 | if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { |
19677e32 BD |
5518 | kvm_queue_exception(vcpu, UD_VECTOR); |
5519 | return 1; | |
5520 | } | |
5521 | ||
55d2375e SC |
5522 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); |
5523 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
5524 | ||
5525 | if (type > 3) { | |
5526 | kvm_inject_gp(vcpu, 0); | |
f9eb4af6 EK |
5527 | return 1; |
5528 | } | |
5529 | ||
55d2375e SC |
5530 | /* According to the Intel instruction reference, the memory operand |
5531 | * is read even if it isn't needed (e.g., for type==all) | |
5532 | */ | |
5addc235 | 5533 | if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), |
fdb28619 EK |
5534 | vmx_instruction_info, false, |
5535 | sizeof(operand), &gva)) | |
3573e22c BD |
5536 | return 1; |
5537 | ||
9715092f | 5538 | return kvm_handle_invpcid(vcpu, type, gva); |
e29acc55 JM |
5539 | } |
5540 | ||
55d2375e | 5541 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
ec378aee | 5542 | { |
55d2375e | 5543 | unsigned long exit_qualification; |
b3897a49 | 5544 | |
55d2375e | 5545 | trace_kvm_pml_full(vcpu->vcpu_id); |
b3897a49 | 5546 | |
5addc235 | 5547 | exit_qualification = vmx_get_exit_qual(vcpu); |
cbf71279 RK |
5548 | |
5549 | /* | |
55d2375e SC |
5550 | * PML buffer FULL happened while executing iret from NMI, |
5551 | * "blocked by NMI" bit has to be set before next VM entry. | |
cbf71279 | 5552 | */ |
55d2375e SC |
5553 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
5554 | enable_vnmi && | |
5555 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
5556 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5557 | GUEST_INTR_STATE_NMI); | |
e49fcb8b | 5558 | |
55d2375e SC |
5559 | /* |
5560 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
5561 | * here.., and there's no userspace involvement needed for PML. | |
5562 | */ | |
ec378aee NHE |
5563 | return 1; |
5564 | } | |
5565 | ||
26efe2fd | 5566 | static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu) |
8ca44e88 | 5567 | { |
804939ea SC |
5568 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5569 | ||
5570 | if (!vmx->req_immediate_exit && | |
26efe2fd | 5571 | !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) { |
55d2375e | 5572 | kvm_lapic_expired_hv_timer(vcpu); |
26efe2fd WL |
5573 | return EXIT_FASTPATH_REENTER_GUEST; |
5574 | } | |
5575 | ||
5576 | return EXIT_FASTPATH_NONE; | |
5577 | } | |
804939ea | 5578 | |
26efe2fd WL |
5579 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
5580 | { | |
5581 | handle_fastpath_preemption_timer(vcpu); | |
55d2375e | 5582 | return 1; |
8ca44e88 DM |
5583 | } |
5584 | ||
55d2375e SC |
5585 | /* |
5586 | * When nested=0, all VMX instruction VM Exits filter here. The handlers | |
5587 | * are overwritten by nested_vmx_setup() when nested=1. | |
5588 | */ | |
5589 | static int handle_vmx_instruction(struct kvm_vcpu *vcpu) | |
b8bbab92 | 5590 | { |
55d2375e SC |
5591 | kvm_queue_exception(vcpu, UD_VECTOR); |
5592 | return 1; | |
b8bbab92 VK |
5593 | } |
5594 | ||
55d2375e | 5595 | static int handle_encls(struct kvm_vcpu *vcpu) |
e7953d7f | 5596 | { |
55d2375e SC |
5597 | /* |
5598 | * SGX virtualization is not yet supported. There is no software | |
5599 | * enable bit for SGX, so we have to trap ENCLS and inject a #UD | |
5600 | * to prevent the guest from executing ENCLS. | |
5601 | */ | |
5602 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5603 | return 1; | |
e7953d7f AG |
5604 | } |
5605 | ||
ec378aee | 5606 | /* |
55d2375e SC |
5607 | * The exit handlers return 1 if the exit was handled fully and guest execution |
5608 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
5609 | * to be done to userspace and return 0. | |
ec378aee | 5610 | */ |
55d2375e | 5611 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
95b5a48c | 5612 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, |
55d2375e SC |
5613 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, |
5614 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, | |
5615 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, | |
5616 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, | |
5617 | [EXIT_REASON_CR_ACCESS] = handle_cr, | |
5618 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
f399e60c AA |
5619 | [EXIT_REASON_CPUID] = kvm_emulate_cpuid, |
5620 | [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, | |
5621 | [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, | |
9dadc2f9 | 5622 | [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, |
f399e60c | 5623 | [EXIT_REASON_HLT] = kvm_emulate_halt, |
55d2375e SC |
5624 | [EXIT_REASON_INVD] = handle_invd, |
5625 | [EXIT_REASON_INVLPG] = handle_invlpg, | |
5626 | [EXIT_REASON_RDPMC] = handle_rdpmc, | |
5627 | [EXIT_REASON_VMCALL] = handle_vmcall, | |
5628 | [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, | |
5629 | [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, | |
5630 | [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, | |
5631 | [EXIT_REASON_VMPTRST] = handle_vmx_instruction, | |
5632 | [EXIT_REASON_VMREAD] = handle_vmx_instruction, | |
5633 | [EXIT_REASON_VMRESUME] = handle_vmx_instruction, | |
5634 | [EXIT_REASON_VMWRITE] = handle_vmx_instruction, | |
5635 | [EXIT_REASON_VMOFF] = handle_vmx_instruction, | |
5636 | [EXIT_REASON_VMON] = handle_vmx_instruction, | |
5637 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, | |
5638 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
5639 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, | |
5640 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, | |
5641 | [EXIT_REASON_WBINVD] = handle_wbinvd, | |
5642 | [EXIT_REASON_XSETBV] = handle_xsetbv, | |
5643 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, | |
5644 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, | |
5645 | [EXIT_REASON_GDTR_IDTR] = handle_desc, | |
5646 | [EXIT_REASON_LDTR_TR] = handle_desc, | |
5647 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, | |
5648 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
5649 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, | |
5650 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, | |
5651 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, | |
5652 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, | |
5653 | [EXIT_REASON_INVEPT] = handle_vmx_instruction, | |
5654 | [EXIT_REASON_INVVPID] = handle_vmx_instruction, | |
5655 | [EXIT_REASON_RDRAND] = handle_invalid_op, | |
5656 | [EXIT_REASON_RDSEED] = handle_invalid_op, | |
55d2375e SC |
5657 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
5658 | [EXIT_REASON_INVPCID] = handle_invpcid, | |
5659 | [EXIT_REASON_VMFUNC] = handle_vmx_instruction, | |
5660 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, | |
5661 | [EXIT_REASON_ENCLS] = handle_encls, | |
5662 | }; | |
b8bbab92 | 5663 | |
55d2375e SC |
5664 | static const int kvm_vmx_max_exit_handlers = |
5665 | ARRAY_SIZE(kvm_vmx_exit_handlers); | |
ec378aee | 5666 | |
235ba74f SC |
5667 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2, |
5668 | u32 *intr_info, u32 *error_code) | |
ec378aee | 5669 | { |
235ba74f SC |
5670 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5671 | ||
5addc235 | 5672 | *info1 = vmx_get_exit_qual(vcpu); |
a6bdda1f | 5673 | if (!(vmx->exit_reason.failed_vmentry)) { |
235ba74f SC |
5674 | *info2 = vmx->idt_vectoring_info; |
5675 | *intr_info = vmx_get_intr_info(vcpu); | |
5676 | if (is_exception_with_error_code(*intr_info)) | |
5677 | *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
5678 | else | |
5679 | *error_code = 0; | |
5680 | } else { | |
5681 | *info2 = 0; | |
5682 | *intr_info = 0; | |
5683 | *error_code = 0; | |
5684 | } | |
ec378aee NHE |
5685 | } |
5686 | ||
55d2375e | 5687 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
27d6c865 | 5688 | { |
55d2375e SC |
5689 | if (vmx->pml_pg) { |
5690 | __free_page(vmx->pml_pg); | |
5691 | vmx->pml_pg = NULL; | |
b8bbab92 | 5692 | } |
27d6c865 NHE |
5693 | } |
5694 | ||
55d2375e | 5695 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
cd232ad0 | 5696 | { |
55d2375e SC |
5697 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5698 | u64 *pml_buf; | |
5699 | u16 pml_idx; | |
cd232ad0 | 5700 | |
55d2375e | 5701 | pml_idx = vmcs_read16(GUEST_PML_INDEX); |
cd232ad0 | 5702 | |
55d2375e SC |
5703 | /* Do nothing if PML buffer is empty */ |
5704 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
5705 | return; | |
cd232ad0 | 5706 | |
55d2375e SC |
5707 | /* PML index always points to next available PML buffer entity */ |
5708 | if (pml_idx >= PML_ENTITY_NUM) | |
5709 | pml_idx = 0; | |
5710 | else | |
5711 | pml_idx++; | |
945679e3 | 5712 | |
55d2375e SC |
5713 | pml_buf = page_address(vmx->pml_pg); |
5714 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
5715 | u64 gpa; | |
945679e3 | 5716 | |
55d2375e SC |
5717 | gpa = pml_buf[pml_idx]; |
5718 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
5719 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); | |
945679e3 VK |
5720 | } |
5721 | ||
55d2375e SC |
5722 | /* reset PML index */ |
5723 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
945679e3 VK |
5724 | } |
5725 | ||
f4160e45 | 5726 | /* |
55d2375e SC |
5727 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. |
5728 | * Called before reporting dirty_bitmap to userspace. | |
f4160e45 | 5729 | */ |
55d2375e | 5730 | static void kvm_flush_pml_buffers(struct kvm *kvm) |
49f705c5 | 5731 | { |
55d2375e SC |
5732 | int i; |
5733 | struct kvm_vcpu *vcpu; | |
49f705c5 | 5734 | /* |
55d2375e SC |
5735 | * We only need to kick vcpu out of guest mode here, as PML buffer |
5736 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
5737 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
5738 | * buffer. | |
49f705c5 | 5739 | */ |
55d2375e SC |
5740 | kvm_for_each_vcpu(i, vcpu, kvm) |
5741 | kvm_vcpu_kick(vcpu); | |
49f705c5 NHE |
5742 | } |
5743 | ||
55d2375e | 5744 | static void vmx_dump_sel(char *name, uint32_t sel) |
49f705c5 | 5745 | { |
55d2375e SC |
5746 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", |
5747 | name, vmcs_read16(sel), | |
5748 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), | |
5749 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
5750 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
49f705c5 NHE |
5751 | } |
5752 | ||
55d2375e | 5753 | static void vmx_dump_dtsel(char *name, uint32_t limit) |
a8bc284e | 5754 | { |
55d2375e SC |
5755 | pr_err("%s limit=0x%08x, base=0x%016lx\n", |
5756 | name, vmcs_read32(limit), | |
5757 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
a8bc284e JM |
5758 | } |
5759 | ||
69090810 | 5760 | void dump_vmcs(void) |
63846663 | 5761 | { |
6f2f8453 PB |
5762 | u32 vmentry_ctl, vmexit_ctl; |
5763 | u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; | |
5764 | unsigned long cr4; | |
63846663 | 5765 | |
6f2f8453 PB |
5766 | if (!dump_invalid_vmcs) { |
5767 | pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); | |
5768 | return; | |
5769 | } | |
5770 | ||
5771 | vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
5772 | vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
5773 | cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5774 | pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
5775 | cr4 = vmcs_readl(GUEST_CR4); | |
6f2f8453 | 5776 | secondary_exec_control = 0; |
55d2375e SC |
5777 | if (cpu_has_secondary_exec_ctrls()) |
5778 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
14c07ad8 | 5779 | |
55d2375e SC |
5780 | pr_err("*** Guest State ***\n"); |
5781 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
5782 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
5783 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
5784 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
5785 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
5786 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
75bc72f0 | 5787 | if (cpu_has_vmx_ept()) { |
55d2375e SC |
5788 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
5789 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
5790 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
5791 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
e9ac033e | 5792 | } |
55d2375e SC |
5793 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", |
5794 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
5795 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
5796 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
5797 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
5798 | vmcs_readl(GUEST_SYSENTER_ESP), | |
5799 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
5800 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
5801 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
5802 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
5803 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
5804 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
5805 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
5806 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
5807 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
5808 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
5809 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
5810 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
5811 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
5812 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", | |
75bc72f0 DE |
5813 | vmcs_read64(GUEST_IA32_EFER), |
5814 | vmcs_read64(GUEST_IA32_PAT)); | |
55d2375e SC |
5815 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", |
5816 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
5817 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); | |
5818 | if (cpu_has_load_perf_global_ctrl() && | |
5819 | vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
5820 | pr_err("PerfGlobCtl = 0x%016llx\n", | |
5821 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
5822 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) | |
5823 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); | |
5824 | pr_err("Interruptibility = %08x ActivityState = %08x\n", | |
5825 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
5826 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
5827 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
5828 | pr_err("InterruptStatus = %04x\n", | |
5829 | vmcs_read16(GUEST_INTR_STATUS)); | |
ff651cb6 | 5830 | |
55d2375e SC |
5831 | pr_err("*** Host State ***\n"); |
5832 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
5833 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
5834 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
5835 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
5836 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
5837 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
5838 | vmcs_read16(HOST_TR_SELECTOR)); | |
5839 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
5840 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
5841 | vmcs_readl(HOST_TR_BASE)); | |
5842 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
5843 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
5844 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
5845 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
5846 | vmcs_readl(HOST_CR4)); | |
5847 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
5848 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
5849 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
5850 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
5851 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
5852 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", | |
5853 | vmcs_read64(HOST_IA32_EFER), | |
5854 | vmcs_read64(HOST_IA32_PAT)); | |
5855 | if (cpu_has_load_perf_global_ctrl() && | |
5856 | vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) | |
5857 | pr_err("PerfGlobCtl = 0x%016llx\n", | |
5858 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
ff651cb6 | 5859 | |
55d2375e SC |
5860 | pr_err("*** Control State ***\n"); |
5861 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
5862 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
5863 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
5864 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
5865 | vmcs_read32(EXCEPTION_BITMAP), | |
5866 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
5867 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
5868 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
5869 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
5870 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
5871 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
5872 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
5873 | vmcs_read32(VM_EXIT_INTR_INFO), | |
5874 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
5875 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
5876 | pr_err(" reason=%08x qualification=%016lx\n", | |
5877 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
5878 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
5879 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
5880 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
5881 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); | |
5882 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) | |
5883 | pr_err("TSC Multiplier = 0x%016llx\n", | |
5884 | vmcs_read64(TSC_MULTIPLIER)); | |
9d609649 PB |
5885 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { |
5886 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { | |
5887 | u16 status = vmcs_read16(GUEST_INTR_STATUS); | |
5888 | pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); | |
5889 | } | |
d6a85c32 | 5890 | pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); |
9d609649 PB |
5891 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) |
5892 | pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); | |
d6a85c32 | 5893 | pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); |
9d609649 | 5894 | } |
55d2375e SC |
5895 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) |
5896 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
5897 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
5898 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); | |
55d2375e SC |
5899 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) |
5900 | pr_err("PLE Gap=%08x Window=%08x\n", | |
5901 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
5902 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
5903 | pr_err("Virtual processor ID = 0x%04x\n", | |
5904 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
ff651cb6 WV |
5905 | } |
5906 | ||
55d2375e SC |
5907 | /* |
5908 | * The guest has exited. See if we can fix it or if we need userspace | |
5909 | * assistance. | |
5910 | */ | |
404d5d7b | 5911 | static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath) |
ff651cb6 | 5912 | { |
55d2375e | 5913 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a6bdda1f | 5914 | union vmx_exit_reason exit_reason = vmx->exit_reason; |
55d2375e | 5915 | u32 vectoring_info = vmx->idt_vectoring_info; |
a6bdda1f | 5916 | u16 exit_handler_index; |
ff651cb6 | 5917 | |
55d2375e SC |
5918 | /* |
5919 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
5920 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
5921 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
5922 | * mode as if vcpus is in root mode, the PML buffer must has been | |
5923 | * flushed already. | |
5924 | */ | |
5925 | if (enable_pml) | |
5926 | vmx_flush_pml_buffer(vcpu); | |
1dc35dac | 5927 | |
db438592 SC |
5928 | /* |
5929 | * We should never reach this point with a pending nested VM-Enter, and | |
5930 | * more specifically emulation of L2 due to invalid guest state (see | |
5931 | * below) should never happen as that means we incorrectly allowed a | |
5932 | * nested VM-Enter with an invalid vmcs12. | |
5933 | */ | |
5934 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
5935 | ||
55d2375e SC |
5936 | /* If guest state is invalid, start emulating */ |
5937 | if (vmx->emulation_required) | |
5938 | return handle_invalid_guest_state(vcpu); | |
1dc35dac | 5939 | |
96b100cd PB |
5940 | if (is_guest_mode(vcpu)) { |
5941 | /* | |
5942 | * The host physical addresses of some pages of guest memory | |
5943 | * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC | |
5944 | * Page). The CPU may write to these pages via their host | |
5945 | * physical address while L2 is running, bypassing any | |
5946 | * address-translation-based dirty tracking (e.g. EPT write | |
5947 | * protection). | |
5948 | * | |
5949 | * Mark them dirty on every exit from L2 to prevent them from | |
5950 | * getting out of sync with dirty tracking. | |
5951 | */ | |
5952 | nested_mark_vmcs12_pages_dirty(vcpu); | |
5953 | ||
f47baaed | 5954 | if (nested_vmx_reflect_vmexit(vcpu)) |
789afc5c | 5955 | return 1; |
96b100cd | 5956 | } |
9ed38ffa | 5957 | |
a6bdda1f | 5958 | if (exit_reason.failed_vmentry) { |
55d2375e SC |
5959 | dump_vmcs(); |
5960 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
5961 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
a6bdda1f | 5962 | = exit_reason.full; |
8a14fe4f | 5963 | vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu; |
55d2375e | 5964 | return 0; |
9ed38ffa LP |
5965 | } |
5966 | ||
55d2375e | 5967 | if (unlikely(vmx->fail)) { |
3b20e03a | 5968 | dump_vmcs(); |
55d2375e SC |
5969 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
5970 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
5971 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
8a14fe4f | 5972 | vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu; |
55d2375e SC |
5973 | return 0; |
5974 | } | |
50c28f21 | 5975 | |
55d2375e SC |
5976 | /* |
5977 | * Note: | |
5978 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
5979 | * delivery event since it indicates guest is accessing MMIO. | |
5980 | * The vm-exit can be triggered again after return to guest that | |
5981 | * will cause infinite loop. | |
5982 | */ | |
5983 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && | |
a6bdda1f SC |
5984 | (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI && |
5985 | exit_reason.basic != EXIT_REASON_EPT_VIOLATION && | |
5986 | exit_reason.basic != EXIT_REASON_PML_FULL && | |
5987 | exit_reason.basic != EXIT_REASON_APIC_ACCESS && | |
5988 | exit_reason.basic != EXIT_REASON_TASK_SWITCH)) { | |
d2be95d4 RW |
5989 | int ndata = 3; |
5990 | ||
55d2375e SC |
5991 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5992 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
55d2375e | 5993 | vcpu->run->internal.data[0] = vectoring_info; |
a6bdda1f | 5994 | vcpu->run->internal.data[1] = exit_reason.full; |
55d2375e | 5995 | vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; |
a6bdda1f | 5996 | if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) { |
d2be95d4 | 5997 | vcpu->run->internal.data[ndata++] = |
55d2375e SC |
5998 | vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
5999 | } | |
d2be95d4 RW |
6000 | vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu; |
6001 | vcpu->run->internal.ndata = ndata; | |
55d2375e SC |
6002 | return 0; |
6003 | } | |
50c28f21 | 6004 | |
55d2375e SC |
6005 | if (unlikely(!enable_vnmi && |
6006 | vmx->loaded_vmcs->soft_vnmi_blocked)) { | |
db438592 | 6007 | if (!vmx_interrupt_blocked(vcpu)) { |
55d2375e SC |
6008 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; |
6009 | } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && | |
6010 | vcpu->arch.nmi_pending) { | |
6011 | /* | |
6012 | * This CPU don't support us in finding the end of an | |
6013 | * NMI-blocked window if the guest runs with IRQs | |
6014 | * disabled. So we pull the trigger after 1 s of | |
6015 | * futile waiting, but inform the user about this. | |
6016 | */ | |
6017 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
6018 | "state on VCPU %d after 1 s timeout\n", | |
6019 | __func__, vcpu->vcpu_id); | |
6020 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
6021 | } | |
6022 | } | |
50c28f21 | 6023 | |
404d5d7b | 6024 | if (exit_fastpath != EXIT_FASTPATH_NONE) |
1e9e2622 | 6025 | return 1; |
c926f2f7 | 6026 | |
a6bdda1f | 6027 | if (exit_reason.basic >= kvm_vmx_max_exit_handlers) |
c926f2f7 | 6028 | goto unexpected_vmexit; |
4289d272 | 6029 | #ifdef CONFIG_RETPOLINE |
a6bdda1f | 6030 | if (exit_reason.basic == EXIT_REASON_MSR_WRITE) |
c926f2f7 | 6031 | return kvm_emulate_wrmsr(vcpu); |
a6bdda1f | 6032 | else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER) |
c926f2f7 | 6033 | return handle_preemption_timer(vcpu); |
a6bdda1f | 6034 | else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW) |
c926f2f7 | 6035 | return handle_interrupt_window(vcpu); |
a6bdda1f | 6036 | else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT) |
c926f2f7 | 6037 | return handle_external_interrupt(vcpu); |
a6bdda1f | 6038 | else if (exit_reason.basic == EXIT_REASON_HLT) |
c926f2f7 | 6039 | return kvm_emulate_halt(vcpu); |
a6bdda1f | 6040 | else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) |
c926f2f7 | 6041 | return handle_ept_misconfig(vcpu); |
4289d272 | 6042 | #endif |
c926f2f7 | 6043 | |
a6bdda1f SC |
6044 | exit_handler_index = array_index_nospec((u16)exit_reason.basic, |
6045 | kvm_vmx_max_exit_handlers); | |
6046 | if (!kvm_vmx_exit_handlers[exit_handler_index]) | |
c926f2f7 MP |
6047 | goto unexpected_vmexit; |
6048 | ||
a6bdda1f | 6049 | return kvm_vmx_exit_handlers[exit_handler_index](vcpu); |
c926f2f7 MP |
6050 | |
6051 | unexpected_vmexit: | |
a6bdda1f SC |
6052 | vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", |
6053 | exit_reason.full); | |
c926f2f7 MP |
6054 | dump_vmcs(); |
6055 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6056 | vcpu->run->internal.suberror = | |
7396d337 | 6057 | KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; |
1aa561b1 | 6058 | vcpu->run->internal.ndata = 2; |
a6bdda1f | 6059 | vcpu->run->internal.data[0] = exit_reason.full; |
8a14fe4f | 6060 | vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu; |
c926f2f7 | 6061 | return 0; |
9ed38ffa LP |
6062 | } |
6063 | ||
efebf0aa | 6064 | /* |
55d2375e SC |
6065 | * Software based L1D cache flush which is used when microcode providing |
6066 | * the cache control MSR is not loaded. | |
efebf0aa | 6067 | * |
55d2375e SC |
6068 | * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to |
6069 | * flush it is required to read in 64 KiB because the replacement algorithm | |
6070 | * is not exactly LRU. This could be sized at runtime via topology | |
6071 | * information but as all relevant affected CPUs have 32KiB L1D cache size | |
6072 | * there is no point in doing so. | |
efebf0aa | 6073 | */ |
3ebccdf3 | 6074 | static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu) |
fe3ef05c | 6075 | { |
55d2375e | 6076 | int size = PAGE_SIZE << L1D_CACHE_ORDER; |
25a2e4fe PB |
6077 | |
6078 | /* | |
55d2375e SC |
6079 | * This code is only executed when the the flush mode is 'cond' or |
6080 | * 'always' | |
25a2e4fe | 6081 | */ |
55d2375e SC |
6082 | if (static_branch_likely(&vmx_l1d_flush_cond)) { |
6083 | bool flush_l1d; | |
25a2e4fe | 6084 | |
55d2375e SC |
6085 | /* |
6086 | * Clear the per-vcpu flush bit, it gets set again | |
6087 | * either from vcpu_run() or from one of the unsafe | |
6088 | * VMEXIT handlers. | |
6089 | */ | |
6090 | flush_l1d = vcpu->arch.l1tf_flush_l1d; | |
6091 | vcpu->arch.l1tf_flush_l1d = false; | |
25a2e4fe | 6092 | |
55d2375e SC |
6093 | /* |
6094 | * Clear the per-cpu flush bit, it gets set again from | |
6095 | * the interrupt handlers. | |
6096 | */ | |
6097 | flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); | |
6098 | kvm_clear_cpu_l1tf_flush_l1d(); | |
25a2e4fe | 6099 | |
55d2375e SC |
6100 | if (!flush_l1d) |
6101 | return; | |
6102 | } | |
09abe320 | 6103 | |
55d2375e | 6104 | vcpu->stat.l1d_flush++; |
25a2e4fe | 6105 | |
55d2375e | 6106 | if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { |
3ebccdf3 | 6107 | native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); |
55d2375e SC |
6108 | return; |
6109 | } | |
25a2e4fe | 6110 | |
55d2375e SC |
6111 | asm volatile( |
6112 | /* First ensure the pages are in the TLB */ | |
6113 | "xorl %%eax, %%eax\n" | |
6114 | ".Lpopulate_tlb:\n\t" | |
6115 | "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" | |
6116 | "addl $4096, %%eax\n\t" | |
6117 | "cmpl %%eax, %[size]\n\t" | |
6118 | "jne .Lpopulate_tlb\n\t" | |
6119 | "xorl %%eax, %%eax\n\t" | |
6120 | "cpuid\n\t" | |
6121 | /* Now fill the cache */ | |
6122 | "xorl %%eax, %%eax\n" | |
6123 | ".Lfill_cache:\n" | |
6124 | "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" | |
6125 | "addl $64, %%eax\n\t" | |
6126 | "cmpl %%eax, %[size]\n\t" | |
6127 | "jne .Lfill_cache\n\t" | |
6128 | "lfence\n" | |
6129 | :: [flush_pages] "r" (vmx_l1d_flush_pages), | |
6130 | [size] "r" (size) | |
6131 | : "eax", "ebx", "ecx", "edx"); | |
09abe320 | 6132 | } |
25a2e4fe | 6133 | |
55d2375e | 6134 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
09abe320 | 6135 | { |
55d2375e | 6136 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
132f4f7e | 6137 | int tpr_threshold; |
09abe320 | 6138 | |
55d2375e SC |
6139 | if (is_guest_mode(vcpu) && |
6140 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
6141 | return; | |
25a2e4fe | 6142 | |
132f4f7e | 6143 | tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; |
02d496cf LA |
6144 | if (is_guest_mode(vcpu)) |
6145 | to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; | |
6146 | else | |
6147 | vmcs_write32(TPR_THRESHOLD, tpr_threshold); | |
8665c3f9 PB |
6148 | } |
6149 | ||
55d2375e | 6150 | void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) |
8665c3f9 | 6151 | { |
fe7f895d | 6152 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
55d2375e | 6153 | u32 sec_exec_control; |
8665c3f9 | 6154 | |
55d2375e SC |
6155 | if (!lapic_in_kernel(vcpu)) |
6156 | return; | |
9314006d | 6157 | |
55d2375e SC |
6158 | if (!flexpriority_enabled && |
6159 | !cpu_has_vmx_virtualize_x2apic_mode()) | |
6160 | return; | |
705699a1 | 6161 | |
55d2375e SC |
6162 | /* Postpone execution until vmcs01 is the current VMCS. */ |
6163 | if (is_guest_mode(vcpu)) { | |
fe7f895d | 6164 | vmx->nested.change_vmcs01_virtual_apic_mode = true; |
55d2375e | 6165 | return; |
6beb7bd5 | 6166 | } |
fe3ef05c | 6167 | |
fe7f895d | 6168 | sec_exec_control = secondary_exec_controls_get(vmx); |
55d2375e SC |
6169 | sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
6170 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
09abe320 | 6171 | |
55d2375e SC |
6172 | switch (kvm_get_apic_mode(vcpu)) { |
6173 | case LAPIC_MODE_INVALID: | |
6174 | WARN_ONCE(true, "Invalid local APIC state"); | |
6175 | case LAPIC_MODE_DISABLED: | |
6176 | break; | |
6177 | case LAPIC_MODE_XAPIC: | |
6178 | if (flexpriority_enabled) { | |
6179 | sec_exec_control |= | |
6180 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
4de1f9d4 SC |
6181 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6182 | ||
6183 | /* | |
6184 | * Flush the TLB, reloading the APIC access page will | |
6185 | * only do so if its physical address has changed, but | |
6186 | * the guest may have inserted a non-APIC mapping into | |
6187 | * the TLB while the APIC access page was disabled. | |
6188 | */ | |
6189 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
55d2375e SC |
6190 | } |
6191 | break; | |
6192 | case LAPIC_MODE_X2APIC: | |
6193 | if (cpu_has_vmx_virtualize_x2apic_mode()) | |
6194 | sec_exec_control |= | |
6195 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
6196 | break; | |
09abe320 | 6197 | } |
fe7f895d | 6198 | secondary_exec_controls_set(vmx, sec_exec_control); |
09abe320 | 6199 | |
55d2375e SC |
6200 | vmx_update_msr_bitmap(vcpu); |
6201 | } | |
0238ea91 | 6202 | |
a4148b7c | 6203 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu) |
55d2375e | 6204 | { |
a4148b7c SC |
6205 | struct page *page; |
6206 | ||
1196cb97 SC |
6207 | /* Defer reload until vmcs01 is the current VMCS. */ |
6208 | if (is_guest_mode(vcpu)) { | |
6209 | to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true; | |
6210 | return; | |
55d2375e | 6211 | } |
1196cb97 | 6212 | |
4de1f9d4 SC |
6213 | if (!(secondary_exec_controls_get(to_vmx(vcpu)) & |
6214 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
6215 | return; | |
6216 | ||
a4148b7c SC |
6217 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
6218 | if (is_error_page(page)) | |
6219 | return; | |
6220 | ||
6221 | vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page)); | |
1196cb97 | 6222 | vmx_flush_tlb_current(vcpu); |
a4148b7c SC |
6223 | |
6224 | /* | |
6225 | * Do not pin apic access page in memory, the MMU notifier | |
6226 | * will call us again if it is migrated or swapped out. | |
6227 | */ | |
6228 | put_page(page); | |
55d2375e | 6229 | } |
fe3ef05c | 6230 | |
55d2375e SC |
6231 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
6232 | { | |
6233 | u16 status; | |
6234 | u8 old; | |
32c7acf0 | 6235 | |
55d2375e SC |
6236 | if (max_isr == -1) |
6237 | max_isr = 0; | |
608406e2 | 6238 | |
55d2375e SC |
6239 | status = vmcs_read16(GUEST_INTR_STATUS); |
6240 | old = status >> 8; | |
6241 | if (max_isr != old) { | |
6242 | status &= 0xff; | |
6243 | status |= max_isr << 8; | |
6244 | vmcs_write16(GUEST_INTR_STATUS, status); | |
6245 | } | |
6246 | } | |
6beb7bd5 | 6247 | |
55d2375e SC |
6248 | static void vmx_set_rvi(int vector) |
6249 | { | |
6250 | u16 status; | |
6251 | u8 old; | |
0b665d30 | 6252 | |
55d2375e SC |
6253 | if (vector == -1) |
6254 | vector = 0; | |
fe3ef05c | 6255 | |
55d2375e SC |
6256 | status = vmcs_read16(GUEST_INTR_STATUS); |
6257 | old = (u8)status & 0xff; | |
6258 | if ((u8)vector != old) { | |
6259 | status &= ~0xff; | |
6260 | status |= (u8)vector; | |
6261 | vmcs_write16(GUEST_INTR_STATUS, status); | |
09abe320 | 6262 | } |
55d2375e | 6263 | } |
09abe320 | 6264 | |
55d2375e SC |
6265 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) |
6266 | { | |
09abe320 | 6267 | /* |
55d2375e SC |
6268 | * When running L2, updating RVI is only relevant when |
6269 | * vmcs12 virtual-interrupt-delivery enabled. | |
6270 | * However, it can be enabled only when L1 also | |
6271 | * intercepts external-interrupts and in that case | |
6272 | * we should not update vmcs02 RVI but instead intercept | |
6273 | * interrupt. Therefore, do nothing when running L2. | |
fe3ef05c | 6274 | */ |
55d2375e SC |
6275 | if (!is_guest_mode(vcpu)) |
6276 | vmx_set_rvi(max_irr); | |
6277 | } | |
fe3ef05c | 6278 | |
55d2375e SC |
6279 | static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
6280 | { | |
6281 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6282 | int max_irr; | |
6283 | bool max_irr_updated; | |
a7c0b07d | 6284 | |
55d2375e SC |
6285 | WARN_ON(!vcpu->arch.apicv_active); |
6286 | if (pi_test_on(&vmx->pi_desc)) { | |
6287 | pi_clear_on(&vmx->pi_desc); | |
6288 | /* | |
d9ff2744 | 6289 | * IOMMU can write to PID.ON, so the barrier matters even on UP. |
55d2375e SC |
6290 | * But on x86 this is just a compiler barrier anyway. |
6291 | */ | |
6292 | smp_mb__after_atomic(); | |
6293 | max_irr_updated = | |
6294 | kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); | |
c4ebd629 VK |
6295 | |
6296 | /* | |
55d2375e SC |
6297 | * If we are running L2 and L1 has a new pending interrupt |
6298 | * which can be injected, we should re-evaluate | |
6299 | * what should be done with this new L1 interrupt. | |
6300 | * If L1 intercepts external-interrupts, we should | |
6301 | * exit from L2 to L1. Otherwise, interrupt should be | |
6302 | * delivered directly to L2. | |
c4ebd629 | 6303 | */ |
55d2375e SC |
6304 | if (is_guest_mode(vcpu) && max_irr_updated) { |
6305 | if (nested_exit_on_intr(vcpu)) | |
6306 | kvm_vcpu_exiting_guest_mode(vcpu); | |
6307 | else | |
6308 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
c4ebd629 | 6309 | } |
55d2375e SC |
6310 | } else { |
6311 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
a7c0b07d | 6312 | } |
55d2375e SC |
6313 | vmx_hwapic_irr_update(vcpu, max_irr); |
6314 | return max_irr; | |
6315 | } | |
a7c0b07d | 6316 | |
55d2375e SC |
6317 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
6318 | { | |
6319 | if (!kvm_vcpu_apicv_active(vcpu)) | |
6320 | return; | |
25a2e4fe | 6321 | |
55d2375e SC |
6322 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
6323 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
6324 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
6325 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
8665c3f9 PB |
6326 | } |
6327 | ||
55d2375e | 6328 | static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) |
8665c3f9 PB |
6329 | { |
6330 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9d1887ef | 6331 | |
55d2375e SC |
6332 | pi_clear_on(&vmx->pi_desc); |
6333 | memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); | |
6334 | } | |
8665c3f9 | 6335 | |
535f7ef2 SC |
6336 | void vmx_do_interrupt_nmi_irqoff(unsigned long entry); |
6337 | ||
8c99fa01 LJ |
6338 | static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu, |
6339 | unsigned long entry) | |
1a5488ef | 6340 | { |
1a5488ef | 6341 | kvm_before_interrupt(vcpu); |
8c99fa01 | 6342 | vmx_do_interrupt_nmi_irqoff(entry); |
1a5488ef SC |
6343 | kvm_after_interrupt(vcpu); |
6344 | } | |
6345 | ||
95b5a48c | 6346 | static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) |
55d2375e | 6347 | { |
8c99fa01 | 6348 | const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist; |
87915858 | 6349 | u32 intr_info = vmx_get_intr_info(&vmx->vcpu); |
fe3ef05c | 6350 | |
55d2375e | 6351 | /* if exit due to PF check for async PF */ |
1a5488ef | 6352 | if (is_page_fault(intr_info)) |
68fd66f1 | 6353 | vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags(); |
55d2375e | 6354 | /* Handle machine checks before interrupts are enabled */ |
1a5488ef | 6355 | else if (is_machine_check(intr_info)) |
55d2375e | 6356 | kvm_machine_check(); |
55d2375e | 6357 | /* We need to handle NMIs before interrupts are enabled */ |
1a5488ef | 6358 | else if (is_nmi(intr_info)) |
8c99fa01 | 6359 | handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry); |
55d2375e | 6360 | } |
fe3ef05c | 6361 | |
95b5a48c | 6362 | static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) |
55d2375e | 6363 | { |
87915858 | 6364 | u32 intr_info = vmx_get_intr_info(vcpu); |
8c99fa01 LJ |
6365 | unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK; |
6366 | gate_desc *desc = (gate_desc *)host_idt_base + vector; | |
fe3ef05c | 6367 | |
49def500 SC |
6368 | if (WARN_ONCE(!is_external_intr(intr_info), |
6369 | "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) | |
6370 | return; | |
6371 | ||
8c99fa01 | 6372 | handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc)); |
55d2375e | 6373 | } |
95b5a48c | 6374 | |
a9ab13ff | 6375 | static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu) |
95b5a48c SC |
6376 | { |
6377 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6378 | ||
a6bdda1f | 6379 | if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT) |
95b5a48c | 6380 | handle_external_interrupt_irqoff(vcpu); |
a6bdda1f | 6381 | else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI) |
95b5a48c SC |
6382 | handle_exception_nmi_irqoff(vmx); |
6383 | } | |
5a6a9748 | 6384 | |
5719455f TL |
6385 | /* |
6386 | * The kvm parameter can be NULL (module initialization, or invocation before | |
6387 | * VM creation). Be sure to check the kvm parameter before using it. | |
6388 | */ | |
6389 | static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index) | |
55d2375e SC |
6390 | { |
6391 | switch (index) { | |
6392 | case MSR_IA32_SMBASE: | |
6393 | /* | |
6394 | * We cannot do SMM unless we can run the guest in big | |
6395 | * real mode. | |
6396 | */ | |
6397 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
95c5c7c7 PB |
6398 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: |
6399 | return nested; | |
55d2375e SC |
6400 | case MSR_AMD64_VIRT_SPEC_CTRL: |
6401 | /* This is AMD only. */ | |
6402 | return false; | |
6403 | default: | |
6404 | return true; | |
3184a995 | 6405 | } |
55d2375e | 6406 | } |
2bb8cafe | 6407 | |
55d2375e SC |
6408 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
6409 | { | |
6410 | u32 exit_intr_info; | |
6411 | bool unblock_nmi; | |
6412 | u8 vector; | |
6413 | bool idtv_info_valid; | |
7ca29de2 | 6414 | |
55d2375e | 6415 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; |
feaf0c7d | 6416 | |
55d2375e SC |
6417 | if (enable_vnmi) { |
6418 | if (vmx->loaded_vmcs->nmi_known_unmasked) | |
6419 | return; | |
87915858 SC |
6420 | |
6421 | exit_intr_info = vmx_get_intr_info(&vmx->vcpu); | |
55d2375e SC |
6422 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
6423 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
6424 | /* | |
6425 | * SDM 3: 27.7.1.2 (September 2008) | |
6426 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
6427 | * a guest IRET fault. | |
6428 | * SDM 3: 23.2.2 (September 2008) | |
6429 | * Bit 12 is undefined in any of the following cases: | |
6430 | * If the VM exit sets the valid bit in the IDT-vectoring | |
6431 | * information field. | |
6432 | * If the VM exit is due to a double fault. | |
6433 | */ | |
6434 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && | |
6435 | vector != DF_VECTOR && !idtv_info_valid) | |
6436 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
6437 | GUEST_INTR_STATE_NMI); | |
6438 | else | |
6439 | vmx->loaded_vmcs->nmi_known_unmasked = | |
6440 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
6441 | & GUEST_INTR_STATE_NMI); | |
6442 | } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) | |
6443 | vmx->loaded_vmcs->vnmi_blocked_time += | |
6444 | ktime_to_ns(ktime_sub(ktime_get(), | |
6445 | vmx->loaded_vmcs->entry_time)); | |
fe3ef05c NHE |
6446 | } |
6447 | ||
55d2375e SC |
6448 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
6449 | u32 idt_vectoring_info, | |
6450 | int instr_len_field, | |
6451 | int error_code_field) | |
0c7f650e | 6452 | { |
55d2375e SC |
6453 | u8 vector; |
6454 | int type; | |
6455 | bool idtv_info_valid; | |
0c7f650e | 6456 | |
55d2375e | 6457 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; |
0c7f650e | 6458 | |
55d2375e SC |
6459 | vcpu->arch.nmi_injected = false; |
6460 | kvm_clear_exception_queue(vcpu); | |
6461 | kvm_clear_interrupt_queue(vcpu); | |
27c42a1b | 6462 | |
55d2375e SC |
6463 | if (!idtv_info_valid) |
6464 | return; | |
c7c2c709 | 6465 | |
55d2375e | 6466 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
ca0bde28 | 6467 | |
55d2375e SC |
6468 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
6469 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
64a919f7 | 6470 | |
55d2375e SC |
6471 | switch (type) { |
6472 | case INTR_TYPE_NMI_INTR: | |
6473 | vcpu->arch.nmi_injected = true; | |
6474 | /* | |
6475 | * SDM 3: 27.7.1.2 (September 2008) | |
6476 | * Clear bit "block by NMI" before VM entry if a NMI | |
6477 | * delivery faulted. | |
6478 | */ | |
6479 | vmx_set_nmi_mask(vcpu, false); | |
6480 | break; | |
6481 | case INTR_TYPE_SOFT_EXCEPTION: | |
6482 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); | |
df561f66 | 6483 | fallthrough; |
55d2375e SC |
6484 | case INTR_TYPE_HARD_EXCEPTION: |
6485 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { | |
6486 | u32 err = vmcs_read32(error_code_field); | |
6487 | kvm_requeue_exception_e(vcpu, vector, err); | |
6488 | } else | |
6489 | kvm_requeue_exception(vcpu, vector); | |
6490 | break; | |
6491 | case INTR_TYPE_SOFT_INTR: | |
6492 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); | |
df561f66 | 6493 | fallthrough; |
55d2375e SC |
6494 | case INTR_TYPE_EXT_INTR: |
6495 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); | |
6496 | break; | |
6497 | default: | |
6498 | break; | |
0447378a | 6499 | } |
ca0bde28 JM |
6500 | } |
6501 | ||
55d2375e | 6502 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
f145d90d | 6503 | { |
55d2375e SC |
6504 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
6505 | VM_EXIT_INSTRUCTION_LEN, | |
6506 | IDT_VECTORING_ERROR_CODE); | |
f145d90d LA |
6507 | } |
6508 | ||
55d2375e | 6509 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
ca0bde28 | 6510 | { |
55d2375e SC |
6511 | __vmx_complete_interrupts(vcpu, |
6512 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
6513 | VM_ENTRY_INSTRUCTION_LEN, | |
6514 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
f1b026a3 | 6515 | |
55d2375e | 6516 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); |
ca0bde28 JM |
6517 | } |
6518 | ||
55d2375e | 6519 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
52017608 | 6520 | { |
55d2375e SC |
6521 | int i, nr_msrs; |
6522 | struct perf_guest_switch_msr *msrs; | |
7c177938 | 6523 | |
55d2375e | 6524 | msrs = perf_guest_get_msrs(&nr_msrs); |
384bb783 | 6525 | |
55d2375e SC |
6526 | if (!msrs) |
6527 | return; | |
f1b026a3 | 6528 | |
55d2375e SC |
6529 | for (i = 0; i < nr_msrs; i++) |
6530 | if (msrs[i].host == msrs[i].guest) | |
6531 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
6532 | else | |
6533 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
6534 | msrs[i].host, false); | |
ca0bde28 | 6535 | } |
52017608 | 6536 | |
55d2375e | 6537 | static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) |
858e25c0 JM |
6538 | { |
6539 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
55d2375e SC |
6540 | u64 tscl; |
6541 | u32 delta_tsc; | |
52017608 | 6542 | |
55d2375e | 6543 | if (vmx->req_immediate_exit) { |
804939ea SC |
6544 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); |
6545 | vmx->loaded_vmcs->hv_timer_soft_disabled = false; | |
6546 | } else if (vmx->hv_deadline_tsc != -1) { | |
55d2375e SC |
6547 | tscl = rdtsc(); |
6548 | if (vmx->hv_deadline_tsc > tscl) | |
6549 | /* set_hv_timer ensures the delta fits in 32-bits */ | |
6550 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
6551 | cpu_preemption_timer_multi); | |
6552 | else | |
6553 | delta_tsc = 0; | |
858e25c0 | 6554 | |
804939ea SC |
6555 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); |
6556 | vmx->loaded_vmcs->hv_timer_soft_disabled = false; | |
6557 | } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { | |
6558 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); | |
6559 | vmx->loaded_vmcs->hv_timer_soft_disabled = true; | |
7f7f1ba3 | 6560 | } |
858e25c0 JM |
6561 | } |
6562 | ||
3ebccdf3 | 6563 | void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) |
ca0bde28 | 6564 | { |
c09b03eb SC |
6565 | if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { |
6566 | vmx->loaded_vmcs->host_state.rsp = host_rsp; | |
6567 | vmcs_writel(HOST_RSP, host_rsp); | |
6568 | } | |
5ad6ece8 | 6569 | } |
5f3d5799 | 6570 | |
404d5d7b | 6571 | static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu) |
dcf068da | 6572 | { |
a6bdda1f | 6573 | switch (to_vmx(vcpu)->exit_reason.basic) { |
dcf068da WL |
6574 | case EXIT_REASON_MSR_WRITE: |
6575 | return handle_fastpath_set_msr_irqoff(vcpu); | |
26efe2fd WL |
6576 | case EXIT_REASON_PREEMPTION_TIMER: |
6577 | return handle_fastpath_preemption_timer(vcpu); | |
dcf068da WL |
6578 | default: |
6579 | return EXIT_FASTPATH_NONE; | |
6580 | } | |
6581 | } | |
6582 | ||
fc2ba5a2 | 6583 | bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); |
5ad6ece8 | 6584 | |
3ebccdf3 TG |
6585 | static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu, |
6586 | struct vcpu_vmx *vmx) | |
6587 | { | |
6588 | /* | |
6589 | * VMENTER enables interrupts (host state), but the kernel state is | |
6590 | * interrupts disabled when this is invoked. Also tell RCU about | |
6591 | * it. This is the same logic as for exit_to_user_mode(). | |
6592 | * | |
6593 | * This ensures that e.g. latency analysis on the host observes | |
6594 | * guest mode as interrupt enabled. | |
6595 | * | |
6596 | * guest_enter_irqoff() informs context tracking about the | |
6597 | * transition to guest mode and if enabled adjusts RCU state | |
6598 | * accordingly. | |
6599 | */ | |
6600 | instrumentation_begin(); | |
6601 | trace_hardirqs_on_prepare(); | |
6602 | lockdep_hardirqs_on_prepare(CALLER_ADDR0); | |
6603 | instrumentation_end(); | |
6604 | ||
6605 | guest_enter_irqoff(); | |
6606 | lockdep_hardirqs_on(CALLER_ADDR0); | |
6607 | ||
6608 | /* L1D Flush includes CPU buffer clear to mitigate MDS */ | |
6609 | if (static_branch_unlikely(&vmx_l1d_should_flush)) | |
6610 | vmx_l1d_flush(vcpu); | |
6611 | else if (static_branch_unlikely(&mds_user_clear)) | |
6612 | mds_clear_cpu_buffers(); | |
6613 | ||
2245d398 TG |
6614 | if (vcpu->arch.cr2 != native_read_cr2()) |
6615 | native_write_cr2(vcpu->arch.cr2); | |
3ebccdf3 TG |
6616 | |
6617 | vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, | |
6618 | vmx->loaded_vmcs->launched); | |
6619 | ||
2245d398 | 6620 | vcpu->arch.cr2 = native_read_cr2(); |
3ebccdf3 TG |
6621 | |
6622 | /* | |
6623 | * VMEXIT disables interrupts (host state), but tracing and lockdep | |
6624 | * have them in state 'on' as recorded before entering guest mode. | |
6625 | * Same as enter_from_user_mode(). | |
6626 | * | |
6627 | * guest_exit_irqoff() restores host context and reinstates RCU if | |
6628 | * enabled and required. | |
6629 | * | |
6630 | * This needs to be done before the below as native_read_msr() | |
6631 | * contains a tracepoint and x86_spec_ctrl_restore_host() calls | |
6632 | * into world and some more. | |
6633 | */ | |
6634 | lockdep_hardirqs_off(CALLER_ADDR0); | |
6635 | guest_exit_irqoff(); | |
6636 | ||
6637 | instrumentation_begin(); | |
6638 | trace_hardirqs_off_finish(); | |
6639 | instrumentation_end(); | |
6640 | } | |
6641 | ||
404d5d7b | 6642 | static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu) |
5ad6ece8 | 6643 | { |
404d5d7b | 6644 | fastpath_t exit_fastpath; |
5ad6ece8 SC |
6645 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6646 | unsigned long cr3, cr4; | |
6647 | ||
404d5d7b | 6648 | reenter_guest: |
5ad6ece8 SC |
6649 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
6650 | if (unlikely(!enable_vnmi && | |
6651 | vmx->loaded_vmcs->soft_vnmi_blocked)) | |
6652 | vmx->loaded_vmcs->entry_time = ktime_get(); | |
6653 | ||
6654 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
6655 | start emulation until we arrive back to a valid state */ | |
6656 | if (vmx->emulation_required) | |
a9ab13ff | 6657 | return EXIT_FASTPATH_NONE; |
5ad6ece8 | 6658 | |
d95df951 LB |
6659 | trace_kvm_entry(vcpu); |
6660 | ||
5ad6ece8 SC |
6661 | if (vmx->ple_window_dirty) { |
6662 | vmx->ple_window_dirty = false; | |
6663 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
6664 | } | |
6665 | ||
c9dfd3fb | 6666 | /* |
6667 | * We did this in prepare_switch_to_guest, because it needs to | |
6668 | * be within srcu_read_lock. | |
6669 | */ | |
6670 | WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync); | |
5ad6ece8 | 6671 | |
cb3c1e2f | 6672 | if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) |
5ad6ece8 | 6673 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); |
cb3c1e2f | 6674 | if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) |
5ad6ece8 SC |
6675 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); |
6676 | ||
6677 | cr3 = __get_current_cr3_fast(); | |
6678 | if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { | |
6679 | vmcs_writel(HOST_CR3, cr3); | |
6680 | vmx->loaded_vmcs->host_state.cr3 = cr3; | |
6681 | } | |
6682 | ||
6683 | cr4 = cr4_read_shadow(); | |
6684 | if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { | |
6685 | vmcs_writel(HOST_CR4, cr4); | |
6686 | vmx->loaded_vmcs->host_state.cr4 = cr4; | |
6687 | } | |
6688 | ||
6689 | /* When single-stepping over STI and MOV SS, we must clear the | |
6690 | * corresponding interruptibility bits in the guest state. Otherwise | |
6691 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
6692 | * exceptions being set, but that's not correct for the guest debugging | |
6693 | * case. */ | |
6694 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
6695 | vmx_set_interrupt_shadow(vcpu, 0); | |
6696 | ||
139a12cf | 6697 | kvm_load_guest_xsave_state(vcpu); |
1811d979 | 6698 | |
5ad6ece8 SC |
6699 | pt_guest_enter(vmx); |
6700 | ||
49097762 | 6701 | atomic_switch_perf_msrs(vmx); |
5ad6ece8 | 6702 | |
804939ea SC |
6703 | if (enable_preemption_timer) |
6704 | vmx_update_hv_timer(vcpu); | |
5ad6ece8 | 6705 | |
010fd37f | 6706 | kvm_wait_lapic_expire(vcpu); |
b6c4bc65 | 6707 | |
5ad6ece8 SC |
6708 | /* |
6709 | * If this vCPU has touched SPEC_CTRL, restore the guest's value if | |
6710 | * it's non-zero. Since vmentry is serialising on affected CPUs, there | |
6711 | * is no need to worry about the conditional branch over the wrmsr | |
6712 | * being speculatively taken. | |
6713 | */ | |
6714 | x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); | |
6715 | ||
3ebccdf3 TG |
6716 | /* The actual VMENTER/EXIT is in the .noinstr.text section. */ |
6717 | vmx_vcpu_enter_exit(vcpu, vmx); | |
b6b8a145 | 6718 | |
55d2375e SC |
6719 | /* |
6720 | * We do not use IBRS in the kernel. If this vCPU has used the | |
6721 | * SPEC_CTRL MSR it may have left it on; save the value and | |
6722 | * turn it off. This is much more efficient than blindly adding | |
6723 | * it to the atomic save/restore list. Especially as the former | |
6724 | * (Saving guest MSRs on vmexit) doesn't even exist in KVM. | |
6725 | * | |
6726 | * For non-nested case: | |
6727 | * If the L01 MSR bitmap does not intercept the MSR, then we need to | |
6728 | * save it. | |
6729 | * | |
6730 | * For nested case: | |
6731 | * If the L02 MSR bitmap does not intercept the MSR, then we need to | |
6732 | * save it. | |
6733 | */ | |
6734 | if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) | |
6735 | vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); | |
b6b8a145 | 6736 | |
55d2375e | 6737 | x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); |
d264ee0c | 6738 | |
55d2375e SC |
6739 | /* All fields are clean at this point */ |
6740 | if (static_branch_unlikely(&enable_evmcs)) | |
6741 | current_evmcs->hv_clean_fields |= | |
6742 | HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; | |
f4124500 | 6743 | |
6f6a657c VK |
6744 | if (static_branch_unlikely(&enable_evmcs)) |
6745 | current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; | |
6746 | ||
55d2375e SC |
6747 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
6748 | if (vmx->host_debugctlmsr) | |
6749 | update_debugctlmsr(vmx->host_debugctlmsr); | |
f4124500 | 6750 | |
55d2375e SC |
6751 | #ifndef CONFIG_X86_64 |
6752 | /* | |
6753 | * The sysexit path does not restore ds/es, so we must set them to | |
6754 | * a reasonable value ourselves. | |
6755 | * | |
6756 | * We can't defer this to vmx_prepare_switch_to_host() since that | |
6757 | * function may be executed in interrupt context, which saves and | |
6758 | * restore segments around it, nullifying its effect. | |
6759 | */ | |
6760 | loadsegment(ds, __USER_DS); | |
6761 | loadsegment(es, __USER_DS); | |
6762 | #endif | |
4704d0be | 6763 | |
e5d03de5 | 6764 | vmx_register_cache_reset(vcpu); |
7854cbca | 6765 | |
2ef444f1 CP |
6766 | pt_guest_exit(vmx); |
6767 | ||
139a12cf | 6768 | kvm_load_host_xsave_state(vcpu); |
1811d979 | 6769 | |
55d2375e SC |
6770 | vmx->nested.nested_run_pending = 0; |
6771 | vmx->idt_vectoring_info = 0; | |
119a9c01 | 6772 | |
873e1da1 | 6773 | if (unlikely(vmx->fail)) { |
a6bdda1f | 6774 | vmx->exit_reason.full = 0xdead; |
a9ab13ff | 6775 | return EXIT_FASTPATH_NONE; |
873e1da1 SC |
6776 | } |
6777 | ||
a6bdda1f SC |
6778 | vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON); |
6779 | if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY)) | |
beb8d93b SC |
6780 | kvm_machine_check(); |
6781 | ||
a6bdda1f | 6782 | trace_kvm_exit(vmx->exit_reason.full, vcpu, KVM_ISA_VMX); |
dcf068da | 6783 | |
a6bdda1f | 6784 | if (unlikely(vmx->exit_reason.failed_vmentry)) |
a9ab13ff WL |
6785 | return EXIT_FASTPATH_NONE; |
6786 | ||
55d2375e SC |
6787 | vmx->loaded_vmcs->launched = 1; |
6788 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
c18911a2 | 6789 | |
55d2375e SC |
6790 | vmx_recover_nmi_blocking(vmx); |
6791 | vmx_complete_interrupts(vmx); | |
a9ab13ff | 6792 | |
dcf068da WL |
6793 | if (is_guest_mode(vcpu)) |
6794 | return EXIT_FASTPATH_NONE; | |
6795 | ||
6796 | exit_fastpath = vmx_exit_handlers_fastpath(vcpu); | |
404d5d7b WL |
6797 | if (exit_fastpath == EXIT_FASTPATH_REENTER_GUEST) { |
6798 | if (!kvm_vcpu_exit_request(vcpu)) { | |
6799 | /* | |
6800 | * FIXME: this goto should be a loop in vcpu_enter_guest, | |
6801 | * but it would incur the cost of a retpoline for now. | |
6802 | * Revisit once static calls are available. | |
6803 | */ | |
379a3c8e WL |
6804 | if (vcpu->arch.apicv_active) |
6805 | vmx_sync_pir_to_irr(vcpu); | |
404d5d7b WL |
6806 | goto reenter_guest; |
6807 | } | |
6808 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; | |
6809 | } | |
6810 | ||
a9ab13ff | 6811 | return exit_fastpath; |
55d2375e | 6812 | } |
2996fca0 | 6813 | |
55d2375e | 6814 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
cf8b84f4 | 6815 | { |
55d2375e | 6816 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4704d0be | 6817 | |
55d2375e SC |
6818 | if (enable_pml) |
6819 | vmx_destroy_pml_buffer(vmx); | |
6820 | free_vpid(vmx->vpid); | |
55d2375e SC |
6821 | nested_vmx_free_vcpu(vcpu); |
6822 | free_loaded_vmcs(vmx->loaded_vmcs); | |
55d2375e | 6823 | } |
4704d0be | 6824 | |
987b2594 | 6825 | static int vmx_create_vcpu(struct kvm_vcpu *vcpu) |
55d2375e | 6826 | { |
41836839 | 6827 | struct vcpu_vmx *vmx; |
34109c04 | 6828 | int i, cpu, err; |
4704d0be | 6829 | |
a9dd6f09 SC |
6830 | BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); |
6831 | vmx = to_vmx(vcpu); | |
d9a710e5 | 6832 | |
55d2375e | 6833 | err = -ENOMEM; |
b666a4b6 | 6834 | |
55d2375e | 6835 | vmx->vpid = allocate_vpid(); |
7cdc2d62 | 6836 | |
5f3d5799 | 6837 | /* |
55d2375e SC |
6838 | * If PML is turned on, failure on enabling PML just results in failure |
6839 | * of creating the vcpu, therefore we can simplify PML logic (by | |
6840 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
67b0ae43 | 6841 | * for the guest), etc. |
5f3d5799 | 6842 | */ |
55d2375e | 6843 | if (enable_pml) { |
41836839 | 6844 | vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
55d2375e | 6845 | if (!vmx->pml_pg) |
987b2594 | 6846 | goto free_vpid; |
55d2375e | 6847 | } |
4704d0be | 6848 | |
14a61b64 | 6849 | BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS); |
4704d0be | 6850 | |
14a61b64 SC |
6851 | for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i) { |
6852 | u32 index = vmx_uret_msrs_list[i]; | |
4be53410 | 6853 | u32 data_low, data_high; |
fbc18007 | 6854 | int j = vmx->nr_uret_msrs; |
4be53410 XL |
6855 | |
6856 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
6857 | continue; | |
6858 | if (wrmsr_safe(index, data_low, data_high) < 0) | |
6859 | continue; | |
46f4f0aa | 6860 | |
802145c5 | 6861 | vmx->guest_uret_msrs[j].slot = i; |
eb3db1b1 | 6862 | vmx->guest_uret_msrs[j].data = 0; |
46f4f0aa PB |
6863 | switch (index) { |
6864 | case MSR_IA32_TSX_CTRL: | |
6865 | /* | |
7131636e PB |
6866 | * TSX_CTRL_CPUID_CLEAR is handled in the CPUID |
6867 | * interception. Keep the host value unchanged to avoid | |
6868 | * changing CPUID bits under the host kernel's feet. | |
6869 | * | |
6870 | * hle=0, rtm=0, tsx_ctrl=1 can be found with some | |
6871 | * combinations of new kernel and old userspace. If | |
6872 | * those guests run on a tsx=off host, do allow guests | |
6873 | * to use TSX_CTRL, but do not change the value on the | |
6874 | * host so that TSX remains always disabled. | |
46f4f0aa | 6875 | */ |
7131636e PB |
6876 | if (boot_cpu_has(X86_FEATURE_RTM)) |
6877 | vmx->guest_uret_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; | |
6878 | else | |
6879 | vmx->guest_uret_msrs[j].mask = 0; | |
46f4f0aa PB |
6880 | break; |
6881 | default: | |
eb3db1b1 | 6882 | vmx->guest_uret_msrs[j].mask = -1ull; |
46f4f0aa PB |
6883 | break; |
6884 | } | |
fbc18007 | 6885 | ++vmx->nr_uret_msrs; |
4be53410 XL |
6886 | } |
6887 | ||
55d2375e SC |
6888 | err = alloc_loaded_vmcs(&vmx->vmcs01); |
6889 | if (err < 0) | |
7d73710d | 6890 | goto free_pml; |
cb61de2f | 6891 | |
3eb90017 AG |
6892 | /* The MSR bitmap starts with all ones */ |
6893 | bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS); | |
6894 | bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS); | |
6895 | ||
476c9bd8 | 6896 | vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R); |
200705df | 6897 | #ifdef CONFIG_X86_64 |
476c9bd8 AL |
6898 | vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW); |
6899 | vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW); | |
6900 | vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); | |
200705df | 6901 | #endif |
476c9bd8 AL |
6902 | vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); |
6903 | vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); | |
6904 | vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); | |
987b2594 | 6905 | if (kvm_cstate_in_guest(vcpu->kvm)) { |
476c9bd8 AL |
6906 | vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R); |
6907 | vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); | |
6908 | vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); | |
6909 | vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); | |
b5170063 | 6910 | } |
55d2375e | 6911 | vmx->msr_bitmap_mode = 0; |
4704d0be | 6912 | |
55d2375e SC |
6913 | vmx->loaded_vmcs = &vmx->vmcs01; |
6914 | cpu = get_cpu(); | |
34109c04 SC |
6915 | vmx_vcpu_load(vcpu, cpu); |
6916 | vcpu->cpu = cpu; | |
1b84292b | 6917 | init_vmcs(vmx); |
34109c04 | 6918 | vmx_vcpu_put(vcpu); |
55d2375e | 6919 | put_cpu(); |
34109c04 | 6920 | if (cpu_need_virtualize_apic_accesses(vcpu)) { |
987b2594 | 6921 | err = alloc_apic_access_page(vcpu->kvm); |
55d2375e SC |
6922 | if (err) |
6923 | goto free_vmcs; | |
6924 | } | |
6925 | ||
6926 | if (enable_ept && !enable_unrestricted_guest) { | |
987b2594 | 6927 | err = init_rmode_identity_map(vcpu->kvm); |
55d2375e SC |
6928 | if (err) |
6929 | goto free_vmcs; | |
6930 | } | |
4704d0be | 6931 | |
55d2375e | 6932 | if (nested) |
b9757a4b | 6933 | memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs)); |
55d2375e SC |
6934 | else |
6935 | memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); | |
bd18bffc | 6936 | |
55d2375e SC |
6937 | vmx->nested.posted_intr_nv = -1; |
6938 | vmx->nested.current_vmptr = -1ull; | |
bd18bffc | 6939 | |
bab0c318 | 6940 | vcpu->arch.microcode_version = 0x100000000ULL; |
32ad73db | 6941 | vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; |
feaf0c7d | 6942 | |
6f1e03bc | 6943 | /* |
55d2375e SC |
6944 | * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR |
6945 | * or POSTED_INTR_WAKEUP_VECTOR. | |
6f1e03bc | 6946 | */ |
55d2375e SC |
6947 | vmx->pi_desc.nv = POSTED_INTR_VECTOR; |
6948 | vmx->pi_desc.sn = 1; | |
4704d0be | 6949 | |
53963a70 LT |
6950 | vmx->ept_pointer = INVALID_PAGE; |
6951 | ||
a9dd6f09 | 6952 | return 0; |
4704d0be | 6953 | |
55d2375e SC |
6954 | free_vmcs: |
6955 | free_loaded_vmcs(vmx->loaded_vmcs); | |
55d2375e SC |
6956 | free_pml: |
6957 | vmx_destroy_pml_buffer(vmx); | |
987b2594 | 6958 | free_vpid: |
55d2375e | 6959 | free_vpid(vmx->vpid); |
a9dd6f09 | 6960 | return err; |
55d2375e | 6961 | } |
36be0b9d | 6962 | |
65fd4cb6 TG |
6963 | #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" |
6964 | #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" | |
21feb4eb | 6965 | |
55d2375e SC |
6966 | static int vmx_vm_init(struct kvm *kvm) |
6967 | { | |
6968 | spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); | |
ff651cb6 | 6969 | |
55d2375e SC |
6970 | if (!ple_gap) |
6971 | kvm->arch.pause_in_guest = true; | |
3af18d9c | 6972 | |
55d2375e SC |
6973 | if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { |
6974 | switch (l1tf_mitigation) { | |
6975 | case L1TF_MITIGATION_OFF: | |
6976 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
6977 | /* 'I explicitly don't care' is set */ | |
6978 | break; | |
6979 | case L1TF_MITIGATION_FLUSH: | |
6980 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
6981 | case L1TF_MITIGATION_FULL: | |
6982 | /* | |
6983 | * Warn upon starting the first VM in a potentially | |
6984 | * insecure environment. | |
6985 | */ | |
b284909a | 6986 | if (sched_smt_active()) |
55d2375e SC |
6987 | pr_warn_once(L1TF_MSG_SMT); |
6988 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) | |
6989 | pr_warn_once(L1TF_MSG_L1D); | |
6990 | break; | |
6991 | case L1TF_MITIGATION_FULL_FORCE: | |
6992 | /* Flush is enforced */ | |
6993 | break; | |
6994 | } | |
6995 | } | |
4e19c36f | 6996 | kvm_apicv_init(kvm, enable_apicv); |
55d2375e | 6997 | return 0; |
4704d0be NHE |
6998 | } |
6999 | ||
f257d6dc | 7000 | static int __init vmx_check_processor_compat(void) |
bd18bffc | 7001 | { |
55d2375e SC |
7002 | struct vmcs_config vmcs_conf; |
7003 | struct vmx_capability vmx_cap; | |
bd18bffc | 7004 | |
ff10e22e SC |
7005 | if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || |
7006 | !this_cpu_has(X86_FEATURE_VMX)) { | |
7007 | pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); | |
7008 | return -EIO; | |
7009 | } | |
7010 | ||
55d2375e | 7011 | if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) |
f257d6dc | 7012 | return -EIO; |
55d2375e | 7013 | if (nested) |
a4443267 | 7014 | nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept); |
55d2375e SC |
7015 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { |
7016 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
7017 | smp_processor_id()); | |
f257d6dc | 7018 | return -EIO; |
bd18bffc | 7019 | } |
f257d6dc | 7020 | return 0; |
bd18bffc SC |
7021 | } |
7022 | ||
55d2375e | 7023 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
bd18bffc | 7024 | { |
55d2375e SC |
7025 | u8 cache; |
7026 | u64 ipat = 0; | |
bd18bffc | 7027 | |
222f06e7 CW |
7028 | /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in |
7029 | * memory aliases with conflicting memory types and sometimes MCEs. | |
7030 | * We have to be careful as to what are honored and when. | |
7031 | * | |
7032 | * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to | |
7033 | * UC. The effective memory type is UC or WC depending on guest PAT. | |
7034 | * This was historically the source of MCEs and we want to be | |
7035 | * conservative. | |
7036 | * | |
7037 | * When there is no need to deal with noncoherent DMA (e.g., no VT-d | |
7038 | * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The | |
7039 | * EPT memory type is set to WB. The effective memory type is forced | |
7040 | * WB. | |
7041 | * | |
7042 | * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The | |
7043 | * EPT memory type is used to emulate guest CD/MTRR. | |
bd18bffc | 7044 | */ |
222f06e7 | 7045 | |
55d2375e SC |
7046 | if (is_mmio) { |
7047 | cache = MTRR_TYPE_UNCACHABLE; | |
7048 | goto exit; | |
7049 | } | |
bd18bffc | 7050 | |
55d2375e SC |
7051 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { |
7052 | ipat = VMX_EPT_IPAT_BIT; | |
7053 | cache = MTRR_TYPE_WRBACK; | |
7054 | goto exit; | |
7055 | } | |
bd18bffc | 7056 | |
55d2375e SC |
7057 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { |
7058 | ipat = VMX_EPT_IPAT_BIT; | |
7059 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
7060 | cache = MTRR_TYPE_WRBACK; | |
7061 | else | |
7062 | cache = MTRR_TYPE_UNCACHABLE; | |
7063 | goto exit; | |
7064 | } | |
bd18bffc | 7065 | |
55d2375e | 7066 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
bd18bffc | 7067 | |
55d2375e SC |
7068 | exit: |
7069 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
7070 | } | |
bd18bffc | 7071 | |
fe7f895d | 7072 | static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) |
55d2375e | 7073 | { |
bd18bffc | 7074 | /* |
55d2375e SC |
7075 | * These bits in the secondary execution controls field |
7076 | * are dynamic, the others are mostly based on the hypervisor | |
7077 | * architecture and the guest's CPUID. Do not touch the | |
7078 | * dynamic bits. | |
bd18bffc | 7079 | */ |
55d2375e SC |
7080 | u32 mask = |
7081 | SECONDARY_EXEC_SHADOW_VMCS | | |
7082 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
7083 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
7084 | SECONDARY_EXEC_DESC; | |
bd18bffc | 7085 | |
fe7f895d SC |
7086 | u32 new_ctl = vmx->secondary_exec_control; |
7087 | u32 cur_ctl = secondary_exec_controls_get(vmx); | |
bd18bffc | 7088 | |
fe7f895d | 7089 | secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); |
bd18bffc SC |
7090 | } |
7091 | ||
4704d0be | 7092 | /* |
55d2375e SC |
7093 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits |
7094 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
4704d0be | 7095 | */ |
55d2375e | 7096 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) |
4704d0be NHE |
7097 | { |
7098 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
55d2375e | 7099 | struct kvm_cpuid_entry2 *entry; |
4704d0be | 7100 | |
55d2375e SC |
7101 | vmx->nested.msrs.cr0_fixed1 = 0xffffffff; |
7102 | vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; | |
e79f245d | 7103 | |
55d2375e SC |
7104 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ |
7105 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
7106 | vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ | |
7107 | } while (0) | |
ff651cb6 | 7108 | |
55d2375e | 7109 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); |
87382003 SC |
7110 | cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); |
7111 | cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); | |
7112 | cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); | |
7113 | cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); | |
7114 | cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); | |
7115 | cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); | |
7116 | cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); | |
7117 | cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); | |
7118 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); | |
7119 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); | |
7120 | cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); | |
7121 | cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); | |
7122 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); | |
7123 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); | |
61ada748 | 7124 | |
55d2375e | 7125 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); |
87382003 SC |
7126 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); |
7127 | cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); | |
7128 | cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); | |
7129 | cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); | |
7130 | cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); | |
7131 | cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); | |
cf3215d9 | 7132 | |
55d2375e SC |
7133 | #undef cr4_fixed1_update |
7134 | } | |
36c3cc42 | 7135 | |
55d2375e SC |
7136 | static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) |
7137 | { | |
7138 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
f459a707 | 7139 | |
55d2375e SC |
7140 | if (kvm_mpx_supported()) { |
7141 | bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); | |
4704d0be | 7142 | |
55d2375e SC |
7143 | if (mpx_enabled) { |
7144 | vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; | |
7145 | vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; | |
7146 | } else { | |
7147 | vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; | |
7148 | vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; | |
7149 | } | |
dccbfcf5 | 7150 | } |
55d2375e | 7151 | } |
4704d0be | 7152 | |
6c0f0bba LK |
7153 | static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) |
7154 | { | |
7155 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7156 | struct kvm_cpuid_entry2 *best = NULL; | |
7157 | int i; | |
7158 | ||
7159 | for (i = 0; i < PT_CPUID_LEAVES; i++) { | |
7160 | best = kvm_find_cpuid_entry(vcpu, 0x14, i); | |
7161 | if (!best) | |
7162 | return; | |
7163 | vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; | |
7164 | vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; | |
7165 | vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; | |
7166 | vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; | |
7167 | } | |
7168 | ||
7169 | /* Get the number of configurable Address Ranges for filtering */ | |
7170 | vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, | |
7171 | PT_CAP_num_address_ranges); | |
7172 | ||
7173 | /* Initialize and clear the no dependency bits */ | |
7174 | vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | | |
7175 | RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); | |
7176 | ||
7177 | /* | |
7178 | * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise | |
7179 | * will inject an #GP | |
7180 | */ | |
7181 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) | |
7182 | vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; | |
7183 | ||
7184 | /* | |
7185 | * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and | |
7186 | * PSBFreq can be set | |
7187 | */ | |
7188 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) | |
7189 | vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | | |
7190 | RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); | |
7191 | ||
7192 | /* | |
7193 | * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and | |
7194 | * MTCFreq can be set | |
7195 | */ | |
7196 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) | |
7197 | vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | | |
7198 | RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); | |
7199 | ||
7200 | /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ | |
7201 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) | |
7202 | vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | | |
7203 | RTIT_CTL_PTW_EN); | |
7204 | ||
7205 | /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ | |
7206 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) | |
7207 | vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; | |
7208 | ||
7209 | /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ | |
7210 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) | |
7211 | vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; | |
7212 | ||
7213 | /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ | |
7214 | if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) | |
7215 | vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; | |
7216 | ||
7217 | /* unmask address range configure area */ | |
7218 | for (i = 0; i < vmx->pt_desc.addr_range; i++) | |
d14eff1b | 7219 | vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); |
6c0f0bba LK |
7220 | } |
7221 | ||
7c1b761b | 7222 | static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) |
55d2375e SC |
7223 | { |
7224 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be | 7225 | |
7204160e AL |
7226 | /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ |
7227 | vcpu->arch.xsaves_enabled = false; | |
7228 | ||
55d2375e SC |
7229 | if (cpu_has_secondary_exec_ctrls()) { |
7230 | vmx_compute_secondary_exec_control(vmx); | |
fe7f895d | 7231 | vmcs_set_secondary_exec_control(vmx); |
705699a1 | 7232 | } |
4704d0be | 7233 | |
55d2375e SC |
7234 | if (nested_vmx_allowed(vcpu)) |
7235 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
32ad73db SC |
7236 | FEAT_CTL_VMX_ENABLED_INSIDE_SMX | |
7237 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; | |
55d2375e SC |
7238 | else |
7239 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
32ad73db SC |
7240 | ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | |
7241 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); | |
4f350c6d | 7242 | |
55d2375e SC |
7243 | if (nested_vmx_allowed(vcpu)) { |
7244 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
7245 | nested_vmx_entry_exit_ctls_update(vcpu); | |
4f350c6d | 7246 | } |
6c0f0bba LK |
7247 | |
7248 | if (boot_cpu_has(X86_FEATURE_INTEL_PT) && | |
7249 | guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) | |
7250 | update_intel_pt_cfg(vcpu); | |
b07a5c53 PB |
7251 | |
7252 | if (boot_cpu_has(X86_FEATURE_RTM)) { | |
eb3db1b1 | 7253 | struct vmx_uret_msr *msr; |
d85a8034 | 7254 | msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL); |
b07a5c53 PB |
7255 | if (msr) { |
7256 | bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); | |
7bf662bb | 7257 | vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); |
b07a5c53 PB |
7258 | } |
7259 | } | |
a6337a35 | 7260 | |
2ed41aa6 SC |
7261 | set_cr4_guest_host_mask(vmx); |
7262 | ||
a6337a35 SC |
7263 | /* Refresh #PF interception to account for MAXPHYADDR changes. */ |
7264 | update_exception_bitmap(vcpu); | |
55d2375e | 7265 | } |
09abb5e3 | 7266 | |
3ec6fd8c | 7267 | static __init void vmx_set_cpu_caps(void) |
55d2375e | 7268 | { |
3ec6fd8c SC |
7269 | kvm_set_cpu_caps(); |
7270 | ||
7271 | /* CPUID 0x1 */ | |
7272 | if (nested) | |
7273 | kvm_cpu_cap_set(X86_FEATURE_VMX); | |
7274 | ||
7275 | /* CPUID 0x7 */ | |
8721f5b0 SC |
7276 | if (kvm_mpx_supported()) |
7277 | kvm_cpu_cap_check_and_set(X86_FEATURE_MPX); | |
7278 | if (cpu_has_vmx_invpcid()) | |
7279 | kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID); | |
7280 | if (vmx_pt_mode_is_host_guest()) | |
7281 | kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT); | |
3ec6fd8c | 7282 | |
90d2f60f SC |
7283 | if (vmx_umip_emulated()) |
7284 | kvm_cpu_cap_set(X86_FEATURE_UMIP); | |
7285 | ||
b3d895d5 | 7286 | /* CPUID 0xD.1 */ |
408e9a31 | 7287 | supported_xss = 0; |
becdad85 | 7288 | if (!cpu_has_vmx_xsaves()) |
b3d895d5 SC |
7289 | kvm_cpu_cap_clear(X86_FEATURE_XSAVES); |
7290 | ||
49aadbc9 SC |
7291 | /* CPUID 0x80000001 and 0x7 (RDPID) */ |
7292 | if (!cpu_has_vmx_rdtscp()) { | |
3ec6fd8c | 7293 | kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); |
49aadbc9 SC |
7294 | kvm_cpu_cap_clear(X86_FEATURE_RDPID); |
7295 | } | |
0abcc8f6 | 7296 | |
becdad85 | 7297 | if (cpu_has_vmx_waitpkg()) |
0abcc8f6 | 7298 | kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG); |
4704d0be NHE |
7299 | } |
7300 | ||
55d2375e | 7301 | static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) |
42124925 | 7302 | { |
55d2375e | 7303 | to_vmx(vcpu)->req_immediate_exit = true; |
7c177938 NHE |
7304 | } |
7305 | ||
35a57134 OU |
7306 | static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, |
7307 | struct x86_instruction_info *info) | |
7308 | { | |
7309 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
7310 | unsigned short port; | |
7311 | bool intercept; | |
7312 | int size; | |
7313 | ||
7314 | if (info->intercept == x86_intercept_in || | |
7315 | info->intercept == x86_intercept_ins) { | |
7316 | port = info->src_val; | |
7317 | size = info->dst_bytes; | |
7318 | } else { | |
7319 | port = info->dst_val; | |
7320 | size = info->src_bytes; | |
7321 | } | |
7322 | ||
7323 | /* | |
7324 | * If the 'use IO bitmaps' VM-execution control is 0, IO instruction | |
7325 | * VM-exits depend on the 'unconditional IO exiting' VM-execution | |
7326 | * control. | |
7327 | * | |
7328 | * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. | |
7329 | */ | |
7330 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
7331 | intercept = nested_cpu_has(vmcs12, | |
7332 | CPU_BASED_UNCOND_IO_EXITING); | |
7333 | else | |
7334 | intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); | |
7335 | ||
86f7e90c | 7336 | /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ |
35a57134 OU |
7337 | return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; |
7338 | } | |
7339 | ||
8a76d7f2 JR |
7340 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
7341 | struct x86_instruction_info *info, | |
21f1b8f2 SC |
7342 | enum x86_intercept_stage stage, |
7343 | struct x86_exception *exception) | |
8a76d7f2 | 7344 | { |
fb6d4d34 | 7345 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
fb6d4d34 | 7346 | |
35a57134 | 7347 | switch (info->intercept) { |
fb6d4d34 PB |
7348 | /* |
7349 | * RDPID causes #UD if disabled through secondary execution controls. | |
7350 | * Because it is marked as EmulateOnUD, we need to intercept it here. | |
b06e5dd8 | 7351 | * Note, RDPID is hidden behind ENABLE_RDTSCP. |
fb6d4d34 | 7352 | */ |
b06e5dd8 | 7353 | case x86_intercept_rdpid: |
7f3603b6 | 7354 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) { |
21f1b8f2 SC |
7355 | exception->vector = UD_VECTOR; |
7356 | exception->error_code_valid = false; | |
35a57134 OU |
7357 | return X86EMUL_PROPAGATE_FAULT; |
7358 | } | |
7359 | break; | |
7360 | ||
7361 | case x86_intercept_in: | |
7362 | case x86_intercept_ins: | |
7363 | case x86_intercept_out: | |
7364 | case x86_intercept_outs: | |
7365 | return vmx_check_intercept_io(vcpu, info); | |
fb6d4d34 | 7366 | |
86f7e90c OU |
7367 | case x86_intercept_lgdt: |
7368 | case x86_intercept_lidt: | |
7369 | case x86_intercept_lldt: | |
7370 | case x86_intercept_ltr: | |
7371 | case x86_intercept_sgdt: | |
7372 | case x86_intercept_sidt: | |
7373 | case x86_intercept_sldt: | |
7374 | case x86_intercept_str: | |
7375 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC)) | |
7376 | return X86EMUL_CONTINUE; | |
7377 | ||
7378 | /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ | |
7379 | break; | |
7380 | ||
fb6d4d34 | 7381 | /* TODO: check more intercepts... */ |
35a57134 OU |
7382 | default: |
7383 | break; | |
7384 | } | |
7385 | ||
07721fee | 7386 | return X86EMUL_UNHANDLEABLE; |
8a76d7f2 JR |
7387 | } |
7388 | ||
64672c95 YJ |
7389 | #ifdef CONFIG_X86_64 |
7390 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
7391 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
7392 | u64 divisor, u64 *result) | |
7393 | { | |
7394 | u64 low = a << shift, high = a >> (64 - shift); | |
7395 | ||
7396 | /* To avoid the overflow on divq */ | |
7397 | if (high >= divisor) | |
7398 | return 1; | |
7399 | ||
7400 | /* Low hold the result, high hold rem which is discarded */ | |
7401 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
7402 | "rm" (divisor), "0" (low), "1" (high)); | |
7403 | *result = low; | |
7404 | ||
7405 | return 0; | |
7406 | } | |
7407 | ||
f9927982 SC |
7408 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, |
7409 | bool *expired) | |
64672c95 | 7410 | { |
386c6ddb | 7411 | struct vcpu_vmx *vmx; |
c5ce8235 | 7412 | u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; |
39497d76 | 7413 | struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; |
386c6ddb | 7414 | |
386c6ddb KA |
7415 | vmx = to_vmx(vcpu); |
7416 | tscl = rdtsc(); | |
7417 | guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
7418 | delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
39497d76 SC |
7419 | lapic_timer_advance_cycles = nsec_to_cycles(vcpu, |
7420 | ktimer->timer_advance_ns); | |
c5ce8235 WL |
7421 | |
7422 | if (delta_tsc > lapic_timer_advance_cycles) | |
7423 | delta_tsc -= lapic_timer_advance_cycles; | |
7424 | else | |
7425 | delta_tsc = 0; | |
64672c95 YJ |
7426 | |
7427 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
7428 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
0967fa1c | 7429 | delta_tsc && u64_shl_div_u64(delta_tsc, |
64672c95 | 7430 | kvm_tsc_scaling_ratio_frac_bits, |
0967fa1c | 7431 | vcpu->arch.tsc_scaling_ratio, &delta_tsc)) |
64672c95 YJ |
7432 | return -ERANGE; |
7433 | ||
7434 | /* | |
7435 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
7436 | * we can't use the preemption timer. | |
7437 | * It's possible that it fits on later vmentries, but checking | |
7438 | * on every vmentry is costly so we just use an hrtimer. | |
7439 | */ | |
7440 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
7441 | return -ERANGE; | |
7442 | ||
7443 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
f9927982 SC |
7444 | *expired = !delta_tsc; |
7445 | return 0; | |
64672c95 YJ |
7446 | } |
7447 | ||
7448 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
7449 | { | |
f459a707 | 7450 | to_vmx(vcpu)->hv_deadline_tsc = -1; |
64672c95 YJ |
7451 | } |
7452 | #endif | |
7453 | ||
48d89b92 | 7454 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 7455 | { |
b31c114b | 7456 | if (!kvm_pause_in_guest(vcpu->kvm)) |
b4a2d31d | 7457 | shrink_ple_window(vcpu); |
ae97a3b8 RK |
7458 | } |
7459 | ||
843e4330 KH |
7460 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
7461 | struct kvm_memory_slot *slot) | |
7462 | { | |
3c9bd400 JZ |
7463 | if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) |
7464 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
843e4330 KH |
7465 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); |
7466 | } | |
7467 | ||
7468 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
7469 | struct kvm_memory_slot *slot) | |
7470 | { | |
7471 | kvm_mmu_slot_set_dirty(kvm, slot); | |
7472 | } | |
7473 | ||
7474 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
7475 | { | |
7476 | kvm_flush_pml_buffers(kvm); | |
7477 | } | |
7478 | ||
7479 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, | |
7480 | struct kvm_memory_slot *memslot, | |
7481 | gfn_t offset, unsigned long mask) | |
7482 | { | |
7483 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
7484 | } | |
7485 | ||
bc22512b YJ |
7486 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
7487 | { | |
7488 | if (pi_pre_block(vcpu)) | |
7489 | return 1; | |
7490 | ||
64672c95 YJ |
7491 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
7492 | kvm_lapic_switch_to_sw_timer(vcpu); | |
7493 | ||
bc22512b YJ |
7494 | return 0; |
7495 | } | |
7496 | ||
bc22512b YJ |
7497 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
7498 | { | |
afaf0b2f | 7499 | if (kvm_x86_ops.set_hv_timer) |
64672c95 YJ |
7500 | kvm_lapic_switch_to_hv_timer(vcpu); |
7501 | ||
bc22512b YJ |
7502 | pi_post_block(vcpu); |
7503 | } | |
7504 | ||
c45dcc71 AR |
7505 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
7506 | { | |
7507 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
7508 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
32ad73db | 7509 | FEAT_CTL_LMCE_ENABLED; |
c45dcc71 AR |
7510 | else |
7511 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
32ad73db | 7512 | ~FEAT_CTL_LMCE_ENABLED; |
c45dcc71 AR |
7513 | } |
7514 | ||
c9d40913 | 7515 | static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection) |
72d7b374 | 7516 | { |
72e9cbdb LP |
7517 | /* we need a nested vmexit to enter SMM, postpone if run is pending */ |
7518 | if (to_vmx(vcpu)->nested.nested_run_pending) | |
c9d40913 | 7519 | return -EBUSY; |
a9fa7cb6 | 7520 | return !is_smm(vcpu); |
72d7b374 LP |
7521 | } |
7522 | ||
0234bf88 LP |
7523 | static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
7524 | { | |
72e9cbdb LP |
7525 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7526 | ||
7527 | vmx->nested.smm.guest_mode = is_guest_mode(vcpu); | |
7528 | if (vmx->nested.smm.guest_mode) | |
7529 | nested_vmx_vmexit(vcpu, -1, 0, 0); | |
7530 | ||
7531 | vmx->nested.smm.vmxon = vmx->nested.vmxon; | |
7532 | vmx->nested.vmxon = false; | |
caa057a2 | 7533 | vmx_clear_hlt(vcpu); |
0234bf88 LP |
7534 | return 0; |
7535 | } | |
7536 | ||
ed19321f | 7537 | static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) |
0234bf88 | 7538 | { |
72e9cbdb LP |
7539 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7540 | int ret; | |
7541 | ||
7542 | if (vmx->nested.smm.vmxon) { | |
7543 | vmx->nested.vmxon = true; | |
7544 | vmx->nested.smm.vmxon = false; | |
7545 | } | |
7546 | ||
7547 | if (vmx->nested.smm.guest_mode) { | |
a633e41e | 7548 | ret = nested_vmx_enter_non_root_mode(vcpu, false); |
72e9cbdb LP |
7549 | if (ret) |
7550 | return ret; | |
7551 | ||
7552 | vmx->nested.smm.guest_mode = false; | |
7553 | } | |
0234bf88 LP |
7554 | return 0; |
7555 | } | |
7556 | ||
c9d40913 | 7557 | static void enable_smi_window(struct kvm_vcpu *vcpu) |
cc3d967f | 7558 | { |
c9d40913 | 7559 | /* RSM will cause a vmexit anyway. */ |
cc3d967f LP |
7560 | } |
7561 | ||
4b9852f4 LA |
7562 | static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) |
7563 | { | |
1c96dcce | 7564 | return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu); |
4b9852f4 LA |
7565 | } |
7566 | ||
93dff2fe JM |
7567 | static void vmx_migrate_timers(struct kvm_vcpu *vcpu) |
7568 | { | |
7569 | if (is_guest_mode(vcpu)) { | |
7570 | struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer; | |
7571 | ||
7572 | if (hrtimer_try_to_cancel(timer) == 1) | |
7573 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); | |
7574 | } | |
7575 | } | |
7576 | ||
6e4fd06f | 7577 | static void hardware_unsetup(void) |
484014fa SC |
7578 | { |
7579 | if (nested) | |
7580 | nested_vmx_hardware_unsetup(); | |
7581 | ||
7582 | free_kvm_area(); | |
7583 | } | |
7584 | ||
7585 | static bool vmx_check_apicv_inhibit_reasons(ulong bit) | |
7586 | { | |
7587 | ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | | |
7588 | BIT(APICV_INHIBIT_REASON_HYPERV); | |
7589 | ||
7590 | return supported & BIT(bit); | |
7591 | } | |
7592 | ||
fb04a1ed PX |
7593 | static int vmx_cpu_dirty_log_size(void) |
7594 | { | |
7595 | return enable_pml ? PML_ENTITY_NUM : 0; | |
7596 | } | |
7597 | ||
e286ac0e | 7598 | static struct kvm_x86_ops vmx_x86_ops __initdata = { |
484014fa SC |
7599 | .hardware_unsetup = hardware_unsetup, |
7600 | ||
7601 | .hardware_enable = hardware_enable, | |
7602 | .hardware_disable = hardware_disable, | |
7603 | .cpu_has_accelerated_tpr = report_flexpriority, | |
7604 | .has_emulated_msr = vmx_has_emulated_msr, | |
7605 | ||
7606 | .vm_size = sizeof(struct kvm_vmx), | |
7607 | .vm_init = vmx_vm_init, | |
7608 | ||
7609 | .vcpu_create = vmx_create_vcpu, | |
7610 | .vcpu_free = vmx_free_vcpu, | |
7611 | .vcpu_reset = vmx_vcpu_reset, | |
7612 | ||
7613 | .prepare_guest_switch = vmx_prepare_switch_to_guest, | |
7614 | .vcpu_load = vmx_vcpu_load, | |
7615 | .vcpu_put = vmx_vcpu_put, | |
7616 | ||
6986982f | 7617 | .update_exception_bitmap = update_exception_bitmap, |
484014fa SC |
7618 | .get_msr_feature = vmx_get_msr_feature, |
7619 | .get_msr = vmx_get_msr, | |
7620 | .set_msr = vmx_set_msr, | |
7621 | .get_segment_base = vmx_get_segment_base, | |
7622 | .get_segment = vmx_get_segment, | |
7623 | .set_segment = vmx_set_segment, | |
7624 | .get_cpl = vmx_get_cpl, | |
7625 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, | |
484014fa | 7626 | .set_cr0 = vmx_set_cr0, |
c2fe3cd4 | 7627 | .is_valid_cr4 = vmx_is_valid_cr4, |
484014fa SC |
7628 | .set_cr4 = vmx_set_cr4, |
7629 | .set_efer = vmx_set_efer, | |
7630 | .get_idt = vmx_get_idt, | |
7631 | .set_idt = vmx_set_idt, | |
7632 | .get_gdt = vmx_get_gdt, | |
7633 | .set_gdt = vmx_set_gdt, | |
484014fa SC |
7634 | .set_dr7 = vmx_set_dr7, |
7635 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, | |
7636 | .cache_reg = vmx_cache_reg, | |
7637 | .get_rflags = vmx_get_rflags, | |
7638 | .set_rflags = vmx_set_rflags, | |
7639 | ||
7780938c | 7640 | .tlb_flush_all = vmx_flush_tlb_all, |
eeeb4f67 | 7641 | .tlb_flush_current = vmx_flush_tlb_current, |
484014fa | 7642 | .tlb_flush_gva = vmx_flush_tlb_gva, |
e64419d9 | 7643 | .tlb_flush_guest = vmx_flush_tlb_guest, |
484014fa SC |
7644 | |
7645 | .run = vmx_vcpu_run, | |
7646 | .handle_exit = vmx_handle_exit, | |
7647 | .skip_emulated_instruction = vmx_skip_emulated_instruction, | |
7648 | .update_emulated_instruction = vmx_update_emulated_instruction, | |
7649 | .set_interrupt_shadow = vmx_set_interrupt_shadow, | |
7650 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
7651 | .patch_hypercall = vmx_patch_hypercall, | |
7652 | .set_irq = vmx_inject_irq, | |
7653 | .set_nmi = vmx_inject_nmi, | |
7654 | .queue_exception = vmx_queue_exception, | |
7655 | .cancel_injection = vmx_cancel_injection, | |
7656 | .interrupt_allowed = vmx_interrupt_allowed, | |
7657 | .nmi_allowed = vmx_nmi_allowed, | |
7658 | .get_nmi_mask = vmx_get_nmi_mask, | |
7659 | .set_nmi_mask = vmx_set_nmi_mask, | |
7660 | .enable_nmi_window = enable_nmi_window, | |
7661 | .enable_irq_window = enable_irq_window, | |
7662 | .update_cr8_intercept = update_cr8_intercept, | |
7663 | .set_virtual_apic_mode = vmx_set_virtual_apic_mode, | |
7664 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, | |
7665 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
7666 | .load_eoi_exitmap = vmx_load_eoi_exitmap, | |
7667 | .apicv_post_state_restore = vmx_apicv_post_state_restore, | |
7668 | .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, | |
7669 | .hwapic_irr_update = vmx_hwapic_irr_update, | |
7670 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
7671 | .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, | |
7672 | .sync_pir_to_irr = vmx_sync_pir_to_irr, | |
7673 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
8888cdd0 | 7674 | .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt, |
484014fa SC |
7675 | |
7676 | .set_tss_addr = vmx_set_tss_addr, | |
7677 | .set_identity_map_addr = vmx_set_identity_map_addr, | |
484014fa SC |
7678 | .get_mt_mask = vmx_get_mt_mask, |
7679 | ||
7680 | .get_exit_info = vmx_get_exit_info, | |
7681 | ||
7c1b761b | 7682 | .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid, |
484014fa SC |
7683 | |
7684 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
7685 | ||
484014fa SC |
7686 | .write_l1_tsc_offset = vmx_write_l1_tsc_offset, |
7687 | ||
7688 | .load_mmu_pgd = vmx_load_mmu_pgd, | |
7689 | ||
7690 | .check_intercept = vmx_check_intercept, | |
7691 | .handle_exit_irqoff = vmx_handle_exit_irqoff, | |
7692 | ||
7693 | .request_immediate_exit = vmx_request_immediate_exit, | |
7694 | ||
7695 | .sched_in = vmx_sched_in, | |
7696 | ||
7697 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
7698 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
7699 | .flush_log_dirty = vmx_flush_log_dirty, | |
7700 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
484014fa SC |
7701 | |
7702 | .pre_block = vmx_pre_block, | |
7703 | .post_block = vmx_post_block, | |
7704 | ||
7705 | .pmu_ops = &intel_pmu_ops, | |
33b22172 | 7706 | .nested_ops = &vmx_nested_ops, |
484014fa | 7707 | |
8888cdd0 | 7708 | .update_pi_irte = pi_update_irte, |
484014fa SC |
7709 | |
7710 | #ifdef CONFIG_X86_64 | |
7711 | .set_hv_timer = vmx_set_hv_timer, | |
7712 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
7713 | #endif | |
7714 | ||
7715 | .setup_mce = vmx_setup_mce, | |
7716 | ||
7717 | .smi_allowed = vmx_smi_allowed, | |
7718 | .pre_enter_smm = vmx_pre_enter_smm, | |
7719 | .pre_leave_smm = vmx_pre_leave_smm, | |
7720 | .enable_smi_window = enable_smi_window, | |
7721 | ||
09e3e2a1 | 7722 | .can_emulate_instruction = vmx_can_emulate_instruction, |
484014fa | 7723 | .apic_init_signal_blocked = vmx_apic_init_signal_blocked, |
93dff2fe | 7724 | .migrate_timers = vmx_migrate_timers, |
3eb90017 AG |
7725 | |
7726 | .msr_filter_changed = vmx_msr_filter_changed, | |
f9a4d621 | 7727 | .complete_emulated_msr = kvm_complete_insn_gp, |
fb04a1ed | 7728 | .cpu_dirty_log_size = vmx_cpu_dirty_log_size, |
647daca2 TL |
7729 | |
7730 | .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector, | |
484014fa SC |
7731 | }; |
7732 | ||
a3203381 SC |
7733 | static __init int hardware_setup(void) |
7734 | { | |
7735 | unsigned long host_bndcfgs; | |
2342080c | 7736 | struct desc_ptr dt; |
703c335d | 7737 | int r, i, ept_lpage_level; |
a3203381 | 7738 | |
2342080c SC |
7739 | store_idt(&dt); |
7740 | host_idt_base = dt.address; | |
7741 | ||
14a61b64 SC |
7742 | for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i) |
7743 | kvm_define_user_return_msr(i, vmx_uret_msrs_list[i]); | |
a3203381 SC |
7744 | |
7745 | if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) | |
7746 | return -EIO; | |
7747 | ||
7748 | if (boot_cpu_has(X86_FEATURE_NX)) | |
7749 | kvm_enable_efer_bits(EFER_NX); | |
7750 | ||
7751 | if (boot_cpu_has(X86_FEATURE_MPX)) { | |
7752 | rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); | |
7753 | WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); | |
7754 | } | |
7755 | ||
7f5581f5 | 7756 | if (!cpu_has_vmx_mpx()) |
cfc48181 SC |
7757 | supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | |
7758 | XFEATURE_MASK_BNDCSR); | |
7759 | ||
a3203381 SC |
7760 | if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || |
7761 | !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) | |
7762 | enable_vpid = 0; | |
7763 | ||
7764 | if (!cpu_has_vmx_ept() || | |
7765 | !cpu_has_vmx_ept_4levels() || | |
7766 | !cpu_has_vmx_ept_mt_wb() || | |
7767 | !cpu_has_vmx_invept_global()) | |
7768 | enable_ept = 0; | |
7769 | ||
7770 | if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) | |
7771 | enable_ept_ad_bits = 0; | |
7772 | ||
7773 | if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) | |
7774 | enable_unrestricted_guest = 0; | |
7775 | ||
7776 | if (!cpu_has_vmx_flexpriority()) | |
7777 | flexpriority_enabled = 0; | |
7778 | ||
7779 | if (!cpu_has_virtual_nmis()) | |
7780 | enable_vnmi = 0; | |
7781 | ||
7782 | /* | |
7783 | * set_apic_access_page_addr() is used to reload apic access | |
7784 | * page upon invalidation. No need to do anything if not | |
7785 | * using the APIC_ACCESS_ADDR VMCS field. | |
7786 | */ | |
7787 | if (!flexpriority_enabled) | |
72b0eaa9 | 7788 | vmx_x86_ops.set_apic_access_page_addr = NULL; |
a3203381 SC |
7789 | |
7790 | if (!cpu_has_vmx_tpr_shadow()) | |
72b0eaa9 | 7791 | vmx_x86_ops.update_cr8_intercept = NULL; |
a3203381 SC |
7792 | |
7793 | #if IS_ENABLED(CONFIG_HYPERV) | |
7794 | if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH | |
1f3a3e46 | 7795 | && enable_ept) { |
72b0eaa9 SC |
7796 | vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb; |
7797 | vmx_x86_ops.tlb_remote_flush_with_range = | |
1f3a3e46 LT |
7798 | hv_remote_flush_tlb_with_range; |
7799 | } | |
a3203381 SC |
7800 | #endif |
7801 | ||
7802 | if (!cpu_has_vmx_ple()) { | |
7803 | ple_gap = 0; | |
7804 | ple_window = 0; | |
7805 | ple_window_grow = 0; | |
7806 | ple_window_max = 0; | |
7807 | ple_window_shrink = 0; | |
7808 | } | |
7809 | ||
7810 | if (!cpu_has_vmx_apicv()) { | |
7811 | enable_apicv = 0; | |
72b0eaa9 | 7812 | vmx_x86_ops.sync_pir_to_irr = NULL; |
a3203381 SC |
7813 | } |
7814 | ||
7815 | if (cpu_has_vmx_tsc_scaling()) { | |
7816 | kvm_has_tsc_control = true; | |
7817 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
7818 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
7819 | } | |
7820 | ||
7821 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ | |
7822 | ||
7823 | if (enable_ept) | |
7824 | vmx_enable_tdp(); | |
703c335d SC |
7825 | |
7826 | if (!enable_ept) | |
7827 | ept_lpage_level = 0; | |
7828 | else if (cpu_has_vmx_ept_1g_page()) | |
3bae0459 | 7829 | ept_lpage_level = PG_LEVEL_1G; |
703c335d | 7830 | else if (cpu_has_vmx_ept_2m_page()) |
3bae0459 | 7831 | ept_lpage_level = PG_LEVEL_2M; |
a3203381 | 7832 | else |
3bae0459 | 7833 | ept_lpage_level = PG_LEVEL_4K; |
83013059 | 7834 | kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level); |
a3203381 | 7835 | |
a3203381 SC |
7836 | /* |
7837 | * Only enable PML when hardware supports PML feature, and both EPT | |
7838 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
7839 | */ | |
7840 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
7841 | enable_pml = 0; | |
7842 | ||
7843 | if (!enable_pml) { | |
72b0eaa9 SC |
7844 | vmx_x86_ops.slot_enable_log_dirty = NULL; |
7845 | vmx_x86_ops.slot_disable_log_dirty = NULL; | |
7846 | vmx_x86_ops.flush_log_dirty = NULL; | |
7847 | vmx_x86_ops.enable_log_dirty_pt_masked = NULL; | |
fb04a1ed | 7848 | vmx_x86_ops.cpu_dirty_log_size = NULL; |
a3203381 SC |
7849 | } |
7850 | ||
7851 | if (!cpu_has_vmx_preemption_timer()) | |
804939ea | 7852 | enable_preemption_timer = false; |
a3203381 | 7853 | |
804939ea SC |
7854 | if (enable_preemption_timer) { |
7855 | u64 use_timer_freq = 5000ULL * 1000 * 1000; | |
a3203381 SC |
7856 | u64 vmx_msr; |
7857 | ||
7858 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
7859 | cpu_preemption_timer_multi = | |
7860 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
804939ea SC |
7861 | |
7862 | if (tsc_khz) | |
7863 | use_timer_freq = (u64)tsc_khz * 1000; | |
7864 | use_timer_freq >>= cpu_preemption_timer_multi; | |
7865 | ||
7866 | /* | |
7867 | * KVM "disables" the preemption timer by setting it to its max | |
7868 | * value. Don't use the timer if it might cause spurious exits | |
7869 | * at a rate faster than 0.1 Hz (of uninterrupted guest time). | |
7870 | */ | |
7871 | if (use_timer_freq > 0xffffffffu / 10) | |
7872 | enable_preemption_timer = false; | |
7873 | } | |
7874 | ||
7875 | if (!enable_preemption_timer) { | |
72b0eaa9 SC |
7876 | vmx_x86_ops.set_hv_timer = NULL; |
7877 | vmx_x86_ops.cancel_hv_timer = NULL; | |
7878 | vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit; | |
a3203381 SC |
7879 | } |
7880 | ||
8888cdd0 | 7881 | kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler); |
a3203381 SC |
7882 | |
7883 | kvm_mce_cap_supported |= MCG_LMCE_P; | |
7884 | ||
f99e3daf CP |
7885 | if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) |
7886 | return -EINVAL; | |
7887 | if (!enable_ept || !cpu_has_vmx_intel_pt()) | |
7888 | pt_mode = PT_MODE_SYSTEM; | |
7889 | ||
a3203381 | 7890 | if (nested) { |
3e8eaccc | 7891 | nested_vmx_setup_ctls_msrs(&vmcs_config.nested, |
a4443267 | 7892 | vmx_capability.ept); |
3e8eaccc | 7893 | |
6c1c6e58 | 7894 | r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); |
a3203381 SC |
7895 | if (r) |
7896 | return r; | |
7897 | } | |
7898 | ||
3ec6fd8c | 7899 | vmx_set_cpu_caps(); |
66a6950f | 7900 | |
a3203381 SC |
7901 | r = alloc_kvm_area(); |
7902 | if (r) | |
7903 | nested_vmx_hardware_unsetup(); | |
7904 | return r; | |
7905 | } | |
7906 | ||
d008dfdb | 7907 | static struct kvm_x86_init_ops vmx_init_ops __initdata = { |
6aa8b732 AK |
7908 | .cpu_has_kvm_support = cpu_has_kvm_support, |
7909 | .disabled_by_bios = vmx_disabled_by_bios, | |
002c7f7c | 7910 | .check_processor_compatibility = vmx_check_processor_compat, |
d008dfdb | 7911 | .hardware_setup = hardware_setup, |
57b119da | 7912 | |
d008dfdb | 7913 | .runtime_ops = &vmx_x86_ops, |
6aa8b732 AK |
7914 | }; |
7915 | ||
72c6d2db | 7916 | static void vmx_cleanup_l1d_flush(void) |
a47dd5f0 PB |
7917 | { |
7918 | if (vmx_l1d_flush_pages) { | |
7919 | free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); | |
7920 | vmx_l1d_flush_pages = NULL; | |
7921 | } | |
72c6d2db TG |
7922 | /* Restore state so sysfs ignores VMX */ |
7923 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; | |
a399477e KRW |
7924 | } |
7925 | ||
a7b9020b TG |
7926 | static void vmx_exit(void) |
7927 | { | |
7928 | #ifdef CONFIG_KEXEC_CORE | |
7929 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); | |
7930 | synchronize_rcu(); | |
7931 | #endif | |
7932 | ||
7933 | kvm_exit(); | |
7934 | ||
7935 | #if IS_ENABLED(CONFIG_HYPERV) | |
7936 | if (static_branch_unlikely(&enable_evmcs)) { | |
7937 | int cpu; | |
7938 | struct hv_vp_assist_page *vp_ap; | |
7939 | /* | |
7940 | * Reset everything to support using non-enlightened VMCS | |
7941 | * access later (e.g. when we reload the module with | |
7942 | * enlightened_vmcs=0) | |
7943 | */ | |
7944 | for_each_online_cpu(cpu) { | |
7945 | vp_ap = hv_get_vp_assist_page(cpu); | |
7946 | ||
7947 | if (!vp_ap) | |
7948 | continue; | |
7949 | ||
6f6a657c | 7950 | vp_ap->nested_control.features.directhypercall = 0; |
a7b9020b TG |
7951 | vp_ap->current_nested_vmcs = 0; |
7952 | vp_ap->enlighten_vmentry = 0; | |
7953 | } | |
7954 | ||
7955 | static_branch_disable(&enable_evmcs); | |
7956 | } | |
7957 | #endif | |
7958 | vmx_cleanup_l1d_flush(); | |
7959 | } | |
7960 | module_exit(vmx_exit); | |
7961 | ||
6aa8b732 AK |
7962 | static int __init vmx_init(void) |
7963 | { | |
dbef2808 | 7964 | int r, cpu; |
773e8a04 VK |
7965 | |
7966 | #if IS_ENABLED(CONFIG_HYPERV) | |
7967 | /* | |
7968 | * Enlightened VMCS usage should be recommended and the host needs | |
7969 | * to support eVMCS v1 or above. We can also disable eVMCS support | |
7970 | * with module parameter. | |
7971 | */ | |
7972 | if (enlightened_vmcs && | |
7973 | ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && | |
7974 | (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= | |
7975 | KVM_EVMCS_VERSION) { | |
7976 | int cpu; | |
7977 | ||
7978 | /* Check that we have assist pages on all online CPUs */ | |
7979 | for_each_online_cpu(cpu) { | |
7980 | if (!hv_get_vp_assist_page(cpu)) { | |
7981 | enlightened_vmcs = false; | |
7982 | break; | |
7983 | } | |
7984 | } | |
7985 | ||
7986 | if (enlightened_vmcs) { | |
7987 | pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); | |
7988 | static_branch_enable(&enable_evmcs); | |
7989 | } | |
6f6a657c VK |
7990 | |
7991 | if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) | |
7992 | vmx_x86_ops.enable_direct_tlbflush | |
7993 | = hv_enable_direct_tlbflush; | |
7994 | ||
773e8a04 VK |
7995 | } else { |
7996 | enlightened_vmcs = false; | |
7997 | } | |
7998 | #endif | |
7999 | ||
d008dfdb | 8000 | r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx), |
a7b9020b | 8001 | __alignof__(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 8002 | if (r) |
34a1cd60 | 8003 | return r; |
25c5f225 | 8004 | |
a7b9020b | 8005 | /* |
7db92e16 TG |
8006 | * Must be called after kvm_init() so enable_ept is properly set |
8007 | * up. Hand the parameter mitigation value in which was stored in | |
8008 | * the pre module init parser. If no parameter was given, it will | |
8009 | * contain 'auto' which will be turned into the default 'cond' | |
8010 | * mitigation mode. | |
8011 | */ | |
19a36d32 WL |
8012 | r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); |
8013 | if (r) { | |
8014 | vmx_exit(); | |
8015 | return r; | |
a47dd5f0 | 8016 | } |
25c5f225 | 8017 | |
dbef2808 VK |
8018 | for_each_possible_cpu(cpu) { |
8019 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8888cdd0 | 8020 | |
a3ff25fc | 8021 | pi_init_cpu(cpu); |
dbef2808 VK |
8022 | } |
8023 | ||
2965faa5 | 8024 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
8025 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
8026 | crash_vmclear_local_loaded_vmcss); | |
8027 | #endif | |
21ebf53b | 8028 | vmx_check_vmcs12_offsets(); |
8f536b76 | 8029 | |
3edd6839 | 8030 | /* |
b96e6506 MG |
8031 | * Shadow paging doesn't have a (further) performance penalty |
8032 | * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it | |
8033 | * by default | |
3edd6839 | 8034 | */ |
b96e6506 MG |
8035 | if (!enable_ept) |
8036 | allow_smaller_maxphyaddr = true; | |
3edd6839 | 8037 | |
fdef3ad1 | 8038 | return 0; |
6aa8b732 | 8039 | } |
a7b9020b | 8040 | module_init(vmx_init); |