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KVM: VMX: Initialize vmx->guest_msrs[] right after allocation
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / vmx / vmx.c
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20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732
AK		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * Copyright (C) 2006 Qumranet, Inc.
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
6aa8b732
AK		 14 */
15
199b118a
SC		 16#include <linux/frame.h>
17#include <linux/highmem.h>
18#include <linux/hrtimer.h>
19#include <linux/kernel.h>
edf88417 20#include <linux/kvm_host.h>
6aa8b732 21#include <linux/module.h>
c7addb90 22#include <linux/moduleparam.h>
e9bda3b3 23#include <linux/mod_devicetable.h>
199b118a 24#include <linux/mm.h>
199b118a 25#include <linux/sched.h>
b284909a 26#include <linux/sched/smt.h>
5a0e3ad6 27#include <linux/slab.h>
cafd6659 28#include <linux/tboot.h>
199b118a 29#include <linux/trace_events.h>
e495606d 30
199b118a 31#include <asm/apic.h>
fd8ca6da 32#include <asm/asm.h>
28b835d6 33#include <asm/cpu.h>
199b118a 34#include <asm/debugreg.h>
3b3be0d1 35#include <asm/desc.h>
952f07ec 36#include <asm/fpu/internal.h>
199b118a 37#include <asm/io.h>
efc64404 38#include <asm/irq_remapping.h>
199b118a
SC		 39#include <asm/kexec.h>
40#include <asm/perf_event.h>
41#include <asm/mce.h>
d6e41f11 42#include <asm/mmu_context.h>
773e8a04 43#include <asm/mshyperv.h>
199b118a
SC		 44#include <asm/spec-ctrl.h>
45#include <asm/virtext.h>
46#include <asm/vmx.h>
6aa8b732 47
3077c191 48#include "capabilities.h"
199b118a 49#include "cpuid.h"
4cebd747 50#include "evmcs.h"
199b118a
SC		 51#include "irq.h"
52#include "kvm_cache_regs.h"
53#include "lapic.h"
54#include "mmu.h"
55d2375e 55#include "nested.h"
89b0c9f5 56#include "ops.h"
25462f7f 57#include "pmu.h"
199b118a 58#include "trace.h"
cb1d474b 59#include "vmcs.h"
609363cf 60#include "vmcs12.h"
89b0c9f5 61#include "vmx.h"
199b118a 62#include "x86.h"
229456fc 63
6aa8b732
AK		 64MODULE_AUTHOR("Qumranet");
65MODULE_LICENSE("GPL");
66
e9bda3b3
JT		 67static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
69 {}
70};
71MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
72
2c4fd91d 73bool __read_mostly enable_vpid = 1;
736caefe 74module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 75
d02fcf50
PB		 76static bool __read_mostly enable_vnmi = 1;
77module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
78
2c4fd91d 79bool __read_mostly flexpriority_enabled = 1;
736caefe 80module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 81
2c4fd91d 82bool __read_mostly enable_ept = 1;
736caefe 83module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 84
2c4fd91d 85bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 86module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
88
2c4fd91d 89bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 90module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
91
a27685c3 92static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 93module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 94
476bc001 95static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 96module_param(fasteoi, bool, S_IRUGO);
97
5a71785d 98static bool __read_mostly enable_apicv = 1;
01e439be 99module_param(enable_apicv, bool, S_IRUGO);
83d4c286 100
801d3424
NHE		 101/*
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
105 */
1e58e5e5 106static bool __read_mostly nested = 1;
801d3424
NHE		 107module_param(nested, bool, S_IRUGO);
108
20300099
WL		 109static u64 __read_mostly host_xss;
110
2c4fd91d 111bool __read_mostly enable_pml = 1;
843e4330
KH		 112module_param_named(pml, enable_pml, bool, S_IRUGO);
113
6f2f8453
PB		 114static bool __read_mostly dump_invalid_vmcs = 0;
115module_param(dump_invalid_vmcs, bool, 0644);
116
904e14fb
PB		 117#define MSR_BITMAP_MODE_X2APIC 1
118#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 119
64903d61
HZ		 120#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
121
64672c95
YJ		 122/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123static int __read_mostly cpu_preemption_timer_multi;
124static bool __read_mostly enable_preemption_timer = 1;
125#ifdef CONFIG_X86_64
126module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127#endif
128
3de6347b 129#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 130#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131#define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 134#define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 137
5dc1f044 138#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 139#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
141
78ac8b47
AK		 142#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
143
bf8c55d8
CP		 144#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
148
149#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151
4b8d54f9
ZE		 152/*
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 156 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
162 */
c8e88717 163static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 164module_param(ple_gap, uint, 0444);
b4a2d31d 165
7fbc85a5
BM		 166static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167module_param(ple_window, uint, 0444);
4b8d54f9 168
b4a2d31d 169/* Default doubles per-vcpu window every exit. */
c8e88717 170static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 171module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 172
173/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 174static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 175module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 176
177/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 178static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, uint, 0444);
b4a2d31d 180
f99e3daf
CP		 181/* Default is SYSTEM mode, 1 for host-guest mode */
182int __read_mostly pt_mode = PT_MODE_SYSTEM;
183module_param(pt_mode, int, S_IRUGO);
184
a399477e 185static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 186static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 187static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 188
7db92e16
TG		 189/* Storage for pre module init parameter parsing */
190static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 191
192static const struct {
193 const char *option;
0027ff2a 194 bool for_parse;
a399477e 195} vmentry_l1d_param[] = {
0027ff2a
PB		 196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 202};
203
7db92e16
TG		 204#define L1D_CACHE_ORDER 4
205static void *vmx_l1d_flush_pages;
206
207static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 208{
7db92e16 209 struct page *page;
288d152c 210 unsigned int i;
a399477e 211
19a36d32
WL		 212 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
214 return 0;
215 }
216
7db92e16
TG		 217 if (!enable_ept) {
218 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
219 return 0;
a399477e
KRW		 220 }
221
d806afa4
YW		 222 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
223 u64 msr;
224
225 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
226 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
228 return 0;
229 }
230 }
8e0b2b91 231
d90a7a0e
JK		 232 /* If set to auto use the default l1tf mitigation method */
233 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
234 switch (l1tf_mitigation) {
235 case L1TF_MITIGATION_OFF:
236 l1tf = VMENTER_L1D_FLUSH_NEVER;
237 break;
238 case L1TF_MITIGATION_FLUSH_NOWARN:
239 case L1TF_MITIGATION_FLUSH:
240 case L1TF_MITIGATION_FLUSH_NOSMT:
241 l1tf = VMENTER_L1D_FLUSH_COND;
242 break;
243 case L1TF_MITIGATION_FULL:
244 case L1TF_MITIGATION_FULL_FORCE:
245 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
246 break;
247 }
248 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
249 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
250 }
251
7db92e16
TG		 252 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
253 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 254 /*
255 * This allocation for vmx_l1d_flush_pages is not tied to a VM
256 * lifetime and so should not be charged to a memcg.
257 */
7db92e16
TG		 258 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
259 if (!page)
260 return -ENOMEM;
261 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 262
263 /*
264 * Initialize each page with a different pattern in
265 * order to protect against KSM in the nested
266 * virtualization case.
267 */
268 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
269 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
270 PAGE_SIZE);
271 }
7db92e16
TG		 272 }
273
274 l1tf_vmx_mitigation = l1tf;
275
895ae47f
TG		 276 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
277 static_branch_enable(&vmx_l1d_should_flush);
278 else
279 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 280
427362a1
NS		 281 if (l1tf == VMENTER_L1D_FLUSH_COND)
282 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 283 else
427362a1 284 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 285 return 0;
286}
287
288static int vmentry_l1d_flush_parse(const char *s)
289{
290 unsigned int i;
291
292 if (s) {
293 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 294 if (vmentry_l1d_param[i].for_parse &&
295 sysfs_streq(s, vmentry_l1d_param[i].option))
296 return i;
7db92e16
TG		 297 }
298 }
a399477e
KRW		 299 return -EINVAL;
300}
301
7db92e16
TG		 302static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
303{
dd4bfa73 304 int l1tf, ret;
7db92e16 305
7db92e16
TG		 306 l1tf = vmentry_l1d_flush_parse(s);
307 if (l1tf < 0)
308 return l1tf;
309
0027ff2a
PB		 310 if (!boot_cpu_has(X86_BUG_L1TF))
311 return 0;
312
7db92e16
TG		 313 /*
314 * Has vmx_init() run already? If not then this is the pre init
315 * parameter parsing. In that case just store the value and let
316 * vmx_init() do the proper setup after enable_ept has been
317 * established.
318 */
319 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
320 vmentry_l1d_flush_param = l1tf;
321 return 0;
322 }
323
dd4bfa73
TG		 324 mutex_lock(&vmx_l1d_flush_mutex);
325 ret = vmx_setup_l1d_flush(l1tf);
326 mutex_unlock(&vmx_l1d_flush_mutex);
327 return ret;
7db92e16
TG		 328}
329
a399477e
KRW		 330static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
331{
0027ff2a
PB		 332 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
333 return sprintf(s, "???\n");
334
7db92e16 335 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 336}
337
338static const struct kernel_param_ops vmentry_l1d_flush_ops = {
339 .set = vmentry_l1d_flush_set,
340 .get = vmentry_l1d_flush_get,
341};
895ae47f 342module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 343
d99e4152
GN		 344static bool guest_state_valid(struct kvm_vcpu *vcpu);
345static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 346static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 347 u32 msr, int type);
75880a01 348
453eafbe
SC		 349void vmx_vmexit(void);
350
52a9fcbc
SC		 351#define vmx_insn_failed(fmt...) \
352do { \
353 WARN_ONCE(1, fmt); \
354 pr_warn_ratelimited(fmt); \
355} while (0)
356
6e202097
SC		 357asmlinkage void vmread_error(unsigned long field, bool fault)
358{
359 if (fault)
360 kvm_spurious_fault();
361 else
362 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
363}
364
52a9fcbc
SC		 365noinline void vmwrite_error(unsigned long field, unsigned long value)
366{
367 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
368 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
369}
370
371noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
372{
373 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
374}
375
376noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
377{
378 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
379}
380
381noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
382{
383 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
384 ext, vpid, gva);
385}
386
387noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
388{
389 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
390 ext, eptp, gpa);
391}
392
6aa8b732 393static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 394DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 395/*
396 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
397 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
398 */
399static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 400
bf9f6ac8
FW		 401/*
402 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
403 * can find which vCPU should be waken up.
404 */
405static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
406static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
407
2384d2b3
SY		 408static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
409static DEFINE_SPINLOCK(vmx_vpid_lock);
410
3077c191
SC		 411struct vmcs_config vmcs_config;
412struct vmx_capability vmx_capability;
d56f546d 413
6aa8b732
AK		 414#define VMX_SEGMENT_FIELD(seg) \
415 [VCPU_SREG_##seg] = { \
416 .selector = GUEST_##seg##_SELECTOR, \
417 .base = GUEST_##seg##_BASE, \
418 .limit = GUEST_##seg##_LIMIT, \
419 .ar_bytes = GUEST_##seg##_AR_BYTES, \
420 }
421
772e0318 422static const struct kvm_vmx_segment_field {
6aa8b732
AK		 423 unsigned selector;
424 unsigned base;
425 unsigned limit;
426 unsigned ar_bytes;
427} kvm_vmx_segment_fields[] = {
428 VMX_SEGMENT_FIELD(CS),
429 VMX_SEGMENT_FIELD(DS),
430 VMX_SEGMENT_FIELD(ES),
431 VMX_SEGMENT_FIELD(FS),
432 VMX_SEGMENT_FIELD(GS),
433 VMX_SEGMENT_FIELD(SS),
434 VMX_SEGMENT_FIELD(TR),
435 VMX_SEGMENT_FIELD(LDTR),
436};
437
cf3646eb 438u64 host_efer;
2342080c 439static unsigned long host_idt_base;
26bb0981 440
4d56c8a7 441/*
898a811f
JM		 442 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
443 * will emulate SYSCALL in legacy mode if the vendor string in guest
444 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
445 * support this emulation, IA32_STAR must always be included in
446 * vmx_msr_index[], even in i386 builds.
4d56c8a7 447 */
cf3646eb 448const u32 vmx_msr_index[] = {
05b3e0c2 449#ifdef CONFIG_X86_64
44ea2b17 450 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 451#endif
8c06585d 452 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 453};
6aa8b732 454
773e8a04
VK		 455#if IS_ENABLED(CONFIG_HYPERV)
456static bool __read_mostly enlightened_vmcs = true;
457module_param(enlightened_vmcs, bool, 0444);
458
877ad952
TL		 459/* check_ept_pointer() should be under protection of ept_pointer_lock. */
460static void check_ept_pointer_match(struct kvm *kvm)
461{
462 struct kvm_vcpu *vcpu;
463 u64 tmp_eptp = INVALID_PAGE;
464 int i;
465
466 kvm_for_each_vcpu(i, vcpu, kvm) {
467 if (!VALID_PAGE(tmp_eptp)) {
468 tmp_eptp = to_vmx(vcpu)->ept_pointer;
469 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
470 to_kvm_vmx(kvm)->ept_pointers_match
471 = EPT_POINTERS_MISMATCH;
472 return;
473 }
474 }
475
476 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
477}
478
8997f657 479static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 480 void *data)
481{
482 struct kvm_tlb_range *range = data;
483
484 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
485 range->pages);
486}
487
488static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
489 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
490{
491 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
492
493 /*
494 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
495 * of the base of EPT PML4 table, strip off EPT configuration
496 * information.
497 */
498 if (range)
499 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
500 kvm_fill_hv_flush_list_func, (void *)range);
501 else
502 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
503}
504
505static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
506 struct kvm_tlb_range *range)
877ad952 507{
a5c214da 508 struct kvm_vcpu *vcpu;
b7c1c226 509 int ret = 0, i;
877ad952
TL		 510
511 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
512
513 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
514 check_ept_pointer_match(kvm);
515
516 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 517 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 518 /* If ept_pointer is invalid pointer, bypass flush request. */
519 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
520 ret |= __hv_remote_flush_tlb_with_range(
521 kvm, vcpu, range);
53963a70 522 }
a5c214da 523 } else {
1f3a3e46
LT		 524 ret = __hv_remote_flush_tlb_with_range(kvm,
525 kvm_get_vcpu(kvm, 0), range);
877ad952 526 }
877ad952 527
877ad952
TL		 528 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
529 return ret;
530}
1f3a3e46
LT		 531static int hv_remote_flush_tlb(struct kvm *kvm)
532{
533 return hv_remote_flush_tlb_with_range(kvm, NULL);
534}
535
6f6a657c
VK		 536static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
537{
538 struct hv_enlightened_vmcs *evmcs;
539 struct hv_partition_assist_pg **p_hv_pa_pg =
540 &vcpu->kvm->arch.hyperv.hv_pa_pg;
541 /*
542 * Synthetic VM-Exit is not enabled in current code and so All
543 * evmcs in singe VM shares same assist page.
544 */
cab01850 545 if (!*p_hv_pa_pg)
6f6a657c 546 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
cab01850
VK		 547
548 if (!*p_hv_pa_pg)
549 return -ENOMEM;
6f6a657c
VK		 550
551 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
552
553 evmcs->partition_assist_page =
554 __pa(*p_hv_pa_pg);
cab01850 555 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
6f6a657c
VK		 556 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
557
6f6a657c
VK		 558 return 0;
559}
560
773e8a04
VK		 561#endif /* IS_ENABLED(CONFIG_HYPERV) */
562
64672c95
YJ		 563/*
564 * Comment's format: document - errata name - stepping - processor name.
565 * Refer from
566 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
567 */
568static u32 vmx_preemption_cpu_tfms[] = {
569/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
5700x000206E6,
571/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
572/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
573/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5740x00020652,
575/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5760x00020655,
577/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
578/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
579/*
580 * 320767.pdf - AAP86 - B1 -
581 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
582 */
5830x000106E5,
584/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5850x000106A0,
586/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5870x000106A1,
588/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5890x000106A4,
590 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
591 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
592 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5930x000106A5,
3d82c565
WH		 594 /* Xeon E3-1220 V2 */
5950x000306A8,
64672c95
YJ		 596};
597
598static inline bool cpu_has_broken_vmx_preemption_timer(void)
599{
600 u32 eax = cpuid_eax(0x00000001), i;
601
602 /* Clear the reserved bits */
603 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 604 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 605 if (eax == vmx_preemption_cpu_tfms[i])
606 return true;
607
608 return false;
609}
610
35754c98 611static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 612{
35754c98 613 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 614}
615
04547156
SY		 616static inline bool report_flexpriority(void)
617{
618 return flexpriority_enabled;
619}
620
97b7ead3 621static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 622{
623 int i;
624
a2fa3e9f 625 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 626 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 627 return i;
628 return -1;
629}
630
97b7ead3 631struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 632{
633 int i;
634
8b9cf98c 635 i = __find_msr_index(vmx, msr);
a75beee6 636 if (i >= 0)
a2fa3e9f 637 return &vmx->guest_msrs[i];
8b6d44c7 638 return NULL;
7725f0ba
AK		 639}
640
7c97fcb3
SC		 641void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
642{
643 vmcs_clear(loaded_vmcs->vmcs);
644 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
645 vmcs_clear(loaded_vmcs->shadow_vmcs);
646 loaded_vmcs->cpu = -1;
647 loaded_vmcs->launched = 0;
648}
649
2965faa5 650#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 651/*
652 * This bitmap is used to indicate whether the vmclear
653 * operation is enabled on all cpus. All disabled by
654 * default.
655 */
656static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
657
658static inline void crash_enable_local_vmclear(int cpu)
659{
660 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
661}
662
663static inline void crash_disable_local_vmclear(int cpu)
664{
665 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
666}
667
668static inline int crash_local_vmclear_enabled(int cpu)
669{
670 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
671}
672
673static void crash_vmclear_local_loaded_vmcss(void)
674{
675 int cpu = raw_smp_processor_id();
676 struct loaded_vmcs *v;
677
678 if (!crash_local_vmclear_enabled(cpu))
679 return;
680
681 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
682 loaded_vmcss_on_cpu_link)
683 vmcs_clear(v->vmcs);
684}
685#else
686static inline void crash_enable_local_vmclear(int cpu) { }
687static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 688#endif /* CONFIG_KEXEC_CORE */
8f536b76 689
d462b819 690static void __loaded_vmcs_clear(void *arg)
6aa8b732 691{
d462b819 692 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 693 int cpu = raw_smp_processor_id();
6aa8b732 694
d462b819
NHE		 695 if (loaded_vmcs->cpu != cpu)
696 return; /* vcpu migration can race with cpu offline */
697 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 698 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 699 crash_disable_local_vmclear(cpu);
d462b819 700 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 701
702 /*
703 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
704 * is before setting loaded_vmcs->vcpu to -1 which is done in
705 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
706 * then adds the vmcs into percpu list before it is deleted.
707 */
708 smp_wmb();
709
d462b819 710 loaded_vmcs_init(loaded_vmcs);
8f536b76 711 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 712}
713
89b0c9f5 714void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 715{
e6c7d321
XG		 716 int cpu = loaded_vmcs->cpu;
717
718 if (cpu != -1)
719 smp_call_function_single(cpu,
720 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 721}
722
2fb92db1
AK		 723static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
724 unsigned field)
725{
726 bool ret;
727 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
728
cb3c1e2f
SC		 729 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
730 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
2fb92db1
AK		 731 vmx->segment_cache.bitmask = 0;
732 }
733 ret = vmx->segment_cache.bitmask & mask;
734 vmx->segment_cache.bitmask |= mask;
735 return ret;
736}
737
738static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
739{
740 u16 *p = &vmx->segment_cache.seg[seg].selector;
741
742 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
743 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
744 return *p;
745}
746
747static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
748{
749 ulong *p = &vmx->segment_cache.seg[seg].base;
750
751 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
752 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
753 return *p;
754}
755
756static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
757{
758 u32 *p = &vmx->segment_cache.seg[seg].limit;
759
760 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
761 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
762 return *p;
763}
764
765static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
766{
767 u32 *p = &vmx->segment_cache.seg[seg].ar;
768
769 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
770 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
771 return *p;
772}
773
97b7ead3 774void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 775{
776 u32 eb;
777
fd7373cc 778 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 779 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 780 /*
781 * Guest access to VMware backdoor ports could legitimately
782 * trigger #GP because of TSS I/O permission bitmap.
783 * We intercept those #GP and allow access to them anyway
784 * as VMware does.
785 */
786 if (enable_vmware_backdoor)
787 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 788 if ((vcpu->guest_debug &
789 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
790 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
791 eb |= 1u << BP_VECTOR;
7ffd92c5 792 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 793 eb = ~0;
089d034e 794 if (enable_ept)
1439442c 795 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 796
797 /* When we are running a nested L2 guest and L1 specified for it a
798 * certain exception bitmap, we must trap the same exceptions and pass
799 * them to L1. When running L2, we will only handle the exceptions
800 * specified above if L1 did not want them.
801 */
802 if (is_guest_mode(vcpu))
803 eb |= get_vmcs12(vcpu)->exception_bitmap;
804
abd3f2d6
AK		 805 vmcs_write32(EXCEPTION_BITMAP, eb);
806}
807
d28b387f
KA		 808/*
809 * Check if MSR is intercepted for currently loaded MSR bitmap.
810 */
811static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
812{
813 unsigned long *msr_bitmap;
814 int f = sizeof(unsigned long);
815
816 if (!cpu_has_vmx_msr_bitmap())
817 return true;
818
819 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
820
821 if (msr <= 0x1fff) {
822 return !!test_bit(msr, msr_bitmap + 0x800 / f);
823 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
824 msr &= 0x1fff;
825 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
826 }
827
828 return true;
829}
830
2961e876
GN		 831static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
832 unsigned long entry, unsigned long exit)
8bf00a52 833{
2961e876
GN		 834 vm_entry_controls_clearbit(vmx, entry);
835 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 836}
837
ca83b4a7
KRW		 838static int find_msr(struct vmx_msrs *m, unsigned int msr)
839{
840 unsigned int i;
841
842 for (i = 0; i < m->nr; ++i) {
843 if (m->val[i].index == msr)
844 return i;
845 }
846 return -ENOENT;
847}
848
61d2ef2c
AK		 849static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
850{
ca83b4a7 851 int i;
61d2ef2c
AK		 852 struct msr_autoload *m = &vmx->msr_autoload;
853
8bf00a52
GN		 854 switch (msr) {
855 case MSR_EFER:
c73da3fc 856 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 857 clear_atomic_switch_msr_special(vmx,
858 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 859 VM_EXIT_LOAD_IA32_EFER);
860 return;
861 }
862 break;
863 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 864 if (cpu_has_load_perf_global_ctrl()) {
2961e876 865 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 866 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
867 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
868 return;
869 }
870 break;
110312c8 871 }
ca83b4a7
KRW		 872 i = find_msr(&m->guest, msr);
873 if (i < 0)
31907093 874 goto skip_guest;
33966dd6 875 --m->guest.nr;
33966dd6 876 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 877 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 878
31907093
KRW		 879skip_guest:
880 i = find_msr(&m->host, msr);
881 if (i < 0)
61d2ef2c 882 return;
31907093
KRW		 883
884 --m->host.nr;
885 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 886 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 887}
888
2961e876
GN		 889static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
890 unsigned long entry, unsigned long exit,
891 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
892 u64 guest_val, u64 host_val)
8bf00a52
GN		 893{
894 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 895 if (host_val_vmcs != HOST_IA32_EFER)
896 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 897 vm_entry_controls_setbit(vmx, entry);
898 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 899}
900
61d2ef2c 901static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 902 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 903{
989e3992 904 int i, j = 0;
61d2ef2c
AK		 905 struct msr_autoload *m = &vmx->msr_autoload;
906
8bf00a52
GN		 907 switch (msr) {
908 case MSR_EFER:
c73da3fc 909 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 910 add_atomic_switch_msr_special(vmx,
911 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 912 VM_EXIT_LOAD_IA32_EFER,
913 GUEST_IA32_EFER,
914 HOST_IA32_EFER,
915 guest_val, host_val);
916 return;
917 }
918 break;
919 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 920 if (cpu_has_load_perf_global_ctrl()) {
2961e876 921 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 922 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
923 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
924 GUEST_IA32_PERF_GLOBAL_CTRL,
925 HOST_IA32_PERF_GLOBAL_CTRL,
926 guest_val, host_val);
927 return;
928 }
929 break;
7099e2e1
RK		 930 case MSR_IA32_PEBS_ENABLE:
931 /* PEBS needs a quiescent period after being disabled (to write
932 * a record). Disabling PEBS through VMX MSR swapping doesn't
933 * provide that period, so a CPU could write host's record into
934 * guest's memory.
935 */
936 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 937 }
938
ca83b4a7 939 i = find_msr(&m->guest, msr);
989e3992
KRW		 940 if (!entry_only)
941 j = find_msr(&m->host, msr);
61d2ef2c 942
98ae70cc
XL		 943 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
944 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
60266204 945 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 946 "Can't add msr %x\n", msr);
947 return;
61d2ef2c 948 }
31907093 949 if (i < 0) {
ca83b4a7 950 i = m->guest.nr++;
33966dd6 951 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 952 }
989e3992
KRW		 953 m->guest.val[i].index = msr;
954 m->guest.val[i].value = guest_val;
955
956 if (entry_only)
957 return;
61d2ef2c 958
31907093
KRW		 959 if (j < 0) {
960 j = m->host.nr++;
33966dd6 961 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 962 }
31907093
KRW		 963 m->host.val[j].index = msr;
964 m->host.val[j].value = host_val;
61d2ef2c
AK		 965}
966
92c0d900 967static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 968{
844a5fe2
PB		 969 u64 guest_efer = vmx->vcpu.arch.efer;
970 u64 ignore_bits = 0;
971
972 if (!enable_ept) {
973 /*
974 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
975 * host CPUID is more efficient than testing guest CPUID
976 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
977 */
978 if (boot_cpu_has(X86_FEATURE_SMEP))
979 guest_efer |= EFER_NX;
980 else if (!(guest_efer & EFER_NX))
981 ignore_bits |= EFER_NX;
982 }
3a34a881 983
51c6cf66 984 /*
844a5fe2 985 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 986 */
844a5fe2 987 ignore_bits |= EFER_SCE;
51c6cf66
AK		 988#ifdef CONFIG_X86_64
989 ignore_bits |= EFER_LMA | EFER_LME;
990 /* SCE is meaningful only in long mode on Intel */
991 if (guest_efer & EFER_LMA)
992 ignore_bits &= ~(u64)EFER_SCE;
993#endif
84ad33ef 994
f6577a5f
AL		 995 /*
996 * On EPT, we can't emulate NX, so we must switch EFER atomically.
997 * On CPUs that support "load IA32_EFER", always switch EFER
998 * atomically, since it's faster than switching it manually.
999 */
c73da3fc 1000 if (cpu_has_load_ia32_efer() ||
f6577a5f 1001 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1002 if (!(guest_efer & EFER_LMA))
1003 guest_efer &= ~EFER_LME;
54b98bff
AL		 1004 if (guest_efer != host_efer)
1005 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 1006 guest_efer, host_efer, false);
02343cf2
SC		 1007 else
1008 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 1009 return false;
844a5fe2 1010 } else {
02343cf2
SC		 1011 clear_atomic_switch_msr(vmx, MSR_EFER);
1012
844a5fe2
PB		 1013 guest_efer &= ~ignore_bits;
1014 guest_efer |= host_efer & ignore_bits;
1015
1016 vmx->guest_msrs[efer_offset].data = guest_efer;
1017 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 1018
844a5fe2
PB		 1019 return true;
1020 }
51c6cf66
AK		 1021}
1022
e28baead
AL		 1023#ifdef CONFIG_X86_32
1024/*
1025 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1026 * VMCS rather than the segment table. KVM uses this helper to figure
1027 * out the current bases to poke them into the VMCS before entry.
1028 */
2d49ec72
GN		 1029static unsigned long segment_base(u16 selector)
1030{
8c2e41f7 1031 struct desc_struct *table;
2d49ec72
GN		 1032 unsigned long v;
1033
8c2e41f7 1034 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1035 return 0;
1036
45fc8757 1037 table = get_current_gdt_ro();
2d49ec72 1038
8c2e41f7 1039 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 1040 u16 ldt_selector = kvm_read_ldt();
1041
8c2e41f7 1042 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1043 return 0;
1044
8c2e41f7 1045 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 1046 }
8c2e41f7 1047 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 1048 return v;
1049}
e28baead 1050#endif
2d49ec72 1051
2ef444f1
CP		 1052static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1053{
1054 u32 i;
1055
1056 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1057 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1058 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1059 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1060 for (i = 0; i < addr_range; i++) {
1061 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1062 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1063 }
1064}
1065
1066static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1067{
1068 u32 i;
1069
1070 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1071 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1072 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1073 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1074 for (i = 0; i < addr_range; i++) {
1075 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1076 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1077 }
1078}
1079
1080static void pt_guest_enter(struct vcpu_vmx *vmx)
1081{
1082 if (pt_mode == PT_MODE_SYSTEM)
1083 return;
1084
2ef444f1 1085 /*
b08c2896
CP		 1086 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1087 * Save host state before VM entry.
2ef444f1 1088 */
b08c2896 1089 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1090 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1091 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1092 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1093 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1094 }
1095}
1096
1097static void pt_guest_exit(struct vcpu_vmx *vmx)
1098{
1099 if (pt_mode == PT_MODE_SYSTEM)
1100 return;
1101
1102 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1103 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1104 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1105 }
1106
1107 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1108 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1109}
1110
13b964a2
SC		 1111void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1112 unsigned long fs_base, unsigned long gs_base)
1113{
1114 if (unlikely(fs_sel != host->fs_sel)) {
1115 if (!(fs_sel & 7))
1116 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1117 else
1118 vmcs_write16(HOST_FS_SELECTOR, 0);
1119 host->fs_sel = fs_sel;
1120 }
1121 if (unlikely(gs_sel != host->gs_sel)) {
1122 if (!(gs_sel & 7))
1123 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1124 else
1125 vmcs_write16(HOST_GS_SELECTOR, 0);
1126 host->gs_sel = gs_sel;
1127 }
1128 if (unlikely(fs_base != host->fs_base)) {
1129 vmcs_writel(HOST_FS_BASE, fs_base);
1130 host->fs_base = fs_base;
1131 }
1132 if (unlikely(gs_base != host->gs_base)) {
1133 vmcs_writel(HOST_GS_BASE, gs_base);
1134 host->gs_base = gs_base;
1135 }
1136}
1137
97b7ead3 1138void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1139{
04d2cc77 1140 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1141 struct vmcs_host_state *host_state;
51e8a8cc 1142#ifdef CONFIG_X86_64
35060ed6 1143 int cpu = raw_smp_processor_id();
51e8a8cc 1144#endif
e368b875
SC		 1145 unsigned long fs_base, gs_base;
1146 u16 fs_sel, gs_sel;
26bb0981 1147 int i;
04d2cc77 1148
d264ee0c
SC		 1149 vmx->req_immediate_exit = false;
1150
f48b4711
LA		 1151 /*
1152 * Note that guest MSRs to be saved/restored can also be changed
1153 * when guest state is loaded. This happens when guest transitions
1154 * to/from long-mode by setting MSR_EFER.LMA.
1155 */
b464f57e
PB		 1156 if (!vmx->guest_msrs_ready) {
1157 vmx->guest_msrs_ready = true;
f48b4711
LA		 1158 for (i = 0; i < vmx->save_nmsrs; ++i)
1159 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1160 vmx->guest_msrs[i].data,
1161 vmx->guest_msrs[i].mask);
1162
1163 }
b464f57e 1164 if (vmx->guest_state_loaded)
33ed6329
AK		 1165 return;
1166
b464f57e 1167 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1168
33ed6329
AK		 1169 /*
1170 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1171 * allow segment selectors with cpl > 0 or ti == 1.
1172 */
d7ee039e 1173 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1174
1175#ifdef CONFIG_X86_64
d7ee039e
SC		 1176 savesegment(ds, host_state->ds_sel);
1177 savesegment(es, host_state->es_sel);
e368b875
SC		 1178
1179 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1180 if (likely(is_64bit_mm(current->mm))) {
1181 save_fsgs_for_kvm();
e368b875
SC		 1182 fs_sel = current->thread.fsindex;
1183 gs_sel = current->thread.gsindex;
b062b794 1184 fs_base = current->thread.fsbase;
e368b875 1185 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1186 } else {
e368b875
SC		 1187 savesegment(fs, fs_sel);
1188 savesegment(gs, gs_sel);
b062b794 1189 fs_base = read_msr(MSR_FS_BASE);
e368b875 1190 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1191 }
b2da15ac 1192
4679b61f 1193 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1194#else
e368b875
SC		 1195 savesegment(fs, fs_sel);
1196 savesegment(gs, gs_sel);
1197 fs_base = segment_base(fs_sel);
1198 gs_base = segment_base(gs_sel);
707c0874 1199#endif
e368b875 1200
13b964a2 1201 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
b464f57e 1202 vmx->guest_state_loaded = true;
33ed6329
AK		 1203}
1204
6d6095bd 1205static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1206{
d7ee039e
SC		 1207 struct vmcs_host_state *host_state;
1208
b464f57e 1209 if (!vmx->guest_state_loaded)
33ed6329
AK		 1210 return;
1211
b464f57e 1212 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1213
e1beb1d3 1214 ++vmx->vcpu.stat.host_state_reload;
bd9966de 1215
c8770e7b 1216#ifdef CONFIG_X86_64
4679b61f 1217 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1218#endif
d7ee039e
SC		 1219 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1220 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1221#ifdef CONFIG_X86_64
d7ee039e 1222 load_gs_index(host_state->gs_sel);
9581d442 1223#else
d7ee039e 1224 loadsegment(gs, host_state->gs_sel);
33ed6329 1225#endif
33ed6329 1226 }
d7ee039e
SC		 1227 if (host_state->fs_sel & 7)
1228 loadsegment(fs, host_state->fs_sel);
b2da15ac 1229#ifdef CONFIG_X86_64
d7ee039e
SC		 1230 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1231 loadsegment(ds, host_state->ds_sel);
1232 loadsegment(es, host_state->es_sel);
b2da15ac 1233 }
b2da15ac 1234#endif
b7ffc44d 1235 invalidate_tss_limit();
44ea2b17 1236#ifdef CONFIG_X86_64
c8770e7b 1237 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1238#endif
45fc8757 1239 load_fixmap_gdt(raw_smp_processor_id());
b464f57e
PB		 1240 vmx->guest_state_loaded = false;
1241 vmx->guest_msrs_ready = false;
33ed6329
AK		 1242}
1243
678e315e
SC		 1244#ifdef CONFIG_X86_64
1245static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1246{
4679b61f 1247 preempt_disable();
b464f57e 1248 if (vmx->guest_state_loaded)
4679b61f
PB		 1249 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1250 preempt_enable();
678e315e 1251 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1252}
1253
678e315e
SC		 1254static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1255{
4679b61f 1256 preempt_disable();
b464f57e 1257 if (vmx->guest_state_loaded)
4679b61f
PB		 1258 wrmsrl(MSR_KERNEL_GS_BASE, data);
1259 preempt_enable();
678e315e
SC		 1260 vmx->msr_guest_kernel_gs_base = data;
1261}
1262#endif
1263
28b835d6
FW		 1264static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1265{
1266 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1267 struct pi_desc old, new;
1268 unsigned int dest;
1269
31afb2ea
PB		 1270 /*
1271 * In case of hot-plug or hot-unplug, we may have to undo
1272 * vmx_vcpu_pi_put even if there is no assigned device. And we
1273 * always keep PI.NDST up to date for simplicity: it makes the
1274 * code easier, and CPU migration is not a fast path.
1275 */
1276 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1277 return;
1278
31afb2ea 1279 /* The full case. */
28b835d6
FW		 1280 do {
1281 old.control = new.control = pi_desc->control;
1282
31afb2ea 1283 dest = cpu_physical_id(cpu);
28b835d6 1284
31afb2ea
PB		 1285 if (x2apic_enabled())
1286 new.ndst = dest;
1287 else
1288 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1289
28b835d6 1290 new.sn = 0;
c0a1666b
PB		 1291 } while (cmpxchg64(&pi_desc->control, old.control,
1292 new.control) != old.control);
c112b5f5
LK		 1293
1294 /*
1295 * Clear SN before reading the bitmap. The VT-d firmware
1296 * writes the bitmap and reads SN atomically (5.2.3 in the
1297 * spec), so it doesn't really have a memory barrier that
1298 * pairs with this, but we cannot do that and we need one.
1299 */
1300 smp_mb__after_atomic();
1301
1302 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1303 pi_set_on(pi_desc);
28b835d6 1304}
1be0e61c 1305
8ef863e6 1306void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1307{
a2fa3e9f 1308 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1309 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1310
b80c76ec 1311 if (!already_loaded) {
fe0e80be 1312 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1313 local_irq_disable();
8f536b76 1314 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1315
1316 /*
1317 * Read loaded_vmcs->cpu should be before fetching
1318 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1319 * See the comments in __loaded_vmcs_clear().
1320 */
1321 smp_rmb();
1322
d462b819
NHE		 1323 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1324 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1325 crash_enable_local_vmclear(cpu);
92fe13be 1326 local_irq_enable();
b80c76ec
JM		 1327 }
1328
1329 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1330 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1331 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1332 indirect_branch_prediction_barrier();
b80c76ec
JM		 1333 }
1334
1335 if (!already_loaded) {
59c58ceb 1336 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1337 unsigned long sysenter_esp;
1338
1339 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1340
6aa8b732
AK		 1341 /*
1342 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1343 * processors. See 22.2.4.
6aa8b732 1344 */
e0c23063 1345 vmcs_writel(HOST_TR_BASE,
72f5e08d 1346 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1347 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 1348
b7ffc44d
AL		 1349 /*
1350 * VM exits change the host TR limit to 0x67 after a VM
1351 * exit. This is okay, since 0x67 covers everything except
1352 * the IO bitmap and have have code to handle the IO bitmap
1353 * being lost after a VM exit.
1354 */
1355 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1356
6aa8b732
AK		 1357 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1358 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1359
d462b819 1360 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1361 }
28b835d6 1362
2680d6da
OH		 1363 /* Setup TSC multiplier */
1364 if (kvm_has_tsc_control &&
c95ba92a
PF		 1365 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1366 decache_tsc_multiplier(vmx);
8ef863e6
SC		 1367}
1368
1369/*
1370 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1371 * vcpu mutex is already taken.
1372 */
1373void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1374{
1375 struct vcpu_vmx *vmx = to_vmx(vcpu);
1376
1377 vmx_vcpu_load_vmcs(vcpu, cpu);
2680d6da 1378
28b835d6 1379 vmx_vcpu_pi_load(vcpu, cpu);
8ef863e6 1380
1be0e61c 1381 vmx->host_pkru = read_pkru();
74c55931 1382 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1383}
1384
1385static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1386{
1387 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1388
1389 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1390 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1391 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1392 return;
1393
1394 /* Set SN when the vCPU is preempted */
1395 if (vcpu->preempted)
1396 pi_set_sn(pi_desc);
6aa8b732
AK		 1397}
1398
13b964a2 1399static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1400{
28b835d6
FW		 1401 vmx_vcpu_pi_put(vcpu);
1402
6d6095bd 1403 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1404}
1405
f244deed
WL		 1406static bool emulation_required(struct kvm_vcpu *vcpu)
1407{
1408 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1409}
1410
edcafe3c
AK		 1411static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1412
97b7ead3 1413unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1414{
e7bddc52 1415 struct vcpu_vmx *vmx = to_vmx(vcpu);
78ac8b47 1416 unsigned long rflags, save_rflags;
345dcaa8 1417
cb3c1e2f
SC		 1418 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1419 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
6de12732 1420 rflags = vmcs_readl(GUEST_RFLAGS);
e7bddc52 1421 if (vmx->rmode.vm86_active) {
6de12732 1422 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
e7bddc52 1423 save_rflags = vmx->rmode.save_rflags;
6de12732
AK		 1424 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1425 }
e7bddc52 1426 vmx->rflags = rflags;
78ac8b47 1427 }
e7bddc52 1428 return vmx->rflags;
6aa8b732
AK		 1429}
1430
97b7ead3 1431void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1432{
e7bddc52 1433 struct vcpu_vmx *vmx = to_vmx(vcpu);
491c1ad1 1434 unsigned long old_rflags;
f244deed 1435
491c1ad1 1436 if (enable_unrestricted_guest) {
cb3c1e2f 1437 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
491c1ad1
SC		 1438 vmx->rflags = rflags;
1439 vmcs_writel(GUEST_RFLAGS, rflags);
1440 return;
1441 }
1442
1443 old_rflags = vmx_get_rflags(vcpu);
e7bddc52
SC		 1444 vmx->rflags = rflags;
1445 if (vmx->rmode.vm86_active) {
1446 vmx->rmode.save_rflags = rflags;
053de044 1447 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1448 }
6aa8b732 1449 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed 1450
e7bddc52
SC		 1451 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1452 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1453}
1454
97b7ead3 1455u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1456{
1457 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1458 int ret = 0;
1459
1460 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1461 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1462 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1463 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1464
37ccdcbe 1465 return ret;
2809f5d2
GC		 1466}
1467
97b7ead3 1468void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1469{
1470 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1471 u32 interruptibility = interruptibility_old;
1472
1473 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1474
48005f64 1475 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1476 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1477 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1478 interruptibility |= GUEST_INTR_STATE_STI;
1479
1480 if ((interruptibility != interruptibility_old))
1481 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1482}
1483
bf8c55d8
CP		 1484static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1485{
1486 struct vcpu_vmx *vmx = to_vmx(vcpu);
1487 unsigned long value;
1488
1489 /*
1490 * Any MSR write that attempts to change bits marked reserved will
1491 * case a #GP fault.
1492 */
1493 if (data & vmx->pt_desc.ctl_bitmask)
1494 return 1;
1495
1496 /*
1497 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1498 * result in a #GP unless the same write also clears TraceEn.
1499 */
1500 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1501 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1502 return 1;
1503
1504 /*
1505 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1506 * and FabricEn would cause #GP, if
1507 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1508 */
1509 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1510 !(data & RTIT_CTL_FABRIC_EN) &&
1511 !intel_pt_validate_cap(vmx->pt_desc.caps,
1512 PT_CAP_single_range_output))
1513 return 1;
1514
1515 /*
1516 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1517 * utilize encodings marked reserved will casue a #GP fault.
1518 */
1519 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1520 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1521 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1522 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1523 return 1;
1524 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1525 PT_CAP_cycle_thresholds);
1526 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1527 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1528 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1529 return 1;
1530 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1531 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1532 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1533 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1534 return 1;
1535
1536 /*
1537 * If ADDRx_CFG is reserved or the encodings is >2 will
1538 * cause a #GP fault.
1539 */
1540 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1541 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1542 return 1;
1543 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1544 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1545 return 1;
1546 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1547 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1548 return 1;
1549 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1550 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1551 return 1;
1552
1553 return 0;
1554}
1555
1957aa63 1556static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1557{
1558 unsigned long rip;
6aa8b732 1559
1957aa63
SC		 1560 /*
1561 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1562 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1563 * set when EPT misconfig occurs. In practice, real hardware updates
1564 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1565 * (namely Hyper-V) don't set it due to it being undefined behavior,
1566 * i.e. we end up advancing IP with some random value.
1567 */
1568 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1569 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1570 rip = kvm_rip_read(vcpu);
1571 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1572 kvm_rip_write(vcpu, rip);
1573 } else {
1574 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1575 return 0;
1576 }
6aa8b732 1577
2809f5d2
GC		 1578 /* skipping an emulated instruction also counts */
1579 vmx_set_interrupt_shadow(vcpu, 0);
f8ea7c60 1580
60fc3d02 1581 return 1;
f8ea7c60
VK		 1582}
1583
caa057a2
WL		 1584static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1585{
1586 /*
1587 * Ensure that we clear the HLT state in the VMCS. We don't need to
1588 * explicitly skip the instruction because if the HLT state is set,
1589 * then the instruction is already executing and RIP has already been
1590 * advanced.
1591 */
1592 if (kvm_hlt_in_guest(vcpu->kvm) &&
1593 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1594 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1595}
1596
cfcd20e5 1597static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1598{
77ab6db0 1599 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1600 unsigned nr = vcpu->arch.exception.nr;
1601 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1602 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1603 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1604
da998b46
JM		 1605 kvm_deliver_exception_payload(vcpu);
1606
8ab2d2e2 1607 if (has_error_code) {
77ab6db0 1608 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1609 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1610 }
77ab6db0 1611
7ffd92c5 1612 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1613 int inc_eip = 0;
1614 if (kvm_exception_is_soft(nr))
1615 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 1616 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
77ab6db0
JK		 1617 return;
1618 }
1619
add5ff7a
SC		 1620 WARN_ON_ONCE(vmx->emulation_required);
1621
66fd3f7f
GN		 1622 if (kvm_exception_is_soft(nr)) {
1623 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1624 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1625 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1626 } else
1627 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1628
1629 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1630
1631 vmx_clear_hlt(vcpu);
298101da
AK		 1632}
1633
4e47c7a6
SY		 1634static bool vmx_rdtscp_supported(void)
1635{
1636 return cpu_has_vmx_rdtscp();
1637}
1638
ad756a16
MJ		 1639static bool vmx_invpcid_supported(void)
1640{
eb4b248e 1641 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1642}
1643
a75beee6
ED		 1644/*
1645 * Swap MSR entry in host/guest MSR entry array.
1646 */
8b9cf98c 1647static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1648{
26bb0981 1649 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1650
1651 tmp = vmx->guest_msrs[to];
1652 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1653 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1654}
1655
e38aea3e
AK		 1656/*
1657 * Set up the vmcs to automatically save and restore system
1658 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1659 * mode, as fiddling with msrs is very expensive.
1660 */
8b9cf98c 1661static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1662{
26bb0981 1663 int save_nmsrs, index;
e38aea3e 1664
a75beee6
ED		 1665 save_nmsrs = 0;
1666#ifdef CONFIG_X86_64
84c8c5b8
JM		 1667 /*
1668 * The SYSCALL MSRs are only needed on long mode guests, and only
1669 * when EFER.SCE is set.
1670 */
1671 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1672 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1673 if (index >= 0)
8b9cf98c
RR		 1674 move_msr_up(vmx, index, save_nmsrs++);
1675 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1676 if (index >= 0)
8b9cf98c 1677 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1678 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1679 if (index >= 0)
8b9cf98c 1680 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1681 }
1682#endif
92c0d900
AK		 1683 index = __find_msr_index(vmx, MSR_EFER);
1684 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1685 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1686 index = __find_msr_index(vmx, MSR_TSC_AUX);
1687 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1688 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1689
26bb0981 1690 vmx->save_nmsrs = save_nmsrs;
b464f57e 1691 vmx->guest_msrs_ready = false;
5897297b 1692
8d14695f 1693 if (cpu_has_vmx_msr_bitmap())
904e14fb 1694 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1695}
1696
e79f245d 1697static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1698{
e79f245d 1699 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1700
e79f245d
KA		 1701 if (is_guest_mode(vcpu) &&
1702 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1703 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1704
1705 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1706}
1707
326e7425 1708static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1709{
45c3af97
PB		 1710 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1711 u64 g_tsc_offset = 0;
1712
1713 /*
1714 * We're here if L1 chose not to trap WRMSR to TSC. According
1715 * to the spec, this should set L1's TSC; The offset that L1
1716 * set for L2 remains unchanged, and still needs to be added
1717 * to the newly set TSC to get L2's TSC.
1718 */
1719 if (is_guest_mode(vcpu) &&
1720 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1721 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1722
45c3af97
PB		 1723 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1724 vcpu->arch.tsc_offset - g_tsc_offset,
1725 offset);
1726 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1727 return offset + g_tsc_offset;
6aa8b732
AK		 1728}
1729
801d3424
NHE		 1730/*
1731 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1732 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1733 * all guests if the "nested" module option is off, and can also be disabled
1734 * for a single guest by disabling its VMX cpuid bit.
1735 */
7c97fcb3 1736bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1737{
d6321d49 1738 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1739}
1740
55d2375e
SC		 1741static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1742 uint64_t val)
62cc6b9d 1743{
55d2375e 1744 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1745
55d2375e 1746 return !(val & ~valid_bits);
62cc6b9d
DM		 1747}
1748
55d2375e 1749static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1750{
55d2375e
SC		 1751 switch (msr->index) {
1752 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1753 if (!nested)
1754 return 1;
1755 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1756 default:
1757 return 1;
1758 }
62cc6b9d 1759
62cc6b9d
DM		 1760 return 0;
1761}
1762
55d2375e
SC		 1763/*
1764 * Reads an msr value (of 'msr_index') into 'pdata'.
1765 * Returns 0 on success, non-0 otherwise.
1766 * Assumes vcpu_load() was already called.
1767 */
1768static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1769{
55d2375e
SC		 1770 struct vcpu_vmx *vmx = to_vmx(vcpu);
1771 struct shared_msr_entry *msr;
bf8c55d8 1772 u32 index;
62cc6b9d 1773
55d2375e
SC		 1774 switch (msr_info->index) {
1775#ifdef CONFIG_X86_64
1776 case MSR_FS_BASE:
1777 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1778 break;
55d2375e
SC		 1779 case MSR_GS_BASE:
1780 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1781 break;
55d2375e
SC		 1782 case MSR_KERNEL_GS_BASE:
1783 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1784 break;
55d2375e
SC		 1785#endif
1786 case MSR_EFER:
1787 return kvm_get_msr_common(vcpu, msr_info);
6e3ba4ab
TX		 1788 case MSR_IA32_UMWAIT_CONTROL:
1789 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1790 return 1;
1791
1792 msr_info->data = vmx->msr_ia32_umwait_control;
1793 break;
55d2375e
SC		 1794 case MSR_IA32_SPEC_CTRL:
1795 if (!msr_info->host_initiated &&
1796 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1797 return 1;
1798
1799 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1800 break;
6aa8b732 1801 case MSR_IA32_SYSENTER_CS:
609e36d3 1802 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1803 break;
1804 case MSR_IA32_SYSENTER_EIP:
609e36d3 1805 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1806 break;
1807 case MSR_IA32_SYSENTER_ESP:
609e36d3 1808 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1809 break;
0dd376e7 1810 case MSR_IA32_BNDCFGS:
691bd434 1811 if (!kvm_mpx_supported() ||
d6321d49
RK		 1812 (!msr_info->host_initiated &&
1813 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1814 return 1;
609e36d3 1815 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1816 break;
c45dcc71
AR		 1817 case MSR_IA32_MCG_EXT_CTL:
1818 if (!msr_info->host_initiated &&
a6cb099a 1819 !(vmx->msr_ia32_feature_control &
c45dcc71 1820 FEATURE_CONTROL_LMCE))
cae50139 1821 return 1;
c45dcc71
AR		 1822 msr_info->data = vcpu->arch.mcg_ext_ctl;
1823 break;
cae50139 1824 case MSR_IA32_FEATURE_CONTROL:
a6cb099a 1825 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1826 break;
1827 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1828 if (!nested_vmx_allowed(vcpu))
1829 return 1;
6677f3da
PB		 1830 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1831 &msr_info->data);
20300099 1832 case MSR_IA32_XSS:
4d763b16
WL		 1833 if (!vmx_xsaves_supported() ||
1834 (!msr_info->host_initiated &&
1835 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1836 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
20300099 1837 return 1;
609e36d3 1838 msr_info->data = vcpu->arch.ia32_xss;
20300099 1839 break;
bf8c55d8
CP		 1840 case MSR_IA32_RTIT_CTL:
1841 if (pt_mode != PT_MODE_HOST_GUEST)
1842 return 1;
1843 msr_info->data = vmx->pt_desc.guest.ctl;
1844 break;
1845 case MSR_IA32_RTIT_STATUS:
1846 if (pt_mode != PT_MODE_HOST_GUEST)
1847 return 1;
1848 msr_info->data = vmx->pt_desc.guest.status;
1849 break;
1850 case MSR_IA32_RTIT_CR3_MATCH:
1851 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1852 !intel_pt_validate_cap(vmx->pt_desc.caps,
1853 PT_CAP_cr3_filtering))
1854 return 1;
1855 msr_info->data = vmx->pt_desc.guest.cr3_match;
1856 break;
1857 case MSR_IA32_RTIT_OUTPUT_BASE:
1858 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1859 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1860 PT_CAP_topa_output) &&
1861 !intel_pt_validate_cap(vmx->pt_desc.caps,
1862 PT_CAP_single_range_output)))
1863 return 1;
1864 msr_info->data = vmx->pt_desc.guest.output_base;
1865 break;
1866 case MSR_IA32_RTIT_OUTPUT_MASK:
1867 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1868 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1869 PT_CAP_topa_output) &&
1870 !intel_pt_validate_cap(vmx->pt_desc.caps,
1871 PT_CAP_single_range_output)))
1872 return 1;
1873 msr_info->data = vmx->pt_desc.guest.output_mask;
1874 break;
1875 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1876 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1877 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1878 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1879 PT_CAP_num_address_ranges)))
1880 return 1;
1881 if (index % 2)
1882 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1883 else
1884 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1885 break;
4e47c7a6 1886 case MSR_TSC_AUX:
d6321d49
RK		 1887 if (!msr_info->host_initiated &&
1888 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1889 return 1;
b2869f28 1890 /* Else, falls through */
6aa8b732 1891 default:
a6cb099a 1892 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1893 if (msr) {
609e36d3 1894 msr_info->data = msr->data;
3bab1f5d 1895 break;
6aa8b732 1896 }
609e36d3 1897 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1898 }
1899
6aa8b732
AK		 1900 return 0;
1901}
1902
1903/*
1904 * Writes msr value into into the appropriate "register".
1905 * Returns 0 on success, non-0 otherwise.
1906 * Assumes vcpu_load() was already called.
1907 */
8fe8ab46 1908static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1909{
a2fa3e9f 1910 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1911 struct shared_msr_entry *msr;
2cc51560 1912 int ret = 0;
8fe8ab46
WA		 1913 u32 msr_index = msr_info->index;
1914 u64 data = msr_info->data;
bf8c55d8 1915 u32 index;
2cc51560 1916
6aa8b732 1917 switch (msr_index) {
3bab1f5d 1918 case MSR_EFER:
8fe8ab46 1919 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1920 break;
16175a79 1921#ifdef CONFIG_X86_64
6aa8b732 1922 case MSR_FS_BASE:
2fb92db1 1923 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1924 vmcs_writel(GUEST_FS_BASE, data);
1925 break;
1926 case MSR_GS_BASE:
2fb92db1 1927 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1928 vmcs_writel(GUEST_GS_BASE, data);
1929 break;
44ea2b17 1930 case MSR_KERNEL_GS_BASE:
678e315e 1931 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1932 break;
6aa8b732
AK		 1933#endif
1934 case MSR_IA32_SYSENTER_CS:
de70d279
SC		 1935 if (is_guest_mode(vcpu))
1936 get_vmcs12(vcpu)->guest_sysenter_cs = data;
6aa8b732
AK		 1937 vmcs_write32(GUEST_SYSENTER_CS, data);
1938 break;
1939 case MSR_IA32_SYSENTER_EIP:
de70d279
SC		 1940 if (is_guest_mode(vcpu))
1941 get_vmcs12(vcpu)->guest_sysenter_eip = data;
f5b42c33 1942 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1943 break;
1944 case MSR_IA32_SYSENTER_ESP:
de70d279
SC		 1945 if (is_guest_mode(vcpu))
1946 get_vmcs12(vcpu)->guest_sysenter_esp = data;
f5b42c33 1947 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1948 break;
699a1ac2
SC		 1949 case MSR_IA32_DEBUGCTLMSR:
1950 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1951 VM_EXIT_SAVE_DEBUG_CONTROLS)
1952 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1953
1954 ret = kvm_set_msr_common(vcpu, msr_info);
1955 break;
1956
0dd376e7 1957 case MSR_IA32_BNDCFGS:
691bd434 1958 if (!kvm_mpx_supported() ||
d6321d49
RK		 1959 (!msr_info->host_initiated &&
1960 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1961 return 1;
fd8cb433 1962 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 1963 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 1964 return 1;
0dd376e7
LJ		 1965 vmcs_write64(GUEST_BNDCFGS, data);
1966 break;
6e3ba4ab
TX		 1967 case MSR_IA32_UMWAIT_CONTROL:
1968 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1969 return 1;
1970
1971 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1972 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1973 return 1;
1974
1975 vmx->msr_ia32_umwait_control = data;
1976 break;
d28b387f
KA		 1977 case MSR_IA32_SPEC_CTRL:
1978 if (!msr_info->host_initiated &&
d28b387f
KA		 1979 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1980 return 1;
1981
1982 /* The STIBP bit doesn't fault even if it's not advertised */
9f65fb29 1983 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
d28b387f
KA		 1984 return 1;
1985
1986 vmx->spec_ctrl = data;
1987
1988 if (!data)
1989 break;
1990
1991 /*
1992 * For non-nested:
1993 * When it's written (to non-zero) for the first time, pass
1994 * it through.
1995 *
1996 * For nested:
1997 * The handling of the MSR bitmap for L2 guests is done in
1998 * nested_vmx_merge_msr_bitmap. We should not touch the
1999 * vmcs02.msr_bitmap here since it gets completely overwritten
2000 * in the merging. We update the vmcs01 here for L1 as well
2001 * since it will end up touching the MSR anyway now.
2002 */
2003 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2004 MSR_IA32_SPEC_CTRL,
2005 MSR_TYPE_RW);
2006 break;
15d45071
AR		 2007 case MSR_IA32_PRED_CMD:
2008 if (!msr_info->host_initiated &&
15d45071
AR		 2009 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2010 return 1;
2011
2012 if (data & ~PRED_CMD_IBPB)
2013 return 1;
2014
2015 if (!data)
2016 break;
2017
2018 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2019
2020 /*
2021 * For non-nested:
2022 * When it's written (to non-zero) for the first time, pass
2023 * it through.
2024 *
2025 * For nested:
2026 * The handling of the MSR bitmap for L2 guests is done in
2027 * nested_vmx_merge_msr_bitmap. We should not touch the
2028 * vmcs02.msr_bitmap here since it gets completely overwritten
2029 * in the merging.
2030 */
2031 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2032 MSR_TYPE_W);
2033 break;
468d472f 2034 case MSR_IA32_CR_PAT:
d28f4290
SC		 2035 if (!kvm_pat_valid(data))
2036 return 1;
2037
142e4be7
SC		 2038 if (is_guest_mode(vcpu) &&
2039 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2040 get_vmcs12(vcpu)->guest_ia32_pat = data;
2041
468d472f
SY		 2042 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2043 vmcs_write64(GUEST_IA32_PAT, data);
2044 vcpu->arch.pat = data;
2045 break;
2046 }
8fe8ab46 2047 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2048 break;
ba904635
WA		 2049 case MSR_IA32_TSC_ADJUST:
2050 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2051 break;
c45dcc71
AR		 2052 case MSR_IA32_MCG_EXT_CTL:
2053 if ((!msr_info->host_initiated &&
2054 !(to_vmx(vcpu)->msr_ia32_feature_control &
2055 FEATURE_CONTROL_LMCE)) ||
2056 (data & ~MCG_EXT_CTL_LMCE_EN))
2057 return 1;
2058 vcpu->arch.mcg_ext_ctl = data;
2059 break;
cae50139 2060 case MSR_IA32_FEATURE_CONTROL:
37e4c997 2061 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 2062 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK		 2063 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2064 return 1;
3b84080b 2065 vmx->msr_ia32_feature_control = data;
cae50139
JK		 2066 if (msr_info->host_initiated && data == 0)
2067 vmx_leave_nested(vcpu);
2068 break;
2069 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 2070 if (!msr_info->host_initiated)
2071 return 1; /* they are read-only */
2072 if (!nested_vmx_allowed(vcpu))
2073 return 1;
2074 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099 2075 case MSR_IA32_XSS:
4d763b16
WL		 2076 if (!vmx_xsaves_supported() ||
2077 (!msr_info->host_initiated &&
2078 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
2079 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
20300099
WL		 2080 return 1;
2081 /*
2082 * The only supported bit as of Skylake is bit 8, but
2083 * it is not supported on KVM.
2084 */
2085 if (data != 0)
2086 return 1;
2087 vcpu->arch.ia32_xss = data;
2088 if (vcpu->arch.ia32_xss != host_xss)
2089 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
989e3992 2090 vcpu->arch.ia32_xss, host_xss, false);
20300099
WL		 2091 else
2092 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2093 break;
bf8c55d8
CP		 2094 case MSR_IA32_RTIT_CTL:
2095 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 2096 vmx_rtit_ctl_check(vcpu, data) ||
2097 vmx->nested.vmxon)
bf8c55d8
CP		 2098 return 1;
2099 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2100 vmx->pt_desc.guest.ctl = data;
b08c2896 2101 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 2102 break;
2103 case MSR_IA32_RTIT_STATUS:
2104 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2105 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2106 (data & MSR_IA32_RTIT_STATUS_MASK))
2107 return 1;
2108 vmx->pt_desc.guest.status = data;
2109 break;
2110 case MSR_IA32_RTIT_CR3_MATCH:
2111 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2112 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2113 !intel_pt_validate_cap(vmx->pt_desc.caps,
2114 PT_CAP_cr3_filtering))
2115 return 1;
2116 vmx->pt_desc.guest.cr3_match = data;
2117 break;
2118 case MSR_IA32_RTIT_OUTPUT_BASE:
2119 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2120 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2121 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2122 PT_CAP_topa_output) &&
2123 !intel_pt_validate_cap(vmx->pt_desc.caps,
2124 PT_CAP_single_range_output)) ||
2125 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2126 return 1;
2127 vmx->pt_desc.guest.output_base = data;
2128 break;
2129 case MSR_IA32_RTIT_OUTPUT_MASK:
2130 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2131 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2132 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2133 PT_CAP_topa_output) &&
2134 !intel_pt_validate_cap(vmx->pt_desc.caps,
2135 PT_CAP_single_range_output)))
2136 return 1;
2137 vmx->pt_desc.guest.output_mask = data;
2138 break;
2139 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2140 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2141 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2142 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2143 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2144 PT_CAP_num_address_ranges)))
2145 return 1;
2146 if (index % 2)
2147 vmx->pt_desc.guest.addr_b[index / 2] = data;
2148 else
2149 vmx->pt_desc.guest.addr_a[index / 2] = data;
2150 break;
4e47c7a6 2151 case MSR_TSC_AUX:
d6321d49
RK		 2152 if (!msr_info->host_initiated &&
2153 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2154 return 1;
2155 /* Check reserved bit, higher 32 bits should be zero */
2156 if ((data >> 32) != 0)
2157 return 1;
b2869f28 2158 /* Else, falls through */
6aa8b732 2159 default:
8b9cf98c 2160 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2161 if (msr) {
8b3c3104 2162 u64 old_msr_data = msr->data;
3bab1f5d 2163 msr->data = data;
2225fd56
AK		 2164 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2165 preempt_disable();
8b3c3104
AH		 2166 ret = kvm_set_shared_msr(msr->index, msr->data,
2167 msr->mask);
2225fd56 2168 preempt_enable();
8b3c3104
AH		 2169 if (ret)
2170 msr->data = old_msr_data;
2225fd56 2171 }
3bab1f5d 2172 break;
6aa8b732 2173 }
8fe8ab46 2174 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2175 }
2176
2cc51560 2177 return ret;
6aa8b732
AK		 2178}
2179
5fdbf976 2180static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2181{
cb3c1e2f
SC		 2182 kvm_register_mark_available(vcpu, reg);
2183
5fdbf976
MT		 2184 switch (reg) {
2185 case VCPU_REGS_RSP:
2186 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2187 break;
2188 case VCPU_REGS_RIP:
2189 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2190 break;
6de4f3ad
AK		 2191 case VCPU_EXREG_PDPTR:
2192 if (enable_ept)
2193 ept_save_pdptrs(vcpu);
2194 break;
34059c25
SC		 2195 case VCPU_EXREG_CR3:
2196 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2197 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2198 break;
5fdbf976 2199 default:
34059c25 2200 WARN_ON_ONCE(1);
5fdbf976
MT		 2201 break;
2202 }
6aa8b732
AK		 2203}
2204
6aa8b732
AK		 2205static __init int cpu_has_kvm_support(void)
2206{
6210e37b 2207 return cpu_has_vmx();
6aa8b732
AK		 2208}
2209
2210static __init int vmx_disabled_by_bios(void)
2211{
2212 u64 msr;
2213
2214 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2215 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2216 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2217 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2218 && tboot_enabled())
2219 return 1;
23f3e991 2220 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2221 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2222 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2223 && !tboot_enabled()) {
2224 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2225 "activate TXT before enabling KVM\n");
cafd6659 2226 return 1;
f9335afe 2227 }
23f3e991
JC		 2228 /* launched w/o TXT and VMX disabled */
2229 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2230 && !tboot_enabled())
2231 return 1;
cafd6659
SW		 2232 }
2233
2234 return 0;
6aa8b732
AK		 2235}
2236
7725b894
DX		 2237static void kvm_cpu_vmxon(u64 addr)
2238{
fe0e80be 2239 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2240 intel_pt_handle_vmx(1);
2241
4b1e5478 2242 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2243}
2244
13a34e06 2245static int hardware_enable(void)
6aa8b732
AK		 2246{
2247 int cpu = raw_smp_processor_id();
2248 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2249 u64 old, test_bits;
6aa8b732 2250
1e02ce4c 2251 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2252 return -EBUSY;
2253
773e8a04
VK		 2254 /*
2255 * This can happen if we hot-added a CPU but failed to allocate
2256 * VP assist page for it.
2257 */
2258 if (static_branch_unlikely(&enable_evmcs) &&
2259 !hv_get_vp_assist_page(cpu))
2260 return -EFAULT;
2261
d462b819 2262 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2263 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2264 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2265
2266 /*
2267 * Now we can enable the vmclear operation in kdump
2268 * since the loaded_vmcss_on_cpu list on this cpu
2269 * has been initialized.
2270 *
2271 * Though the cpu is not in VMX operation now, there
2272 * is no problem to enable the vmclear operation
2273 * for the loaded_vmcss_on_cpu list is empty!
2274 */
2275 crash_enable_local_vmclear(cpu);
2276
6aa8b732 2277 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2278
2279 test_bits = FEATURE_CONTROL_LOCKED;
2280 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2281 if (tboot_enabled())
2282 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2283
2284 if ((old & test_bits) != test_bits) {
6aa8b732 2285 /* enable and lock */
cafd6659
SW		 2286 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2287 }
fe0e80be 2288 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2289 if (enable_ept)
2290 ept_sync_global();
10474ae8
AG		 2291
2292 return 0;
6aa8b732
AK		 2293}
2294
d462b819 2295static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2296{
2297 int cpu = raw_smp_processor_id();
d462b819 2298 struct loaded_vmcs *v, *n;
543e4243 2299
d462b819
NHE		 2300 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2301 loaded_vmcss_on_cpu_link)
2302 __loaded_vmcs_clear(v);
543e4243
AK		 2303}
2304
710ff4a8
EH		 2305
2306/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2307 * tricks.
2308 */
2309static void kvm_cpu_vmxoff(void)
6aa8b732 2310{
4b1e5478 2311 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2312
2313 intel_pt_handle_vmx(0);
fe0e80be 2314 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2315}
2316
13a34e06 2317static void hardware_disable(void)
710ff4a8 2318{
fe0e80be
DH		 2319 vmclear_local_loaded_vmcss();
2320 kvm_cpu_vmxoff();
710ff4a8
EH		 2321}
2322
1c3d14fe 2323static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2324 u32 msr, u32 *result)
1c3d14fe
YS		 2325{
2326 u32 vmx_msr_low, vmx_msr_high;
2327 u32 ctl = ctl_min | ctl_opt;
2328
2329 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2330
2331 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2332 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2333
2334 /* Ensure minimum (required) set of control bits are supported. */
2335 if (ctl_min & ~ctl)
002c7f7c 2336 return -EIO;
1c3d14fe
YS		 2337
2338 *result = ctl;
2339 return 0;
2340}
2341
7caaa711
SC		 2342static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2343 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2344{
2345 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2346 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2347 u32 _pin_based_exec_control = 0;
2348 u32 _cpu_based_exec_control = 0;
f78e0e2e 2349 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2350 u32 _vmexit_control = 0;
2351 u32 _vmentry_control = 0;
2352
1389309c 2353 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2354 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2355#ifdef CONFIG_X86_64
2356 CPU_BASED_CR8_LOAD_EXITING |
2357 CPU_BASED_CR8_STORE_EXITING |
2358#endif
d56f546d
SY		 2359 CPU_BASED_CR3_LOAD_EXITING |
2360 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2361 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2362 CPU_BASED_MOV_DR_EXITING |
a7052897 2363 CPU_BASED_USE_TSC_OFFSETING |
4d5422ce
WL		 2364 CPU_BASED_MWAIT_EXITING |
2365 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2366 CPU_BASED_INVLPG_EXITING |
2367 CPU_BASED_RDPMC_EXITING;
443381a8 2368
f78e0e2e 2369 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2370 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2371 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2372 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2373 &_cpu_based_exec_control) < 0)
002c7f7c 2374 return -EIO;
6e5d865c
YS		 2375#ifdef CONFIG_X86_64
2376 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2377 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2378 ~CPU_BASED_CR8_STORE_EXITING;
2379#endif
f78e0e2e 2380 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2381 min2 = 0;
2382 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2383 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2384 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2385 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2386 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2387 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2388 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2389 SECONDARY_EXEC_DESC |
ad756a16 2390 SECONDARY_EXEC_RDTSCP |
83d4c286 2391 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2392 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2393 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2394 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2395 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2396 SECONDARY_EXEC_RDSEED_EXITING |
2397 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2398 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2399 SECONDARY_EXEC_TSC_SCALING |
e69e72fa 2400 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
f99e3daf
CP		 2401 SECONDARY_EXEC_PT_USE_GPA |
2402 SECONDARY_EXEC_PT_CONCEAL_VMX |
0b665d30
SC		 2403 SECONDARY_EXEC_ENABLE_VMFUNC |
2404 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2405 if (adjust_vmx_controls(min2, opt2,
2406 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2407 &_cpu_based_2nd_exec_control) < 0)
2408 return -EIO;
2409 }
2410#ifndef CONFIG_X86_64
2411 if (!(_cpu_based_2nd_exec_control &
2412 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2413 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2414#endif
83d4c286
YZ		 2415
2416 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2417 _cpu_based_2nd_exec_control &= ~(
8d14695f 2418 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2419 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2420 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2421
61f1dd90 2422 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2423 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2424
d56f546d 2425 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2426 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2427 enabled */
5fff7d27
GN		 2428 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2429 CPU_BASED_CR3_STORE_EXITING |
2430 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2431 } else if (vmx_cap->ept) {
2432 vmx_cap->ept = 0;
61f1dd90
WL		 2433 pr_warn_once("EPT CAP should not exist if not support "
2434 "1-setting enable EPT VM-execution control\n");
2435 }
2436 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2437 vmx_cap->vpid) {
2438 vmx_cap->vpid = 0;
61f1dd90
WL		 2439 pr_warn_once("VPID CAP should not exist if not support "
2440 "1-setting enable VPID VM-execution control\n");
d56f546d 2441 }
1c3d14fe 2442
91fa0f8e 2443 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2444#ifdef CONFIG_X86_64
2445 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2446#endif
c73da3fc 2447 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2448 VM_EXIT_LOAD_IA32_PAT |
2449 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2450 VM_EXIT_CLEAR_BNDCFGS |
2451 VM_EXIT_PT_CONCEAL_PIP |
2452 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2453 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2454 &_vmexit_control) < 0)
002c7f7c 2455 return -EIO;
1c3d14fe 2456
8a1b4392
PB		 2457 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2458 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2459 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2460 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2461 &_pin_based_exec_control) < 0)
2462 return -EIO;
2463
1c17c3e6
PB		 2464 if (cpu_has_broken_vmx_preemption_timer())
2465 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2466 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2467 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2468 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2469
c845f9c6 2470 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2471 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2472 VM_ENTRY_LOAD_IA32_PAT |
2473 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2474 VM_ENTRY_LOAD_BNDCFGS |
2475 VM_ENTRY_PT_CONCEAL_PIP |
2476 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2477 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2478 &_vmentry_control) < 0)
002c7f7c 2479 return -EIO;
6aa8b732 2480
c73da3fc
SC		 2481 /*
2482 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2483 * can't be used due to an errata where VM Exit may incorrectly clear
2484 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2485 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2486 */
2487 if (boot_cpu_data.x86 == 0x6) {
2488 switch (boot_cpu_data.x86_model) {
2489 case 26: /* AAK155 */
2490 case 30: /* AAP115 */
2491 case 37: /* AAT100 */
2492 case 44: /* BC86,AAY89,BD102 */
2493 case 46: /* BA97 */
85ba2b16 2494 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2495 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2496 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2497 "does not work properly. Using workaround\n");
2498 break;
2499 default:
2500 break;
2501 }
2502 }
2503
2504
c68876fd 2505 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2506
2507 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2508 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2509 return -EIO;
1c3d14fe
YS		 2510
2511#ifdef CONFIG_X86_64
2512 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2513 if (vmx_msr_high & (1u<<16))
002c7f7c 2514 return -EIO;
1c3d14fe
YS		 2515#endif
2516
2517 /* Require Write-Back (WB) memory type for VMCS accesses. */
2518 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2519 return -EIO;
1c3d14fe 2520
002c7f7c 2521 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2522 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2523 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2524
2307af1c 2525 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2526
002c7f7c
YS		 2527 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2528 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2529 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2530 vmcs_conf->vmexit_ctrl = _vmexit_control;
2531 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2532
773e8a04
VK		 2533 if (static_branch_unlikely(&enable_evmcs))
2534 evmcs_sanitize_exec_ctrls(vmcs_conf);
2535
1c3d14fe 2536 return 0;
c68876fd 2537}
6aa8b732 2538
41836839 2539struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2540{
2541 int node = cpu_to_node(cpu);
2542 struct page *pages;
2543 struct vmcs *vmcs;
2544
41836839 2545 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2546 if (!pages)
2547 return NULL;
2548 vmcs = page_address(pages);
1c3d14fe 2549 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2550
2551 /* KVM supports Enlightened VMCS v1 only */
2552 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2553 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2554 else
392b2f25 2555 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2556
491a6038
LA		 2557 if (shadow)
2558 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2559 return vmcs;
2560}
2561
89b0c9f5 2562void free_vmcs(struct vmcs *vmcs)
6aa8b732 2563{
1c3d14fe 2564 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2565}
2566
d462b819
NHE		 2567/*
2568 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2569 */
89b0c9f5 2570void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2571{
2572 if (!loaded_vmcs->vmcs)
2573 return;
2574 loaded_vmcs_clear(loaded_vmcs);
2575 free_vmcs(loaded_vmcs->vmcs);
2576 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2577 if (loaded_vmcs->msr_bitmap)
2578 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2579 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2580}
2581
89b0c9f5 2582int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2583{
491a6038 2584 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2585 if (!loaded_vmcs->vmcs)
2586 return -ENOMEM;
2587
2588 loaded_vmcs->shadow_vmcs = NULL;
804939ea 2589 loaded_vmcs->hv_timer_soft_disabled = false;
f21f165e 2590 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2591
2592 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2593 loaded_vmcs->msr_bitmap = (unsigned long *)
2594 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2595 if (!loaded_vmcs->msr_bitmap)
2596 goto out_vmcs;
2597 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2598
1f008e11
AB		 2599 if (IS_ENABLED(CONFIG_HYPERV) &&
2600 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2601 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2602 struct hv_enlightened_vmcs *evmcs =
2603 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2604
2605 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2606 }
904e14fb 2607 }
d7ee039e
SC		 2608
2609 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
3af80fec
SC		 2610 memset(&loaded_vmcs->controls_shadow, 0,
2611 sizeof(struct vmcs_controls_shadow));
d7ee039e 2612
f21f165e 2613 return 0;
904e14fb
PB		 2614
2615out_vmcs:
2616 free_loaded_vmcs(loaded_vmcs);
2617 return -ENOMEM;
f21f165e
PB		 2618}
2619
39959588 2620static void free_kvm_area(void)
6aa8b732
AK		 2621{
2622 int cpu;
2623
3230bb47 2624 for_each_possible_cpu(cpu) {
6aa8b732 2625 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2626 per_cpu(vmxarea, cpu) = NULL;
2627 }
6aa8b732
AK		 2628}
2629
6aa8b732
AK		 2630static __init int alloc_kvm_area(void)
2631{
2632 int cpu;
2633
3230bb47 2634 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2635 struct vmcs *vmcs;
2636
41836839 2637 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2638 if (!vmcs) {
2639 free_kvm_area();
2640 return -ENOMEM;
2641 }
2642
2307af1c
LA		 2643 /*
2644 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2645 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2646 * revision_id reported by MSR_IA32_VMX_BASIC.
2647 *
312a4661 2648 * However, even though not explicitly documented by
2307af1c
LA		 2649 * TLFS, VMXArea passed as VMXON argument should
2650 * still be marked with revision_id reported by
2651 * physical CPU.
2652 */
2653 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2654 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2655
6aa8b732
AK		 2656 per_cpu(vmxarea, cpu) = vmcs;
2657 }
2658 return 0;
2659}
2660
91b0aa2c 2661static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2662 struct kvm_segment *save)
6aa8b732 2663{
d99e4152
GN		 2664 if (!emulate_invalid_guest_state) {
2665 /*
2666 * CS and SS RPL should be equal during guest entry according
2667 * to VMX spec, but in reality it is not always so. Since vcpu
2668 * is in the middle of the transition from real mode to
2669 * protected mode it is safe to assume that RPL 0 is a good
2670 * default value.
2671 */
2672 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2673 save->selector &= ~SEGMENT_RPL_MASK;
2674 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2675 save->s = 1;
6aa8b732 2676 }
d99e4152 2677 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2678}
2679
2680static void enter_pmode(struct kvm_vcpu *vcpu)
2681{
2682 unsigned long flags;
a89a8fb9 2683 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2684
d99e4152
GN		 2685 /*
2686 * Update real mode segment cache. It may be not up-to-date if sement
2687 * register was written while vcpu was in a guest mode.
2688 */
2689 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2690 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2691 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2692 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2693 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2694 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2695
7ffd92c5 2696 vmx->rmode.vm86_active = 0;
6aa8b732 2697
2fb92db1
AK		 2698 vmx_segment_cache_clear(vmx);
2699
f5f7b2fe 2700 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2701
2702 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2703 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2704 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2705 vmcs_writel(GUEST_RFLAGS, flags);
2706
66aee91a
RR		 2707 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2708 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2709
2710 update_exception_bitmap(vcpu);
2711
91b0aa2c
GN		 2712 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2713 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2714 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2715 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2716 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2717 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2718}
2719
f5f7b2fe 2720static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2721{
772e0318 2722 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2723 struct kvm_segment var = *save;
2724
2725 var.dpl = 0x3;
2726 if (seg == VCPU_SREG_CS)
2727 var.type = 0x3;
2728
2729 if (!emulate_invalid_guest_state) {
2730 var.selector = var.base >> 4;
2731 var.base = var.base & 0xffff0;
2732 var.limit = 0xffff;
2733 var.g = 0;
2734 var.db = 0;
2735 var.present = 1;
2736 var.s = 1;
2737 var.l = 0;
2738 var.unusable = 0;
2739 var.type = 0x3;
2740 var.avl = 0;
2741 if (save->base & 0xf)
2742 printk_once(KERN_WARNING "kvm: segment base is not "
2743 "paragraph aligned when entering "
2744 "protected mode (seg=%d)", seg);
2745 }
6aa8b732 2746
d99e4152 2747 vmcs_write16(sf->selector, var.selector);
96794e4e 2748 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2749 vmcs_write32(sf->limit, var.limit);
2750 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2751}
2752
2753static void enter_rmode(struct kvm_vcpu *vcpu)
2754{
2755 unsigned long flags;
a89a8fb9 2756 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2757 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2758
f5f7b2fe
AK		 2759 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2760 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2761 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2762 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2763 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2764 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2765 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2766
7ffd92c5 2767 vmx->rmode.vm86_active = 1;
6aa8b732 2768
776e58ea
GN		 2769 /*
2770 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2771 * vcpu. Warn the user that an update is overdue.
776e58ea 2772 */
40bbb9d0 2773 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2774 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2775 "called before entering vcpu\n");
776e58ea 2776
2fb92db1
AK		 2777 vmx_segment_cache_clear(vmx);
2778
40bbb9d0 2779 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2780 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2781 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2782
2783 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2784 vmx->rmode.save_rflags = flags;
6aa8b732 2785
053de044 2786 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2787
2788 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2789 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2790 update_exception_bitmap(vcpu);
2791
d99e4152
GN		 2792 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2793 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2794 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2795 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2796 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2797 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2798
8668a3c4 2799 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2800}
2801
97b7ead3 2802void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2803{
2804 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2805 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2806
2807 if (!msr)
2808 return;
401d10de 2809
f6801dff 2810 vcpu->arch.efer = efer;
401d10de 2811 if (efer & EFER_LMA) {
2961e876 2812 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2813 msr->data = efer;
2814 } else {
2961e876 2815 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2816
2817 msr->data = efer & ~EFER_LME;
2818 }
2819 setup_msrs(vmx);
2820}
2821
05b3e0c2 2822#ifdef CONFIG_X86_64
6aa8b732
AK		 2823
2824static void enter_lmode(struct kvm_vcpu *vcpu)
2825{
2826 u32 guest_tr_ar;
2827
2fb92db1
AK		 2828 vmx_segment_cache_clear(to_vmx(vcpu));
2829
6aa8b732 2830 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2831 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2832 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2833 __func__);
6aa8b732 2834 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2835 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2836 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2837 }
da38f438 2838 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2839}
2840
2841static void exit_lmode(struct kvm_vcpu *vcpu)
2842{
2961e876 2843 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2844 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2845}
2846
2847#endif
2848
faff8758
JS		 2849static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2850{
2851 int vpid = to_vmx(vcpu)->vpid;
2852
2853 if (!vpid_sync_vcpu_addr(vpid, addr))
2854 vpid_sync_context(vpid);
2855
2856 /*
2857 * If VPIDs are not supported or enabled, then the above is a no-op.
2858 * But we don't really need a TLB flush in that case anyway, because
2859 * each VM entry/exit includes an implicit flush when VPID is 0.
2860 */
2861}
2862
e8467fda
AK		 2863static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2864{
2865 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2866
2867 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2868 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2869}
2870
25c4c276 2871static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2872{
fc78f519
AK		 2873 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2874
2875 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2876 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2877}
2878
1439442c
SY		 2879static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2880{
d0d538b9
GN		 2881 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2882
cb3c1e2f 2883 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
6de4f3ad
AK		 2884 return;
2885
bf03d4f9 2886 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2887 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2888 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2889 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2890 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2891 }
2892}
2893
97b7ead3 2894void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2895{
d0d538b9
GN		 2896 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2897
bf03d4f9 2898 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2899 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2900 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2901 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2902 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2903 }
6de4f3ad 2904
cb3c1e2f 2905 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
8f5d549f
AK		 2906}
2907
1439442c
SY		 2908static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2909 unsigned long cr0,
2910 struct kvm_vcpu *vcpu)
2911{
2183f564
SC		 2912 struct vcpu_vmx *vmx = to_vmx(vcpu);
2913
cb3c1e2f 2914 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
34059c25 2915 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
1439442c
SY		 2916 if (!(cr0 & X86_CR0_PG)) {
2917 /* From paging/starting to nonpaging */
2183f564
SC		 2918 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2919 CPU_BASED_CR3_STORE_EXITING);
1439442c 2920 vcpu->arch.cr0 = cr0;
fc78f519 2921 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2922 } else if (!is_paging(vcpu)) {
2923 /* From nonpaging to paging */
2183f564
SC		 2924 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2925 CPU_BASED_CR3_STORE_EXITING);
1439442c 2926 vcpu->arch.cr0 = cr0;
fc78f519 2927 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2928 }
95eb84a7
SY		 2929
2930 if (!(cr0 & X86_CR0_WP))
2931 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2932}
2933
97b7ead3 2934void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2935{
7ffd92c5 2936 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2937 unsigned long hw_cr0;
2938
3de6347b 2939 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2940 if (enable_unrestricted_guest)
5037878e 2941 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2942 else {
5037878e 2943 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2944
218e763f
GN		 2945 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2946 enter_pmode(vcpu);
6aa8b732 2947
218e763f
GN		 2948 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2949 enter_rmode(vcpu);
2950 }
6aa8b732 2951
05b3e0c2 2952#ifdef CONFIG_X86_64
f6801dff 2953 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2954 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2955 enter_lmode(vcpu);
707d92fa 2956 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2957 exit_lmode(vcpu);
2958 }
2959#endif
2960
b4d18517 2961 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2962 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2963
6aa8b732 2964 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2965 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2966 vcpu->arch.cr0 = cr0;
14168786
GN		 2967
2968 /* depends on vcpu->arch.cr0 to be set to a new value */
2969 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2970}
2971
855feb67
YZ		 2972static int get_ept_level(struct kvm_vcpu *vcpu)
2973{
2974 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2975 return 5;
2976 return 4;
2977}
2978
89b0c9f5 2979u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2980{
855feb67
YZ		 2981 u64 eptp = VMX_EPTP_MT_WB;
2982
2983 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 2984
995f00a6
PF		 2985 if (enable_ept_ad_bits &&
2986 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 2987 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 2988 eptp |= (root_hpa & PAGE_MASK);
2989
2990 return eptp;
2991}
2992
97b7ead3 2993void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 2994{
877ad952 2995 struct kvm *kvm = vcpu->kvm;
04f11ef4 2996 bool update_guest_cr3 = true;
1439442c
SY		 2997 unsigned long guest_cr3;
2998 u64 eptp;
2999
3000 guest_cr3 = cr3;
089d034e 3001 if (enable_ept) {
995f00a6 3002 eptp = construct_eptp(vcpu, cr3);
1439442c 3003 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 3004
3005 if (kvm_x86_ops->tlb_remote_flush) {
3006 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3007 to_vmx(vcpu)->ept_pointer = eptp;
3008 to_kvm_vmx(kvm)->ept_pointers_match
3009 = EPT_POINTERS_CHECK;
3010 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3011 }
3012
04f11ef4
SC		 3013 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3014 if (is_guest_mode(vcpu))
3015 update_guest_cr3 = false;
b17b7436 3016 else if (!enable_unrestricted_guest && !is_paging(vcpu))
877ad952 3017 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
b17b7436
SC		 3018 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3019 guest_cr3 = vcpu->arch.cr3;
3020 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3021 update_guest_cr3 = false;
7c93be44 3022 ept_load_pdptrs(vcpu);
1439442c
SY		 3023 }
3024
04f11ef4
SC		 3025 if (update_guest_cr3)
3026 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3027}
3028
97b7ead3 3029int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3030{
fe7f895d 3031 struct vcpu_vmx *vmx = to_vmx(vcpu);
085e68ee
BS		 3032 /*
3033 * Pass through host's Machine Check Enable value to hw_cr4, which
3034 * is in force while we are in guest mode. Do not let guests control
3035 * this bit, even if host CR4.MCE == 0.
3036 */
5dc1f044
SC		 3037 unsigned long hw_cr4;
3038
3039 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3040 if (enable_unrestricted_guest)
3041 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
fe7f895d 3042 else if (vmx->rmode.vm86_active)
5dc1f044
SC		 3043 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3044 else
3045 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 3046
64f7a115
SC		 3047 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3048 if (cr4 & X86_CR4_UMIP) {
fe7f895d 3049 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
64f7a115
SC		 3050 hw_cr4 &= ~X86_CR4_UMIP;
3051 } else if (!is_guest_mode(vcpu) ||
fe7f895d
SC		 3052 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3053 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3054 }
64f7a115 3055 }
0367f205 3056
5e1746d6
NHE		 3057 if (cr4 & X86_CR4_VMXE) {
3058 /*
3059 * To use VMXON (and later other VMX instructions), a guest
3060 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3061 * So basically the check on whether to allow nested VMX
5bea5123
PB		 3062 * is here. We operate under the default treatment of SMM,
3063 * so VMX cannot be enabled under SMM.
5e1746d6 3064 */
5bea5123 3065 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 3066 return 1;
1a0d74e6 3067 }
3899152c 3068
fe7f895d 3069 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 3070 return 1;
3071
ad312c7c 3072 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 3073
3074 if (!enable_unrestricted_guest) {
3075 if (enable_ept) {
3076 if (!is_paging(vcpu)) {
3077 hw_cr4 &= ~X86_CR4_PAE;
3078 hw_cr4 |= X86_CR4_PSE;
3079 } else if (!(cr4 & X86_CR4_PAE)) {
3080 hw_cr4 &= ~X86_CR4_PAE;
3081 }
bc23008b 3082 }
1439442c 3083
656ec4a4 3084 /*
ddba2628
HH		 3085 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3086 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3087 * to be manually disabled when guest switches to non-paging
3088 * mode.
3089 *
3090 * If !enable_unrestricted_guest, the CPU is always running
3091 * with CR0.PG=1 and CR4 needs to be modified.
3092 * If enable_unrestricted_guest, the CPU automatically
3093 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 3094 */
5dc1f044
SC		 3095 if (!is_paging(vcpu))
3096 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3097 }
656ec4a4 3098
1439442c
SY		 3099 vmcs_writel(CR4_READ_SHADOW, cr4);
3100 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3101 return 0;
6aa8b732
AK		 3102}
3103
97b7ead3 3104void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 3105{
a9179499 3106 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3107 u32 ar;
3108
c6ad1153 3109 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3110 *var = vmx->rmode.segs[seg];
a9179499 3111 if (seg == VCPU_SREG_TR
2fb92db1 3112 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3113 return;
1390a28b
AK		 3114 var->base = vmx_read_guest_seg_base(vmx, seg);
3115 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3116 return;
a9179499 3117 }
2fb92db1
AK		 3118 var->base = vmx_read_guest_seg_base(vmx, seg);
3119 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3120 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3121 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3122 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3123 var->type = ar & 15;
3124 var->s = (ar >> 4) & 1;
3125 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3126 /*
3127 * Some userspaces do not preserve unusable property. Since usable
3128 * segment has to be present according to VMX spec we can use present
3129 * property to amend userspace bug by making unusable segment always
3130 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3131 * segment as unusable.
3132 */
3133 var->present = !var->unusable;
6aa8b732
AK		 3134 var->avl = (ar >> 12) & 1;
3135 var->l = (ar >> 13) & 1;
3136 var->db = (ar >> 14) & 1;
3137 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3138}
3139
a9179499
AK		 3140static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3141{
a9179499
AK		 3142 struct kvm_segment s;
3143
3144 if (to_vmx(vcpu)->rmode.vm86_active) {
3145 vmx_get_segment(vcpu, &s, seg);
3146 return s.base;
3147 }
2fb92db1 3148 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3149}
3150
97b7ead3 3151int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3152{
b09408d0
MT		 3153 struct vcpu_vmx *vmx = to_vmx(vcpu);
3154
ae9fedc7 3155 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3156 return 0;
ae9fedc7
PB		 3157 else {
3158 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3159 return VMX_AR_DPL(ar);
69c73028 3160 }
69c73028
AK		 3161}
3162
653e3108 3163static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3164{
6aa8b732
AK		 3165 u32 ar;
3166
f0495f9b 3167 if (var->unusable || !var->present)
6aa8b732
AK		 3168 ar = 1 << 16;
3169 else {
3170 ar = var->type & 15;
3171 ar |= (var->s & 1) << 4;
3172 ar |= (var->dpl & 3) << 5;
3173 ar |= (var->present & 1) << 7;
3174 ar |= (var->avl & 1) << 12;
3175 ar |= (var->l & 1) << 13;
3176 ar |= (var->db & 1) << 14;
3177 ar |= (var->g & 1) << 15;
3178 }
653e3108
AK		 3179
3180 return ar;
3181}
3182
97b7ead3 3183void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3184{
7ffd92c5 3185 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3186 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3187
2fb92db1
AK		 3188 vmx_segment_cache_clear(vmx);
3189
1ecd50a9
GN		 3190 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3191 vmx->rmode.segs[seg] = *var;
3192 if (seg == VCPU_SREG_TR)
3193 vmcs_write16(sf->selector, var->selector);
3194 else if (var->s)
3195 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3196 goto out;
653e3108 3197 }
1ecd50a9 3198
653e3108
AK		 3199 vmcs_writel(sf->base, var->base);
3200 vmcs_write32(sf->limit, var->limit);
3201 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3202
3203 /*
3204 * Fix the "Accessed" bit in AR field of segment registers for older
3205 * qemu binaries.
3206 * IA32 arch specifies that at the time of processor reset the
3207 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3208 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3209 * state vmexit when "unrestricted guest" mode is turned on.
3210 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3211 * tree. Newer qemu binaries with that qemu fix would not need this
3212 * kvm hack.
3213 */
3214 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3215 var->type |= 0x1; /* Accessed */
3a624e29 3216
f924d66d 3217 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3218
3219out:
98eb2f8b 3220 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3221}
3222
6aa8b732
AK		 3223static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3224{
2fb92db1 3225 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3226
3227 *db = (ar >> 14) & 1;
3228 *l = (ar >> 13) & 1;
3229}
3230
89a27f4d 3231static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3232{
89a27f4d
GN		 3233 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3234 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3235}
3236
89a27f4d 3237static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3238{
89a27f4d
GN		 3239 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3240 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3241}
3242
89a27f4d 3243static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3244{
89a27f4d
GN		 3245 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3246 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3247}
3248
89a27f4d 3249static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3250{
89a27f4d
GN		 3251 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3252 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3253}
3254
648dfaa7
MG		 3255static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3256{
3257 struct kvm_segment var;
3258 u32 ar;
3259
3260 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3261 var.dpl = 0x3;
0647f4aa
GN		 3262 if (seg == VCPU_SREG_CS)
3263 var.type = 0x3;
648dfaa7
MG		 3264 ar = vmx_segment_access_rights(&var);
3265
3266 if (var.base != (var.selector << 4))
3267 return false;
89efbed0 3268 if (var.limit != 0xffff)
648dfaa7 3269 return false;
07f42f5f 3270 if (ar != 0xf3)
648dfaa7
MG		 3271 return false;
3272
3273 return true;
3274}
3275
3276static bool code_segment_valid(struct kvm_vcpu *vcpu)
3277{
3278 struct kvm_segment cs;
3279 unsigned int cs_rpl;
3280
3281 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3282 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3283
1872a3f4
AK		 3284 if (cs.unusable)
3285 return false;
4d283ec9 3286 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3287 return false;
3288 if (!cs.s)
3289 return false;
4d283ec9 3290 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3291 if (cs.dpl > cs_rpl)
3292 return false;
1872a3f4 3293 } else {
648dfaa7
MG		 3294 if (cs.dpl != cs_rpl)
3295 return false;
3296 }
3297 if (!cs.present)
3298 return false;
3299
3300 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3301 return true;
3302}
3303
3304static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3305{
3306 struct kvm_segment ss;
3307 unsigned int ss_rpl;
3308
3309 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3310 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3311
1872a3f4
AK		 3312 if (ss.unusable)
3313 return true;
3314 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3315 return false;
3316 if (!ss.s)
3317 return false;
3318 if (ss.dpl != ss_rpl) /* DPL != RPL */
3319 return false;
3320 if (!ss.present)
3321 return false;
3322
3323 return true;
3324}
3325
3326static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3327{
3328 struct kvm_segment var;
3329 unsigned int rpl;
3330
3331 vmx_get_segment(vcpu, &var, seg);
b32a9918 3332 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3333
1872a3f4
AK		 3334 if (var.unusable)
3335 return true;
648dfaa7
MG		 3336 if (!var.s)
3337 return false;
3338 if (!var.present)
3339 return false;
4d283ec9 3340 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3341 if (var.dpl < rpl) /* DPL < RPL */
3342 return false;
3343 }
3344
3345 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3346 * rights flags
3347 */
3348 return true;
3349}
3350
3351static bool tr_valid(struct kvm_vcpu *vcpu)
3352{
3353 struct kvm_segment tr;
3354
3355 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3356
1872a3f4
AK		 3357 if (tr.unusable)
3358 return false;
b32a9918 3359 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3360 return false;
1872a3f4 3361 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3362 return false;
3363 if (!tr.present)
3364 return false;
3365
3366 return true;
3367}
3368
3369static bool ldtr_valid(struct kvm_vcpu *vcpu)
3370{
3371 struct kvm_segment ldtr;
3372
3373 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3374
1872a3f4
AK		 3375 if (ldtr.unusable)
3376 return true;
b32a9918 3377 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3378 return false;
3379 if (ldtr.type != 2)
3380 return false;
3381 if (!ldtr.present)
3382 return false;
3383
3384 return true;
3385}
3386
3387static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3388{
3389 struct kvm_segment cs, ss;
3390
3391 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3392 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3393
b32a9918
NA		 3394 return ((cs.selector & SEGMENT_RPL_MASK) ==
3395 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3396}
3397
3398/*
3399 * Check if guest state is valid. Returns true if valid, false if
3400 * not.
3401 * We assume that registers are always usable
3402 */
3403static bool guest_state_valid(struct kvm_vcpu *vcpu)
3404{
c5e97c80
GN		 3405 if (enable_unrestricted_guest)
3406 return true;
3407
648dfaa7 3408 /* real mode guest state checks */
f13882d8 3409 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3410 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3411 return false;
3412 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3413 return false;
3414 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3415 return false;
3416 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3417 return false;
3418 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3419 return false;
3420 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3421 return false;
3422 } else {
3423 /* protected mode guest state checks */
3424 if (!cs_ss_rpl_check(vcpu))
3425 return false;
3426 if (!code_segment_valid(vcpu))
3427 return false;
3428 if (!stack_segment_valid(vcpu))
3429 return false;
3430 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3431 return false;
3432 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3433 return false;
3434 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3435 return false;
3436 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3437 return false;
3438 if (!tr_valid(vcpu))
3439 return false;
3440 if (!ldtr_valid(vcpu))
3441 return false;
3442 }
3443 /* TODO:
3444 * - Add checks on RIP
3445 * - Add checks on RFLAGS
3446 */
3447
3448 return true;
3449}
3450
d77c26fc 3451static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3452{
40dcaa9f 3453 gfn_t fn;
195aefde 3454 u16 data = 0;
1f755a82 3455 int idx, r;
6aa8b732 3456
40dcaa9f 3457 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3458 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3459 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3460 if (r < 0)
10589a46 3461 goto out;
195aefde 3462 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3463 r = kvm_write_guest_page(kvm, fn++, &data,
3464 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3465 if (r < 0)
10589a46 3466 goto out;
195aefde
IE		 3467 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3468 if (r < 0)
10589a46 3469 goto out;
195aefde
IE		 3470 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3471 if (r < 0)
10589a46 3472 goto out;
195aefde 3473 data = ~0;
10589a46
MT		 3474 r = kvm_write_guest_page(kvm, fn, &data,
3475 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3476 sizeof(u8));
10589a46 3477out:
40dcaa9f 3478 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3479 return r;
6aa8b732
AK		 3480}
3481
b7ebfb05
SY		 3482static int init_rmode_identity_map(struct kvm *kvm)
3483{
40bbb9d0 3484 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
f51770ed 3485 int i, idx, r = 0;
ba049e93 3486 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3487 u32 tmp;
3488
40bbb9d0 3489 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3490 mutex_lock(&kvm->slots_lock);
3491
40bbb9d0 3492 if (likely(kvm_vmx->ept_identity_pagetable_done))
a255d479 3493 goto out2;
a255d479 3494
40bbb9d0
SC		 3495 if (!kvm_vmx->ept_identity_map_addr)
3496 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3497 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3498
d8a6e365 3499 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3500 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3501 if (r < 0)
a255d479
TC		 3502 goto out2;
3503
40dcaa9f 3504 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3505 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3506 if (r < 0)
3507 goto out;
3508 /* Set up identity-mapping pagetable for EPT in real mode */
3509 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3510 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3511 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3512 r = kvm_write_guest_page(kvm, identity_map_pfn,
3513 &tmp, i * sizeof(tmp), sizeof(tmp));
3514 if (r < 0)
3515 goto out;
3516 }
40bbb9d0 3517 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3518
b7ebfb05 3519out:
40dcaa9f 3520 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3521
3522out2:
3523 mutex_unlock(&kvm->slots_lock);
f51770ed 3524 return r;
b7ebfb05
SY		 3525}
3526
6aa8b732
AK		 3527static void seg_setup(int seg)
3528{
772e0318 3529 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3530 unsigned int ar;
6aa8b732
AK		 3531
3532 vmcs_write16(sf->selector, 0);
3533 vmcs_writel(sf->base, 0);
3534 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3535 ar = 0x93;
3536 if (seg == VCPU_SREG_CS)
3537 ar |= 0x08; /* code segment */
3a624e29
NK		 3538
3539 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3540}
3541
f78e0e2e
SY		 3542static int alloc_apic_access_page(struct kvm *kvm)
3543{
4484141a 3544 struct page *page;
f78e0e2e
SY		 3545 int r = 0;
3546
79fac95e 3547 mutex_lock(&kvm->slots_lock);
c24ae0dc 3548 if (kvm->arch.apic_access_page_done)
f78e0e2e 3549 goto out;
1d8007bd
PB		 3550 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3551 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3552 if (r)
3553 goto out;
72dc67a6 3554
73a6d941 3555 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3556 if (is_error_page(page)) {
3557 r = -EFAULT;
3558 goto out;
3559 }
3560
c24ae0dc
TC		 3561 /*
3562 * Do not pin the page in memory, so that memory hot-unplug
3563 * is able to migrate it.
3564 */
3565 put_page(page);
3566 kvm->arch.apic_access_page_done = true;
f78e0e2e 3567out:
79fac95e 3568 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3569 return r;
3570}
3571
97b7ead3 3572int allocate_vpid(void)
2384d2b3
SY		 3573{
3574 int vpid;
3575
919818ab 3576 if (!enable_vpid)
991e7a0e 3577 return 0;
2384d2b3
SY		 3578 spin_lock(&vmx_vpid_lock);
3579 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3580 if (vpid < VMX_NR_VPIDS)
2384d2b3 3581 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3582 else
3583 vpid = 0;
2384d2b3 3584 spin_unlock(&vmx_vpid_lock);
991e7a0e 3585 return vpid;
2384d2b3
SY		 3586}
3587
97b7ead3 3588void free_vpid(int vpid)
cdbecfc3 3589{
991e7a0e 3590 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3591 return;
3592 spin_lock(&vmx_vpid_lock);
991e7a0e 3593 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3594 spin_unlock(&vmx_vpid_lock);
3595}
3596
1e4329ee 3597static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3598 u32 msr, int type)
25c5f225 3599{
3e7c73e9 3600 int f = sizeof(unsigned long);
25c5f225
SY		 3601
3602 if (!cpu_has_vmx_msr_bitmap())
3603 return;
3604
ceef7d10
VK		 3605 if (static_branch_unlikely(&enable_evmcs))
3606 evmcs_touch_msr_bitmap();
3607
25c5f225
SY		 3608 /*
3609 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3610 * have the write-low and read-high bitmap offsets the wrong way round.
3611 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3612 */
25c5f225 3613 if (msr <= 0x1fff) {
8d14695f
YZ		 3614 if (type & MSR_TYPE_R)
3615 /* read-low */
3616 __clear_bit(msr, msr_bitmap + 0x000 / f);
3617
3618 if (type & MSR_TYPE_W)
3619 /* write-low */
3620 __clear_bit(msr, msr_bitmap + 0x800 / f);
3621
25c5f225
SY		 3622 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3623 msr &= 0x1fff;
8d14695f
YZ		 3624 if (type & MSR_TYPE_R)
3625 /* read-high */
3626 __clear_bit(msr, msr_bitmap + 0x400 / f);
3627
3628 if (type & MSR_TYPE_W)
3629 /* write-high */
3630 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3631
3632 }
3633}
3634
1e4329ee 3635static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3636 u32 msr, int type)
3637{
3638 int f = sizeof(unsigned long);
3639
3640 if (!cpu_has_vmx_msr_bitmap())
3641 return;
3642
ceef7d10
VK		 3643 if (static_branch_unlikely(&enable_evmcs))
3644 evmcs_touch_msr_bitmap();
3645
904e14fb
PB		 3646 /*
3647 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3648 * have the write-low and read-high bitmap offsets the wrong way round.
3649 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3650 */
3651 if (msr <= 0x1fff) {
3652 if (type & MSR_TYPE_R)
3653 /* read-low */
3654 __set_bit(msr, msr_bitmap + 0x000 / f);
3655
3656 if (type & MSR_TYPE_W)
3657 /* write-low */
3658 __set_bit(msr, msr_bitmap + 0x800 / f);
3659
3660 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3661 msr &= 0x1fff;
3662 if (type & MSR_TYPE_R)
3663 /* read-high */
3664 __set_bit(msr, msr_bitmap + 0x400 / f);
3665
3666 if (type & MSR_TYPE_W)
3667 /* write-high */
3668 __set_bit(msr, msr_bitmap + 0xc00 / f);
3669
3670 }
3671}
3672
1e4329ee 3673static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3674 u32 msr, int type, bool value)
3675{
3676 if (value)
3677 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3678 else
3679 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3680}
3681
904e14fb 3682static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3683{
904e14fb
PB		 3684 u8 mode = 0;
3685
3686 if (cpu_has_secondary_exec_ctrls() &&
fe7f895d 3687 (secondary_exec_controls_get(to_vmx(vcpu)) &
904e14fb
PB		 3688 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3689 mode |= MSR_BITMAP_MODE_X2APIC;
3690 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3691 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3692 }
3693
904e14fb 3694 return mode;
8d14695f
YZ		 3695}
3696
904e14fb
PB		 3697static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3698 u8 mode)
8d14695f 3699{
904e14fb
PB		 3700 int msr;
3701
3702 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3703 unsigned word = msr / BITS_PER_LONG;
3704 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3705 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3706 }
3707
3708 if (mode & MSR_BITMAP_MODE_X2APIC) {
3709 /*
3710 * TPR reads and writes can be virtualized even if virtual interrupt
3711 * delivery is not in use.
3712 */
3713 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3714 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3715 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3716 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3717 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3718 }
f6e90f9e 3719 }
5897297b
AK		 3720}
3721
97b7ead3 3722void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3723{
3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
3725 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3726 u8 mode = vmx_msr_bitmap_mode(vcpu);
3727 u8 changed = mode ^ vmx->msr_bitmap_mode;
3728
3729 if (!changed)
3730 return;
3731
904e14fb
PB		 3732 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3733 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3734
3735 vmx->msr_bitmap_mode = mode;
3736}
3737
b08c2896
CP		 3738void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3739{
3740 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3741 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3742 u32 i;
3743
3744 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3745 MSR_TYPE_RW, flag);
3746 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3747 MSR_TYPE_RW, flag);
3748 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3749 MSR_TYPE_RW, flag);
3750 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3751 MSR_TYPE_RW, flag);
3752 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3753 vmx_set_intercept_for_msr(msr_bitmap,
3754 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3755 vmx_set_intercept_for_msr(msr_bitmap,
3756 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3757 }
3758}
3759
2cf9af0b 3760static bool vmx_get_enable_apicv(struct kvm *kvm)
d50ab6c1 3761{
d62caabb 3762 return enable_apicv;
d50ab6c1
PB		 3763}
3764
e6c67d8c
LA		 3765static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3766{
3767 struct vcpu_vmx *vmx = to_vmx(vcpu);
3768 void *vapic_page;
3769 u32 vppr;
3770 int rvi;
3771
3772 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3773 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
96c66e87 3774 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
e6c67d8c
LA		 3775 return false;
3776
7e712684 3777 rvi = vmx_get_rvi();
e6c67d8c 3778
96c66e87 3779 vapic_page = vmx->nested.virtual_apic_map.hva;
e6c67d8c 3780 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
e6c67d8c
LA		 3781
3782 return ((rvi & 0xf0) > (vppr & 0xf0));
3783}
3784
06a5524f
WV		 3785static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3786 bool nested)
21bc8dc5
RK		 3787{
3788#ifdef CONFIG_SMP
06a5524f
WV		 3789 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3790
21bc8dc5 3791 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3792 /*
5753743f
HZ		 3793 * The vector of interrupt to be delivered to vcpu had
3794 * been set in PIR before this function.
3795 *
3796 * Following cases will be reached in this block, and
3797 * we always send a notification event in all cases as
3798 * explained below.
3799 *
3800 * Case 1: vcpu keeps in non-root mode. Sending a
3801 * notification event posts the interrupt to vcpu.
3802 *
3803 * Case 2: vcpu exits to root mode and is still
3804 * runnable. PIR will be synced to vIRR before the
3805 * next vcpu entry. Sending a notification event in
3806 * this case has no effect, as vcpu is not in root
3807 * mode.
28b835d6 3808 *
5753743f
HZ		 3809 * Case 3: vcpu exits to root mode and is blocked.
3810 * vcpu_block() has already synced PIR to vIRR and
3811 * never blocks vcpu if vIRR is not cleared. Therefore,
3812 * a blocked vcpu here does not wait for any requested
3813 * interrupts in PIR, and sending a notification event
3814 * which has no effect is safe here.
28b835d6 3815 */
28b835d6 3816
06a5524f 3817 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3818 return true;
3819 }
3820#endif
3821 return false;
3822}
3823
705699a1
WV		 3824static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3825 int vector)
3826{
3827 struct vcpu_vmx *vmx = to_vmx(vcpu);
3828
3829 if (is_guest_mode(vcpu) &&
3830 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3831 /*
3832 * If a posted intr is not recognized by hardware,
3833 * we will accomplish it in the next vmentry.
3834 */
3835 vmx->nested.pi_pending = true;
3836 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3837 /* the PIR and ON have been set by L1. */
3838 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3839 kvm_vcpu_kick(vcpu);
705699a1
WV		 3840 return 0;
3841 }
3842 return -1;
3843}
a20ed54d
YZ		 3844/*
3845 * Send interrupt to vcpu via posted interrupt way.
3846 * 1. If target vcpu is running(non-root mode), send posted interrupt
3847 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3848 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3849 * interrupt from PIR in next vmentry.
3850 */
3851static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3852{
3853 struct vcpu_vmx *vmx = to_vmx(vcpu);
3854 int r;
3855
705699a1
WV		 3856 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3857 if (!r)
3858 return;
3859
a20ed54d
YZ		 3860 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3861 return;
3862
b95234c8
PB		 3863 /* If a previous notification has sent the IPI, nothing to do. */
3864 if (pi_test_and_set_on(&vmx->pi_desc))
3865 return;
3866
06a5524f 3867 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ		 3868 kvm_vcpu_kick(vcpu);
3869}
3870
a3a8ff8e
NHE		 3871/*
3872 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3873 * will not change in the lifetime of the guest.
3874 * Note that host-state that does change is set elsewhere. E.g., host-state
3875 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3876 */
97b7ead3 3877void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3878{
3879 u32 low32, high32;
3880 unsigned long tmpl;
d6e41f11 3881 unsigned long cr0, cr3, cr4;
a3a8ff8e 3882
04ac88ab
AL		 3883 cr0 = read_cr0();
3884 WARN_ON(cr0 & X86_CR0_TS);
3885 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3886
3887 /*
3888 * Save the most likely value for this task's CR3 in the VMCS.
3889 * We can't use __get_current_cr3_fast() because we're not atomic.
3890 */
6c690ee1 3891 cr3 = __read_cr3();
d6e41f11 3892 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3893 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3894
d974baa3 3895 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3896 cr4 = cr4_read_shadow();
d974baa3 3897 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3898 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3899
a3a8ff8e 3900 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3901#ifdef CONFIG_X86_64
3902 /*
3903 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3904 * vmx_prepare_switch_to_host(), in case userspace uses
3905 * the null selectors too (the expected case).
b2da15ac
AK		 3906 */
3907 vmcs_write16(HOST_DS_SELECTOR, 0);
3908 vmcs_write16(HOST_ES_SELECTOR, 0);
3909#else
a3a8ff8e
NHE		 3910 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3911 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3912#endif
a3a8ff8e
NHE		 3913 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3914 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3915
2342080c 3916 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
a3a8ff8e 3917
453eafbe 3918 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3919
3920 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3921 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3922 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3923 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3924
3925 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3926 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3927 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3928 }
5a5e8a15 3929
c73da3fc 3930 if (cpu_has_load_ia32_efer())
5a5e8a15 3931 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3932}
3933
97b7ead3 3934void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3935{
3936 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3937 if (enable_ept)
3938 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3939 if (is_guest_mode(&vmx->vcpu))
3940 vmx->vcpu.arch.cr4_guest_owned_bits &=
3941 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3942 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3943}
3944
c075c3e4 3945u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
01e439be
YZ		 3946{
3947 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3948
d62caabb 3949 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3950 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3951
3952 if (!enable_vnmi)
3953 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3954
804939ea
SC		 3955 if (!enable_preemption_timer)
3956 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3957
01e439be
YZ		 3958 return pin_based_exec_ctrl;
3959}
3960
d62caabb
AS		 3961static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3962{
3963 struct vcpu_vmx *vmx = to_vmx(vcpu);
3964
c5f2c766 3965 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3966 if (cpu_has_secondary_exec_ctrls()) {
3967 if (kvm_vcpu_apicv_active(vcpu))
fe7f895d 3968 secondary_exec_controls_setbit(vmx,
3ce424e4
RK		 3969 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3970 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3971 else
fe7f895d 3972 secondary_exec_controls_clearbit(vmx,
3ce424e4
RK		 3973 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3974 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3975 }
3976
3977 if (cpu_has_vmx_msr_bitmap())
904e14fb 3978 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3979}
3980
89b0c9f5
SC		 3981u32 vmx_exec_control(struct vcpu_vmx *vmx)
3982{
3983 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3984
3985 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3986 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3987
3988 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3989 exec_control &= ~CPU_BASED_TPR_SHADOW;
3990#ifdef CONFIG_X86_64
3991 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3992 CPU_BASED_CR8_LOAD_EXITING;
3993#endif
3994 }
3995 if (!enable_ept)
3996 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3997 CPU_BASED_CR3_LOAD_EXITING |
3998 CPU_BASED_INVLPG_EXITING;
3999 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4000 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4001 CPU_BASED_MONITOR_EXITING);
4002 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4003 exec_control &= ~CPU_BASED_HLT_EXITING;
4004 return exec_control;
4005}
4006
4007
80154d77 4008static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 4009{
80154d77
PB		 4010 struct kvm_vcpu *vcpu = &vmx->vcpu;
4011
bf8179a0 4012 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 4013
f99e3daf
CP		 4014 if (pt_mode == PT_MODE_SYSTEM)
4015 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 4016 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 4017 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4018 if (vmx->vpid == 0)
4019 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4020 if (!enable_ept) {
4021 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4022 enable_unrestricted_guest = 0;
4023 }
4024 if (!enable_unrestricted_guest)
4025 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 4026 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 4027 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 4028 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 4029 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4030 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4031 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 4032
4033 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4034 * in vmx_set_cr4. */
4035 exec_control &= ~SECONDARY_EXEC_DESC;
4036
abc4fc58
AG		 4037 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4038 (handle_vmptrld).
4039 We can NOT enable shadow_vmcs here because we don't have yet
4040 a current VMCS12
4041 */
4042 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 4043
4044 if (!enable_pml)
4045 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 4046
3db13480
PB		 4047 if (vmx_xsaves_supported()) {
4048 /* Exposing XSAVES only when XSAVE is exposed */
4049 bool xsaves_enabled =
4050 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4051 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4052
4053 if (!xsaves_enabled)
4054 exec_control &= ~SECONDARY_EXEC_XSAVES;
4055
4056 if (nested) {
4057 if (xsaves_enabled)
6677f3da 4058 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 4059 SECONDARY_EXEC_XSAVES;
4060 else
6677f3da 4061 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 4062 ~SECONDARY_EXEC_XSAVES;
4063 }
4064 }
4065
80154d77
PB		 4066 if (vmx_rdtscp_supported()) {
4067 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4068 if (!rdtscp_enabled)
4069 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4070
4071 if (nested) {
4072 if (rdtscp_enabled)
6677f3da 4073 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4074 SECONDARY_EXEC_RDTSCP;
4075 else
6677f3da 4076 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4077 ~SECONDARY_EXEC_RDTSCP;
4078 }
4079 }
4080
4081 if (vmx_invpcid_supported()) {
4082 /* Exposing INVPCID only when PCID is exposed */
4083 bool invpcid_enabled =
4084 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4085 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4086
4087 if (!invpcid_enabled) {
4088 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4089 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4090 }
4091
4092 if (nested) {
4093 if (invpcid_enabled)
6677f3da 4094 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4095 SECONDARY_EXEC_ENABLE_INVPCID;
4096 else
6677f3da 4097 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4098 ~SECONDARY_EXEC_ENABLE_INVPCID;
4099 }
4100 }
4101
45ec368c
JM		 4102 if (vmx_rdrand_supported()) {
4103 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4104 if (rdrand_enabled)
736fdf72 4105 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4106
4107 if (nested) {
4108 if (rdrand_enabled)
6677f3da 4109 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4110 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 4111 else
6677f3da 4112 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4113 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4114 }
4115 }
4116
75f4fc8d
JM		 4117 if (vmx_rdseed_supported()) {
4118 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4119 if (rdseed_enabled)
736fdf72 4120 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4121
4122 if (nested) {
4123 if (rdseed_enabled)
6677f3da 4124 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4125 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 4126 else
6677f3da 4127 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4128 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4129 }
4130 }
4131
e69e72fa
TX		 4132 if (vmx_waitpkg_supported()) {
4133 bool waitpkg_enabled =
4134 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4135
4136 if (!waitpkg_enabled)
4137 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4138
4139 if (nested) {
4140 if (waitpkg_enabled)
4141 vmx->nested.msrs.secondary_ctls_high |=
4142 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4143 else
4144 vmx->nested.msrs.secondary_ctls_high &=
4145 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4146 }
4147 }
4148
80154d77 4149 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 4150}
4151
ce88decf
XG		 4152static void ept_set_mmio_spte_mask(void)
4153{
4154 /*
4155 * EPT Misconfigurations can be generated if the value of bits 2:0
4156 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 4157 */
dcdca5fe 4158 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4af77151 4159 VMX_EPT_MISCONFIG_WX_VALUE, 0);
ce88decf
XG		 4160}
4161
f53cd63c 4162#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 4163
944c3464
SC		 4164/*
4165 * Sets up the vmcs for emulated real mode.
4166 */
4167static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4168{
944c3464
SC		 4169 if (nested)
4170 nested_vmx_vcpu_setup();
4171
25c5f225 4172 if (cpu_has_vmx_msr_bitmap())
904e14fb 4173 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4174
6aa8b732
AK		 4175 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4176
6aa8b732 4177 /* Control */
3af80fec 4178 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4179
3af80fec 4180 exec_controls_set(vmx, vmx_exec_control(vmx));
6aa8b732 4181
dfa169bb 4182 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4183 vmx_compute_secondary_exec_control(vmx);
3af80fec 4184 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
dfa169bb 4185 }
f78e0e2e 4186
d62caabb 4187 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4188 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4189 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4190 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4191 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4192
4193 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4194
0bcf261c 4195 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4196 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4197 }
4198
b31c114b 4199 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4200 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4201 vmx->ple_window = ple_window;
4202 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4203 }
4204
c3707958
XG		 4205 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4206 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4207 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4208
9581d442
AK		 4209 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4210 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4211 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4212 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4213 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4214
2a499e49
BD		 4215 if (cpu_has_vmx_vmfunc())
4216 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4217
2cc51560
ED		 4218 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4219 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4220 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4221 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4222 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4223
74545705
RK		 4224 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4225 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4226
3af80fec 4227 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4228
4229 /* 22.2.1, 20.8.1 */
3af80fec 4230 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
1c3d14fe 4231
bd7e5b08
PB		 4232 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4233 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4234
bf8179a0 4235 set_cr4_guest_host_mask(vmx);
e00c8cf2 4236
35fbe0d4
XL		 4237 if (vmx->vpid != 0)
4238 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4239
f53cd63c
WL		 4240 if (vmx_xsaves_supported())
4241 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4242
4e59516a 4243 if (enable_pml) {
4e59516a
PF		 4244 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4245 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4246 }
0b665d30
SC		 4247
4248 if (cpu_has_vmx_encls_vmexit())
4249 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4250
4251 if (pt_mode == PT_MODE_HOST_GUEST) {
4252 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4253 /* Bit[6~0] are forced to 1, writes are ignored. */
4254 vmx->pt_desc.guest.output_mask = 0x7F;
4255 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4256 }
e00c8cf2
AK		 4257}
4258
d28bc9dd 4259static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4260{
4261 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4262 struct msr_data apic_base_msr;
d28bc9dd 4263 u64 cr0;
e00c8cf2 4264
7ffd92c5 4265 vmx->rmode.vm86_active = 0;
d28b387f 4266 vmx->spec_ctrl = 0;
e00c8cf2 4267
6e3ba4ab
TX		 4268 vmx->msr_ia32_umwait_control = 0;
4269
518e7b94 4270 vcpu->arch.microcode_version = 0x100000000ULL;
ad312c7c 4271 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
95c06540 4272 vmx->hv_deadline_tsc = -1;
d28bc9dd
NA		 4273 kvm_set_cr8(vcpu, 0);
4274
4275 if (!init_event) {
4276 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4277 MSR_IA32_APICBASE_ENABLE;
4278 if (kvm_vcpu_is_reset_bsp(vcpu))
4279 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4280 apic_base_msr.host_initiated = true;
4281 kvm_set_apic_base(vcpu, &apic_base_msr);
4282 }
e00c8cf2 4283
2fb92db1
AK		 4284 vmx_segment_cache_clear(vmx);
4285
5706be0d 4286 seg_setup(VCPU_SREG_CS);
66450a21 4287 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4288 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4289
4290 seg_setup(VCPU_SREG_DS);
4291 seg_setup(VCPU_SREG_ES);
4292 seg_setup(VCPU_SREG_FS);
4293 seg_setup(VCPU_SREG_GS);
4294 seg_setup(VCPU_SREG_SS);
4295
4296 vmcs_write16(GUEST_TR_SELECTOR, 0);
4297 vmcs_writel(GUEST_TR_BASE, 0);
4298 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4299 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4300
4301 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4302 vmcs_writel(GUEST_LDTR_BASE, 0);
4303 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4304 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4305
d28bc9dd
NA		 4306 if (!init_event) {
4307 vmcs_write32(GUEST_SYSENTER_CS, 0);
4308 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4309 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4310 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4311 }
e00c8cf2 4312
c37c2873 4313 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4314 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4315
e00c8cf2
AK		 4316 vmcs_writel(GUEST_GDTR_BASE, 0);
4317 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4318
4319 vmcs_writel(GUEST_IDTR_BASE, 0);
4320 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4321
443381a8 4322 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4323 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4324 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4325 if (kvm_mpx_supported())
4326 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4327
e00c8cf2
AK		 4328 setup_msrs(vmx);
4329
6aa8b732
AK		 4330 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4331
d28bc9dd 4332 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4333 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4334 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4335 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4336 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4337 vmcs_write32(TPR_THRESHOLD, 0);
4338 }
4339
a73896cb 4340 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4341
d28bc9dd 4342 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4343 vmx->vcpu.arch.cr0 = cr0;
f2463247 4344 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4345 vmx_set_cr4(vcpu, 0);
5690891b 4346 vmx_set_efer(vcpu, 0);
bd7e5b08 4347
d28bc9dd 4348 update_exception_bitmap(vcpu);
6aa8b732 4349
dd5f5341 4350 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4351 if (init_event)
4352 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4353}
4354
55d2375e 4355static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4356{
2183f564 4357 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK		 4358}
4359
c9a7953f 4360static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4361{
d02fcf50 4362 if (!enable_vnmi ||
8a1b4392 4363 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4364 enable_irq_window(vcpu);
4365 return;
4366 }
3b86cd99 4367
2183f564 4368 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK		 4369}
4370
66fd3f7f 4371static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4372{
9c8cba37 4373 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4374 uint32_t intr;
4375 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4376
229456fc 4377 trace_kvm_inj_virq(irq);
2714d1d3 4378
fa89a817 4379 ++vcpu->stat.irq_injections;
7ffd92c5 4380 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4381 int inc_eip = 0;
4382 if (vcpu->arch.interrupt.soft)
4383 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 4384 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
85f455f7
ED		 4385 return;
4386 }
66fd3f7f
GN		 4387 intr = irq | INTR_INFO_VALID_MASK;
4388 if (vcpu->arch.interrupt.soft) {
4389 intr |= INTR_TYPE_SOFT_INTR;
4390 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4391 vmx->vcpu.arch.event_exit_inst_len);
4392 } else
4393 intr |= INTR_TYPE_EXT_INTR;
4394 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4395
4396 vmx_clear_hlt(vcpu);
85f455f7
ED		 4397}
4398
f08864b4
SY		 4399static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4400{
66a5a347
JK		 4401 struct vcpu_vmx *vmx = to_vmx(vcpu);
4402
d02fcf50 4403 if (!enable_vnmi) {
8a1b4392
PB		 4404 /*
4405 * Tracking the NMI-blocked state in software is built upon
4406 * finding the next open IRQ window. This, in turn, depends on
4407 * well-behaving guests: They have to keep IRQs disabled at
4408 * least as long as the NMI handler runs. Otherwise we may
4409 * cause NMI nesting, maybe breaking the guest. But as this is
4410 * highly unlikely, we can live with the residual risk.
4411 */
4412 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4413 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4414 }
4415
4c4a6f79
PB		 4416 ++vcpu->stat.nmi_injections;
4417 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4418
7ffd92c5 4419 if (vmx->rmode.vm86_active) {
9497e1f2 4420 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
66a5a347
JK		 4421 return;
4422 }
c5a6d5f7 4423
f08864b4
SY		 4424 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4425 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4426
4427 vmx_clear_hlt(vcpu);
f08864b4
SY		 4428}
4429
97b7ead3 4430bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4431{
4c4a6f79
PB		 4432 struct vcpu_vmx *vmx = to_vmx(vcpu);
4433 bool masked;
4434
d02fcf50 4435 if (!enable_vnmi)
8a1b4392 4436 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4437 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4438 return false;
4c4a6f79
PB		 4439 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4440 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4441 return masked;
3cfc3092
JK		 4442}
4443
97b7ead3 4444void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4445{
4446 struct vcpu_vmx *vmx = to_vmx(vcpu);
4447
d02fcf50 4448 if (!enable_vnmi) {
8a1b4392
PB		 4449 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4450 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4451 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4452 }
4453 } else {
4454 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4455 if (masked)
4456 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4457 GUEST_INTR_STATE_NMI);
4458 else
4459 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4460 GUEST_INTR_STATE_NMI);
4461 }
3cfc3092
JK		 4462}
4463
2505dc9f
JK		 4464static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4465{
b6b8a145
JK		 4466 if (to_vmx(vcpu)->nested.nested_run_pending)
4467 return 0;
ea8ceb83 4468
d02fcf50 4469 if (!enable_vnmi &&
8a1b4392
PB		 4470 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4471 return 0;
4472
2505dc9f
JK		 4473 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4474 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4475 | GUEST_INTR_STATE_NMI));
4476}
4477
78646121
GN		 4478static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4479{
b6b8a145
JK		 4480 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4481 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4482 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4483 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4484}
4485
cbc94022
IE		 4486static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4487{
4488 int ret;
cbc94022 4489
f7eaeb0a
SC		 4490 if (enable_unrestricted_guest)
4491 return 0;
4492
1d8007bd
PB		 4493 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4494 PAGE_SIZE * 3);
cbc94022
IE		 4495 if (ret)
4496 return ret;
40bbb9d0 4497 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4498 return init_rmode_tss(kvm);
cbc94022
IE		 4499}
4500
2ac52ab8
SC		 4501static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4502{
40bbb9d0 4503 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4504 return 0;
4505}
4506
0ca1b4f4 4507static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4508{
77ab6db0 4509 switch (vec) {
77ab6db0 4510 case BP_VECTOR:
c573cd22
JK		 4511 /*
4512 * Update instruction length as we may reinject the exception
4513 * from user space while in guest debugging mode.
4514 */
4515 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4516 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4517 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4518 return false;
4519 /* fall through */
4520 case DB_VECTOR:
4521 if (vcpu->guest_debug &
4522 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4523 return false;
d0bfb940
JK		 4524 /* fall through */
4525 case DE_VECTOR:
77ab6db0
JK		 4526 case OF_VECTOR:
4527 case BR_VECTOR:
4528 case UD_VECTOR:
4529 case DF_VECTOR:
4530 case SS_VECTOR:
4531 case GP_VECTOR:
4532 case MF_VECTOR:
0ca1b4f4
GN		 4533 return true;
4534 break;
77ab6db0 4535 }
0ca1b4f4
GN		 4536 return false;
4537}
4538
4539static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4540 int vec, u32 err_code)
4541{
4542 /*
4543 * Instruction with address size override prefix opcode 0x67
4544 * Cause the #SS fault with 0 error code in VM86 mode.
4545 */
4546 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
60fc3d02 4547 if (kvm_emulate_instruction(vcpu, 0)) {
0ca1b4f4
GN		 4548 if (vcpu->arch.halt_request) {
4549 vcpu->arch.halt_request = 0;
5cb56059 4550 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4551 }
4552 return 1;
4553 }
4554 return 0;
4555 }
4556
4557 /*
4558 * Forward all other exceptions that are valid in real mode.
4559 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4560 * the required debugging infrastructure rework.
4561 */
4562 kvm_queue_exception(vcpu, vec);
4563 return 1;
6aa8b732
AK		 4564}
4565
a0861c02
AK		 4566/*
4567 * Trigger machine check on the host. We assume all the MSRs are already set up
4568 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4569 * We pass a fake environment to the machine check handler because we want
4570 * the guest to be always treated like user space, no matter what context
4571 * it used internally.
4572 */
4573static void kvm_machine_check(void)
4574{
4575#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4576 struct pt_regs regs = {
4577 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4578 .flags = X86_EFLAGS_IF,
4579 };
4580
4581 do_machine_check(&regs, 0);
4582#endif
4583}
4584
851ba692 4585static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02 4586{
95b5a48c 4587 /* handled by vmx_vcpu_run() */
a0861c02
AK		 4588 return 1;
4589}
4590
95b5a48c 4591static int handle_exception_nmi(struct kvm_vcpu *vcpu)
6aa8b732 4592{
1155f76a 4593 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4594 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4595 u32 intr_info, ex_no, error_code;
42dbaa5a 4596 unsigned long cr2, rip, dr6;
6aa8b732 4597 u32 vect_info;
6aa8b732 4598
1155f76a 4599 vect_info = vmx->idt_vectoring_info;
88786475 4600 intr_info = vmx->exit_intr_info;
6aa8b732 4601
2ea72039 4602 if (is_machine_check(intr_info) || is_nmi(intr_info))
95b5a48c 4603 return 1; /* handled by handle_exception_nmi_irqoff() */
2ab455cc 4604
082d06ed
WL		 4605 if (is_invalid_opcode(intr_info))
4606 return handle_ud(vcpu);
7aa81cc0 4607
6aa8b732 4608 error_code = 0;
2e11384c 4609 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4610 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4611
9e869480
LA		 4612 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4613 WARN_ON_ONCE(!enable_vmware_backdoor);
a6c6ed1e
SC		 4614
4615 /*
4616 * VMware backdoor emulation on #GP interception only handles
4617 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4618 * error code on #GP.
4619 */
4620 if (error_code) {
4621 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4622 return 1;
4623 }
60fc3d02 4624 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9e869480
LA		 4625 }
4626
bf4ca23e
XG		 4627 /*
4628 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4629 * MMIO, it is better to report an internal error.
4630 * See the comments in vmx_handle_exit.
4631 */
4632 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4633 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4634 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4635 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4636 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4637 vcpu->run->internal.data[0] = vect_info;
4638 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4639 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4640 return 0;
4641 }
4642
6aa8b732
AK		 4643 if (is_page_fault(intr_info)) {
4644 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4645 /* EPT won't cause page fault directly */
4646 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4647 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4648 }
4649
d0bfb940 4650 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4651
4652 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4653 return handle_rmode_exception(vcpu, ex_no, error_code);
4654
42dbaa5a 4655 switch (ex_no) {
54a20552
EN		 4656 case AC_VECTOR:
4657 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4658 return 1;
42dbaa5a
JK		 4659 case DB_VECTOR:
4660 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4661 if (!(vcpu->guest_debug &
4662 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1fc5d194 4663 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4664 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4665 if (is_icebp(intr_info))
1957aa63 4666 WARN_ON(!skip_emulated_instruction(vcpu));
fd2a445a 4667
42dbaa5a
JK		 4668 kvm_queue_exception(vcpu, DB_VECTOR);
4669 return 1;
4670 }
4671 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4672 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4673 /* fall through */
4674 case BP_VECTOR:
c573cd22
JK		 4675 /*
4676 * Update instruction length as we may reinject #BP from
4677 * user space while in guest debugging mode. Reading it for
4678 * #DB as well causes no harm, it is not used in that case.
4679 */
4680 vmx->vcpu.arch.event_exit_inst_len =
4681 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4682 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4683 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4684 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4685 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4686 break;
4687 default:
d0bfb940
JK		 4688 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4689 kvm_run->ex.exception = ex_no;
4690 kvm_run->ex.error_code = error_code;
42dbaa5a 4691 break;
6aa8b732 4692 }
6aa8b732
AK		 4693 return 0;
4694}
4695
851ba692 4696static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4697{
1165f5fe 4698 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4699 return 1;
4700}
4701
851ba692 4702static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4703{
851ba692 4704 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4705 vcpu->mmio_needed = 0;
988ad74f
AK		 4706 return 0;
4707}
6aa8b732 4708
851ba692 4709static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4710{
bfdaab09 4711 unsigned long exit_qualification;
dca7f128 4712 int size, in, string;
039576c0 4713 unsigned port;
6aa8b732 4714
bfdaab09 4715 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4716 string = (exit_qualification & 16) != 0;
e70669ab 4717
cf8f70bf 4718 ++vcpu->stat.io_exits;
e70669ab 4719
432baf60 4720 if (string)
60fc3d02 4721 return kvm_emulate_instruction(vcpu, 0);
e70669ab 4722
cf8f70bf
GN		 4723 port = exit_qualification >> 16;
4724 size = (exit_qualification & 7) + 1;
432baf60 4725 in = (exit_qualification & 8) != 0;
cf8f70bf 4726
dca7f128 4727 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4728}
4729
102d8325
IM		 4730static void
4731vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4732{
4733 /*
4734 * Patch in the VMCALL instruction:
4735 */
4736 hypercall[0] = 0x0f;
4737 hypercall[1] = 0x01;
4738 hypercall[2] = 0xc1;
102d8325
IM		 4739}
4740
0fa06071 4741/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4742static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4743{
eeadf9e7 4744 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4745 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4746 unsigned long orig_val = val;
4747
eeadf9e7
NHE		 4748 /*
4749 * We get here when L2 changed cr0 in a way that did not change
4750 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4751 * but did change L0 shadowed bits. So we first calculate the
4752 * effective cr0 value that L1 would like to write into the
4753 * hardware. It consists of the L2-owned bits from the new
4754 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4755 */
1a0d74e6
JK		 4756 val = (val & ~vmcs12->cr0_guest_host_mask) |
4757 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4758
3899152c 4759 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4760 return 1;
1a0d74e6
JK		 4761
4762 if (kvm_set_cr0(vcpu, val))
4763 return 1;
4764 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4765 return 0;
1a0d74e6
JK		 4766 } else {
4767 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4768 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4769 return 1;
3899152c 4770
eeadf9e7 4771 return kvm_set_cr0(vcpu, val);
1a0d74e6 4772 }
eeadf9e7
NHE		 4773}
4774
4775static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4776{
4777 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4778 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4779 unsigned long orig_val = val;
4780
4781 /* analogously to handle_set_cr0 */
4782 val = (val & ~vmcs12->cr4_guest_host_mask) |
4783 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4784 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4785 return 1;
1a0d74e6 4786 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4787 return 0;
4788 } else
4789 return kvm_set_cr4(vcpu, val);
4790}
4791
0367f205
PB		 4792static int handle_desc(struct kvm_vcpu *vcpu)
4793{
4794 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
60fc3d02 4795 return kvm_emulate_instruction(vcpu, 0);
0367f205
PB		 4796}
4797
851ba692 4798static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4799{
229456fc 4800 unsigned long exit_qualification, val;
6aa8b732
AK		 4801 int cr;
4802 int reg;
49a9b07e 4803 int err;
6affcbed 4804 int ret;
6aa8b732 4805
bfdaab09 4806 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4807 cr = exit_qualification & 15;
4808 reg = (exit_qualification >> 8) & 15;
4809 switch ((exit_qualification >> 4) & 3) {
4810 case 0: /* mov to cr */
1e32c079 4811 val = kvm_register_readl(vcpu, reg);
229456fc 4812 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4813 switch (cr) {
4814 case 0:
eeadf9e7 4815 err = handle_set_cr0(vcpu, val);
6affcbed 4816 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4817 case 3:
e1de91cc 4818 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4819 err = kvm_set_cr3(vcpu, val);
6affcbed 4820 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4821 case 4:
eeadf9e7 4822 err = handle_set_cr4(vcpu, val);
6affcbed 4823 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4824 case 8: {
4825 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4826 u8 cr8 = (u8)val;
eea1cff9 4827 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4828 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4829 if (lapic_in_kernel(vcpu))
6affcbed 4830 return ret;
0a5fff19 4831 if (cr8_prev <= cr8)
6affcbed
KH		 4832 return ret;
4833 /*
4834 * TODO: we might be squashing a
4835 * KVM_GUESTDBG_SINGLESTEP-triggered
4836 * KVM_EXIT_DEBUG here.
4837 */
851ba692 4838 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4839 return 0;
4840 }
4b8073e4 4841 }
6aa8b732 4842 break;
25c4c276 4843 case 2: /* clts */
bd7e5b08
PB		 4844 WARN_ONCE(1, "Guest should always own CR0.TS");
4845 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4846 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4847 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4848 case 1: /*mov from cr*/
4849 switch (cr) {
4850 case 3:
e1de91cc 4851 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4852 val = kvm_read_cr3(vcpu);
4853 kvm_register_write(vcpu, reg, val);
4854 trace_kvm_cr_read(cr, val);
6affcbed 4855 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4856 case 8:
229456fc
MT		 4857 val = kvm_get_cr8(vcpu);
4858 kvm_register_write(vcpu, reg, val);
4859 trace_kvm_cr_read(cr, val);
6affcbed 4860 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4861 }
4862 break;
4863 case 3: /* lmsw */
a1f83a74 4864 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4865 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4866 kvm_lmsw(vcpu, val);
6aa8b732 4867
6affcbed 4868 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4869 default:
4870 break;
4871 }
851ba692 4872 vcpu->run->exit_reason = 0;
a737f256 4873 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4874 (int)(exit_qualification >> 4) & 3, cr);
4875 return 0;
4876}
4877
851ba692 4878static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4879{
bfdaab09 4880 unsigned long exit_qualification;
16f8a6f9
NA		 4881 int dr, dr7, reg;
4882
4883 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4884 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4885
4886 /* First, if DR does not exist, trigger UD */
4887 if (!kvm_require_dr(vcpu, dr))
4888 return 1;
6aa8b732 4889
f2483415 4890 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4891 if (!kvm_require_cpl(vcpu, 0))
4892 return 1;
16f8a6f9
NA		 4893 dr7 = vmcs_readl(GUEST_DR7);
4894 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4895 /*
4896 * As the vm-exit takes precedence over the debug trap, we
4897 * need to emulate the latter, either for the host or the
4898 * guest debugging itself.
4899 */
4900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4901 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4902 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4903 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4904 vcpu->run->debug.arch.exception = DB_VECTOR;
4905 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4906 return 0;
4907 } else {
1fc5d194 4908 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4909 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4910 kvm_queue_exception(vcpu, DB_VECTOR);
4911 return 1;
4912 }
4913 }
4914
81908bf4 4915 if (vcpu->guest_debug == 0) {
2183f564 4916 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4917
4918 /*
4919 * No more DR vmexits; force a reload of the debug registers
4920 * and reenter on this instruction. The next vmexit will
4921 * retrieve the full state of the debug registers.
4922 */
4923 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4924 return 1;
4925 }
4926
42dbaa5a
JK		 4927 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4928 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4929 unsigned long val;
4c4d563b
JK		 4930
4931 if (kvm_get_dr(vcpu, dr, &val))
4932 return 1;
4933 kvm_register_write(vcpu, reg, val);
020df079 4934 } else
5777392e 4935 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4936 return 1;
4937
6affcbed 4938 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4939}
4940
73aaf249
JK		 4941static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4942{
4943 return vcpu->arch.dr6;
4944}
4945
4946static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4947{
4948}
4949
81908bf4
PB		 4950static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4951{
81908bf4
PB		 4952 get_debugreg(vcpu->arch.db[0], 0);
4953 get_debugreg(vcpu->arch.db[1], 1);
4954 get_debugreg(vcpu->arch.db[2], 2);
4955 get_debugreg(vcpu->arch.db[3], 3);
4956 get_debugreg(vcpu->arch.dr6, 6);
4957 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4958
4959 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2183f564 4960 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4961}
4962
020df079
GN		 4963static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4964{
4965 vmcs_writel(GUEST_DR7, val);
4966}
4967
851ba692 4968static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4969{
6a908b62 4970 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK		 4971}
4972
851ba692 4973static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4974{
1edce0a9 4975 return kvm_emulate_rdmsr(vcpu);
6aa8b732
AK		 4976}
4977
851ba692 4978static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4979{
1edce0a9 4980 return kvm_emulate_wrmsr(vcpu);
6aa8b732
AK		 4981}
4982
851ba692 4983static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4984{
eb90f341 4985 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4986 return 1;
4987}
4988
851ba692 4989static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4990{
2183f564 4991 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 4992
3842d135
AK		 4993 kvm_make_request(KVM_REQ_EVENT, vcpu);
4994
a26bf12a 4995 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4996 return 1;
4997}
4998
851ba692 4999static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5000{
d3bef15f 5001 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5002}
5003
851ba692 5004static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5005{
0d9c055e 5006 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 5007}
5008
ec25d5e6
GN		 5009static int handle_invd(struct kvm_vcpu *vcpu)
5010{
60fc3d02 5011 return kvm_emulate_instruction(vcpu, 0);
ec25d5e6
GN		 5012}
5013
851ba692 5014static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5015{
f9c617f6 5016 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5017
5018 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 5019 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 5020}
5021
fee84b07
AK		 5022static int handle_rdpmc(struct kvm_vcpu *vcpu)
5023{
5024 int err;
5025
5026 err = kvm_rdpmc(vcpu);
6affcbed 5027 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 5028}
5029
851ba692 5030static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5031{
6affcbed 5032 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5033}
5034
2acf923e
DC		 5035static int handle_xsetbv(struct kvm_vcpu *vcpu)
5036{
5037 u64 new_bv = kvm_read_edx_eax(vcpu);
de3cd117 5038 u32 index = kvm_rcx_read(vcpu);
2acf923e
DC		 5039
5040 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 5041 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 5042 return 1;
5043}
5044
851ba692 5045static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5046{
58fbbf26
KT		 5047 if (likely(fasteoi)) {
5048 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5049 int access_type, offset;
5050
5051 access_type = exit_qualification & APIC_ACCESS_TYPE;
5052 offset = exit_qualification & APIC_ACCESS_OFFSET;
5053 /*
5054 * Sane guest uses MOV to write EOI, with written value
5055 * not cared. So make a short-circuit here by avoiding
5056 * heavy instruction emulation.
5057 */
5058 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5059 (offset == APIC_EOI)) {
5060 kvm_lapic_set_eoi(vcpu);
6affcbed 5061 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 5062 }
5063 }
60fc3d02 5064 return kvm_emulate_instruction(vcpu, 0);
f78e0e2e
SY		 5065}
5066
c7c9c56c
YZ		 5067static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5068{
5069 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5070 int vector = exit_qualification & 0xff;
5071
5072 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5073 kvm_apic_set_eoi_accelerated(vcpu, vector);
5074 return 1;
5075}
5076
83d4c286
YZ		 5077static int handle_apic_write(struct kvm_vcpu *vcpu)
5078{
5079 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5080 u32 offset = exit_qualification & 0xfff;
5081
5082 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5083 kvm_apic_write_nodecode(vcpu, offset);
5084 return 1;
5085}
5086
851ba692 5087static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5088{
60637aac 5089 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5090 unsigned long exit_qualification;
e269fb21
JK		 5091 bool has_error_code = false;
5092 u32 error_code = 0;
37817f29 5093 u16 tss_selector;
7f3d35fd 5094 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5095
5096 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5097 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5098 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5099
5100 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5101
5102 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5103 if (reason == TASK_SWITCH_GATE && idt_v) {
5104 switch (type) {
5105 case INTR_TYPE_NMI_INTR:
5106 vcpu->arch.nmi_injected = false;
654f06fc 5107 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5108 break;
5109 case INTR_TYPE_EXT_INTR:
66fd3f7f 5110 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5111 kvm_clear_interrupt_queue(vcpu);
5112 break;
5113 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5114 if (vmx->idt_vectoring_info &
5115 VECTORING_INFO_DELIVER_CODE_MASK) {
5116 has_error_code = true;
5117 error_code =
5118 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5119 }
5120 /* fall through */
64a7ec06
GN		 5121 case INTR_TYPE_SOFT_EXCEPTION:
5122 kvm_clear_exception_queue(vcpu);
5123 break;
5124 default:
5125 break;
5126 }
60637aac 5127 }
37817f29
IE		 5128 tss_selector = exit_qualification;
5129
64a7ec06
GN		 5130 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5131 type != INTR_TYPE_EXT_INTR &&
5132 type != INTR_TYPE_NMI_INTR))
1957aa63 5133 WARN_ON(!skip_emulated_instruction(vcpu));
64a7ec06 5134
42dbaa5a
JK		 5135 /*
5136 * TODO: What about debug traps on tss switch?
5137 * Are we supposed to inject them and update dr6?
5138 */
1051778f
SC		 5139 return kvm_task_switch(vcpu, tss_selector,
5140 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
60fc3d02 5141 reason, has_error_code, error_code);
37817f29
IE		 5142}
5143
851ba692 5144static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5145{
f9c617f6 5146 unsigned long exit_qualification;
1439442c 5147 gpa_t gpa;
eebed243 5148 u64 error_code;
1439442c 5149
f9c617f6 5150 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5151
0be9c7a8
GN		 5152 /*
5153 * EPT violation happened while executing iret from NMI,
5154 * "blocked by NMI" bit has to be set before next VM entry.
5155 * There are errata that may cause this bit to not be set:
5156 * AAK134, BY25.
5157 */
bcd1c294 5158 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5159 enable_vnmi &&
bcd1c294 5160 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5161 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5162
1439442c 5163 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5164 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5165
27959a44 5166 /* Is it a read fault? */
ab22a473 5167 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5168 ? PFERR_USER_MASK : 0;
5169 /* Is it a write fault? */
ab22a473 5170 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5171 ? PFERR_WRITE_MASK : 0;
5172 /* Is it a fetch fault? */
ab22a473 5173 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5174 ? PFERR_FETCH_MASK : 0;
5175 /* ept page table entry is present? */
5176 error_code |= (exit_qualification &
5177 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5178 EPT_VIOLATION_EXECUTABLE))
5179 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5180
eebed243
PB		 5181 error_code |= (exit_qualification & 0x100) != 0 ?
5182 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5183
25d92081 5184 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5185 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5186}
5187
851ba692 5188static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5189{
68f89400
MT		 5190 gpa_t gpa;
5191
9034e6e8
PB		 5192 /*
5193 * A nested guest cannot optimize MMIO vmexits, because we have an
5194 * nGPA here instead of the required GPA.
5195 */
68f89400 5196 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5197 if (!is_guest_mode(vcpu) &&
5198 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5199 trace_kvm_fast_mmio(gpa);
1957aa63 5200 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 5201 }
68f89400 5202
c75d0edc 5203 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5204}
5205
851ba692 5206static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5207{
d02fcf50 5208 WARN_ON_ONCE(!enable_vnmi);
2183f564 5209 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 5210 ++vcpu->stat.nmi_window_exits;
3842d135 5211 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5212
5213 return 1;
5214}
5215
80ced186 5216static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5217{
8b3079a5 5218 struct vcpu_vmx *vmx = to_vmx(vcpu);
49e9d557 5219 bool intr_window_requested;
b8405c18 5220 unsigned count = 130;
49e9d557 5221
2bb8cafe
SC		 5222 /*
5223 * We should never reach the point where we are emulating L2
5224 * due to invalid guest state as that means we incorrectly
5225 * allowed a nested VMEntry with an invalid vmcs12.
5226 */
5227 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5228
2183f564
SC		 5229 intr_window_requested = exec_controls_get(vmx) &
5230 CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5231
98eb2f8b 5232 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5233 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5234 return handle_interrupt_window(&vmx->vcpu);
5235
72875d8a 5236 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5237 return 1;
5238
60fc3d02 5239 if (!kvm_emulate_instruction(vcpu, 0))
8fff2710 5240 return 0;
1d5a4d9b 5241
add5ff7a 5242 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
8fff2710
SC		 5243 vcpu->arch.exception.pending) {
5244 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5245 vcpu->run->internal.suberror =
5246 KVM_INTERNAL_ERROR_EMULATION;
5247 vcpu->run->internal.ndata = 0;
5248 return 0;
5249 }
ea953ef0 5250
8d76c49e
GN		 5251 if (vcpu->arch.halt_request) {
5252 vcpu->arch.halt_request = 0;
8fff2710 5253 return kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5254 }
5255
8fff2710
SC		 5256 /*
5257 * Note, return 1 and not 0, vcpu_run() is responsible for
5258 * morphing the pending signal into the proper return code.
5259 */
ea953ef0 5260 if (signal_pending(current))
8fff2710
SC		 5261 return 1;
5262
ea953ef0
MG		 5263 if (need_resched())
5264 schedule();
5265 }
5266
8fff2710 5267 return 1;
b4a2d31d
RK		 5268}
5269
5270static void grow_ple_window(struct kvm_vcpu *vcpu)
5271{
5272 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5273 unsigned int old = vmx->ple_window;
b4a2d31d 5274
c8e88717
BM		 5275 vmx->ple_window = __grow_ple_window(old, ple_window,
5276 ple_window_grow,
5277 ple_window_max);
b4a2d31d 5278
4f75bcc3 5279 if (vmx->ple_window != old) {
b4a2d31d 5280 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5281 trace_kvm_ple_window_update(vcpu->vcpu_id,
5282 vmx->ple_window, old);
5283 }
b4a2d31d
RK		 5284}
5285
5286static void shrink_ple_window(struct kvm_vcpu *vcpu)
5287{
5288 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5289 unsigned int old = vmx->ple_window;
b4a2d31d 5290
c8e88717
BM		 5291 vmx->ple_window = __shrink_ple_window(old, ple_window,
5292 ple_window_shrink,
5293 ple_window);
b4a2d31d 5294
4f75bcc3 5295 if (vmx->ple_window != old) {
b4a2d31d 5296 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5297 trace_kvm_ple_window_update(vcpu->vcpu_id,
5298 vmx->ple_window, old);
5299 }
b4a2d31d
RK		 5300}
5301
bf9f6ac8
FW		 5302/*
5303 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5304 */
5305static void wakeup_handler(void)
5306{
5307 struct kvm_vcpu *vcpu;
5308 int cpu = smp_processor_id();
5309
5310 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5311 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5312 blocked_vcpu_list) {
5313 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5314
5315 if (pi_test_on(pi_desc) == 1)
5316 kvm_vcpu_kick(vcpu);
5317 }
5318 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5319}
5320
e01bca2f 5321static void vmx_enable_tdp(void)
f160c7b7
JS		 5322{
5323 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5324 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5325 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5326 0ull, VMX_EPT_EXECUTABLE_MASK,
5327 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5328 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5329
5330 ept_set_mmio_spte_mask();
5331 kvm_enable_tdp();
5332}
5333
4b8d54f9
ZE		 5334/*
5335 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5336 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5337 */
9fb41ba8 5338static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5339{
b31c114b 5340 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5341 grow_ple_window(vcpu);
5342
de63ad4c
LM		 5343 /*
5344 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5345 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5346 * never set PAUSE_EXITING and just set PLE if supported,
5347 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5348 */
5349 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5350 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5351}
5352
87c00572 5353static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5354{
6affcbed 5355 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5356}
5357
87c00572
GS		 5358static int handle_mwait(struct kvm_vcpu *vcpu)
5359{
5360 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5361 return handle_nop(vcpu);
5362}
5363
45ec368c
JM		 5364static int handle_invalid_op(struct kvm_vcpu *vcpu)
5365{
5366 kvm_queue_exception(vcpu, UD_VECTOR);
5367 return 1;
5368}
5369
5f3d45e7
MD		 5370static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5371{
5372 return 1;
5373}
5374
87c00572
GS		 5375static int handle_monitor(struct kvm_vcpu *vcpu)
5376{
5377 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5378 return handle_nop(vcpu);
5379}
5380
55d2375e 5381static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5382{
55d2375e
SC		 5383 u32 vmx_instruction_info;
5384 unsigned long type;
5385 bool pcid_enabled;
5386 gva_t gva;
5387 struct x86_exception e;
5388 unsigned i;
5389 unsigned long roots_to_free = 0;
5390 struct {
5391 u64 pcid;
5392 u64 gla;
5393 } operand;
f9eb4af6 5394
55d2375e 5395 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5396 kvm_queue_exception(vcpu, UD_VECTOR);
5397 return 1;
5398 }
5399
55d2375e
SC		 5400 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5401 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5402
5403 if (type > 3) {
5404 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5405 return 1;
5406 }
5407
55d2375e
SC		 5408 /* According to the Intel instruction reference, the memory operand
5409 * is read even if it isn't needed (e.g., for type==all)
5410 */
3573e22c 5411 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
fdb28619
EK		 5412 vmx_instruction_info, false,
5413 sizeof(operand), &gva))
3573e22c
BD		 5414 return 1;
5415
55d2375e 5416 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5417 kvm_inject_page_fault(vcpu, &e);
5418 return 1;
5419 }
5420
55d2375e
SC		 5421 if (operand.pcid >> 12 != 0) {
5422 kvm_inject_gp(vcpu, 0);
5423 return 1;
abfc52c6 5424 }
e29acc55 5425
55d2375e 5426 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5427
55d2375e
SC		 5428 switch (type) {
5429 case INVPCID_TYPE_INDIV_ADDR:
5430 if ((!pcid_enabled && (operand.pcid != 0)) ||
5431 is_noncanonical_address(operand.gla, vcpu)) {
5432 kvm_inject_gp(vcpu, 0);
5433 return 1;
5434 }
5435 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5436 return kvm_skip_emulated_instruction(vcpu);
61ada748 5437
55d2375e
SC		 5438 case INVPCID_TYPE_SINGLE_CTXT:
5439 if (!pcid_enabled && (operand.pcid != 0)) {
5440 kvm_inject_gp(vcpu, 0);
5441 return 1;
5442 }
e29acc55 5443
55d2375e
SC		 5444 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5445 kvm_mmu_sync_roots(vcpu);
5446 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5447 }
e29acc55 5448
55d2375e
SC		 5449 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5450 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5451 == operand.pcid)
5452 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5453
55d2375e
SC		 5454 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5455 /*
5456 * If neither the current cr3 nor any of the prev_roots use the
5457 * given PCID, then nothing needs to be done here because a
5458 * resync will happen anyway before switching to any other CR3.
5459 */
e29acc55 5460
55d2375e 5461 return kvm_skip_emulated_instruction(vcpu);
61ada748 5462
55d2375e
SC		 5463 case INVPCID_TYPE_ALL_NON_GLOBAL:
5464 /*
5465 * Currently, KVM doesn't mark global entries in the shadow
5466 * page tables, so a non-global flush just degenerates to a
5467 * global flush. If needed, we could optimize this later by
5468 * keeping track of global entries in shadow page tables.
5469 */
e29acc55 5470
55d2375e
SC		 5471 /* fall-through */
5472 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5473 kvm_mmu_unload(vcpu);
5474 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5475
55d2375e
SC		 5476 default:
5477 BUG(); /* We have already checked above that type <= 3 */
5478 }
e29acc55
JM		 5479}
5480
55d2375e 5481static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5482{
55d2375e 5483 unsigned long exit_qualification;
b3897a49 5484
55d2375e 5485 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5486
55d2375e 5487 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5488
5489 /*
55d2375e
SC		 5490 * PML buffer FULL happened while executing iret from NMI,
5491 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5492 */
55d2375e
SC		 5493 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5494 enable_vnmi &&
5495 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5496 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5497 GUEST_INTR_STATE_NMI);
e49fcb8b 5498
55d2375e
SC		 5499 /*
5500 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5501 * here.., and there's no userspace involvement needed for PML.
5502 */
ec378aee
NHE		 5503 return 1;
5504}
5505
55d2375e 5506static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5507{
804939ea
SC		 5508 struct vcpu_vmx *vmx = to_vmx(vcpu);
5509
5510 if (!vmx->req_immediate_exit &&
5511 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
55d2375e 5512 kvm_lapic_expired_hv_timer(vcpu);
804939ea 5513
55d2375e 5514 return 1;
8ca44e88
DM		 5515}
5516
55d2375e
SC		 5517/*
5518 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5519 * are overwritten by nested_vmx_setup() when nested=1.
5520 */
5521static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5522{
55d2375e
SC		 5523 kvm_queue_exception(vcpu, UD_VECTOR);
5524 return 1;
b8bbab92
VK		 5525}
5526
55d2375e 5527static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5528{
55d2375e
SC		 5529 /*
5530 * SGX virtualization is not yet supported. There is no software
5531 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5532 * to prevent the guest from executing ENCLS.
5533 */
5534 kvm_queue_exception(vcpu, UD_VECTOR);
5535 return 1;
e7953d7f
AG		 5536}
5537
ec378aee 5538/*
55d2375e
SC		 5539 * The exit handlers return 1 if the exit was handled fully and guest execution
5540 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5541 * to be done to userspace and return 0.
ec378aee 5542 */
55d2375e 5543static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
95b5a48c 5544 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
55d2375e
SC		 5545 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5546 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5547 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5548 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5549 [EXIT_REASON_CR_ACCESS] = handle_cr,
5550 [EXIT_REASON_DR_ACCESS] = handle_dr,
5551 [EXIT_REASON_CPUID] = handle_cpuid,
5552 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5553 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5554 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5555 [EXIT_REASON_HLT] = handle_halt,
5556 [EXIT_REASON_INVD] = handle_invd,
5557 [EXIT_REASON_INVLPG] = handle_invlpg,
5558 [EXIT_REASON_RDPMC] = handle_rdpmc,
5559 [EXIT_REASON_VMCALL] = handle_vmcall,
5560 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5561 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5562 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5563 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5564 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5565 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5566 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5567 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5568 [EXIT_REASON_VMON] = handle_vmx_instruction,
5569 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5570 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5571 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5572 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5573 [EXIT_REASON_WBINVD] = handle_wbinvd,
5574 [EXIT_REASON_XSETBV] = handle_xsetbv,
5575 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5576 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5577 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5578 [EXIT_REASON_LDTR_TR] = handle_desc,
5579 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5580 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5581 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5582 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5583 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5584 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5585 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5586 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5587 [EXIT_REASON_RDRAND] = handle_invalid_op,
5588 [EXIT_REASON_RDSEED] = handle_invalid_op,
55d2375e
SC		 5589 [EXIT_REASON_PML_FULL] = handle_pml_full,
5590 [EXIT_REASON_INVPCID] = handle_invpcid,
5591 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5592 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5593 [EXIT_REASON_ENCLS] = handle_encls,
5594};
b8bbab92 5595
55d2375e
SC		 5596static const int kvm_vmx_max_exit_handlers =
5597 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5598
55d2375e 5599static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5600{
55d2375e
SC		 5601 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5602 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5603}
5604
55d2375e 5605static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5606{
55d2375e
SC		 5607 if (vmx->pml_pg) {
5608 __free_page(vmx->pml_pg);
5609 vmx->pml_pg = NULL;
b8bbab92 5610 }
27d6c865
NHE		 5611}
5612
55d2375e 5613static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5614{
55d2375e
SC		 5615 struct vcpu_vmx *vmx = to_vmx(vcpu);
5616 u64 *pml_buf;
5617 u16 pml_idx;
cd232ad0 5618
55d2375e 5619 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5620
55d2375e
SC		 5621 /* Do nothing if PML buffer is empty */
5622 if (pml_idx == (PML_ENTITY_NUM - 1))
5623 return;
cd232ad0 5624
55d2375e
SC		 5625 /* PML index always points to next available PML buffer entity */
5626 if (pml_idx >= PML_ENTITY_NUM)
5627 pml_idx = 0;
5628 else
5629 pml_idx++;
945679e3 5630
55d2375e
SC		 5631 pml_buf = page_address(vmx->pml_pg);
5632 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5633 u64 gpa;
945679e3 5634
55d2375e
SC		 5635 gpa = pml_buf[pml_idx];
5636 WARN_ON(gpa & (PAGE_SIZE - 1));
5637 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5638 }
5639
55d2375e
SC		 5640 /* reset PML index */
5641 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5642}
5643
f4160e45 5644/*
55d2375e
SC		 5645 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5646 * Called before reporting dirty_bitmap to userspace.
f4160e45 5647 */
55d2375e 5648static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5649{
55d2375e
SC		 5650 int i;
5651 struct kvm_vcpu *vcpu;
49f705c5 5652 /*
55d2375e
SC		 5653 * We only need to kick vcpu out of guest mode here, as PML buffer
5654 * is flushed at beginning of all VMEXITs, and it's obvious that only
5655 * vcpus running in guest are possible to have unflushed GPAs in PML
5656 * buffer.
49f705c5 5657 */
55d2375e
SC		 5658 kvm_for_each_vcpu(i, vcpu, kvm)
5659 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5660}
5661
55d2375e 5662static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5663{
55d2375e
SC		 5664 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5665 name, vmcs_read16(sel),
5666 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5667 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5668 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5669}
5670
55d2375e 5671static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5672{
55d2375e
SC		 5673 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5674 name, vmcs_read32(limit),
5675 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5676}
5677
69090810 5678void dump_vmcs(void)
63846663 5679{
6f2f8453
PB		 5680 u32 vmentry_ctl, vmexit_ctl;
5681 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5682 unsigned long cr4;
5683 u64 efer;
55d2375e 5684 int i, n;
63846663 5685
6f2f8453
PB		 5686 if (!dump_invalid_vmcs) {
5687 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5688 return;
5689 }
5690
5691 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5692 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5693 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5694 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5695 cr4 = vmcs_readl(GUEST_CR4);
5696 efer = vmcs_read64(GUEST_IA32_EFER);
5697 secondary_exec_control = 0;
55d2375e
SC		 5698 if (cpu_has_secondary_exec_ctrls())
5699 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5700
55d2375e
SC		 5701 pr_err("*** Guest State ***\n");
5702 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5703 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5704 vmcs_readl(CR0_GUEST_HOST_MASK));
5705 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5706 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5707 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5708 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5709 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5710 {
5711 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5712 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5713 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5714 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5715 }
55d2375e
SC		 5716 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5717 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5718 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5719 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5720 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5721 vmcs_readl(GUEST_SYSENTER_ESP),
5722 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5723 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5724 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5725 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5726 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5727 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5728 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5729 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5730 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5731 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5732 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5733 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5734 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5735 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5736 efer, vmcs_read64(GUEST_IA32_PAT));
5737 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5738 vmcs_read64(GUEST_IA32_DEBUGCTL),
5739 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5740 if (cpu_has_load_perf_global_ctrl() &&
5741 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5742 pr_err("PerfGlobCtl = 0x%016llx\n",
5743 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5744 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5745 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5746 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5747 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5748 vmcs_read32(GUEST_ACTIVITY_STATE));
5749 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5750 pr_err("InterruptStatus = %04x\n",
5751 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5752
55d2375e
SC		 5753 pr_err("*** Host State ***\n");
5754 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5755 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5756 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5757 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5758 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5759 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5760 vmcs_read16(HOST_TR_SELECTOR));
5761 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5762 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5763 vmcs_readl(HOST_TR_BASE));
5764 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5765 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5766 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5767 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5768 vmcs_readl(HOST_CR4));
5769 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5770 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5771 vmcs_read32(HOST_IA32_SYSENTER_CS),
5772 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5773 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5774 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5775 vmcs_read64(HOST_IA32_EFER),
5776 vmcs_read64(HOST_IA32_PAT));
5777 if (cpu_has_load_perf_global_ctrl() &&
5778 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5779 pr_err("PerfGlobCtl = 0x%016llx\n",
5780 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5781
55d2375e
SC		 5782 pr_err("*** Control State ***\n");
5783 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5784 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5785 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5786 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5787 vmcs_read32(EXCEPTION_BITMAP),
5788 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5789 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5790 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5791 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5792 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5793 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5794 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5795 vmcs_read32(VM_EXIT_INTR_INFO),
5796 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5797 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5798 pr_err(" reason=%08x qualification=%016lx\n",
5799 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5800 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5801 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5802 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5803 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5804 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5805 pr_err("TSC Multiplier = 0x%016llx\n",
5806 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5807 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5808 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5809 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5810 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5811 }
d6a85c32 5812 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9d609649
PB		 5813 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5814 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
d6a85c32 5815 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
9d609649 5816 }
55d2375e
SC		 5817 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5818 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5819 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5820 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5821 n = vmcs_read32(CR3_TARGET_COUNT);
5822 for (i = 0; i + 1 < n; i += 4)
5823 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5824 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5825 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5826 if (i < n)
5827 pr_err("CR3 target%u=%016lx\n",
5828 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5829 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5830 pr_err("PLE Gap=%08x Window=%08x\n",
5831 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5832 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5833 pr_err("Virtual processor ID = 0x%04x\n",
5834 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5835}
5836
55d2375e
SC		 5837/*
5838 * The guest has exited. See if we can fix it or if we need userspace
5839 * assistance.
5840 */
5841static int vmx_handle_exit(struct kvm_vcpu *vcpu)
ff651cb6 5842{
55d2375e
SC		 5843 struct vcpu_vmx *vmx = to_vmx(vcpu);
5844 u32 exit_reason = vmx->exit_reason;
5845 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5846
55d2375e 5847 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5848
55d2375e
SC		 5849 /*
5850 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5851 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5852 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5853 * mode as if vcpus is in root mode, the PML buffer must has been
5854 * flushed already.
5855 */
5856 if (enable_pml)
5857 vmx_flush_pml_buffer(vcpu);
1dc35dac 5858
55d2375e
SC		 5859 /* If guest state is invalid, start emulating */
5860 if (vmx->emulation_required)
5861 return handle_invalid_guest_state(vcpu);
1dc35dac 5862
55d2375e
SC		 5863 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5864 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5865
55d2375e
SC		 5866 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5867 dump_vmcs();
5868 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5869 vcpu->run->fail_entry.hardware_entry_failure_reason
5870 = exit_reason;
5871 return 0;
9ed38ffa
LP		 5872 }
5873
55d2375e 5874 if (unlikely(vmx->fail)) {
3b20e03a 5875 dump_vmcs();
55d2375e
SC		 5876 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5877 vcpu->run->fail_entry.hardware_entry_failure_reason
5878 = vmcs_read32(VM_INSTRUCTION_ERROR);
5879 return 0;
5880 }
50c28f21 5881
55d2375e
SC		 5882 /*
5883 * Note:
5884 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5885 * delivery event since it indicates guest is accessing MMIO.
5886 * The vm-exit can be triggered again after return to guest that
5887 * will cause infinite loop.
5888 */
5889 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5890 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5891 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5892 exit_reason != EXIT_REASON_PML_FULL &&
5893 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5894 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5895 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5896 vcpu->run->internal.ndata = 3;
5897 vcpu->run->internal.data[0] = vectoring_info;
5898 vcpu->run->internal.data[1] = exit_reason;
5899 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5900 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5901 vcpu->run->internal.ndata++;
5902 vcpu->run->internal.data[3] =
5903 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5904 }
5905 return 0;
5906 }
50c28f21 5907
55d2375e
SC		 5908 if (unlikely(!enable_vnmi &&
5909 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5910 if (vmx_interrupt_allowed(vcpu)) {
5911 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5912 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5913 vcpu->arch.nmi_pending) {
5914 /*
5915 * This CPU don't support us in finding the end of an
5916 * NMI-blocked window if the guest runs with IRQs
5917 * disabled. So we pull the trigger after 1 s of
5918 * futile waiting, but inform the user about this.
5919 */
5920 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5921 "state on VCPU %d after 1 s timeout\n",
5922 __func__, vcpu->vcpu_id);
5923 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5924 }
5925 }
50c28f21 5926
55d2375e
SC		 5927 if (exit_reason < kvm_vmx_max_exit_handlers
5928 && kvm_vmx_exit_handlers[exit_reason])
5929 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5930 else {
5931 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5932 exit_reason);
7396d337
LA		 5933 dump_vmcs();
5934 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5935 vcpu->run->internal.suberror =
5936 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5937 vcpu->run->internal.ndata = 1;
5938 vcpu->run->internal.data[0] = exit_reason;
5939 return 0;
55d2375e 5940 }
9ed38ffa
LP		 5941}
5942
efebf0aa 5943/*
55d2375e
SC		 5944 * Software based L1D cache flush which is used when microcode providing
5945 * the cache control MSR is not loaded.
efebf0aa 5946 *
55d2375e
SC		 5947 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5948 * flush it is required to read in 64 KiB because the replacement algorithm
5949 * is not exactly LRU. This could be sized at runtime via topology
5950 * information but as all relevant affected CPUs have 32KiB L1D cache size
5951 * there is no point in doing so.
efebf0aa 5952 */
55d2375e 5953static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5954{
55d2375e 5955 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5956
5957 /*
55d2375e
SC		 5958 * This code is only executed when the the flush mode is 'cond' or
5959 * 'always'
25a2e4fe 5960 */
55d2375e
SC		 5961 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5962 bool flush_l1d;
25a2e4fe 5963
55d2375e
SC		 5964 /*
5965 * Clear the per-vcpu flush bit, it gets set again
5966 * either from vcpu_run() or from one of the unsafe
5967 * VMEXIT handlers.
5968 */
5969 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5970 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5971
55d2375e
SC		 5972 /*
5973 * Clear the per-cpu flush bit, it gets set again from
5974 * the interrupt handlers.
5975 */
5976 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5977 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 5978
55d2375e
SC		 5979 if (!flush_l1d)
5980 return;
5981 }
09abe320 5982
55d2375e 5983 vcpu->stat.l1d_flush++;
25a2e4fe 5984
55d2375e
SC		 5985 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5986 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5987 return;
5988 }
25a2e4fe 5989
55d2375e
SC		 5990 asm volatile(
5991 /* First ensure the pages are in the TLB */
5992 "xorl %%eax, %%eax\n"
5993 ".Lpopulate_tlb:\n\t"
5994 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5995 "addl $4096, %%eax\n\t"
5996 "cmpl %%eax, %[size]\n\t"
5997 "jne .Lpopulate_tlb\n\t"
5998 "xorl %%eax, %%eax\n\t"
5999 "cpuid\n\t"
6000 /* Now fill the cache */
6001 "xorl %%eax, %%eax\n"
6002 ".Lfill_cache:\n"
6003 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6004 "addl $64, %%eax\n\t"
6005 "cmpl %%eax, %[size]\n\t"
6006 "jne .Lfill_cache\n\t"
6007 "lfence\n"
6008 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6009 [size] "r" (size)
6010 : "eax", "ebx", "ecx", "edx");
09abe320 6011}
25a2e4fe 6012
55d2375e 6013static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 6014{
55d2375e 6015 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
09abe320 6016
55d2375e
SC		 6017 if (is_guest_mode(vcpu) &&
6018 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6019 return;
25a2e4fe 6020
55d2375e
SC		 6021 if (irr == -1 || tpr < irr) {
6022 vmcs_write32(TPR_THRESHOLD, 0);
6023 return;
25a2e4fe 6024 }
55d2375e
SC		 6025
6026 vmcs_write32(TPR_THRESHOLD, irr);
8665c3f9
PB		 6027}
6028
55d2375e 6029void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 6030{
fe7f895d 6031 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6032 u32 sec_exec_control;
8665c3f9 6033
55d2375e
SC		 6034 if (!lapic_in_kernel(vcpu))
6035 return;
9314006d 6036
55d2375e
SC		 6037 if (!flexpriority_enabled &&
6038 !cpu_has_vmx_virtualize_x2apic_mode())
6039 return;
705699a1 6040
55d2375e
SC		 6041 /* Postpone execution until vmcs01 is the current VMCS. */
6042 if (is_guest_mode(vcpu)) {
fe7f895d 6043 vmx->nested.change_vmcs01_virtual_apic_mode = true;
55d2375e 6044 return;
6beb7bd5 6045 }
fe3ef05c 6046
fe7f895d 6047 sec_exec_control = secondary_exec_controls_get(vmx);
55d2375e
SC		 6048 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6049 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 6050
55d2375e
SC		 6051 switch (kvm_get_apic_mode(vcpu)) {
6052 case LAPIC_MODE_INVALID:
6053 WARN_ONCE(true, "Invalid local APIC state");
6054 case LAPIC_MODE_DISABLED:
6055 break;
6056 case LAPIC_MODE_XAPIC:
6057 if (flexpriority_enabled) {
6058 sec_exec_control |=
6059 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6060 vmx_flush_tlb(vcpu, true);
6061 }
6062 break;
6063 case LAPIC_MODE_X2APIC:
6064 if (cpu_has_vmx_virtualize_x2apic_mode())
6065 sec_exec_control |=
6066 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6067 break;
09abe320 6068 }
fe7f895d 6069 secondary_exec_controls_set(vmx, sec_exec_control);
09abe320 6070
55d2375e
SC		 6071 vmx_update_msr_bitmap(vcpu);
6072}
0238ea91 6073
55d2375e
SC		 6074static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6075{
6076 if (!is_guest_mode(vcpu)) {
6077 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6078 vmx_flush_tlb(vcpu, true);
6079 }
6080}
fe3ef05c 6081
55d2375e
SC		 6082static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6083{
6084 u16 status;
6085 u8 old;
32c7acf0 6086
55d2375e
SC		 6087 if (max_isr == -1)
6088 max_isr = 0;
608406e2 6089
55d2375e
SC		 6090 status = vmcs_read16(GUEST_INTR_STATUS);
6091 old = status >> 8;
6092 if (max_isr != old) {
6093 status &= 0xff;
6094 status |= max_isr << 8;
6095 vmcs_write16(GUEST_INTR_STATUS, status);
6096 }
6097}
6beb7bd5 6098
55d2375e
SC		 6099static void vmx_set_rvi(int vector)
6100{
6101 u16 status;
6102 u8 old;
0b665d30 6103
55d2375e
SC		 6104 if (vector == -1)
6105 vector = 0;
fe3ef05c 6106
55d2375e
SC		 6107 status = vmcs_read16(GUEST_INTR_STATUS);
6108 old = (u8)status & 0xff;
6109 if ((u8)vector != old) {
6110 status &= ~0xff;
6111 status |= (u8)vector;
6112 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6113 }
55d2375e 6114}
09abe320 6115
55d2375e
SC		 6116static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6117{
09abe320 6118 /*
55d2375e
SC		 6119 * When running L2, updating RVI is only relevant when
6120 * vmcs12 virtual-interrupt-delivery enabled.
6121 * However, it can be enabled only when L1 also
6122 * intercepts external-interrupts and in that case
6123 * we should not update vmcs02 RVI but instead intercept
6124 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6125 */
55d2375e
SC		 6126 if (!is_guest_mode(vcpu))
6127 vmx_set_rvi(max_irr);
6128}
fe3ef05c 6129
55d2375e
SC		 6130static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6131{
6132 struct vcpu_vmx *vmx = to_vmx(vcpu);
6133 int max_irr;
6134 bool max_irr_updated;
a7c0b07d 6135
55d2375e
SC		 6136 WARN_ON(!vcpu->arch.apicv_active);
6137 if (pi_test_on(&vmx->pi_desc)) {
6138 pi_clear_on(&vmx->pi_desc);
6139 /*
6140 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6141 * But on x86 this is just a compiler barrier anyway.
6142 */
6143 smp_mb__after_atomic();
6144 max_irr_updated =
6145 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6146
6147 /*
55d2375e
SC		 6148 * If we are running L2 and L1 has a new pending interrupt
6149 * which can be injected, we should re-evaluate
6150 * what should be done with this new L1 interrupt.
6151 * If L1 intercepts external-interrupts, we should
6152 * exit from L2 to L1. Otherwise, interrupt should be
6153 * delivered directly to L2.
c4ebd629 6154 */
55d2375e
SC		 6155 if (is_guest_mode(vcpu) && max_irr_updated) {
6156 if (nested_exit_on_intr(vcpu))
6157 kvm_vcpu_exiting_guest_mode(vcpu);
6158 else
6159 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6160 }
55d2375e
SC		 6161 } else {
6162 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6163 }
55d2375e
SC		 6164 vmx_hwapic_irr_update(vcpu, max_irr);
6165 return max_irr;
6166}
a7c0b07d 6167
17e433b5
WL		 6168static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6169{
6170 return pi_test_on(vcpu_to_pi_desc(vcpu));
6171}
6172
55d2375e
SC		 6173static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6174{
6175 if (!kvm_vcpu_apicv_active(vcpu))
6176 return;
25a2e4fe 6177
55d2375e
SC		 6178 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6179 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6180 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6181 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6182}
6183
55d2375e 6184static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6185{
6186 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6187
55d2375e
SC		 6188 pi_clear_on(&vmx->pi_desc);
6189 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6190}
8665c3f9 6191
95b5a48c 6192static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
55d2375e 6193{
beb8d93b 6194 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6195
55d2375e 6196 /* if exit due to PF check for async PF */
beb8d93b 6197 if (is_page_fault(vmx->exit_intr_info))
55d2375e 6198 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 6199
55d2375e 6200 /* Handle machine checks before interrupts are enabled */
beb8d93b 6201 if (is_machine_check(vmx->exit_intr_info))
55d2375e 6202 kvm_machine_check();
fe3ef05c 6203
55d2375e 6204 /* We need to handle NMIs before interrupts are enabled */
beb8d93b 6205 if (is_nmi(vmx->exit_intr_info)) {
55d2375e
SC		 6206 kvm_before_interrupt(&vmx->vcpu);
6207 asm("int $2");
6208 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6209 }
55d2375e 6210}
fe3ef05c 6211
95b5a48c 6212static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
55d2375e 6213{
49def500
SC		 6214 unsigned int vector;
6215 unsigned long entry;
55d2375e 6216#ifdef CONFIG_X86_64
49def500 6217 unsigned long tmp;
55d2375e 6218#endif
49def500
SC		 6219 gate_desc *desc;
6220 u32 intr_info;
fe3ef05c 6221
49def500
SC		 6222 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6223 if (WARN_ONCE(!is_external_intr(intr_info),
6224 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6225 return;
6226
6227 vector = intr_info & INTR_INFO_VECTOR_MASK;
2342080c 6228 desc = (gate_desc *)host_idt_base + vector;
49def500
SC		 6229 entry = gate_offset(desc);
6230
165072b0
SC		 6231 kvm_before_interrupt(vcpu);
6232
49def500 6233 asm volatile(
55d2375e 6234#ifdef CONFIG_X86_64
49def500
SC		 6235 "mov %%" _ASM_SP ", %[sp]\n\t"
6236 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6237 "push $%c[ss]\n\t"
6238 "push %[sp]\n\t"
55d2375e 6239#endif
49def500
SC		 6240 "pushf\n\t"
6241 __ASM_SIZE(push) " $%c[cs]\n\t"
6242 CALL_NOSPEC
6243 :
55d2375e 6244#ifdef CONFIG_X86_64
49def500 6245 [sp]"=&r"(tmp),
55d2375e 6246#endif
49def500
SC		 6247 ASM_CALL_CONSTRAINT
6248 :
6249 THUNK_TARGET(entry),
6250 [ss]"i"(__KERNEL_DS),
6251 [cs]"i"(__KERNEL_CS)
6252 );
165072b0
SC		 6253
6254 kvm_after_interrupt(vcpu);
55d2375e 6255}
95b5a48c
SC		 6256STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6257
6258static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6259{
6260 struct vcpu_vmx *vmx = to_vmx(vcpu);
6261
6262 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6263 handle_external_interrupt_irqoff(vcpu);
6264 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6265 handle_exception_nmi_irqoff(vmx);
6266}
5a6a9748 6267
55d2375e
SC		 6268static bool vmx_has_emulated_msr(int index)
6269{
6270 switch (index) {
6271 case MSR_IA32_SMBASE:
6272 /*
6273 * We cannot do SMM unless we can run the guest in big
6274 * real mode.
6275 */
6276 return enable_unrestricted_guest || emulate_invalid_guest_state;
95c5c7c7
PB		 6277 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6278 return nested;
55d2375e
SC		 6279 case MSR_AMD64_VIRT_SPEC_CTRL:
6280 /* This is AMD only. */
6281 return false;
6282 default:
6283 return true;
3184a995 6284 }
55d2375e 6285}
2bb8cafe 6286
86f5201d
CP		 6287static bool vmx_pt_supported(void)
6288{
6289 return pt_mode == PT_MODE_HOST_GUEST;
6290}
6291
55d2375e
SC		 6292static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6293{
6294 u32 exit_intr_info;
6295 bool unblock_nmi;
6296 u8 vector;
6297 bool idtv_info_valid;
7ca29de2 6298
55d2375e 6299 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6300
55d2375e
SC		 6301 if (enable_vnmi) {
6302 if (vmx->loaded_vmcs->nmi_known_unmasked)
6303 return;
6304 /*
6305 * Can't use vmx->exit_intr_info since we're not sure what
6306 * the exit reason is.
6307 */
6308 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6309 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6310 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6311 /*
6312 * SDM 3: 27.7.1.2 (September 2008)
6313 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6314 * a guest IRET fault.
6315 * SDM 3: 23.2.2 (September 2008)
6316 * Bit 12 is undefined in any of the following cases:
6317 * If the VM exit sets the valid bit in the IDT-vectoring
6318 * information field.
6319 * If the VM exit is due to a double fault.
6320 */
6321 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6322 vector != DF_VECTOR && !idtv_info_valid)
6323 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6324 GUEST_INTR_STATE_NMI);
6325 else
6326 vmx->loaded_vmcs->nmi_known_unmasked =
6327 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6328 & GUEST_INTR_STATE_NMI);
6329 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6330 vmx->loaded_vmcs->vnmi_blocked_time +=
6331 ktime_to_ns(ktime_sub(ktime_get(),
6332 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6333}
6334
55d2375e
SC		 6335static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6336 u32 idt_vectoring_info,
6337 int instr_len_field,
6338 int error_code_field)
0c7f650e 6339{
55d2375e
SC		 6340 u8 vector;
6341 int type;
6342 bool idtv_info_valid;
0c7f650e 6343
55d2375e 6344 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6345
55d2375e
SC		 6346 vcpu->arch.nmi_injected = false;
6347 kvm_clear_exception_queue(vcpu);
6348 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6349
55d2375e
SC		 6350 if (!idtv_info_valid)
6351 return;
c7c2c709 6352
55d2375e 6353 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6354
55d2375e
SC		 6355 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6356 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6357
55d2375e
SC		 6358 switch (type) {
6359 case INTR_TYPE_NMI_INTR:
6360 vcpu->arch.nmi_injected = true;
6361 /*
6362 * SDM 3: 27.7.1.2 (September 2008)
6363 * Clear bit "block by NMI" before VM entry if a NMI
6364 * delivery faulted.
6365 */
6366 vmx_set_nmi_mask(vcpu, false);
6367 break;
6368 case INTR_TYPE_SOFT_EXCEPTION:
6369 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6370 /* fall through */
6371 case INTR_TYPE_HARD_EXCEPTION:
6372 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6373 u32 err = vmcs_read32(error_code_field);
6374 kvm_requeue_exception_e(vcpu, vector, err);
6375 } else
6376 kvm_requeue_exception(vcpu, vector);
6377 break;
6378 case INTR_TYPE_SOFT_INTR:
6379 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6380 /* fall through */
6381 case INTR_TYPE_EXT_INTR:
6382 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6383 break;
6384 default:
6385 break;
0447378a 6386 }
ca0bde28
JM		 6387}
6388
55d2375e 6389static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6390{
55d2375e
SC		 6391 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6392 VM_EXIT_INSTRUCTION_LEN,
6393 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6394}
6395
55d2375e 6396static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6397{
55d2375e
SC		 6398 __vmx_complete_interrupts(vcpu,
6399 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6400 VM_ENTRY_INSTRUCTION_LEN,
6401 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6402
55d2375e 6403 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6404}
6405
55d2375e 6406static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6407{
55d2375e
SC		 6408 int i, nr_msrs;
6409 struct perf_guest_switch_msr *msrs;
7c177938 6410
55d2375e 6411 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6412
55d2375e
SC		 6413 if (!msrs)
6414 return;
f1b026a3 6415
55d2375e
SC		 6416 for (i = 0; i < nr_msrs; i++)
6417 if (msrs[i].host == msrs[i].guest)
6418 clear_atomic_switch_msr(vmx, msrs[i].msr);
6419 else
6420 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6421 msrs[i].host, false);
ca0bde28 6422}
52017608 6423
6e3ba4ab
TX		 6424static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6425{
6426 u32 host_umwait_control;
6427
6428 if (!vmx_has_waitpkg(vmx))
6429 return;
6430
6431 host_umwait_control = get_umwait_control_msr();
6432
6433 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6434 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6435 vmx->msr_ia32_umwait_control,
6436 host_umwait_control, false);
6437 else
6438 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6439}
6440
55d2375e 6441static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6442{
6443 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6444 u64 tscl;
6445 u32 delta_tsc;
52017608 6446
55d2375e 6447 if (vmx->req_immediate_exit) {
804939ea
SC		 6448 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6449 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6450 } else if (vmx->hv_deadline_tsc != -1) {
55d2375e
SC		 6451 tscl = rdtsc();
6452 if (vmx->hv_deadline_tsc > tscl)
6453 /* set_hv_timer ensures the delta fits in 32-bits */
6454 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6455 cpu_preemption_timer_multi);
6456 else
6457 delta_tsc = 0;
858e25c0 6458
804939ea
SC		 6459 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6460 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6461 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6462 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6463 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
7f7f1ba3 6464 }
858e25c0
JM		 6465}
6466
c09b03eb 6467void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6468{
c09b03eb
SC		 6469 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6470 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6471 vmcs_writel(HOST_RSP, host_rsp);
6472 }
5ad6ece8 6473}
5f3d5799 6474
fc2ba5a2 6475bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6476
6477static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6478{
6479 struct vcpu_vmx *vmx = to_vmx(vcpu);
6480 unsigned long cr3, cr4;
6481
6482 /* Record the guest's net vcpu time for enforced NMI injections. */
6483 if (unlikely(!enable_vnmi &&
6484 vmx->loaded_vmcs->soft_vnmi_blocked))
6485 vmx->loaded_vmcs->entry_time = ktime_get();
6486
6487 /* Don't enter VMX if guest state is invalid, let the exit handler
6488 start emulation until we arrive back to a valid state */
6489 if (vmx->emulation_required)
6490 return;
6491
6492 if (vmx->ple_window_dirty) {
6493 vmx->ple_window_dirty = false;
6494 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6495 }
6496
3731905e
SC		 6497 if (vmx->nested.need_vmcs12_to_shadow_sync)
6498 nested_sync_vmcs12_to_shadow(vcpu);
5ad6ece8 6499
cb3c1e2f 6500 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
5ad6ece8 6501 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
cb3c1e2f 6502 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
5ad6ece8
SC		 6503 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6504
6505 cr3 = __get_current_cr3_fast();
6506 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6507 vmcs_writel(HOST_CR3, cr3);
6508 vmx->loaded_vmcs->host_state.cr3 = cr3;
6509 }
6510
6511 cr4 = cr4_read_shadow();
6512 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6513 vmcs_writel(HOST_CR4, cr4);
6514 vmx->loaded_vmcs->host_state.cr4 = cr4;
6515 }
6516
6517 /* When single-stepping over STI and MOV SS, we must clear the
6518 * corresponding interruptibility bits in the guest state. Otherwise
6519 * vmentry fails as it then expects bit 14 (BS) in pending debug
6520 * exceptions being set, but that's not correct for the guest debugging
6521 * case. */
6522 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6523 vmx_set_interrupt_shadow(vcpu, 0);
6524
1811d979
WC		 6525 kvm_load_guest_xcr0(vcpu);
6526
5ad6ece8
SC		 6527 if (static_cpu_has(X86_FEATURE_PKU) &&
6528 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6529 vcpu->arch.pkru != vmx->host_pkru)
6530 __write_pkru(vcpu->arch.pkru);
6531
6532 pt_guest_enter(vmx);
6533
6534 atomic_switch_perf_msrs(vmx);
6e3ba4ab 6535 atomic_switch_umwait_control_msr(vmx);
5ad6ece8 6536
804939ea
SC		 6537 if (enable_preemption_timer)
6538 vmx_update_hv_timer(vcpu);
5ad6ece8 6539
b6c4bc65
WL		 6540 if (lapic_in_kernel(vcpu) &&
6541 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6542 kvm_wait_lapic_expire(vcpu);
6543
5ad6ece8
SC		 6544 /*
6545 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6546 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6547 * is no need to worry about the conditional branch over the wrmsr
6548 * being speculatively taken.
6549 */
6550 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6551
fa4bff16 6552 /* L1D Flush includes CPU buffer clear to mitigate MDS */
c823dd5c
SC		 6553 if (static_branch_unlikely(&vmx_l1d_should_flush))
6554 vmx_l1d_flush(vcpu);
fa4bff16
LT		 6555 else if (static_branch_unlikely(&mds_user_clear))
6556 mds_clear_cpu_buffers();
c823dd5c
SC		 6557
6558 if (vcpu->arch.cr2 != read_cr2())
6559 write_cr2(vcpu->arch.cr2);
6560
fc2ba5a2
SC		 6561 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6562 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6563
6564 vcpu->arch.cr2 = read_cr2();
b6b8a145 6565
55d2375e
SC		 6566 /*
6567 * We do not use IBRS in the kernel. If this vCPU has used the
6568 * SPEC_CTRL MSR it may have left it on; save the value and
6569 * turn it off. This is much more efficient than blindly adding
6570 * it to the atomic save/restore list. Especially as the former
6571 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6572 *
6573 * For non-nested case:
6574 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6575 * save it.
6576 *
6577 * For nested case:
6578 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6579 * save it.
6580 */
6581 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6582 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6583
55d2375e 6584 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6585
55d2375e
SC		 6586 /* All fields are clean at this point */
6587 if (static_branch_unlikely(&enable_evmcs))
6588 current_evmcs->hv_clean_fields |=
6589 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6590
6f6a657c
VK		 6591 if (static_branch_unlikely(&enable_evmcs))
6592 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6593
55d2375e
SC		 6594 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6595 if (vmx->host_debugctlmsr)
6596 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6597
55d2375e
SC		 6598#ifndef CONFIG_X86_64
6599 /*
6600 * The sysexit path does not restore ds/es, so we must set them to
6601 * a reasonable value ourselves.
6602 *
6603 * We can't defer this to vmx_prepare_switch_to_host() since that
6604 * function may be executed in interrupt context, which saves and
6605 * restore segments around it, nullifying its effect.
6606 */
6607 loadsegment(ds, __USER_DS);
6608 loadsegment(es, __USER_DS);
6609#endif
4704d0be 6610
55d2375e
SC		 6611 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6612 | (1 << VCPU_EXREG_RFLAGS)
6613 | (1 << VCPU_EXREG_PDPTR)
6614 | (1 << VCPU_EXREG_SEGMENTS)
6615 | (1 << VCPU_EXREG_CR3));
6616 vcpu->arch.regs_dirty = 0;
7854cbca 6617
2ef444f1
CP		 6618 pt_guest_exit(vmx);
6619
3633cfc3 6620 /*
55d2375e
SC		 6621 * eager fpu is enabled if PKEY is supported and CR4 is switched
6622 * back on host, so it is safe to read guest PKRU from current
6623 * XSAVE.
3633cfc3 6624 */
55d2375e
SC		 6625 if (static_cpu_has(X86_FEATURE_PKU) &&
6626 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
c806e887 6627 vcpu->arch.pkru = rdpkru();
55d2375e
SC		 6628 if (vcpu->arch.pkru != vmx->host_pkru)
6629 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6630 }
6631
1811d979
WC		 6632 kvm_put_guest_xcr0(vcpu);
6633
55d2375e
SC		 6634 vmx->nested.nested_run_pending = 0;
6635 vmx->idt_vectoring_info = 0;
119a9c01 6636
55d2375e 6637 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
beb8d93b
SC		 6638 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6639 kvm_machine_check();
6640
55d2375e
SC		 6641 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6642 return;
608406e2 6643
55d2375e
SC		 6644 vmx->loaded_vmcs->launched = 1;
6645 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6646
55d2375e
SC		 6647 vmx_recover_nmi_blocking(vmx);
6648 vmx_complete_interrupts(vmx);
6649}
2996fca0 6650
55d2375e
SC		 6651static struct kvm *vmx_vm_alloc(void)
6652{
41836839
BG		 6653 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6654 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6655 PAGE_KERNEL);
55d2375e 6656 return &kvm_vmx->kvm;
cf8b84f4
JM		 6657}
6658
55d2375e
SC		 6659static void vmx_vm_free(struct kvm *kvm)
6660{
6f6a657c 6661 kfree(kvm->arch.hyperv.hv_pa_pg);
55d2375e
SC		 6662 vfree(to_kvm_vmx(kvm));
6663}
6664
6665static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6666{
55d2375e 6667 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6668
55d2375e
SC		 6669 if (enable_pml)
6670 vmx_destroy_pml_buffer(vmx);
6671 free_vpid(vmx->vpid);
55d2375e
SC		 6672 nested_vmx_free_vcpu(vcpu);
6673 free_loaded_vmcs(vmx->loaded_vmcs);
6674 kfree(vmx->guest_msrs);
6675 kvm_vcpu_uninit(vcpu);
d9a710e5 6676 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
b666a4b6 6677 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
55d2375e
SC		 6678 kmem_cache_free(kvm_vcpu_cache, vmx);
6679}
4704d0be 6680
55d2375e
SC		 6681static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6682{
6683 int err;
41836839 6684 struct vcpu_vmx *vmx;
55d2375e 6685 unsigned long *msr_bitmap;
4be53410 6686 int i, cpu;
7313c698 6687
12b58f4e
SC		 6688 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6689 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6690
41836839 6691 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6692 if (!vmx)
6693 return ERR_PTR(-ENOMEM);
4704d0be 6694
d9a710e5
WL		 6695 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6696 GFP_KERNEL_ACCOUNT);
6697 if (!vmx->vcpu.arch.user_fpu) {
6698 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6699 err = -ENOMEM;
6700 goto free_partial_vcpu;
6701 }
6702
41836839
BG		 6703 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6704 GFP_KERNEL_ACCOUNT);
b666a4b6
MO		 6705 if (!vmx->vcpu.arch.guest_fpu) {
6706 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6707 err = -ENOMEM;
d9a710e5 6708 goto free_user_fpu;
b666a4b6
MO		 6709 }
6710
55d2375e 6711 vmx->vpid = allocate_vpid();
7cdc2d62 6712
55d2375e
SC		 6713 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6714 if (err)
6715 goto free_vcpu;
5f3d5799 6716
55d2375e 6717 err = -ENOMEM;
5f3d5799
JK		 6718
6719 /*
55d2375e
SC		 6720 * If PML is turned on, failure on enabling PML just results in failure
6721 * of creating the vcpu, therefore we can simplify PML logic (by
6722 * avoiding dealing with cases, such as enabling PML partially on vcpus
6723 * for the guest, etc.
5f3d5799 6724 */
55d2375e 6725 if (enable_pml) {
41836839 6726 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e
SC		 6727 if (!vmx->pml_pg)
6728 goto uninit_vcpu;
6729 }
4704d0be 6730
41836839 6731 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6732 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6733 > PAGE_SIZE);
21feb4eb 6734
55d2375e
SC		 6735 if (!vmx->guest_msrs)
6736 goto free_pml;
4704d0be 6737
4be53410
XL		 6738 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6739 u32 index = vmx_msr_index[i];
6740 u32 data_low, data_high;
6741 int j = vmx->nmsrs;
6742
6743 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6744 continue;
6745 if (wrmsr_safe(index, data_low, data_high) < 0)
6746 continue;
6747 vmx->guest_msrs[j].index = i;
6748 vmx->guest_msrs[j].data = 0;
6749 vmx->guest_msrs[j].mask = -1ull;
6750 ++vmx->nmsrs;
6751 }
6752
55d2375e
SC		 6753 err = alloc_loaded_vmcs(&vmx->vmcs01);
6754 if (err < 0)
6755 goto free_msrs;
cb61de2f 6756
55d2375e 6757 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6758 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6759 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6760 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6761 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6762 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6763 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6764 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
b5170063
WL		 6765 if (kvm_cstate_in_guest(kvm)) {
6766 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6767 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6768 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6769 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6770 }
55d2375e 6771 vmx->msr_bitmap_mode = 0;
4704d0be 6772
55d2375e
SC		 6773 vmx->loaded_vmcs = &vmx->vmcs01;
6774 cpu = get_cpu();
6775 vmx_vcpu_load(&vmx->vcpu, cpu);
6776 vmx->vcpu.cpu = cpu;
6777 vmx_vcpu_setup(vmx);
6778 vmx_vcpu_put(&vmx->vcpu);
6779 put_cpu();
6780 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6781 err = alloc_apic_access_page(kvm);
6782 if (err)
6783 goto free_vmcs;
6784 }
6785
6786 if (enable_ept && !enable_unrestricted_guest) {
6787 err = init_rmode_identity_map(kvm);
6788 if (err)
6789 goto free_vmcs;
6790 }
4704d0be 6791
55d2375e
SC		 6792 if (nested)
6793 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6794 vmx_capability.ept,
6795 kvm_vcpu_apicv_active(&vmx->vcpu));
6796 else
6797 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6798
55d2375e
SC		 6799 vmx->nested.posted_intr_nv = -1;
6800 vmx->nested.current_vmptr = -1ull;
bd18bffc 6801
55d2375e 6802 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
feaf0c7d 6803
6f1e03bc 6804 /*
55d2375e
SC		 6805 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6806 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6807 */
55d2375e
SC		 6808 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6809 vmx->pi_desc.sn = 1;
4704d0be 6810
53963a70
LT		 6811 vmx->ept_pointer = INVALID_PAGE;
6812
55d2375e 6813 return &vmx->vcpu;
4704d0be 6814
55d2375e
SC		 6815free_vmcs:
6816 free_loaded_vmcs(vmx->loaded_vmcs);
6817free_msrs:
6818 kfree(vmx->guest_msrs);
6819free_pml:
6820 vmx_destroy_pml_buffer(vmx);
6821uninit_vcpu:
6822 kvm_vcpu_uninit(&vmx->vcpu);
6823free_vcpu:
6824 free_vpid(vmx->vpid);
b666a4b6 6825 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
d9a710e5
WL		 6826free_user_fpu:
6827 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
b666a4b6 6828free_partial_vcpu:
55d2375e
SC		 6829 kmem_cache_free(kvm_vcpu_cache, vmx);
6830 return ERR_PTR(err);
6831}
36be0b9d 6832
65fd4cb6
TG		 6833#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6834#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
21feb4eb 6835
55d2375e
SC		 6836static int vmx_vm_init(struct kvm *kvm)
6837{
6838 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6839
55d2375e
SC		 6840 if (!ple_gap)
6841 kvm->arch.pause_in_guest = true;
3af18d9c 6842
55d2375e
SC		 6843 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6844 switch (l1tf_mitigation) {
6845 case L1TF_MITIGATION_OFF:
6846 case L1TF_MITIGATION_FLUSH_NOWARN:
6847 /* 'I explicitly don't care' is set */
6848 break;
6849 case L1TF_MITIGATION_FLUSH:
6850 case L1TF_MITIGATION_FLUSH_NOSMT:
6851 case L1TF_MITIGATION_FULL:
6852 /*
6853 * Warn upon starting the first VM in a potentially
6854 * insecure environment.
6855 */
b284909a 6856 if (sched_smt_active())
55d2375e
SC		 6857 pr_warn_once(L1TF_MSG_SMT);
6858 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6859 pr_warn_once(L1TF_MSG_L1D);
6860 break;
6861 case L1TF_MITIGATION_FULL_FORCE:
6862 /* Flush is enforced */
6863 break;
6864 }
6865 }
6866 return 0;
4704d0be
NHE		 6867}
6868
f257d6dc 6869static int __init vmx_check_processor_compat(void)
bd18bffc 6870{
55d2375e
SC		 6871 struct vmcs_config vmcs_conf;
6872 struct vmx_capability vmx_cap;
bd18bffc 6873
55d2375e 6874 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
f257d6dc 6875 return -EIO;
55d2375e
SC		 6876 if (nested)
6877 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6878 enable_apicv);
6879 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6880 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6881 smp_processor_id());
f257d6dc 6882 return -EIO;
bd18bffc 6883 }
f257d6dc 6884 return 0;
bd18bffc
SC		 6885}
6886
55d2375e 6887static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6888{
55d2375e
SC		 6889 u8 cache;
6890 u64 ipat = 0;
bd18bffc 6891
55d2375e
SC		 6892 /* For VT-d and EPT combination
6893 * 1. MMIO: always map as UC
6894 * 2. EPT with VT-d:
6895 * a. VT-d without snooping control feature: can't guarantee the
6896 * result, try to trust guest.
6897 * b. VT-d with snooping control feature: snooping control feature of
6898 * VT-d engine can guarantee the cache correctness. Just set it
6899 * to WB to keep consistent with host. So the same as item 3.
6900 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6901 * consistent with host MTRR
bd18bffc 6902 */
55d2375e
SC		 6903 if (is_mmio) {
6904 cache = MTRR_TYPE_UNCACHABLE;
6905 goto exit;
6906 }
bd18bffc 6907
55d2375e
SC		 6908 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6909 ipat = VMX_EPT_IPAT_BIT;
6910 cache = MTRR_TYPE_WRBACK;
6911 goto exit;
6912 }
bd18bffc 6913
55d2375e
SC		 6914 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6915 ipat = VMX_EPT_IPAT_BIT;
6916 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6917 cache = MTRR_TYPE_WRBACK;
6918 else
6919 cache = MTRR_TYPE_UNCACHABLE;
6920 goto exit;
6921 }
bd18bffc 6922
55d2375e 6923 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6924
55d2375e
SC		 6925exit:
6926 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6927}
bd18bffc 6928
55d2375e
SC		 6929static int vmx_get_lpage_level(void)
6930{
6931 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6932 return PT_DIRECTORY_LEVEL;
6933 else
6934 /* For shadow and EPT supported 1GB page */
6935 return PT_PDPE_LEVEL;
6936}
bd18bffc 6937
fe7f895d 6938static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
55d2375e 6939{
bd18bffc 6940 /*
55d2375e
SC		 6941 * These bits in the secondary execution controls field
6942 * are dynamic, the others are mostly based on the hypervisor
6943 * architecture and the guest's CPUID. Do not touch the
6944 * dynamic bits.
bd18bffc 6945 */
55d2375e
SC		 6946 u32 mask =
6947 SECONDARY_EXEC_SHADOW_VMCS |
6948 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6949 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6950 SECONDARY_EXEC_DESC;
bd18bffc 6951
fe7f895d
SC		 6952 u32 new_ctl = vmx->secondary_exec_control;
6953 u32 cur_ctl = secondary_exec_controls_get(vmx);
bd18bffc 6954
fe7f895d 6955 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6956}
6957
4704d0be 6958/*
55d2375e
SC		 6959 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6960 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6961 */
55d2375e 6962static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6963{
6964 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6965 struct kvm_cpuid_entry2 *entry;
4704d0be 6966
55d2375e
SC		 6967 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6968 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6969
55d2375e
SC		 6970#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6971 if (entry && (entry->_reg & (_cpuid_mask))) \
6972 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6973} while (0)
ff651cb6 6974
55d2375e
SC		 6975 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6976 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6977 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6978 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6979 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6980 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6981 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6982 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6983 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6984 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6985 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6986 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6987 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6988 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6989 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
61ada748 6990
55d2375e
SC		 6991 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6992 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6993 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6994 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6995 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6996 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
cf3215d9 6997
55d2375e
SC		 6998#undef cr4_fixed1_update
6999}
36c3cc42 7000
55d2375e
SC		 7001static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7002{
7003 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 7004
55d2375e
SC		 7005 if (kvm_mpx_supported()) {
7006 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 7007
55d2375e
SC		 7008 if (mpx_enabled) {
7009 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7010 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7011 } else {
7012 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7013 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7014 }
dccbfcf5 7015 }
55d2375e 7016}
4704d0be 7017
6c0f0bba
LK		 7018static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7019{
7020 struct vcpu_vmx *vmx = to_vmx(vcpu);
7021 struct kvm_cpuid_entry2 *best = NULL;
7022 int i;
7023
7024 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7025 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7026 if (!best)
7027 return;
7028 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7029 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7030 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7031 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7032 }
7033
7034 /* Get the number of configurable Address Ranges for filtering */
7035 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7036 PT_CAP_num_address_ranges);
7037
7038 /* Initialize and clear the no dependency bits */
7039 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7040 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7041
7042 /*
7043 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7044 * will inject an #GP
7045 */
7046 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7047 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7048
7049 /*
7050 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7051 * PSBFreq can be set
7052 */
7053 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7054 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7055 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7056
7057 /*
7058 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7059 * MTCFreq can be set
7060 */
7061 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7062 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7063 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7064
7065 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7066 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7067 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7068 RTIT_CTL_PTW_EN);
7069
7070 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7071 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7072 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7073
7074 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7075 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7076 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7077
7078 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7079 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7080 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7081
7082 /* unmask address range configure area */
7083 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 7084 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 7085}
7086
55d2375e
SC		 7087static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7088{
7089 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 7090
55d2375e
SC		 7091 if (cpu_has_secondary_exec_ctrls()) {
7092 vmx_compute_secondary_exec_control(vmx);
fe7f895d 7093 vmcs_set_secondary_exec_control(vmx);
705699a1 7094 }
4704d0be 7095
55d2375e
SC		 7096 if (nested_vmx_allowed(vcpu))
7097 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7098 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7099 else
7100 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7101 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4f350c6d 7102
55d2375e
SC		 7103 if (nested_vmx_allowed(vcpu)) {
7104 nested_vmx_cr_fixed1_bits_update(vcpu);
7105 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 7106 }
6c0f0bba
LK		 7107
7108 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7109 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7110 update_intel_pt_cfg(vcpu);
55d2375e 7111}
09abb5e3 7112
55d2375e
SC		 7113static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7114{
7115 if (func == 1 && nested)
7116 entry->ecx |= bit(X86_FEATURE_VMX);
4704d0be
NHE		 7117}
7118
55d2375e 7119static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 7120{
55d2375e 7121 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 7122}
7123
8a76d7f2
JR		 7124static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7125 struct x86_instruction_info *info,
7126 enum x86_intercept_stage stage)
7127{
fb6d4d34
PB		 7128 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7129 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7130
7131 /*
7132 * RDPID causes #UD if disabled through secondary execution controls.
7133 * Because it is marked as EmulateOnUD, we need to intercept it here.
7134 */
7135 if (info->intercept == x86_intercept_rdtscp &&
7136 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7137 ctxt->exception.vector = UD_VECTOR;
7138 ctxt->exception.error_code_valid = false;
7139 return X86EMUL_PROPAGATE_FAULT;
7140 }
7141
7142 /* TODO: check more intercepts... */
8a76d7f2
JR		 7143 return X86EMUL_CONTINUE;
7144}
7145
64672c95
YJ		 7146#ifdef CONFIG_X86_64
7147/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7148static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7149 u64 divisor, u64 *result)
7150{
7151 u64 low = a << shift, high = a >> (64 - shift);
7152
7153 /* To avoid the overflow on divq */
7154 if (high >= divisor)
7155 return 1;
7156
7157 /* Low hold the result, high hold rem which is discarded */
7158 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7159 "rm" (divisor), "0" (low), "1" (high));
7160 *result = low;
7161
7162 return 0;
7163}
7164
f9927982
SC		 7165static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7166 bool *expired)
64672c95 7167{
386c6ddb 7168 struct vcpu_vmx *vmx;
c5ce8235 7169 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
39497d76 7170 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
386c6ddb 7171
0c5f81da
WL		 7172 if (kvm_mwait_in_guest(vcpu->kvm) ||
7173 kvm_can_post_timer_interrupt(vcpu))
386c6ddb
KA		 7174 return -EOPNOTSUPP;
7175
7176 vmx = to_vmx(vcpu);
7177 tscl = rdtsc();
7178 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7179 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
39497d76
SC		 7180 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7181 ktimer->timer_advance_ns);
c5ce8235
WL		 7182
7183 if (delta_tsc > lapic_timer_advance_cycles)
7184 delta_tsc -= lapic_timer_advance_cycles;
7185 else
7186 delta_tsc = 0;
64672c95
YJ		 7187
7188 /* Convert to host delta tsc if tsc scaling is enabled */
7189 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
0967fa1c 7190 delta_tsc && u64_shl_div_u64(delta_tsc,
64672c95 7191 kvm_tsc_scaling_ratio_frac_bits,
0967fa1c 7192 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
64672c95
YJ		 7193 return -ERANGE;
7194
7195 /*
7196 * If the delta tsc can't fit in the 32 bit after the multi shift,
7197 * we can't use the preemption timer.
7198 * It's possible that it fits on later vmentries, but checking
7199 * on every vmentry is costly so we just use an hrtimer.
7200 */
7201 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7202 return -ERANGE;
7203
7204 vmx->hv_deadline_tsc = tscl + delta_tsc;
f9927982
SC		 7205 *expired = !delta_tsc;
7206 return 0;
64672c95
YJ		 7207}
7208
7209static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7210{
f459a707 7211 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7212}
7213#endif
7214
48d89b92 7215static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7216{
b31c114b 7217 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7218 shrink_ple_window(vcpu);
ae97a3b8
RK		 7219}
7220
843e4330
KH		 7221static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7222 struct kvm_memory_slot *slot)
7223{
7224 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7225 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7226}
7227
7228static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7229 struct kvm_memory_slot *slot)
7230{
7231 kvm_mmu_slot_set_dirty(kvm, slot);
7232}
7233
7234static void vmx_flush_log_dirty(struct kvm *kvm)
7235{
7236 kvm_flush_pml_buffers(kvm);
7237}
7238
c5f983f6
BD		 7239static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7240{
7241 struct vmcs12 *vmcs12;
7242 struct vcpu_vmx *vmx = to_vmx(vcpu);
3d5f6beb 7243 gpa_t gpa, dst;
c5f983f6
BD		 7244
7245 if (is_guest_mode(vcpu)) {
7246 WARN_ON_ONCE(vmx->nested.pml_full);
7247
7248 /*
7249 * Check if PML is enabled for the nested guest.
7250 * Whether eptp bit 6 is set is already checked
7251 * as part of A/D emulation.
7252 */
7253 vmcs12 = get_vmcs12(vcpu);
7254 if (!nested_cpu_has_pml(vmcs12))
7255 return 0;
7256
4769886b 7257 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7258 vmx->nested.pml_full = true;
7259 return 1;
7260 }
7261
7262 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
3d5f6beb 7263 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
c5f983f6 7264
3d5f6beb
KA		 7265 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7266 offset_in_page(dst), sizeof(gpa)))
c5f983f6
BD		 7267 return 0;
7268
3d5f6beb 7269 vmcs12->guest_pml_index--;
c5f983f6
BD		 7270 }
7271
7272 return 0;
7273}
7274
843e4330
KH		 7275static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7276 struct kvm_memory_slot *memslot,
7277 gfn_t offset, unsigned long mask)
7278{
7279 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7280}
7281
cd39e117
PB		 7282static void __pi_post_block(struct kvm_vcpu *vcpu)
7283{
7284 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7285 struct pi_desc old, new;
7286 unsigned int dest;
cd39e117
PB		 7287
7288 do {
7289 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7290 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7291 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7292
7293 dest = cpu_physical_id(vcpu->cpu);
7294
7295 if (x2apic_enabled())
7296 new.ndst = dest;
7297 else
7298 new.ndst = (dest << 8) & 0xFF00;
7299
cd39e117
PB		 7300 /* set 'NV' to 'notification vector' */
7301 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7302 } while (cmpxchg64(&pi_desc->control, old.control,
7303 new.control) != old.control);
cd39e117 7304
8b306e2f
PB		 7305 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7306 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7307 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7308 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7309 vcpu->pre_pcpu = -1;
7310 }
7311}
7312
bf9f6ac8
FW		 7313/*
7314 * This routine does the following things for vCPU which is going
7315 * to be blocked if VT-d PI is enabled.
7316 * - Store the vCPU to the wakeup list, so when interrupts happen
7317 * we can find the right vCPU to wake up.
7318 * - Change the Posted-interrupt descriptor as below:
7319 * 'NDST' <-- vcpu->pre_pcpu
7320 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7321 * - If 'ON' is set during this process, which means at least one
7322 * interrupt is posted for this vCPU, we cannot block it, in
7323 * this case, return 1, otherwise, return 0.
7324 *
7325 */
bc22512b 7326static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7327{
bf9f6ac8
FW		 7328 unsigned int dest;
7329 struct pi_desc old, new;
7330 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7331
7332 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7333 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7334 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7335 return 0;
7336
8b306e2f
PB		 7337 WARN_ON(irqs_disabled());
7338 local_irq_disable();
7339 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7340 vcpu->pre_pcpu = vcpu->cpu;
7341 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7342 list_add_tail(&vcpu->blocked_vcpu_list,
7343 &per_cpu(blocked_vcpu_on_cpu,
7344 vcpu->pre_pcpu));
7345 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7346 }
bf9f6ac8
FW		 7347
7348 do {
7349 old.control = new.control = pi_desc->control;
7350
bf9f6ac8
FW		 7351 WARN((pi_desc->sn == 1),
7352 "Warning: SN field of posted-interrupts "
7353 "is set before blocking\n");
7354
7355 /*
7356 * Since vCPU can be preempted during this process,
7357 * vcpu->cpu could be different with pre_pcpu, we
7358 * need to set pre_pcpu as the destination of wakeup
7359 * notification event, then we can find the right vCPU
7360 * to wakeup in wakeup handler if interrupts happen
7361 * when the vCPU is in blocked state.
7362 */
7363 dest = cpu_physical_id(vcpu->pre_pcpu);
7364
7365 if (x2apic_enabled())
7366 new.ndst = dest;
7367 else
7368 new.ndst = (dest << 8) & 0xFF00;
7369
7370 /* set 'NV' to 'wakeup vector' */
7371 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7372 } while (cmpxchg64(&pi_desc->control, old.control,
7373 new.control) != old.control);
bf9f6ac8 7374
8b306e2f
PB		 7375 /* We should not block the vCPU if an interrupt is posted for it. */
7376 if (pi_test_on(pi_desc) == 1)
7377 __pi_post_block(vcpu);
7378
7379 local_irq_enable();
7380 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7381}
7382
bc22512b
YJ		 7383static int vmx_pre_block(struct kvm_vcpu *vcpu)
7384{
7385 if (pi_pre_block(vcpu))
7386 return 1;
7387
64672c95
YJ		 7388 if (kvm_lapic_hv_timer_in_use(vcpu))
7389 kvm_lapic_switch_to_sw_timer(vcpu);
7390
bc22512b
YJ		 7391 return 0;
7392}
7393
7394static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7395{
8b306e2f 7396 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7397 return;
7398
8b306e2f
PB		 7399 WARN_ON(irqs_disabled());
7400 local_irq_disable();
cd39e117 7401 __pi_post_block(vcpu);
8b306e2f 7402 local_irq_enable();
bf9f6ac8
FW		 7403}
7404
bc22512b
YJ		 7405static void vmx_post_block(struct kvm_vcpu *vcpu)
7406{
64672c95
YJ		 7407 if (kvm_x86_ops->set_hv_timer)
7408 kvm_lapic_switch_to_hv_timer(vcpu);
7409
bc22512b
YJ		 7410 pi_post_block(vcpu);
7411}
7412
efc64404
FW		 7413/*
7414 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7415 *
7416 * @kvm: kvm
7417 * @host_irq: host irq of the interrupt
7418 * @guest_irq: gsi of the interrupt
7419 * @set: set or unset PI
7420 * returns 0 on success, < 0 on failure
7421 */
7422static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7423 uint32_t guest_irq, bool set)
7424{
7425 struct kvm_kernel_irq_routing_entry *e;
7426 struct kvm_irq_routing_table *irq_rt;
7427 struct kvm_lapic_irq irq;
7428 struct kvm_vcpu *vcpu;
7429 struct vcpu_data vcpu_info;
3a8b0677 7430 int idx, ret = 0;
efc64404
FW		 7431
7432 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7433 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7434 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7435 return 0;
7436
7437 idx = srcu_read_lock(&kvm->irq_srcu);
7438 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7439 if (guest_irq >= irq_rt->nr_rt_entries ||
7440 hlist_empty(&irq_rt->map[guest_irq])) {
7441 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7442 guest_irq, irq_rt->nr_rt_entries);
7443 goto out;
7444 }
efc64404
FW		 7445
7446 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7447 if (e->type != KVM_IRQ_ROUTING_MSI)
7448 continue;
7449 /*
7450 * VT-d PI cannot support posting multicast/broadcast
7451 * interrupts to a vCPU, we still use interrupt remapping
7452 * for these kind of interrupts.
7453 *
7454 * For lowest-priority interrupts, we only support
7455 * those with single CPU as the destination, e.g. user
7456 * configures the interrupts via /proc/irq or uses
7457 * irqbalance to make the interrupts single-CPU.
7458 *
7459 * We will support full lowest-priority interrupt later.
fdcf7562
AG		 7460 *
7461 * In addition, we can only inject generic interrupts using
7462 * the PI mechanism, refuse to route others through it.
efc64404
FW		 7463 */
7464
37131313 7465 kvm_set_msi_irq(kvm, e, &irq);
fdcf7562
AG		 7466 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7467 !kvm_irq_is_postable(&irq)) {
23a1c257
FW		 7468 /*
7469 * Make sure the IRTE is in remapped mode if
7470 * we don't handle it in posted mode.
7471 */
7472 ret = irq_set_vcpu_affinity(host_irq, NULL);
7473 if (ret < 0) {
7474 printk(KERN_INFO
7475 "failed to back to remapped mode, irq: %u\n",
7476 host_irq);
7477 goto out;
7478 }
7479
efc64404 7480 continue;
23a1c257 7481 }
efc64404
FW		 7482
7483 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7484 vcpu_info.vector = irq.vector;
7485
2698d82e 7486 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7487 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7488
7489 if (set)
7490 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7491 else
efc64404 7492 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7493
7494 if (ret < 0) {
7495 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7496 __func__);
7497 goto out;
7498 }
7499 }
7500
7501 ret = 0;
7502out:
7503 srcu_read_unlock(&kvm->irq_srcu, idx);
7504 return ret;
7505}
7506
c45dcc71
AR		 7507static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7508{
7509 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7510 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7511 FEATURE_CONTROL_LMCE;
7512 else
7513 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7514 ~FEATURE_CONTROL_LMCE;
7515}
7516
72d7b374
LP		 7517static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7518{
72e9cbdb
LP		 7519 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7520 if (to_vmx(vcpu)->nested.nested_run_pending)
7521 return 0;
72d7b374
LP		 7522 return 1;
7523}
7524
0234bf88
LP		 7525static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7526{
72e9cbdb
LP		 7527 struct vcpu_vmx *vmx = to_vmx(vcpu);
7528
7529 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7530 if (vmx->nested.smm.guest_mode)
7531 nested_vmx_vmexit(vcpu, -1, 0, 0);
7532
7533 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7534 vmx->nested.vmxon = false;
caa057a2 7535 vmx_clear_hlt(vcpu);
0234bf88
LP		 7536 return 0;
7537}
7538
ed19321f 7539static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7540{
72e9cbdb
LP		 7541 struct vcpu_vmx *vmx = to_vmx(vcpu);
7542 int ret;
7543
7544 if (vmx->nested.smm.vmxon) {
7545 vmx->nested.vmxon = true;
7546 vmx->nested.smm.vmxon = false;
7547 }
7548
7549 if (vmx->nested.smm.guest_mode) {
a633e41e 7550 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7551 if (ret)
7552 return ret;
7553
7554 vmx->nested.smm.guest_mode = false;
7555 }
0234bf88
LP		 7556 return 0;
7557}
7558
cc3d967f
LP		 7559static int enable_smi_window(struct kvm_vcpu *vcpu)
7560{
7561 return 0;
7562}
7563
05d5a486
SB		 7564static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7565{
9481b7f1 7566 return false;
05d5a486
SB		 7567}
7568
4b9852f4
LA		 7569static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7570{
7571 return to_vmx(vcpu)->nested.vmxon;
7572}
7573
a3203381
SC		 7574static __init int hardware_setup(void)
7575{
7576 unsigned long host_bndcfgs;
2342080c 7577 struct desc_ptr dt;
a3203381
SC		 7578 int r, i;
7579
7580 rdmsrl_safe(MSR_EFER, &host_efer);
7581
2342080c
SC		 7582 store_idt(&dt);
7583 host_idt_base = dt.address;
7584
a3203381
SC		 7585 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7586 kvm_define_shared_msr(i, vmx_msr_index[i]);
7587
7588 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7589 return -EIO;
7590
7591 if (boot_cpu_has(X86_FEATURE_NX))
7592 kvm_enable_efer_bits(EFER_NX);
7593
7594 if (boot_cpu_has(X86_FEATURE_MPX)) {
7595 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7596 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7597 }
7598
7599 if (boot_cpu_has(X86_FEATURE_XSAVES))
7600 rdmsrl(MSR_IA32_XSS, host_xss);
7601
7602 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7603 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7604 enable_vpid = 0;
7605
7606 if (!cpu_has_vmx_ept() ||
7607 !cpu_has_vmx_ept_4levels() ||
7608 !cpu_has_vmx_ept_mt_wb() ||
7609 !cpu_has_vmx_invept_global())
7610 enable_ept = 0;
7611
7612 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7613 enable_ept_ad_bits = 0;
7614
7615 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7616 enable_unrestricted_guest = 0;
7617
7618 if (!cpu_has_vmx_flexpriority())
7619 flexpriority_enabled = 0;
7620
7621 if (!cpu_has_virtual_nmis())
7622 enable_vnmi = 0;
7623
7624 /*
7625 * set_apic_access_page_addr() is used to reload apic access
7626 * page upon invalidation. No need to do anything if not
7627 * using the APIC_ACCESS_ADDR VMCS field.
7628 */
7629 if (!flexpriority_enabled)
7630 kvm_x86_ops->set_apic_access_page_addr = NULL;
7631
7632 if (!cpu_has_vmx_tpr_shadow())
7633 kvm_x86_ops->update_cr8_intercept = NULL;
7634
7635 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7636 kvm_disable_largepages();
7637
7638#if IS_ENABLED(CONFIG_HYPERV)
7639 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7640 && enable_ept) {
7641 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7642 kvm_x86_ops->tlb_remote_flush_with_range =
7643 hv_remote_flush_tlb_with_range;
7644 }
a3203381
SC		 7645#endif
7646
7647 if (!cpu_has_vmx_ple()) {
7648 ple_gap = 0;
7649 ple_window = 0;
7650 ple_window_grow = 0;
7651 ple_window_max = 0;
7652 ple_window_shrink = 0;
7653 }
7654
7655 if (!cpu_has_vmx_apicv()) {
7656 enable_apicv = 0;
7657 kvm_x86_ops->sync_pir_to_irr = NULL;
7658 }
7659
7660 if (cpu_has_vmx_tsc_scaling()) {
7661 kvm_has_tsc_control = true;
7662 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7663 kvm_tsc_scaling_ratio_frac_bits = 48;
7664 }
7665
7666 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7667
7668 if (enable_ept)
7669 vmx_enable_tdp();
7670 else
7671 kvm_disable_tdp();
7672
a3203381
SC		 7673 /*
7674 * Only enable PML when hardware supports PML feature, and both EPT
7675 * and EPT A/D bit features are enabled -- PML depends on them to work.
7676 */
7677 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7678 enable_pml = 0;
7679
7680 if (!enable_pml) {
7681 kvm_x86_ops->slot_enable_log_dirty = NULL;
7682 kvm_x86_ops->slot_disable_log_dirty = NULL;
7683 kvm_x86_ops->flush_log_dirty = NULL;
7684 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7685 }
7686
7687 if (!cpu_has_vmx_preemption_timer())
804939ea 7688 enable_preemption_timer = false;
a3203381 7689
804939ea
SC		 7690 if (enable_preemption_timer) {
7691 u64 use_timer_freq = 5000ULL * 1000 * 1000;
a3203381
SC		 7692 u64 vmx_msr;
7693
7694 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7695 cpu_preemption_timer_multi =
7696 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
804939ea
SC		 7697
7698 if (tsc_khz)
7699 use_timer_freq = (u64)tsc_khz * 1000;
7700 use_timer_freq >>= cpu_preemption_timer_multi;
7701
7702 /*
7703 * KVM "disables" the preemption timer by setting it to its max
7704 * value. Don't use the timer if it might cause spurious exits
7705 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7706 */
7707 if (use_timer_freq > 0xffffffffu / 10)
7708 enable_preemption_timer = false;
7709 }
7710
7711 if (!enable_preemption_timer) {
a3203381
SC		 7712 kvm_x86_ops->set_hv_timer = NULL;
7713 kvm_x86_ops->cancel_hv_timer = NULL;
804939ea 7714 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
a3203381
SC		 7715 }
7716
a3203381 7717 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7718
7719 kvm_mce_cap_supported |= MCG_LMCE_P;
7720
f99e3daf
CP		 7721 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7722 return -EINVAL;
7723 if (!enable_ept || !cpu_has_vmx_intel_pt())
7724 pt_mode = PT_MODE_SYSTEM;
7725
a3203381 7726 if (nested) {
3e8eaccc
SC		 7727 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7728 vmx_capability.ept, enable_apicv);
7729
e4027cfa 7730 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7731 if (r)
7732 return r;
7733 }
7734
7735 r = alloc_kvm_area();
7736 if (r)
7737 nested_vmx_hardware_unsetup();
7738 return r;
7739}
7740
7741static __exit void hardware_unsetup(void)
7742{
7743 if (nested)
7744 nested_vmx_hardware_unsetup();
7745
7746 free_kvm_area();
7747}
7748
404f6aac 7749static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7750 .cpu_has_kvm_support = cpu_has_kvm_support,
7751 .disabled_by_bios = vmx_disabled_by_bios,
7752 .hardware_setup = hardware_setup,
7753 .hardware_unsetup = hardware_unsetup,
002c7f7c 7754 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7755 .hardware_enable = hardware_enable,
7756 .hardware_disable = hardware_disable,
04547156 7757 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7758 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7759
b31c114b 7760 .vm_init = vmx_vm_init,
434a1e94
SC		 7761 .vm_alloc = vmx_vm_alloc,
7762 .vm_free = vmx_vm_free,
b31c114b 7763
6aa8b732
AK		 7764 .vcpu_create = vmx_create_vcpu,
7765 .vcpu_free = vmx_free_vcpu,
04d2cc77 7766 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7767
6d6095bd 7768 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7769 .vcpu_load = vmx_vcpu_load,
7770 .vcpu_put = vmx_vcpu_put,
7771
a96036b8 7772 .update_bp_intercept = update_exception_bitmap,
801e459a 7773 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7774 .get_msr = vmx_get_msr,
7775 .set_msr = vmx_set_msr,
7776 .get_segment_base = vmx_get_segment_base,
7777 .get_segment = vmx_get_segment,
7778 .set_segment = vmx_set_segment,
2e4d2653 7779 .get_cpl = vmx_get_cpl,
6aa8b732 7780 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7781 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 7782 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7783 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7784 .set_cr3 = vmx_set_cr3,
7785 .set_cr4 = vmx_set_cr4,
6aa8b732 7786 .set_efer = vmx_set_efer,
6aa8b732
AK		 7787 .get_idt = vmx_get_idt,
7788 .set_idt = vmx_set_idt,
7789 .get_gdt = vmx_get_gdt,
7790 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7791 .get_dr6 = vmx_get_dr6,
7792 .set_dr6 = vmx_set_dr6,
020df079 7793 .set_dr7 = vmx_set_dr7,
81908bf4 7794 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7795 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7796 .get_rflags = vmx_get_rflags,
7797 .set_rflags = vmx_set_rflags,
be94f6b7 7798
6aa8b732 7799 .tlb_flush = vmx_flush_tlb,
faff8758 7800 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7801
6aa8b732 7802 .run = vmx_vcpu_run,
6062d012 7803 .handle_exit = vmx_handle_exit,
1957aa63 7804 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7805 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7806 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7807 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7808 .set_irq = vmx_inject_irq,
95ba8273 7809 .set_nmi = vmx_inject_nmi,
298101da 7810 .queue_exception = vmx_queue_exception,
b463a6f7 7811 .cancel_injection = vmx_cancel_injection,
78646121 7812 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7813 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7814 .get_nmi_mask = vmx_get_nmi_mask,
7815 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7816 .enable_nmi_window = enable_nmi_window,
7817 .enable_irq_window = enable_irq_window,
7818 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7819 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7820 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS		 7821 .get_enable_apicv = vmx_get_enable_apicv,
7822 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7823 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7824 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ		 7825 .hwapic_irr_update = vmx_hwapic_irr_update,
7826 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7827 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7828 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7829 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
17e433b5 7830 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
95ba8273 7831
cbc94022 7832 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7833 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7834 .get_tdp_level = get_ept_level,
4b12f0de 7835 .get_mt_mask = vmx_get_mt_mask,
229456fc 7836
586f9607 7837 .get_exit_info = vmx_get_exit_info,
586f9607 7838
17cc3935 7839 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7840
7841 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7842
7843 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7844 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7845
7846 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7847
7848 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7849
e79f245d 7850 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7851 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7852
7853 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7854
7855 .check_intercept = vmx_check_intercept,
95b5a48c 7856 .handle_exit_irqoff = vmx_handle_exit_irqoff,
da8999d3 7857 .mpx_supported = vmx_mpx_supported,
55412b2e 7858 .xsaves_supported = vmx_xsaves_supported,
66336cab 7859 .umip_emulated = vmx_umip_emulated,
86f5201d 7860 .pt_supported = vmx_pt_supported,
b6b8a145 7861
d264ee0c 7862 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7863
7864 .sched_in = vmx_sched_in,
843e4330
KH		 7865
7866 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7867 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7868 .flush_log_dirty = vmx_flush_log_dirty,
7869 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7870 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7871
bf9f6ac8
FW		 7872 .pre_block = vmx_pre_block,
7873 .post_block = vmx_post_block,
7874
25462f7f 7875 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7876
7877 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7878
7879#ifdef CONFIG_X86_64
7880 .set_hv_timer = vmx_set_hv_timer,
7881 .cancel_hv_timer = vmx_cancel_hv_timer,
7882#endif
c45dcc71
AR		 7883
7884 .setup_mce = vmx_setup_mce,
0234bf88 7885
72d7b374 7886 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7887 .pre_enter_smm = vmx_pre_enter_smm,
7888 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7889 .enable_smi_window = enable_smi_window,
57b119da 7890
e4027cfa
SC		 7891 .check_nested_events = NULL,
7892 .get_nested_state = NULL,
7893 .set_nested_state = NULL,
7894 .get_vmcs12_pages = NULL,
7895 .nested_enable_evmcs = NULL,
ea152987 7896 .nested_get_evmcs_version = NULL,
05d5a486 7897 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
4b9852f4 7898 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
6aa8b732
AK		 7899};
7900
72c6d2db 7901static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7902{
7903 if (vmx_l1d_flush_pages) {
7904 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7905 vmx_l1d_flush_pages = NULL;
7906 }
72c6d2db
TG		 7907 /* Restore state so sysfs ignores VMX */
7908 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7909}
7910
a7b9020b
TG		 7911static void vmx_exit(void)
7912{
7913#ifdef CONFIG_KEXEC_CORE
7914 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7915 synchronize_rcu();
7916#endif
7917
7918 kvm_exit();
7919
7920#if IS_ENABLED(CONFIG_HYPERV)
7921 if (static_branch_unlikely(&enable_evmcs)) {
7922 int cpu;
7923 struct hv_vp_assist_page *vp_ap;
7924 /*
7925 * Reset everything to support using non-enlightened VMCS
7926 * access later (e.g. when we reload the module with
7927 * enlightened_vmcs=0)
7928 */
7929 for_each_online_cpu(cpu) {
7930 vp_ap = hv_get_vp_assist_page(cpu);
7931
7932 if (!vp_ap)
7933 continue;
7934
6f6a657c 7935 vp_ap->nested_control.features.directhypercall = 0;
a7b9020b
TG		 7936 vp_ap->current_nested_vmcs = 0;
7937 vp_ap->enlighten_vmentry = 0;
7938 }
7939
7940 static_branch_disable(&enable_evmcs);
7941 }
7942#endif
7943 vmx_cleanup_l1d_flush();
7944}
7945module_exit(vmx_exit);
7946
6aa8b732
AK		 7947static int __init vmx_init(void)
7948{
773e8a04
VK		 7949 int r;
7950
7951#if IS_ENABLED(CONFIG_HYPERV)
7952 /*
7953 * Enlightened VMCS usage should be recommended and the host needs
7954 * to support eVMCS v1 or above. We can also disable eVMCS support
7955 * with module parameter.
7956 */
7957 if (enlightened_vmcs &&
7958 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7959 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7960 KVM_EVMCS_VERSION) {
7961 int cpu;
7962
7963 /* Check that we have assist pages on all online CPUs */
7964 for_each_online_cpu(cpu) {
7965 if (!hv_get_vp_assist_page(cpu)) {
7966 enlightened_vmcs = false;
7967 break;
7968 }
7969 }
7970
7971 if (enlightened_vmcs) {
7972 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7973 static_branch_enable(&enable_evmcs);
7974 }
6f6a657c
VK		 7975
7976 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7977 vmx_x86_ops.enable_direct_tlbflush
7978 = hv_enable_direct_tlbflush;
7979
773e8a04
VK		 7980 } else {
7981 enlightened_vmcs = false;
7982 }
7983#endif
7984
7985 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 7986 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7987 if (r)
34a1cd60 7988 return r;
25c5f225 7989
a7b9020b 7990 /*
7db92e16
TG		 7991 * Must be called after kvm_init() so enable_ept is properly set
7992 * up. Hand the parameter mitigation value in which was stored in
7993 * the pre module init parser. If no parameter was given, it will
7994 * contain 'auto' which will be turned into the default 'cond'
7995 * mitigation mode.
7996 */
19a36d32
WL		 7997 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7998 if (r) {
7999 vmx_exit();
8000 return r;
a47dd5f0 8001 }
25c5f225 8002
2965faa5 8003#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 8004 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8005 crash_vmclear_local_loaded_vmcss);
8006#endif
21ebf53b 8007 vmx_check_vmcs12_offsets();
8f536b76 8008
fdef3ad1 8009 return 0;
6aa8b732 8010}
a7b9020b 8011module_init(vmx_init);
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