]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - arch/x86/kvm/vmx/vmx.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: optimize check for valid PAT value
[mirror_ubuntu-focal-kernel.git] / arch / x86 / kvm / vmx / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
199b118a
SC		 19#include <linux/frame.h>
20#include <linux/highmem.h>
21#include <linux/hrtimer.h>
22#include <linux/kernel.h>
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
c7addb90 25#include <linux/moduleparam.h>
e9bda3b3 26#include <linux/mod_devicetable.h>
199b118a 27#include <linux/mm.h>
199b118a 28#include <linux/sched.h>
b284909a 29#include <linux/sched/smt.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
199b118a 32#include <linux/trace_events.h>
e495606d 33
199b118a 34#include <asm/apic.h>
fd8ca6da 35#include <asm/asm.h>
28b835d6 36#include <asm/cpu.h>
199b118a 37#include <asm/debugreg.h>
3b3be0d1 38#include <asm/desc.h>
952f07ec 39#include <asm/fpu/internal.h>
199b118a 40#include <asm/io.h>
efc64404 41#include <asm/irq_remapping.h>
199b118a
SC		 42#include <asm/kexec.h>
43#include <asm/perf_event.h>
44#include <asm/mce.h>
d6e41f11 45#include <asm/mmu_context.h>
773e8a04 46#include <asm/mshyperv.h>
199b118a
SC		 47#include <asm/spec-ctrl.h>
48#include <asm/virtext.h>
49#include <asm/vmx.h>
6aa8b732 50
3077c191 51#include "capabilities.h"
199b118a 52#include "cpuid.h"
4cebd747 53#include "evmcs.h"
199b118a
SC		 54#include "irq.h"
55#include "kvm_cache_regs.h"
56#include "lapic.h"
57#include "mmu.h"
55d2375e 58#include "nested.h"
89b0c9f5 59#include "ops.h"
25462f7f 60#include "pmu.h"
199b118a 61#include "trace.h"
cb1d474b 62#include "vmcs.h"
609363cf 63#include "vmcs12.h"
89b0c9f5 64#include "vmx.h"
199b118a 65#include "x86.h"
229456fc 66
6aa8b732
AK		 67MODULE_AUTHOR("Qumranet");
68MODULE_LICENSE("GPL");
69
e9bda3b3
JT		 70static const struct x86_cpu_id vmx_cpu_id[] = {
71 X86_FEATURE_MATCH(X86_FEATURE_VMX),
72 {}
73};
74MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
75
2c4fd91d 76bool __read_mostly enable_vpid = 1;
736caefe 77module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 78
d02fcf50
PB		 79static bool __read_mostly enable_vnmi = 1;
80module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
81
2c4fd91d 82bool __read_mostly flexpriority_enabled = 1;
736caefe 83module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 84
2c4fd91d 85bool __read_mostly enable_ept = 1;
736caefe 86module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 87
2c4fd91d 88bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 89module_param_named(unrestricted_guest,
90 enable_unrestricted_guest, bool, S_IRUGO);
91
2c4fd91d 92bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 93module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
94
a27685c3 95static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 96module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 97
476bc001 98static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 99module_param(fasteoi, bool, S_IRUGO);
100
5a71785d 101static bool __read_mostly enable_apicv = 1;
01e439be 102module_param(enable_apicv, bool, S_IRUGO);
83d4c286 103
801d3424
NHE		 104/*
105 * If nested=1, nested virtualization is supported, i.e., guests may use
106 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
107 * use VMX instructions.
108 */
1e58e5e5 109static bool __read_mostly nested = 1;
801d3424
NHE		 110module_param(nested, bool, S_IRUGO);
111
20300099
WL		 112static u64 __read_mostly host_xss;
113
2c4fd91d 114bool __read_mostly enable_pml = 1;
843e4330
KH		 115module_param_named(pml, enable_pml, bool, S_IRUGO);
116
904e14fb
PB		 117#define MSR_BITMAP_MODE_X2APIC 1
118#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 119
64903d61
HZ		 120#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
121
64672c95
YJ		 122/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123static int __read_mostly cpu_preemption_timer_multi;
124static bool __read_mostly enable_preemption_timer = 1;
125#ifdef CONFIG_X86_64
126module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127#endif
128
3de6347b 129#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 130#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131#define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 134#define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 137
5dc1f044 138#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 139#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
141
78ac8b47
AK		 142#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
143
bf8c55d8
CP		 144#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
148
149#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151
4b8d54f9
ZE		 152/*
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 156 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
162 */
c8e88717 163static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 164module_param(ple_gap, uint, 0444);
b4a2d31d 165
7fbc85a5
BM		 166static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167module_param(ple_window, uint, 0444);
4b8d54f9 168
b4a2d31d 169/* Default doubles per-vcpu window every exit. */
c8e88717 170static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 171module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 172
173/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 174static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 175module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 176
177/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 178static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, uint, 0444);
b4a2d31d 180
f99e3daf
CP		 181/* Default is SYSTEM mode, 1 for host-guest mode */
182int __read_mostly pt_mode = PT_MODE_SYSTEM;
183module_param(pt_mode, int, S_IRUGO);
184
a399477e 185static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 186static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 187static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 188
7db92e16
TG		 189/* Storage for pre module init parameter parsing */
190static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 191
192static const struct {
193 const char *option;
0027ff2a 194 bool for_parse;
a399477e 195} vmentry_l1d_param[] = {
0027ff2a
PB		 196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 202};
203
7db92e16
TG		 204#define L1D_CACHE_ORDER 4
205static void *vmx_l1d_flush_pages;
206
207static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 208{
7db92e16 209 struct page *page;
288d152c 210 unsigned int i;
a399477e 211
7db92e16
TG		 212 if (!enable_ept) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
214 return 0;
a399477e
KRW		 215 }
216
d806afa4
YW		 217 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
218 u64 msr;
219
220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
221 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
222 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
223 return 0;
224 }
225 }
8e0b2b91 226
d90a7a0e
JK		 227 /* If set to auto use the default l1tf mitigation method */
228 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
229 switch (l1tf_mitigation) {
230 case L1TF_MITIGATION_OFF:
231 l1tf = VMENTER_L1D_FLUSH_NEVER;
232 break;
233 case L1TF_MITIGATION_FLUSH_NOWARN:
234 case L1TF_MITIGATION_FLUSH:
235 case L1TF_MITIGATION_FLUSH_NOSMT:
236 l1tf = VMENTER_L1D_FLUSH_COND;
237 break;
238 case L1TF_MITIGATION_FULL:
239 case L1TF_MITIGATION_FULL_FORCE:
240 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
241 break;
242 }
243 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
244 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
245 }
246
7db92e16
TG		 247 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
248 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 249 /*
250 * This allocation for vmx_l1d_flush_pages is not tied to a VM
251 * lifetime and so should not be charged to a memcg.
252 */
7db92e16
TG		 253 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
254 if (!page)
255 return -ENOMEM;
256 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 257
258 /*
259 * Initialize each page with a different pattern in
260 * order to protect against KSM in the nested
261 * virtualization case.
262 */
263 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
264 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
265 PAGE_SIZE);
266 }
7db92e16
TG		 267 }
268
269 l1tf_vmx_mitigation = l1tf;
270
895ae47f
TG		 271 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
272 static_branch_enable(&vmx_l1d_should_flush);
273 else
274 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 275
427362a1
NS		 276 if (l1tf == VMENTER_L1D_FLUSH_COND)
277 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 278 else
427362a1 279 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 280 return 0;
281}
282
283static int vmentry_l1d_flush_parse(const char *s)
284{
285 unsigned int i;
286
287 if (s) {
288 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 289 if (vmentry_l1d_param[i].for_parse &&
290 sysfs_streq(s, vmentry_l1d_param[i].option))
291 return i;
7db92e16
TG		 292 }
293 }
a399477e
KRW		 294 return -EINVAL;
295}
296
7db92e16
TG		 297static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
298{
dd4bfa73 299 int l1tf, ret;
7db92e16 300
7db92e16
TG		 301 l1tf = vmentry_l1d_flush_parse(s);
302 if (l1tf < 0)
303 return l1tf;
304
0027ff2a
PB		 305 if (!boot_cpu_has(X86_BUG_L1TF))
306 return 0;
307
7db92e16
TG		 308 /*
309 * Has vmx_init() run already? If not then this is the pre init
310 * parameter parsing. In that case just store the value and let
311 * vmx_init() do the proper setup after enable_ept has been
312 * established.
313 */
314 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
315 vmentry_l1d_flush_param = l1tf;
316 return 0;
317 }
318
dd4bfa73
TG		 319 mutex_lock(&vmx_l1d_flush_mutex);
320 ret = vmx_setup_l1d_flush(l1tf);
321 mutex_unlock(&vmx_l1d_flush_mutex);
322 return ret;
7db92e16
TG		 323}
324
a399477e
KRW		 325static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
326{
0027ff2a
PB		 327 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
328 return sprintf(s, "???\n");
329
7db92e16 330 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 331}
332
333static const struct kernel_param_ops vmentry_l1d_flush_ops = {
334 .set = vmentry_l1d_flush_set,
335 .get = vmentry_l1d_flush_get,
336};
895ae47f 337module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 338
d99e4152
GN		 339static bool guest_state_valid(struct kvm_vcpu *vcpu);
340static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 341static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 342 u32 msr, int type);
75880a01 343
453eafbe
SC		 344void vmx_vmexit(void);
345
6aa8b732 346static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 347DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 348/*
349 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
350 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
351 */
352static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 353
bf9f6ac8
FW		 354/*
355 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
356 * can find which vCPU should be waken up.
357 */
358static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
359static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
360
2384d2b3
SY		 361static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
362static DEFINE_SPINLOCK(vmx_vpid_lock);
363
3077c191
SC		 364struct vmcs_config vmcs_config;
365struct vmx_capability vmx_capability;
d56f546d 366
6aa8b732
AK		 367#define VMX_SEGMENT_FIELD(seg) \
368 [VCPU_SREG_##seg] = { \
369 .selector = GUEST_##seg##_SELECTOR, \
370 .base = GUEST_##seg##_BASE, \
371 .limit = GUEST_##seg##_LIMIT, \
372 .ar_bytes = GUEST_##seg##_AR_BYTES, \
373 }
374
772e0318 375static const struct kvm_vmx_segment_field {
6aa8b732
AK		 376 unsigned selector;
377 unsigned base;
378 unsigned limit;
379 unsigned ar_bytes;
380} kvm_vmx_segment_fields[] = {
381 VMX_SEGMENT_FIELD(CS),
382 VMX_SEGMENT_FIELD(DS),
383 VMX_SEGMENT_FIELD(ES),
384 VMX_SEGMENT_FIELD(FS),
385 VMX_SEGMENT_FIELD(GS),
386 VMX_SEGMENT_FIELD(SS),
387 VMX_SEGMENT_FIELD(TR),
388 VMX_SEGMENT_FIELD(LDTR),
389};
390
cf3646eb 391u64 host_efer;
26bb0981 392
4d56c8a7 393/*
898a811f
JM		 394 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
395 * will emulate SYSCALL in legacy mode if the vendor string in guest
396 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
397 * support this emulation, IA32_STAR must always be included in
398 * vmx_msr_index[], even in i386 builds.
4d56c8a7 399 */
cf3646eb 400const u32 vmx_msr_index[] = {
05b3e0c2 401#ifdef CONFIG_X86_64
44ea2b17 402 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 403#endif
8c06585d 404 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 405};
6aa8b732 406
773e8a04
VK		 407#if IS_ENABLED(CONFIG_HYPERV)
408static bool __read_mostly enlightened_vmcs = true;
409module_param(enlightened_vmcs, bool, 0444);
410
877ad952
TL		 411/* check_ept_pointer() should be under protection of ept_pointer_lock. */
412static void check_ept_pointer_match(struct kvm *kvm)
413{
414 struct kvm_vcpu *vcpu;
415 u64 tmp_eptp = INVALID_PAGE;
416 int i;
417
418 kvm_for_each_vcpu(i, vcpu, kvm) {
419 if (!VALID_PAGE(tmp_eptp)) {
420 tmp_eptp = to_vmx(vcpu)->ept_pointer;
421 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
422 to_kvm_vmx(kvm)->ept_pointers_match
423 = EPT_POINTERS_MISMATCH;
424 return;
425 }
426 }
427
428 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
429}
430
8997f657 431static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 432 void *data)
433{
434 struct kvm_tlb_range *range = data;
435
436 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
437 range->pages);
438}
439
440static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
441 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
442{
443 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
444
445 /*
446 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
447 * of the base of EPT PML4 table, strip off EPT configuration
448 * information.
449 */
450 if (range)
451 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
452 kvm_fill_hv_flush_list_func, (void *)range);
453 else
454 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
455}
456
457static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
458 struct kvm_tlb_range *range)
877ad952 459{
a5c214da 460 struct kvm_vcpu *vcpu;
b7c1c226 461 int ret = 0, i;
877ad952
TL		 462
463 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
464
465 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
466 check_ept_pointer_match(kvm);
467
468 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 469 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 470 /* If ept_pointer is invalid pointer, bypass flush request. */
471 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
472 ret |= __hv_remote_flush_tlb_with_range(
473 kvm, vcpu, range);
53963a70 474 }
a5c214da 475 } else {
1f3a3e46
LT		 476 ret = __hv_remote_flush_tlb_with_range(kvm,
477 kvm_get_vcpu(kvm, 0), range);
877ad952 478 }
877ad952 479
877ad952
TL		 480 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
481 return ret;
482}
1f3a3e46
LT		 483static int hv_remote_flush_tlb(struct kvm *kvm)
484{
485 return hv_remote_flush_tlb_with_range(kvm, NULL);
486}
487
773e8a04
VK		 488#endif /* IS_ENABLED(CONFIG_HYPERV) */
489
64672c95
YJ		 490/*
491 * Comment's format: document - errata name - stepping - processor name.
492 * Refer from
493 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
494 */
495static u32 vmx_preemption_cpu_tfms[] = {
496/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
4970x000206E6,
498/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
499/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
500/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5010x00020652,
502/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5030x00020655,
504/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
505/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
506/*
507 * 320767.pdf - AAP86 - B1 -
508 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
509 */
5100x000106E5,
511/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5120x000106A0,
513/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5140x000106A1,
515/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5160x000106A4,
517 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
518 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
519 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5200x000106A5,
3d82c565
WH		 521 /* Xeon E3-1220 V2 */
5220x000306A8,
64672c95
YJ		 523};
524
525static inline bool cpu_has_broken_vmx_preemption_timer(void)
526{
527 u32 eax = cpuid_eax(0x00000001), i;
528
529 /* Clear the reserved bits */
530 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 531 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 532 if (eax == vmx_preemption_cpu_tfms[i])
533 return true;
534
535 return false;
536}
537
35754c98 538static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 539{
35754c98 540 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 541}
542
04547156
SY		 543static inline bool report_flexpriority(void)
544{
545 return flexpriority_enabled;
546}
547
97b7ead3 548static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 549{
550 int i;
551
a2fa3e9f 552 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 553 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 554 return i;
555 return -1;
556}
557
97b7ead3 558struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 559{
560 int i;
561
8b9cf98c 562 i = __find_msr_index(vmx, msr);
a75beee6 563 if (i >= 0)
a2fa3e9f 564 return &vmx->guest_msrs[i];
8b6d44c7 565 return NULL;
7725f0ba
AK		 566}
567
7c97fcb3
SC		 568void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
569{
570 vmcs_clear(loaded_vmcs->vmcs);
571 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
572 vmcs_clear(loaded_vmcs->shadow_vmcs);
573 loaded_vmcs->cpu = -1;
574 loaded_vmcs->launched = 0;
575}
576
2965faa5 577#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 578/*
579 * This bitmap is used to indicate whether the vmclear
580 * operation is enabled on all cpus. All disabled by
581 * default.
582 */
583static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
584
585static inline void crash_enable_local_vmclear(int cpu)
586{
587 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
588}
589
590static inline void crash_disable_local_vmclear(int cpu)
591{
592 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
593}
594
595static inline int crash_local_vmclear_enabled(int cpu)
596{
597 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
598}
599
600static void crash_vmclear_local_loaded_vmcss(void)
601{
602 int cpu = raw_smp_processor_id();
603 struct loaded_vmcs *v;
604
605 if (!crash_local_vmclear_enabled(cpu))
606 return;
607
608 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
609 loaded_vmcss_on_cpu_link)
610 vmcs_clear(v->vmcs);
611}
612#else
613static inline void crash_enable_local_vmclear(int cpu) { }
614static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 615#endif /* CONFIG_KEXEC_CORE */
8f536b76 616
d462b819 617static void __loaded_vmcs_clear(void *arg)
6aa8b732 618{
d462b819 619 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 620 int cpu = raw_smp_processor_id();
6aa8b732 621
d462b819
NHE		 622 if (loaded_vmcs->cpu != cpu)
623 return; /* vcpu migration can race with cpu offline */
624 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 625 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 626 crash_disable_local_vmclear(cpu);
d462b819 627 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 628
629 /*
630 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
631 * is before setting loaded_vmcs->vcpu to -1 which is done in
632 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
633 * then adds the vmcs into percpu list before it is deleted.
634 */
635 smp_wmb();
636
d462b819 637 loaded_vmcs_init(loaded_vmcs);
8f536b76 638 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 639}
640
89b0c9f5 641void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 642{
e6c7d321
XG		 643 int cpu = loaded_vmcs->cpu;
644
645 if (cpu != -1)
646 smp_call_function_single(cpu,
647 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 648}
649
2fb92db1
AK		 650static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
651 unsigned field)
652{
653 bool ret;
654 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
655
656 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
657 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
658 vmx->segment_cache.bitmask = 0;
659 }
660 ret = vmx->segment_cache.bitmask & mask;
661 vmx->segment_cache.bitmask |= mask;
662 return ret;
663}
664
665static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
666{
667 u16 *p = &vmx->segment_cache.seg[seg].selector;
668
669 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
670 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
671 return *p;
672}
673
674static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
675{
676 ulong *p = &vmx->segment_cache.seg[seg].base;
677
678 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
679 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
680 return *p;
681}
682
683static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
684{
685 u32 *p = &vmx->segment_cache.seg[seg].limit;
686
687 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
688 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
689 return *p;
690}
691
692static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
693{
694 u32 *p = &vmx->segment_cache.seg[seg].ar;
695
696 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
697 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
698 return *p;
699}
700
97b7ead3 701void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 702{
703 u32 eb;
704
fd7373cc 705 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 706 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 707 /*
708 * Guest access to VMware backdoor ports could legitimately
709 * trigger #GP because of TSS I/O permission bitmap.
710 * We intercept those #GP and allow access to them anyway
711 * as VMware does.
712 */
713 if (enable_vmware_backdoor)
714 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 715 if ((vcpu->guest_debug &
716 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
717 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
718 eb |= 1u << BP_VECTOR;
7ffd92c5 719 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 720 eb = ~0;
089d034e 721 if (enable_ept)
1439442c 722 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 723
724 /* When we are running a nested L2 guest and L1 specified for it a
725 * certain exception bitmap, we must trap the same exceptions and pass
726 * them to L1. When running L2, we will only handle the exceptions
727 * specified above if L1 did not want them.
728 */
729 if (is_guest_mode(vcpu))
730 eb |= get_vmcs12(vcpu)->exception_bitmap;
731
abd3f2d6
AK		 732 vmcs_write32(EXCEPTION_BITMAP, eb);
733}
734
d28b387f
KA		 735/*
736 * Check if MSR is intercepted for currently loaded MSR bitmap.
737 */
738static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
739{
740 unsigned long *msr_bitmap;
741 int f = sizeof(unsigned long);
742
743 if (!cpu_has_vmx_msr_bitmap())
744 return true;
745
746 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
747
748 if (msr <= 0x1fff) {
749 return !!test_bit(msr, msr_bitmap + 0x800 / f);
750 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
751 msr &= 0x1fff;
752 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
753 }
754
755 return true;
756}
757
2961e876
GN		 758static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
759 unsigned long entry, unsigned long exit)
8bf00a52 760{
2961e876
GN		 761 vm_entry_controls_clearbit(vmx, entry);
762 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 763}
764
ca83b4a7
KRW		 765static int find_msr(struct vmx_msrs *m, unsigned int msr)
766{
767 unsigned int i;
768
769 for (i = 0; i < m->nr; ++i) {
770 if (m->val[i].index == msr)
771 return i;
772 }
773 return -ENOENT;
774}
775
61d2ef2c
AK		 776static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
777{
ca83b4a7 778 int i;
61d2ef2c
AK		 779 struct msr_autoload *m = &vmx->msr_autoload;
780
8bf00a52
GN		 781 switch (msr) {
782 case MSR_EFER:
c73da3fc 783 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 784 clear_atomic_switch_msr_special(vmx,
785 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 786 VM_EXIT_LOAD_IA32_EFER);
787 return;
788 }
789 break;
790 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 791 if (cpu_has_load_perf_global_ctrl()) {
2961e876 792 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 793 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
794 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
795 return;
796 }
797 break;
110312c8 798 }
ca83b4a7
KRW		 799 i = find_msr(&m->guest, msr);
800 if (i < 0)
31907093 801 goto skip_guest;
33966dd6 802 --m->guest.nr;
33966dd6 803 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 804 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 805
31907093
KRW		 806skip_guest:
807 i = find_msr(&m->host, msr);
808 if (i < 0)
61d2ef2c 809 return;
31907093
KRW		 810
811 --m->host.nr;
812 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 813 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 814}
815
2961e876
GN		 816static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
817 unsigned long entry, unsigned long exit,
818 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
819 u64 guest_val, u64 host_val)
8bf00a52
GN		 820{
821 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 822 if (host_val_vmcs != HOST_IA32_EFER)
823 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 824 vm_entry_controls_setbit(vmx, entry);
825 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 826}
827
61d2ef2c 828static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 829 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 830{
989e3992 831 int i, j = 0;
61d2ef2c
AK		 832 struct msr_autoload *m = &vmx->msr_autoload;
833
8bf00a52
GN		 834 switch (msr) {
835 case MSR_EFER:
c73da3fc 836 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 837 add_atomic_switch_msr_special(vmx,
838 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 839 VM_EXIT_LOAD_IA32_EFER,
840 GUEST_IA32_EFER,
841 HOST_IA32_EFER,
842 guest_val, host_val);
843 return;
844 }
845 break;
846 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 847 if (cpu_has_load_perf_global_ctrl()) {
2961e876 848 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 849 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
850 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
851 GUEST_IA32_PERF_GLOBAL_CTRL,
852 HOST_IA32_PERF_GLOBAL_CTRL,
853 guest_val, host_val);
854 return;
855 }
856 break;
7099e2e1
RK		 857 case MSR_IA32_PEBS_ENABLE:
858 /* PEBS needs a quiescent period after being disabled (to write
859 * a record). Disabling PEBS through VMX MSR swapping doesn't
860 * provide that period, so a CPU could write host's record into
861 * guest's memory.
862 */
863 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 864 }
865
ca83b4a7 866 i = find_msr(&m->guest, msr);
989e3992
KRW		 867 if (!entry_only)
868 j = find_msr(&m->host, msr);
61d2ef2c 869
98ae70cc
XL		 870 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
871 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
60266204 872 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 873 "Can't add msr %x\n", msr);
874 return;
61d2ef2c 875 }
31907093 876 if (i < 0) {
ca83b4a7 877 i = m->guest.nr++;
33966dd6 878 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 879 }
989e3992
KRW		 880 m->guest.val[i].index = msr;
881 m->guest.val[i].value = guest_val;
882
883 if (entry_only)
884 return;
61d2ef2c 885
31907093
KRW		 886 if (j < 0) {
887 j = m->host.nr++;
33966dd6 888 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 889 }
31907093
KRW		 890 m->host.val[j].index = msr;
891 m->host.val[j].value = host_val;
61d2ef2c
AK		 892}
893
92c0d900 894static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 895{
844a5fe2
PB		 896 u64 guest_efer = vmx->vcpu.arch.efer;
897 u64 ignore_bits = 0;
898
899 if (!enable_ept) {
900 /*
901 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
902 * host CPUID is more efficient than testing guest CPUID
903 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
904 */
905 if (boot_cpu_has(X86_FEATURE_SMEP))
906 guest_efer |= EFER_NX;
907 else if (!(guest_efer & EFER_NX))
908 ignore_bits |= EFER_NX;
909 }
3a34a881 910
51c6cf66 911 /*
844a5fe2 912 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 913 */
844a5fe2 914 ignore_bits |= EFER_SCE;
51c6cf66
AK		 915#ifdef CONFIG_X86_64
916 ignore_bits |= EFER_LMA | EFER_LME;
917 /* SCE is meaningful only in long mode on Intel */
918 if (guest_efer & EFER_LMA)
919 ignore_bits &= ~(u64)EFER_SCE;
920#endif
84ad33ef 921
f6577a5f
AL		 922 /*
923 * On EPT, we can't emulate NX, so we must switch EFER atomically.
924 * On CPUs that support "load IA32_EFER", always switch EFER
925 * atomically, since it's faster than switching it manually.
926 */
c73da3fc 927 if (cpu_has_load_ia32_efer() ||
f6577a5f 928 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 929 if (!(guest_efer & EFER_LMA))
930 guest_efer &= ~EFER_LME;
54b98bff
AL		 931 if (guest_efer != host_efer)
932 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 933 guest_efer, host_efer, false);
02343cf2
SC		 934 else
935 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 936 return false;
844a5fe2 937 } else {
02343cf2
SC		 938 clear_atomic_switch_msr(vmx, MSR_EFER);
939
844a5fe2
PB		 940 guest_efer &= ~ignore_bits;
941 guest_efer |= host_efer & ignore_bits;
942
943 vmx->guest_msrs[efer_offset].data = guest_efer;
944 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 945
844a5fe2
PB		 946 return true;
947 }
51c6cf66
AK		 948}
949
e28baead
AL		 950#ifdef CONFIG_X86_32
951/*
952 * On 32-bit kernels, VM exits still load the FS and GS bases from the
953 * VMCS rather than the segment table. KVM uses this helper to figure
954 * out the current bases to poke them into the VMCS before entry.
955 */
2d49ec72
GN		 956static unsigned long segment_base(u16 selector)
957{
8c2e41f7 958 struct desc_struct *table;
2d49ec72
GN		 959 unsigned long v;
960
8c2e41f7 961 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 962 return 0;
963
45fc8757 964 table = get_current_gdt_ro();
2d49ec72 965
8c2e41f7 966 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 967 u16 ldt_selector = kvm_read_ldt();
968
8c2e41f7 969 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 970 return 0;
971
8c2e41f7 972 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 973 }
8c2e41f7 974 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 975 return v;
976}
e28baead 977#endif
2d49ec72 978
2ef444f1
CP		 979static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
980{
981 u32 i;
982
983 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
984 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
985 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
986 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
987 for (i = 0; i < addr_range; i++) {
988 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
989 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
990 }
991}
992
993static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
994{
995 u32 i;
996
997 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
998 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
999 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1000 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1001 for (i = 0; i < addr_range; i++) {
1002 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1003 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1004 }
1005}
1006
1007static void pt_guest_enter(struct vcpu_vmx *vmx)
1008{
1009 if (pt_mode == PT_MODE_SYSTEM)
1010 return;
1011
2ef444f1 1012 /*
b08c2896
CP		 1013 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1014 * Save host state before VM entry.
2ef444f1 1015 */
b08c2896 1016 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1017 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1018 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1019 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1020 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1021 }
1022}
1023
1024static void pt_guest_exit(struct vcpu_vmx *vmx)
1025{
1026 if (pt_mode == PT_MODE_SYSTEM)
1027 return;
1028
1029 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1030 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1031 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1032 }
1033
1034 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1035 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1036}
1037
97b7ead3 1038void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1039{
04d2cc77 1040 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1041 struct vmcs_host_state *host_state;
51e8a8cc 1042#ifdef CONFIG_X86_64
35060ed6 1043 int cpu = raw_smp_processor_id();
51e8a8cc 1044#endif
e368b875
SC		 1045 unsigned long fs_base, gs_base;
1046 u16 fs_sel, gs_sel;
26bb0981 1047 int i;
04d2cc77 1048
d264ee0c
SC		 1049 vmx->req_immediate_exit = false;
1050
f48b4711
LA		 1051 /*
1052 * Note that guest MSRs to be saved/restored can also be changed
1053 * when guest state is loaded. This happens when guest transitions
1054 * to/from long-mode by setting MSR_EFER.LMA.
1055 */
1056 if (!vmx->loaded_cpu_state || vmx->guest_msrs_dirty) {
1057 vmx->guest_msrs_dirty = false;
1058 for (i = 0; i < vmx->save_nmsrs; ++i)
1059 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1060 vmx->guest_msrs[i].data,
1061 vmx->guest_msrs[i].mask);
1062
1063 }
1064
bd9966de 1065 if (vmx->loaded_cpu_state)
33ed6329
AK		 1066 return;
1067
bd9966de 1068 vmx->loaded_cpu_state = vmx->loaded_vmcs;
d7ee039e 1069 host_state = &vmx->loaded_cpu_state->host_state;
bd9966de 1070
33ed6329
AK		 1071 /*
1072 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1073 * allow segment selectors with cpl > 0 or ti == 1.
1074 */
d7ee039e 1075 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1076
1077#ifdef CONFIG_X86_64
d7ee039e
SC		 1078 savesegment(ds, host_state->ds_sel);
1079 savesegment(es, host_state->es_sel);
e368b875
SC		 1080
1081 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1082 if (likely(is_64bit_mm(current->mm))) {
1083 save_fsgs_for_kvm();
e368b875
SC		 1084 fs_sel = current->thread.fsindex;
1085 gs_sel = current->thread.gsindex;
b062b794 1086 fs_base = current->thread.fsbase;
e368b875 1087 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1088 } else {
e368b875
SC		 1089 savesegment(fs, fs_sel);
1090 savesegment(gs, gs_sel);
b062b794 1091 fs_base = read_msr(MSR_FS_BASE);
e368b875 1092 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1093 }
b2da15ac 1094
4679b61f 1095 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1096#else
e368b875
SC		 1097 savesegment(fs, fs_sel);
1098 savesegment(gs, gs_sel);
1099 fs_base = segment_base(fs_sel);
1100 gs_base = segment_base(gs_sel);
707c0874 1101#endif
e368b875 1102
8f21a0bb
SC		 1103 if (unlikely(fs_sel != host_state->fs_sel)) {
1104 if (!(fs_sel & 7))
1105 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1106 else
1107 vmcs_write16(HOST_FS_SELECTOR, 0);
1108 host_state->fs_sel = fs_sel;
1109 }
1110 if (unlikely(gs_sel != host_state->gs_sel)) {
1111 if (!(gs_sel & 7))
1112 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1113 else
1114 vmcs_write16(HOST_GS_SELECTOR, 0);
1115 host_state->gs_sel = gs_sel;
1116 }
5e079c7e
SC		 1117 if (unlikely(fs_base != host_state->fs_base)) {
1118 vmcs_writel(HOST_FS_BASE, fs_base);
1119 host_state->fs_base = fs_base;
1120 }
1121 if (unlikely(gs_base != host_state->gs_base)) {
1122 vmcs_writel(HOST_GS_BASE, gs_base);
1123 host_state->gs_base = gs_base;
1124 }
33ed6329
AK		 1125}
1126
6d6095bd 1127static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1128{
d7ee039e
SC		 1129 struct vmcs_host_state *host_state;
1130
bd9966de 1131 if (!vmx->loaded_cpu_state)
33ed6329
AK		 1132 return;
1133
bd9966de 1134 WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
d7ee039e 1135 host_state = &vmx->loaded_cpu_state->host_state;
bd9966de 1136
e1beb1d3 1137 ++vmx->vcpu.stat.host_state_reload;
bd9966de
SC		 1138 vmx->loaded_cpu_state = NULL;
1139
c8770e7b 1140#ifdef CONFIG_X86_64
4679b61f 1141 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1142#endif
d7ee039e
SC		 1143 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1144 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1145#ifdef CONFIG_X86_64
d7ee039e 1146 load_gs_index(host_state->gs_sel);
9581d442 1147#else
d7ee039e 1148 loadsegment(gs, host_state->gs_sel);
33ed6329 1149#endif
33ed6329 1150 }
d7ee039e
SC		 1151 if (host_state->fs_sel & 7)
1152 loadsegment(fs, host_state->fs_sel);
b2da15ac 1153#ifdef CONFIG_X86_64
d7ee039e
SC		 1154 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1155 loadsegment(ds, host_state->ds_sel);
1156 loadsegment(es, host_state->es_sel);
b2da15ac 1157 }
b2da15ac 1158#endif
b7ffc44d 1159 invalidate_tss_limit();
44ea2b17 1160#ifdef CONFIG_X86_64
c8770e7b 1161 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1162#endif
45fc8757 1163 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK		 1164}
1165
678e315e
SC		 1166#ifdef CONFIG_X86_64
1167static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1168{
4679b61f
PB		 1169 preempt_disable();
1170 if (vmx->loaded_cpu_state)
1171 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1172 preempt_enable();
678e315e 1173 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1174}
1175
678e315e
SC		 1176static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1177{
4679b61f
PB		 1178 preempt_disable();
1179 if (vmx->loaded_cpu_state)
1180 wrmsrl(MSR_KERNEL_GS_BASE, data);
1181 preempt_enable();
678e315e
SC		 1182 vmx->msr_guest_kernel_gs_base = data;
1183}
1184#endif
1185
28b835d6
FW		 1186static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1187{
1188 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1189 struct pi_desc old, new;
1190 unsigned int dest;
1191
31afb2ea
PB		 1192 /*
1193 * In case of hot-plug or hot-unplug, we may have to undo
1194 * vmx_vcpu_pi_put even if there is no assigned device. And we
1195 * always keep PI.NDST up to date for simplicity: it makes the
1196 * code easier, and CPU migration is not a fast path.
1197 */
1198 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1199 return;
1200
31afb2ea 1201 /* The full case. */
28b835d6
FW		 1202 do {
1203 old.control = new.control = pi_desc->control;
1204
31afb2ea 1205 dest = cpu_physical_id(cpu);
28b835d6 1206
31afb2ea
PB		 1207 if (x2apic_enabled())
1208 new.ndst = dest;
1209 else
1210 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1211
28b835d6 1212 new.sn = 0;
c0a1666b
PB		 1213 } while (cmpxchg64(&pi_desc->control, old.control,
1214 new.control) != old.control);
c112b5f5
LK		 1215
1216 /*
1217 * Clear SN before reading the bitmap. The VT-d firmware
1218 * writes the bitmap and reads SN atomically (5.2.3 in the
1219 * spec), so it doesn't really have a memory barrier that
1220 * pairs with this, but we cannot do that and we need one.
1221 */
1222 smp_mb__after_atomic();
1223
1224 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1225 pi_set_on(pi_desc);
28b835d6 1226}
1be0e61c 1227
6aa8b732
AK		 1228/*
1229 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1230 * vcpu mutex is already taken.
1231 */
97b7ead3 1232void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1233{
a2fa3e9f 1234 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1235 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1236
b80c76ec 1237 if (!already_loaded) {
fe0e80be 1238 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1239 local_irq_disable();
8f536b76 1240 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1241
1242 /*
1243 * Read loaded_vmcs->cpu should be before fetching
1244 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1245 * See the comments in __loaded_vmcs_clear().
1246 */
1247 smp_rmb();
1248
d462b819
NHE		 1249 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1250 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1251 crash_enable_local_vmclear(cpu);
92fe13be 1252 local_irq_enable();
b80c76ec
JM		 1253 }
1254
1255 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1256 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1257 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1258 indirect_branch_prediction_barrier();
b80c76ec
JM		 1259 }
1260
1261 if (!already_loaded) {
59c58ceb 1262 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1263 unsigned long sysenter_esp;
1264
1265 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1266
6aa8b732
AK		 1267 /*
1268 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1269 * processors. See 22.2.4.
6aa8b732 1270 */
e0c23063 1271 vmcs_writel(HOST_TR_BASE,
72f5e08d 1272 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1273 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 1274
b7ffc44d
AL		 1275 /*
1276 * VM exits change the host TR limit to 0x67 after a VM
1277 * exit. This is okay, since 0x67 covers everything except
1278 * the IO bitmap and have have code to handle the IO bitmap
1279 * being lost after a VM exit.
1280 */
1281 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1282
6aa8b732
AK		 1283 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1284 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1285
d462b819 1286 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1287 }
28b835d6 1288
2680d6da
OH		 1289 /* Setup TSC multiplier */
1290 if (kvm_has_tsc_control &&
c95ba92a
PF		 1291 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1292 decache_tsc_multiplier(vmx);
2680d6da 1293
28b835d6 1294 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 1295 vmx->host_pkru = read_pkru();
74c55931 1296 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1297}
1298
1299static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1300{
1301 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1302
1303 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1304 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1305 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1306 return;
1307
1308 /* Set SN when the vCPU is preempted */
1309 if (vcpu->preempted)
1310 pi_set_sn(pi_desc);
6aa8b732
AK		 1311}
1312
97b7ead3 1313void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1314{
28b835d6
FW		 1315 vmx_vcpu_pi_put(vcpu);
1316
6d6095bd 1317 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1318}
1319
f244deed
WL		 1320static bool emulation_required(struct kvm_vcpu *vcpu)
1321{
1322 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1323}
1324
edcafe3c
AK		 1325static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1326
97b7ead3 1327unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1328{
78ac8b47 1329 unsigned long rflags, save_rflags;
345dcaa8 1330
6de12732
AK		 1331 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1332 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1333 rflags = vmcs_readl(GUEST_RFLAGS);
1334 if (to_vmx(vcpu)->rmode.vm86_active) {
1335 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1336 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1337 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1338 }
1339 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1340 }
6de12732 1341 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1342}
1343
97b7ead3 1344void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1345{
f244deed
WL		 1346 unsigned long old_rflags = vmx_get_rflags(vcpu);
1347
6de12732
AK		 1348 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1349 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1350 if (to_vmx(vcpu)->rmode.vm86_active) {
1351 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1352 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1353 }
6aa8b732 1354 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed
WL		 1355
1356 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1357 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1358}
1359
97b7ead3 1360u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1361{
1362 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1363 int ret = 0;
1364
1365 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1366 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1367 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1368 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1369
37ccdcbe 1370 return ret;
2809f5d2
GC		 1371}
1372
97b7ead3 1373void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1374{
1375 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1376 u32 interruptibility = interruptibility_old;
1377
1378 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1379
48005f64 1380 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1381 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1382 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1383 interruptibility |= GUEST_INTR_STATE_STI;
1384
1385 if ((interruptibility != interruptibility_old))
1386 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1387}
1388
bf8c55d8
CP		 1389static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1390{
1391 struct vcpu_vmx *vmx = to_vmx(vcpu);
1392 unsigned long value;
1393
1394 /*
1395 * Any MSR write that attempts to change bits marked reserved will
1396 * case a #GP fault.
1397 */
1398 if (data & vmx->pt_desc.ctl_bitmask)
1399 return 1;
1400
1401 /*
1402 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1403 * result in a #GP unless the same write also clears TraceEn.
1404 */
1405 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1406 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1407 return 1;
1408
1409 /*
1410 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1411 * and FabricEn would cause #GP, if
1412 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1413 */
1414 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1415 !(data & RTIT_CTL_FABRIC_EN) &&
1416 !intel_pt_validate_cap(vmx->pt_desc.caps,
1417 PT_CAP_single_range_output))
1418 return 1;
1419
1420 /*
1421 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1422 * utilize encodings marked reserved will casue a #GP fault.
1423 */
1424 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1425 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1426 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1427 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1428 return 1;
1429 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1430 PT_CAP_cycle_thresholds);
1431 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1432 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1433 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1434 return 1;
1435 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1436 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1437 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1438 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1439 return 1;
1440
1441 /*
1442 * If ADDRx_CFG is reserved or the encodings is >2 will
1443 * cause a #GP fault.
1444 */
1445 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1446 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1447 return 1;
1448 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1449 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1450 return 1;
1451 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1452 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1453 return 1;
1454 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1455 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1456 return 1;
1457
1458 return 0;
1459}
1460
1461
6aa8b732
AK		 1462static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1463{
1464 unsigned long rip;
6aa8b732 1465
5fdbf976 1466 rip = kvm_rip_read(vcpu);
6aa8b732 1467 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1468 kvm_rip_write(vcpu, rip);
6aa8b732 1469
2809f5d2
GC		 1470 /* skipping an emulated instruction also counts */
1471 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1472}
1473
caa057a2
WL		 1474static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1475{
1476 /*
1477 * Ensure that we clear the HLT state in the VMCS. We don't need to
1478 * explicitly skip the instruction because if the HLT state is set,
1479 * then the instruction is already executing and RIP has already been
1480 * advanced.
1481 */
1482 if (kvm_hlt_in_guest(vcpu->kvm) &&
1483 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1484 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1485}
1486
cfcd20e5 1487static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1488{
77ab6db0 1489 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1490 unsigned nr = vcpu->arch.exception.nr;
1491 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1492 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1493 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1494
da998b46
JM		 1495 kvm_deliver_exception_payload(vcpu);
1496
8ab2d2e2 1497 if (has_error_code) {
77ab6db0 1498 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1499 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1500 }
77ab6db0 1501
7ffd92c5 1502 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1503 int inc_eip = 0;
1504 if (kvm_exception_is_soft(nr))
1505 inc_eip = vcpu->arch.event_exit_inst_len;
1506 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1507 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1508 return;
1509 }
1510
add5ff7a
SC		 1511 WARN_ON_ONCE(vmx->emulation_required);
1512
66fd3f7f
GN		 1513 if (kvm_exception_is_soft(nr)) {
1514 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1515 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1516 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1517 } else
1518 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1519
1520 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1521
1522 vmx_clear_hlt(vcpu);
298101da
AK		 1523}
1524
4e47c7a6
SY		 1525static bool vmx_rdtscp_supported(void)
1526{
1527 return cpu_has_vmx_rdtscp();
1528}
1529
ad756a16
MJ		 1530static bool vmx_invpcid_supported(void)
1531{
eb4b248e 1532 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1533}
1534
a75beee6
ED		 1535/*
1536 * Swap MSR entry in host/guest MSR entry array.
1537 */
8b9cf98c 1538static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1539{
26bb0981 1540 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1541
1542 tmp = vmx->guest_msrs[to];
1543 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1544 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1545}
1546
e38aea3e
AK		 1547/*
1548 * Set up the vmcs to automatically save and restore system
1549 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1550 * mode, as fiddling with msrs is very expensive.
1551 */
8b9cf98c 1552static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1553{
26bb0981 1554 int save_nmsrs, index;
e38aea3e 1555
a75beee6
ED		 1556 save_nmsrs = 0;
1557#ifdef CONFIG_X86_64
84c8c5b8
JM		 1558 /*
1559 * The SYSCALL MSRs are only needed on long mode guests, and only
1560 * when EFER.SCE is set.
1561 */
1562 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1563 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1564 if (index >= 0)
8b9cf98c
RR		 1565 move_msr_up(vmx, index, save_nmsrs++);
1566 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1567 if (index >= 0)
8b9cf98c 1568 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1569 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1570 if (index >= 0)
8b9cf98c 1571 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1572 }
1573#endif
92c0d900
AK		 1574 index = __find_msr_index(vmx, MSR_EFER);
1575 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1576 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1577 index = __find_msr_index(vmx, MSR_TSC_AUX);
1578 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1579 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1580
26bb0981 1581 vmx->save_nmsrs = save_nmsrs;
f48b4711 1582 vmx->guest_msrs_dirty = true;
5897297b 1583
8d14695f 1584 if (cpu_has_vmx_msr_bitmap())
904e14fb 1585 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1586}
1587
e79f245d 1588static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1589{
e79f245d 1590 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1591
e79f245d
KA		 1592 if (is_guest_mode(vcpu) &&
1593 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1594 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1595
1596 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1597}
1598
326e7425 1599static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1600{
45c3af97
PB		 1601 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1602 u64 g_tsc_offset = 0;
1603
1604 /*
1605 * We're here if L1 chose not to trap WRMSR to TSC. According
1606 * to the spec, this should set L1's TSC; The offset that L1
1607 * set for L2 remains unchanged, and still needs to be added
1608 * to the newly set TSC to get L2's TSC.
1609 */
1610 if (is_guest_mode(vcpu) &&
1611 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1612 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1613
45c3af97
PB		 1614 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1615 vcpu->arch.tsc_offset - g_tsc_offset,
1616 offset);
1617 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1618 return offset + g_tsc_offset;
6aa8b732
AK		 1619}
1620
801d3424
NHE		 1621/*
1622 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1623 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1624 * all guests if the "nested" module option is off, and can also be disabled
1625 * for a single guest by disabling its VMX cpuid bit.
1626 */
7c97fcb3 1627bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1628{
d6321d49 1629 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1630}
1631
55d2375e
SC		 1632static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1633 uint64_t val)
62cc6b9d 1634{
55d2375e 1635 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1636
55d2375e 1637 return !(val & ~valid_bits);
62cc6b9d
DM		 1638}
1639
55d2375e 1640static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1641{
55d2375e
SC		 1642 switch (msr->index) {
1643 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1644 if (!nested)
1645 return 1;
1646 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1647 default:
1648 return 1;
1649 }
62cc6b9d 1650
62cc6b9d
DM		 1651 return 0;
1652}
1653
55d2375e
SC		 1654/*
1655 * Reads an msr value (of 'msr_index') into 'pdata'.
1656 * Returns 0 on success, non-0 otherwise.
1657 * Assumes vcpu_load() was already called.
1658 */
1659static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1660{
55d2375e
SC		 1661 struct vcpu_vmx *vmx = to_vmx(vcpu);
1662 struct shared_msr_entry *msr;
bf8c55d8 1663 u32 index;
62cc6b9d 1664
55d2375e
SC		 1665 switch (msr_info->index) {
1666#ifdef CONFIG_X86_64
1667 case MSR_FS_BASE:
1668 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1669 break;
55d2375e
SC		 1670 case MSR_GS_BASE:
1671 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1672 break;
55d2375e
SC		 1673 case MSR_KERNEL_GS_BASE:
1674 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1675 break;
55d2375e
SC		 1676#endif
1677 case MSR_EFER:
1678 return kvm_get_msr_common(vcpu, msr_info);
1679 case MSR_IA32_SPEC_CTRL:
1680 if (!msr_info->host_initiated &&
1681 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1682 return 1;
1683
1684 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1685 break;
6aa8b732 1686 case MSR_IA32_SYSENTER_CS:
609e36d3 1687 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1688 break;
1689 case MSR_IA32_SYSENTER_EIP:
609e36d3 1690 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1691 break;
1692 case MSR_IA32_SYSENTER_ESP:
609e36d3 1693 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1694 break;
0dd376e7 1695 case MSR_IA32_BNDCFGS:
691bd434 1696 if (!kvm_mpx_supported() ||
d6321d49
RK		 1697 (!msr_info->host_initiated &&
1698 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1699 return 1;
609e36d3 1700 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1701 break;
c45dcc71
AR		 1702 case MSR_IA32_MCG_EXT_CTL:
1703 if (!msr_info->host_initiated &&
a6cb099a 1704 !(vmx->msr_ia32_feature_control &
c45dcc71 1705 FEATURE_CONTROL_LMCE))
cae50139 1706 return 1;
c45dcc71
AR		 1707 msr_info->data = vcpu->arch.mcg_ext_ctl;
1708 break;
cae50139 1709 case MSR_IA32_FEATURE_CONTROL:
a6cb099a 1710 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1711 break;
1712 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1713 if (!nested_vmx_allowed(vcpu))
1714 return 1;
6677f3da
PB		 1715 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1716 &msr_info->data);
20300099
WL		 1717 case MSR_IA32_XSS:
1718 if (!vmx_xsaves_supported())
1719 return 1;
609e36d3 1720 msr_info->data = vcpu->arch.ia32_xss;
20300099 1721 break;
bf8c55d8
CP		 1722 case MSR_IA32_RTIT_CTL:
1723 if (pt_mode != PT_MODE_HOST_GUEST)
1724 return 1;
1725 msr_info->data = vmx->pt_desc.guest.ctl;
1726 break;
1727 case MSR_IA32_RTIT_STATUS:
1728 if (pt_mode != PT_MODE_HOST_GUEST)
1729 return 1;
1730 msr_info->data = vmx->pt_desc.guest.status;
1731 break;
1732 case MSR_IA32_RTIT_CR3_MATCH:
1733 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1734 !intel_pt_validate_cap(vmx->pt_desc.caps,
1735 PT_CAP_cr3_filtering))
1736 return 1;
1737 msr_info->data = vmx->pt_desc.guest.cr3_match;
1738 break;
1739 case MSR_IA32_RTIT_OUTPUT_BASE:
1740 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1741 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1742 PT_CAP_topa_output) &&
1743 !intel_pt_validate_cap(vmx->pt_desc.caps,
1744 PT_CAP_single_range_output)))
1745 return 1;
1746 msr_info->data = vmx->pt_desc.guest.output_base;
1747 break;
1748 case MSR_IA32_RTIT_OUTPUT_MASK:
1749 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1750 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1751 PT_CAP_topa_output) &&
1752 !intel_pt_validate_cap(vmx->pt_desc.caps,
1753 PT_CAP_single_range_output)))
1754 return 1;
1755 msr_info->data = vmx->pt_desc.guest.output_mask;
1756 break;
1757 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1758 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1759 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1760 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1761 PT_CAP_num_address_ranges)))
1762 return 1;
1763 if (index % 2)
1764 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1765 else
1766 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1767 break;
4e47c7a6 1768 case MSR_TSC_AUX:
d6321d49
RK		 1769 if (!msr_info->host_initiated &&
1770 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1771 return 1;
b2869f28 1772 /* Else, falls through */
6aa8b732 1773 default:
a6cb099a 1774 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1775 if (msr) {
609e36d3 1776 msr_info->data = msr->data;
3bab1f5d 1777 break;
6aa8b732 1778 }
609e36d3 1779 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1780 }
1781
6aa8b732
AK		 1782 return 0;
1783}
1784
1785/*
1786 * Writes msr value into into the appropriate "register".
1787 * Returns 0 on success, non-0 otherwise.
1788 * Assumes vcpu_load() was already called.
1789 */
8fe8ab46 1790static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1791{
a2fa3e9f 1792 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1793 struct shared_msr_entry *msr;
2cc51560 1794 int ret = 0;
8fe8ab46
WA		 1795 u32 msr_index = msr_info->index;
1796 u64 data = msr_info->data;
bf8c55d8 1797 u32 index;
2cc51560 1798
6aa8b732 1799 switch (msr_index) {
3bab1f5d 1800 case MSR_EFER:
8fe8ab46 1801 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1802 break;
16175a79 1803#ifdef CONFIG_X86_64
6aa8b732 1804 case MSR_FS_BASE:
2fb92db1 1805 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1806 vmcs_writel(GUEST_FS_BASE, data);
1807 break;
1808 case MSR_GS_BASE:
2fb92db1 1809 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1810 vmcs_writel(GUEST_GS_BASE, data);
1811 break;
44ea2b17 1812 case MSR_KERNEL_GS_BASE:
678e315e 1813 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1814 break;
6aa8b732
AK		 1815#endif
1816 case MSR_IA32_SYSENTER_CS:
1817 vmcs_write32(GUEST_SYSENTER_CS, data);
1818 break;
1819 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1820 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1821 break;
1822 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1823 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1824 break;
0dd376e7 1825 case MSR_IA32_BNDCFGS:
691bd434 1826 if (!kvm_mpx_supported() ||
d6321d49
RK		 1827 (!msr_info->host_initiated &&
1828 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1829 return 1;
fd8cb433 1830 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 1831 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 1832 return 1;
0dd376e7
LJ		 1833 vmcs_write64(GUEST_BNDCFGS, data);
1834 break;
d28b387f
KA		 1835 case MSR_IA32_SPEC_CTRL:
1836 if (!msr_info->host_initiated &&
d28b387f
KA		 1837 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1838 return 1;
1839
1840 /* The STIBP bit doesn't fault even if it's not advertised */
9f65fb29 1841 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
d28b387f
KA		 1842 return 1;
1843
1844 vmx->spec_ctrl = data;
1845
1846 if (!data)
1847 break;
1848
1849 /*
1850 * For non-nested:
1851 * When it's written (to non-zero) for the first time, pass
1852 * it through.
1853 *
1854 * For nested:
1855 * The handling of the MSR bitmap for L2 guests is done in
1856 * nested_vmx_merge_msr_bitmap. We should not touch the
1857 * vmcs02.msr_bitmap here since it gets completely overwritten
1858 * in the merging. We update the vmcs01 here for L1 as well
1859 * since it will end up touching the MSR anyway now.
1860 */
1861 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1862 MSR_IA32_SPEC_CTRL,
1863 MSR_TYPE_RW);
1864 break;
15d45071
AR		 1865 case MSR_IA32_PRED_CMD:
1866 if (!msr_info->host_initiated &&
15d45071
AR		 1867 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1868 return 1;
1869
1870 if (data & ~PRED_CMD_IBPB)
1871 return 1;
1872
1873 if (!data)
1874 break;
1875
1876 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1877
1878 /*
1879 * For non-nested:
1880 * When it's written (to non-zero) for the first time, pass
1881 * it through.
1882 *
1883 * For nested:
1884 * The handling of the MSR bitmap for L2 guests is done in
1885 * nested_vmx_merge_msr_bitmap. We should not touch the
1886 * vmcs02.msr_bitmap here since it gets completely overwritten
1887 * in the merging.
1888 */
1889 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1890 MSR_TYPE_W);
1891 break;
468d472f
SY		 1892 case MSR_IA32_CR_PAT:
1893 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
674ea351 1894 if (!kvm_pat_valid(data))
4566654b 1895 return 1;
468d472f
SY		 1896 vmcs_write64(GUEST_IA32_PAT, data);
1897 vcpu->arch.pat = data;
1898 break;
1899 }
8fe8ab46 1900 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1901 break;
ba904635
WA		 1902 case MSR_IA32_TSC_ADJUST:
1903 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1904 break;
c45dcc71
AR		 1905 case MSR_IA32_MCG_EXT_CTL:
1906 if ((!msr_info->host_initiated &&
1907 !(to_vmx(vcpu)->msr_ia32_feature_control &
1908 FEATURE_CONTROL_LMCE)) ||
1909 (data & ~MCG_EXT_CTL_LMCE_EN))
1910 return 1;
1911 vcpu->arch.mcg_ext_ctl = data;
1912 break;
cae50139 1913 case MSR_IA32_FEATURE_CONTROL:
37e4c997 1914 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 1915 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK		 1916 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1917 return 1;
3b84080b 1918 vmx->msr_ia32_feature_control = data;
cae50139
JK		 1919 if (msr_info->host_initiated && data == 0)
1920 vmx_leave_nested(vcpu);
1921 break;
1922 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 1923 if (!msr_info->host_initiated)
1924 return 1; /* they are read-only */
1925 if (!nested_vmx_allowed(vcpu))
1926 return 1;
1927 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL		 1928 case MSR_IA32_XSS:
1929 if (!vmx_xsaves_supported())
1930 return 1;
1931 /*
1932 * The only supported bit as of Skylake is bit 8, but
1933 * it is not supported on KVM.
1934 */
1935 if (data != 0)
1936 return 1;
1937 vcpu->arch.ia32_xss = data;
1938 if (vcpu->arch.ia32_xss != host_xss)
1939 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
989e3992 1940 vcpu->arch.ia32_xss, host_xss, false);
20300099
WL		 1941 else
1942 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
1943 break;
bf8c55d8
CP		 1944 case MSR_IA32_RTIT_CTL:
1945 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 1946 vmx_rtit_ctl_check(vcpu, data) ||
1947 vmx->nested.vmxon)
bf8c55d8
CP		 1948 return 1;
1949 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
1950 vmx->pt_desc.guest.ctl = data;
b08c2896 1951 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 1952 break;
1953 case MSR_IA32_RTIT_STATUS:
1954 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1955 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1956 (data & MSR_IA32_RTIT_STATUS_MASK))
1957 return 1;
1958 vmx->pt_desc.guest.status = data;
1959 break;
1960 case MSR_IA32_RTIT_CR3_MATCH:
1961 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1962 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1963 !intel_pt_validate_cap(vmx->pt_desc.caps,
1964 PT_CAP_cr3_filtering))
1965 return 1;
1966 vmx->pt_desc.guest.cr3_match = data;
1967 break;
1968 case MSR_IA32_RTIT_OUTPUT_BASE:
1969 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1970 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1971 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1972 PT_CAP_topa_output) &&
1973 !intel_pt_validate_cap(vmx->pt_desc.caps,
1974 PT_CAP_single_range_output)) ||
1975 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
1976 return 1;
1977 vmx->pt_desc.guest.output_base = data;
1978 break;
1979 case MSR_IA32_RTIT_OUTPUT_MASK:
1980 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1981 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1982 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1983 PT_CAP_topa_output) &&
1984 !intel_pt_validate_cap(vmx->pt_desc.caps,
1985 PT_CAP_single_range_output)))
1986 return 1;
1987 vmx->pt_desc.guest.output_mask = data;
1988 break;
1989 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1990 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1991 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1992 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1993 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1994 PT_CAP_num_address_ranges)))
1995 return 1;
1996 if (index % 2)
1997 vmx->pt_desc.guest.addr_b[index / 2] = data;
1998 else
1999 vmx->pt_desc.guest.addr_a[index / 2] = data;
2000 break;
4e47c7a6 2001 case MSR_TSC_AUX:
d6321d49
RK		 2002 if (!msr_info->host_initiated &&
2003 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2004 return 1;
2005 /* Check reserved bit, higher 32 bits should be zero */
2006 if ((data >> 32) != 0)
2007 return 1;
b2869f28 2008 /* Else, falls through */
6aa8b732 2009 default:
8b9cf98c 2010 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2011 if (msr) {
8b3c3104 2012 u64 old_msr_data = msr->data;
3bab1f5d 2013 msr->data = data;
2225fd56
AK		 2014 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2015 preempt_disable();
8b3c3104
AH		 2016 ret = kvm_set_shared_msr(msr->index, msr->data,
2017 msr->mask);
2225fd56 2018 preempt_enable();
8b3c3104
AH		 2019 if (ret)
2020 msr->data = old_msr_data;
2225fd56 2021 }
3bab1f5d 2022 break;
6aa8b732 2023 }
8fe8ab46 2024 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2025 }
2026
2cc51560 2027 return ret;
6aa8b732
AK		 2028}
2029
5fdbf976 2030static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2031{
5fdbf976
MT		 2032 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2033 switch (reg) {
2034 case VCPU_REGS_RSP:
2035 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2036 break;
2037 case VCPU_REGS_RIP:
2038 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2039 break;
6de4f3ad
AK		 2040 case VCPU_EXREG_PDPTR:
2041 if (enable_ept)
2042 ept_save_pdptrs(vcpu);
2043 break;
5fdbf976
MT		 2044 default:
2045 break;
2046 }
6aa8b732
AK		 2047}
2048
6aa8b732
AK		 2049static __init int cpu_has_kvm_support(void)
2050{
6210e37b 2051 return cpu_has_vmx();
6aa8b732
AK		 2052}
2053
2054static __init int vmx_disabled_by_bios(void)
2055{
2056 u64 msr;
2057
2058 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2059 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2060 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2061 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2062 && tboot_enabled())
2063 return 1;
23f3e991 2064 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2065 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2066 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2067 && !tboot_enabled()) {
2068 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2069 "activate TXT before enabling KVM\n");
cafd6659 2070 return 1;
f9335afe 2071 }
23f3e991
JC		 2072 /* launched w/o TXT and VMX disabled */
2073 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2074 && !tboot_enabled())
2075 return 1;
cafd6659
SW		 2076 }
2077
2078 return 0;
6aa8b732
AK		 2079}
2080
7725b894
DX		 2081static void kvm_cpu_vmxon(u64 addr)
2082{
fe0e80be 2083 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2084 intel_pt_handle_vmx(1);
2085
4b1e5478 2086 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2087}
2088
13a34e06 2089static int hardware_enable(void)
6aa8b732
AK		 2090{
2091 int cpu = raw_smp_processor_id();
2092 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2093 u64 old, test_bits;
6aa8b732 2094
1e02ce4c 2095 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2096 return -EBUSY;
2097
773e8a04
VK		 2098 /*
2099 * This can happen if we hot-added a CPU but failed to allocate
2100 * VP assist page for it.
2101 */
2102 if (static_branch_unlikely(&enable_evmcs) &&
2103 !hv_get_vp_assist_page(cpu))
2104 return -EFAULT;
2105
d462b819 2106 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2107 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2108 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2109
2110 /*
2111 * Now we can enable the vmclear operation in kdump
2112 * since the loaded_vmcss_on_cpu list on this cpu
2113 * has been initialized.
2114 *
2115 * Though the cpu is not in VMX operation now, there
2116 * is no problem to enable the vmclear operation
2117 * for the loaded_vmcss_on_cpu list is empty!
2118 */
2119 crash_enable_local_vmclear(cpu);
2120
6aa8b732 2121 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2122
2123 test_bits = FEATURE_CONTROL_LOCKED;
2124 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2125 if (tboot_enabled())
2126 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2127
2128 if ((old & test_bits) != test_bits) {
6aa8b732 2129 /* enable and lock */
cafd6659
SW		 2130 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2131 }
fe0e80be 2132 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2133 if (enable_ept)
2134 ept_sync_global();
10474ae8
AG		 2135
2136 return 0;
6aa8b732
AK		 2137}
2138
d462b819 2139static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2140{
2141 int cpu = raw_smp_processor_id();
d462b819 2142 struct loaded_vmcs *v, *n;
543e4243 2143
d462b819
NHE		 2144 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2145 loaded_vmcss_on_cpu_link)
2146 __loaded_vmcs_clear(v);
543e4243
AK		 2147}
2148
710ff4a8
EH		 2149
2150/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2151 * tricks.
2152 */
2153static void kvm_cpu_vmxoff(void)
6aa8b732 2154{
4b1e5478 2155 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2156
2157 intel_pt_handle_vmx(0);
fe0e80be 2158 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2159}
2160
13a34e06 2161static void hardware_disable(void)
710ff4a8 2162{
fe0e80be
DH		 2163 vmclear_local_loaded_vmcss();
2164 kvm_cpu_vmxoff();
710ff4a8
EH		 2165}
2166
1c3d14fe 2167static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2168 u32 msr, u32 *result)
1c3d14fe
YS		 2169{
2170 u32 vmx_msr_low, vmx_msr_high;
2171 u32 ctl = ctl_min | ctl_opt;
2172
2173 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2174
2175 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2176 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2177
2178 /* Ensure minimum (required) set of control bits are supported. */
2179 if (ctl_min & ~ctl)
002c7f7c 2180 return -EIO;
1c3d14fe
YS		 2181
2182 *result = ctl;
2183 return 0;
2184}
2185
7caaa711
SC		 2186static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2187 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2188{
2189 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2190 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2191 u32 _pin_based_exec_control = 0;
2192 u32 _cpu_based_exec_control = 0;
f78e0e2e 2193 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2194 u32 _vmexit_control = 0;
2195 u32 _vmentry_control = 0;
2196
1389309c 2197 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2198 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2199#ifdef CONFIG_X86_64
2200 CPU_BASED_CR8_LOAD_EXITING |
2201 CPU_BASED_CR8_STORE_EXITING |
2202#endif
d56f546d
SY		 2203 CPU_BASED_CR3_LOAD_EXITING |
2204 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2205 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2206 CPU_BASED_MOV_DR_EXITING |
a7052897 2207 CPU_BASED_USE_TSC_OFFSETING |
4d5422ce
WL		 2208 CPU_BASED_MWAIT_EXITING |
2209 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2210 CPU_BASED_INVLPG_EXITING |
2211 CPU_BASED_RDPMC_EXITING;
443381a8 2212
f78e0e2e 2213 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2214 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2215 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2216 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2217 &_cpu_based_exec_control) < 0)
002c7f7c 2218 return -EIO;
6e5d865c
YS		 2219#ifdef CONFIG_X86_64
2220 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2221 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2222 ~CPU_BASED_CR8_STORE_EXITING;
2223#endif
f78e0e2e 2224 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2225 min2 = 0;
2226 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2227 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2228 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2229 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2230 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2231 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2232 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2233 SECONDARY_EXEC_DESC |
ad756a16 2234 SECONDARY_EXEC_RDTSCP |
83d4c286 2235 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2236 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2237 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2238 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2239 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2240 SECONDARY_EXEC_RDSEED_EXITING |
2241 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2242 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2243 SECONDARY_EXEC_TSC_SCALING |
f99e3daf
CP		 2244 SECONDARY_EXEC_PT_USE_GPA |
2245 SECONDARY_EXEC_PT_CONCEAL_VMX |
0b665d30
SC		 2246 SECONDARY_EXEC_ENABLE_VMFUNC |
2247 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2248 if (adjust_vmx_controls(min2, opt2,
2249 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2250 &_cpu_based_2nd_exec_control) < 0)
2251 return -EIO;
2252 }
2253#ifndef CONFIG_X86_64
2254 if (!(_cpu_based_2nd_exec_control &
2255 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2256 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2257#endif
83d4c286
YZ		 2258
2259 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2260 _cpu_based_2nd_exec_control &= ~(
8d14695f 2261 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2262 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2263 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2264
61f1dd90 2265 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2266 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2267
d56f546d 2268 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2269 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2270 enabled */
5fff7d27
GN		 2271 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2272 CPU_BASED_CR3_STORE_EXITING |
2273 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2274 } else if (vmx_cap->ept) {
2275 vmx_cap->ept = 0;
61f1dd90
WL		 2276 pr_warn_once("EPT CAP should not exist if not support "
2277 "1-setting enable EPT VM-execution control\n");
2278 }
2279 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2280 vmx_cap->vpid) {
2281 vmx_cap->vpid = 0;
61f1dd90
WL		 2282 pr_warn_once("VPID CAP should not exist if not support "
2283 "1-setting enable VPID VM-execution control\n");
d56f546d 2284 }
1c3d14fe 2285
91fa0f8e 2286 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2287#ifdef CONFIG_X86_64
2288 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2289#endif
c73da3fc 2290 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2291 VM_EXIT_LOAD_IA32_PAT |
2292 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2293 VM_EXIT_CLEAR_BNDCFGS |
2294 VM_EXIT_PT_CONCEAL_PIP |
2295 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2296 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2297 &_vmexit_control) < 0)
002c7f7c 2298 return -EIO;
1c3d14fe 2299
8a1b4392
PB		 2300 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2301 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2302 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2303 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2304 &_pin_based_exec_control) < 0)
2305 return -EIO;
2306
1c17c3e6
PB		 2307 if (cpu_has_broken_vmx_preemption_timer())
2308 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2309 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2310 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2311 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2312
c845f9c6 2313 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2314 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2315 VM_ENTRY_LOAD_IA32_PAT |
2316 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2317 VM_ENTRY_LOAD_BNDCFGS |
2318 VM_ENTRY_PT_CONCEAL_PIP |
2319 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2320 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2321 &_vmentry_control) < 0)
002c7f7c 2322 return -EIO;
6aa8b732 2323
c73da3fc
SC		 2324 /*
2325 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2326 * can't be used due to an errata where VM Exit may incorrectly clear
2327 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2328 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2329 */
2330 if (boot_cpu_data.x86 == 0x6) {
2331 switch (boot_cpu_data.x86_model) {
2332 case 26: /* AAK155 */
2333 case 30: /* AAP115 */
2334 case 37: /* AAT100 */
2335 case 44: /* BC86,AAY89,BD102 */
2336 case 46: /* BA97 */
85ba2b16 2337 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2338 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2339 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2340 "does not work properly. Using workaround\n");
2341 break;
2342 default:
2343 break;
2344 }
2345 }
2346
2347
c68876fd 2348 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2349
2350 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2351 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2352 return -EIO;
1c3d14fe
YS		 2353
2354#ifdef CONFIG_X86_64
2355 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2356 if (vmx_msr_high & (1u<<16))
002c7f7c 2357 return -EIO;
1c3d14fe
YS		 2358#endif
2359
2360 /* Require Write-Back (WB) memory type for VMCS accesses. */
2361 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2362 return -EIO;
1c3d14fe 2363
002c7f7c 2364 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2365 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2366 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2367
2307af1c 2368 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2369
002c7f7c
YS		 2370 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2371 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2372 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2373 vmcs_conf->vmexit_ctrl = _vmexit_control;
2374 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2375
773e8a04
VK		 2376 if (static_branch_unlikely(&enable_evmcs))
2377 evmcs_sanitize_exec_ctrls(vmcs_conf);
2378
1c3d14fe 2379 return 0;
c68876fd 2380}
6aa8b732 2381
41836839 2382struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2383{
2384 int node = cpu_to_node(cpu);
2385 struct page *pages;
2386 struct vmcs *vmcs;
2387
41836839 2388 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2389 if (!pages)
2390 return NULL;
2391 vmcs = page_address(pages);
1c3d14fe 2392 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2393
2394 /* KVM supports Enlightened VMCS v1 only */
2395 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2396 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2397 else
392b2f25 2398 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2399
491a6038
LA		 2400 if (shadow)
2401 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2402 return vmcs;
2403}
2404
89b0c9f5 2405void free_vmcs(struct vmcs *vmcs)
6aa8b732 2406{
1c3d14fe 2407 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2408}
2409
d462b819
NHE		 2410/*
2411 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2412 */
89b0c9f5 2413void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2414{
2415 if (!loaded_vmcs->vmcs)
2416 return;
2417 loaded_vmcs_clear(loaded_vmcs);
2418 free_vmcs(loaded_vmcs->vmcs);
2419 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2420 if (loaded_vmcs->msr_bitmap)
2421 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2422 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2423}
2424
89b0c9f5 2425int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2426{
491a6038 2427 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2428 if (!loaded_vmcs->vmcs)
2429 return -ENOMEM;
2430
2431 loaded_vmcs->shadow_vmcs = NULL;
2432 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2433
2434 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2435 loaded_vmcs->msr_bitmap = (unsigned long *)
2436 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2437 if (!loaded_vmcs->msr_bitmap)
2438 goto out_vmcs;
2439 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2440
1f008e11
AB		 2441 if (IS_ENABLED(CONFIG_HYPERV) &&
2442 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2443 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2444 struct hv_enlightened_vmcs *evmcs =
2445 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2446
2447 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2448 }
904e14fb 2449 }
d7ee039e
SC		 2450
2451 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2452
f21f165e 2453 return 0;
904e14fb
PB		 2454
2455out_vmcs:
2456 free_loaded_vmcs(loaded_vmcs);
2457 return -ENOMEM;
f21f165e
PB		 2458}
2459
39959588 2460static void free_kvm_area(void)
6aa8b732
AK		 2461{
2462 int cpu;
2463
3230bb47 2464 for_each_possible_cpu(cpu) {
6aa8b732 2465 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2466 per_cpu(vmxarea, cpu) = NULL;
2467 }
6aa8b732
AK		 2468}
2469
6aa8b732
AK		 2470static __init int alloc_kvm_area(void)
2471{
2472 int cpu;
2473
3230bb47 2474 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2475 struct vmcs *vmcs;
2476
41836839 2477 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2478 if (!vmcs) {
2479 free_kvm_area();
2480 return -ENOMEM;
2481 }
2482
2307af1c
LA		 2483 /*
2484 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2485 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2486 * revision_id reported by MSR_IA32_VMX_BASIC.
2487 *
312a4661 2488 * However, even though not explicitly documented by
2307af1c
LA		 2489 * TLFS, VMXArea passed as VMXON argument should
2490 * still be marked with revision_id reported by
2491 * physical CPU.
2492 */
2493 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2494 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2495
6aa8b732
AK		 2496 per_cpu(vmxarea, cpu) = vmcs;
2497 }
2498 return 0;
2499}
2500
91b0aa2c 2501static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2502 struct kvm_segment *save)
6aa8b732 2503{
d99e4152
GN		 2504 if (!emulate_invalid_guest_state) {
2505 /*
2506 * CS and SS RPL should be equal during guest entry according
2507 * to VMX spec, but in reality it is not always so. Since vcpu
2508 * is in the middle of the transition from real mode to
2509 * protected mode it is safe to assume that RPL 0 is a good
2510 * default value.
2511 */
2512 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2513 save->selector &= ~SEGMENT_RPL_MASK;
2514 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2515 save->s = 1;
6aa8b732 2516 }
d99e4152 2517 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2518}
2519
2520static void enter_pmode(struct kvm_vcpu *vcpu)
2521{
2522 unsigned long flags;
a89a8fb9 2523 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2524
d99e4152
GN		 2525 /*
2526 * Update real mode segment cache. It may be not up-to-date if sement
2527 * register was written while vcpu was in a guest mode.
2528 */
2529 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2530 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2531 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2532 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2533 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2534 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2535
7ffd92c5 2536 vmx->rmode.vm86_active = 0;
6aa8b732 2537
2fb92db1
AK		 2538 vmx_segment_cache_clear(vmx);
2539
f5f7b2fe 2540 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2541
2542 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2543 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2544 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2545 vmcs_writel(GUEST_RFLAGS, flags);
2546
66aee91a
RR		 2547 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2548 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2549
2550 update_exception_bitmap(vcpu);
2551
91b0aa2c
GN		 2552 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2553 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2554 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2555 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2556 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2557 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2558}
2559
f5f7b2fe 2560static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2561{
772e0318 2562 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2563 struct kvm_segment var = *save;
2564
2565 var.dpl = 0x3;
2566 if (seg == VCPU_SREG_CS)
2567 var.type = 0x3;
2568
2569 if (!emulate_invalid_guest_state) {
2570 var.selector = var.base >> 4;
2571 var.base = var.base & 0xffff0;
2572 var.limit = 0xffff;
2573 var.g = 0;
2574 var.db = 0;
2575 var.present = 1;
2576 var.s = 1;
2577 var.l = 0;
2578 var.unusable = 0;
2579 var.type = 0x3;
2580 var.avl = 0;
2581 if (save->base & 0xf)
2582 printk_once(KERN_WARNING "kvm: segment base is not "
2583 "paragraph aligned when entering "
2584 "protected mode (seg=%d)", seg);
2585 }
6aa8b732 2586
d99e4152 2587 vmcs_write16(sf->selector, var.selector);
96794e4e 2588 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2589 vmcs_write32(sf->limit, var.limit);
2590 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2591}
2592
2593static void enter_rmode(struct kvm_vcpu *vcpu)
2594{
2595 unsigned long flags;
a89a8fb9 2596 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2597 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2598
f5f7b2fe
AK		 2599 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2600 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2601 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2602 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2603 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2604 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2605 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2606
7ffd92c5 2607 vmx->rmode.vm86_active = 1;
6aa8b732 2608
776e58ea
GN		 2609 /*
2610 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2611 * vcpu. Warn the user that an update is overdue.
776e58ea 2612 */
40bbb9d0 2613 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2614 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2615 "called before entering vcpu\n");
776e58ea 2616
2fb92db1
AK		 2617 vmx_segment_cache_clear(vmx);
2618
40bbb9d0 2619 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2620 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2621 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2622
2623 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2624 vmx->rmode.save_rflags = flags;
6aa8b732 2625
053de044 2626 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2627
2628 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2629 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2630 update_exception_bitmap(vcpu);
2631
d99e4152
GN		 2632 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2633 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2634 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2635 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2636 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2637 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2638
8668a3c4 2639 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2640}
2641
97b7ead3 2642void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2643{
2644 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2645 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2646
2647 if (!msr)
2648 return;
401d10de 2649
f6801dff 2650 vcpu->arch.efer = efer;
401d10de 2651 if (efer & EFER_LMA) {
2961e876 2652 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2653 msr->data = efer;
2654 } else {
2961e876 2655 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2656
2657 msr->data = efer & ~EFER_LME;
2658 }
2659 setup_msrs(vmx);
2660}
2661
05b3e0c2 2662#ifdef CONFIG_X86_64
6aa8b732
AK		 2663
2664static void enter_lmode(struct kvm_vcpu *vcpu)
2665{
2666 u32 guest_tr_ar;
2667
2fb92db1
AK		 2668 vmx_segment_cache_clear(to_vmx(vcpu));
2669
6aa8b732 2670 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2671 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2672 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2673 __func__);
6aa8b732 2674 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2675 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2676 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2677 }
da38f438 2678 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2679}
2680
2681static void exit_lmode(struct kvm_vcpu *vcpu)
2682{
2961e876 2683 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2684 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2685}
2686
2687#endif
2688
faff8758
JS		 2689static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2690{
2691 int vpid = to_vmx(vcpu)->vpid;
2692
2693 if (!vpid_sync_vcpu_addr(vpid, addr))
2694 vpid_sync_context(vpid);
2695
2696 /*
2697 * If VPIDs are not supported or enabled, then the above is a no-op.
2698 * But we don't really need a TLB flush in that case anyway, because
2699 * each VM entry/exit includes an implicit flush when VPID is 0.
2700 */
2701}
2702
e8467fda
AK		 2703static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2704{
2705 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2706
2707 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2708 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2709}
2710
aff48baa
AK		 2711static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2712{
b4d18517 2713 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
aff48baa
AK		 2714 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2715 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2716}
2717
25c4c276 2718static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2719{
fc78f519
AK		 2720 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2721
2722 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2723 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2724}
2725
1439442c
SY		 2726static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2727{
d0d538b9
GN		 2728 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2729
6de4f3ad
AK		 2730 if (!test_bit(VCPU_EXREG_PDPTR,
2731 (unsigned long *)&vcpu->arch.regs_dirty))
2732 return;
2733
1439442c 2734 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 2735 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2736 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2737 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2738 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2739 }
2740}
2741
97b7ead3 2742void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2743{
d0d538b9
GN		 2744 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2745
8f5d549f 2746 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 2747 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2748 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2749 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2750 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2751 }
6de4f3ad
AK		 2752
2753 __set_bit(VCPU_EXREG_PDPTR,
2754 (unsigned long *)&vcpu->arch.regs_avail);
2755 __set_bit(VCPU_EXREG_PDPTR,
2756 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2757}
2758
1439442c
SY		 2759static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2760 unsigned long cr0,
2761 struct kvm_vcpu *vcpu)
2762{
5233dd51
MT		 2763 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2764 vmx_decache_cr3(vcpu);
1439442c
SY		 2765 if (!(cr0 & X86_CR0_PG)) {
2766 /* From paging/starting to nonpaging */
2767 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2768 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2769 (CPU_BASED_CR3_LOAD_EXITING |
2770 CPU_BASED_CR3_STORE_EXITING));
2771 vcpu->arch.cr0 = cr0;
fc78f519 2772 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2773 } else if (!is_paging(vcpu)) {
2774 /* From nonpaging to paging */
2775 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2776 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2777 ~(CPU_BASED_CR3_LOAD_EXITING |
2778 CPU_BASED_CR3_STORE_EXITING));
2779 vcpu->arch.cr0 = cr0;
fc78f519 2780 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2781 }
95eb84a7
SY		 2782
2783 if (!(cr0 & X86_CR0_WP))
2784 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2785}
2786
97b7ead3 2787void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2788{
7ffd92c5 2789 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2790 unsigned long hw_cr0;
2791
3de6347b 2792 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2793 if (enable_unrestricted_guest)
5037878e 2794 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2795 else {
5037878e 2796 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2797
218e763f
GN		 2798 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2799 enter_pmode(vcpu);
6aa8b732 2800
218e763f
GN		 2801 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2802 enter_rmode(vcpu);
2803 }
6aa8b732 2804
05b3e0c2 2805#ifdef CONFIG_X86_64
f6801dff 2806 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2807 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2808 enter_lmode(vcpu);
707d92fa 2809 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2810 exit_lmode(vcpu);
2811 }
2812#endif
2813
b4d18517 2814 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2815 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2816
6aa8b732 2817 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2818 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2819 vcpu->arch.cr0 = cr0;
14168786
GN		 2820
2821 /* depends on vcpu->arch.cr0 to be set to a new value */
2822 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2823}
2824
855feb67
YZ		 2825static int get_ept_level(struct kvm_vcpu *vcpu)
2826{
2827 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2828 return 5;
2829 return 4;
2830}
2831
89b0c9f5 2832u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2833{
855feb67
YZ		 2834 u64 eptp = VMX_EPTP_MT_WB;
2835
2836 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 2837
995f00a6
PF		 2838 if (enable_ept_ad_bits &&
2839 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 2840 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 2841 eptp |= (root_hpa & PAGE_MASK);
2842
2843 return eptp;
2844}
2845
97b7ead3 2846void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 2847{
877ad952 2848 struct kvm *kvm = vcpu->kvm;
1439442c
SY		 2849 unsigned long guest_cr3;
2850 u64 eptp;
2851
2852 guest_cr3 = cr3;
089d034e 2853 if (enable_ept) {
995f00a6 2854 eptp = construct_eptp(vcpu, cr3);
1439442c 2855 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 2856
2857 if (kvm_x86_ops->tlb_remote_flush) {
2858 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2859 to_vmx(vcpu)->ept_pointer = eptp;
2860 to_kvm_vmx(kvm)->ept_pointers_match
2861 = EPT_POINTERS_CHECK;
2862 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2863 }
2864
e90008df
SC		 2865 if (enable_unrestricted_guest || is_paging(vcpu) ||
2866 is_guest_mode(vcpu))
59ab5a8f
JK		 2867 guest_cr3 = kvm_read_cr3(vcpu);
2868 else
877ad952 2869 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
7c93be44 2870 ept_load_pdptrs(vcpu);
1439442c
SY		 2871 }
2872
1439442c 2873 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2874}
2875
97b7ead3 2876int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2877{
085e68ee
BS		 2878 /*
2879 * Pass through host's Machine Check Enable value to hw_cr4, which
2880 * is in force while we are in guest mode. Do not let guests control
2881 * this bit, even if host CR4.MCE == 0.
2882 */
5dc1f044
SC		 2883 unsigned long hw_cr4;
2884
2885 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2886 if (enable_unrestricted_guest)
2887 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2888 else if (to_vmx(vcpu)->rmode.vm86_active)
2889 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2890 else
2891 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 2892
64f7a115
SC		 2893 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2894 if (cr4 & X86_CR4_UMIP) {
2895 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
0367f205 2896 SECONDARY_EXEC_DESC);
64f7a115
SC		 2897 hw_cr4 &= ~X86_CR4_UMIP;
2898 } else if (!is_guest_mode(vcpu) ||
2899 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
2900 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
2901 SECONDARY_EXEC_DESC);
2902 }
0367f205 2903
5e1746d6
NHE		 2904 if (cr4 & X86_CR4_VMXE) {
2905 /*
2906 * To use VMXON (and later other VMX instructions), a guest
2907 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2908 * So basically the check on whether to allow nested VMX
5bea5123
PB		 2909 * is here. We operate under the default treatment of SMM,
2910 * so VMX cannot be enabled under SMM.
5e1746d6 2911 */
5bea5123 2912 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 2913 return 1;
1a0d74e6 2914 }
3899152c
DM		 2915
2916 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 2917 return 1;
2918
ad312c7c 2919 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 2920
2921 if (!enable_unrestricted_guest) {
2922 if (enable_ept) {
2923 if (!is_paging(vcpu)) {
2924 hw_cr4 &= ~X86_CR4_PAE;
2925 hw_cr4 |= X86_CR4_PSE;
2926 } else if (!(cr4 & X86_CR4_PAE)) {
2927 hw_cr4 &= ~X86_CR4_PAE;
2928 }
bc23008b 2929 }
1439442c 2930
656ec4a4 2931 /*
ddba2628
HH		 2932 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
2933 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
2934 * to be manually disabled when guest switches to non-paging
2935 * mode.
2936 *
2937 * If !enable_unrestricted_guest, the CPU is always running
2938 * with CR0.PG=1 and CR4 needs to be modified.
2939 * If enable_unrestricted_guest, the CPU automatically
2940 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 2941 */
5dc1f044
SC		 2942 if (!is_paging(vcpu))
2943 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
2944 }
656ec4a4 2945
1439442c
SY		 2946 vmcs_writel(CR4_READ_SHADOW, cr4);
2947 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2948 return 0;
6aa8b732
AK		 2949}
2950
97b7ead3 2951void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 2952{
a9179499 2953 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2954 u32 ar;
2955
c6ad1153 2956 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 2957 *var = vmx->rmode.segs[seg];
a9179499 2958 if (seg == VCPU_SREG_TR
2fb92db1 2959 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 2960 return;
1390a28b
AK		 2961 var->base = vmx_read_guest_seg_base(vmx, seg);
2962 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2963 return;
a9179499 2964 }
2fb92db1
AK		 2965 var->base = vmx_read_guest_seg_base(vmx, seg);
2966 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2967 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2968 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 2969 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 2970 var->type = ar & 15;
2971 var->s = (ar >> 4) & 1;
2972 var->dpl = (ar >> 5) & 3;
03617c18
GN		 2973 /*
2974 * Some userspaces do not preserve unusable property. Since usable
2975 * segment has to be present according to VMX spec we can use present
2976 * property to amend userspace bug by making unusable segment always
2977 * nonpresent. vmx_segment_access_rights() already marks nonpresent
2978 * segment as unusable.
2979 */
2980 var->present = !var->unusable;
6aa8b732
AK		 2981 var->avl = (ar >> 12) & 1;
2982 var->l = (ar >> 13) & 1;
2983 var->db = (ar >> 14) & 1;
2984 var->g = (ar >> 15) & 1;
6aa8b732
AK		 2985}
2986
a9179499
AK		 2987static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2988{
a9179499
AK		 2989 struct kvm_segment s;
2990
2991 if (to_vmx(vcpu)->rmode.vm86_active) {
2992 vmx_get_segment(vcpu, &s, seg);
2993 return s.base;
2994 }
2fb92db1 2995 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 2996}
2997
97b7ead3 2998int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2999{
b09408d0
MT		 3000 struct vcpu_vmx *vmx = to_vmx(vcpu);
3001
ae9fedc7 3002 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3003 return 0;
ae9fedc7
PB		 3004 else {
3005 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3006 return VMX_AR_DPL(ar);
69c73028 3007 }
69c73028
AK		 3008}
3009
653e3108 3010static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3011{
6aa8b732
AK		 3012 u32 ar;
3013
f0495f9b 3014 if (var->unusable || !var->present)
6aa8b732
AK		 3015 ar = 1 << 16;
3016 else {
3017 ar = var->type & 15;
3018 ar |= (var->s & 1) << 4;
3019 ar |= (var->dpl & 3) << 5;
3020 ar |= (var->present & 1) << 7;
3021 ar |= (var->avl & 1) << 12;
3022 ar |= (var->l & 1) << 13;
3023 ar |= (var->db & 1) << 14;
3024 ar |= (var->g & 1) << 15;
3025 }
653e3108
AK		 3026
3027 return ar;
3028}
3029
97b7ead3 3030void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3031{
7ffd92c5 3032 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3033 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3034
2fb92db1
AK		 3035 vmx_segment_cache_clear(vmx);
3036
1ecd50a9
GN		 3037 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3038 vmx->rmode.segs[seg] = *var;
3039 if (seg == VCPU_SREG_TR)
3040 vmcs_write16(sf->selector, var->selector);
3041 else if (var->s)
3042 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3043 goto out;
653e3108 3044 }
1ecd50a9 3045
653e3108
AK		 3046 vmcs_writel(sf->base, var->base);
3047 vmcs_write32(sf->limit, var->limit);
3048 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3049
3050 /*
3051 * Fix the "Accessed" bit in AR field of segment registers for older
3052 * qemu binaries.
3053 * IA32 arch specifies that at the time of processor reset the
3054 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3055 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3056 * state vmexit when "unrestricted guest" mode is turned on.
3057 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3058 * tree. Newer qemu binaries with that qemu fix would not need this
3059 * kvm hack.
3060 */
3061 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3062 var->type |= 0x1; /* Accessed */
3a624e29 3063
f924d66d 3064 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3065
3066out:
98eb2f8b 3067 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3068}
3069
6aa8b732
AK		 3070static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3071{
2fb92db1 3072 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3073
3074 *db = (ar >> 14) & 1;
3075 *l = (ar >> 13) & 1;
3076}
3077
89a27f4d 3078static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3079{
89a27f4d
GN		 3080 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3081 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3082}
3083
89a27f4d 3084static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3085{
89a27f4d
GN		 3086 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3087 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3088}
3089
89a27f4d 3090static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3091{
89a27f4d
GN		 3092 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3093 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3094}
3095
89a27f4d 3096static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3097{
89a27f4d
GN		 3098 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3099 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3100}
3101
648dfaa7
MG		 3102static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3103{
3104 struct kvm_segment var;
3105 u32 ar;
3106
3107 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3108 var.dpl = 0x3;
0647f4aa
GN		 3109 if (seg == VCPU_SREG_CS)
3110 var.type = 0x3;
648dfaa7
MG		 3111 ar = vmx_segment_access_rights(&var);
3112
3113 if (var.base != (var.selector << 4))
3114 return false;
89efbed0 3115 if (var.limit != 0xffff)
648dfaa7 3116 return false;
07f42f5f 3117 if (ar != 0xf3)
648dfaa7
MG		 3118 return false;
3119
3120 return true;
3121}
3122
3123static bool code_segment_valid(struct kvm_vcpu *vcpu)
3124{
3125 struct kvm_segment cs;
3126 unsigned int cs_rpl;
3127
3128 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3129 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3130
1872a3f4
AK		 3131 if (cs.unusable)
3132 return false;
4d283ec9 3133 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3134 return false;
3135 if (!cs.s)
3136 return false;
4d283ec9 3137 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3138 if (cs.dpl > cs_rpl)
3139 return false;
1872a3f4 3140 } else {
648dfaa7
MG		 3141 if (cs.dpl != cs_rpl)
3142 return false;
3143 }
3144 if (!cs.present)
3145 return false;
3146
3147 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3148 return true;
3149}
3150
3151static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3152{
3153 struct kvm_segment ss;
3154 unsigned int ss_rpl;
3155
3156 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3157 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3158
1872a3f4
AK		 3159 if (ss.unusable)
3160 return true;
3161 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3162 return false;
3163 if (!ss.s)
3164 return false;
3165 if (ss.dpl != ss_rpl) /* DPL != RPL */
3166 return false;
3167 if (!ss.present)
3168 return false;
3169
3170 return true;
3171}
3172
3173static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3174{
3175 struct kvm_segment var;
3176 unsigned int rpl;
3177
3178 vmx_get_segment(vcpu, &var, seg);
b32a9918 3179 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3180
1872a3f4
AK		 3181 if (var.unusable)
3182 return true;
648dfaa7
MG		 3183 if (!var.s)
3184 return false;
3185 if (!var.present)
3186 return false;
4d283ec9 3187 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3188 if (var.dpl < rpl) /* DPL < RPL */
3189 return false;
3190 }
3191
3192 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3193 * rights flags
3194 */
3195 return true;
3196}
3197
3198static bool tr_valid(struct kvm_vcpu *vcpu)
3199{
3200 struct kvm_segment tr;
3201
3202 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3203
1872a3f4
AK		 3204 if (tr.unusable)
3205 return false;
b32a9918 3206 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3207 return false;
1872a3f4 3208 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3209 return false;
3210 if (!tr.present)
3211 return false;
3212
3213 return true;
3214}
3215
3216static bool ldtr_valid(struct kvm_vcpu *vcpu)
3217{
3218 struct kvm_segment ldtr;
3219
3220 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3221
1872a3f4
AK		 3222 if (ldtr.unusable)
3223 return true;
b32a9918 3224 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3225 return false;
3226 if (ldtr.type != 2)
3227 return false;
3228 if (!ldtr.present)
3229 return false;
3230
3231 return true;
3232}
3233
3234static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3235{
3236 struct kvm_segment cs, ss;
3237
3238 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3239 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3240
b32a9918
NA		 3241 return ((cs.selector & SEGMENT_RPL_MASK) ==
3242 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3243}
3244
3245/*
3246 * Check if guest state is valid. Returns true if valid, false if
3247 * not.
3248 * We assume that registers are always usable
3249 */
3250static bool guest_state_valid(struct kvm_vcpu *vcpu)
3251{
c5e97c80
GN		 3252 if (enable_unrestricted_guest)
3253 return true;
3254
648dfaa7 3255 /* real mode guest state checks */
f13882d8 3256 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3257 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3258 return false;
3259 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3260 return false;
3261 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3262 return false;
3263 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3264 return false;
3265 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3266 return false;
3267 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3268 return false;
3269 } else {
3270 /* protected mode guest state checks */
3271 if (!cs_ss_rpl_check(vcpu))
3272 return false;
3273 if (!code_segment_valid(vcpu))
3274 return false;
3275 if (!stack_segment_valid(vcpu))
3276 return false;
3277 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3278 return false;
3279 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3280 return false;
3281 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3282 return false;
3283 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3284 return false;
3285 if (!tr_valid(vcpu))
3286 return false;
3287 if (!ldtr_valid(vcpu))
3288 return false;
3289 }
3290 /* TODO:
3291 * - Add checks on RIP
3292 * - Add checks on RFLAGS
3293 */
3294
3295 return true;
3296}
3297
d77c26fc 3298static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3299{
40dcaa9f 3300 gfn_t fn;
195aefde 3301 u16 data = 0;
1f755a82 3302 int idx, r;
6aa8b732 3303
40dcaa9f 3304 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3305 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3306 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3307 if (r < 0)
10589a46 3308 goto out;
195aefde 3309 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3310 r = kvm_write_guest_page(kvm, fn++, &data,
3311 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3312 if (r < 0)
10589a46 3313 goto out;
195aefde
IE		 3314 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3315 if (r < 0)
10589a46 3316 goto out;
195aefde
IE		 3317 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3318 if (r < 0)
10589a46 3319 goto out;
195aefde 3320 data = ~0;
10589a46
MT		 3321 r = kvm_write_guest_page(kvm, fn, &data,
3322 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3323 sizeof(u8));
10589a46 3324out:
40dcaa9f 3325 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3326 return r;
6aa8b732
AK		 3327}
3328
b7ebfb05
SY		 3329static int init_rmode_identity_map(struct kvm *kvm)
3330{
40bbb9d0 3331 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
f51770ed 3332 int i, idx, r = 0;
ba049e93 3333 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3334 u32 tmp;
3335
40bbb9d0 3336 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3337 mutex_lock(&kvm->slots_lock);
3338
40bbb9d0 3339 if (likely(kvm_vmx->ept_identity_pagetable_done))
a255d479 3340 goto out2;
a255d479 3341
40bbb9d0
SC		 3342 if (!kvm_vmx->ept_identity_map_addr)
3343 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3344 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3345
d8a6e365 3346 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3347 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3348 if (r < 0)
a255d479
TC		 3349 goto out2;
3350
40dcaa9f 3351 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3352 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3353 if (r < 0)
3354 goto out;
3355 /* Set up identity-mapping pagetable for EPT in real mode */
3356 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3357 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3358 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3359 r = kvm_write_guest_page(kvm, identity_map_pfn,
3360 &tmp, i * sizeof(tmp), sizeof(tmp));
3361 if (r < 0)
3362 goto out;
3363 }
40bbb9d0 3364 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3365
b7ebfb05 3366out:
40dcaa9f 3367 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3368
3369out2:
3370 mutex_unlock(&kvm->slots_lock);
f51770ed 3371 return r;
b7ebfb05
SY		 3372}
3373
6aa8b732
AK		 3374static void seg_setup(int seg)
3375{
772e0318 3376 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3377 unsigned int ar;
6aa8b732
AK		 3378
3379 vmcs_write16(sf->selector, 0);
3380 vmcs_writel(sf->base, 0);
3381 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3382 ar = 0x93;
3383 if (seg == VCPU_SREG_CS)
3384 ar |= 0x08; /* code segment */
3a624e29
NK		 3385
3386 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3387}
3388
f78e0e2e
SY		 3389static int alloc_apic_access_page(struct kvm *kvm)
3390{
4484141a 3391 struct page *page;
f78e0e2e
SY		 3392 int r = 0;
3393
79fac95e 3394 mutex_lock(&kvm->slots_lock);
c24ae0dc 3395 if (kvm->arch.apic_access_page_done)
f78e0e2e 3396 goto out;
1d8007bd
PB		 3397 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3398 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3399 if (r)
3400 goto out;
72dc67a6 3401
73a6d941 3402 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3403 if (is_error_page(page)) {
3404 r = -EFAULT;
3405 goto out;
3406 }
3407
c24ae0dc
TC		 3408 /*
3409 * Do not pin the page in memory, so that memory hot-unplug
3410 * is able to migrate it.
3411 */
3412 put_page(page);
3413 kvm->arch.apic_access_page_done = true;
f78e0e2e 3414out:
79fac95e 3415 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3416 return r;
3417}
3418
97b7ead3 3419int allocate_vpid(void)
2384d2b3
SY		 3420{
3421 int vpid;
3422
919818ab 3423 if (!enable_vpid)
991e7a0e 3424 return 0;
2384d2b3
SY		 3425 spin_lock(&vmx_vpid_lock);
3426 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3427 if (vpid < VMX_NR_VPIDS)
2384d2b3 3428 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3429 else
3430 vpid = 0;
2384d2b3 3431 spin_unlock(&vmx_vpid_lock);
991e7a0e 3432 return vpid;
2384d2b3
SY		 3433}
3434
97b7ead3 3435void free_vpid(int vpid)
cdbecfc3 3436{
991e7a0e 3437 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3438 return;
3439 spin_lock(&vmx_vpid_lock);
991e7a0e 3440 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3441 spin_unlock(&vmx_vpid_lock);
3442}
3443
1e4329ee 3444static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3445 u32 msr, int type)
25c5f225 3446{
3e7c73e9 3447 int f = sizeof(unsigned long);
25c5f225
SY		 3448
3449 if (!cpu_has_vmx_msr_bitmap())
3450 return;
3451
ceef7d10
VK		 3452 if (static_branch_unlikely(&enable_evmcs))
3453 evmcs_touch_msr_bitmap();
3454
25c5f225
SY		 3455 /*
3456 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3457 * have the write-low and read-high bitmap offsets the wrong way round.
3458 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3459 */
25c5f225 3460 if (msr <= 0x1fff) {
8d14695f
YZ		 3461 if (type & MSR_TYPE_R)
3462 /* read-low */
3463 __clear_bit(msr, msr_bitmap + 0x000 / f);
3464
3465 if (type & MSR_TYPE_W)
3466 /* write-low */
3467 __clear_bit(msr, msr_bitmap + 0x800 / f);
3468
25c5f225
SY		 3469 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3470 msr &= 0x1fff;
8d14695f
YZ		 3471 if (type & MSR_TYPE_R)
3472 /* read-high */
3473 __clear_bit(msr, msr_bitmap + 0x400 / f);
3474
3475 if (type & MSR_TYPE_W)
3476 /* write-high */
3477 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3478
3479 }
3480}
3481
1e4329ee 3482static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3483 u32 msr, int type)
3484{
3485 int f = sizeof(unsigned long);
3486
3487 if (!cpu_has_vmx_msr_bitmap())
3488 return;
3489
ceef7d10
VK		 3490 if (static_branch_unlikely(&enable_evmcs))
3491 evmcs_touch_msr_bitmap();
3492
904e14fb
PB		 3493 /*
3494 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3495 * have the write-low and read-high bitmap offsets the wrong way round.
3496 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3497 */
3498 if (msr <= 0x1fff) {
3499 if (type & MSR_TYPE_R)
3500 /* read-low */
3501 __set_bit(msr, msr_bitmap + 0x000 / f);
3502
3503 if (type & MSR_TYPE_W)
3504 /* write-low */
3505 __set_bit(msr, msr_bitmap + 0x800 / f);
3506
3507 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3508 msr &= 0x1fff;
3509 if (type & MSR_TYPE_R)
3510 /* read-high */
3511 __set_bit(msr, msr_bitmap + 0x400 / f);
3512
3513 if (type & MSR_TYPE_W)
3514 /* write-high */
3515 __set_bit(msr, msr_bitmap + 0xc00 / f);
3516
3517 }
3518}
3519
1e4329ee 3520static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3521 u32 msr, int type, bool value)
3522{
3523 if (value)
3524 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3525 else
3526 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3527}
3528
904e14fb 3529static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3530{
904e14fb
PB		 3531 u8 mode = 0;
3532
3533 if (cpu_has_secondary_exec_ctrls() &&
3534 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
3535 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3536 mode |= MSR_BITMAP_MODE_X2APIC;
3537 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3538 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3539 }
3540
904e14fb 3541 return mode;
8d14695f
YZ		 3542}
3543
904e14fb
PB		 3544static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3545 u8 mode)
8d14695f 3546{
904e14fb
PB		 3547 int msr;
3548
3549 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3550 unsigned word = msr / BITS_PER_LONG;
3551 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3552 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3553 }
3554
3555 if (mode & MSR_BITMAP_MODE_X2APIC) {
3556 /*
3557 * TPR reads and writes can be virtualized even if virtual interrupt
3558 * delivery is not in use.
3559 */
3560 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3561 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3562 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3563 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3564 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3565 }
f6e90f9e 3566 }
5897297b
AK		 3567}
3568
97b7ead3 3569void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3570{
3571 struct vcpu_vmx *vmx = to_vmx(vcpu);
3572 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3573 u8 mode = vmx_msr_bitmap_mode(vcpu);
3574 u8 changed = mode ^ vmx->msr_bitmap_mode;
3575
3576 if (!changed)
3577 return;
3578
904e14fb
PB		 3579 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3580 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3581
3582 vmx->msr_bitmap_mode = mode;
3583}
3584
b08c2896
CP		 3585void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3586{
3587 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3588 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3589 u32 i;
3590
3591 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3592 MSR_TYPE_RW, flag);
3593 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3594 MSR_TYPE_RW, flag);
3595 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3596 MSR_TYPE_RW, flag);
3597 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3598 MSR_TYPE_RW, flag);
3599 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3600 vmx_set_intercept_for_msr(msr_bitmap,
3601 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3602 vmx_set_intercept_for_msr(msr_bitmap,
3603 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3604 }
3605}
3606
b2a05fef 3607static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
d50ab6c1 3608{
d62caabb 3609 return enable_apicv;
d50ab6c1
PB		 3610}
3611
e6c67d8c
LA		 3612static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3613{
3614 struct vcpu_vmx *vmx = to_vmx(vcpu);
3615 void *vapic_page;
3616 u32 vppr;
3617 int rvi;
3618
3619 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3620 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3621 WARN_ON_ONCE(!vmx->nested.virtual_apic_page))
3622 return false;
3623
7e712684 3624 rvi = vmx_get_rvi();
e6c67d8c
LA		 3625
3626 vapic_page = kmap(vmx->nested.virtual_apic_page);
3627 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3628 kunmap(vmx->nested.virtual_apic_page);
3629
3630 return ((rvi & 0xf0) > (vppr & 0xf0));
3631}
3632
06a5524f
WV		 3633static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3634 bool nested)
21bc8dc5
RK		 3635{
3636#ifdef CONFIG_SMP
06a5524f
WV		 3637 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3638
21bc8dc5 3639 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3640 /*
5753743f
HZ		 3641 * The vector of interrupt to be delivered to vcpu had
3642 * been set in PIR before this function.
3643 *
3644 * Following cases will be reached in this block, and
3645 * we always send a notification event in all cases as
3646 * explained below.
3647 *
3648 * Case 1: vcpu keeps in non-root mode. Sending a
3649 * notification event posts the interrupt to vcpu.
3650 *
3651 * Case 2: vcpu exits to root mode and is still
3652 * runnable. PIR will be synced to vIRR before the
3653 * next vcpu entry. Sending a notification event in
3654 * this case has no effect, as vcpu is not in root
3655 * mode.
28b835d6 3656 *
5753743f
HZ		 3657 * Case 3: vcpu exits to root mode and is blocked.
3658 * vcpu_block() has already synced PIR to vIRR and
3659 * never blocks vcpu if vIRR is not cleared. Therefore,
3660 * a blocked vcpu here does not wait for any requested
3661 * interrupts in PIR, and sending a notification event
3662 * which has no effect is safe here.
28b835d6 3663 */
28b835d6 3664
06a5524f 3665 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3666 return true;
3667 }
3668#endif
3669 return false;
3670}
3671
705699a1
WV		 3672static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3673 int vector)
3674{
3675 struct vcpu_vmx *vmx = to_vmx(vcpu);
3676
3677 if (is_guest_mode(vcpu) &&
3678 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3679 /*
3680 * If a posted intr is not recognized by hardware,
3681 * we will accomplish it in the next vmentry.
3682 */
3683 vmx->nested.pi_pending = true;
3684 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3685 /* the PIR and ON have been set by L1. */
3686 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3687 kvm_vcpu_kick(vcpu);
705699a1
WV		 3688 return 0;
3689 }
3690 return -1;
3691}
a20ed54d
YZ		 3692/*
3693 * Send interrupt to vcpu via posted interrupt way.
3694 * 1. If target vcpu is running(non-root mode), send posted interrupt
3695 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3696 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3697 * interrupt from PIR in next vmentry.
3698 */
3699static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3700{
3701 struct vcpu_vmx *vmx = to_vmx(vcpu);
3702 int r;
3703
705699a1
WV		 3704 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3705 if (!r)
3706 return;
3707
a20ed54d
YZ		 3708 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3709 return;
3710
b95234c8
PB		 3711 /* If a previous notification has sent the IPI, nothing to do. */
3712 if (pi_test_and_set_on(&vmx->pi_desc))
3713 return;
3714
06a5524f 3715 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ		 3716 kvm_vcpu_kick(vcpu);
3717}
3718
a3a8ff8e
NHE		 3719/*
3720 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3721 * will not change in the lifetime of the guest.
3722 * Note that host-state that does change is set elsewhere. E.g., host-state
3723 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3724 */
97b7ead3 3725void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3726{
3727 u32 low32, high32;
3728 unsigned long tmpl;
3729 struct desc_ptr dt;
d6e41f11 3730 unsigned long cr0, cr3, cr4;
a3a8ff8e 3731
04ac88ab
AL		 3732 cr0 = read_cr0();
3733 WARN_ON(cr0 & X86_CR0_TS);
3734 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3735
3736 /*
3737 * Save the most likely value for this task's CR3 in the VMCS.
3738 * We can't use __get_current_cr3_fast() because we're not atomic.
3739 */
6c690ee1 3740 cr3 = __read_cr3();
d6e41f11 3741 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3742 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3743
d974baa3 3744 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3745 cr4 = cr4_read_shadow();
d974baa3 3746 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3747 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3748
a3a8ff8e 3749 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3750#ifdef CONFIG_X86_64
3751 /*
3752 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3753 * vmx_prepare_switch_to_host(), in case userspace uses
3754 * the null selectors too (the expected case).
b2da15ac
AK		 3755 */
3756 vmcs_write16(HOST_DS_SELECTOR, 0);
3757 vmcs_write16(HOST_ES_SELECTOR, 0);
3758#else
a3a8ff8e
NHE		 3759 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3760 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3761#endif
a3a8ff8e
NHE		 3762 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3763 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3764
87930019 3765 store_idt(&dt);
a3a8ff8e 3766 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 3767 vmx->host_idt_base = dt.address;
a3a8ff8e 3768
453eafbe 3769 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3770
3771 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3772 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3773 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3774 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3775
3776 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3777 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3778 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3779 }
5a5e8a15 3780
c73da3fc 3781 if (cpu_has_load_ia32_efer())
5a5e8a15 3782 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3783}
3784
97b7ead3 3785void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3786{
3787 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3788 if (enable_ept)
3789 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3790 if (is_guest_mode(&vmx->vcpu))
3791 vmx->vcpu.arch.cr4_guest_owned_bits &=
3792 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3793 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3794}
3795
01e439be
YZ		 3796static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3797{
3798 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3799
d62caabb 3800 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3801 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3802
3803 if (!enable_vnmi)
3804 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3805
64672c95
YJ		 3806 /* Enable the preemption timer dynamically */
3807 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 3808 return pin_based_exec_ctrl;
3809}
3810
d62caabb
AS		 3811static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3812{
3813 struct vcpu_vmx *vmx = to_vmx(vcpu);
3814
3815 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3816 if (cpu_has_secondary_exec_ctrls()) {
3817 if (kvm_vcpu_apicv_active(vcpu))
3818 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
3819 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3820 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3821 else
3822 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
3823 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3824 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3825 }
3826
3827 if (cpu_has_vmx_msr_bitmap())
904e14fb 3828 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3829}
3830
89b0c9f5
SC		 3831u32 vmx_exec_control(struct vcpu_vmx *vmx)
3832{
3833 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3834
3835 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3836 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3837
3838 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3839 exec_control &= ~CPU_BASED_TPR_SHADOW;
3840#ifdef CONFIG_X86_64
3841 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3842 CPU_BASED_CR8_LOAD_EXITING;
3843#endif
3844 }
3845 if (!enable_ept)
3846 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3847 CPU_BASED_CR3_LOAD_EXITING |
3848 CPU_BASED_INVLPG_EXITING;
3849 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3850 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3851 CPU_BASED_MONITOR_EXITING);
3852 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3853 exec_control &= ~CPU_BASED_HLT_EXITING;
3854 return exec_control;
3855}
3856
3857
80154d77 3858static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 3859{
80154d77
PB		 3860 struct kvm_vcpu *vcpu = &vmx->vcpu;
3861
bf8179a0 3862 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 3863
f99e3daf
CP		 3864 if (pt_mode == PT_MODE_SYSTEM)
3865 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 3866 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 3867 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3868 if (vmx->vpid == 0)
3869 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3870 if (!enable_ept) {
3871 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3872 enable_unrestricted_guest = 0;
3873 }
3874 if (!enable_unrestricted_guest)
3875 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 3876 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 3877 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 3878 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 3879 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3880 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 3881 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 3882
3883 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3884 * in vmx_set_cr4. */
3885 exec_control &= ~SECONDARY_EXEC_DESC;
3886
abc4fc58
AG		 3887 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3888 (handle_vmptrld).
3889 We can NOT enable shadow_vmcs here because we don't have yet
3890 a current VMCS12
3891 */
3892 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 3893
3894 if (!enable_pml)
3895 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 3896
3db13480
PB		 3897 if (vmx_xsaves_supported()) {
3898 /* Exposing XSAVES only when XSAVE is exposed */
3899 bool xsaves_enabled =
3900 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3901 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3902
3903 if (!xsaves_enabled)
3904 exec_control &= ~SECONDARY_EXEC_XSAVES;
3905
3906 if (nested) {
3907 if (xsaves_enabled)
6677f3da 3908 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 3909 SECONDARY_EXEC_XSAVES;
3910 else
6677f3da 3911 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 3912 ~SECONDARY_EXEC_XSAVES;
3913 }
3914 }
3915
80154d77
PB		 3916 if (vmx_rdtscp_supported()) {
3917 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3918 if (!rdtscp_enabled)
3919 exec_control &= ~SECONDARY_EXEC_RDTSCP;
3920
3921 if (nested) {
3922 if (rdtscp_enabled)
6677f3da 3923 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3924 SECONDARY_EXEC_RDTSCP;
3925 else
6677f3da 3926 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3927 ~SECONDARY_EXEC_RDTSCP;
3928 }
3929 }
3930
3931 if (vmx_invpcid_supported()) {
3932 /* Exposing INVPCID only when PCID is exposed */
3933 bool invpcid_enabled =
3934 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
3935 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
3936
3937 if (!invpcid_enabled) {
3938 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3939 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
3940 }
3941
3942 if (nested) {
3943 if (invpcid_enabled)
6677f3da 3944 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3945 SECONDARY_EXEC_ENABLE_INVPCID;
3946 else
6677f3da 3947 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3948 ~SECONDARY_EXEC_ENABLE_INVPCID;
3949 }
3950 }
3951
45ec368c
JM		 3952 if (vmx_rdrand_supported()) {
3953 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
3954 if (rdrand_enabled)
736fdf72 3955 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3956
3957 if (nested) {
3958 if (rdrand_enabled)
6677f3da 3959 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 3960 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 3961 else
6677f3da 3962 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 3963 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3964 }
3965 }
3966
75f4fc8d
JM		 3967 if (vmx_rdseed_supported()) {
3968 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
3969 if (rdseed_enabled)
736fdf72 3970 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 3971
3972 if (nested) {
3973 if (rdseed_enabled)
6677f3da 3974 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 3975 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 3976 else
6677f3da 3977 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 3978 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 3979 }
3980 }
3981
80154d77 3982 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 3983}
3984
ce88decf
XG		 3985static void ept_set_mmio_spte_mask(void)
3986{
3987 /*
3988 * EPT Misconfigurations can be generated if the value of bits 2:0
3989 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 3990 */
dcdca5fe
PF		 3991 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
3992 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG		 3993}
3994
f53cd63c 3995#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 3996
944c3464
SC		 3997/*
3998 * Sets up the vmcs for emulated real mode.
3999 */
4000static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4001{
4002 int i;
4003
4004 if (nested)
4005 nested_vmx_vcpu_setup();
4006
25c5f225 4007 if (cpu_has_vmx_msr_bitmap())
904e14fb 4008 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4009
6aa8b732
AK		 4010 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4011
6aa8b732 4012 /* Control */
01e439be 4013 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 4014 vmx->hv_deadline_tsc = -1;
6e5d865c 4015
bf8179a0 4016 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4017
dfa169bb 4018 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4019 vmx_compute_secondary_exec_control(vmx);
bf8179a0 4020 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
80154d77 4021 vmx->secondary_exec_control);
dfa169bb 4022 }
f78e0e2e 4023
d62caabb 4024 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4025 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4026 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4027 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4028 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4029
4030 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4031
0bcf261c 4032 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4033 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4034 }
4035
b31c114b 4036 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4037 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4038 vmx->ple_window = ple_window;
4039 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4040 }
4041
c3707958
XG		 4042 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4043 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4044 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4045
9581d442
AK		 4046 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4047 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4048 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4049 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4050 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4051
2a499e49
BD		 4052 if (cpu_has_vmx_vmfunc())
4053 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4054
2cc51560
ED		 4055 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4056 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4057 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4058 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4059 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4060
74545705
RK		 4061 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4062 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4063
03916db9 4064 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4065 u32 index = vmx_msr_index[i];
4066 u32 data_low, data_high;
a2fa3e9f 4067 int j = vmx->nmsrs;
6aa8b732
AK		 4068
4069 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4070 continue;
432bd6cb
AK		 4071 if (wrmsr_safe(index, data_low, data_high) < 0)
4072 continue;
26bb0981
AK		 4073 vmx->guest_msrs[j].index = i;
4074 vmx->guest_msrs[j].data = 0;
d5696725 4075 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4076 ++vmx->nmsrs;
6aa8b732 4077 }
6aa8b732 4078
c73da3fc 4079 vm_exit_controls_init(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4080
4081 /* 22.2.1, 20.8.1 */
c73da3fc 4082 vm_entry_controls_init(vmx, vmx_vmentry_ctrl());
1c3d14fe 4083
bd7e5b08
PB		 4084 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4085 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4086
bf8179a0 4087 set_cr4_guest_host_mask(vmx);
e00c8cf2 4088
f53cd63c
WL		 4089 if (vmx_xsaves_supported())
4090 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4091
4e59516a 4092 if (enable_pml) {
4e59516a
PF		 4093 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4094 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4095 }
0b665d30
SC		 4096
4097 if (cpu_has_vmx_encls_vmexit())
4098 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4099
4100 if (pt_mode == PT_MODE_HOST_GUEST) {
4101 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4102 /* Bit[6~0] are forced to 1, writes are ignored. */
4103 vmx->pt_desc.guest.output_mask = 0x7F;
4104 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4105 }
e00c8cf2
AK		 4106}
4107
d28bc9dd 4108static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4109{
4110 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4111 struct msr_data apic_base_msr;
d28bc9dd 4112 u64 cr0;
e00c8cf2 4113
7ffd92c5 4114 vmx->rmode.vm86_active = 0;
d28b387f 4115 vmx->spec_ctrl = 0;
e00c8cf2 4116
518e7b94 4117 vcpu->arch.microcode_version = 0x100000000ULL;
ad312c7c 4118 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4119 kvm_set_cr8(vcpu, 0);
4120
4121 if (!init_event) {
4122 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4123 MSR_IA32_APICBASE_ENABLE;
4124 if (kvm_vcpu_is_reset_bsp(vcpu))
4125 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4126 apic_base_msr.host_initiated = true;
4127 kvm_set_apic_base(vcpu, &apic_base_msr);
4128 }
e00c8cf2 4129
2fb92db1
AK		 4130 vmx_segment_cache_clear(vmx);
4131
5706be0d 4132 seg_setup(VCPU_SREG_CS);
66450a21 4133 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4134 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4135
4136 seg_setup(VCPU_SREG_DS);
4137 seg_setup(VCPU_SREG_ES);
4138 seg_setup(VCPU_SREG_FS);
4139 seg_setup(VCPU_SREG_GS);
4140 seg_setup(VCPU_SREG_SS);
4141
4142 vmcs_write16(GUEST_TR_SELECTOR, 0);
4143 vmcs_writel(GUEST_TR_BASE, 0);
4144 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4145 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4146
4147 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4148 vmcs_writel(GUEST_LDTR_BASE, 0);
4149 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4150 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4151
d28bc9dd
NA		 4152 if (!init_event) {
4153 vmcs_write32(GUEST_SYSENTER_CS, 0);
4154 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4155 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4156 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4157 }
e00c8cf2 4158
c37c2873 4159 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4160 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4161
e00c8cf2
AK		 4162 vmcs_writel(GUEST_GDTR_BASE, 0);
4163 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4164
4165 vmcs_writel(GUEST_IDTR_BASE, 0);
4166 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4167
443381a8 4168 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4169 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4170 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4171 if (kvm_mpx_supported())
4172 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4173
e00c8cf2
AK		 4174 setup_msrs(vmx);
4175
6aa8b732
AK		 4176 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4177
d28bc9dd 4178 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4179 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4180 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4181 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4182 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4183 vmcs_write32(TPR_THRESHOLD, 0);
4184 }
4185
a73896cb 4186 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4187
2384d2b3
SY		 4188 if (vmx->vpid != 0)
4189 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4190
d28bc9dd 4191 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4192 vmx->vcpu.arch.cr0 = cr0;
f2463247 4193 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4194 vmx_set_cr4(vcpu, 0);
5690891b 4195 vmx_set_efer(vcpu, 0);
bd7e5b08 4196
d28bc9dd 4197 update_exception_bitmap(vcpu);
6aa8b732 4198
dd5f5341 4199 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4200 if (init_event)
4201 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4202}
4203
55d2375e 4204static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4205{
47c0152e
PB		 4206 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
4207 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK		 4208}
4209
c9a7953f 4210static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4211{
d02fcf50 4212 if (!enable_vnmi ||
8a1b4392 4213 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4214 enable_irq_window(vcpu);
4215 return;
4216 }
3b86cd99 4217
47c0152e
PB		 4218 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
4219 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK		 4220}
4221
66fd3f7f 4222static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4223{
9c8cba37 4224 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4225 uint32_t intr;
4226 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4227
229456fc 4228 trace_kvm_inj_virq(irq);
2714d1d3 4229
fa89a817 4230 ++vcpu->stat.irq_injections;
7ffd92c5 4231 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4232 int inc_eip = 0;
4233 if (vcpu->arch.interrupt.soft)
4234 inc_eip = vcpu->arch.event_exit_inst_len;
4235 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4236 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4237 return;
4238 }
66fd3f7f
GN		 4239 intr = irq | INTR_INFO_VALID_MASK;
4240 if (vcpu->arch.interrupt.soft) {
4241 intr |= INTR_TYPE_SOFT_INTR;
4242 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4243 vmx->vcpu.arch.event_exit_inst_len);
4244 } else
4245 intr |= INTR_TYPE_EXT_INTR;
4246 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4247
4248 vmx_clear_hlt(vcpu);
85f455f7
ED		 4249}
4250
f08864b4
SY		 4251static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4252{
66a5a347
JK		 4253 struct vcpu_vmx *vmx = to_vmx(vcpu);
4254
d02fcf50 4255 if (!enable_vnmi) {
8a1b4392
PB		 4256 /*
4257 * Tracking the NMI-blocked state in software is built upon
4258 * finding the next open IRQ window. This, in turn, depends on
4259 * well-behaving guests: They have to keep IRQs disabled at
4260 * least as long as the NMI handler runs. Otherwise we may
4261 * cause NMI nesting, maybe breaking the guest. But as this is
4262 * highly unlikely, we can live with the residual risk.
4263 */
4264 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4265 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4266 }
4267
4c4a6f79
PB		 4268 ++vcpu->stat.nmi_injections;
4269 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4270
7ffd92c5 4271 if (vmx->rmode.vm86_active) {
71f9833b 4272 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4273 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4274 return;
4275 }
c5a6d5f7 4276
f08864b4
SY		 4277 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4278 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4279
4280 vmx_clear_hlt(vcpu);
f08864b4
SY		 4281}
4282
97b7ead3 4283bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4284{
4c4a6f79
PB		 4285 struct vcpu_vmx *vmx = to_vmx(vcpu);
4286 bool masked;
4287
d02fcf50 4288 if (!enable_vnmi)
8a1b4392 4289 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4290 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4291 return false;
4c4a6f79
PB		 4292 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4293 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4294 return masked;
3cfc3092
JK		 4295}
4296
97b7ead3 4297void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4298{
4299 struct vcpu_vmx *vmx = to_vmx(vcpu);
4300
d02fcf50 4301 if (!enable_vnmi) {
8a1b4392
PB		 4302 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4303 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4304 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4305 }
4306 } else {
4307 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4308 if (masked)
4309 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4310 GUEST_INTR_STATE_NMI);
4311 else
4312 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4313 GUEST_INTR_STATE_NMI);
4314 }
3cfc3092
JK		 4315}
4316
2505dc9f
JK		 4317static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4318{
b6b8a145
JK		 4319 if (to_vmx(vcpu)->nested.nested_run_pending)
4320 return 0;
ea8ceb83 4321
d02fcf50 4322 if (!enable_vnmi &&
8a1b4392
PB		 4323 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4324 return 0;
4325
2505dc9f
JK		 4326 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4327 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4328 | GUEST_INTR_STATE_NMI));
4329}
4330
78646121
GN		 4331static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4332{
b6b8a145
JK		 4333 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4334 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4335 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4336 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4337}
4338
cbc94022
IE		 4339static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4340{
4341 int ret;
cbc94022 4342
f7eaeb0a
SC		 4343 if (enable_unrestricted_guest)
4344 return 0;
4345
1d8007bd
PB		 4346 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4347 PAGE_SIZE * 3);
cbc94022
IE		 4348 if (ret)
4349 return ret;
40bbb9d0 4350 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4351 return init_rmode_tss(kvm);
cbc94022
IE		 4352}
4353
2ac52ab8
SC		 4354static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4355{
40bbb9d0 4356 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4357 return 0;
4358}
4359
0ca1b4f4 4360static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4361{
77ab6db0 4362 switch (vec) {
77ab6db0 4363 case BP_VECTOR:
c573cd22
JK		 4364 /*
4365 * Update instruction length as we may reinject the exception
4366 * from user space while in guest debugging mode.
4367 */
4368 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4369 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4370 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4371 return false;
4372 /* fall through */
4373 case DB_VECTOR:
4374 if (vcpu->guest_debug &
4375 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4376 return false;
d0bfb940
JK		 4377 /* fall through */
4378 case DE_VECTOR:
77ab6db0
JK		 4379 case OF_VECTOR:
4380 case BR_VECTOR:
4381 case UD_VECTOR:
4382 case DF_VECTOR:
4383 case SS_VECTOR:
4384 case GP_VECTOR:
4385 case MF_VECTOR:
0ca1b4f4
GN		 4386 return true;
4387 break;
77ab6db0 4388 }
0ca1b4f4
GN		 4389 return false;
4390}
4391
4392static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4393 int vec, u32 err_code)
4394{
4395 /*
4396 * Instruction with address size override prefix opcode 0x67
4397 * Cause the #SS fault with 0 error code in VM86 mode.
4398 */
4399 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
0ce97a2b 4400 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
0ca1b4f4
GN		 4401 if (vcpu->arch.halt_request) {
4402 vcpu->arch.halt_request = 0;
5cb56059 4403 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4404 }
4405 return 1;
4406 }
4407 return 0;
4408 }
4409
4410 /*
4411 * Forward all other exceptions that are valid in real mode.
4412 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4413 * the required debugging infrastructure rework.
4414 */
4415 kvm_queue_exception(vcpu, vec);
4416 return 1;
6aa8b732
AK		 4417}
4418
a0861c02
AK		 4419/*
4420 * Trigger machine check on the host. We assume all the MSRs are already set up
4421 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4422 * We pass a fake environment to the machine check handler because we want
4423 * the guest to be always treated like user space, no matter what context
4424 * it used internally.
4425 */
4426static void kvm_machine_check(void)
4427{
4428#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4429 struct pt_regs regs = {
4430 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4431 .flags = X86_EFLAGS_IF,
4432 };
4433
4434 do_machine_check(&regs, 0);
4435#endif
4436}
4437
851ba692 4438static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4439{
4440 /* already handled by vcpu_run */
4441 return 1;
4442}
4443
851ba692 4444static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4445{
1155f76a 4446 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4447 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4448 u32 intr_info, ex_no, error_code;
42dbaa5a 4449 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4450 u32 vect_info;
4451 enum emulation_result er;
4452
1155f76a 4453 vect_info = vmx->idt_vectoring_info;
88786475 4454 intr_info = vmx->exit_intr_info;
6aa8b732 4455
a0861c02 4456 if (is_machine_check(intr_info))
851ba692 4457 return handle_machine_check(vcpu);
a0861c02 4458
ef85b673 4459 if (is_nmi(intr_info))
1b6269db 4460 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 4461
082d06ed
WL		 4462 if (is_invalid_opcode(intr_info))
4463 return handle_ud(vcpu);
7aa81cc0 4464
6aa8b732 4465 error_code = 0;
2e11384c 4466 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4467 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4468
9e869480
LA		 4469 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4470 WARN_ON_ONCE(!enable_vmware_backdoor);
0ce97a2b 4471 er = kvm_emulate_instruction(vcpu,
9e869480
LA		 4472 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
4473 if (er == EMULATE_USER_EXIT)
4474 return 0;
4475 else if (er != EMULATE_DONE)
4476 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4477 return 1;
4478 }
4479
bf4ca23e
XG		 4480 /*
4481 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4482 * MMIO, it is better to report an internal error.
4483 * See the comments in vmx_handle_exit.
4484 */
4485 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4486 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4487 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4488 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4489 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4490 vcpu->run->internal.data[0] = vect_info;
4491 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4492 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4493 return 0;
4494 }
4495
6aa8b732
AK		 4496 if (is_page_fault(intr_info)) {
4497 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4498 /* EPT won't cause page fault directly */
4499 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4500 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4501 }
4502
d0bfb940 4503 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4504
4505 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4506 return handle_rmode_exception(vcpu, ex_no, error_code);
4507
42dbaa5a 4508 switch (ex_no) {
54a20552
EN		 4509 case AC_VECTOR:
4510 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4511 return 1;
42dbaa5a
JK		 4512 case DB_VECTOR:
4513 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4514 if (!(vcpu->guest_debug &
4515 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4516 vcpu->arch.dr6 &= ~15;
6f43ed01 4517 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4518 if (is_icebp(intr_info))
fd2a445a
HD		 4519 skip_emulated_instruction(vcpu);
4520
42dbaa5a
JK		 4521 kvm_queue_exception(vcpu, DB_VECTOR);
4522 return 1;
4523 }
4524 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4525 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4526 /* fall through */
4527 case BP_VECTOR:
c573cd22
JK		 4528 /*
4529 * Update instruction length as we may reinject #BP from
4530 * user space while in guest debugging mode. Reading it for
4531 * #DB as well causes no harm, it is not used in that case.
4532 */
4533 vmx->vcpu.arch.event_exit_inst_len =
4534 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4535 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4536 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4537 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4538 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4539 break;
4540 default:
d0bfb940
JK		 4541 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4542 kvm_run->ex.exception = ex_no;
4543 kvm_run->ex.error_code = error_code;
42dbaa5a 4544 break;
6aa8b732 4545 }
6aa8b732
AK		 4546 return 0;
4547}
4548
851ba692 4549static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4550{
1165f5fe 4551 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4552 return 1;
4553}
4554
851ba692 4555static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4556{
851ba692 4557 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4558 vcpu->mmio_needed = 0;
988ad74f
AK		 4559 return 0;
4560}
6aa8b732 4561
851ba692 4562static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4563{
bfdaab09 4564 unsigned long exit_qualification;
dca7f128 4565 int size, in, string;
039576c0 4566 unsigned port;
6aa8b732 4567
bfdaab09 4568 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4569 string = (exit_qualification & 16) != 0;
e70669ab 4570
cf8f70bf 4571 ++vcpu->stat.io_exits;
e70669ab 4572
432baf60 4573 if (string)
0ce97a2b 4574 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4575
cf8f70bf
GN		 4576 port = exit_qualification >> 16;
4577 size = (exit_qualification & 7) + 1;
432baf60 4578 in = (exit_qualification & 8) != 0;
cf8f70bf 4579
dca7f128 4580 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4581}
4582
102d8325
IM		 4583static void
4584vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4585{
4586 /*
4587 * Patch in the VMCALL instruction:
4588 */
4589 hypercall[0] = 0x0f;
4590 hypercall[1] = 0x01;
4591 hypercall[2] = 0xc1;
102d8325
IM		 4592}
4593
0fa06071 4594/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4595static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4596{
eeadf9e7 4597 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4598 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4599 unsigned long orig_val = val;
4600
eeadf9e7
NHE		 4601 /*
4602 * We get here when L2 changed cr0 in a way that did not change
4603 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4604 * but did change L0 shadowed bits. So we first calculate the
4605 * effective cr0 value that L1 would like to write into the
4606 * hardware. It consists of the L2-owned bits from the new
4607 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4608 */
1a0d74e6
JK		 4609 val = (val & ~vmcs12->cr0_guest_host_mask) |
4610 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4611
3899152c 4612 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4613 return 1;
1a0d74e6
JK		 4614
4615 if (kvm_set_cr0(vcpu, val))
4616 return 1;
4617 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4618 return 0;
1a0d74e6
JK		 4619 } else {
4620 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4621 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4622 return 1;
3899152c 4623
eeadf9e7 4624 return kvm_set_cr0(vcpu, val);
1a0d74e6 4625 }
eeadf9e7
NHE		 4626}
4627
4628static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4629{
4630 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4631 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4632 unsigned long orig_val = val;
4633
4634 /* analogously to handle_set_cr0 */
4635 val = (val & ~vmcs12->cr4_guest_host_mask) |
4636 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4637 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4638 return 1;
1a0d74e6 4639 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4640 return 0;
4641 } else
4642 return kvm_set_cr4(vcpu, val);
4643}
4644
0367f205
PB		 4645static int handle_desc(struct kvm_vcpu *vcpu)
4646{
4647 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
0ce97a2b 4648 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
0367f205
PB		 4649}
4650
851ba692 4651static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4652{
229456fc 4653 unsigned long exit_qualification, val;
6aa8b732
AK		 4654 int cr;
4655 int reg;
49a9b07e 4656 int err;
6affcbed 4657 int ret;
6aa8b732 4658
bfdaab09 4659 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4660 cr = exit_qualification & 15;
4661 reg = (exit_qualification >> 8) & 15;
4662 switch ((exit_qualification >> 4) & 3) {
4663 case 0: /* mov to cr */
1e32c079 4664 val = kvm_register_readl(vcpu, reg);
229456fc 4665 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4666 switch (cr) {
4667 case 0:
eeadf9e7 4668 err = handle_set_cr0(vcpu, val);
6affcbed 4669 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4670 case 3:
e1de91cc 4671 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4672 err = kvm_set_cr3(vcpu, val);
6affcbed 4673 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4674 case 4:
eeadf9e7 4675 err = handle_set_cr4(vcpu, val);
6affcbed 4676 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4677 case 8: {
4678 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4679 u8 cr8 = (u8)val;
eea1cff9 4680 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4681 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4682 if (lapic_in_kernel(vcpu))
6affcbed 4683 return ret;
0a5fff19 4684 if (cr8_prev <= cr8)
6affcbed
KH		 4685 return ret;
4686 /*
4687 * TODO: we might be squashing a
4688 * KVM_GUESTDBG_SINGLESTEP-triggered
4689 * KVM_EXIT_DEBUG here.
4690 */
851ba692 4691 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4692 return 0;
4693 }
4b8073e4 4694 }
6aa8b732 4695 break;
25c4c276 4696 case 2: /* clts */
bd7e5b08
PB		 4697 WARN_ONCE(1, "Guest should always own CR0.TS");
4698 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4699 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4700 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4701 case 1: /*mov from cr*/
4702 switch (cr) {
4703 case 3:
e1de91cc 4704 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4705 val = kvm_read_cr3(vcpu);
4706 kvm_register_write(vcpu, reg, val);
4707 trace_kvm_cr_read(cr, val);
6affcbed 4708 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4709 case 8:
229456fc
MT		 4710 val = kvm_get_cr8(vcpu);
4711 kvm_register_write(vcpu, reg, val);
4712 trace_kvm_cr_read(cr, val);
6affcbed 4713 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4714 }
4715 break;
4716 case 3: /* lmsw */
a1f83a74 4717 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4718 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4719 kvm_lmsw(vcpu, val);
6aa8b732 4720
6affcbed 4721 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4722 default:
4723 break;
4724 }
851ba692 4725 vcpu->run->exit_reason = 0;
a737f256 4726 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4727 (int)(exit_qualification >> 4) & 3, cr);
4728 return 0;
4729}
4730
851ba692 4731static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4732{
bfdaab09 4733 unsigned long exit_qualification;
16f8a6f9
NA		 4734 int dr, dr7, reg;
4735
4736 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4737 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4738
4739 /* First, if DR does not exist, trigger UD */
4740 if (!kvm_require_dr(vcpu, dr))
4741 return 1;
6aa8b732 4742
f2483415 4743 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4744 if (!kvm_require_cpl(vcpu, 0))
4745 return 1;
16f8a6f9
NA		 4746 dr7 = vmcs_readl(GUEST_DR7);
4747 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4748 /*
4749 * As the vm-exit takes precedence over the debug trap, we
4750 * need to emulate the latter, either for the host or the
4751 * guest debugging itself.
4752 */
4753 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4754 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4755 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4756 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4757 vcpu->run->debug.arch.exception = DB_VECTOR;
4758 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4759 return 0;
4760 } else {
7305eb5d 4761 vcpu->arch.dr6 &= ~15;
6f43ed01 4762 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4763 kvm_queue_exception(vcpu, DB_VECTOR);
4764 return 1;
4765 }
4766 }
4767
81908bf4 4768 if (vcpu->guest_debug == 0) {
8f22372f
PB		 4769 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4770 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4771
4772 /*
4773 * No more DR vmexits; force a reload of the debug registers
4774 * and reenter on this instruction. The next vmexit will
4775 * retrieve the full state of the debug registers.
4776 */
4777 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4778 return 1;
4779 }
4780
42dbaa5a
JK		 4781 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4782 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4783 unsigned long val;
4c4d563b
JK		 4784
4785 if (kvm_get_dr(vcpu, dr, &val))
4786 return 1;
4787 kvm_register_write(vcpu, reg, val);
020df079 4788 } else
5777392e 4789 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4790 return 1;
4791
6affcbed 4792 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4793}
4794
73aaf249
JK		 4795static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4796{
4797 return vcpu->arch.dr6;
4798}
4799
4800static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4801{
4802}
4803
81908bf4
PB		 4804static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4805{
81908bf4
PB		 4806 get_debugreg(vcpu->arch.db[0], 0);
4807 get_debugreg(vcpu->arch.db[1], 1);
4808 get_debugreg(vcpu->arch.db[2], 2);
4809 get_debugreg(vcpu->arch.db[3], 3);
4810 get_debugreg(vcpu->arch.dr6, 6);
4811 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4812
4813 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 4814 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4815}
4816
020df079
GN		 4817static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4818{
4819 vmcs_writel(GUEST_DR7, val);
4820}
4821
851ba692 4822static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4823{
6a908b62 4824 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK		 4825}
4826
851ba692 4827static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4828{
ad312c7c 4829 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 4830 struct msr_data msr_info;
6aa8b732 4831
609e36d3
PB		 4832 msr_info.index = ecx;
4833 msr_info.host_initiated = false;
4834 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 4835 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4836 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4837 return 1;
4838 }
4839
609e36d3 4840 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 4841
6aa8b732 4842 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 4843 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
4844 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 4845 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4846}
4847
851ba692 4848static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4849{
8fe8ab46 4850 struct msr_data msr;
ad312c7c
ZX		 4851 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4852 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4853 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4854
8fe8ab46
WA		 4855 msr.data = data;
4856 msr.index = ecx;
4857 msr.host_initiated = false;
854e8bb1 4858 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 4859 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4860 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4861 return 1;
4862 }
4863
59200273 4864 trace_kvm_msr_write(ecx, data);
6affcbed 4865 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4866}
4867
851ba692 4868static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4869{
eb90f341 4870 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4871 return 1;
4872}
4873
851ba692 4874static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4875{
47c0152e
PB		 4876 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4877 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 4878
3842d135
AK		 4879 kvm_make_request(KVM_REQ_EVENT, vcpu);
4880
a26bf12a 4881 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4882 return 1;
4883}
4884
851ba692 4885static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 4886{
d3bef15f 4887 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4888}
4889
851ba692 4890static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4891{
0d9c055e 4892 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 4893}
4894
ec25d5e6
GN		 4895static int handle_invd(struct kvm_vcpu *vcpu)
4896{
0ce97a2b 4897 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4898}
4899
851ba692 4900static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4901{
f9c617f6 4902 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4903
4904 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 4905 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 4906}
4907
fee84b07
AK		 4908static int handle_rdpmc(struct kvm_vcpu *vcpu)
4909{
4910 int err;
4911
4912 err = kvm_rdpmc(vcpu);
6affcbed 4913 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 4914}
4915
851ba692 4916static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 4917{
6affcbed 4918 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4919}
4920
2acf923e
DC		 4921static int handle_xsetbv(struct kvm_vcpu *vcpu)
4922{
4923 u64 new_bv = kvm_read_edx_eax(vcpu);
4924 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4925
4926 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 4927 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 4928 return 1;
4929}
4930
f53cd63c
WL		 4931static int handle_xsaves(struct kvm_vcpu *vcpu)
4932{
6affcbed 4933 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4934 WARN(1, "this should never happen\n");
4935 return 1;
4936}
4937
4938static int handle_xrstors(struct kvm_vcpu *vcpu)
4939{
6affcbed 4940 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4941 WARN(1, "this should never happen\n");
4942 return 1;
4943}
4944
851ba692 4945static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4946{
58fbbf26
KT		 4947 if (likely(fasteoi)) {
4948 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4949 int access_type, offset;
4950
4951 access_type = exit_qualification & APIC_ACCESS_TYPE;
4952 offset = exit_qualification & APIC_ACCESS_OFFSET;
4953 /*
4954 * Sane guest uses MOV to write EOI, with written value
4955 * not cared. So make a short-circuit here by avoiding
4956 * heavy instruction emulation.
4957 */
4958 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4959 (offset == APIC_EOI)) {
4960 kvm_lapic_set_eoi(vcpu);
6affcbed 4961 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 4962 }
4963 }
0ce97a2b 4964 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4965}
4966
c7c9c56c
YZ		 4967static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4968{
4969 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4970 int vector = exit_qualification & 0xff;
4971
4972 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4973 kvm_apic_set_eoi_accelerated(vcpu, vector);
4974 return 1;
4975}
4976
83d4c286
YZ		 4977static int handle_apic_write(struct kvm_vcpu *vcpu)
4978{
4979 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4980 u32 offset = exit_qualification & 0xfff;
4981
4982 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4983 kvm_apic_write_nodecode(vcpu, offset);
4984 return 1;
4985}
4986
851ba692 4987static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4988{
60637aac 4989 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4990 unsigned long exit_qualification;
e269fb21
JK		 4991 bool has_error_code = false;
4992 u32 error_code = 0;
37817f29 4993 u16 tss_selector;
7f3d35fd 4994 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4995
4996 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4997 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4998 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4999
5000 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5001
5002 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5003 if (reason == TASK_SWITCH_GATE && idt_v) {
5004 switch (type) {
5005 case INTR_TYPE_NMI_INTR:
5006 vcpu->arch.nmi_injected = false;
654f06fc 5007 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5008 break;
5009 case INTR_TYPE_EXT_INTR:
66fd3f7f 5010 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5011 kvm_clear_interrupt_queue(vcpu);
5012 break;
5013 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5014 if (vmx->idt_vectoring_info &
5015 VECTORING_INFO_DELIVER_CODE_MASK) {
5016 has_error_code = true;
5017 error_code =
5018 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5019 }
5020 /* fall through */
64a7ec06
GN		 5021 case INTR_TYPE_SOFT_EXCEPTION:
5022 kvm_clear_exception_queue(vcpu);
5023 break;
5024 default:
5025 break;
5026 }
60637aac 5027 }
37817f29
IE		 5028 tss_selector = exit_qualification;
5029
64a7ec06
GN		 5030 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5031 type != INTR_TYPE_EXT_INTR &&
5032 type != INTR_TYPE_NMI_INTR))
5033 skip_emulated_instruction(vcpu);
5034
7f3d35fd
KW		 5035 if (kvm_task_switch(vcpu, tss_selector,
5036 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5037 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5038 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5039 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5040 vcpu->run->internal.ndata = 0;
42dbaa5a 5041 return 0;
acb54517 5042 }
42dbaa5a 5043
42dbaa5a
JK		 5044 /*
5045 * TODO: What about debug traps on tss switch?
5046 * Are we supposed to inject them and update dr6?
5047 */
5048
5049 return 1;
37817f29
IE		 5050}
5051
851ba692 5052static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5053{
f9c617f6 5054 unsigned long exit_qualification;
1439442c 5055 gpa_t gpa;
eebed243 5056 u64 error_code;
1439442c 5057
f9c617f6 5058 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5059
0be9c7a8
GN		 5060 /*
5061 * EPT violation happened while executing iret from NMI,
5062 * "blocked by NMI" bit has to be set before next VM entry.
5063 * There are errata that may cause this bit to not be set:
5064 * AAK134, BY25.
5065 */
bcd1c294 5066 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5067 enable_vnmi &&
bcd1c294 5068 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5069 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5070
1439442c 5071 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5072 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5073
27959a44 5074 /* Is it a read fault? */
ab22a473 5075 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5076 ? PFERR_USER_MASK : 0;
5077 /* Is it a write fault? */
ab22a473 5078 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5079 ? PFERR_WRITE_MASK : 0;
5080 /* Is it a fetch fault? */
ab22a473 5081 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5082 ? PFERR_FETCH_MASK : 0;
5083 /* ept page table entry is present? */
5084 error_code |= (exit_qualification &
5085 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5086 EPT_VIOLATION_EXECUTABLE))
5087 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5088
eebed243
PB		 5089 error_code |= (exit_qualification & 0x100) != 0 ?
5090 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5091
25d92081 5092 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5093 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5094}
5095
851ba692 5096static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5097{
68f89400
MT		 5098 gpa_t gpa;
5099
9034e6e8
PB		 5100 /*
5101 * A nested guest cannot optimize MMIO vmexits, because we have an
5102 * nGPA here instead of the required GPA.
5103 */
68f89400 5104 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5105 if (!is_guest_mode(vcpu) &&
5106 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5107 trace_kvm_fast_mmio(gpa);
d391f120
VK		 5108 /*
5109 * Doing kvm_skip_emulated_instruction() depends on undefined
5110 * behavior: Intel's manual doesn't mandate
5111 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5112 * occurs and while on real hardware it was observed to be set,
5113 * other hypervisors (namely Hyper-V) don't set it, we end up
5114 * advancing IP with some random value. Disable fast mmio when
5115 * running nested and keep it for real hardware in hope that
5116 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5117 */
5118 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
5119 return kvm_skip_emulated_instruction(vcpu);
5120 else
0ce97a2b 5121 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
c4409905 5122 EMULATE_DONE;
68c3b4d1 5123 }
68f89400 5124
c75d0edc 5125 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5126}
5127
851ba692 5128static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5129{
d02fcf50 5130 WARN_ON_ONCE(!enable_vnmi);
47c0152e
PB		 5131 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5132 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 5133 ++vcpu->stat.nmi_window_exits;
3842d135 5134 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5135
5136 return 1;
5137}
5138
80ced186 5139static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5140{
8b3079a5
AK		 5141 struct vcpu_vmx *vmx = to_vmx(vcpu);
5142 enum emulation_result err = EMULATE_DONE;
80ced186 5143 int ret = 1;
49e9d557
AK		 5144 u32 cpu_exec_ctrl;
5145 bool intr_window_requested;
b8405c18 5146 unsigned count = 130;
49e9d557 5147
2bb8cafe
SC		 5148 /*
5149 * We should never reach the point where we are emulating L2
5150 * due to invalid guest state as that means we incorrectly
5151 * allowed a nested VMEntry with an invalid vmcs12.
5152 */
5153 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5154
49e9d557
AK		 5155 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5156 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5157
98eb2f8b 5158 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5159 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5160 return handle_interrupt_window(&vmx->vcpu);
5161
72875d8a 5162 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5163 return 1;
5164
0ce97a2b 5165 err = kvm_emulate_instruction(vcpu, 0);
ea953ef0 5166
ac0a48c3 5167 if (err == EMULATE_USER_EXIT) {
94452b9e 5168 ++vcpu->stat.mmio_exits;
80ced186
MG		 5169 ret = 0;
5170 goto out;
5171 }
1d5a4d9b 5172
add5ff7a
SC		 5173 if (err != EMULATE_DONE)
5174 goto emulation_error;
5175
5176 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5177 vcpu->arch.exception.pending)
5178 goto emulation_error;
ea953ef0 5179
8d76c49e
GN		 5180 if (vcpu->arch.halt_request) {
5181 vcpu->arch.halt_request = 0;
5cb56059 5182 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5183 goto out;
5184 }
5185
ea953ef0 5186 if (signal_pending(current))
80ced186 5187 goto out;
ea953ef0
MG		 5188 if (need_resched())
5189 schedule();
5190 }
5191
80ced186
MG		 5192out:
5193 return ret;
b4a2d31d 5194
add5ff7a
SC		 5195emulation_error:
5196 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5197 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5198 vcpu->run->internal.ndata = 0;
5199 return 0;
b4a2d31d
RK		 5200}
5201
5202static void grow_ple_window(struct kvm_vcpu *vcpu)
5203{
5204 struct vcpu_vmx *vmx = to_vmx(vcpu);
5205 int old = vmx->ple_window;
5206
c8e88717
BM		 5207 vmx->ple_window = __grow_ple_window(old, ple_window,
5208 ple_window_grow,
5209 ple_window_max);
b4a2d31d
RK		 5210
5211 if (vmx->ple_window != old)
5212 vmx->ple_window_dirty = true;
7b46268d
RK		 5213
5214 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5215}
5216
5217static void shrink_ple_window(struct kvm_vcpu *vcpu)
5218{
5219 struct vcpu_vmx *vmx = to_vmx(vcpu);
5220 int old = vmx->ple_window;
5221
c8e88717
BM		 5222 vmx->ple_window = __shrink_ple_window(old, ple_window,
5223 ple_window_shrink,
5224 ple_window);
b4a2d31d
RK		 5225
5226 if (vmx->ple_window != old)
5227 vmx->ple_window_dirty = true;
7b46268d
RK		 5228
5229 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5230}
5231
bf9f6ac8
FW		 5232/*
5233 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5234 */
5235static void wakeup_handler(void)
5236{
5237 struct kvm_vcpu *vcpu;
5238 int cpu = smp_processor_id();
5239
5240 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5241 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5242 blocked_vcpu_list) {
5243 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5244
5245 if (pi_test_on(pi_desc) == 1)
5246 kvm_vcpu_kick(vcpu);
5247 }
5248 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5249}
5250
e01bca2f 5251static void vmx_enable_tdp(void)
f160c7b7
JS		 5252{
5253 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5254 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5255 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5256 0ull, VMX_EPT_EXECUTABLE_MASK,
5257 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5258 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5259
5260 ept_set_mmio_spte_mask();
5261 kvm_enable_tdp();
5262}
5263
4b8d54f9
ZE		 5264/*
5265 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5266 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5267 */
9fb41ba8 5268static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5269{
b31c114b 5270 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5271 grow_ple_window(vcpu);
5272
de63ad4c
LM		 5273 /*
5274 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5275 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5276 * never set PAUSE_EXITING and just set PLE if supported,
5277 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5278 */
5279 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5280 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5281}
5282
87c00572 5283static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5284{
6affcbed 5285 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5286}
5287
87c00572
GS		 5288static int handle_mwait(struct kvm_vcpu *vcpu)
5289{
5290 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5291 return handle_nop(vcpu);
5292}
5293
45ec368c
JM		 5294static int handle_invalid_op(struct kvm_vcpu *vcpu)
5295{
5296 kvm_queue_exception(vcpu, UD_VECTOR);
5297 return 1;
5298}
5299
5f3d45e7
MD		 5300static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5301{
5302 return 1;
5303}
5304
87c00572
GS		 5305static int handle_monitor(struct kvm_vcpu *vcpu)
5306{
5307 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5308 return handle_nop(vcpu);
5309}
5310
55d2375e 5311static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5312{
55d2375e
SC		 5313 u32 vmx_instruction_info;
5314 unsigned long type;
5315 bool pcid_enabled;
5316 gva_t gva;
5317 struct x86_exception e;
5318 unsigned i;
5319 unsigned long roots_to_free = 0;
5320 struct {
5321 u64 pcid;
5322 u64 gla;
5323 } operand;
f9eb4af6 5324
55d2375e 5325 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5326 kvm_queue_exception(vcpu, UD_VECTOR);
5327 return 1;
5328 }
5329
55d2375e
SC		 5330 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5331 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5332
5333 if (type > 3) {
5334 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5335 return 1;
5336 }
5337
55d2375e
SC		 5338 /* According to the Intel instruction reference, the memory operand
5339 * is read even if it isn't needed (e.g., for type==all)
5340 */
3573e22c 5341 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
55d2375e 5342 vmx_instruction_info, false, &gva))
3573e22c
BD		 5343 return 1;
5344
55d2375e 5345 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5346 kvm_inject_page_fault(vcpu, &e);
5347 return 1;
5348 }
5349
55d2375e
SC		 5350 if (operand.pcid >> 12 != 0) {
5351 kvm_inject_gp(vcpu, 0);
5352 return 1;
abfc52c6 5353 }
e29acc55 5354
55d2375e 5355 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5356
55d2375e
SC		 5357 switch (type) {
5358 case INVPCID_TYPE_INDIV_ADDR:
5359 if ((!pcid_enabled && (operand.pcid != 0)) ||
5360 is_noncanonical_address(operand.gla, vcpu)) {
5361 kvm_inject_gp(vcpu, 0);
5362 return 1;
5363 }
5364 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5365 return kvm_skip_emulated_instruction(vcpu);
61ada748 5366
55d2375e
SC		 5367 case INVPCID_TYPE_SINGLE_CTXT:
5368 if (!pcid_enabled && (operand.pcid != 0)) {
5369 kvm_inject_gp(vcpu, 0);
5370 return 1;
5371 }
e29acc55 5372
55d2375e
SC		 5373 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5374 kvm_mmu_sync_roots(vcpu);
5375 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5376 }
e29acc55 5377
55d2375e
SC		 5378 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5379 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5380 == operand.pcid)
5381 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5382
55d2375e
SC		 5383 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5384 /*
5385 * If neither the current cr3 nor any of the prev_roots use the
5386 * given PCID, then nothing needs to be done here because a
5387 * resync will happen anyway before switching to any other CR3.
5388 */
e29acc55 5389
55d2375e 5390 return kvm_skip_emulated_instruction(vcpu);
61ada748 5391
55d2375e
SC		 5392 case INVPCID_TYPE_ALL_NON_GLOBAL:
5393 /*
5394 * Currently, KVM doesn't mark global entries in the shadow
5395 * page tables, so a non-global flush just degenerates to a
5396 * global flush. If needed, we could optimize this later by
5397 * keeping track of global entries in shadow page tables.
5398 */
e29acc55 5399
55d2375e
SC		 5400 /* fall-through */
5401 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5402 kvm_mmu_unload(vcpu);
5403 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5404
55d2375e
SC		 5405 default:
5406 BUG(); /* We have already checked above that type <= 3 */
5407 }
e29acc55
JM		 5408}
5409
55d2375e 5410static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5411{
55d2375e 5412 unsigned long exit_qualification;
b3897a49 5413
55d2375e 5414 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5415
55d2375e 5416 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5417
5418 /*
55d2375e
SC		 5419 * PML buffer FULL happened while executing iret from NMI,
5420 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5421 */
55d2375e
SC		 5422 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5423 enable_vnmi &&
5424 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5425 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5426 GUEST_INTR_STATE_NMI);
e49fcb8b 5427
55d2375e
SC		 5428 /*
5429 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5430 * here.., and there's no userspace involvement needed for PML.
5431 */
ec378aee
NHE		 5432 return 1;
5433}
5434
55d2375e 5435static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5436{
55d2375e
SC		 5437 if (!to_vmx(vcpu)->req_immediate_exit)
5438 kvm_lapic_expired_hv_timer(vcpu);
5439 return 1;
8ca44e88
DM		 5440}
5441
55d2375e
SC		 5442/*
5443 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5444 * are overwritten by nested_vmx_setup() when nested=1.
5445 */
5446static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5447{
55d2375e
SC		 5448 kvm_queue_exception(vcpu, UD_VECTOR);
5449 return 1;
b8bbab92
VK		 5450}
5451
55d2375e 5452static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5453{
55d2375e
SC		 5454 /*
5455 * SGX virtualization is not yet supported. There is no software
5456 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5457 * to prevent the guest from executing ENCLS.
5458 */
5459 kvm_queue_exception(vcpu, UD_VECTOR);
5460 return 1;
e7953d7f
AG		 5461}
5462
ec378aee 5463/*
55d2375e
SC		 5464 * The exit handlers return 1 if the exit was handled fully and guest execution
5465 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5466 * to be done to userspace and return 0.
ec378aee 5467 */
55d2375e
SC		 5468static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5469 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5470 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5471 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5472 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5473 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5474 [EXIT_REASON_CR_ACCESS] = handle_cr,
5475 [EXIT_REASON_DR_ACCESS] = handle_dr,
5476 [EXIT_REASON_CPUID] = handle_cpuid,
5477 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5478 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5479 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5480 [EXIT_REASON_HLT] = handle_halt,
5481 [EXIT_REASON_INVD] = handle_invd,
5482 [EXIT_REASON_INVLPG] = handle_invlpg,
5483 [EXIT_REASON_RDPMC] = handle_rdpmc,
5484 [EXIT_REASON_VMCALL] = handle_vmcall,
5485 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5486 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5487 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5488 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5489 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5490 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5491 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5492 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5493 [EXIT_REASON_VMON] = handle_vmx_instruction,
5494 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5495 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5496 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5497 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5498 [EXIT_REASON_WBINVD] = handle_wbinvd,
5499 [EXIT_REASON_XSETBV] = handle_xsetbv,
5500 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5501 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5502 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5503 [EXIT_REASON_LDTR_TR] = handle_desc,
5504 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5505 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5506 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5507 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5508 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5509 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5510 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5511 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5512 [EXIT_REASON_RDRAND] = handle_invalid_op,
5513 [EXIT_REASON_RDSEED] = handle_invalid_op,
5514 [EXIT_REASON_XSAVES] = handle_xsaves,
5515 [EXIT_REASON_XRSTORS] = handle_xrstors,
5516 [EXIT_REASON_PML_FULL] = handle_pml_full,
5517 [EXIT_REASON_INVPCID] = handle_invpcid,
5518 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5519 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5520 [EXIT_REASON_ENCLS] = handle_encls,
5521};
b8bbab92 5522
55d2375e
SC		 5523static const int kvm_vmx_max_exit_handlers =
5524 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5525
55d2375e 5526static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5527{
55d2375e
SC		 5528 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5529 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5530}
5531
55d2375e 5532static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5533{
55d2375e
SC		 5534 if (vmx->pml_pg) {
5535 __free_page(vmx->pml_pg);
5536 vmx->pml_pg = NULL;
b8bbab92 5537 }
27d6c865
NHE		 5538}
5539
55d2375e 5540static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5541{
55d2375e
SC		 5542 struct vcpu_vmx *vmx = to_vmx(vcpu);
5543 u64 *pml_buf;
5544 u16 pml_idx;
cd232ad0 5545
55d2375e 5546 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5547
55d2375e
SC		 5548 /* Do nothing if PML buffer is empty */
5549 if (pml_idx == (PML_ENTITY_NUM - 1))
5550 return;
cd232ad0 5551
55d2375e
SC		 5552 /* PML index always points to next available PML buffer entity */
5553 if (pml_idx >= PML_ENTITY_NUM)
5554 pml_idx = 0;
5555 else
5556 pml_idx++;
945679e3 5557
55d2375e
SC		 5558 pml_buf = page_address(vmx->pml_pg);
5559 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5560 u64 gpa;
945679e3 5561
55d2375e
SC		 5562 gpa = pml_buf[pml_idx];
5563 WARN_ON(gpa & (PAGE_SIZE - 1));
5564 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5565 }
5566
55d2375e
SC		 5567 /* reset PML index */
5568 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5569}
5570
f4160e45 5571/*
55d2375e
SC		 5572 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5573 * Called before reporting dirty_bitmap to userspace.
f4160e45 5574 */
55d2375e 5575static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5576{
55d2375e
SC		 5577 int i;
5578 struct kvm_vcpu *vcpu;
49f705c5 5579 /*
55d2375e
SC		 5580 * We only need to kick vcpu out of guest mode here, as PML buffer
5581 * is flushed at beginning of all VMEXITs, and it's obvious that only
5582 * vcpus running in guest are possible to have unflushed GPAs in PML
5583 * buffer.
49f705c5 5584 */
55d2375e
SC		 5585 kvm_for_each_vcpu(i, vcpu, kvm)
5586 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5587}
5588
55d2375e 5589static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5590{
55d2375e
SC		 5591 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5592 name, vmcs_read16(sel),
5593 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5594 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5595 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5596}
5597
55d2375e 5598static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5599{
55d2375e
SC		 5600 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5601 name, vmcs_read32(limit),
5602 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5603}
5604
69090810 5605void dump_vmcs(void)
63846663 5606{
55d2375e
SC		 5607 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5608 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5609 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5610 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5611 u32 secondary_exec_control = 0;
5612 unsigned long cr4 = vmcs_readl(GUEST_CR4);
5613 u64 efer = vmcs_read64(GUEST_IA32_EFER);
5614 int i, n;
63846663 5615
55d2375e
SC		 5616 if (cpu_has_secondary_exec_ctrls())
5617 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5618
55d2375e
SC		 5619 pr_err("*** Guest State ***\n");
5620 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5621 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5622 vmcs_readl(CR0_GUEST_HOST_MASK));
5623 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5624 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5625 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5626 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5627 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5628 {
5629 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5630 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5631 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5632 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5633 }
55d2375e
SC		 5634 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5635 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5636 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5637 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5638 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5639 vmcs_readl(GUEST_SYSENTER_ESP),
5640 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5641 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5642 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5643 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5644 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5645 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5646 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5647 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5648 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5649 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5650 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5651 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5652 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5653 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5654 efer, vmcs_read64(GUEST_IA32_PAT));
5655 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5656 vmcs_read64(GUEST_IA32_DEBUGCTL),
5657 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5658 if (cpu_has_load_perf_global_ctrl() &&
5659 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5660 pr_err("PerfGlobCtl = 0x%016llx\n",
5661 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5662 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5663 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5664 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5665 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5666 vmcs_read32(GUEST_ACTIVITY_STATE));
5667 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5668 pr_err("InterruptStatus = %04x\n",
5669 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5670
55d2375e
SC		 5671 pr_err("*** Host State ***\n");
5672 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5673 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5674 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5675 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5676 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5677 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5678 vmcs_read16(HOST_TR_SELECTOR));
5679 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5680 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5681 vmcs_readl(HOST_TR_BASE));
5682 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5683 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5684 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5685 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5686 vmcs_readl(HOST_CR4));
5687 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5688 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5689 vmcs_read32(HOST_IA32_SYSENTER_CS),
5690 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5691 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5692 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5693 vmcs_read64(HOST_IA32_EFER),
5694 vmcs_read64(HOST_IA32_PAT));
5695 if (cpu_has_load_perf_global_ctrl() &&
5696 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5697 pr_err("PerfGlobCtl = 0x%016llx\n",
5698 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5699
55d2375e
SC		 5700 pr_err("*** Control State ***\n");
5701 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5702 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5703 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5704 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5705 vmcs_read32(EXCEPTION_BITMAP),
5706 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5707 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5708 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5709 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5710 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5711 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5712 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5713 vmcs_read32(VM_EXIT_INTR_INFO),
5714 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5715 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5716 pr_err(" reason=%08x qualification=%016lx\n",
5717 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5718 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5719 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5720 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5721 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5722 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5723 pr_err("TSC Multiplier = 0x%016llx\n",
5724 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5725 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5726 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5727 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5728 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5729 }
5730 pr_err(KERN_CONT "TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5731 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5732 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5733 pr_err(KERN_CONT "virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5734 }
55d2375e
SC		 5735 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5736 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5737 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5738 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5739 n = vmcs_read32(CR3_TARGET_COUNT);
5740 for (i = 0; i + 1 < n; i += 4)
5741 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5742 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5743 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5744 if (i < n)
5745 pr_err("CR3 target%u=%016lx\n",
5746 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5747 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5748 pr_err("PLE Gap=%08x Window=%08x\n",
5749 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5750 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5751 pr_err("Virtual processor ID = 0x%04x\n",
5752 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5753}
5754
55d2375e
SC		 5755/*
5756 * The guest has exited. See if we can fix it or if we need userspace
5757 * assistance.
5758 */
5759static int vmx_handle_exit(struct kvm_vcpu *vcpu)
ff651cb6 5760{
55d2375e
SC		 5761 struct vcpu_vmx *vmx = to_vmx(vcpu);
5762 u32 exit_reason = vmx->exit_reason;
5763 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5764
55d2375e 5765 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5766
55d2375e
SC		 5767 /*
5768 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5769 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5770 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5771 * mode as if vcpus is in root mode, the PML buffer must has been
5772 * flushed already.
5773 */
5774 if (enable_pml)
5775 vmx_flush_pml_buffer(vcpu);
1dc35dac 5776
55d2375e
SC		 5777 /* If guest state is invalid, start emulating */
5778 if (vmx->emulation_required)
5779 return handle_invalid_guest_state(vcpu);
1dc35dac 5780
55d2375e
SC		 5781 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5782 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5783
55d2375e
SC		 5784 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5785 dump_vmcs();
5786 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5787 vcpu->run->fail_entry.hardware_entry_failure_reason
5788 = exit_reason;
5789 return 0;
9ed38ffa
LP		 5790 }
5791
55d2375e
SC		 5792 if (unlikely(vmx->fail)) {
5793 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5794 vcpu->run->fail_entry.hardware_entry_failure_reason
5795 = vmcs_read32(VM_INSTRUCTION_ERROR);
5796 return 0;
5797 }
50c28f21 5798
55d2375e
SC		 5799 /*
5800 * Note:
5801 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5802 * delivery event since it indicates guest is accessing MMIO.
5803 * The vm-exit can be triggered again after return to guest that
5804 * will cause infinite loop.
5805 */
5806 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5807 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5808 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5809 exit_reason != EXIT_REASON_PML_FULL &&
5810 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5811 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5812 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5813 vcpu->run->internal.ndata = 3;
5814 vcpu->run->internal.data[0] = vectoring_info;
5815 vcpu->run->internal.data[1] = exit_reason;
5816 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5817 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5818 vcpu->run->internal.ndata++;
5819 vcpu->run->internal.data[3] =
5820 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5821 }
5822 return 0;
5823 }
50c28f21 5824
55d2375e
SC		 5825 if (unlikely(!enable_vnmi &&
5826 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5827 if (vmx_interrupt_allowed(vcpu)) {
5828 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5829 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5830 vcpu->arch.nmi_pending) {
5831 /*
5832 * This CPU don't support us in finding the end of an
5833 * NMI-blocked window if the guest runs with IRQs
5834 * disabled. So we pull the trigger after 1 s of
5835 * futile waiting, but inform the user about this.
5836 */
5837 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5838 "state on VCPU %d after 1 s timeout\n",
5839 __func__, vcpu->vcpu_id);
5840 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5841 }
5842 }
50c28f21 5843
55d2375e
SC		 5844 if (exit_reason < kvm_vmx_max_exit_handlers
5845 && kvm_vmx_exit_handlers[exit_reason])
5846 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5847 else {
5848 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5849 exit_reason);
5850 kvm_queue_exception(vcpu, UD_VECTOR);
5851 return 1;
5852 }
9ed38ffa
LP		 5853}
5854
efebf0aa 5855/*
55d2375e
SC		 5856 * Software based L1D cache flush which is used when microcode providing
5857 * the cache control MSR is not loaded.
efebf0aa 5858 *
55d2375e
SC		 5859 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5860 * flush it is required to read in 64 KiB because the replacement algorithm
5861 * is not exactly LRU. This could be sized at runtime via topology
5862 * information but as all relevant affected CPUs have 32KiB L1D cache size
5863 * there is no point in doing so.
efebf0aa 5864 */
55d2375e 5865static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5866{
55d2375e 5867 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5868
5869 /*
55d2375e
SC		 5870 * This code is only executed when the the flush mode is 'cond' or
5871 * 'always'
25a2e4fe 5872 */
55d2375e
SC		 5873 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5874 bool flush_l1d;
25a2e4fe 5875
55d2375e
SC		 5876 /*
5877 * Clear the per-vcpu flush bit, it gets set again
5878 * either from vcpu_run() or from one of the unsafe
5879 * VMEXIT handlers.
5880 */
5881 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5882 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5883
55d2375e
SC		 5884 /*
5885 * Clear the per-cpu flush bit, it gets set again from
5886 * the interrupt handlers.
5887 */
5888 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5889 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 5890
55d2375e
SC		 5891 if (!flush_l1d)
5892 return;
5893 }
09abe320 5894
55d2375e 5895 vcpu->stat.l1d_flush++;
25a2e4fe 5896
55d2375e
SC		 5897 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5898 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5899 return;
5900 }
25a2e4fe 5901
55d2375e
SC		 5902 asm volatile(
5903 /* First ensure the pages are in the TLB */
5904 "xorl %%eax, %%eax\n"
5905 ".Lpopulate_tlb:\n\t"
5906 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5907 "addl $4096, %%eax\n\t"
5908 "cmpl %%eax, %[size]\n\t"
5909 "jne .Lpopulate_tlb\n\t"
5910 "xorl %%eax, %%eax\n\t"
5911 "cpuid\n\t"
5912 /* Now fill the cache */
5913 "xorl %%eax, %%eax\n"
5914 ".Lfill_cache:\n"
5915 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5916 "addl $64, %%eax\n\t"
5917 "cmpl %%eax, %[size]\n\t"
5918 "jne .Lfill_cache\n\t"
5919 "lfence\n"
5920 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5921 [size] "r" (size)
5922 : "eax", "ebx", "ecx", "edx");
09abe320 5923}
25a2e4fe 5924
55d2375e 5925static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 5926{
55d2375e 5927 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
09abe320 5928
55d2375e
SC		 5929 if (is_guest_mode(vcpu) &&
5930 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5931 return;
25a2e4fe 5932
55d2375e
SC		 5933 if (irr == -1 || tpr < irr) {
5934 vmcs_write32(TPR_THRESHOLD, 0);
5935 return;
25a2e4fe 5936 }
55d2375e
SC		 5937
5938 vmcs_write32(TPR_THRESHOLD, irr);
8665c3f9
PB		 5939}
5940
55d2375e 5941void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 5942{
55d2375e 5943 u32 sec_exec_control;
8665c3f9 5944
55d2375e
SC		 5945 if (!lapic_in_kernel(vcpu))
5946 return;
9314006d 5947
55d2375e
SC		 5948 if (!flexpriority_enabled &&
5949 !cpu_has_vmx_virtualize_x2apic_mode())
5950 return;
705699a1 5951
55d2375e
SC		 5952 /* Postpone execution until vmcs01 is the current VMCS. */
5953 if (is_guest_mode(vcpu)) {
5954 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
5955 return;
6beb7bd5 5956 }
fe3ef05c 5957
55d2375e
SC		 5958 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5959 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
5960 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 5961
55d2375e
SC		 5962 switch (kvm_get_apic_mode(vcpu)) {
5963 case LAPIC_MODE_INVALID:
5964 WARN_ONCE(true, "Invalid local APIC state");
5965 case LAPIC_MODE_DISABLED:
5966 break;
5967 case LAPIC_MODE_XAPIC:
5968 if (flexpriority_enabled) {
5969 sec_exec_control |=
5970 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5971 vmx_flush_tlb(vcpu, true);
5972 }
5973 break;
5974 case LAPIC_MODE_X2APIC:
5975 if (cpu_has_vmx_virtualize_x2apic_mode())
5976 sec_exec_control |=
5977 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5978 break;
09abe320 5979 }
55d2375e 5980 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
09abe320 5981
55d2375e
SC		 5982 vmx_update_msr_bitmap(vcpu);
5983}
0238ea91 5984
55d2375e
SC		 5985static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
5986{
5987 if (!is_guest_mode(vcpu)) {
5988 vmcs_write64(APIC_ACCESS_ADDR, hpa);
5989 vmx_flush_tlb(vcpu, true);
5990 }
5991}
fe3ef05c 5992
55d2375e
SC		 5993static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5994{
5995 u16 status;
5996 u8 old;
32c7acf0 5997
55d2375e
SC		 5998 if (max_isr == -1)
5999 max_isr = 0;
608406e2 6000
55d2375e
SC		 6001 status = vmcs_read16(GUEST_INTR_STATUS);
6002 old = status >> 8;
6003 if (max_isr != old) {
6004 status &= 0xff;
6005 status |= max_isr << 8;
6006 vmcs_write16(GUEST_INTR_STATUS, status);
6007 }
6008}
6beb7bd5 6009
55d2375e
SC		 6010static void vmx_set_rvi(int vector)
6011{
6012 u16 status;
6013 u8 old;
0b665d30 6014
55d2375e
SC		 6015 if (vector == -1)
6016 vector = 0;
fe3ef05c 6017
55d2375e
SC		 6018 status = vmcs_read16(GUEST_INTR_STATUS);
6019 old = (u8)status & 0xff;
6020 if ((u8)vector != old) {
6021 status &= ~0xff;
6022 status |= (u8)vector;
6023 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6024 }
55d2375e 6025}
09abe320 6026
55d2375e
SC		 6027static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6028{
09abe320 6029 /*
55d2375e
SC		 6030 * When running L2, updating RVI is only relevant when
6031 * vmcs12 virtual-interrupt-delivery enabled.
6032 * However, it can be enabled only when L1 also
6033 * intercepts external-interrupts and in that case
6034 * we should not update vmcs02 RVI but instead intercept
6035 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6036 */
55d2375e
SC		 6037 if (!is_guest_mode(vcpu))
6038 vmx_set_rvi(max_irr);
6039}
fe3ef05c 6040
55d2375e
SC		 6041static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6042{
6043 struct vcpu_vmx *vmx = to_vmx(vcpu);
6044 int max_irr;
6045 bool max_irr_updated;
a7c0b07d 6046
55d2375e
SC		 6047 WARN_ON(!vcpu->arch.apicv_active);
6048 if (pi_test_on(&vmx->pi_desc)) {
6049 pi_clear_on(&vmx->pi_desc);
6050 /*
6051 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6052 * But on x86 this is just a compiler barrier anyway.
6053 */
6054 smp_mb__after_atomic();
6055 max_irr_updated =
6056 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6057
6058 /*
55d2375e
SC		 6059 * If we are running L2 and L1 has a new pending interrupt
6060 * which can be injected, we should re-evaluate
6061 * what should be done with this new L1 interrupt.
6062 * If L1 intercepts external-interrupts, we should
6063 * exit from L2 to L1. Otherwise, interrupt should be
6064 * delivered directly to L2.
c4ebd629 6065 */
55d2375e
SC		 6066 if (is_guest_mode(vcpu) && max_irr_updated) {
6067 if (nested_exit_on_intr(vcpu))
6068 kvm_vcpu_exiting_guest_mode(vcpu);
6069 else
6070 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6071 }
55d2375e
SC		 6072 } else {
6073 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6074 }
55d2375e
SC		 6075 vmx_hwapic_irr_update(vcpu, max_irr);
6076 return max_irr;
6077}
a7c0b07d 6078
55d2375e
SC		 6079static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6080{
6081 if (!kvm_vcpu_apicv_active(vcpu))
6082 return;
25a2e4fe 6083
55d2375e
SC		 6084 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6085 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6086 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6087 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6088}
6089
55d2375e 6090static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6091{
6092 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6093
55d2375e
SC		 6094 pi_clear_on(&vmx->pi_desc);
6095 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6096}
8665c3f9 6097
55d2375e
SC		 6098static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6099{
6100 u32 exit_intr_info = 0;
6101 u16 basic_exit_reason = (u16)vmx->exit_reason;
fe3ef05c 6102
55d2375e
SC		 6103 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6104 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
6105 return;
fe3ef05c 6106
55d2375e
SC		 6107 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6108 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6109 vmx->exit_intr_info = exit_intr_info;
fe3ef05c 6110
55d2375e
SC		 6111 /* if exit due to PF check for async PF */
6112 if (is_page_fault(exit_intr_info))
6113 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 6114
55d2375e
SC		 6115 /* Handle machine checks before interrupts are enabled */
6116 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
6117 is_machine_check(exit_intr_info))
6118 kvm_machine_check();
fe3ef05c 6119
55d2375e
SC		 6120 /* We need to handle NMIs before interrupts are enabled */
6121 if (is_nmi(exit_intr_info)) {
6122 kvm_before_interrupt(&vmx->vcpu);
6123 asm("int $2");
6124 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6125 }
55d2375e 6126}
fe3ef05c 6127
55d2375e
SC		 6128static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6129{
6130 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6131
55d2375e
SC		 6132 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6133 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6134 unsigned int vector;
6135 unsigned long entry;
6136 gate_desc *desc;
6137 struct vcpu_vmx *vmx = to_vmx(vcpu);
6138#ifdef CONFIG_X86_64
6139 unsigned long tmp;
6140#endif
fe3ef05c 6141
55d2375e
SC		 6142 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6143 desc = (gate_desc *)vmx->host_idt_base + vector;
6144 entry = gate_offset(desc);
6145 asm volatile(
6146#ifdef CONFIG_X86_64
6147 "mov %%" _ASM_SP ", %[sp]\n\t"
6148 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6149 "push $%c[ss]\n\t"
6150 "push %[sp]\n\t"
6151#endif
6152 "pushf\n\t"
6153 __ASM_SIZE(push) " $%c[cs]\n\t"
6154 CALL_NOSPEC
6155 :
6156#ifdef CONFIG_X86_64
6157 [sp]"=&r"(tmp),
6158#endif
6159 ASM_CALL_CONSTRAINT
6160 :
6161 THUNK_TARGET(entry),
6162 [ss]"i"(__KERNEL_DS),
6163 [cs]"i"(__KERNEL_CS)
6164 );
6165 }
6166}
6167STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
5a6a9748 6168
55d2375e
SC		 6169static bool vmx_has_emulated_msr(int index)
6170{
6171 switch (index) {
6172 case MSR_IA32_SMBASE:
6173 /*
6174 * We cannot do SMM unless we can run the guest in big
6175 * real mode.
6176 */
6177 return enable_unrestricted_guest || emulate_invalid_guest_state;
6178 case MSR_AMD64_VIRT_SPEC_CTRL:
6179 /* This is AMD only. */
6180 return false;
6181 default:
6182 return true;
3184a995 6183 }
55d2375e 6184}
2bb8cafe 6185
86f5201d
CP		 6186static bool vmx_pt_supported(void)
6187{
6188 return pt_mode == PT_MODE_HOST_GUEST;
6189}
6190
55d2375e
SC		 6191static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6192{
6193 u32 exit_intr_info;
6194 bool unblock_nmi;
6195 u8 vector;
6196 bool idtv_info_valid;
7ca29de2 6197
55d2375e 6198 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6199
55d2375e
SC		 6200 if (enable_vnmi) {
6201 if (vmx->loaded_vmcs->nmi_known_unmasked)
6202 return;
6203 /*
6204 * Can't use vmx->exit_intr_info since we're not sure what
6205 * the exit reason is.
6206 */
6207 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6208 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6209 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6210 /*
6211 * SDM 3: 27.7.1.2 (September 2008)
6212 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6213 * a guest IRET fault.
6214 * SDM 3: 23.2.2 (September 2008)
6215 * Bit 12 is undefined in any of the following cases:
6216 * If the VM exit sets the valid bit in the IDT-vectoring
6217 * information field.
6218 * If the VM exit is due to a double fault.
6219 */
6220 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6221 vector != DF_VECTOR && !idtv_info_valid)
6222 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6223 GUEST_INTR_STATE_NMI);
6224 else
6225 vmx->loaded_vmcs->nmi_known_unmasked =
6226 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6227 & GUEST_INTR_STATE_NMI);
6228 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6229 vmx->loaded_vmcs->vnmi_blocked_time +=
6230 ktime_to_ns(ktime_sub(ktime_get(),
6231 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6232}
6233
55d2375e
SC		 6234static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6235 u32 idt_vectoring_info,
6236 int instr_len_field,
6237 int error_code_field)
0c7f650e 6238{
55d2375e
SC		 6239 u8 vector;
6240 int type;
6241 bool idtv_info_valid;
0c7f650e 6242
55d2375e 6243 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6244
55d2375e
SC		 6245 vcpu->arch.nmi_injected = false;
6246 kvm_clear_exception_queue(vcpu);
6247 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6248
55d2375e
SC		 6249 if (!idtv_info_valid)
6250 return;
c7c2c709 6251
55d2375e 6252 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6253
55d2375e
SC		 6254 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6255 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6256
55d2375e
SC		 6257 switch (type) {
6258 case INTR_TYPE_NMI_INTR:
6259 vcpu->arch.nmi_injected = true;
6260 /*
6261 * SDM 3: 27.7.1.2 (September 2008)
6262 * Clear bit "block by NMI" before VM entry if a NMI
6263 * delivery faulted.
6264 */
6265 vmx_set_nmi_mask(vcpu, false);
6266 break;
6267 case INTR_TYPE_SOFT_EXCEPTION:
6268 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6269 /* fall through */
6270 case INTR_TYPE_HARD_EXCEPTION:
6271 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6272 u32 err = vmcs_read32(error_code_field);
6273 kvm_requeue_exception_e(vcpu, vector, err);
6274 } else
6275 kvm_requeue_exception(vcpu, vector);
6276 break;
6277 case INTR_TYPE_SOFT_INTR:
6278 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6279 /* fall through */
6280 case INTR_TYPE_EXT_INTR:
6281 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6282 break;
6283 default:
6284 break;
0447378a 6285 }
ca0bde28
JM		 6286}
6287
55d2375e 6288static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6289{
55d2375e
SC		 6290 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6291 VM_EXIT_INSTRUCTION_LEN,
6292 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6293}
6294
55d2375e 6295static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6296{
55d2375e
SC		 6297 __vmx_complete_interrupts(vcpu,
6298 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6299 VM_ENTRY_INSTRUCTION_LEN,
6300 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6301
55d2375e 6302 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6303}
6304
55d2375e 6305static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6306{
55d2375e
SC		 6307 int i, nr_msrs;
6308 struct perf_guest_switch_msr *msrs;
7c177938 6309
55d2375e 6310 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6311
55d2375e
SC		 6312 if (!msrs)
6313 return;
f1b026a3 6314
55d2375e
SC		 6315 for (i = 0; i < nr_msrs; i++)
6316 if (msrs[i].host == msrs[i].guest)
6317 clear_atomic_switch_msr(vmx, msrs[i].msr);
6318 else
6319 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6320 msrs[i].host, false);
ca0bde28 6321}
52017608 6322
55d2375e
SC		 6323static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
6324{
6325 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
6326 if (!vmx->loaded_vmcs->hv_timer_armed)
6327 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
6328 PIN_BASED_VMX_PREEMPTION_TIMER);
6329 vmx->loaded_vmcs->hv_timer_armed = true;
6330}
ca0bde28 6331
55d2375e 6332static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6333{
6334 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6335 u64 tscl;
6336 u32 delta_tsc;
52017608 6337
55d2375e
SC		 6338 if (vmx->req_immediate_exit) {
6339 vmx_arm_hv_timer(vmx, 0);
6340 return;
16fb9a46
SC		 6341 }
6342
55d2375e
SC		 6343 if (vmx->hv_deadline_tsc != -1) {
6344 tscl = rdtsc();
6345 if (vmx->hv_deadline_tsc > tscl)
6346 /* set_hv_timer ensures the delta fits in 32-bits */
6347 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6348 cpu_preemption_timer_multi);
6349 else
6350 delta_tsc = 0;
858e25c0 6351
55d2375e
SC		 6352 vmx_arm_hv_timer(vmx, delta_tsc);
6353 return;
7f7f1ba3 6354 }
858e25c0 6355
55d2375e
SC		 6356 if (vmx->loaded_vmcs->hv_timer_armed)
6357 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
6358 PIN_BASED_VMX_PREEMPTION_TIMER);
6359 vmx->loaded_vmcs->hv_timer_armed = false;
858e25c0
JM		 6360}
6361
c09b03eb 6362void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6363{
c09b03eb
SC		 6364 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6365 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6366 vmcs_writel(HOST_RSP, host_rsp);
6367 }
5ad6ece8 6368}
5f3d5799 6369
fc2ba5a2 6370bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6371
6372static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6373{
6374 struct vcpu_vmx *vmx = to_vmx(vcpu);
6375 unsigned long cr3, cr4;
6376
6377 /* Record the guest's net vcpu time for enforced NMI injections. */
6378 if (unlikely(!enable_vnmi &&
6379 vmx->loaded_vmcs->soft_vnmi_blocked))
6380 vmx->loaded_vmcs->entry_time = ktime_get();
6381
6382 /* Don't enter VMX if guest state is invalid, let the exit handler
6383 start emulation until we arrive back to a valid state */
6384 if (vmx->emulation_required)
6385 return;
6386
6387 if (vmx->ple_window_dirty) {
6388 vmx->ple_window_dirty = false;
6389 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6390 }
6391
6392 if (vmx->nested.need_vmcs12_sync)
6393 nested_sync_from_vmcs12(vcpu);
6394
6395 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6396 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6397 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6398 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6399
6400 cr3 = __get_current_cr3_fast();
6401 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6402 vmcs_writel(HOST_CR3, cr3);
6403 vmx->loaded_vmcs->host_state.cr3 = cr3;
6404 }
6405
6406 cr4 = cr4_read_shadow();
6407 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6408 vmcs_writel(HOST_CR4, cr4);
6409 vmx->loaded_vmcs->host_state.cr4 = cr4;
6410 }
6411
6412 /* When single-stepping over STI and MOV SS, we must clear the
6413 * corresponding interruptibility bits in the guest state. Otherwise
6414 * vmentry fails as it then expects bit 14 (BS) in pending debug
6415 * exceptions being set, but that's not correct for the guest debugging
6416 * case. */
6417 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6418 vmx_set_interrupt_shadow(vcpu, 0);
6419
1811d979
WC		 6420 kvm_load_guest_xcr0(vcpu);
6421
5ad6ece8
SC		 6422 if (static_cpu_has(X86_FEATURE_PKU) &&
6423 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6424 vcpu->arch.pkru != vmx->host_pkru)
6425 __write_pkru(vcpu->arch.pkru);
6426
6427 pt_guest_enter(vmx);
6428
6429 atomic_switch_perf_msrs(vmx);
6430
6431 vmx_update_hv_timer(vcpu);
6432
6433 /*
6434 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6435 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6436 * is no need to worry about the conditional branch over the wrmsr
6437 * being speculatively taken.
6438 */
6439 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6440
c823dd5c
SC		 6441 if (static_branch_unlikely(&vmx_l1d_should_flush))
6442 vmx_l1d_flush(vcpu);
6443
6444 if (vcpu->arch.cr2 != read_cr2())
6445 write_cr2(vcpu->arch.cr2);
6446
fc2ba5a2
SC		 6447 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6448 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6449
6450 vcpu->arch.cr2 = read_cr2();
b6b8a145 6451
55d2375e
SC		 6452 /*
6453 * We do not use IBRS in the kernel. If this vCPU has used the
6454 * SPEC_CTRL MSR it may have left it on; save the value and
6455 * turn it off. This is much more efficient than blindly adding
6456 * it to the atomic save/restore list. Especially as the former
6457 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6458 *
6459 * For non-nested case:
6460 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6461 * save it.
6462 *
6463 * For nested case:
6464 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6465 * save it.
6466 */
6467 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6468 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6469
55d2375e 6470 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6471
55d2375e
SC		 6472 /* Eliminate branch target predictions from guest mode */
6473 vmexit_fill_RSB();
f4124500 6474
55d2375e
SC		 6475 /* All fields are clean at this point */
6476 if (static_branch_unlikely(&enable_evmcs))
6477 current_evmcs->hv_clean_fields |=
6478 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6479
55d2375e
SC		 6480 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6481 if (vmx->host_debugctlmsr)
6482 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6483
55d2375e
SC		 6484#ifndef CONFIG_X86_64
6485 /*
6486 * The sysexit path does not restore ds/es, so we must set them to
6487 * a reasonable value ourselves.
6488 *
6489 * We can't defer this to vmx_prepare_switch_to_host() since that
6490 * function may be executed in interrupt context, which saves and
6491 * restore segments around it, nullifying its effect.
6492 */
6493 loadsegment(ds, __USER_DS);
6494 loadsegment(es, __USER_DS);
6495#endif
4704d0be 6496
55d2375e
SC		 6497 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6498 | (1 << VCPU_EXREG_RFLAGS)
6499 | (1 << VCPU_EXREG_PDPTR)
6500 | (1 << VCPU_EXREG_SEGMENTS)
6501 | (1 << VCPU_EXREG_CR3));
6502 vcpu->arch.regs_dirty = 0;
7854cbca 6503
2ef444f1
CP		 6504 pt_guest_exit(vmx);
6505
3633cfc3 6506 /*
55d2375e
SC		 6507 * eager fpu is enabled if PKEY is supported and CR4 is switched
6508 * back on host, so it is safe to read guest PKRU from current
6509 * XSAVE.
3633cfc3 6510 */
55d2375e
SC		 6511 if (static_cpu_has(X86_FEATURE_PKU) &&
6512 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6513 vcpu->arch.pkru = __read_pkru();
6514 if (vcpu->arch.pkru != vmx->host_pkru)
6515 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6516 }
6517
1811d979
WC		 6518 kvm_put_guest_xcr0(vcpu);
6519
55d2375e
SC		 6520 vmx->nested.nested_run_pending = 0;
6521 vmx->idt_vectoring_info = 0;
119a9c01 6522
55d2375e
SC		 6523 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6524 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6525 return;
608406e2 6526
55d2375e
SC		 6527 vmx->loaded_vmcs->launched = 1;
6528 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6529
55d2375e
SC		 6530 vmx_complete_atomic_exit(vmx);
6531 vmx_recover_nmi_blocking(vmx);
6532 vmx_complete_interrupts(vmx);
6533}
2996fca0 6534
55d2375e
SC		 6535static struct kvm *vmx_vm_alloc(void)
6536{
41836839
BG		 6537 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6538 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6539 PAGE_KERNEL);
55d2375e 6540 return &kvm_vmx->kvm;
cf8b84f4
JM		 6541}
6542
55d2375e
SC		 6543static void vmx_vm_free(struct kvm *kvm)
6544{
6545 vfree(to_kvm_vmx(kvm));
6546}
6547
6548static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6549{
55d2375e 6550 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6551
55d2375e
SC		 6552 if (enable_pml)
6553 vmx_destroy_pml_buffer(vmx);
6554 free_vpid(vmx->vpid);
55d2375e
SC		 6555 nested_vmx_free_vcpu(vcpu);
6556 free_loaded_vmcs(vmx->loaded_vmcs);
6557 kfree(vmx->guest_msrs);
6558 kvm_vcpu_uninit(vcpu);
b666a4b6 6559 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
55d2375e
SC		 6560 kmem_cache_free(kvm_vcpu_cache, vmx);
6561}
4704d0be 6562
55d2375e
SC		 6563static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6564{
6565 int err;
41836839 6566 struct vcpu_vmx *vmx;
55d2375e
SC		 6567 unsigned long *msr_bitmap;
6568 int cpu;
7313c698 6569
41836839 6570 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6571 if (!vmx)
6572 return ERR_PTR(-ENOMEM);
4704d0be 6573
41836839
BG		 6574 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6575 GFP_KERNEL_ACCOUNT);
b666a4b6
MO		 6576 if (!vmx->vcpu.arch.guest_fpu) {
6577 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6578 err = -ENOMEM;
6579 goto free_partial_vcpu;
6580 }
6581
55d2375e 6582 vmx->vpid = allocate_vpid();
7cdc2d62 6583
55d2375e
SC		 6584 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6585 if (err)
6586 goto free_vcpu;
5f3d5799 6587
55d2375e 6588 err = -ENOMEM;
5f3d5799
JK		 6589
6590 /*
55d2375e
SC		 6591 * If PML is turned on, failure on enabling PML just results in failure
6592 * of creating the vcpu, therefore we can simplify PML logic (by
6593 * avoiding dealing with cases, such as enabling PML partially on vcpus
6594 * for the guest, etc.
5f3d5799 6595 */
55d2375e 6596 if (enable_pml) {
41836839 6597 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e
SC		 6598 if (!vmx->pml_pg)
6599 goto uninit_vcpu;
6600 }
4704d0be 6601
41836839 6602 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6603 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6604 > PAGE_SIZE);
21feb4eb 6605
55d2375e
SC		 6606 if (!vmx->guest_msrs)
6607 goto free_pml;
4704d0be 6608
55d2375e
SC		 6609 err = alloc_loaded_vmcs(&vmx->vmcs01);
6610 if (err < 0)
6611 goto free_msrs;
cb61de2f 6612
55d2375e 6613 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6614 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6615 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6616 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6617 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6618 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6619 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6620 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6621 vmx->msr_bitmap_mode = 0;
4704d0be 6622
55d2375e
SC		 6623 vmx->loaded_vmcs = &vmx->vmcs01;
6624 cpu = get_cpu();
6625 vmx_vcpu_load(&vmx->vcpu, cpu);
6626 vmx->vcpu.cpu = cpu;
6627 vmx_vcpu_setup(vmx);
6628 vmx_vcpu_put(&vmx->vcpu);
6629 put_cpu();
6630 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6631 err = alloc_apic_access_page(kvm);
6632 if (err)
6633 goto free_vmcs;
6634 }
6635
6636 if (enable_ept && !enable_unrestricted_guest) {
6637 err = init_rmode_identity_map(kvm);
6638 if (err)
6639 goto free_vmcs;
6640 }
4704d0be 6641
55d2375e
SC		 6642 if (nested)
6643 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6644 vmx_capability.ept,
6645 kvm_vcpu_apicv_active(&vmx->vcpu));
6646 else
6647 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6648
55d2375e
SC		 6649 vmx->nested.posted_intr_nv = -1;
6650 vmx->nested.current_vmptr = -1ull;
bd18bffc 6651
55d2375e 6652 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
feaf0c7d 6653
6f1e03bc 6654 /*
55d2375e
SC		 6655 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6656 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6657 */
55d2375e
SC		 6658 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6659 vmx->pi_desc.sn = 1;
4704d0be 6660
53963a70
LT		 6661 vmx->ept_pointer = INVALID_PAGE;
6662
55d2375e 6663 return &vmx->vcpu;
4704d0be 6664
55d2375e
SC		 6665free_vmcs:
6666 free_loaded_vmcs(vmx->loaded_vmcs);
6667free_msrs:
6668 kfree(vmx->guest_msrs);
6669free_pml:
6670 vmx_destroy_pml_buffer(vmx);
6671uninit_vcpu:
6672 kvm_vcpu_uninit(&vmx->vcpu);
6673free_vcpu:
6674 free_vpid(vmx->vpid);
b666a4b6
MO		 6675 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6676free_partial_vcpu:
55d2375e
SC		 6677 kmem_cache_free(kvm_vcpu_cache, vmx);
6678 return ERR_PTR(err);
6679}
36be0b9d 6680
55d2375e
SC		 6681#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
6682#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
21feb4eb 6683
55d2375e
SC		 6684static int vmx_vm_init(struct kvm *kvm)
6685{
6686 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6687
55d2375e
SC		 6688 if (!ple_gap)
6689 kvm->arch.pause_in_guest = true;
3af18d9c 6690
55d2375e
SC		 6691 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6692 switch (l1tf_mitigation) {
6693 case L1TF_MITIGATION_OFF:
6694 case L1TF_MITIGATION_FLUSH_NOWARN:
6695 /* 'I explicitly don't care' is set */
6696 break;
6697 case L1TF_MITIGATION_FLUSH:
6698 case L1TF_MITIGATION_FLUSH_NOSMT:
6699 case L1TF_MITIGATION_FULL:
6700 /*
6701 * Warn upon starting the first VM in a potentially
6702 * insecure environment.
6703 */
b284909a 6704 if (sched_smt_active())
55d2375e
SC		 6705 pr_warn_once(L1TF_MSG_SMT);
6706 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6707 pr_warn_once(L1TF_MSG_L1D);
6708 break;
6709 case L1TF_MITIGATION_FULL_FORCE:
6710 /* Flush is enforced */
6711 break;
6712 }
6713 }
6714 return 0;
4704d0be
NHE		 6715}
6716
55d2375e 6717static void __init vmx_check_processor_compat(void *rtn)
bd18bffc 6718{
55d2375e
SC		 6719 struct vmcs_config vmcs_conf;
6720 struct vmx_capability vmx_cap;
bd18bffc 6721
55d2375e
SC		 6722 *(int *)rtn = 0;
6723 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6724 *(int *)rtn = -EIO;
6725 if (nested)
6726 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6727 enable_apicv);
6728 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6729 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6730 smp_processor_id());
6731 *(int *)rtn = -EIO;
bd18bffc 6732 }
bd18bffc
SC		 6733}
6734
55d2375e 6735static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6736{
55d2375e
SC		 6737 u8 cache;
6738 u64 ipat = 0;
bd18bffc 6739
55d2375e
SC		 6740 /* For VT-d and EPT combination
6741 * 1. MMIO: always map as UC
6742 * 2. EPT with VT-d:
6743 * a. VT-d without snooping control feature: can't guarantee the
6744 * result, try to trust guest.
6745 * b. VT-d with snooping control feature: snooping control feature of
6746 * VT-d engine can guarantee the cache correctness. Just set it
6747 * to WB to keep consistent with host. So the same as item 3.
6748 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6749 * consistent with host MTRR
bd18bffc 6750 */
55d2375e
SC		 6751 if (is_mmio) {
6752 cache = MTRR_TYPE_UNCACHABLE;
6753 goto exit;
6754 }
bd18bffc 6755
55d2375e
SC		 6756 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6757 ipat = VMX_EPT_IPAT_BIT;
6758 cache = MTRR_TYPE_WRBACK;
6759 goto exit;
6760 }
bd18bffc 6761
55d2375e
SC		 6762 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6763 ipat = VMX_EPT_IPAT_BIT;
6764 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6765 cache = MTRR_TYPE_WRBACK;
6766 else
6767 cache = MTRR_TYPE_UNCACHABLE;
6768 goto exit;
6769 }
bd18bffc 6770
55d2375e 6771 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6772
55d2375e
SC		 6773exit:
6774 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6775}
bd18bffc 6776
55d2375e
SC		 6777static int vmx_get_lpage_level(void)
6778{
6779 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6780 return PT_DIRECTORY_LEVEL;
6781 else
6782 /* For shadow and EPT supported 1GB page */
6783 return PT_PDPE_LEVEL;
6784}
bd18bffc 6785
55d2375e
SC		 6786static void vmcs_set_secondary_exec_control(u32 new_ctl)
6787{
bd18bffc 6788 /*
55d2375e
SC		 6789 * These bits in the secondary execution controls field
6790 * are dynamic, the others are mostly based on the hypervisor
6791 * architecture and the guest's CPUID. Do not touch the
6792 * dynamic bits.
bd18bffc 6793 */
55d2375e
SC		 6794 u32 mask =
6795 SECONDARY_EXEC_SHADOW_VMCS |
6796 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6797 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6798 SECONDARY_EXEC_DESC;
bd18bffc 6799
55d2375e 6800 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
bd18bffc 6801
55d2375e
SC		 6802 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6803 (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6804}
6805
4704d0be 6806/*
55d2375e
SC		 6807 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6808 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6809 */
55d2375e 6810static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6811{
6812 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6813 struct kvm_cpuid_entry2 *entry;
4704d0be 6814
55d2375e
SC		 6815 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6816 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6817
55d2375e
SC		 6818#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6819 if (entry && (entry->_reg & (_cpuid_mask))) \
6820 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6821} while (0)
ff651cb6 6822
55d2375e
SC		 6823 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6824 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6825 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6826 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6827 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6828 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6829 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6830 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6831 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6832 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6833 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6834 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6835 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6836 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6837 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
61ada748 6838
55d2375e
SC		 6839 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6840 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6841 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6842 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6843 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6844 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
cf3215d9 6845
55d2375e
SC		 6846#undef cr4_fixed1_update
6847}
36c3cc42 6848
55d2375e
SC		 6849static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6850{
6851 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 6852
55d2375e
SC		 6853 if (kvm_mpx_supported()) {
6854 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 6855
55d2375e
SC		 6856 if (mpx_enabled) {
6857 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6858 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6859 } else {
6860 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6861 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6862 }
dccbfcf5 6863 }
55d2375e 6864}
4704d0be 6865
e51bfdb6
LA		 6866static bool guest_cpuid_has_pmu(struct kvm_vcpu *vcpu)
6867{
6868 struct kvm_cpuid_entry2 *entry;
6869 union cpuid10_eax eax;
6870
6871 entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
6872 if (!entry)
6873 return false;
6874
6875 eax.full = entry->eax;
6876 return (eax.split.version_id > 0);
6877}
6878
6879static void nested_vmx_procbased_ctls_update(struct kvm_vcpu *vcpu)
6880{
6881 struct vcpu_vmx *vmx = to_vmx(vcpu);
6882 bool pmu_enabled = guest_cpuid_has_pmu(vcpu);
6883
6884 if (pmu_enabled)
6885 vmx->nested.msrs.procbased_ctls_high |= CPU_BASED_RDPMC_EXITING;
6886 else
6887 vmx->nested.msrs.procbased_ctls_high &= ~CPU_BASED_RDPMC_EXITING;
6888}
6889
6c0f0bba
LK		 6890static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6891{
6892 struct vcpu_vmx *vmx = to_vmx(vcpu);
6893 struct kvm_cpuid_entry2 *best = NULL;
6894 int i;
6895
6896 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6897 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6898 if (!best)
6899 return;
6900 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6901 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6902 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6903 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
6904 }
6905
6906 /* Get the number of configurable Address Ranges for filtering */
6907 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
6908 PT_CAP_num_address_ranges);
6909
6910 /* Initialize and clear the no dependency bits */
6911 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
6912 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
6913
6914 /*
6915 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
6916 * will inject an #GP
6917 */
6918 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
6919 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
6920
6921 /*
6922 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
6923 * PSBFreq can be set
6924 */
6925 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
6926 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
6927 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
6928
6929 /*
6930 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
6931 * MTCFreq can be set
6932 */
6933 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
6934 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
6935 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
6936
6937 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
6938 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
6939 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
6940 RTIT_CTL_PTW_EN);
6941
6942 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
6943 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
6944 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
6945
6946 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
6947 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
6948 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
6949
6950 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
6951 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
6952 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
6953
6954 /* unmask address range configure area */
6955 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 6956 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 6957}
6958
55d2375e
SC		 6959static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6960{
6961 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6962
55d2375e
SC		 6963 if (cpu_has_secondary_exec_ctrls()) {
6964 vmx_compute_secondary_exec_control(vmx);
6965 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
705699a1 6966 }
4704d0be 6967
55d2375e
SC		 6968 if (nested_vmx_allowed(vcpu))
6969 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
6970 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6971 else
6972 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
6973 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4f350c6d 6974
55d2375e
SC		 6975 if (nested_vmx_allowed(vcpu)) {
6976 nested_vmx_cr_fixed1_bits_update(vcpu);
6977 nested_vmx_entry_exit_ctls_update(vcpu);
e51bfdb6 6978 nested_vmx_procbased_ctls_update(vcpu);
4f350c6d 6979 }
6c0f0bba
LK		 6980
6981 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
6982 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
6983 update_intel_pt_cfg(vcpu);
55d2375e 6984}
09abb5e3 6985
55d2375e
SC		 6986static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6987{
6988 if (func == 1 && nested)
6989 entry->ecx |= bit(X86_FEATURE_VMX);
4704d0be
NHE		 6990}
6991
55d2375e 6992static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 6993{
55d2375e 6994 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 6995}
6996
8a76d7f2
JR		 6997static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6998 struct x86_instruction_info *info,
6999 enum x86_intercept_stage stage)
7000{
fb6d4d34
PB		 7001 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7002 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7003
7004 /*
7005 * RDPID causes #UD if disabled through secondary execution controls.
7006 * Because it is marked as EmulateOnUD, we need to intercept it here.
7007 */
7008 if (info->intercept == x86_intercept_rdtscp &&
7009 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7010 ctxt->exception.vector = UD_VECTOR;
7011 ctxt->exception.error_code_valid = false;
7012 return X86EMUL_PROPAGATE_FAULT;
7013 }
7014
7015 /* TODO: check more intercepts... */
8a76d7f2
JR		 7016 return X86EMUL_CONTINUE;
7017}
7018
64672c95
YJ		 7019#ifdef CONFIG_X86_64
7020/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7021static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7022 u64 divisor, u64 *result)
7023{
7024 u64 low = a << shift, high = a >> (64 - shift);
7025
7026 /* To avoid the overflow on divq */
7027 if (high >= divisor)
7028 return 1;
7029
7030 /* Low hold the result, high hold rem which is discarded */
7031 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7032 "rm" (divisor), "0" (low), "1" (high));
7033 *result = low;
7034
7035 return 0;
7036}
7037
7038static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
7039{
386c6ddb 7040 struct vcpu_vmx *vmx;
c5ce8235 7041 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
386c6ddb
KA		 7042
7043 if (kvm_mwait_in_guest(vcpu->kvm))
7044 return -EOPNOTSUPP;
7045
7046 vmx = to_vmx(vcpu);
7047 tscl = rdtsc();
7048 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7049 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
c5ce8235
WL		 7050 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
7051
7052 if (delta_tsc > lapic_timer_advance_cycles)
7053 delta_tsc -= lapic_timer_advance_cycles;
7054 else
7055 delta_tsc = 0;
64672c95
YJ		 7056
7057 /* Convert to host delta tsc if tsc scaling is enabled */
7058 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7059 u64_shl_div_u64(delta_tsc,
7060 kvm_tsc_scaling_ratio_frac_bits,
7061 vcpu->arch.tsc_scaling_ratio,
7062 &delta_tsc))
7063 return -ERANGE;
7064
7065 /*
7066 * If the delta tsc can't fit in the 32 bit after the multi shift,
7067 * we can't use the preemption timer.
7068 * It's possible that it fits on later vmentries, but checking
7069 * on every vmentry is costly so we just use an hrtimer.
7070 */
7071 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7072 return -ERANGE;
7073
7074 vmx->hv_deadline_tsc = tscl + delta_tsc;
c8533544 7075 return delta_tsc == 0;
64672c95
YJ		 7076}
7077
7078static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7079{
f459a707 7080 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7081}
7082#endif
7083
48d89b92 7084static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7085{
b31c114b 7086 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7087 shrink_ple_window(vcpu);
ae97a3b8
RK		 7088}
7089
843e4330
KH		 7090static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7091 struct kvm_memory_slot *slot)
7092{
7093 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7094 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7095}
7096
7097static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7098 struct kvm_memory_slot *slot)
7099{
7100 kvm_mmu_slot_set_dirty(kvm, slot);
7101}
7102
7103static void vmx_flush_log_dirty(struct kvm *kvm)
7104{
7105 kvm_flush_pml_buffers(kvm);
7106}
7107
c5f983f6
BD		 7108static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7109{
7110 struct vmcs12 *vmcs12;
7111 struct vcpu_vmx *vmx = to_vmx(vcpu);
7112 gpa_t gpa;
7113 struct page *page = NULL;
7114 u64 *pml_address;
7115
7116 if (is_guest_mode(vcpu)) {
7117 WARN_ON_ONCE(vmx->nested.pml_full);
7118
7119 /*
7120 * Check if PML is enabled for the nested guest.
7121 * Whether eptp bit 6 is set is already checked
7122 * as part of A/D emulation.
7123 */
7124 vmcs12 = get_vmcs12(vcpu);
7125 if (!nested_cpu_has_pml(vmcs12))
7126 return 0;
7127
4769886b 7128 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7129 vmx->nested.pml_full = true;
7130 return 1;
7131 }
7132
7133 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7134
5e2f30b7
DH		 7135 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
7136 if (is_error_page(page))
c5f983f6
BD		 7137 return 0;
7138
7139 pml_address = kmap(page);
7140 pml_address[vmcs12->guest_pml_index--] = gpa;
7141 kunmap(page);
53a70daf 7142 kvm_release_page_clean(page);
c5f983f6
BD		 7143 }
7144
7145 return 0;
7146}
7147
843e4330
KH		 7148static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7149 struct kvm_memory_slot *memslot,
7150 gfn_t offset, unsigned long mask)
7151{
7152 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7153}
7154
cd39e117
PB		 7155static void __pi_post_block(struct kvm_vcpu *vcpu)
7156{
7157 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7158 struct pi_desc old, new;
7159 unsigned int dest;
cd39e117
PB		 7160
7161 do {
7162 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7163 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7164 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7165
7166 dest = cpu_physical_id(vcpu->cpu);
7167
7168 if (x2apic_enabled())
7169 new.ndst = dest;
7170 else
7171 new.ndst = (dest << 8) & 0xFF00;
7172
cd39e117
PB		 7173 /* set 'NV' to 'notification vector' */
7174 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7175 } while (cmpxchg64(&pi_desc->control, old.control,
7176 new.control) != old.control);
cd39e117 7177
8b306e2f
PB		 7178 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7179 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7180 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7181 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7182 vcpu->pre_pcpu = -1;
7183 }
7184}
7185
bf9f6ac8
FW		 7186/*
7187 * This routine does the following things for vCPU which is going
7188 * to be blocked if VT-d PI is enabled.
7189 * - Store the vCPU to the wakeup list, so when interrupts happen
7190 * we can find the right vCPU to wake up.
7191 * - Change the Posted-interrupt descriptor as below:
7192 * 'NDST' <-- vcpu->pre_pcpu
7193 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7194 * - If 'ON' is set during this process, which means at least one
7195 * interrupt is posted for this vCPU, we cannot block it, in
7196 * this case, return 1, otherwise, return 0.
7197 *
7198 */
bc22512b 7199static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7200{
bf9f6ac8
FW		 7201 unsigned int dest;
7202 struct pi_desc old, new;
7203 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7204
7205 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7206 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7207 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7208 return 0;
7209
8b306e2f
PB		 7210 WARN_ON(irqs_disabled());
7211 local_irq_disable();
7212 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7213 vcpu->pre_pcpu = vcpu->cpu;
7214 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7215 list_add_tail(&vcpu->blocked_vcpu_list,
7216 &per_cpu(blocked_vcpu_on_cpu,
7217 vcpu->pre_pcpu));
7218 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7219 }
bf9f6ac8
FW		 7220
7221 do {
7222 old.control = new.control = pi_desc->control;
7223
bf9f6ac8
FW		 7224 WARN((pi_desc->sn == 1),
7225 "Warning: SN field of posted-interrupts "
7226 "is set before blocking\n");
7227
7228 /*
7229 * Since vCPU can be preempted during this process,
7230 * vcpu->cpu could be different with pre_pcpu, we
7231 * need to set pre_pcpu as the destination of wakeup
7232 * notification event, then we can find the right vCPU
7233 * to wakeup in wakeup handler if interrupts happen
7234 * when the vCPU is in blocked state.
7235 */
7236 dest = cpu_physical_id(vcpu->pre_pcpu);
7237
7238 if (x2apic_enabled())
7239 new.ndst = dest;
7240 else
7241 new.ndst = (dest << 8) & 0xFF00;
7242
7243 /* set 'NV' to 'wakeup vector' */
7244 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7245 } while (cmpxchg64(&pi_desc->control, old.control,
7246 new.control) != old.control);
bf9f6ac8 7247
8b306e2f
PB		 7248 /* We should not block the vCPU if an interrupt is posted for it. */
7249 if (pi_test_on(pi_desc) == 1)
7250 __pi_post_block(vcpu);
7251
7252 local_irq_enable();
7253 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7254}
7255
bc22512b
YJ		 7256static int vmx_pre_block(struct kvm_vcpu *vcpu)
7257{
7258 if (pi_pre_block(vcpu))
7259 return 1;
7260
64672c95
YJ		 7261 if (kvm_lapic_hv_timer_in_use(vcpu))
7262 kvm_lapic_switch_to_sw_timer(vcpu);
7263
bc22512b
YJ		 7264 return 0;
7265}
7266
7267static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7268{
8b306e2f 7269 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7270 return;
7271
8b306e2f
PB		 7272 WARN_ON(irqs_disabled());
7273 local_irq_disable();
cd39e117 7274 __pi_post_block(vcpu);
8b306e2f 7275 local_irq_enable();
bf9f6ac8
FW		 7276}
7277
bc22512b
YJ		 7278static void vmx_post_block(struct kvm_vcpu *vcpu)
7279{
64672c95
YJ		 7280 if (kvm_x86_ops->set_hv_timer)
7281 kvm_lapic_switch_to_hv_timer(vcpu);
7282
bc22512b
YJ		 7283 pi_post_block(vcpu);
7284}
7285
efc64404
FW		 7286/*
7287 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7288 *
7289 * @kvm: kvm
7290 * @host_irq: host irq of the interrupt
7291 * @guest_irq: gsi of the interrupt
7292 * @set: set or unset PI
7293 * returns 0 on success, < 0 on failure
7294 */
7295static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7296 uint32_t guest_irq, bool set)
7297{
7298 struct kvm_kernel_irq_routing_entry *e;
7299 struct kvm_irq_routing_table *irq_rt;
7300 struct kvm_lapic_irq irq;
7301 struct kvm_vcpu *vcpu;
7302 struct vcpu_data vcpu_info;
3a8b0677 7303 int idx, ret = 0;
efc64404
FW		 7304
7305 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7306 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7307 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7308 return 0;
7309
7310 idx = srcu_read_lock(&kvm->irq_srcu);
7311 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7312 if (guest_irq >= irq_rt->nr_rt_entries ||
7313 hlist_empty(&irq_rt->map[guest_irq])) {
7314 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7315 guest_irq, irq_rt->nr_rt_entries);
7316 goto out;
7317 }
efc64404
FW		 7318
7319 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7320 if (e->type != KVM_IRQ_ROUTING_MSI)
7321 continue;
7322 /*
7323 * VT-d PI cannot support posting multicast/broadcast
7324 * interrupts to a vCPU, we still use interrupt remapping
7325 * for these kind of interrupts.
7326 *
7327 * For lowest-priority interrupts, we only support
7328 * those with single CPU as the destination, e.g. user
7329 * configures the interrupts via /proc/irq or uses
7330 * irqbalance to make the interrupts single-CPU.
7331 *
7332 * We will support full lowest-priority interrupt later.
7333 */
7334
37131313 7335 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW		 7336 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
7337 /*
7338 * Make sure the IRTE is in remapped mode if
7339 * we don't handle it in posted mode.
7340 */
7341 ret = irq_set_vcpu_affinity(host_irq, NULL);
7342 if (ret < 0) {
7343 printk(KERN_INFO
7344 "failed to back to remapped mode, irq: %u\n",
7345 host_irq);
7346 goto out;
7347 }
7348
efc64404 7349 continue;
23a1c257 7350 }
efc64404
FW		 7351
7352 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7353 vcpu_info.vector = irq.vector;
7354
2698d82e 7355 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7356 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7357
7358 if (set)
7359 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7360 else
efc64404 7361 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7362
7363 if (ret < 0) {
7364 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7365 __func__);
7366 goto out;
7367 }
7368 }
7369
7370 ret = 0;
7371out:
7372 srcu_read_unlock(&kvm->irq_srcu, idx);
7373 return ret;
7374}
7375
c45dcc71
AR		 7376static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7377{
7378 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7379 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7380 FEATURE_CONTROL_LMCE;
7381 else
7382 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7383 ~FEATURE_CONTROL_LMCE;
7384}
7385
72d7b374
LP		 7386static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7387{
72e9cbdb
LP		 7388 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7389 if (to_vmx(vcpu)->nested.nested_run_pending)
7390 return 0;
72d7b374
LP		 7391 return 1;
7392}
7393
0234bf88
LP		 7394static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7395{
72e9cbdb
LP		 7396 struct vcpu_vmx *vmx = to_vmx(vcpu);
7397
7398 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7399 if (vmx->nested.smm.guest_mode)
7400 nested_vmx_vmexit(vcpu, -1, 0, 0);
7401
7402 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7403 vmx->nested.vmxon = false;
caa057a2 7404 vmx_clear_hlt(vcpu);
0234bf88
LP		 7405 return 0;
7406}
7407
ed19321f 7408static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7409{
72e9cbdb
LP		 7410 struct vcpu_vmx *vmx = to_vmx(vcpu);
7411 int ret;
7412
7413 if (vmx->nested.smm.vmxon) {
7414 vmx->nested.vmxon = true;
7415 vmx->nested.smm.vmxon = false;
7416 }
7417
7418 if (vmx->nested.smm.guest_mode) {
a633e41e 7419 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7420 if (ret)
7421 return ret;
7422
7423 vmx->nested.smm.guest_mode = false;
7424 }
0234bf88
LP		 7425 return 0;
7426}
7427
cc3d967f
LP		 7428static int enable_smi_window(struct kvm_vcpu *vcpu)
7429{
7430 return 0;
7431}
7432
05d5a486
SB		 7433static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7434{
7435 return 0;
7436}
7437
a3203381
SC		 7438static __init int hardware_setup(void)
7439{
7440 unsigned long host_bndcfgs;
7441 int r, i;
7442
7443 rdmsrl_safe(MSR_EFER, &host_efer);
7444
7445 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7446 kvm_define_shared_msr(i, vmx_msr_index[i]);
7447
7448 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7449 return -EIO;
7450
7451 if (boot_cpu_has(X86_FEATURE_NX))
7452 kvm_enable_efer_bits(EFER_NX);
7453
7454 if (boot_cpu_has(X86_FEATURE_MPX)) {
7455 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7456 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7457 }
7458
7459 if (boot_cpu_has(X86_FEATURE_XSAVES))
7460 rdmsrl(MSR_IA32_XSS, host_xss);
7461
7462 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7463 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7464 enable_vpid = 0;
7465
7466 if (!cpu_has_vmx_ept() ||
7467 !cpu_has_vmx_ept_4levels() ||
7468 !cpu_has_vmx_ept_mt_wb() ||
7469 !cpu_has_vmx_invept_global())
7470 enable_ept = 0;
7471
7472 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7473 enable_ept_ad_bits = 0;
7474
7475 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7476 enable_unrestricted_guest = 0;
7477
7478 if (!cpu_has_vmx_flexpriority())
7479 flexpriority_enabled = 0;
7480
7481 if (!cpu_has_virtual_nmis())
7482 enable_vnmi = 0;
7483
7484 /*
7485 * set_apic_access_page_addr() is used to reload apic access
7486 * page upon invalidation. No need to do anything if not
7487 * using the APIC_ACCESS_ADDR VMCS field.
7488 */
7489 if (!flexpriority_enabled)
7490 kvm_x86_ops->set_apic_access_page_addr = NULL;
7491
7492 if (!cpu_has_vmx_tpr_shadow())
7493 kvm_x86_ops->update_cr8_intercept = NULL;
7494
7495 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7496 kvm_disable_largepages();
7497
7498#if IS_ENABLED(CONFIG_HYPERV)
7499 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7500 && enable_ept) {
7501 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7502 kvm_x86_ops->tlb_remote_flush_with_range =
7503 hv_remote_flush_tlb_with_range;
7504 }
a3203381
SC		 7505#endif
7506
7507 if (!cpu_has_vmx_ple()) {
7508 ple_gap = 0;
7509 ple_window = 0;
7510 ple_window_grow = 0;
7511 ple_window_max = 0;
7512 ple_window_shrink = 0;
7513 }
7514
7515 if (!cpu_has_vmx_apicv()) {
7516 enable_apicv = 0;
7517 kvm_x86_ops->sync_pir_to_irr = NULL;
7518 }
7519
7520 if (cpu_has_vmx_tsc_scaling()) {
7521 kvm_has_tsc_control = true;
7522 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7523 kvm_tsc_scaling_ratio_frac_bits = 48;
7524 }
7525
7526 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7527
7528 if (enable_ept)
7529 vmx_enable_tdp();
7530 else
7531 kvm_disable_tdp();
7532
a3203381
SC		 7533 /*
7534 * Only enable PML when hardware supports PML feature, and both EPT
7535 * and EPT A/D bit features are enabled -- PML depends on them to work.
7536 */
7537 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7538 enable_pml = 0;
7539
7540 if (!enable_pml) {
7541 kvm_x86_ops->slot_enable_log_dirty = NULL;
7542 kvm_x86_ops->slot_disable_log_dirty = NULL;
7543 kvm_x86_ops->flush_log_dirty = NULL;
7544 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7545 }
7546
7547 if (!cpu_has_vmx_preemption_timer())
7548 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7549
7550 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7551 u64 vmx_msr;
7552
7553 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7554 cpu_preemption_timer_multi =
7555 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7556 } else {
7557 kvm_x86_ops->set_hv_timer = NULL;
7558 kvm_x86_ops->cancel_hv_timer = NULL;
7559 }
7560
a3203381 7561 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7562
7563 kvm_mce_cap_supported |= MCG_LMCE_P;
7564
f99e3daf
CP		 7565 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7566 return -EINVAL;
7567 if (!enable_ept || !cpu_has_vmx_intel_pt())
7568 pt_mode = PT_MODE_SYSTEM;
7569
a3203381 7570 if (nested) {
3e8eaccc
SC		 7571 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7572 vmx_capability.ept, enable_apicv);
7573
e4027cfa 7574 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7575 if (r)
7576 return r;
7577 }
7578
7579 r = alloc_kvm_area();
7580 if (r)
7581 nested_vmx_hardware_unsetup();
7582 return r;
7583}
7584
7585static __exit void hardware_unsetup(void)
7586{
7587 if (nested)
7588 nested_vmx_hardware_unsetup();
7589
7590 free_kvm_area();
7591}
7592
404f6aac 7593static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7594 .cpu_has_kvm_support = cpu_has_kvm_support,
7595 .disabled_by_bios = vmx_disabled_by_bios,
7596 .hardware_setup = hardware_setup,
7597 .hardware_unsetup = hardware_unsetup,
002c7f7c 7598 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7599 .hardware_enable = hardware_enable,
7600 .hardware_disable = hardware_disable,
04547156 7601 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7602 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7603
b31c114b 7604 .vm_init = vmx_vm_init,
434a1e94
SC		 7605 .vm_alloc = vmx_vm_alloc,
7606 .vm_free = vmx_vm_free,
b31c114b 7607
6aa8b732
AK		 7608 .vcpu_create = vmx_create_vcpu,
7609 .vcpu_free = vmx_free_vcpu,
04d2cc77 7610 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7611
6d6095bd 7612 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7613 .vcpu_load = vmx_vcpu_load,
7614 .vcpu_put = vmx_vcpu_put,
7615
a96036b8 7616 .update_bp_intercept = update_exception_bitmap,
801e459a 7617 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7618 .get_msr = vmx_get_msr,
7619 .set_msr = vmx_set_msr,
7620 .get_segment_base = vmx_get_segment_base,
7621 .get_segment = vmx_get_segment,
7622 .set_segment = vmx_set_segment,
2e4d2653 7623 .get_cpl = vmx_get_cpl,
6aa8b732 7624 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7625 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7626 .decache_cr3 = vmx_decache_cr3,
25c4c276 7627 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7628 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7629 .set_cr3 = vmx_set_cr3,
7630 .set_cr4 = vmx_set_cr4,
6aa8b732 7631 .set_efer = vmx_set_efer,
6aa8b732
AK		 7632 .get_idt = vmx_get_idt,
7633 .set_idt = vmx_set_idt,
7634 .get_gdt = vmx_get_gdt,
7635 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7636 .get_dr6 = vmx_get_dr6,
7637 .set_dr6 = vmx_set_dr6,
020df079 7638 .set_dr7 = vmx_set_dr7,
81908bf4 7639 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7640 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7641 .get_rflags = vmx_get_rflags,
7642 .set_rflags = vmx_set_rflags,
be94f6b7 7643
6aa8b732 7644 .tlb_flush = vmx_flush_tlb,
faff8758 7645 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7646
6aa8b732 7647 .run = vmx_vcpu_run,
6062d012 7648 .handle_exit = vmx_handle_exit,
6aa8b732 7649 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7650 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7651 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7652 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7653 .set_irq = vmx_inject_irq,
95ba8273 7654 .set_nmi = vmx_inject_nmi,
298101da 7655 .queue_exception = vmx_queue_exception,
b463a6f7 7656 .cancel_injection = vmx_cancel_injection,
78646121 7657 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7658 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7659 .get_nmi_mask = vmx_get_nmi_mask,
7660 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7661 .enable_nmi_window = enable_nmi_window,
7662 .enable_irq_window = enable_irq_window,
7663 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7664 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7665 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS		 7666 .get_enable_apicv = vmx_get_enable_apicv,
7667 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7668 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7669 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ		 7670 .hwapic_irr_update = vmx_hwapic_irr_update,
7671 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7672 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7673 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7674 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 7675
cbc94022 7676 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7677 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7678 .get_tdp_level = get_ept_level,
4b12f0de 7679 .get_mt_mask = vmx_get_mt_mask,
229456fc 7680
586f9607 7681 .get_exit_info = vmx_get_exit_info,
586f9607 7682
17cc3935 7683 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7684
7685 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7686
7687 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7688 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7689
7690 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7691
7692 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7693
e79f245d 7694 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7695 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7696
7697 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7698
7699 .check_intercept = vmx_check_intercept,
a547c6db 7700 .handle_external_intr = vmx_handle_external_intr,
da8999d3 7701 .mpx_supported = vmx_mpx_supported,
55412b2e 7702 .xsaves_supported = vmx_xsaves_supported,
66336cab 7703 .umip_emulated = vmx_umip_emulated,
86f5201d 7704 .pt_supported = vmx_pt_supported,
b6b8a145 7705
d264ee0c 7706 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7707
7708 .sched_in = vmx_sched_in,
843e4330
KH		 7709
7710 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7711 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7712 .flush_log_dirty = vmx_flush_log_dirty,
7713 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7714 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7715
bf9f6ac8
FW		 7716 .pre_block = vmx_pre_block,
7717 .post_block = vmx_post_block,
7718
25462f7f 7719 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7720
7721 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7722
7723#ifdef CONFIG_X86_64
7724 .set_hv_timer = vmx_set_hv_timer,
7725 .cancel_hv_timer = vmx_cancel_hv_timer,
7726#endif
c45dcc71
AR		 7727
7728 .setup_mce = vmx_setup_mce,
0234bf88 7729
72d7b374 7730 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7731 .pre_enter_smm = vmx_pre_enter_smm,
7732 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7733 .enable_smi_window = enable_smi_window,
57b119da 7734
e4027cfa
SC		 7735 .check_nested_events = NULL,
7736 .get_nested_state = NULL,
7737 .set_nested_state = NULL,
7738 .get_vmcs12_pages = NULL,
7739 .nested_enable_evmcs = NULL,
05d5a486 7740 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
6aa8b732
AK		 7741};
7742
72c6d2db 7743static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7744{
7745 if (vmx_l1d_flush_pages) {
7746 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7747 vmx_l1d_flush_pages = NULL;
7748 }
72c6d2db
TG		 7749 /* Restore state so sysfs ignores VMX */
7750 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7751}
7752
a7b9020b
TG		 7753static void vmx_exit(void)
7754{
7755#ifdef CONFIG_KEXEC_CORE
7756 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7757 synchronize_rcu();
7758#endif
7759
7760 kvm_exit();
7761
7762#if IS_ENABLED(CONFIG_HYPERV)
7763 if (static_branch_unlikely(&enable_evmcs)) {
7764 int cpu;
7765 struct hv_vp_assist_page *vp_ap;
7766 /*
7767 * Reset everything to support using non-enlightened VMCS
7768 * access later (e.g. when we reload the module with
7769 * enlightened_vmcs=0)
7770 */
7771 for_each_online_cpu(cpu) {
7772 vp_ap = hv_get_vp_assist_page(cpu);
7773
7774 if (!vp_ap)
7775 continue;
7776
7777 vp_ap->current_nested_vmcs = 0;
7778 vp_ap->enlighten_vmentry = 0;
7779 }
7780
7781 static_branch_disable(&enable_evmcs);
7782 }
7783#endif
7784 vmx_cleanup_l1d_flush();
7785}
7786module_exit(vmx_exit);
7787
6aa8b732
AK		 7788static int __init vmx_init(void)
7789{
773e8a04
VK		 7790 int r;
7791
7792#if IS_ENABLED(CONFIG_HYPERV)
7793 /*
7794 * Enlightened VMCS usage should be recommended and the host needs
7795 * to support eVMCS v1 or above. We can also disable eVMCS support
7796 * with module parameter.
7797 */
7798 if (enlightened_vmcs &&
7799 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7800 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7801 KVM_EVMCS_VERSION) {
7802 int cpu;
7803
7804 /* Check that we have assist pages on all online CPUs */
7805 for_each_online_cpu(cpu) {
7806 if (!hv_get_vp_assist_page(cpu)) {
7807 enlightened_vmcs = false;
7808 break;
7809 }
7810 }
7811
7812 if (enlightened_vmcs) {
7813 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7814 static_branch_enable(&enable_evmcs);
7815 }
7816 } else {
7817 enlightened_vmcs = false;
7818 }
7819#endif
7820
7821 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 7822 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7823 if (r)
34a1cd60 7824 return r;
25c5f225 7825
a7b9020b 7826 /*
7db92e16
TG		 7827 * Must be called after kvm_init() so enable_ept is properly set
7828 * up. Hand the parameter mitigation value in which was stored in
7829 * the pre module init parser. If no parameter was given, it will
7830 * contain 'auto' which will be turned into the default 'cond'
7831 * mitigation mode.
7832 */
7833 if (boot_cpu_has(X86_BUG_L1TF)) {
7834 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7835 if (r) {
7836 vmx_exit();
7837 return r;
7838 }
a47dd5f0 7839 }
25c5f225 7840
2965faa5 7841#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 7842 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7843 crash_vmclear_local_loaded_vmcss);
7844#endif
21ebf53b 7845 vmx_check_vmcs12_offsets();
8f536b76 7846
fdef3ad1 7847 return 0;
6aa8b732 7848}
a7b9020b 7849module_init(vmx_init);
Ubuntu Focal Linux kernel mirror