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Merge tag 'powerpc-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / vmx / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
199b118a
SC		 19#include <linux/frame.h>
20#include <linux/highmem.h>
21#include <linux/hrtimer.h>
22#include <linux/kernel.h>
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
c7addb90 25#include <linux/moduleparam.h>
e9bda3b3 26#include <linux/mod_devicetable.h>
199b118a 27#include <linux/mm.h>
199b118a 28#include <linux/sched.h>
b284909a 29#include <linux/sched/smt.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
199b118a 32#include <linux/trace_events.h>
e495606d 33
199b118a 34#include <asm/apic.h>
fd8ca6da 35#include <asm/asm.h>
28b835d6 36#include <asm/cpu.h>
199b118a 37#include <asm/debugreg.h>
3b3be0d1 38#include <asm/desc.h>
952f07ec 39#include <asm/fpu/internal.h>
199b118a 40#include <asm/io.h>
efc64404 41#include <asm/irq_remapping.h>
199b118a
SC		 42#include <asm/kexec.h>
43#include <asm/perf_event.h>
44#include <asm/mce.h>
d6e41f11 45#include <asm/mmu_context.h>
773e8a04 46#include <asm/mshyperv.h>
199b118a
SC		 47#include <asm/spec-ctrl.h>
48#include <asm/virtext.h>
49#include <asm/vmx.h>
6aa8b732 50
3077c191 51#include "capabilities.h"
199b118a 52#include "cpuid.h"
4cebd747 53#include "evmcs.h"
199b118a
SC		 54#include "irq.h"
55#include "kvm_cache_regs.h"
56#include "lapic.h"
57#include "mmu.h"
55d2375e 58#include "nested.h"
89b0c9f5 59#include "ops.h"
25462f7f 60#include "pmu.h"
199b118a 61#include "trace.h"
cb1d474b 62#include "vmcs.h"
609363cf 63#include "vmcs12.h"
89b0c9f5 64#include "vmx.h"
199b118a 65#include "x86.h"
229456fc 66
6aa8b732
AK		 67MODULE_AUTHOR("Qumranet");
68MODULE_LICENSE("GPL");
69
e9bda3b3
JT		 70static const struct x86_cpu_id vmx_cpu_id[] = {
71 X86_FEATURE_MATCH(X86_FEATURE_VMX),
72 {}
73};
74MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
75
2c4fd91d 76bool __read_mostly enable_vpid = 1;
736caefe 77module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 78
d02fcf50
PB		 79static bool __read_mostly enable_vnmi = 1;
80module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
81
2c4fd91d 82bool __read_mostly flexpriority_enabled = 1;
736caefe 83module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 84
2c4fd91d 85bool __read_mostly enable_ept = 1;
736caefe 86module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 87
2c4fd91d 88bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 89module_param_named(unrestricted_guest,
90 enable_unrestricted_guest, bool, S_IRUGO);
91
2c4fd91d 92bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 93module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
94
a27685c3 95static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 96module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 97
476bc001 98static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 99module_param(fasteoi, bool, S_IRUGO);
100
5a71785d 101static bool __read_mostly enable_apicv = 1;
01e439be 102module_param(enable_apicv, bool, S_IRUGO);
83d4c286 103
801d3424
NHE		 104/*
105 * If nested=1, nested virtualization is supported, i.e., guests may use
106 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
107 * use VMX instructions.
108 */
1e58e5e5 109static bool __read_mostly nested = 1;
801d3424
NHE		 110module_param(nested, bool, S_IRUGO);
111
20300099
WL		 112static u64 __read_mostly host_xss;
113
2c4fd91d 114bool __read_mostly enable_pml = 1;
843e4330
KH		 115module_param_named(pml, enable_pml, bool, S_IRUGO);
116
904e14fb
PB		 117#define MSR_BITMAP_MODE_X2APIC 1
118#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 119
64903d61
HZ		 120#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
121
64672c95
YJ		 122/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123static int __read_mostly cpu_preemption_timer_multi;
124static bool __read_mostly enable_preemption_timer = 1;
125#ifdef CONFIG_X86_64
126module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127#endif
128
3de6347b 129#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 130#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131#define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 134#define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 137
5dc1f044 138#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 139#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
141
78ac8b47
AK		 142#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
143
bf8c55d8
CP		 144#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
148
149#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151
4b8d54f9
ZE		 152/*
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 156 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
162 */
c8e88717 163static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 164module_param(ple_gap, uint, 0444);
b4a2d31d 165
7fbc85a5
BM		 166static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167module_param(ple_window, uint, 0444);
4b8d54f9 168
b4a2d31d 169/* Default doubles per-vcpu window every exit. */
c8e88717 170static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 171module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 172
173/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 174static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 175module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 176
177/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 178static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, uint, 0444);
b4a2d31d 180
f99e3daf
CP		 181/* Default is SYSTEM mode, 1 for host-guest mode */
182int __read_mostly pt_mode = PT_MODE_SYSTEM;
183module_param(pt_mode, int, S_IRUGO);
184
a399477e 185static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 186static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 187static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 188
7db92e16
TG		 189/* Storage for pre module init parameter parsing */
190static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 191
192static const struct {
193 const char *option;
0027ff2a 194 bool for_parse;
a399477e 195} vmentry_l1d_param[] = {
0027ff2a
PB		 196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 202};
203
7db92e16
TG		 204#define L1D_CACHE_ORDER 4
205static void *vmx_l1d_flush_pages;
206
207static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 208{
7db92e16 209 struct page *page;
288d152c 210 unsigned int i;
a399477e 211
7db92e16
TG		 212 if (!enable_ept) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
214 return 0;
a399477e
KRW		 215 }
216
d806afa4
YW		 217 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
218 u64 msr;
219
220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
221 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
222 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
223 return 0;
224 }
225 }
8e0b2b91 226
d90a7a0e
JK		 227 /* If set to auto use the default l1tf mitigation method */
228 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
229 switch (l1tf_mitigation) {
230 case L1TF_MITIGATION_OFF:
231 l1tf = VMENTER_L1D_FLUSH_NEVER;
232 break;
233 case L1TF_MITIGATION_FLUSH_NOWARN:
234 case L1TF_MITIGATION_FLUSH:
235 case L1TF_MITIGATION_FLUSH_NOSMT:
236 l1tf = VMENTER_L1D_FLUSH_COND;
237 break;
238 case L1TF_MITIGATION_FULL:
239 case L1TF_MITIGATION_FULL_FORCE:
240 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
241 break;
242 }
243 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
244 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
245 }
246
7db92e16
TG		 247 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
248 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 249 /*
250 * This allocation for vmx_l1d_flush_pages is not tied to a VM
251 * lifetime and so should not be charged to a memcg.
252 */
7db92e16
TG		 253 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
254 if (!page)
255 return -ENOMEM;
256 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 257
258 /*
259 * Initialize each page with a different pattern in
260 * order to protect against KSM in the nested
261 * virtualization case.
262 */
263 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
264 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
265 PAGE_SIZE);
266 }
7db92e16
TG		 267 }
268
269 l1tf_vmx_mitigation = l1tf;
270
895ae47f
TG		 271 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
272 static_branch_enable(&vmx_l1d_should_flush);
273 else
274 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 275
427362a1
NS		 276 if (l1tf == VMENTER_L1D_FLUSH_COND)
277 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 278 else
427362a1 279 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 280 return 0;
281}
282
283static int vmentry_l1d_flush_parse(const char *s)
284{
285 unsigned int i;
286
287 if (s) {
288 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 289 if (vmentry_l1d_param[i].for_parse &&
290 sysfs_streq(s, vmentry_l1d_param[i].option))
291 return i;
7db92e16
TG		 292 }
293 }
a399477e
KRW		 294 return -EINVAL;
295}
296
7db92e16
TG		 297static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
298{
dd4bfa73 299 int l1tf, ret;
7db92e16 300
7db92e16
TG		 301 l1tf = vmentry_l1d_flush_parse(s);
302 if (l1tf < 0)
303 return l1tf;
304
0027ff2a
PB		 305 if (!boot_cpu_has(X86_BUG_L1TF))
306 return 0;
307
7db92e16
TG		 308 /*
309 * Has vmx_init() run already? If not then this is the pre init
310 * parameter parsing. In that case just store the value and let
311 * vmx_init() do the proper setup after enable_ept has been
312 * established.
313 */
314 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
315 vmentry_l1d_flush_param = l1tf;
316 return 0;
317 }
318
dd4bfa73
TG		 319 mutex_lock(&vmx_l1d_flush_mutex);
320 ret = vmx_setup_l1d_flush(l1tf);
321 mutex_unlock(&vmx_l1d_flush_mutex);
322 return ret;
7db92e16
TG		 323}
324
a399477e
KRW		 325static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
326{
0027ff2a
PB		 327 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
328 return sprintf(s, "???\n");
329
7db92e16 330 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 331}
332
333static const struct kernel_param_ops vmentry_l1d_flush_ops = {
334 .set = vmentry_l1d_flush_set,
335 .get = vmentry_l1d_flush_get,
336};
895ae47f 337module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 338
d99e4152
GN		 339static bool guest_state_valid(struct kvm_vcpu *vcpu);
340static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 341static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 342 u32 msr, int type);
75880a01 343
453eafbe
SC		 344void vmx_vmexit(void);
345
6aa8b732 346static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 347DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 348/*
349 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
350 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
351 */
352static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 353
bf9f6ac8
FW		 354/*
355 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
356 * can find which vCPU should be waken up.
357 */
358static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
359static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
360
2384d2b3
SY		 361static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
362static DEFINE_SPINLOCK(vmx_vpid_lock);
363
3077c191
SC		 364struct vmcs_config vmcs_config;
365struct vmx_capability vmx_capability;
d56f546d 366
6aa8b732
AK		 367#define VMX_SEGMENT_FIELD(seg) \
368 [VCPU_SREG_##seg] = { \
369 .selector = GUEST_##seg##_SELECTOR, \
370 .base = GUEST_##seg##_BASE, \
371 .limit = GUEST_##seg##_LIMIT, \
372 .ar_bytes = GUEST_##seg##_AR_BYTES, \
373 }
374
772e0318 375static const struct kvm_vmx_segment_field {
6aa8b732
AK		 376 unsigned selector;
377 unsigned base;
378 unsigned limit;
379 unsigned ar_bytes;
380} kvm_vmx_segment_fields[] = {
381 VMX_SEGMENT_FIELD(CS),
382 VMX_SEGMENT_FIELD(DS),
383 VMX_SEGMENT_FIELD(ES),
384 VMX_SEGMENT_FIELD(FS),
385 VMX_SEGMENT_FIELD(GS),
386 VMX_SEGMENT_FIELD(SS),
387 VMX_SEGMENT_FIELD(TR),
388 VMX_SEGMENT_FIELD(LDTR),
389};
390
cf3646eb 391u64 host_efer;
26bb0981 392
4d56c8a7 393/*
898a811f
JM		 394 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
395 * will emulate SYSCALL in legacy mode if the vendor string in guest
396 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
397 * support this emulation, IA32_STAR must always be included in
398 * vmx_msr_index[], even in i386 builds.
4d56c8a7 399 */
cf3646eb 400const u32 vmx_msr_index[] = {
05b3e0c2 401#ifdef CONFIG_X86_64
44ea2b17 402 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 403#endif
8c06585d 404 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 405};
6aa8b732 406
773e8a04
VK		 407#if IS_ENABLED(CONFIG_HYPERV)
408static bool __read_mostly enlightened_vmcs = true;
409module_param(enlightened_vmcs, bool, 0444);
410
877ad952
TL		 411/* check_ept_pointer() should be under protection of ept_pointer_lock. */
412static void check_ept_pointer_match(struct kvm *kvm)
413{
414 struct kvm_vcpu *vcpu;
415 u64 tmp_eptp = INVALID_PAGE;
416 int i;
417
418 kvm_for_each_vcpu(i, vcpu, kvm) {
419 if (!VALID_PAGE(tmp_eptp)) {
420 tmp_eptp = to_vmx(vcpu)->ept_pointer;
421 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
422 to_kvm_vmx(kvm)->ept_pointers_match
423 = EPT_POINTERS_MISMATCH;
424 return;
425 }
426 }
427
428 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
429}
430
8997f657 431static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 432 void *data)
433{
434 struct kvm_tlb_range *range = data;
435
436 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
437 range->pages);
438}
439
440static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
441 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
442{
443 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
444
445 /*
446 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
447 * of the base of EPT PML4 table, strip off EPT configuration
448 * information.
449 */
450 if (range)
451 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
452 kvm_fill_hv_flush_list_func, (void *)range);
453 else
454 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
455}
456
457static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
458 struct kvm_tlb_range *range)
877ad952 459{
a5c214da 460 struct kvm_vcpu *vcpu;
b7c1c226 461 int ret = 0, i;
877ad952
TL		 462
463 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
464
465 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
466 check_ept_pointer_match(kvm);
467
468 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 469 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 470 /* If ept_pointer is invalid pointer, bypass flush request. */
471 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
472 ret |= __hv_remote_flush_tlb_with_range(
473 kvm, vcpu, range);
53963a70 474 }
a5c214da 475 } else {
1f3a3e46
LT		 476 ret = __hv_remote_flush_tlb_with_range(kvm,
477 kvm_get_vcpu(kvm, 0), range);
877ad952 478 }
877ad952 479
877ad952
TL		 480 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
481 return ret;
482}
1f3a3e46
LT		 483static int hv_remote_flush_tlb(struct kvm *kvm)
484{
485 return hv_remote_flush_tlb_with_range(kvm, NULL);
486}
487
773e8a04
VK		 488#endif /* IS_ENABLED(CONFIG_HYPERV) */
489
64672c95
YJ		 490/*
491 * Comment's format: document - errata name - stepping - processor name.
492 * Refer from
493 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
494 */
495static u32 vmx_preemption_cpu_tfms[] = {
496/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
4970x000206E6,
498/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
499/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
500/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5010x00020652,
502/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5030x00020655,
504/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
505/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
506/*
507 * 320767.pdf - AAP86 - B1 -
508 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
509 */
5100x000106E5,
511/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5120x000106A0,
513/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5140x000106A1,
515/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5160x000106A4,
517 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
518 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
519 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5200x000106A5,
3d82c565
WH		 521 /* Xeon E3-1220 V2 */
5220x000306A8,
64672c95
YJ		 523};
524
525static inline bool cpu_has_broken_vmx_preemption_timer(void)
526{
527 u32 eax = cpuid_eax(0x00000001), i;
528
529 /* Clear the reserved bits */
530 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 531 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 532 if (eax == vmx_preemption_cpu_tfms[i])
533 return true;
534
535 return false;
536}
537
35754c98 538static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 539{
35754c98 540 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 541}
542
04547156
SY		 543static inline bool report_flexpriority(void)
544{
545 return flexpriority_enabled;
546}
547
97b7ead3 548static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 549{
550 int i;
551
a2fa3e9f 552 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 553 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 554 return i;
555 return -1;
556}
557
97b7ead3 558struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 559{
560 int i;
561
8b9cf98c 562 i = __find_msr_index(vmx, msr);
a75beee6 563 if (i >= 0)
a2fa3e9f 564 return &vmx->guest_msrs[i];
8b6d44c7 565 return NULL;
7725f0ba
AK		 566}
567
7c97fcb3
SC		 568void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
569{
570 vmcs_clear(loaded_vmcs->vmcs);
571 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
572 vmcs_clear(loaded_vmcs->shadow_vmcs);
573 loaded_vmcs->cpu = -1;
574 loaded_vmcs->launched = 0;
575}
576
2965faa5 577#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 578/*
579 * This bitmap is used to indicate whether the vmclear
580 * operation is enabled on all cpus. All disabled by
581 * default.
582 */
583static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
584
585static inline void crash_enable_local_vmclear(int cpu)
586{
587 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
588}
589
590static inline void crash_disable_local_vmclear(int cpu)
591{
592 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
593}
594
595static inline int crash_local_vmclear_enabled(int cpu)
596{
597 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
598}
599
600static void crash_vmclear_local_loaded_vmcss(void)
601{
602 int cpu = raw_smp_processor_id();
603 struct loaded_vmcs *v;
604
605 if (!crash_local_vmclear_enabled(cpu))
606 return;
607
608 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
609 loaded_vmcss_on_cpu_link)
610 vmcs_clear(v->vmcs);
611}
612#else
613static inline void crash_enable_local_vmclear(int cpu) { }
614static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 615#endif /* CONFIG_KEXEC_CORE */
8f536b76 616
d462b819 617static void __loaded_vmcs_clear(void *arg)
6aa8b732 618{
d462b819 619 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 620 int cpu = raw_smp_processor_id();
6aa8b732 621
d462b819
NHE		 622 if (loaded_vmcs->cpu != cpu)
623 return; /* vcpu migration can race with cpu offline */
624 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 625 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 626 crash_disable_local_vmclear(cpu);
d462b819 627 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 628
629 /*
630 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
631 * is before setting loaded_vmcs->vcpu to -1 which is done in
632 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
633 * then adds the vmcs into percpu list before it is deleted.
634 */
635 smp_wmb();
636
d462b819 637 loaded_vmcs_init(loaded_vmcs);
8f536b76 638 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 639}
640
89b0c9f5 641void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 642{
e6c7d321
XG		 643 int cpu = loaded_vmcs->cpu;
644
645 if (cpu != -1)
646 smp_call_function_single(cpu,
647 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 648}
649
2fb92db1
AK		 650static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
651 unsigned field)
652{
653 bool ret;
654 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
655
656 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
657 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
658 vmx->segment_cache.bitmask = 0;
659 }
660 ret = vmx->segment_cache.bitmask & mask;
661 vmx->segment_cache.bitmask |= mask;
662 return ret;
663}
664
665static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
666{
667 u16 *p = &vmx->segment_cache.seg[seg].selector;
668
669 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
670 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
671 return *p;
672}
673
674static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
675{
676 ulong *p = &vmx->segment_cache.seg[seg].base;
677
678 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
679 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
680 return *p;
681}
682
683static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
684{
685 u32 *p = &vmx->segment_cache.seg[seg].limit;
686
687 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
688 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
689 return *p;
690}
691
692static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
693{
694 u32 *p = &vmx->segment_cache.seg[seg].ar;
695
696 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
697 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
698 return *p;
699}
700
97b7ead3 701void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 702{
703 u32 eb;
704
fd7373cc 705 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 706 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 707 /*
708 * Guest access to VMware backdoor ports could legitimately
709 * trigger #GP because of TSS I/O permission bitmap.
710 * We intercept those #GP and allow access to them anyway
711 * as VMware does.
712 */
713 if (enable_vmware_backdoor)
714 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 715 if ((vcpu->guest_debug &
716 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
717 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
718 eb |= 1u << BP_VECTOR;
7ffd92c5 719 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 720 eb = ~0;
089d034e 721 if (enable_ept)
1439442c 722 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 723
724 /* When we are running a nested L2 guest and L1 specified for it a
725 * certain exception bitmap, we must trap the same exceptions and pass
726 * them to L1. When running L2, we will only handle the exceptions
727 * specified above if L1 did not want them.
728 */
729 if (is_guest_mode(vcpu))
730 eb |= get_vmcs12(vcpu)->exception_bitmap;
731
abd3f2d6
AK		 732 vmcs_write32(EXCEPTION_BITMAP, eb);
733}
734
d28b387f
KA		 735/*
736 * Check if MSR is intercepted for currently loaded MSR bitmap.
737 */
738static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
739{
740 unsigned long *msr_bitmap;
741 int f = sizeof(unsigned long);
742
743 if (!cpu_has_vmx_msr_bitmap())
744 return true;
745
746 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
747
748 if (msr <= 0x1fff) {
749 return !!test_bit(msr, msr_bitmap + 0x800 / f);
750 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
751 msr &= 0x1fff;
752 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
753 }
754
755 return true;
756}
757
2961e876
GN		 758static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
759 unsigned long entry, unsigned long exit)
8bf00a52 760{
2961e876
GN		 761 vm_entry_controls_clearbit(vmx, entry);
762 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 763}
764
ca83b4a7
KRW		 765static int find_msr(struct vmx_msrs *m, unsigned int msr)
766{
767 unsigned int i;
768
769 for (i = 0; i < m->nr; ++i) {
770 if (m->val[i].index == msr)
771 return i;
772 }
773 return -ENOENT;
774}
775
61d2ef2c
AK		 776static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
777{
ca83b4a7 778 int i;
61d2ef2c
AK		 779 struct msr_autoload *m = &vmx->msr_autoload;
780
8bf00a52
GN		 781 switch (msr) {
782 case MSR_EFER:
c73da3fc 783 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 784 clear_atomic_switch_msr_special(vmx,
785 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 786 VM_EXIT_LOAD_IA32_EFER);
787 return;
788 }
789 break;
790 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 791 if (cpu_has_load_perf_global_ctrl()) {
2961e876 792 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 793 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
794 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
795 return;
796 }
797 break;
110312c8 798 }
ca83b4a7
KRW		 799 i = find_msr(&m->guest, msr);
800 if (i < 0)
31907093 801 goto skip_guest;
33966dd6 802 --m->guest.nr;
33966dd6 803 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 804 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 805
31907093
KRW		 806skip_guest:
807 i = find_msr(&m->host, msr);
808 if (i < 0)
61d2ef2c 809 return;
31907093
KRW		 810
811 --m->host.nr;
812 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 813 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 814}
815
2961e876
GN		 816static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
817 unsigned long entry, unsigned long exit,
818 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
819 u64 guest_val, u64 host_val)
8bf00a52
GN		 820{
821 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 822 if (host_val_vmcs != HOST_IA32_EFER)
823 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 824 vm_entry_controls_setbit(vmx, entry);
825 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 826}
827
61d2ef2c 828static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 829 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 830{
989e3992 831 int i, j = 0;
61d2ef2c
AK		 832 struct msr_autoload *m = &vmx->msr_autoload;
833
8bf00a52
GN		 834 switch (msr) {
835 case MSR_EFER:
c73da3fc 836 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 837 add_atomic_switch_msr_special(vmx,
838 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 839 VM_EXIT_LOAD_IA32_EFER,
840 GUEST_IA32_EFER,
841 HOST_IA32_EFER,
842 guest_val, host_val);
843 return;
844 }
845 break;
846 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 847 if (cpu_has_load_perf_global_ctrl()) {
2961e876 848 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 849 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
850 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
851 GUEST_IA32_PERF_GLOBAL_CTRL,
852 HOST_IA32_PERF_GLOBAL_CTRL,
853 guest_val, host_val);
854 return;
855 }
856 break;
7099e2e1
RK		 857 case MSR_IA32_PEBS_ENABLE:
858 /* PEBS needs a quiescent period after being disabled (to write
859 * a record). Disabling PEBS through VMX MSR swapping doesn't
860 * provide that period, so a CPU could write host's record into
861 * guest's memory.
862 */
863 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 864 }
865
ca83b4a7 866 i = find_msr(&m->guest, msr);
989e3992
KRW		 867 if (!entry_only)
868 j = find_msr(&m->host, msr);
61d2ef2c 869
98ae70cc
XL		 870 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
871 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
60266204 872 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 873 "Can't add msr %x\n", msr);
874 return;
61d2ef2c 875 }
31907093 876 if (i < 0) {
ca83b4a7 877 i = m->guest.nr++;
33966dd6 878 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 879 }
989e3992
KRW		 880 m->guest.val[i].index = msr;
881 m->guest.val[i].value = guest_val;
882
883 if (entry_only)
884 return;
61d2ef2c 885
31907093
KRW		 886 if (j < 0) {
887 j = m->host.nr++;
33966dd6 888 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 889 }
31907093
KRW		 890 m->host.val[j].index = msr;
891 m->host.val[j].value = host_val;
61d2ef2c
AK		 892}
893
92c0d900 894static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 895{
844a5fe2
PB		 896 u64 guest_efer = vmx->vcpu.arch.efer;
897 u64 ignore_bits = 0;
898
899 if (!enable_ept) {
900 /*
901 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
902 * host CPUID is more efficient than testing guest CPUID
903 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
904 */
905 if (boot_cpu_has(X86_FEATURE_SMEP))
906 guest_efer |= EFER_NX;
907 else if (!(guest_efer & EFER_NX))
908 ignore_bits |= EFER_NX;
909 }
3a34a881 910
51c6cf66 911 /*
844a5fe2 912 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 913 */
844a5fe2 914 ignore_bits |= EFER_SCE;
51c6cf66
AK		 915#ifdef CONFIG_X86_64
916 ignore_bits |= EFER_LMA | EFER_LME;
917 /* SCE is meaningful only in long mode on Intel */
918 if (guest_efer & EFER_LMA)
919 ignore_bits &= ~(u64)EFER_SCE;
920#endif
84ad33ef 921
f6577a5f
AL		 922 /*
923 * On EPT, we can't emulate NX, so we must switch EFER atomically.
924 * On CPUs that support "load IA32_EFER", always switch EFER
925 * atomically, since it's faster than switching it manually.
926 */
c73da3fc 927 if (cpu_has_load_ia32_efer() ||
f6577a5f 928 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 929 if (!(guest_efer & EFER_LMA))
930 guest_efer &= ~EFER_LME;
54b98bff
AL		 931 if (guest_efer != host_efer)
932 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 933 guest_efer, host_efer, false);
02343cf2
SC		 934 else
935 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 936 return false;
844a5fe2 937 } else {
02343cf2
SC		 938 clear_atomic_switch_msr(vmx, MSR_EFER);
939
844a5fe2
PB		 940 guest_efer &= ~ignore_bits;
941 guest_efer |= host_efer & ignore_bits;
942
943 vmx->guest_msrs[efer_offset].data = guest_efer;
944 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 945
844a5fe2
PB		 946 return true;
947 }
51c6cf66
AK		 948}
949
e28baead
AL		 950#ifdef CONFIG_X86_32
951/*
952 * On 32-bit kernels, VM exits still load the FS and GS bases from the
953 * VMCS rather than the segment table. KVM uses this helper to figure
954 * out the current bases to poke them into the VMCS before entry.
955 */
2d49ec72
GN		 956static unsigned long segment_base(u16 selector)
957{
8c2e41f7 958 struct desc_struct *table;
2d49ec72
GN		 959 unsigned long v;
960
8c2e41f7 961 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 962 return 0;
963
45fc8757 964 table = get_current_gdt_ro();
2d49ec72 965
8c2e41f7 966 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 967 u16 ldt_selector = kvm_read_ldt();
968
8c2e41f7 969 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 970 return 0;
971
8c2e41f7 972 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 973 }
8c2e41f7 974 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 975 return v;
976}
e28baead 977#endif
2d49ec72 978
2ef444f1
CP		 979static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
980{
981 u32 i;
982
983 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
984 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
985 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
986 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
987 for (i = 0; i < addr_range; i++) {
988 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
989 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
990 }
991}
992
993static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
994{
995 u32 i;
996
997 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
998 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
999 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1000 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1001 for (i = 0; i < addr_range; i++) {
1002 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1003 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1004 }
1005}
1006
1007static void pt_guest_enter(struct vcpu_vmx *vmx)
1008{
1009 if (pt_mode == PT_MODE_SYSTEM)
1010 return;
1011
2ef444f1 1012 /*
b08c2896
CP		 1013 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1014 * Save host state before VM entry.
2ef444f1 1015 */
b08c2896 1016 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1017 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1018 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1019 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1020 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1021 }
1022}
1023
1024static void pt_guest_exit(struct vcpu_vmx *vmx)
1025{
1026 if (pt_mode == PT_MODE_SYSTEM)
1027 return;
1028
1029 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1030 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1031 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1032 }
1033
1034 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1035 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1036}
1037
97b7ead3 1038void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1039{
04d2cc77 1040 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1041 struct vmcs_host_state *host_state;
51e8a8cc 1042#ifdef CONFIG_X86_64
35060ed6 1043 int cpu = raw_smp_processor_id();
51e8a8cc 1044#endif
e368b875
SC		 1045 unsigned long fs_base, gs_base;
1046 u16 fs_sel, gs_sel;
26bb0981 1047 int i;
04d2cc77 1048
d264ee0c
SC		 1049 vmx->req_immediate_exit = false;
1050
f48b4711
LA		 1051 /*
1052 * Note that guest MSRs to be saved/restored can also be changed
1053 * when guest state is loaded. This happens when guest transitions
1054 * to/from long-mode by setting MSR_EFER.LMA.
1055 */
1056 if (!vmx->loaded_cpu_state || vmx->guest_msrs_dirty) {
1057 vmx->guest_msrs_dirty = false;
1058 for (i = 0; i < vmx->save_nmsrs; ++i)
1059 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1060 vmx->guest_msrs[i].data,
1061 vmx->guest_msrs[i].mask);
1062
1063 }
1064
bd9966de 1065 if (vmx->loaded_cpu_state)
33ed6329
AK		 1066 return;
1067
bd9966de 1068 vmx->loaded_cpu_state = vmx->loaded_vmcs;
d7ee039e 1069 host_state = &vmx->loaded_cpu_state->host_state;
bd9966de 1070
33ed6329
AK		 1071 /*
1072 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1073 * allow segment selectors with cpl > 0 or ti == 1.
1074 */
d7ee039e 1075 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1076
1077#ifdef CONFIG_X86_64
d7ee039e
SC		 1078 savesegment(ds, host_state->ds_sel);
1079 savesegment(es, host_state->es_sel);
e368b875
SC		 1080
1081 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1082 if (likely(is_64bit_mm(current->mm))) {
1083 save_fsgs_for_kvm();
e368b875
SC		 1084 fs_sel = current->thread.fsindex;
1085 gs_sel = current->thread.gsindex;
b062b794 1086 fs_base = current->thread.fsbase;
e368b875 1087 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1088 } else {
e368b875
SC		 1089 savesegment(fs, fs_sel);
1090 savesegment(gs, gs_sel);
b062b794 1091 fs_base = read_msr(MSR_FS_BASE);
e368b875 1092 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1093 }
b2da15ac 1094
4679b61f 1095 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1096#else
e368b875
SC		 1097 savesegment(fs, fs_sel);
1098 savesegment(gs, gs_sel);
1099 fs_base = segment_base(fs_sel);
1100 gs_base = segment_base(gs_sel);
707c0874 1101#endif
e368b875 1102
8f21a0bb
SC		 1103 if (unlikely(fs_sel != host_state->fs_sel)) {
1104 if (!(fs_sel & 7))
1105 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1106 else
1107 vmcs_write16(HOST_FS_SELECTOR, 0);
1108 host_state->fs_sel = fs_sel;
1109 }
1110 if (unlikely(gs_sel != host_state->gs_sel)) {
1111 if (!(gs_sel & 7))
1112 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1113 else
1114 vmcs_write16(HOST_GS_SELECTOR, 0);
1115 host_state->gs_sel = gs_sel;
1116 }
5e079c7e
SC		 1117 if (unlikely(fs_base != host_state->fs_base)) {
1118 vmcs_writel(HOST_FS_BASE, fs_base);
1119 host_state->fs_base = fs_base;
1120 }
1121 if (unlikely(gs_base != host_state->gs_base)) {
1122 vmcs_writel(HOST_GS_BASE, gs_base);
1123 host_state->gs_base = gs_base;
1124 }
33ed6329
AK		 1125}
1126
6d6095bd 1127static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1128{
d7ee039e
SC		 1129 struct vmcs_host_state *host_state;
1130
bd9966de 1131 if (!vmx->loaded_cpu_state)
33ed6329
AK		 1132 return;
1133
bd9966de 1134 WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
d7ee039e 1135 host_state = &vmx->loaded_cpu_state->host_state;
bd9966de 1136
e1beb1d3 1137 ++vmx->vcpu.stat.host_state_reload;
bd9966de
SC		 1138 vmx->loaded_cpu_state = NULL;
1139
c8770e7b 1140#ifdef CONFIG_X86_64
4679b61f 1141 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1142#endif
d7ee039e
SC		 1143 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1144 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1145#ifdef CONFIG_X86_64
d7ee039e 1146 load_gs_index(host_state->gs_sel);
9581d442 1147#else
d7ee039e 1148 loadsegment(gs, host_state->gs_sel);
33ed6329 1149#endif
33ed6329 1150 }
d7ee039e
SC		 1151 if (host_state->fs_sel & 7)
1152 loadsegment(fs, host_state->fs_sel);
b2da15ac 1153#ifdef CONFIG_X86_64
d7ee039e
SC		 1154 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1155 loadsegment(ds, host_state->ds_sel);
1156 loadsegment(es, host_state->es_sel);
b2da15ac 1157 }
b2da15ac 1158#endif
b7ffc44d 1159 invalidate_tss_limit();
44ea2b17 1160#ifdef CONFIG_X86_64
c8770e7b 1161 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1162#endif
45fc8757 1163 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK		 1164}
1165
678e315e
SC		 1166#ifdef CONFIG_X86_64
1167static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1168{
4679b61f
PB		 1169 preempt_disable();
1170 if (vmx->loaded_cpu_state)
1171 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1172 preempt_enable();
678e315e 1173 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1174}
1175
678e315e
SC		 1176static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1177{
4679b61f
PB		 1178 preempt_disable();
1179 if (vmx->loaded_cpu_state)
1180 wrmsrl(MSR_KERNEL_GS_BASE, data);
1181 preempt_enable();
678e315e
SC		 1182 vmx->msr_guest_kernel_gs_base = data;
1183}
1184#endif
1185
28b835d6
FW		 1186static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1187{
1188 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1189 struct pi_desc old, new;
1190 unsigned int dest;
1191
31afb2ea
PB		 1192 /*
1193 * In case of hot-plug or hot-unplug, we may have to undo
1194 * vmx_vcpu_pi_put even if there is no assigned device. And we
1195 * always keep PI.NDST up to date for simplicity: it makes the
1196 * code easier, and CPU migration is not a fast path.
1197 */
1198 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1199 return;
1200
31afb2ea 1201 /* The full case. */
28b835d6
FW		 1202 do {
1203 old.control = new.control = pi_desc->control;
1204
31afb2ea 1205 dest = cpu_physical_id(cpu);
28b835d6 1206
31afb2ea
PB		 1207 if (x2apic_enabled())
1208 new.ndst = dest;
1209 else
1210 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1211
28b835d6 1212 new.sn = 0;
c0a1666b
PB		 1213 } while (cmpxchg64(&pi_desc->control, old.control,
1214 new.control) != old.control);
c112b5f5
LK		 1215
1216 /*
1217 * Clear SN before reading the bitmap. The VT-d firmware
1218 * writes the bitmap and reads SN atomically (5.2.3 in the
1219 * spec), so it doesn't really have a memory barrier that
1220 * pairs with this, but we cannot do that and we need one.
1221 */
1222 smp_mb__after_atomic();
1223
1224 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1225 pi_set_on(pi_desc);
28b835d6 1226}
1be0e61c 1227
6aa8b732
AK		 1228/*
1229 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1230 * vcpu mutex is already taken.
1231 */
97b7ead3 1232void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1233{
a2fa3e9f 1234 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1235 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1236
b80c76ec 1237 if (!already_loaded) {
fe0e80be 1238 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1239 local_irq_disable();
8f536b76 1240 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1241
1242 /*
1243 * Read loaded_vmcs->cpu should be before fetching
1244 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1245 * See the comments in __loaded_vmcs_clear().
1246 */
1247 smp_rmb();
1248
d462b819
NHE		 1249 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1250 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1251 crash_enable_local_vmclear(cpu);
92fe13be 1252 local_irq_enable();
b80c76ec
JM		 1253 }
1254
1255 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1256 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1257 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1258 indirect_branch_prediction_barrier();
b80c76ec
JM		 1259 }
1260
1261 if (!already_loaded) {
59c58ceb 1262 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1263 unsigned long sysenter_esp;
1264
1265 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1266
6aa8b732
AK		 1267 /*
1268 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1269 * processors. See 22.2.4.
6aa8b732 1270 */
e0c23063 1271 vmcs_writel(HOST_TR_BASE,
72f5e08d 1272 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1273 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 1274
b7ffc44d
AL		 1275 /*
1276 * VM exits change the host TR limit to 0x67 after a VM
1277 * exit. This is okay, since 0x67 covers everything except
1278 * the IO bitmap and have have code to handle the IO bitmap
1279 * being lost after a VM exit.
1280 */
1281 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1282
6aa8b732
AK		 1283 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1284 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1285
d462b819 1286 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1287 }
28b835d6 1288
2680d6da
OH		 1289 /* Setup TSC multiplier */
1290 if (kvm_has_tsc_control &&
c95ba92a
PF		 1291 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1292 decache_tsc_multiplier(vmx);
2680d6da 1293
28b835d6 1294 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 1295 vmx->host_pkru = read_pkru();
74c55931 1296 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1297}
1298
1299static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1300{
1301 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1302
1303 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1304 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1305 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1306 return;
1307
1308 /* Set SN when the vCPU is preempted */
1309 if (vcpu->preempted)
1310 pi_set_sn(pi_desc);
6aa8b732
AK		 1311}
1312
97b7ead3 1313void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1314{
28b835d6
FW		 1315 vmx_vcpu_pi_put(vcpu);
1316
6d6095bd 1317 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1318}
1319
f244deed
WL		 1320static bool emulation_required(struct kvm_vcpu *vcpu)
1321{
1322 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1323}
1324
edcafe3c
AK		 1325static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1326
97b7ead3 1327unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1328{
78ac8b47 1329 unsigned long rflags, save_rflags;
345dcaa8 1330
6de12732
AK		 1331 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1332 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1333 rflags = vmcs_readl(GUEST_RFLAGS);
1334 if (to_vmx(vcpu)->rmode.vm86_active) {
1335 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1336 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1337 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1338 }
1339 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1340 }
6de12732 1341 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1342}
1343
97b7ead3 1344void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1345{
f244deed
WL		 1346 unsigned long old_rflags = vmx_get_rflags(vcpu);
1347
6de12732
AK		 1348 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1349 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1350 if (to_vmx(vcpu)->rmode.vm86_active) {
1351 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1352 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1353 }
6aa8b732 1354 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed
WL		 1355
1356 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1357 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1358}
1359
97b7ead3 1360u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1361{
1362 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1363 int ret = 0;
1364
1365 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1366 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1367 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1368 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1369
37ccdcbe 1370 return ret;
2809f5d2
GC		 1371}
1372
97b7ead3 1373void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1374{
1375 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1376 u32 interruptibility = interruptibility_old;
1377
1378 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1379
48005f64 1380 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1381 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1382 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1383 interruptibility |= GUEST_INTR_STATE_STI;
1384
1385 if ((interruptibility != interruptibility_old))
1386 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1387}
1388
bf8c55d8
CP		 1389static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1390{
1391 struct vcpu_vmx *vmx = to_vmx(vcpu);
1392 unsigned long value;
1393
1394 /*
1395 * Any MSR write that attempts to change bits marked reserved will
1396 * case a #GP fault.
1397 */
1398 if (data & vmx->pt_desc.ctl_bitmask)
1399 return 1;
1400
1401 /*
1402 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1403 * result in a #GP unless the same write also clears TraceEn.
1404 */
1405 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1406 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1407 return 1;
1408
1409 /*
1410 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1411 * and FabricEn would cause #GP, if
1412 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1413 */
1414 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1415 !(data & RTIT_CTL_FABRIC_EN) &&
1416 !intel_pt_validate_cap(vmx->pt_desc.caps,
1417 PT_CAP_single_range_output))
1418 return 1;
1419
1420 /*
1421 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1422 * utilize encodings marked reserved will casue a #GP fault.
1423 */
1424 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1425 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1426 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1427 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1428 return 1;
1429 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1430 PT_CAP_cycle_thresholds);
1431 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1432 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1433 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1434 return 1;
1435 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1436 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1437 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1438 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1439 return 1;
1440
1441 /*
1442 * If ADDRx_CFG is reserved or the encodings is >2 will
1443 * cause a #GP fault.
1444 */
1445 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1446 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1447 return 1;
1448 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1449 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1450 return 1;
1451 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1452 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1453 return 1;
1454 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1455 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1456 return 1;
1457
1458 return 0;
1459}
1460
1461
6aa8b732
AK		 1462static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1463{
1464 unsigned long rip;
6aa8b732 1465
5fdbf976 1466 rip = kvm_rip_read(vcpu);
6aa8b732 1467 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1468 kvm_rip_write(vcpu, rip);
6aa8b732 1469
2809f5d2
GC		 1470 /* skipping an emulated instruction also counts */
1471 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1472}
1473
caa057a2
WL		 1474static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1475{
1476 /*
1477 * Ensure that we clear the HLT state in the VMCS. We don't need to
1478 * explicitly skip the instruction because if the HLT state is set,
1479 * then the instruction is already executing and RIP has already been
1480 * advanced.
1481 */
1482 if (kvm_hlt_in_guest(vcpu->kvm) &&
1483 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1484 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1485}
1486
cfcd20e5 1487static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1488{
77ab6db0 1489 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1490 unsigned nr = vcpu->arch.exception.nr;
1491 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1492 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1493 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1494
da998b46
JM		 1495 kvm_deliver_exception_payload(vcpu);
1496
8ab2d2e2 1497 if (has_error_code) {
77ab6db0 1498 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1499 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1500 }
77ab6db0 1501
7ffd92c5 1502 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1503 int inc_eip = 0;
1504 if (kvm_exception_is_soft(nr))
1505 inc_eip = vcpu->arch.event_exit_inst_len;
1506 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1507 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1508 return;
1509 }
1510
add5ff7a
SC		 1511 WARN_ON_ONCE(vmx->emulation_required);
1512
66fd3f7f
GN		 1513 if (kvm_exception_is_soft(nr)) {
1514 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1515 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1516 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1517 } else
1518 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1519
1520 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1521
1522 vmx_clear_hlt(vcpu);
298101da
AK		 1523}
1524
4e47c7a6
SY		 1525static bool vmx_rdtscp_supported(void)
1526{
1527 return cpu_has_vmx_rdtscp();
1528}
1529
ad756a16
MJ		 1530static bool vmx_invpcid_supported(void)
1531{
eb4b248e 1532 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1533}
1534
a75beee6
ED		 1535/*
1536 * Swap MSR entry in host/guest MSR entry array.
1537 */
8b9cf98c 1538static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1539{
26bb0981 1540 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1541
1542 tmp = vmx->guest_msrs[to];
1543 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1544 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1545}
1546
e38aea3e
AK		 1547/*
1548 * Set up the vmcs to automatically save and restore system
1549 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1550 * mode, as fiddling with msrs is very expensive.
1551 */
8b9cf98c 1552static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1553{
26bb0981 1554 int save_nmsrs, index;
e38aea3e 1555
a75beee6
ED		 1556 save_nmsrs = 0;
1557#ifdef CONFIG_X86_64
84c8c5b8
JM		 1558 /*
1559 * The SYSCALL MSRs are only needed on long mode guests, and only
1560 * when EFER.SCE is set.
1561 */
1562 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1563 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1564 if (index >= 0)
8b9cf98c
RR		 1565 move_msr_up(vmx, index, save_nmsrs++);
1566 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1567 if (index >= 0)
8b9cf98c 1568 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1569 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1570 if (index >= 0)
8b9cf98c 1571 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1572 }
1573#endif
92c0d900
AK		 1574 index = __find_msr_index(vmx, MSR_EFER);
1575 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1576 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1577 index = __find_msr_index(vmx, MSR_TSC_AUX);
1578 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1579 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1580
26bb0981 1581 vmx->save_nmsrs = save_nmsrs;
f48b4711 1582 vmx->guest_msrs_dirty = true;
5897297b 1583
8d14695f 1584 if (cpu_has_vmx_msr_bitmap())
904e14fb 1585 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1586}
1587
e79f245d 1588static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1589{
e79f245d 1590 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1591
e79f245d
KA		 1592 if (is_guest_mode(vcpu) &&
1593 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1594 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1595
1596 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1597}
1598
326e7425 1599static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1600{
45c3af97
PB		 1601 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1602 u64 g_tsc_offset = 0;
1603
1604 /*
1605 * We're here if L1 chose not to trap WRMSR to TSC. According
1606 * to the spec, this should set L1's TSC; The offset that L1
1607 * set for L2 remains unchanged, and still needs to be added
1608 * to the newly set TSC to get L2's TSC.
1609 */
1610 if (is_guest_mode(vcpu) &&
1611 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1612 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1613
45c3af97
PB		 1614 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1615 vcpu->arch.tsc_offset - g_tsc_offset,
1616 offset);
1617 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1618 return offset + g_tsc_offset;
6aa8b732
AK		 1619}
1620
801d3424
NHE		 1621/*
1622 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1623 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1624 * all guests if the "nested" module option is off, and can also be disabled
1625 * for a single guest by disabling its VMX cpuid bit.
1626 */
7c97fcb3 1627bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1628{
d6321d49 1629 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1630}
1631
55d2375e
SC		 1632static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1633 uint64_t val)
62cc6b9d 1634{
55d2375e 1635 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1636
55d2375e 1637 return !(val & ~valid_bits);
62cc6b9d
DM		 1638}
1639
55d2375e 1640static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1641{
55d2375e
SC		 1642 switch (msr->index) {
1643 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1644 if (!nested)
1645 return 1;
1646 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1647 default:
1648 return 1;
1649 }
62cc6b9d 1650
62cc6b9d
DM		 1651 return 0;
1652}
1653
55d2375e
SC		 1654/*
1655 * Reads an msr value (of 'msr_index') into 'pdata'.
1656 * Returns 0 on success, non-0 otherwise.
1657 * Assumes vcpu_load() was already called.
1658 */
1659static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1660{
55d2375e
SC		 1661 struct vcpu_vmx *vmx = to_vmx(vcpu);
1662 struct shared_msr_entry *msr;
bf8c55d8 1663 u32 index;
62cc6b9d 1664
55d2375e
SC		 1665 switch (msr_info->index) {
1666#ifdef CONFIG_X86_64
1667 case MSR_FS_BASE:
1668 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1669 break;
55d2375e
SC		 1670 case MSR_GS_BASE:
1671 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1672 break;
55d2375e
SC		 1673 case MSR_KERNEL_GS_BASE:
1674 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1675 break;
55d2375e
SC		 1676#endif
1677 case MSR_EFER:
1678 return kvm_get_msr_common(vcpu, msr_info);
1679 case MSR_IA32_SPEC_CTRL:
1680 if (!msr_info->host_initiated &&
1681 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1682 return 1;
1683
1684 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1685 break;
6aa8b732 1686 case MSR_IA32_SYSENTER_CS:
609e36d3 1687 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1688 break;
1689 case MSR_IA32_SYSENTER_EIP:
609e36d3 1690 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1691 break;
1692 case MSR_IA32_SYSENTER_ESP:
609e36d3 1693 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1694 break;
6c6a2ab9
LA		 1695 case MSR_IA32_POWER_CTL:
1696 msr_info->data = vmx->msr_ia32_power_ctl;
1697 break;
0dd376e7 1698 case MSR_IA32_BNDCFGS:
691bd434 1699 if (!kvm_mpx_supported() ||
d6321d49
RK		 1700 (!msr_info->host_initiated &&
1701 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1702 return 1;
609e36d3 1703 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1704 break;
c45dcc71
AR		 1705 case MSR_IA32_MCG_EXT_CTL:
1706 if (!msr_info->host_initiated &&
a6cb099a 1707 !(vmx->msr_ia32_feature_control &
c45dcc71 1708 FEATURE_CONTROL_LMCE))
cae50139 1709 return 1;
c45dcc71
AR		 1710 msr_info->data = vcpu->arch.mcg_ext_ctl;
1711 break;
cae50139 1712 case MSR_IA32_FEATURE_CONTROL:
a6cb099a 1713 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1714 break;
1715 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1716 if (!nested_vmx_allowed(vcpu))
1717 return 1;
6677f3da
PB		 1718 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1719 &msr_info->data);
20300099
WL		 1720 case MSR_IA32_XSS:
1721 if (!vmx_xsaves_supported())
1722 return 1;
609e36d3 1723 msr_info->data = vcpu->arch.ia32_xss;
20300099 1724 break;
bf8c55d8
CP		 1725 case MSR_IA32_RTIT_CTL:
1726 if (pt_mode != PT_MODE_HOST_GUEST)
1727 return 1;
1728 msr_info->data = vmx->pt_desc.guest.ctl;
1729 break;
1730 case MSR_IA32_RTIT_STATUS:
1731 if (pt_mode != PT_MODE_HOST_GUEST)
1732 return 1;
1733 msr_info->data = vmx->pt_desc.guest.status;
1734 break;
1735 case MSR_IA32_RTIT_CR3_MATCH:
1736 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1737 !intel_pt_validate_cap(vmx->pt_desc.caps,
1738 PT_CAP_cr3_filtering))
1739 return 1;
1740 msr_info->data = vmx->pt_desc.guest.cr3_match;
1741 break;
1742 case MSR_IA32_RTIT_OUTPUT_BASE:
1743 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1744 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1745 PT_CAP_topa_output) &&
1746 !intel_pt_validate_cap(vmx->pt_desc.caps,
1747 PT_CAP_single_range_output)))
1748 return 1;
1749 msr_info->data = vmx->pt_desc.guest.output_base;
1750 break;
1751 case MSR_IA32_RTIT_OUTPUT_MASK:
1752 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1753 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1754 PT_CAP_topa_output) &&
1755 !intel_pt_validate_cap(vmx->pt_desc.caps,
1756 PT_CAP_single_range_output)))
1757 return 1;
1758 msr_info->data = vmx->pt_desc.guest.output_mask;
1759 break;
1760 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1761 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1762 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1763 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1764 PT_CAP_num_address_ranges)))
1765 return 1;
1766 if (index % 2)
1767 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1768 else
1769 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1770 break;
4e47c7a6 1771 case MSR_TSC_AUX:
d6321d49
RK		 1772 if (!msr_info->host_initiated &&
1773 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1774 return 1;
b2869f28 1775 /* Else, falls through */
6aa8b732 1776 default:
a6cb099a 1777 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1778 if (msr) {
609e36d3 1779 msr_info->data = msr->data;
3bab1f5d 1780 break;
6aa8b732 1781 }
609e36d3 1782 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1783 }
1784
6aa8b732
AK		 1785 return 0;
1786}
1787
1788/*
1789 * Writes msr value into into the appropriate "register".
1790 * Returns 0 on success, non-0 otherwise.
1791 * Assumes vcpu_load() was already called.
1792 */
8fe8ab46 1793static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1794{
a2fa3e9f 1795 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1796 struct shared_msr_entry *msr;
2cc51560 1797 int ret = 0;
8fe8ab46
WA		 1798 u32 msr_index = msr_info->index;
1799 u64 data = msr_info->data;
bf8c55d8 1800 u32 index;
2cc51560 1801
6aa8b732 1802 switch (msr_index) {
3bab1f5d 1803 case MSR_EFER:
8fe8ab46 1804 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1805 break;
16175a79 1806#ifdef CONFIG_X86_64
6aa8b732 1807 case MSR_FS_BASE:
2fb92db1 1808 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1809 vmcs_writel(GUEST_FS_BASE, data);
1810 break;
1811 case MSR_GS_BASE:
2fb92db1 1812 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1813 vmcs_writel(GUEST_GS_BASE, data);
1814 break;
44ea2b17 1815 case MSR_KERNEL_GS_BASE:
678e315e 1816 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1817 break;
6aa8b732
AK		 1818#endif
1819 case MSR_IA32_SYSENTER_CS:
1820 vmcs_write32(GUEST_SYSENTER_CS, data);
1821 break;
1822 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1823 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1824 break;
1825 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1826 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1827 break;
6c6a2ab9
LA		 1828 case MSR_IA32_POWER_CTL:
1829 vmx->msr_ia32_power_ctl = data;
1830 break;
0dd376e7 1831 case MSR_IA32_BNDCFGS:
691bd434 1832 if (!kvm_mpx_supported() ||
d6321d49
RK		 1833 (!msr_info->host_initiated &&
1834 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1835 return 1;
fd8cb433 1836 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 1837 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 1838 return 1;
0dd376e7
LJ		 1839 vmcs_write64(GUEST_BNDCFGS, data);
1840 break;
d28b387f
KA		 1841 case MSR_IA32_SPEC_CTRL:
1842 if (!msr_info->host_initiated &&
d28b387f
KA		 1843 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1844 return 1;
1845
1846 /* The STIBP bit doesn't fault even if it's not advertised */
9f65fb29 1847 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
d28b387f
KA		 1848 return 1;
1849
1850 vmx->spec_ctrl = data;
1851
1852 if (!data)
1853 break;
1854
1855 /*
1856 * For non-nested:
1857 * When it's written (to non-zero) for the first time, pass
1858 * it through.
1859 *
1860 * For nested:
1861 * The handling of the MSR bitmap for L2 guests is done in
1862 * nested_vmx_merge_msr_bitmap. We should not touch the
1863 * vmcs02.msr_bitmap here since it gets completely overwritten
1864 * in the merging. We update the vmcs01 here for L1 as well
1865 * since it will end up touching the MSR anyway now.
1866 */
1867 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1868 MSR_IA32_SPEC_CTRL,
1869 MSR_TYPE_RW);
1870 break;
15d45071
AR		 1871 case MSR_IA32_PRED_CMD:
1872 if (!msr_info->host_initiated &&
15d45071
AR		 1873 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1874 return 1;
1875
1876 if (data & ~PRED_CMD_IBPB)
1877 return 1;
1878
1879 if (!data)
1880 break;
1881
1882 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1883
1884 /*
1885 * For non-nested:
1886 * When it's written (to non-zero) for the first time, pass
1887 * it through.
1888 *
1889 * For nested:
1890 * The handling of the MSR bitmap for L2 guests is done in
1891 * nested_vmx_merge_msr_bitmap. We should not touch the
1892 * vmcs02.msr_bitmap here since it gets completely overwritten
1893 * in the merging.
1894 */
1895 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1896 MSR_TYPE_W);
1897 break;
468d472f
SY		 1898 case MSR_IA32_CR_PAT:
1899 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
674ea351 1900 if (!kvm_pat_valid(data))
4566654b 1901 return 1;
468d472f
SY		 1902 vmcs_write64(GUEST_IA32_PAT, data);
1903 vcpu->arch.pat = data;
1904 break;
1905 }
8fe8ab46 1906 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1907 break;
ba904635
WA		 1908 case MSR_IA32_TSC_ADJUST:
1909 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1910 break;
c45dcc71
AR		 1911 case MSR_IA32_MCG_EXT_CTL:
1912 if ((!msr_info->host_initiated &&
1913 !(to_vmx(vcpu)->msr_ia32_feature_control &
1914 FEATURE_CONTROL_LMCE)) ||
1915 (data & ~MCG_EXT_CTL_LMCE_EN))
1916 return 1;
1917 vcpu->arch.mcg_ext_ctl = data;
1918 break;
cae50139 1919 case MSR_IA32_FEATURE_CONTROL:
37e4c997 1920 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 1921 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK		 1922 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1923 return 1;
3b84080b 1924 vmx->msr_ia32_feature_control = data;
cae50139
JK		 1925 if (msr_info->host_initiated && data == 0)
1926 vmx_leave_nested(vcpu);
1927 break;
1928 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 1929 if (!msr_info->host_initiated)
1930 return 1; /* they are read-only */
1931 if (!nested_vmx_allowed(vcpu))
1932 return 1;
1933 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL		 1934 case MSR_IA32_XSS:
1935 if (!vmx_xsaves_supported())
1936 return 1;
1937 /*
1938 * The only supported bit as of Skylake is bit 8, but
1939 * it is not supported on KVM.
1940 */
1941 if (data != 0)
1942 return 1;
1943 vcpu->arch.ia32_xss = data;
1944 if (vcpu->arch.ia32_xss != host_xss)
1945 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
989e3992 1946 vcpu->arch.ia32_xss, host_xss, false);
20300099
WL		 1947 else
1948 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
1949 break;
bf8c55d8
CP		 1950 case MSR_IA32_RTIT_CTL:
1951 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 1952 vmx_rtit_ctl_check(vcpu, data) ||
1953 vmx->nested.vmxon)
bf8c55d8
CP		 1954 return 1;
1955 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
1956 vmx->pt_desc.guest.ctl = data;
b08c2896 1957 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 1958 break;
1959 case MSR_IA32_RTIT_STATUS:
1960 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1961 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1962 (data & MSR_IA32_RTIT_STATUS_MASK))
1963 return 1;
1964 vmx->pt_desc.guest.status = data;
1965 break;
1966 case MSR_IA32_RTIT_CR3_MATCH:
1967 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1968 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1969 !intel_pt_validate_cap(vmx->pt_desc.caps,
1970 PT_CAP_cr3_filtering))
1971 return 1;
1972 vmx->pt_desc.guest.cr3_match = data;
1973 break;
1974 case MSR_IA32_RTIT_OUTPUT_BASE:
1975 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1976 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1977 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1978 PT_CAP_topa_output) &&
1979 !intel_pt_validate_cap(vmx->pt_desc.caps,
1980 PT_CAP_single_range_output)) ||
1981 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
1982 return 1;
1983 vmx->pt_desc.guest.output_base = data;
1984 break;
1985 case MSR_IA32_RTIT_OUTPUT_MASK:
1986 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1987 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1988 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1989 PT_CAP_topa_output) &&
1990 !intel_pt_validate_cap(vmx->pt_desc.caps,
1991 PT_CAP_single_range_output)))
1992 return 1;
1993 vmx->pt_desc.guest.output_mask = data;
1994 break;
1995 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1996 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1997 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1998 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1999 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2000 PT_CAP_num_address_ranges)))
2001 return 1;
2002 if (index % 2)
2003 vmx->pt_desc.guest.addr_b[index / 2] = data;
2004 else
2005 vmx->pt_desc.guest.addr_a[index / 2] = data;
2006 break;
4e47c7a6 2007 case MSR_TSC_AUX:
d6321d49
RK		 2008 if (!msr_info->host_initiated &&
2009 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2010 return 1;
2011 /* Check reserved bit, higher 32 bits should be zero */
2012 if ((data >> 32) != 0)
2013 return 1;
b2869f28 2014 /* Else, falls through */
6aa8b732 2015 default:
8b9cf98c 2016 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2017 if (msr) {
8b3c3104 2018 u64 old_msr_data = msr->data;
3bab1f5d 2019 msr->data = data;
2225fd56
AK		 2020 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2021 preempt_disable();
8b3c3104
AH		 2022 ret = kvm_set_shared_msr(msr->index, msr->data,
2023 msr->mask);
2225fd56 2024 preempt_enable();
8b3c3104
AH		 2025 if (ret)
2026 msr->data = old_msr_data;
2225fd56 2027 }
3bab1f5d 2028 break;
6aa8b732 2029 }
8fe8ab46 2030 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2031 }
2032
2cc51560 2033 return ret;
6aa8b732
AK		 2034}
2035
5fdbf976 2036static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2037{
5fdbf976
MT		 2038 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2039 switch (reg) {
2040 case VCPU_REGS_RSP:
2041 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2042 break;
2043 case VCPU_REGS_RIP:
2044 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2045 break;
6de4f3ad
AK		 2046 case VCPU_EXREG_PDPTR:
2047 if (enable_ept)
2048 ept_save_pdptrs(vcpu);
2049 break;
5fdbf976
MT		 2050 default:
2051 break;
2052 }
6aa8b732
AK		 2053}
2054
6aa8b732
AK		 2055static __init int cpu_has_kvm_support(void)
2056{
6210e37b 2057 return cpu_has_vmx();
6aa8b732
AK		 2058}
2059
2060static __init int vmx_disabled_by_bios(void)
2061{
2062 u64 msr;
2063
2064 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2065 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2066 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2067 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2068 && tboot_enabled())
2069 return 1;
23f3e991 2070 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2071 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2072 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2073 && !tboot_enabled()) {
2074 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2075 "activate TXT before enabling KVM\n");
cafd6659 2076 return 1;
f9335afe 2077 }
23f3e991
JC		 2078 /* launched w/o TXT and VMX disabled */
2079 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2080 && !tboot_enabled())
2081 return 1;
cafd6659
SW		 2082 }
2083
2084 return 0;
6aa8b732
AK		 2085}
2086
7725b894
DX		 2087static void kvm_cpu_vmxon(u64 addr)
2088{
fe0e80be 2089 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2090 intel_pt_handle_vmx(1);
2091
4b1e5478 2092 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2093}
2094
13a34e06 2095static int hardware_enable(void)
6aa8b732
AK		 2096{
2097 int cpu = raw_smp_processor_id();
2098 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2099 u64 old, test_bits;
6aa8b732 2100
1e02ce4c 2101 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2102 return -EBUSY;
2103
773e8a04
VK		 2104 /*
2105 * This can happen if we hot-added a CPU but failed to allocate
2106 * VP assist page for it.
2107 */
2108 if (static_branch_unlikely(&enable_evmcs) &&
2109 !hv_get_vp_assist_page(cpu))
2110 return -EFAULT;
2111
d462b819 2112 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2113 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2114 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2115
2116 /*
2117 * Now we can enable the vmclear operation in kdump
2118 * since the loaded_vmcss_on_cpu list on this cpu
2119 * has been initialized.
2120 *
2121 * Though the cpu is not in VMX operation now, there
2122 * is no problem to enable the vmclear operation
2123 * for the loaded_vmcss_on_cpu list is empty!
2124 */
2125 crash_enable_local_vmclear(cpu);
2126
6aa8b732 2127 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2128
2129 test_bits = FEATURE_CONTROL_LOCKED;
2130 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2131 if (tboot_enabled())
2132 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2133
2134 if ((old & test_bits) != test_bits) {
6aa8b732 2135 /* enable and lock */
cafd6659
SW		 2136 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2137 }
fe0e80be 2138 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2139 if (enable_ept)
2140 ept_sync_global();
10474ae8
AG		 2141
2142 return 0;
6aa8b732
AK		 2143}
2144
d462b819 2145static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2146{
2147 int cpu = raw_smp_processor_id();
d462b819 2148 struct loaded_vmcs *v, *n;
543e4243 2149
d462b819
NHE		 2150 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2151 loaded_vmcss_on_cpu_link)
2152 __loaded_vmcs_clear(v);
543e4243
AK		 2153}
2154
710ff4a8
EH		 2155
2156/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2157 * tricks.
2158 */
2159static void kvm_cpu_vmxoff(void)
6aa8b732 2160{
4b1e5478 2161 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2162
2163 intel_pt_handle_vmx(0);
fe0e80be 2164 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2165}
2166
13a34e06 2167static void hardware_disable(void)
710ff4a8 2168{
fe0e80be
DH		 2169 vmclear_local_loaded_vmcss();
2170 kvm_cpu_vmxoff();
710ff4a8
EH		 2171}
2172
1c3d14fe 2173static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2174 u32 msr, u32 *result)
1c3d14fe
YS		 2175{
2176 u32 vmx_msr_low, vmx_msr_high;
2177 u32 ctl = ctl_min | ctl_opt;
2178
2179 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2180
2181 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2182 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2183
2184 /* Ensure minimum (required) set of control bits are supported. */
2185 if (ctl_min & ~ctl)
002c7f7c 2186 return -EIO;
1c3d14fe
YS		 2187
2188 *result = ctl;
2189 return 0;
2190}
2191
7caaa711
SC		 2192static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2193 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2194{
2195 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2196 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2197 u32 _pin_based_exec_control = 0;
2198 u32 _cpu_based_exec_control = 0;
f78e0e2e 2199 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2200 u32 _vmexit_control = 0;
2201 u32 _vmentry_control = 0;
2202
1389309c 2203 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2204 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2205#ifdef CONFIG_X86_64
2206 CPU_BASED_CR8_LOAD_EXITING |
2207 CPU_BASED_CR8_STORE_EXITING |
2208#endif
d56f546d
SY		 2209 CPU_BASED_CR3_LOAD_EXITING |
2210 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2211 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2212 CPU_BASED_MOV_DR_EXITING |
a7052897 2213 CPU_BASED_USE_TSC_OFFSETING |
4d5422ce
WL		 2214 CPU_BASED_MWAIT_EXITING |
2215 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2216 CPU_BASED_INVLPG_EXITING |
2217 CPU_BASED_RDPMC_EXITING;
443381a8 2218
f78e0e2e 2219 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2220 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2221 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2222 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2223 &_cpu_based_exec_control) < 0)
002c7f7c 2224 return -EIO;
6e5d865c
YS		 2225#ifdef CONFIG_X86_64
2226 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2227 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2228 ~CPU_BASED_CR8_STORE_EXITING;
2229#endif
f78e0e2e 2230 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2231 min2 = 0;
2232 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2233 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2234 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2235 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2236 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2237 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2238 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2239 SECONDARY_EXEC_DESC |
ad756a16 2240 SECONDARY_EXEC_RDTSCP |
83d4c286 2241 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2242 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2243 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2244 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2245 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2246 SECONDARY_EXEC_RDSEED_EXITING |
2247 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2248 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2249 SECONDARY_EXEC_TSC_SCALING |
f99e3daf
CP		 2250 SECONDARY_EXEC_PT_USE_GPA |
2251 SECONDARY_EXEC_PT_CONCEAL_VMX |
0b665d30
SC		 2252 SECONDARY_EXEC_ENABLE_VMFUNC |
2253 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2254 if (adjust_vmx_controls(min2, opt2,
2255 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2256 &_cpu_based_2nd_exec_control) < 0)
2257 return -EIO;
2258 }
2259#ifndef CONFIG_X86_64
2260 if (!(_cpu_based_2nd_exec_control &
2261 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2262 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2263#endif
83d4c286
YZ		 2264
2265 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2266 _cpu_based_2nd_exec_control &= ~(
8d14695f 2267 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2268 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2269 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2270
61f1dd90 2271 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2272 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2273
d56f546d 2274 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2275 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2276 enabled */
5fff7d27
GN		 2277 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2278 CPU_BASED_CR3_STORE_EXITING |
2279 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2280 } else if (vmx_cap->ept) {
2281 vmx_cap->ept = 0;
61f1dd90
WL		 2282 pr_warn_once("EPT CAP should not exist if not support "
2283 "1-setting enable EPT VM-execution control\n");
2284 }
2285 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2286 vmx_cap->vpid) {
2287 vmx_cap->vpid = 0;
61f1dd90
WL		 2288 pr_warn_once("VPID CAP should not exist if not support "
2289 "1-setting enable VPID VM-execution control\n");
d56f546d 2290 }
1c3d14fe 2291
91fa0f8e 2292 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2293#ifdef CONFIG_X86_64
2294 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2295#endif
c73da3fc 2296 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2297 VM_EXIT_LOAD_IA32_PAT |
2298 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2299 VM_EXIT_CLEAR_BNDCFGS |
2300 VM_EXIT_PT_CONCEAL_PIP |
2301 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2302 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2303 &_vmexit_control) < 0)
002c7f7c 2304 return -EIO;
1c3d14fe 2305
8a1b4392
PB		 2306 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2307 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2308 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2309 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2310 &_pin_based_exec_control) < 0)
2311 return -EIO;
2312
1c17c3e6
PB		 2313 if (cpu_has_broken_vmx_preemption_timer())
2314 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2315 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2316 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2317 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2318
c845f9c6 2319 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2320 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2321 VM_ENTRY_LOAD_IA32_PAT |
2322 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2323 VM_ENTRY_LOAD_BNDCFGS |
2324 VM_ENTRY_PT_CONCEAL_PIP |
2325 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2326 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2327 &_vmentry_control) < 0)
002c7f7c 2328 return -EIO;
6aa8b732 2329
c73da3fc
SC		 2330 /*
2331 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2332 * can't be used due to an errata where VM Exit may incorrectly clear
2333 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2334 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2335 */
2336 if (boot_cpu_data.x86 == 0x6) {
2337 switch (boot_cpu_data.x86_model) {
2338 case 26: /* AAK155 */
2339 case 30: /* AAP115 */
2340 case 37: /* AAT100 */
2341 case 44: /* BC86,AAY89,BD102 */
2342 case 46: /* BA97 */
85ba2b16 2343 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2344 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2345 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2346 "does not work properly. Using workaround\n");
2347 break;
2348 default:
2349 break;
2350 }
2351 }
2352
2353
c68876fd 2354 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2355
2356 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2357 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2358 return -EIO;
1c3d14fe
YS		 2359
2360#ifdef CONFIG_X86_64
2361 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2362 if (vmx_msr_high & (1u<<16))
002c7f7c 2363 return -EIO;
1c3d14fe
YS		 2364#endif
2365
2366 /* Require Write-Back (WB) memory type for VMCS accesses. */
2367 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2368 return -EIO;
1c3d14fe 2369
002c7f7c 2370 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2371 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2372 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2373
2307af1c 2374 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2375
002c7f7c
YS		 2376 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2377 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2378 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2379 vmcs_conf->vmexit_ctrl = _vmexit_control;
2380 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2381
773e8a04
VK		 2382 if (static_branch_unlikely(&enable_evmcs))
2383 evmcs_sanitize_exec_ctrls(vmcs_conf);
2384
1c3d14fe 2385 return 0;
c68876fd 2386}
6aa8b732 2387
41836839 2388struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2389{
2390 int node = cpu_to_node(cpu);
2391 struct page *pages;
2392 struct vmcs *vmcs;
2393
41836839 2394 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2395 if (!pages)
2396 return NULL;
2397 vmcs = page_address(pages);
1c3d14fe 2398 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2399
2400 /* KVM supports Enlightened VMCS v1 only */
2401 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2402 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2403 else
392b2f25 2404 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2405
491a6038
LA		 2406 if (shadow)
2407 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2408 return vmcs;
2409}
2410
89b0c9f5 2411void free_vmcs(struct vmcs *vmcs)
6aa8b732 2412{
1c3d14fe 2413 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2414}
2415
d462b819
NHE		 2416/*
2417 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2418 */
89b0c9f5 2419void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2420{
2421 if (!loaded_vmcs->vmcs)
2422 return;
2423 loaded_vmcs_clear(loaded_vmcs);
2424 free_vmcs(loaded_vmcs->vmcs);
2425 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2426 if (loaded_vmcs->msr_bitmap)
2427 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2428 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2429}
2430
89b0c9f5 2431int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2432{
491a6038 2433 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2434 if (!loaded_vmcs->vmcs)
2435 return -ENOMEM;
2436
2437 loaded_vmcs->shadow_vmcs = NULL;
2438 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2439
2440 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2441 loaded_vmcs->msr_bitmap = (unsigned long *)
2442 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2443 if (!loaded_vmcs->msr_bitmap)
2444 goto out_vmcs;
2445 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2446
1f008e11
AB		 2447 if (IS_ENABLED(CONFIG_HYPERV) &&
2448 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2449 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2450 struct hv_enlightened_vmcs *evmcs =
2451 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2452
2453 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2454 }
904e14fb 2455 }
d7ee039e
SC		 2456
2457 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2458
f21f165e 2459 return 0;
904e14fb
PB		 2460
2461out_vmcs:
2462 free_loaded_vmcs(loaded_vmcs);
2463 return -ENOMEM;
f21f165e
PB		 2464}
2465
39959588 2466static void free_kvm_area(void)
6aa8b732
AK		 2467{
2468 int cpu;
2469
3230bb47 2470 for_each_possible_cpu(cpu) {
6aa8b732 2471 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2472 per_cpu(vmxarea, cpu) = NULL;
2473 }
6aa8b732
AK		 2474}
2475
6aa8b732
AK		 2476static __init int alloc_kvm_area(void)
2477{
2478 int cpu;
2479
3230bb47 2480 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2481 struct vmcs *vmcs;
2482
41836839 2483 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2484 if (!vmcs) {
2485 free_kvm_area();
2486 return -ENOMEM;
2487 }
2488
2307af1c
LA		 2489 /*
2490 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2491 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2492 * revision_id reported by MSR_IA32_VMX_BASIC.
2493 *
312a4661 2494 * However, even though not explicitly documented by
2307af1c
LA		 2495 * TLFS, VMXArea passed as VMXON argument should
2496 * still be marked with revision_id reported by
2497 * physical CPU.
2498 */
2499 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2500 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2501
6aa8b732
AK		 2502 per_cpu(vmxarea, cpu) = vmcs;
2503 }
2504 return 0;
2505}
2506
91b0aa2c 2507static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2508 struct kvm_segment *save)
6aa8b732 2509{
d99e4152
GN		 2510 if (!emulate_invalid_guest_state) {
2511 /*
2512 * CS and SS RPL should be equal during guest entry according
2513 * to VMX spec, but in reality it is not always so. Since vcpu
2514 * is in the middle of the transition from real mode to
2515 * protected mode it is safe to assume that RPL 0 is a good
2516 * default value.
2517 */
2518 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2519 save->selector &= ~SEGMENT_RPL_MASK;
2520 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2521 save->s = 1;
6aa8b732 2522 }
d99e4152 2523 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2524}
2525
2526static void enter_pmode(struct kvm_vcpu *vcpu)
2527{
2528 unsigned long flags;
a89a8fb9 2529 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2530
d99e4152
GN		 2531 /*
2532 * Update real mode segment cache. It may be not up-to-date if sement
2533 * register was written while vcpu was in a guest mode.
2534 */
2535 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2536 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2537 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2538 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2539 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2540 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2541
7ffd92c5 2542 vmx->rmode.vm86_active = 0;
6aa8b732 2543
2fb92db1
AK		 2544 vmx_segment_cache_clear(vmx);
2545
f5f7b2fe 2546 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2547
2548 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2549 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2550 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2551 vmcs_writel(GUEST_RFLAGS, flags);
2552
66aee91a
RR		 2553 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2554 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2555
2556 update_exception_bitmap(vcpu);
2557
91b0aa2c
GN		 2558 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2559 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2560 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2561 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2562 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2563 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2564}
2565
f5f7b2fe 2566static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2567{
772e0318 2568 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2569 struct kvm_segment var = *save;
2570
2571 var.dpl = 0x3;
2572 if (seg == VCPU_SREG_CS)
2573 var.type = 0x3;
2574
2575 if (!emulate_invalid_guest_state) {
2576 var.selector = var.base >> 4;
2577 var.base = var.base & 0xffff0;
2578 var.limit = 0xffff;
2579 var.g = 0;
2580 var.db = 0;
2581 var.present = 1;
2582 var.s = 1;
2583 var.l = 0;
2584 var.unusable = 0;
2585 var.type = 0x3;
2586 var.avl = 0;
2587 if (save->base & 0xf)
2588 printk_once(KERN_WARNING "kvm: segment base is not "
2589 "paragraph aligned when entering "
2590 "protected mode (seg=%d)", seg);
2591 }
6aa8b732 2592
d99e4152 2593 vmcs_write16(sf->selector, var.selector);
96794e4e 2594 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2595 vmcs_write32(sf->limit, var.limit);
2596 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2597}
2598
2599static void enter_rmode(struct kvm_vcpu *vcpu)
2600{
2601 unsigned long flags;
a89a8fb9 2602 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2603 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2604
f5f7b2fe
AK		 2605 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2606 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2607 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2608 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2609 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2610 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2611 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2612
7ffd92c5 2613 vmx->rmode.vm86_active = 1;
6aa8b732 2614
776e58ea
GN		 2615 /*
2616 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2617 * vcpu. Warn the user that an update is overdue.
776e58ea 2618 */
40bbb9d0 2619 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2620 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2621 "called before entering vcpu\n");
776e58ea 2622
2fb92db1
AK		 2623 vmx_segment_cache_clear(vmx);
2624
40bbb9d0 2625 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2626 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2627 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2628
2629 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2630 vmx->rmode.save_rflags = flags;
6aa8b732 2631
053de044 2632 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2633
2634 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2635 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2636 update_exception_bitmap(vcpu);
2637
d99e4152
GN		 2638 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2639 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2640 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2641 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2642 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2643 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2644
8668a3c4 2645 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2646}
2647
97b7ead3 2648void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2649{
2650 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2651 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2652
2653 if (!msr)
2654 return;
401d10de 2655
f6801dff 2656 vcpu->arch.efer = efer;
401d10de 2657 if (efer & EFER_LMA) {
2961e876 2658 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2659 msr->data = efer;
2660 } else {
2961e876 2661 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2662
2663 msr->data = efer & ~EFER_LME;
2664 }
2665 setup_msrs(vmx);
2666}
2667
05b3e0c2 2668#ifdef CONFIG_X86_64
6aa8b732
AK		 2669
2670static void enter_lmode(struct kvm_vcpu *vcpu)
2671{
2672 u32 guest_tr_ar;
2673
2fb92db1
AK		 2674 vmx_segment_cache_clear(to_vmx(vcpu));
2675
6aa8b732 2676 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2677 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2678 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2679 __func__);
6aa8b732 2680 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2681 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2682 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2683 }
da38f438 2684 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2685}
2686
2687static void exit_lmode(struct kvm_vcpu *vcpu)
2688{
2961e876 2689 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2690 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2691}
2692
2693#endif
2694
faff8758
JS		 2695static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2696{
2697 int vpid = to_vmx(vcpu)->vpid;
2698
2699 if (!vpid_sync_vcpu_addr(vpid, addr))
2700 vpid_sync_context(vpid);
2701
2702 /*
2703 * If VPIDs are not supported or enabled, then the above is a no-op.
2704 * But we don't really need a TLB flush in that case anyway, because
2705 * each VM entry/exit includes an implicit flush when VPID is 0.
2706 */
2707}
2708
e8467fda
AK		 2709static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2710{
2711 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2712
2713 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2714 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2715}
2716
aff48baa
AK		 2717static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2718{
b4d18517 2719 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
aff48baa
AK		 2720 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2721 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2722}
2723
25c4c276 2724static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2725{
fc78f519
AK		 2726 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2727
2728 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2729 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2730}
2731
1439442c
SY		 2732static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2733{
d0d538b9
GN		 2734 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2735
6de4f3ad
AK		 2736 if (!test_bit(VCPU_EXREG_PDPTR,
2737 (unsigned long *)&vcpu->arch.regs_dirty))
2738 return;
2739
1439442c 2740 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 2741 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2742 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2743 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2744 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2745 }
2746}
2747
97b7ead3 2748void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2749{
d0d538b9
GN		 2750 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2751
8f5d549f 2752 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 2753 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2754 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2755 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2756 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2757 }
6de4f3ad
AK		 2758
2759 __set_bit(VCPU_EXREG_PDPTR,
2760 (unsigned long *)&vcpu->arch.regs_avail);
2761 __set_bit(VCPU_EXREG_PDPTR,
2762 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2763}
2764
1439442c
SY		 2765static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2766 unsigned long cr0,
2767 struct kvm_vcpu *vcpu)
2768{
5233dd51
MT		 2769 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2770 vmx_decache_cr3(vcpu);
1439442c
SY		 2771 if (!(cr0 & X86_CR0_PG)) {
2772 /* From paging/starting to nonpaging */
2773 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2774 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2775 (CPU_BASED_CR3_LOAD_EXITING |
2776 CPU_BASED_CR3_STORE_EXITING));
2777 vcpu->arch.cr0 = cr0;
fc78f519 2778 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2779 } else if (!is_paging(vcpu)) {
2780 /* From nonpaging to paging */
2781 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2782 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2783 ~(CPU_BASED_CR3_LOAD_EXITING |
2784 CPU_BASED_CR3_STORE_EXITING));
2785 vcpu->arch.cr0 = cr0;
fc78f519 2786 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2787 }
95eb84a7
SY		 2788
2789 if (!(cr0 & X86_CR0_WP))
2790 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2791}
2792
97b7ead3 2793void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2794{
7ffd92c5 2795 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2796 unsigned long hw_cr0;
2797
3de6347b 2798 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2799 if (enable_unrestricted_guest)
5037878e 2800 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2801 else {
5037878e 2802 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2803
218e763f
GN		 2804 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2805 enter_pmode(vcpu);
6aa8b732 2806
218e763f
GN		 2807 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2808 enter_rmode(vcpu);
2809 }
6aa8b732 2810
05b3e0c2 2811#ifdef CONFIG_X86_64
f6801dff 2812 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2813 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2814 enter_lmode(vcpu);
707d92fa 2815 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2816 exit_lmode(vcpu);
2817 }
2818#endif
2819
b4d18517 2820 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2821 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2822
6aa8b732 2823 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2824 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2825 vcpu->arch.cr0 = cr0;
14168786
GN		 2826
2827 /* depends on vcpu->arch.cr0 to be set to a new value */
2828 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2829}
2830
855feb67
YZ		 2831static int get_ept_level(struct kvm_vcpu *vcpu)
2832{
2833 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2834 return 5;
2835 return 4;
2836}
2837
89b0c9f5 2838u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2839{
855feb67
YZ		 2840 u64 eptp = VMX_EPTP_MT_WB;
2841
2842 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 2843
995f00a6
PF		 2844 if (enable_ept_ad_bits &&
2845 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 2846 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 2847 eptp |= (root_hpa & PAGE_MASK);
2848
2849 return eptp;
2850}
2851
97b7ead3 2852void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 2853{
877ad952 2854 struct kvm *kvm = vcpu->kvm;
1439442c
SY		 2855 unsigned long guest_cr3;
2856 u64 eptp;
2857
2858 guest_cr3 = cr3;
089d034e 2859 if (enable_ept) {
995f00a6 2860 eptp = construct_eptp(vcpu, cr3);
1439442c 2861 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 2862
2863 if (kvm_x86_ops->tlb_remote_flush) {
2864 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2865 to_vmx(vcpu)->ept_pointer = eptp;
2866 to_kvm_vmx(kvm)->ept_pointers_match
2867 = EPT_POINTERS_CHECK;
2868 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2869 }
2870
e90008df
SC		 2871 if (enable_unrestricted_guest || is_paging(vcpu) ||
2872 is_guest_mode(vcpu))
59ab5a8f
JK		 2873 guest_cr3 = kvm_read_cr3(vcpu);
2874 else
877ad952 2875 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
7c93be44 2876 ept_load_pdptrs(vcpu);
1439442c
SY		 2877 }
2878
1439442c 2879 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2880}
2881
97b7ead3 2882int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2883{
085e68ee
BS		 2884 /*
2885 * Pass through host's Machine Check Enable value to hw_cr4, which
2886 * is in force while we are in guest mode. Do not let guests control
2887 * this bit, even if host CR4.MCE == 0.
2888 */
5dc1f044
SC		 2889 unsigned long hw_cr4;
2890
2891 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2892 if (enable_unrestricted_guest)
2893 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2894 else if (to_vmx(vcpu)->rmode.vm86_active)
2895 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2896 else
2897 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 2898
64f7a115
SC		 2899 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2900 if (cr4 & X86_CR4_UMIP) {
2901 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
0367f205 2902 SECONDARY_EXEC_DESC);
64f7a115
SC		 2903 hw_cr4 &= ~X86_CR4_UMIP;
2904 } else if (!is_guest_mode(vcpu) ||
2905 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
2906 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
2907 SECONDARY_EXEC_DESC);
2908 }
0367f205 2909
5e1746d6
NHE		 2910 if (cr4 & X86_CR4_VMXE) {
2911 /*
2912 * To use VMXON (and later other VMX instructions), a guest
2913 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2914 * So basically the check on whether to allow nested VMX
5bea5123
PB		 2915 * is here. We operate under the default treatment of SMM,
2916 * so VMX cannot be enabled under SMM.
5e1746d6 2917 */
5bea5123 2918 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 2919 return 1;
1a0d74e6 2920 }
3899152c
DM		 2921
2922 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 2923 return 1;
2924
ad312c7c 2925 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 2926
2927 if (!enable_unrestricted_guest) {
2928 if (enable_ept) {
2929 if (!is_paging(vcpu)) {
2930 hw_cr4 &= ~X86_CR4_PAE;
2931 hw_cr4 |= X86_CR4_PSE;
2932 } else if (!(cr4 & X86_CR4_PAE)) {
2933 hw_cr4 &= ~X86_CR4_PAE;
2934 }
bc23008b 2935 }
1439442c 2936
656ec4a4 2937 /*
ddba2628
HH		 2938 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
2939 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
2940 * to be manually disabled when guest switches to non-paging
2941 * mode.
2942 *
2943 * If !enable_unrestricted_guest, the CPU is always running
2944 * with CR0.PG=1 and CR4 needs to be modified.
2945 * If enable_unrestricted_guest, the CPU automatically
2946 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 2947 */
5dc1f044
SC		 2948 if (!is_paging(vcpu))
2949 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
2950 }
656ec4a4 2951
1439442c
SY		 2952 vmcs_writel(CR4_READ_SHADOW, cr4);
2953 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2954 return 0;
6aa8b732
AK		 2955}
2956
97b7ead3 2957void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 2958{
a9179499 2959 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2960 u32 ar;
2961
c6ad1153 2962 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 2963 *var = vmx->rmode.segs[seg];
a9179499 2964 if (seg == VCPU_SREG_TR
2fb92db1 2965 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 2966 return;
1390a28b
AK		 2967 var->base = vmx_read_guest_seg_base(vmx, seg);
2968 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2969 return;
a9179499 2970 }
2fb92db1
AK		 2971 var->base = vmx_read_guest_seg_base(vmx, seg);
2972 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2973 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2974 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 2975 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 2976 var->type = ar & 15;
2977 var->s = (ar >> 4) & 1;
2978 var->dpl = (ar >> 5) & 3;
03617c18
GN		 2979 /*
2980 * Some userspaces do not preserve unusable property. Since usable
2981 * segment has to be present according to VMX spec we can use present
2982 * property to amend userspace bug by making unusable segment always
2983 * nonpresent. vmx_segment_access_rights() already marks nonpresent
2984 * segment as unusable.
2985 */
2986 var->present = !var->unusable;
6aa8b732
AK		 2987 var->avl = (ar >> 12) & 1;
2988 var->l = (ar >> 13) & 1;
2989 var->db = (ar >> 14) & 1;
2990 var->g = (ar >> 15) & 1;
6aa8b732
AK		 2991}
2992
a9179499
AK		 2993static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2994{
a9179499
AK		 2995 struct kvm_segment s;
2996
2997 if (to_vmx(vcpu)->rmode.vm86_active) {
2998 vmx_get_segment(vcpu, &s, seg);
2999 return s.base;
3000 }
2fb92db1 3001 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3002}
3003
97b7ead3 3004int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3005{
b09408d0
MT		 3006 struct vcpu_vmx *vmx = to_vmx(vcpu);
3007
ae9fedc7 3008 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3009 return 0;
ae9fedc7
PB		 3010 else {
3011 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3012 return VMX_AR_DPL(ar);
69c73028 3013 }
69c73028
AK		 3014}
3015
653e3108 3016static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3017{
6aa8b732
AK		 3018 u32 ar;
3019
f0495f9b 3020 if (var->unusable || !var->present)
6aa8b732
AK		 3021 ar = 1 << 16;
3022 else {
3023 ar = var->type & 15;
3024 ar |= (var->s & 1) << 4;
3025 ar |= (var->dpl & 3) << 5;
3026 ar |= (var->present & 1) << 7;
3027 ar |= (var->avl & 1) << 12;
3028 ar |= (var->l & 1) << 13;
3029 ar |= (var->db & 1) << 14;
3030 ar |= (var->g & 1) << 15;
3031 }
653e3108
AK		 3032
3033 return ar;
3034}
3035
97b7ead3 3036void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3037{
7ffd92c5 3038 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3039 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3040
2fb92db1
AK		 3041 vmx_segment_cache_clear(vmx);
3042
1ecd50a9
GN		 3043 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3044 vmx->rmode.segs[seg] = *var;
3045 if (seg == VCPU_SREG_TR)
3046 vmcs_write16(sf->selector, var->selector);
3047 else if (var->s)
3048 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3049 goto out;
653e3108 3050 }
1ecd50a9 3051
653e3108
AK		 3052 vmcs_writel(sf->base, var->base);
3053 vmcs_write32(sf->limit, var->limit);
3054 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3055
3056 /*
3057 * Fix the "Accessed" bit in AR field of segment registers for older
3058 * qemu binaries.
3059 * IA32 arch specifies that at the time of processor reset the
3060 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3061 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3062 * state vmexit when "unrestricted guest" mode is turned on.
3063 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3064 * tree. Newer qemu binaries with that qemu fix would not need this
3065 * kvm hack.
3066 */
3067 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3068 var->type |= 0x1; /* Accessed */
3a624e29 3069
f924d66d 3070 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3071
3072out:
98eb2f8b 3073 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3074}
3075
6aa8b732
AK		 3076static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3077{
2fb92db1 3078 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3079
3080 *db = (ar >> 14) & 1;
3081 *l = (ar >> 13) & 1;
3082}
3083
89a27f4d 3084static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3085{
89a27f4d
GN		 3086 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3087 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3088}
3089
89a27f4d 3090static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3091{
89a27f4d
GN		 3092 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3093 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3094}
3095
89a27f4d 3096static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3097{
89a27f4d
GN		 3098 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3099 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3100}
3101
89a27f4d 3102static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3103{
89a27f4d
GN		 3104 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3105 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3106}
3107
648dfaa7
MG		 3108static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3109{
3110 struct kvm_segment var;
3111 u32 ar;
3112
3113 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3114 var.dpl = 0x3;
0647f4aa
GN		 3115 if (seg == VCPU_SREG_CS)
3116 var.type = 0x3;
648dfaa7
MG		 3117 ar = vmx_segment_access_rights(&var);
3118
3119 if (var.base != (var.selector << 4))
3120 return false;
89efbed0 3121 if (var.limit != 0xffff)
648dfaa7 3122 return false;
07f42f5f 3123 if (ar != 0xf3)
648dfaa7
MG		 3124 return false;
3125
3126 return true;
3127}
3128
3129static bool code_segment_valid(struct kvm_vcpu *vcpu)
3130{
3131 struct kvm_segment cs;
3132 unsigned int cs_rpl;
3133
3134 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3135 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3136
1872a3f4
AK		 3137 if (cs.unusable)
3138 return false;
4d283ec9 3139 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3140 return false;
3141 if (!cs.s)
3142 return false;
4d283ec9 3143 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3144 if (cs.dpl > cs_rpl)
3145 return false;
1872a3f4 3146 } else {
648dfaa7
MG		 3147 if (cs.dpl != cs_rpl)
3148 return false;
3149 }
3150 if (!cs.present)
3151 return false;
3152
3153 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3154 return true;
3155}
3156
3157static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3158{
3159 struct kvm_segment ss;
3160 unsigned int ss_rpl;
3161
3162 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3163 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3164
1872a3f4
AK		 3165 if (ss.unusable)
3166 return true;
3167 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3168 return false;
3169 if (!ss.s)
3170 return false;
3171 if (ss.dpl != ss_rpl) /* DPL != RPL */
3172 return false;
3173 if (!ss.present)
3174 return false;
3175
3176 return true;
3177}
3178
3179static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3180{
3181 struct kvm_segment var;
3182 unsigned int rpl;
3183
3184 vmx_get_segment(vcpu, &var, seg);
b32a9918 3185 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3186
1872a3f4
AK		 3187 if (var.unusable)
3188 return true;
648dfaa7
MG		 3189 if (!var.s)
3190 return false;
3191 if (!var.present)
3192 return false;
4d283ec9 3193 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3194 if (var.dpl < rpl) /* DPL < RPL */
3195 return false;
3196 }
3197
3198 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3199 * rights flags
3200 */
3201 return true;
3202}
3203
3204static bool tr_valid(struct kvm_vcpu *vcpu)
3205{
3206 struct kvm_segment tr;
3207
3208 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3209
1872a3f4
AK		 3210 if (tr.unusable)
3211 return false;
b32a9918 3212 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3213 return false;
1872a3f4 3214 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3215 return false;
3216 if (!tr.present)
3217 return false;
3218
3219 return true;
3220}
3221
3222static bool ldtr_valid(struct kvm_vcpu *vcpu)
3223{
3224 struct kvm_segment ldtr;
3225
3226 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3227
1872a3f4
AK		 3228 if (ldtr.unusable)
3229 return true;
b32a9918 3230 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3231 return false;
3232 if (ldtr.type != 2)
3233 return false;
3234 if (!ldtr.present)
3235 return false;
3236
3237 return true;
3238}
3239
3240static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3241{
3242 struct kvm_segment cs, ss;
3243
3244 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3245 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3246
b32a9918
NA		 3247 return ((cs.selector & SEGMENT_RPL_MASK) ==
3248 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3249}
3250
3251/*
3252 * Check if guest state is valid. Returns true if valid, false if
3253 * not.
3254 * We assume that registers are always usable
3255 */
3256static bool guest_state_valid(struct kvm_vcpu *vcpu)
3257{
c5e97c80
GN		 3258 if (enable_unrestricted_guest)
3259 return true;
3260
648dfaa7 3261 /* real mode guest state checks */
f13882d8 3262 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3263 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3264 return false;
3265 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3266 return false;
3267 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3268 return false;
3269 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3270 return false;
3271 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3272 return false;
3273 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3274 return false;
3275 } else {
3276 /* protected mode guest state checks */
3277 if (!cs_ss_rpl_check(vcpu))
3278 return false;
3279 if (!code_segment_valid(vcpu))
3280 return false;
3281 if (!stack_segment_valid(vcpu))
3282 return false;
3283 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3284 return false;
3285 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3286 return false;
3287 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3288 return false;
3289 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3290 return false;
3291 if (!tr_valid(vcpu))
3292 return false;
3293 if (!ldtr_valid(vcpu))
3294 return false;
3295 }
3296 /* TODO:
3297 * - Add checks on RIP
3298 * - Add checks on RFLAGS
3299 */
3300
3301 return true;
3302}
3303
d77c26fc 3304static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3305{
40dcaa9f 3306 gfn_t fn;
195aefde 3307 u16 data = 0;
1f755a82 3308 int idx, r;
6aa8b732 3309
40dcaa9f 3310 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3311 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3312 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3313 if (r < 0)
10589a46 3314 goto out;
195aefde 3315 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3316 r = kvm_write_guest_page(kvm, fn++, &data,
3317 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3318 if (r < 0)
10589a46 3319 goto out;
195aefde
IE		 3320 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3321 if (r < 0)
10589a46 3322 goto out;
195aefde
IE		 3323 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3324 if (r < 0)
10589a46 3325 goto out;
195aefde 3326 data = ~0;
10589a46
MT		 3327 r = kvm_write_guest_page(kvm, fn, &data,
3328 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3329 sizeof(u8));
10589a46 3330out:
40dcaa9f 3331 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3332 return r;
6aa8b732
AK		 3333}
3334
b7ebfb05
SY		 3335static int init_rmode_identity_map(struct kvm *kvm)
3336{
40bbb9d0 3337 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
f51770ed 3338 int i, idx, r = 0;
ba049e93 3339 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3340 u32 tmp;
3341
40bbb9d0 3342 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3343 mutex_lock(&kvm->slots_lock);
3344
40bbb9d0 3345 if (likely(kvm_vmx->ept_identity_pagetable_done))
a255d479 3346 goto out2;
a255d479 3347
40bbb9d0
SC		 3348 if (!kvm_vmx->ept_identity_map_addr)
3349 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3350 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3351
d8a6e365 3352 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3353 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3354 if (r < 0)
a255d479
TC		 3355 goto out2;
3356
40dcaa9f 3357 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3358 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3359 if (r < 0)
3360 goto out;
3361 /* Set up identity-mapping pagetable for EPT in real mode */
3362 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3363 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3364 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3365 r = kvm_write_guest_page(kvm, identity_map_pfn,
3366 &tmp, i * sizeof(tmp), sizeof(tmp));
3367 if (r < 0)
3368 goto out;
3369 }
40bbb9d0 3370 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3371
b7ebfb05 3372out:
40dcaa9f 3373 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3374
3375out2:
3376 mutex_unlock(&kvm->slots_lock);
f51770ed 3377 return r;
b7ebfb05
SY		 3378}
3379
6aa8b732
AK		 3380static void seg_setup(int seg)
3381{
772e0318 3382 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3383 unsigned int ar;
6aa8b732
AK		 3384
3385 vmcs_write16(sf->selector, 0);
3386 vmcs_writel(sf->base, 0);
3387 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3388 ar = 0x93;
3389 if (seg == VCPU_SREG_CS)
3390 ar |= 0x08; /* code segment */
3a624e29
NK		 3391
3392 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3393}
3394
f78e0e2e
SY		 3395static int alloc_apic_access_page(struct kvm *kvm)
3396{
4484141a 3397 struct page *page;
f78e0e2e
SY		 3398 int r = 0;
3399
79fac95e 3400 mutex_lock(&kvm->slots_lock);
c24ae0dc 3401 if (kvm->arch.apic_access_page_done)
f78e0e2e 3402 goto out;
1d8007bd
PB		 3403 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3404 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3405 if (r)
3406 goto out;
72dc67a6 3407
73a6d941 3408 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3409 if (is_error_page(page)) {
3410 r = -EFAULT;
3411 goto out;
3412 }
3413
c24ae0dc
TC		 3414 /*
3415 * Do not pin the page in memory, so that memory hot-unplug
3416 * is able to migrate it.
3417 */
3418 put_page(page);
3419 kvm->arch.apic_access_page_done = true;
f78e0e2e 3420out:
79fac95e 3421 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3422 return r;
3423}
3424
97b7ead3 3425int allocate_vpid(void)
2384d2b3
SY		 3426{
3427 int vpid;
3428
919818ab 3429 if (!enable_vpid)
991e7a0e 3430 return 0;
2384d2b3
SY		 3431 spin_lock(&vmx_vpid_lock);
3432 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3433 if (vpid < VMX_NR_VPIDS)
2384d2b3 3434 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3435 else
3436 vpid = 0;
2384d2b3 3437 spin_unlock(&vmx_vpid_lock);
991e7a0e 3438 return vpid;
2384d2b3
SY		 3439}
3440
97b7ead3 3441void free_vpid(int vpid)
cdbecfc3 3442{
991e7a0e 3443 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3444 return;
3445 spin_lock(&vmx_vpid_lock);
991e7a0e 3446 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3447 spin_unlock(&vmx_vpid_lock);
3448}
3449
1e4329ee 3450static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3451 u32 msr, int type)
25c5f225 3452{
3e7c73e9 3453 int f = sizeof(unsigned long);
25c5f225
SY		 3454
3455 if (!cpu_has_vmx_msr_bitmap())
3456 return;
3457
ceef7d10
VK		 3458 if (static_branch_unlikely(&enable_evmcs))
3459 evmcs_touch_msr_bitmap();
3460
25c5f225
SY		 3461 /*
3462 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3463 * have the write-low and read-high bitmap offsets the wrong way round.
3464 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3465 */
25c5f225 3466 if (msr <= 0x1fff) {
8d14695f
YZ		 3467 if (type & MSR_TYPE_R)
3468 /* read-low */
3469 __clear_bit(msr, msr_bitmap + 0x000 / f);
3470
3471 if (type & MSR_TYPE_W)
3472 /* write-low */
3473 __clear_bit(msr, msr_bitmap + 0x800 / f);
3474
25c5f225
SY		 3475 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3476 msr &= 0x1fff;
8d14695f
YZ		 3477 if (type & MSR_TYPE_R)
3478 /* read-high */
3479 __clear_bit(msr, msr_bitmap + 0x400 / f);
3480
3481 if (type & MSR_TYPE_W)
3482 /* write-high */
3483 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3484
3485 }
3486}
3487
1e4329ee 3488static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3489 u32 msr, int type)
3490{
3491 int f = sizeof(unsigned long);
3492
3493 if (!cpu_has_vmx_msr_bitmap())
3494 return;
3495
ceef7d10
VK		 3496 if (static_branch_unlikely(&enable_evmcs))
3497 evmcs_touch_msr_bitmap();
3498
904e14fb
PB		 3499 /*
3500 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3501 * have the write-low and read-high bitmap offsets the wrong way round.
3502 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3503 */
3504 if (msr <= 0x1fff) {
3505 if (type & MSR_TYPE_R)
3506 /* read-low */
3507 __set_bit(msr, msr_bitmap + 0x000 / f);
3508
3509 if (type & MSR_TYPE_W)
3510 /* write-low */
3511 __set_bit(msr, msr_bitmap + 0x800 / f);
3512
3513 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3514 msr &= 0x1fff;
3515 if (type & MSR_TYPE_R)
3516 /* read-high */
3517 __set_bit(msr, msr_bitmap + 0x400 / f);
3518
3519 if (type & MSR_TYPE_W)
3520 /* write-high */
3521 __set_bit(msr, msr_bitmap + 0xc00 / f);
3522
3523 }
3524}
3525
1e4329ee 3526static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3527 u32 msr, int type, bool value)
3528{
3529 if (value)
3530 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3531 else
3532 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3533}
3534
904e14fb 3535static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3536{
904e14fb
PB		 3537 u8 mode = 0;
3538
3539 if (cpu_has_secondary_exec_ctrls() &&
3540 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
3541 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3542 mode |= MSR_BITMAP_MODE_X2APIC;
3543 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3544 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3545 }
3546
904e14fb 3547 return mode;
8d14695f
YZ		 3548}
3549
904e14fb
PB		 3550static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3551 u8 mode)
8d14695f 3552{
904e14fb
PB		 3553 int msr;
3554
3555 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3556 unsigned word = msr / BITS_PER_LONG;
3557 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3558 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3559 }
3560
3561 if (mode & MSR_BITMAP_MODE_X2APIC) {
3562 /*
3563 * TPR reads and writes can be virtualized even if virtual interrupt
3564 * delivery is not in use.
3565 */
3566 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3567 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3568 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3569 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3570 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3571 }
f6e90f9e 3572 }
5897297b
AK		 3573}
3574
97b7ead3 3575void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3576{
3577 struct vcpu_vmx *vmx = to_vmx(vcpu);
3578 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3579 u8 mode = vmx_msr_bitmap_mode(vcpu);
3580 u8 changed = mode ^ vmx->msr_bitmap_mode;
3581
3582 if (!changed)
3583 return;
3584
904e14fb
PB		 3585 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3586 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3587
3588 vmx->msr_bitmap_mode = mode;
3589}
3590
b08c2896
CP		 3591void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3592{
3593 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3594 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3595 u32 i;
3596
3597 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3598 MSR_TYPE_RW, flag);
3599 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3600 MSR_TYPE_RW, flag);
3601 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3602 MSR_TYPE_RW, flag);
3603 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3604 MSR_TYPE_RW, flag);
3605 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3606 vmx_set_intercept_for_msr(msr_bitmap,
3607 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3608 vmx_set_intercept_for_msr(msr_bitmap,
3609 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3610 }
3611}
3612
b2a05fef 3613static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
d50ab6c1 3614{
d62caabb 3615 return enable_apicv;
d50ab6c1
PB		 3616}
3617
e6c67d8c
LA		 3618static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3619{
3620 struct vcpu_vmx *vmx = to_vmx(vcpu);
3621 void *vapic_page;
3622 u32 vppr;
3623 int rvi;
3624
3625 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3626 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
96c66e87 3627 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
e6c67d8c
LA		 3628 return false;
3629
7e712684 3630 rvi = vmx_get_rvi();
e6c67d8c 3631
96c66e87 3632 vapic_page = vmx->nested.virtual_apic_map.hva;
e6c67d8c 3633 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
e6c67d8c
LA		 3634
3635 return ((rvi & 0xf0) > (vppr & 0xf0));
3636}
3637
06a5524f
WV		 3638static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3639 bool nested)
21bc8dc5
RK		 3640{
3641#ifdef CONFIG_SMP
06a5524f
WV		 3642 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3643
21bc8dc5 3644 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3645 /*
5753743f
HZ		 3646 * The vector of interrupt to be delivered to vcpu had
3647 * been set in PIR before this function.
3648 *
3649 * Following cases will be reached in this block, and
3650 * we always send a notification event in all cases as
3651 * explained below.
3652 *
3653 * Case 1: vcpu keeps in non-root mode. Sending a
3654 * notification event posts the interrupt to vcpu.
3655 *
3656 * Case 2: vcpu exits to root mode and is still
3657 * runnable. PIR will be synced to vIRR before the
3658 * next vcpu entry. Sending a notification event in
3659 * this case has no effect, as vcpu is not in root
3660 * mode.
28b835d6 3661 *
5753743f
HZ		 3662 * Case 3: vcpu exits to root mode and is blocked.
3663 * vcpu_block() has already synced PIR to vIRR and
3664 * never blocks vcpu if vIRR is not cleared. Therefore,
3665 * a blocked vcpu here does not wait for any requested
3666 * interrupts in PIR, and sending a notification event
3667 * which has no effect is safe here.
28b835d6 3668 */
28b835d6 3669
06a5524f 3670 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3671 return true;
3672 }
3673#endif
3674 return false;
3675}
3676
705699a1
WV		 3677static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3678 int vector)
3679{
3680 struct vcpu_vmx *vmx = to_vmx(vcpu);
3681
3682 if (is_guest_mode(vcpu) &&
3683 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3684 /*
3685 * If a posted intr is not recognized by hardware,
3686 * we will accomplish it in the next vmentry.
3687 */
3688 vmx->nested.pi_pending = true;
3689 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3690 /* the PIR and ON have been set by L1. */
3691 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3692 kvm_vcpu_kick(vcpu);
705699a1
WV		 3693 return 0;
3694 }
3695 return -1;
3696}
a20ed54d
YZ		 3697/*
3698 * Send interrupt to vcpu via posted interrupt way.
3699 * 1. If target vcpu is running(non-root mode), send posted interrupt
3700 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3701 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3702 * interrupt from PIR in next vmentry.
3703 */
3704static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3705{
3706 struct vcpu_vmx *vmx = to_vmx(vcpu);
3707 int r;
3708
705699a1
WV		 3709 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3710 if (!r)
3711 return;
3712
a20ed54d
YZ		 3713 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3714 return;
3715
b95234c8
PB		 3716 /* If a previous notification has sent the IPI, nothing to do. */
3717 if (pi_test_and_set_on(&vmx->pi_desc))
3718 return;
3719
06a5524f 3720 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ		 3721 kvm_vcpu_kick(vcpu);
3722}
3723
a3a8ff8e
NHE		 3724/*
3725 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3726 * will not change in the lifetime of the guest.
3727 * Note that host-state that does change is set elsewhere. E.g., host-state
3728 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3729 */
97b7ead3 3730void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3731{
3732 u32 low32, high32;
3733 unsigned long tmpl;
3734 struct desc_ptr dt;
d6e41f11 3735 unsigned long cr0, cr3, cr4;
a3a8ff8e 3736
04ac88ab
AL		 3737 cr0 = read_cr0();
3738 WARN_ON(cr0 & X86_CR0_TS);
3739 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3740
3741 /*
3742 * Save the most likely value for this task's CR3 in the VMCS.
3743 * We can't use __get_current_cr3_fast() because we're not atomic.
3744 */
6c690ee1 3745 cr3 = __read_cr3();
d6e41f11 3746 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3747 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3748
d974baa3 3749 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3750 cr4 = cr4_read_shadow();
d974baa3 3751 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3752 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3753
a3a8ff8e 3754 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3755#ifdef CONFIG_X86_64
3756 /*
3757 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3758 * vmx_prepare_switch_to_host(), in case userspace uses
3759 * the null selectors too (the expected case).
b2da15ac
AK		 3760 */
3761 vmcs_write16(HOST_DS_SELECTOR, 0);
3762 vmcs_write16(HOST_ES_SELECTOR, 0);
3763#else
a3a8ff8e
NHE		 3764 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3765 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3766#endif
a3a8ff8e
NHE		 3767 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3768 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3769
87930019 3770 store_idt(&dt);
a3a8ff8e 3771 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 3772 vmx->host_idt_base = dt.address;
a3a8ff8e 3773
453eafbe 3774 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3775
3776 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3777 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3778 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3779 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3780
3781 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3782 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3783 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3784 }
5a5e8a15 3785
c73da3fc 3786 if (cpu_has_load_ia32_efer())
5a5e8a15 3787 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3788}
3789
97b7ead3 3790void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3791{
3792 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3793 if (enable_ept)
3794 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3795 if (is_guest_mode(&vmx->vcpu))
3796 vmx->vcpu.arch.cr4_guest_owned_bits &=
3797 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3798 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3799}
3800
01e439be
YZ		 3801static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3802{
3803 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3804
d62caabb 3805 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3806 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3807
3808 if (!enable_vnmi)
3809 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3810
64672c95
YJ		 3811 /* Enable the preemption timer dynamically */
3812 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 3813 return pin_based_exec_ctrl;
3814}
3815
d62caabb
AS		 3816static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3817{
3818 struct vcpu_vmx *vmx = to_vmx(vcpu);
3819
3820 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3821 if (cpu_has_secondary_exec_ctrls()) {
3822 if (kvm_vcpu_apicv_active(vcpu))
3823 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
3824 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3825 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3826 else
3827 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
3828 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3829 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3830 }
3831
3832 if (cpu_has_vmx_msr_bitmap())
904e14fb 3833 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3834}
3835
89b0c9f5
SC		 3836u32 vmx_exec_control(struct vcpu_vmx *vmx)
3837{
3838 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3839
3840 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3841 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3842
3843 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3844 exec_control &= ~CPU_BASED_TPR_SHADOW;
3845#ifdef CONFIG_X86_64
3846 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3847 CPU_BASED_CR8_LOAD_EXITING;
3848#endif
3849 }
3850 if (!enable_ept)
3851 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3852 CPU_BASED_CR3_LOAD_EXITING |
3853 CPU_BASED_INVLPG_EXITING;
3854 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3855 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3856 CPU_BASED_MONITOR_EXITING);
3857 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3858 exec_control &= ~CPU_BASED_HLT_EXITING;
3859 return exec_control;
3860}
3861
3862
80154d77 3863static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 3864{
80154d77
PB		 3865 struct kvm_vcpu *vcpu = &vmx->vcpu;
3866
bf8179a0 3867 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 3868
f99e3daf
CP		 3869 if (pt_mode == PT_MODE_SYSTEM)
3870 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 3871 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 3872 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3873 if (vmx->vpid == 0)
3874 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3875 if (!enable_ept) {
3876 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3877 enable_unrestricted_guest = 0;
3878 }
3879 if (!enable_unrestricted_guest)
3880 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 3881 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 3882 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 3883 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 3884 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3885 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 3886 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 3887
3888 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3889 * in vmx_set_cr4. */
3890 exec_control &= ~SECONDARY_EXEC_DESC;
3891
abc4fc58
AG		 3892 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3893 (handle_vmptrld).
3894 We can NOT enable shadow_vmcs here because we don't have yet
3895 a current VMCS12
3896 */
3897 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 3898
3899 if (!enable_pml)
3900 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 3901
3db13480
PB		 3902 if (vmx_xsaves_supported()) {
3903 /* Exposing XSAVES only when XSAVE is exposed */
3904 bool xsaves_enabled =
3905 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3906 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3907
3908 if (!xsaves_enabled)
3909 exec_control &= ~SECONDARY_EXEC_XSAVES;
3910
3911 if (nested) {
3912 if (xsaves_enabled)
6677f3da 3913 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 3914 SECONDARY_EXEC_XSAVES;
3915 else
6677f3da 3916 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 3917 ~SECONDARY_EXEC_XSAVES;
3918 }
3919 }
3920
80154d77
PB		 3921 if (vmx_rdtscp_supported()) {
3922 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3923 if (!rdtscp_enabled)
3924 exec_control &= ~SECONDARY_EXEC_RDTSCP;
3925
3926 if (nested) {
3927 if (rdtscp_enabled)
6677f3da 3928 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3929 SECONDARY_EXEC_RDTSCP;
3930 else
6677f3da 3931 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3932 ~SECONDARY_EXEC_RDTSCP;
3933 }
3934 }
3935
3936 if (vmx_invpcid_supported()) {
3937 /* Exposing INVPCID only when PCID is exposed */
3938 bool invpcid_enabled =
3939 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
3940 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
3941
3942 if (!invpcid_enabled) {
3943 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3944 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
3945 }
3946
3947 if (nested) {
3948 if (invpcid_enabled)
6677f3da 3949 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3950 SECONDARY_EXEC_ENABLE_INVPCID;
3951 else
6677f3da 3952 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3953 ~SECONDARY_EXEC_ENABLE_INVPCID;
3954 }
3955 }
3956
45ec368c
JM		 3957 if (vmx_rdrand_supported()) {
3958 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
3959 if (rdrand_enabled)
736fdf72 3960 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3961
3962 if (nested) {
3963 if (rdrand_enabled)
6677f3da 3964 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 3965 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 3966 else
6677f3da 3967 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 3968 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3969 }
3970 }
3971
75f4fc8d
JM		 3972 if (vmx_rdseed_supported()) {
3973 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
3974 if (rdseed_enabled)
736fdf72 3975 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 3976
3977 if (nested) {
3978 if (rdseed_enabled)
6677f3da 3979 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 3980 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 3981 else
6677f3da 3982 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 3983 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 3984 }
3985 }
3986
80154d77 3987 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 3988}
3989
ce88decf
XG		 3990static void ept_set_mmio_spte_mask(void)
3991{
3992 /*
3993 * EPT Misconfigurations can be generated if the value of bits 2:0
3994 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 3995 */
dcdca5fe
PF		 3996 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
3997 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG		 3998}
3999
f53cd63c 4000#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 4001
944c3464
SC		 4002/*
4003 * Sets up the vmcs for emulated real mode.
4004 */
4005static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4006{
4007 int i;
4008
4009 if (nested)
4010 nested_vmx_vcpu_setup();
4011
25c5f225 4012 if (cpu_has_vmx_msr_bitmap())
904e14fb 4013 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4014
6aa8b732
AK		 4015 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4016
6aa8b732 4017 /* Control */
01e439be 4018 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 4019 vmx->hv_deadline_tsc = -1;
6e5d865c 4020
bf8179a0 4021 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4022
dfa169bb 4023 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4024 vmx_compute_secondary_exec_control(vmx);
bf8179a0 4025 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
80154d77 4026 vmx->secondary_exec_control);
dfa169bb 4027 }
f78e0e2e 4028
d62caabb 4029 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4030 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4031 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4032 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4033 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4034
4035 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4036
0bcf261c 4037 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4038 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4039 }
4040
b31c114b 4041 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4042 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4043 vmx->ple_window = ple_window;
4044 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4045 }
4046
c3707958
XG		 4047 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4048 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4049 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4050
9581d442
AK		 4051 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4052 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4053 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4054 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4055 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4056
2a499e49
BD		 4057 if (cpu_has_vmx_vmfunc())
4058 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4059
2cc51560
ED		 4060 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4061 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4062 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4063 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4064 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4065
74545705
RK		 4066 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4067 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4068
03916db9 4069 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4070 u32 index = vmx_msr_index[i];
4071 u32 data_low, data_high;
a2fa3e9f 4072 int j = vmx->nmsrs;
6aa8b732
AK		 4073
4074 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4075 continue;
432bd6cb
AK		 4076 if (wrmsr_safe(index, data_low, data_high) < 0)
4077 continue;
26bb0981
AK		 4078 vmx->guest_msrs[j].index = i;
4079 vmx->guest_msrs[j].data = 0;
d5696725 4080 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4081 ++vmx->nmsrs;
6aa8b732 4082 }
6aa8b732 4083
c73da3fc 4084 vm_exit_controls_init(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4085
4086 /* 22.2.1, 20.8.1 */
c73da3fc 4087 vm_entry_controls_init(vmx, vmx_vmentry_ctrl());
1c3d14fe 4088
bd7e5b08
PB		 4089 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4090 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4091
bf8179a0 4092 set_cr4_guest_host_mask(vmx);
e00c8cf2 4093
f53cd63c
WL		 4094 if (vmx_xsaves_supported())
4095 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4096
4e59516a 4097 if (enable_pml) {
4e59516a
PF		 4098 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4099 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4100 }
0b665d30
SC		 4101
4102 if (cpu_has_vmx_encls_vmexit())
4103 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4104
4105 if (pt_mode == PT_MODE_HOST_GUEST) {
4106 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4107 /* Bit[6~0] are forced to 1, writes are ignored. */
4108 vmx->pt_desc.guest.output_mask = 0x7F;
4109 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4110 }
e00c8cf2
AK		 4111}
4112
d28bc9dd 4113static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4114{
4115 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4116 struct msr_data apic_base_msr;
d28bc9dd 4117 u64 cr0;
e00c8cf2 4118
7ffd92c5 4119 vmx->rmode.vm86_active = 0;
d28b387f 4120 vmx->spec_ctrl = 0;
e00c8cf2 4121
518e7b94 4122 vcpu->arch.microcode_version = 0x100000000ULL;
ad312c7c 4123 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4124 kvm_set_cr8(vcpu, 0);
4125
4126 if (!init_event) {
4127 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4128 MSR_IA32_APICBASE_ENABLE;
4129 if (kvm_vcpu_is_reset_bsp(vcpu))
4130 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4131 apic_base_msr.host_initiated = true;
4132 kvm_set_apic_base(vcpu, &apic_base_msr);
4133 }
e00c8cf2 4134
2fb92db1
AK		 4135 vmx_segment_cache_clear(vmx);
4136
5706be0d 4137 seg_setup(VCPU_SREG_CS);
66450a21 4138 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4139 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4140
4141 seg_setup(VCPU_SREG_DS);
4142 seg_setup(VCPU_SREG_ES);
4143 seg_setup(VCPU_SREG_FS);
4144 seg_setup(VCPU_SREG_GS);
4145 seg_setup(VCPU_SREG_SS);
4146
4147 vmcs_write16(GUEST_TR_SELECTOR, 0);
4148 vmcs_writel(GUEST_TR_BASE, 0);
4149 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4150 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4151
4152 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4153 vmcs_writel(GUEST_LDTR_BASE, 0);
4154 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4155 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4156
d28bc9dd
NA		 4157 if (!init_event) {
4158 vmcs_write32(GUEST_SYSENTER_CS, 0);
4159 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4160 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4161 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4162 }
e00c8cf2 4163
c37c2873 4164 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4165 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4166
e00c8cf2
AK		 4167 vmcs_writel(GUEST_GDTR_BASE, 0);
4168 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4169
4170 vmcs_writel(GUEST_IDTR_BASE, 0);
4171 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4172
443381a8 4173 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4174 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4175 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4176 if (kvm_mpx_supported())
4177 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4178
e00c8cf2
AK		 4179 setup_msrs(vmx);
4180
6aa8b732
AK		 4181 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4182
d28bc9dd 4183 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4184 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4185 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4186 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4187 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4188 vmcs_write32(TPR_THRESHOLD, 0);
4189 }
4190
a73896cb 4191 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4192
2384d2b3
SY		 4193 if (vmx->vpid != 0)
4194 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4195
d28bc9dd 4196 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4197 vmx->vcpu.arch.cr0 = cr0;
f2463247 4198 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4199 vmx_set_cr4(vcpu, 0);
5690891b 4200 vmx_set_efer(vcpu, 0);
bd7e5b08 4201
d28bc9dd 4202 update_exception_bitmap(vcpu);
6aa8b732 4203
dd5f5341 4204 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4205 if (init_event)
4206 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4207}
4208
55d2375e 4209static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4210{
47c0152e
PB		 4211 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
4212 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK		 4213}
4214
c9a7953f 4215static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4216{
d02fcf50 4217 if (!enable_vnmi ||
8a1b4392 4218 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4219 enable_irq_window(vcpu);
4220 return;
4221 }
3b86cd99 4222
47c0152e
PB		 4223 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
4224 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK		 4225}
4226
66fd3f7f 4227static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4228{
9c8cba37 4229 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4230 uint32_t intr;
4231 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4232
229456fc 4233 trace_kvm_inj_virq(irq);
2714d1d3 4234
fa89a817 4235 ++vcpu->stat.irq_injections;
7ffd92c5 4236 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4237 int inc_eip = 0;
4238 if (vcpu->arch.interrupt.soft)
4239 inc_eip = vcpu->arch.event_exit_inst_len;
4240 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4241 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4242 return;
4243 }
66fd3f7f
GN		 4244 intr = irq | INTR_INFO_VALID_MASK;
4245 if (vcpu->arch.interrupt.soft) {
4246 intr |= INTR_TYPE_SOFT_INTR;
4247 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4248 vmx->vcpu.arch.event_exit_inst_len);
4249 } else
4250 intr |= INTR_TYPE_EXT_INTR;
4251 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4252
4253 vmx_clear_hlt(vcpu);
85f455f7
ED		 4254}
4255
f08864b4
SY		 4256static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4257{
66a5a347
JK		 4258 struct vcpu_vmx *vmx = to_vmx(vcpu);
4259
d02fcf50 4260 if (!enable_vnmi) {
8a1b4392
PB		 4261 /*
4262 * Tracking the NMI-blocked state in software is built upon
4263 * finding the next open IRQ window. This, in turn, depends on
4264 * well-behaving guests: They have to keep IRQs disabled at
4265 * least as long as the NMI handler runs. Otherwise we may
4266 * cause NMI nesting, maybe breaking the guest. But as this is
4267 * highly unlikely, we can live with the residual risk.
4268 */
4269 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4270 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4271 }
4272
4c4a6f79
PB		 4273 ++vcpu->stat.nmi_injections;
4274 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4275
7ffd92c5 4276 if (vmx->rmode.vm86_active) {
71f9833b 4277 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4278 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4279 return;
4280 }
c5a6d5f7 4281
f08864b4
SY		 4282 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4283 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4284
4285 vmx_clear_hlt(vcpu);
f08864b4
SY		 4286}
4287
97b7ead3 4288bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4289{
4c4a6f79
PB		 4290 struct vcpu_vmx *vmx = to_vmx(vcpu);
4291 bool masked;
4292
d02fcf50 4293 if (!enable_vnmi)
8a1b4392 4294 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4295 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4296 return false;
4c4a6f79
PB		 4297 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4298 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4299 return masked;
3cfc3092
JK		 4300}
4301
97b7ead3 4302void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4303{
4304 struct vcpu_vmx *vmx = to_vmx(vcpu);
4305
d02fcf50 4306 if (!enable_vnmi) {
8a1b4392
PB		 4307 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4308 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4309 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4310 }
4311 } else {
4312 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4313 if (masked)
4314 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4315 GUEST_INTR_STATE_NMI);
4316 else
4317 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4318 GUEST_INTR_STATE_NMI);
4319 }
3cfc3092
JK		 4320}
4321
2505dc9f
JK		 4322static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4323{
b6b8a145
JK		 4324 if (to_vmx(vcpu)->nested.nested_run_pending)
4325 return 0;
ea8ceb83 4326
d02fcf50 4327 if (!enable_vnmi &&
8a1b4392
PB		 4328 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4329 return 0;
4330
2505dc9f
JK		 4331 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4332 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4333 | GUEST_INTR_STATE_NMI));
4334}
4335
78646121
GN		 4336static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4337{
b6b8a145
JK		 4338 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4339 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4340 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4341 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4342}
4343
cbc94022
IE		 4344static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4345{
4346 int ret;
cbc94022 4347
f7eaeb0a
SC		 4348 if (enable_unrestricted_guest)
4349 return 0;
4350
1d8007bd
PB		 4351 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4352 PAGE_SIZE * 3);
cbc94022
IE		 4353 if (ret)
4354 return ret;
40bbb9d0 4355 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4356 return init_rmode_tss(kvm);
cbc94022
IE		 4357}
4358
2ac52ab8
SC		 4359static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4360{
40bbb9d0 4361 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4362 return 0;
4363}
4364
0ca1b4f4 4365static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4366{
77ab6db0 4367 switch (vec) {
77ab6db0 4368 case BP_VECTOR:
c573cd22
JK		 4369 /*
4370 * Update instruction length as we may reinject the exception
4371 * from user space while in guest debugging mode.
4372 */
4373 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4374 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4375 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4376 return false;
4377 /* fall through */
4378 case DB_VECTOR:
4379 if (vcpu->guest_debug &
4380 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4381 return false;
d0bfb940
JK		 4382 /* fall through */
4383 case DE_VECTOR:
77ab6db0
JK		 4384 case OF_VECTOR:
4385 case BR_VECTOR:
4386 case UD_VECTOR:
4387 case DF_VECTOR:
4388 case SS_VECTOR:
4389 case GP_VECTOR:
4390 case MF_VECTOR:
0ca1b4f4
GN		 4391 return true;
4392 break;
77ab6db0 4393 }
0ca1b4f4
GN		 4394 return false;
4395}
4396
4397static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4398 int vec, u32 err_code)
4399{
4400 /*
4401 * Instruction with address size override prefix opcode 0x67
4402 * Cause the #SS fault with 0 error code in VM86 mode.
4403 */
4404 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
0ce97a2b 4405 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
0ca1b4f4
GN		 4406 if (vcpu->arch.halt_request) {
4407 vcpu->arch.halt_request = 0;
5cb56059 4408 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4409 }
4410 return 1;
4411 }
4412 return 0;
4413 }
4414
4415 /*
4416 * Forward all other exceptions that are valid in real mode.
4417 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4418 * the required debugging infrastructure rework.
4419 */
4420 kvm_queue_exception(vcpu, vec);
4421 return 1;
6aa8b732
AK		 4422}
4423
a0861c02
AK		 4424/*
4425 * Trigger machine check on the host. We assume all the MSRs are already set up
4426 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4427 * We pass a fake environment to the machine check handler because we want
4428 * the guest to be always treated like user space, no matter what context
4429 * it used internally.
4430 */
4431static void kvm_machine_check(void)
4432{
4433#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4434 struct pt_regs regs = {
4435 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4436 .flags = X86_EFLAGS_IF,
4437 };
4438
4439 do_machine_check(&regs, 0);
4440#endif
4441}
4442
851ba692 4443static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4444{
4445 /* already handled by vcpu_run */
4446 return 1;
4447}
4448
851ba692 4449static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4450{
1155f76a 4451 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4452 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4453 u32 intr_info, ex_no, error_code;
42dbaa5a 4454 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4455 u32 vect_info;
4456 enum emulation_result er;
4457
1155f76a 4458 vect_info = vmx->idt_vectoring_info;
88786475 4459 intr_info = vmx->exit_intr_info;
6aa8b732 4460
a0861c02 4461 if (is_machine_check(intr_info))
851ba692 4462 return handle_machine_check(vcpu);
a0861c02 4463
ef85b673 4464 if (is_nmi(intr_info))
1b6269db 4465 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 4466
082d06ed
WL		 4467 if (is_invalid_opcode(intr_info))
4468 return handle_ud(vcpu);
7aa81cc0 4469
6aa8b732 4470 error_code = 0;
2e11384c 4471 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4472 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4473
9e869480
LA		 4474 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4475 WARN_ON_ONCE(!enable_vmware_backdoor);
0ce97a2b 4476 er = kvm_emulate_instruction(vcpu,
9e869480
LA		 4477 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
4478 if (er == EMULATE_USER_EXIT)
4479 return 0;
4480 else if (er != EMULATE_DONE)
4481 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4482 return 1;
4483 }
4484
bf4ca23e
XG		 4485 /*
4486 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4487 * MMIO, it is better to report an internal error.
4488 * See the comments in vmx_handle_exit.
4489 */
4490 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4491 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4492 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4493 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4494 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4495 vcpu->run->internal.data[0] = vect_info;
4496 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4497 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4498 return 0;
4499 }
4500
6aa8b732
AK		 4501 if (is_page_fault(intr_info)) {
4502 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4503 /* EPT won't cause page fault directly */
4504 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4505 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4506 }
4507
d0bfb940 4508 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4509
4510 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4511 return handle_rmode_exception(vcpu, ex_no, error_code);
4512
42dbaa5a 4513 switch (ex_no) {
54a20552
EN		 4514 case AC_VECTOR:
4515 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4516 return 1;
42dbaa5a
JK		 4517 case DB_VECTOR:
4518 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4519 if (!(vcpu->guest_debug &
4520 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4521 vcpu->arch.dr6 &= ~15;
6f43ed01 4522 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4523 if (is_icebp(intr_info))
fd2a445a
HD		 4524 skip_emulated_instruction(vcpu);
4525
42dbaa5a
JK		 4526 kvm_queue_exception(vcpu, DB_VECTOR);
4527 return 1;
4528 }
4529 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4530 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4531 /* fall through */
4532 case BP_VECTOR:
c573cd22
JK		 4533 /*
4534 * Update instruction length as we may reinject #BP from
4535 * user space while in guest debugging mode. Reading it for
4536 * #DB as well causes no harm, it is not used in that case.
4537 */
4538 vmx->vcpu.arch.event_exit_inst_len =
4539 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4540 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4541 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4542 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4543 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4544 break;
4545 default:
d0bfb940
JK		 4546 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4547 kvm_run->ex.exception = ex_no;
4548 kvm_run->ex.error_code = error_code;
42dbaa5a 4549 break;
6aa8b732 4550 }
6aa8b732
AK		 4551 return 0;
4552}
4553
851ba692 4554static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4555{
1165f5fe 4556 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4557 return 1;
4558}
4559
851ba692 4560static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4561{
851ba692 4562 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4563 vcpu->mmio_needed = 0;
988ad74f
AK		 4564 return 0;
4565}
6aa8b732 4566
851ba692 4567static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4568{
bfdaab09 4569 unsigned long exit_qualification;
dca7f128 4570 int size, in, string;
039576c0 4571 unsigned port;
6aa8b732 4572
bfdaab09 4573 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4574 string = (exit_qualification & 16) != 0;
e70669ab 4575
cf8f70bf 4576 ++vcpu->stat.io_exits;
e70669ab 4577
432baf60 4578 if (string)
0ce97a2b 4579 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4580
cf8f70bf
GN		 4581 port = exit_qualification >> 16;
4582 size = (exit_qualification & 7) + 1;
432baf60 4583 in = (exit_qualification & 8) != 0;
cf8f70bf 4584
dca7f128 4585 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4586}
4587
102d8325
IM		 4588static void
4589vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4590{
4591 /*
4592 * Patch in the VMCALL instruction:
4593 */
4594 hypercall[0] = 0x0f;
4595 hypercall[1] = 0x01;
4596 hypercall[2] = 0xc1;
102d8325
IM		 4597}
4598
0fa06071 4599/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4600static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4601{
eeadf9e7 4602 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4603 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4604 unsigned long orig_val = val;
4605
eeadf9e7
NHE		 4606 /*
4607 * We get here when L2 changed cr0 in a way that did not change
4608 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4609 * but did change L0 shadowed bits. So we first calculate the
4610 * effective cr0 value that L1 would like to write into the
4611 * hardware. It consists of the L2-owned bits from the new
4612 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4613 */
1a0d74e6
JK		 4614 val = (val & ~vmcs12->cr0_guest_host_mask) |
4615 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4616
3899152c 4617 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4618 return 1;
1a0d74e6
JK		 4619
4620 if (kvm_set_cr0(vcpu, val))
4621 return 1;
4622 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4623 return 0;
1a0d74e6
JK		 4624 } else {
4625 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4626 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4627 return 1;
3899152c 4628
eeadf9e7 4629 return kvm_set_cr0(vcpu, val);
1a0d74e6 4630 }
eeadf9e7
NHE		 4631}
4632
4633static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4634{
4635 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4636 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4637 unsigned long orig_val = val;
4638
4639 /* analogously to handle_set_cr0 */
4640 val = (val & ~vmcs12->cr4_guest_host_mask) |
4641 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4642 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4643 return 1;
1a0d74e6 4644 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4645 return 0;
4646 } else
4647 return kvm_set_cr4(vcpu, val);
4648}
4649
0367f205
PB		 4650static int handle_desc(struct kvm_vcpu *vcpu)
4651{
4652 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
0ce97a2b 4653 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
0367f205
PB		 4654}
4655
851ba692 4656static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4657{
229456fc 4658 unsigned long exit_qualification, val;
6aa8b732
AK		 4659 int cr;
4660 int reg;
49a9b07e 4661 int err;
6affcbed 4662 int ret;
6aa8b732 4663
bfdaab09 4664 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4665 cr = exit_qualification & 15;
4666 reg = (exit_qualification >> 8) & 15;
4667 switch ((exit_qualification >> 4) & 3) {
4668 case 0: /* mov to cr */
1e32c079 4669 val = kvm_register_readl(vcpu, reg);
229456fc 4670 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4671 switch (cr) {
4672 case 0:
eeadf9e7 4673 err = handle_set_cr0(vcpu, val);
6affcbed 4674 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4675 case 3:
e1de91cc 4676 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4677 err = kvm_set_cr3(vcpu, val);
6affcbed 4678 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4679 case 4:
eeadf9e7 4680 err = handle_set_cr4(vcpu, val);
6affcbed 4681 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4682 case 8: {
4683 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4684 u8 cr8 = (u8)val;
eea1cff9 4685 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4686 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4687 if (lapic_in_kernel(vcpu))
6affcbed 4688 return ret;
0a5fff19 4689 if (cr8_prev <= cr8)
6affcbed
KH		 4690 return ret;
4691 /*
4692 * TODO: we might be squashing a
4693 * KVM_GUESTDBG_SINGLESTEP-triggered
4694 * KVM_EXIT_DEBUG here.
4695 */
851ba692 4696 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4697 return 0;
4698 }
4b8073e4 4699 }
6aa8b732 4700 break;
25c4c276 4701 case 2: /* clts */
bd7e5b08
PB		 4702 WARN_ONCE(1, "Guest should always own CR0.TS");
4703 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4704 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4705 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4706 case 1: /*mov from cr*/
4707 switch (cr) {
4708 case 3:
e1de91cc 4709 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4710 val = kvm_read_cr3(vcpu);
4711 kvm_register_write(vcpu, reg, val);
4712 trace_kvm_cr_read(cr, val);
6affcbed 4713 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4714 case 8:
229456fc
MT		 4715 val = kvm_get_cr8(vcpu);
4716 kvm_register_write(vcpu, reg, val);
4717 trace_kvm_cr_read(cr, val);
6affcbed 4718 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4719 }
4720 break;
4721 case 3: /* lmsw */
a1f83a74 4722 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4723 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4724 kvm_lmsw(vcpu, val);
6aa8b732 4725
6affcbed 4726 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4727 default:
4728 break;
4729 }
851ba692 4730 vcpu->run->exit_reason = 0;
a737f256 4731 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4732 (int)(exit_qualification >> 4) & 3, cr);
4733 return 0;
4734}
4735
851ba692 4736static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4737{
bfdaab09 4738 unsigned long exit_qualification;
16f8a6f9
NA		 4739 int dr, dr7, reg;
4740
4741 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4742 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4743
4744 /* First, if DR does not exist, trigger UD */
4745 if (!kvm_require_dr(vcpu, dr))
4746 return 1;
6aa8b732 4747
f2483415 4748 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4749 if (!kvm_require_cpl(vcpu, 0))
4750 return 1;
16f8a6f9
NA		 4751 dr7 = vmcs_readl(GUEST_DR7);
4752 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4753 /*
4754 * As the vm-exit takes precedence over the debug trap, we
4755 * need to emulate the latter, either for the host or the
4756 * guest debugging itself.
4757 */
4758 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4759 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4760 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4761 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4762 vcpu->run->debug.arch.exception = DB_VECTOR;
4763 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4764 return 0;
4765 } else {
7305eb5d 4766 vcpu->arch.dr6 &= ~15;
6f43ed01 4767 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4768 kvm_queue_exception(vcpu, DB_VECTOR);
4769 return 1;
4770 }
4771 }
4772
81908bf4 4773 if (vcpu->guest_debug == 0) {
8f22372f
PB		 4774 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4775 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4776
4777 /*
4778 * No more DR vmexits; force a reload of the debug registers
4779 * and reenter on this instruction. The next vmexit will
4780 * retrieve the full state of the debug registers.
4781 */
4782 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4783 return 1;
4784 }
4785
42dbaa5a
JK		 4786 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4787 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4788 unsigned long val;
4c4d563b
JK		 4789
4790 if (kvm_get_dr(vcpu, dr, &val))
4791 return 1;
4792 kvm_register_write(vcpu, reg, val);
020df079 4793 } else
5777392e 4794 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4795 return 1;
4796
6affcbed 4797 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4798}
4799
73aaf249
JK		 4800static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4801{
4802 return vcpu->arch.dr6;
4803}
4804
4805static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4806{
4807}
4808
81908bf4
PB		 4809static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4810{
81908bf4
PB		 4811 get_debugreg(vcpu->arch.db[0], 0);
4812 get_debugreg(vcpu->arch.db[1], 1);
4813 get_debugreg(vcpu->arch.db[2], 2);
4814 get_debugreg(vcpu->arch.db[3], 3);
4815 get_debugreg(vcpu->arch.dr6, 6);
4816 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4817
4818 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 4819 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4820}
4821
020df079
GN		 4822static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4823{
4824 vmcs_writel(GUEST_DR7, val);
4825}
4826
851ba692 4827static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4828{
6a908b62 4829 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK		 4830}
4831
851ba692 4832static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4833{
2b3eaf81 4834 u32 ecx = kvm_rcx_read(vcpu);
609e36d3 4835 struct msr_data msr_info;
6aa8b732 4836
609e36d3
PB		 4837 msr_info.index = ecx;
4838 msr_info.host_initiated = false;
4839 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 4840 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4841 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4842 return 1;
4843 }
4844
609e36d3 4845 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 4846
2b3eaf81
SC		 4847 kvm_rax_write(vcpu, msr_info.data & -1u);
4848 kvm_rdx_write(vcpu, (msr_info.data >> 32) & -1u);
6affcbed 4849 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4850}
4851
851ba692 4852static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4853{
8fe8ab46 4854 struct msr_data msr;
2b3eaf81
SC		 4855 u32 ecx = kvm_rcx_read(vcpu);
4856 u64 data = kvm_read_edx_eax(vcpu);
6aa8b732 4857
8fe8ab46
WA		 4858 msr.data = data;
4859 msr.index = ecx;
4860 msr.host_initiated = false;
854e8bb1 4861 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 4862 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4863 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4864 return 1;
4865 }
4866
59200273 4867 trace_kvm_msr_write(ecx, data);
6affcbed 4868 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4869}
4870
851ba692 4871static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4872{
eb90f341 4873 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4874 return 1;
4875}
4876
851ba692 4877static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4878{
47c0152e
PB		 4879 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4880 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 4881
3842d135
AK		 4882 kvm_make_request(KVM_REQ_EVENT, vcpu);
4883
a26bf12a 4884 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4885 return 1;
4886}
4887
851ba692 4888static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 4889{
d3bef15f 4890 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4891}
4892
851ba692 4893static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4894{
0d9c055e 4895 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 4896}
4897
ec25d5e6
GN		 4898static int handle_invd(struct kvm_vcpu *vcpu)
4899{
0ce97a2b 4900 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4901}
4902
851ba692 4903static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4904{
f9c617f6 4905 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4906
4907 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 4908 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 4909}
4910
fee84b07
AK		 4911static int handle_rdpmc(struct kvm_vcpu *vcpu)
4912{
4913 int err;
4914
4915 err = kvm_rdpmc(vcpu);
6affcbed 4916 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 4917}
4918
851ba692 4919static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 4920{
6affcbed 4921 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4922}
4923
2acf923e
DC		 4924static int handle_xsetbv(struct kvm_vcpu *vcpu)
4925{
4926 u64 new_bv = kvm_read_edx_eax(vcpu);
de3cd117 4927 u32 index = kvm_rcx_read(vcpu);
2acf923e
DC		 4928
4929 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 4930 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 4931 return 1;
4932}
4933
f53cd63c
WL		 4934static int handle_xsaves(struct kvm_vcpu *vcpu)
4935{
6affcbed 4936 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4937 WARN(1, "this should never happen\n");
4938 return 1;
4939}
4940
4941static int handle_xrstors(struct kvm_vcpu *vcpu)
4942{
6affcbed 4943 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4944 WARN(1, "this should never happen\n");
4945 return 1;
4946}
4947
851ba692 4948static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4949{
58fbbf26
KT		 4950 if (likely(fasteoi)) {
4951 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4952 int access_type, offset;
4953
4954 access_type = exit_qualification & APIC_ACCESS_TYPE;
4955 offset = exit_qualification & APIC_ACCESS_OFFSET;
4956 /*
4957 * Sane guest uses MOV to write EOI, with written value
4958 * not cared. So make a short-circuit here by avoiding
4959 * heavy instruction emulation.
4960 */
4961 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4962 (offset == APIC_EOI)) {
4963 kvm_lapic_set_eoi(vcpu);
6affcbed 4964 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 4965 }
4966 }
0ce97a2b 4967 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4968}
4969
c7c9c56c
YZ		 4970static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4971{
4972 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4973 int vector = exit_qualification & 0xff;
4974
4975 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4976 kvm_apic_set_eoi_accelerated(vcpu, vector);
4977 return 1;
4978}
4979
83d4c286
YZ		 4980static int handle_apic_write(struct kvm_vcpu *vcpu)
4981{
4982 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4983 u32 offset = exit_qualification & 0xfff;
4984
4985 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4986 kvm_apic_write_nodecode(vcpu, offset);
4987 return 1;
4988}
4989
851ba692 4990static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4991{
60637aac 4992 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4993 unsigned long exit_qualification;
e269fb21
JK		 4994 bool has_error_code = false;
4995 u32 error_code = 0;
37817f29 4996 u16 tss_selector;
7f3d35fd 4997 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4998
4999 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5000 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5001 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5002
5003 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5004
5005 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5006 if (reason == TASK_SWITCH_GATE && idt_v) {
5007 switch (type) {
5008 case INTR_TYPE_NMI_INTR:
5009 vcpu->arch.nmi_injected = false;
654f06fc 5010 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5011 break;
5012 case INTR_TYPE_EXT_INTR:
66fd3f7f 5013 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5014 kvm_clear_interrupt_queue(vcpu);
5015 break;
5016 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5017 if (vmx->idt_vectoring_info &
5018 VECTORING_INFO_DELIVER_CODE_MASK) {
5019 has_error_code = true;
5020 error_code =
5021 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5022 }
5023 /* fall through */
64a7ec06
GN		 5024 case INTR_TYPE_SOFT_EXCEPTION:
5025 kvm_clear_exception_queue(vcpu);
5026 break;
5027 default:
5028 break;
5029 }
60637aac 5030 }
37817f29
IE		 5031 tss_selector = exit_qualification;
5032
64a7ec06
GN		 5033 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5034 type != INTR_TYPE_EXT_INTR &&
5035 type != INTR_TYPE_NMI_INTR))
5036 skip_emulated_instruction(vcpu);
5037
7f3d35fd
KW		 5038 if (kvm_task_switch(vcpu, tss_selector,
5039 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5040 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5041 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5042 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5043 vcpu->run->internal.ndata = 0;
42dbaa5a 5044 return 0;
acb54517 5045 }
42dbaa5a 5046
42dbaa5a
JK		 5047 /*
5048 * TODO: What about debug traps on tss switch?
5049 * Are we supposed to inject them and update dr6?
5050 */
5051
5052 return 1;
37817f29
IE		 5053}
5054
851ba692 5055static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5056{
f9c617f6 5057 unsigned long exit_qualification;
1439442c 5058 gpa_t gpa;
eebed243 5059 u64 error_code;
1439442c 5060
f9c617f6 5061 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5062
0be9c7a8
GN		 5063 /*
5064 * EPT violation happened while executing iret from NMI,
5065 * "blocked by NMI" bit has to be set before next VM entry.
5066 * There are errata that may cause this bit to not be set:
5067 * AAK134, BY25.
5068 */
bcd1c294 5069 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5070 enable_vnmi &&
bcd1c294 5071 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5072 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5073
1439442c 5074 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5075 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5076
27959a44 5077 /* Is it a read fault? */
ab22a473 5078 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5079 ? PFERR_USER_MASK : 0;
5080 /* Is it a write fault? */
ab22a473 5081 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5082 ? PFERR_WRITE_MASK : 0;
5083 /* Is it a fetch fault? */
ab22a473 5084 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5085 ? PFERR_FETCH_MASK : 0;
5086 /* ept page table entry is present? */
5087 error_code |= (exit_qualification &
5088 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5089 EPT_VIOLATION_EXECUTABLE))
5090 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5091
eebed243
PB		 5092 error_code |= (exit_qualification & 0x100) != 0 ?
5093 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5094
25d92081 5095 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5096 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5097}
5098
851ba692 5099static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5100{
68f89400
MT		 5101 gpa_t gpa;
5102
9034e6e8
PB		 5103 /*
5104 * A nested guest cannot optimize MMIO vmexits, because we have an
5105 * nGPA here instead of the required GPA.
5106 */
68f89400 5107 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5108 if (!is_guest_mode(vcpu) &&
5109 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5110 trace_kvm_fast_mmio(gpa);
d391f120
VK		 5111 /*
5112 * Doing kvm_skip_emulated_instruction() depends on undefined
5113 * behavior: Intel's manual doesn't mandate
5114 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5115 * occurs and while on real hardware it was observed to be set,
5116 * other hypervisors (namely Hyper-V) don't set it, we end up
5117 * advancing IP with some random value. Disable fast mmio when
5118 * running nested and keep it for real hardware in hope that
5119 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5120 */
5121 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
5122 return kvm_skip_emulated_instruction(vcpu);
5123 else
0ce97a2b 5124 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
c4409905 5125 EMULATE_DONE;
68c3b4d1 5126 }
68f89400 5127
c75d0edc 5128 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5129}
5130
851ba692 5131static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5132{
d02fcf50 5133 WARN_ON_ONCE(!enable_vnmi);
47c0152e
PB		 5134 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5135 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 5136 ++vcpu->stat.nmi_window_exits;
3842d135 5137 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5138
5139 return 1;
5140}
5141
80ced186 5142static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5143{
8b3079a5
AK		 5144 struct vcpu_vmx *vmx = to_vmx(vcpu);
5145 enum emulation_result err = EMULATE_DONE;
80ced186 5146 int ret = 1;
49e9d557
AK		 5147 u32 cpu_exec_ctrl;
5148 bool intr_window_requested;
b8405c18 5149 unsigned count = 130;
49e9d557 5150
2bb8cafe
SC		 5151 /*
5152 * We should never reach the point where we are emulating L2
5153 * due to invalid guest state as that means we incorrectly
5154 * allowed a nested VMEntry with an invalid vmcs12.
5155 */
5156 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5157
49e9d557
AK		 5158 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5159 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5160
98eb2f8b 5161 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5162 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5163 return handle_interrupt_window(&vmx->vcpu);
5164
72875d8a 5165 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5166 return 1;
5167
0ce97a2b 5168 err = kvm_emulate_instruction(vcpu, 0);
ea953ef0 5169
ac0a48c3 5170 if (err == EMULATE_USER_EXIT) {
94452b9e 5171 ++vcpu->stat.mmio_exits;
80ced186
MG		 5172 ret = 0;
5173 goto out;
5174 }
1d5a4d9b 5175
add5ff7a
SC		 5176 if (err != EMULATE_DONE)
5177 goto emulation_error;
5178
5179 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5180 vcpu->arch.exception.pending)
5181 goto emulation_error;
ea953ef0 5182
8d76c49e
GN		 5183 if (vcpu->arch.halt_request) {
5184 vcpu->arch.halt_request = 0;
5cb56059 5185 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5186 goto out;
5187 }
5188
ea953ef0 5189 if (signal_pending(current))
80ced186 5190 goto out;
ea953ef0
MG		 5191 if (need_resched())
5192 schedule();
5193 }
5194
80ced186
MG		 5195out:
5196 return ret;
b4a2d31d 5197
add5ff7a
SC		 5198emulation_error:
5199 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5200 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5201 vcpu->run->internal.ndata = 0;
5202 return 0;
b4a2d31d
RK		 5203}
5204
5205static void grow_ple_window(struct kvm_vcpu *vcpu)
5206{
5207 struct vcpu_vmx *vmx = to_vmx(vcpu);
5208 int old = vmx->ple_window;
5209
c8e88717
BM		 5210 vmx->ple_window = __grow_ple_window(old, ple_window,
5211 ple_window_grow,
5212 ple_window_max);
b4a2d31d
RK		 5213
5214 if (vmx->ple_window != old)
5215 vmx->ple_window_dirty = true;
7b46268d
RK		 5216
5217 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5218}
5219
5220static void shrink_ple_window(struct kvm_vcpu *vcpu)
5221{
5222 struct vcpu_vmx *vmx = to_vmx(vcpu);
5223 int old = vmx->ple_window;
5224
c8e88717
BM		 5225 vmx->ple_window = __shrink_ple_window(old, ple_window,
5226 ple_window_shrink,
5227 ple_window);
b4a2d31d
RK		 5228
5229 if (vmx->ple_window != old)
5230 vmx->ple_window_dirty = true;
7b46268d
RK		 5231
5232 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5233}
5234
bf9f6ac8
FW		 5235/*
5236 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5237 */
5238static void wakeup_handler(void)
5239{
5240 struct kvm_vcpu *vcpu;
5241 int cpu = smp_processor_id();
5242
5243 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5244 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5245 blocked_vcpu_list) {
5246 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5247
5248 if (pi_test_on(pi_desc) == 1)
5249 kvm_vcpu_kick(vcpu);
5250 }
5251 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5252}
5253
e01bca2f 5254static void vmx_enable_tdp(void)
f160c7b7
JS		 5255{
5256 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5257 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5258 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5259 0ull, VMX_EPT_EXECUTABLE_MASK,
5260 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5261 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5262
5263 ept_set_mmio_spte_mask();
5264 kvm_enable_tdp();
5265}
5266
4b8d54f9
ZE		 5267/*
5268 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5269 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5270 */
9fb41ba8 5271static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5272{
b31c114b 5273 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5274 grow_ple_window(vcpu);
5275
de63ad4c
LM		 5276 /*
5277 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5278 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5279 * never set PAUSE_EXITING and just set PLE if supported,
5280 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5281 */
5282 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5283 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5284}
5285
87c00572 5286static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5287{
6affcbed 5288 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5289}
5290
87c00572
GS		 5291static int handle_mwait(struct kvm_vcpu *vcpu)
5292{
5293 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5294 return handle_nop(vcpu);
5295}
5296
45ec368c
JM		 5297static int handle_invalid_op(struct kvm_vcpu *vcpu)
5298{
5299 kvm_queue_exception(vcpu, UD_VECTOR);
5300 return 1;
5301}
5302
5f3d45e7
MD		 5303static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5304{
5305 return 1;
5306}
5307
87c00572
GS		 5308static int handle_monitor(struct kvm_vcpu *vcpu)
5309{
5310 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5311 return handle_nop(vcpu);
5312}
5313
55d2375e 5314static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5315{
55d2375e
SC		 5316 u32 vmx_instruction_info;
5317 unsigned long type;
5318 bool pcid_enabled;
5319 gva_t gva;
5320 struct x86_exception e;
5321 unsigned i;
5322 unsigned long roots_to_free = 0;
5323 struct {
5324 u64 pcid;
5325 u64 gla;
5326 } operand;
f9eb4af6 5327
55d2375e 5328 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5329 kvm_queue_exception(vcpu, UD_VECTOR);
5330 return 1;
5331 }
5332
55d2375e
SC		 5333 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5334 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5335
5336 if (type > 3) {
5337 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5338 return 1;
5339 }
5340
55d2375e
SC		 5341 /* According to the Intel instruction reference, the memory operand
5342 * is read even if it isn't needed (e.g., for type==all)
5343 */
3573e22c 5344 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
55d2375e 5345 vmx_instruction_info, false, &gva))
3573e22c
BD		 5346 return 1;
5347
55d2375e 5348 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5349 kvm_inject_page_fault(vcpu, &e);
5350 return 1;
5351 }
5352
55d2375e
SC		 5353 if (operand.pcid >> 12 != 0) {
5354 kvm_inject_gp(vcpu, 0);
5355 return 1;
abfc52c6 5356 }
e29acc55 5357
55d2375e 5358 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5359
55d2375e
SC		 5360 switch (type) {
5361 case INVPCID_TYPE_INDIV_ADDR:
5362 if ((!pcid_enabled && (operand.pcid != 0)) ||
5363 is_noncanonical_address(operand.gla, vcpu)) {
5364 kvm_inject_gp(vcpu, 0);
5365 return 1;
5366 }
5367 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5368 return kvm_skip_emulated_instruction(vcpu);
61ada748 5369
55d2375e
SC		 5370 case INVPCID_TYPE_SINGLE_CTXT:
5371 if (!pcid_enabled && (operand.pcid != 0)) {
5372 kvm_inject_gp(vcpu, 0);
5373 return 1;
5374 }
e29acc55 5375
55d2375e
SC		 5376 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5377 kvm_mmu_sync_roots(vcpu);
5378 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5379 }
e29acc55 5380
55d2375e
SC		 5381 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5382 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5383 == operand.pcid)
5384 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5385
55d2375e
SC		 5386 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5387 /*
5388 * If neither the current cr3 nor any of the prev_roots use the
5389 * given PCID, then nothing needs to be done here because a
5390 * resync will happen anyway before switching to any other CR3.
5391 */
e29acc55 5392
55d2375e 5393 return kvm_skip_emulated_instruction(vcpu);
61ada748 5394
55d2375e
SC		 5395 case INVPCID_TYPE_ALL_NON_GLOBAL:
5396 /*
5397 * Currently, KVM doesn't mark global entries in the shadow
5398 * page tables, so a non-global flush just degenerates to a
5399 * global flush. If needed, we could optimize this later by
5400 * keeping track of global entries in shadow page tables.
5401 */
e29acc55 5402
55d2375e
SC		 5403 /* fall-through */
5404 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5405 kvm_mmu_unload(vcpu);
5406 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5407
55d2375e
SC		 5408 default:
5409 BUG(); /* We have already checked above that type <= 3 */
5410 }
e29acc55
JM		 5411}
5412
55d2375e 5413static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5414{
55d2375e 5415 unsigned long exit_qualification;
b3897a49 5416
55d2375e 5417 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5418
55d2375e 5419 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5420
5421 /*
55d2375e
SC		 5422 * PML buffer FULL happened while executing iret from NMI,
5423 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5424 */
55d2375e
SC		 5425 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5426 enable_vnmi &&
5427 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5428 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5429 GUEST_INTR_STATE_NMI);
e49fcb8b 5430
55d2375e
SC		 5431 /*
5432 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5433 * here.., and there's no userspace involvement needed for PML.
5434 */
ec378aee
NHE		 5435 return 1;
5436}
5437
55d2375e 5438static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5439{
55d2375e
SC		 5440 if (!to_vmx(vcpu)->req_immediate_exit)
5441 kvm_lapic_expired_hv_timer(vcpu);
5442 return 1;
8ca44e88
DM		 5443}
5444
55d2375e
SC		 5445/*
5446 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5447 * are overwritten by nested_vmx_setup() when nested=1.
5448 */
5449static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5450{
55d2375e
SC		 5451 kvm_queue_exception(vcpu, UD_VECTOR);
5452 return 1;
b8bbab92
VK		 5453}
5454
55d2375e 5455static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5456{
55d2375e
SC		 5457 /*
5458 * SGX virtualization is not yet supported. There is no software
5459 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5460 * to prevent the guest from executing ENCLS.
5461 */
5462 kvm_queue_exception(vcpu, UD_VECTOR);
5463 return 1;
e7953d7f
AG		 5464}
5465
ec378aee 5466/*
55d2375e
SC		 5467 * The exit handlers return 1 if the exit was handled fully and guest execution
5468 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5469 * to be done to userspace and return 0.
ec378aee 5470 */
55d2375e
SC		 5471static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5472 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5473 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5474 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5475 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5476 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5477 [EXIT_REASON_CR_ACCESS] = handle_cr,
5478 [EXIT_REASON_DR_ACCESS] = handle_dr,
5479 [EXIT_REASON_CPUID] = handle_cpuid,
5480 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5481 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5482 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5483 [EXIT_REASON_HLT] = handle_halt,
5484 [EXIT_REASON_INVD] = handle_invd,
5485 [EXIT_REASON_INVLPG] = handle_invlpg,
5486 [EXIT_REASON_RDPMC] = handle_rdpmc,
5487 [EXIT_REASON_VMCALL] = handle_vmcall,
5488 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5489 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5490 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5491 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5492 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5493 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5494 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5495 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5496 [EXIT_REASON_VMON] = handle_vmx_instruction,
5497 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5498 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5499 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5500 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5501 [EXIT_REASON_WBINVD] = handle_wbinvd,
5502 [EXIT_REASON_XSETBV] = handle_xsetbv,
5503 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5504 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5505 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5506 [EXIT_REASON_LDTR_TR] = handle_desc,
5507 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5508 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5509 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5510 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5511 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5512 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5513 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5514 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5515 [EXIT_REASON_RDRAND] = handle_invalid_op,
5516 [EXIT_REASON_RDSEED] = handle_invalid_op,
5517 [EXIT_REASON_XSAVES] = handle_xsaves,
5518 [EXIT_REASON_XRSTORS] = handle_xrstors,
5519 [EXIT_REASON_PML_FULL] = handle_pml_full,
5520 [EXIT_REASON_INVPCID] = handle_invpcid,
5521 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5522 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5523 [EXIT_REASON_ENCLS] = handle_encls,
5524};
b8bbab92 5525
55d2375e
SC		 5526static const int kvm_vmx_max_exit_handlers =
5527 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5528
55d2375e 5529static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5530{
55d2375e
SC		 5531 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5532 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5533}
5534
55d2375e 5535static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5536{
55d2375e
SC		 5537 if (vmx->pml_pg) {
5538 __free_page(vmx->pml_pg);
5539 vmx->pml_pg = NULL;
b8bbab92 5540 }
27d6c865
NHE		 5541}
5542
55d2375e 5543static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5544{
55d2375e
SC		 5545 struct vcpu_vmx *vmx = to_vmx(vcpu);
5546 u64 *pml_buf;
5547 u16 pml_idx;
cd232ad0 5548
55d2375e 5549 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5550
55d2375e
SC		 5551 /* Do nothing if PML buffer is empty */
5552 if (pml_idx == (PML_ENTITY_NUM - 1))
5553 return;
cd232ad0 5554
55d2375e
SC		 5555 /* PML index always points to next available PML buffer entity */
5556 if (pml_idx >= PML_ENTITY_NUM)
5557 pml_idx = 0;
5558 else
5559 pml_idx++;
945679e3 5560
55d2375e
SC		 5561 pml_buf = page_address(vmx->pml_pg);
5562 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5563 u64 gpa;
945679e3 5564
55d2375e
SC		 5565 gpa = pml_buf[pml_idx];
5566 WARN_ON(gpa & (PAGE_SIZE - 1));
5567 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5568 }
5569
55d2375e
SC		 5570 /* reset PML index */
5571 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5572}
5573
f4160e45 5574/*
55d2375e
SC		 5575 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5576 * Called before reporting dirty_bitmap to userspace.
f4160e45 5577 */
55d2375e 5578static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5579{
55d2375e
SC		 5580 int i;
5581 struct kvm_vcpu *vcpu;
49f705c5 5582 /*
55d2375e
SC		 5583 * We only need to kick vcpu out of guest mode here, as PML buffer
5584 * is flushed at beginning of all VMEXITs, and it's obvious that only
5585 * vcpus running in guest are possible to have unflushed GPAs in PML
5586 * buffer.
49f705c5 5587 */
55d2375e
SC		 5588 kvm_for_each_vcpu(i, vcpu, kvm)
5589 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5590}
5591
55d2375e 5592static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5593{
55d2375e
SC		 5594 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5595 name, vmcs_read16(sel),
5596 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5597 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5598 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5599}
5600
55d2375e 5601static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5602{
55d2375e
SC		 5603 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5604 name, vmcs_read32(limit),
5605 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5606}
5607
69090810 5608void dump_vmcs(void)
63846663 5609{
55d2375e
SC		 5610 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5611 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5612 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5613 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5614 u32 secondary_exec_control = 0;
5615 unsigned long cr4 = vmcs_readl(GUEST_CR4);
5616 u64 efer = vmcs_read64(GUEST_IA32_EFER);
5617 int i, n;
63846663 5618
55d2375e
SC		 5619 if (cpu_has_secondary_exec_ctrls())
5620 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5621
55d2375e
SC		 5622 pr_err("*** Guest State ***\n");
5623 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5624 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5625 vmcs_readl(CR0_GUEST_HOST_MASK));
5626 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5627 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5628 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5629 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5630 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5631 {
5632 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5633 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5634 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5635 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5636 }
55d2375e
SC		 5637 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5638 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5639 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5640 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5641 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5642 vmcs_readl(GUEST_SYSENTER_ESP),
5643 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5644 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5645 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5646 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5647 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5648 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5649 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5650 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5651 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5652 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5653 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5654 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5655 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5656 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5657 efer, vmcs_read64(GUEST_IA32_PAT));
5658 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5659 vmcs_read64(GUEST_IA32_DEBUGCTL),
5660 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5661 if (cpu_has_load_perf_global_ctrl() &&
5662 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5663 pr_err("PerfGlobCtl = 0x%016llx\n",
5664 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5665 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5666 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5667 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5668 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5669 vmcs_read32(GUEST_ACTIVITY_STATE));
5670 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5671 pr_err("InterruptStatus = %04x\n",
5672 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5673
55d2375e
SC		 5674 pr_err("*** Host State ***\n");
5675 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5676 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5677 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5678 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5679 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5680 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5681 vmcs_read16(HOST_TR_SELECTOR));
5682 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5683 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5684 vmcs_readl(HOST_TR_BASE));
5685 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5686 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5687 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5688 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5689 vmcs_readl(HOST_CR4));
5690 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5691 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5692 vmcs_read32(HOST_IA32_SYSENTER_CS),
5693 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5694 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5695 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5696 vmcs_read64(HOST_IA32_EFER),
5697 vmcs_read64(HOST_IA32_PAT));
5698 if (cpu_has_load_perf_global_ctrl() &&
5699 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5700 pr_err("PerfGlobCtl = 0x%016llx\n",
5701 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5702
55d2375e
SC		 5703 pr_err("*** Control State ***\n");
5704 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5705 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5706 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5707 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5708 vmcs_read32(EXCEPTION_BITMAP),
5709 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5710 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5711 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5712 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5713 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5714 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5715 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5716 vmcs_read32(VM_EXIT_INTR_INFO),
5717 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5718 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5719 pr_err(" reason=%08x qualification=%016lx\n",
5720 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5721 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5722 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5723 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5724 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5725 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5726 pr_err("TSC Multiplier = 0x%016llx\n",
5727 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5728 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5729 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5730 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5731 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5732 }
d6a85c32 5733 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9d609649
PB		 5734 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5735 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
d6a85c32 5736 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
9d609649 5737 }
55d2375e
SC		 5738 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5739 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5740 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5741 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5742 n = vmcs_read32(CR3_TARGET_COUNT);
5743 for (i = 0; i + 1 < n; i += 4)
5744 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5745 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5746 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5747 if (i < n)
5748 pr_err("CR3 target%u=%016lx\n",
5749 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5750 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5751 pr_err("PLE Gap=%08x Window=%08x\n",
5752 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5753 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5754 pr_err("Virtual processor ID = 0x%04x\n",
5755 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5756}
5757
55d2375e
SC		 5758/*
5759 * The guest has exited. See if we can fix it or if we need userspace
5760 * assistance.
5761 */
5762static int vmx_handle_exit(struct kvm_vcpu *vcpu)
ff651cb6 5763{
55d2375e
SC		 5764 struct vcpu_vmx *vmx = to_vmx(vcpu);
5765 u32 exit_reason = vmx->exit_reason;
5766 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5767
55d2375e 5768 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5769
55d2375e
SC		 5770 /*
5771 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5772 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5773 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5774 * mode as if vcpus is in root mode, the PML buffer must has been
5775 * flushed already.
5776 */
5777 if (enable_pml)
5778 vmx_flush_pml_buffer(vcpu);
1dc35dac 5779
55d2375e
SC		 5780 /* If guest state is invalid, start emulating */
5781 if (vmx->emulation_required)
5782 return handle_invalid_guest_state(vcpu);
1dc35dac 5783
55d2375e
SC		 5784 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5785 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5786
55d2375e
SC		 5787 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5788 dump_vmcs();
5789 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5790 vcpu->run->fail_entry.hardware_entry_failure_reason
5791 = exit_reason;
5792 return 0;
9ed38ffa
LP		 5793 }
5794
55d2375e
SC		 5795 if (unlikely(vmx->fail)) {
5796 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5797 vcpu->run->fail_entry.hardware_entry_failure_reason
5798 = vmcs_read32(VM_INSTRUCTION_ERROR);
5799 return 0;
5800 }
50c28f21 5801
55d2375e
SC		 5802 /*
5803 * Note:
5804 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5805 * delivery event since it indicates guest is accessing MMIO.
5806 * The vm-exit can be triggered again after return to guest that
5807 * will cause infinite loop.
5808 */
5809 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5810 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5811 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5812 exit_reason != EXIT_REASON_PML_FULL &&
5813 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5814 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5815 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5816 vcpu->run->internal.ndata = 3;
5817 vcpu->run->internal.data[0] = vectoring_info;
5818 vcpu->run->internal.data[1] = exit_reason;
5819 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5820 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5821 vcpu->run->internal.ndata++;
5822 vcpu->run->internal.data[3] =
5823 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5824 }
5825 return 0;
5826 }
50c28f21 5827
55d2375e
SC		 5828 if (unlikely(!enable_vnmi &&
5829 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5830 if (vmx_interrupt_allowed(vcpu)) {
5831 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5832 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5833 vcpu->arch.nmi_pending) {
5834 /*
5835 * This CPU don't support us in finding the end of an
5836 * NMI-blocked window if the guest runs with IRQs
5837 * disabled. So we pull the trigger after 1 s of
5838 * futile waiting, but inform the user about this.
5839 */
5840 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5841 "state on VCPU %d after 1 s timeout\n",
5842 __func__, vcpu->vcpu_id);
5843 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5844 }
5845 }
50c28f21 5846
55d2375e
SC		 5847 if (exit_reason < kvm_vmx_max_exit_handlers
5848 && kvm_vmx_exit_handlers[exit_reason])
5849 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5850 else {
5851 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5852 exit_reason);
5853 kvm_queue_exception(vcpu, UD_VECTOR);
5854 return 1;
5855 }
9ed38ffa
LP		 5856}
5857
efebf0aa 5858/*
55d2375e
SC		 5859 * Software based L1D cache flush which is used when microcode providing
5860 * the cache control MSR is not loaded.
efebf0aa 5861 *
55d2375e
SC		 5862 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5863 * flush it is required to read in 64 KiB because the replacement algorithm
5864 * is not exactly LRU. This could be sized at runtime via topology
5865 * information but as all relevant affected CPUs have 32KiB L1D cache size
5866 * there is no point in doing so.
efebf0aa 5867 */
55d2375e 5868static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5869{
55d2375e 5870 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5871
5872 /*
55d2375e
SC		 5873 * This code is only executed when the the flush mode is 'cond' or
5874 * 'always'
25a2e4fe 5875 */
55d2375e
SC		 5876 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5877 bool flush_l1d;
25a2e4fe 5878
55d2375e
SC		 5879 /*
5880 * Clear the per-vcpu flush bit, it gets set again
5881 * either from vcpu_run() or from one of the unsafe
5882 * VMEXIT handlers.
5883 */
5884 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5885 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5886
55d2375e
SC		 5887 /*
5888 * Clear the per-cpu flush bit, it gets set again from
5889 * the interrupt handlers.
5890 */
5891 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5892 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 5893
55d2375e
SC		 5894 if (!flush_l1d)
5895 return;
5896 }
09abe320 5897
55d2375e 5898 vcpu->stat.l1d_flush++;
25a2e4fe 5899
55d2375e
SC		 5900 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5901 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5902 return;
5903 }
25a2e4fe 5904
55d2375e
SC		 5905 asm volatile(
5906 /* First ensure the pages are in the TLB */
5907 "xorl %%eax, %%eax\n"
5908 ".Lpopulate_tlb:\n\t"
5909 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5910 "addl $4096, %%eax\n\t"
5911 "cmpl %%eax, %[size]\n\t"
5912 "jne .Lpopulate_tlb\n\t"
5913 "xorl %%eax, %%eax\n\t"
5914 "cpuid\n\t"
5915 /* Now fill the cache */
5916 "xorl %%eax, %%eax\n"
5917 ".Lfill_cache:\n"
5918 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5919 "addl $64, %%eax\n\t"
5920 "cmpl %%eax, %[size]\n\t"
5921 "jne .Lfill_cache\n\t"
5922 "lfence\n"
5923 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5924 [size] "r" (size)
5925 : "eax", "ebx", "ecx", "edx");
09abe320 5926}
25a2e4fe 5927
55d2375e 5928static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 5929{
55d2375e 5930 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
09abe320 5931
55d2375e
SC		 5932 if (is_guest_mode(vcpu) &&
5933 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5934 return;
25a2e4fe 5935
55d2375e
SC		 5936 if (irr == -1 || tpr < irr) {
5937 vmcs_write32(TPR_THRESHOLD, 0);
5938 return;
25a2e4fe 5939 }
55d2375e
SC		 5940
5941 vmcs_write32(TPR_THRESHOLD, irr);
8665c3f9
PB		 5942}
5943
55d2375e 5944void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 5945{
55d2375e 5946 u32 sec_exec_control;
8665c3f9 5947
55d2375e
SC		 5948 if (!lapic_in_kernel(vcpu))
5949 return;
9314006d 5950
55d2375e
SC		 5951 if (!flexpriority_enabled &&
5952 !cpu_has_vmx_virtualize_x2apic_mode())
5953 return;
705699a1 5954
55d2375e
SC		 5955 /* Postpone execution until vmcs01 is the current VMCS. */
5956 if (is_guest_mode(vcpu)) {
5957 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
5958 return;
6beb7bd5 5959 }
fe3ef05c 5960
55d2375e
SC		 5961 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5962 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
5963 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 5964
55d2375e
SC		 5965 switch (kvm_get_apic_mode(vcpu)) {
5966 case LAPIC_MODE_INVALID:
5967 WARN_ONCE(true, "Invalid local APIC state");
5968 case LAPIC_MODE_DISABLED:
5969 break;
5970 case LAPIC_MODE_XAPIC:
5971 if (flexpriority_enabled) {
5972 sec_exec_control |=
5973 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5974 vmx_flush_tlb(vcpu, true);
5975 }
5976 break;
5977 case LAPIC_MODE_X2APIC:
5978 if (cpu_has_vmx_virtualize_x2apic_mode())
5979 sec_exec_control |=
5980 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5981 break;
09abe320 5982 }
55d2375e 5983 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
09abe320 5984
55d2375e
SC		 5985 vmx_update_msr_bitmap(vcpu);
5986}
0238ea91 5987
55d2375e
SC		 5988static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
5989{
5990 if (!is_guest_mode(vcpu)) {
5991 vmcs_write64(APIC_ACCESS_ADDR, hpa);
5992 vmx_flush_tlb(vcpu, true);
5993 }
5994}
fe3ef05c 5995
55d2375e
SC		 5996static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5997{
5998 u16 status;
5999 u8 old;
32c7acf0 6000
55d2375e
SC		 6001 if (max_isr == -1)
6002 max_isr = 0;
608406e2 6003
55d2375e
SC		 6004 status = vmcs_read16(GUEST_INTR_STATUS);
6005 old = status >> 8;
6006 if (max_isr != old) {
6007 status &= 0xff;
6008 status |= max_isr << 8;
6009 vmcs_write16(GUEST_INTR_STATUS, status);
6010 }
6011}
6beb7bd5 6012
55d2375e
SC		 6013static void vmx_set_rvi(int vector)
6014{
6015 u16 status;
6016 u8 old;
0b665d30 6017
55d2375e
SC		 6018 if (vector == -1)
6019 vector = 0;
fe3ef05c 6020
55d2375e
SC		 6021 status = vmcs_read16(GUEST_INTR_STATUS);
6022 old = (u8)status & 0xff;
6023 if ((u8)vector != old) {
6024 status &= ~0xff;
6025 status |= (u8)vector;
6026 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6027 }
55d2375e 6028}
09abe320 6029
55d2375e
SC		 6030static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6031{
09abe320 6032 /*
55d2375e
SC		 6033 * When running L2, updating RVI is only relevant when
6034 * vmcs12 virtual-interrupt-delivery enabled.
6035 * However, it can be enabled only when L1 also
6036 * intercepts external-interrupts and in that case
6037 * we should not update vmcs02 RVI but instead intercept
6038 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6039 */
55d2375e
SC		 6040 if (!is_guest_mode(vcpu))
6041 vmx_set_rvi(max_irr);
6042}
fe3ef05c 6043
55d2375e
SC		 6044static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6045{
6046 struct vcpu_vmx *vmx = to_vmx(vcpu);
6047 int max_irr;
6048 bool max_irr_updated;
a7c0b07d 6049
55d2375e
SC		 6050 WARN_ON(!vcpu->arch.apicv_active);
6051 if (pi_test_on(&vmx->pi_desc)) {
6052 pi_clear_on(&vmx->pi_desc);
6053 /*
6054 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6055 * But on x86 this is just a compiler barrier anyway.
6056 */
6057 smp_mb__after_atomic();
6058 max_irr_updated =
6059 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6060
6061 /*
55d2375e
SC		 6062 * If we are running L2 and L1 has a new pending interrupt
6063 * which can be injected, we should re-evaluate
6064 * what should be done with this new L1 interrupt.
6065 * If L1 intercepts external-interrupts, we should
6066 * exit from L2 to L1. Otherwise, interrupt should be
6067 * delivered directly to L2.
c4ebd629 6068 */
55d2375e
SC		 6069 if (is_guest_mode(vcpu) && max_irr_updated) {
6070 if (nested_exit_on_intr(vcpu))
6071 kvm_vcpu_exiting_guest_mode(vcpu);
6072 else
6073 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6074 }
55d2375e
SC		 6075 } else {
6076 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6077 }
55d2375e
SC		 6078 vmx_hwapic_irr_update(vcpu, max_irr);
6079 return max_irr;
6080}
a7c0b07d 6081
55d2375e
SC		 6082static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6083{
6084 if (!kvm_vcpu_apicv_active(vcpu))
6085 return;
25a2e4fe 6086
55d2375e
SC		 6087 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6088 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6089 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6090 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6091}
6092
55d2375e 6093static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6094{
6095 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6096
55d2375e
SC		 6097 pi_clear_on(&vmx->pi_desc);
6098 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6099}
8665c3f9 6100
55d2375e
SC		 6101static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6102{
6103 u32 exit_intr_info = 0;
6104 u16 basic_exit_reason = (u16)vmx->exit_reason;
fe3ef05c 6105
55d2375e
SC		 6106 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6107 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
6108 return;
fe3ef05c 6109
55d2375e
SC		 6110 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6111 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6112 vmx->exit_intr_info = exit_intr_info;
fe3ef05c 6113
55d2375e
SC		 6114 /* if exit due to PF check for async PF */
6115 if (is_page_fault(exit_intr_info))
6116 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 6117
55d2375e
SC		 6118 /* Handle machine checks before interrupts are enabled */
6119 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
6120 is_machine_check(exit_intr_info))
6121 kvm_machine_check();
fe3ef05c 6122
55d2375e
SC		 6123 /* We need to handle NMIs before interrupts are enabled */
6124 if (is_nmi(exit_intr_info)) {
6125 kvm_before_interrupt(&vmx->vcpu);
6126 asm("int $2");
6127 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6128 }
55d2375e 6129}
fe3ef05c 6130
55d2375e
SC		 6131static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6132{
6133 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6134
55d2375e
SC		 6135 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6136 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6137 unsigned int vector;
6138 unsigned long entry;
6139 gate_desc *desc;
6140 struct vcpu_vmx *vmx = to_vmx(vcpu);
6141#ifdef CONFIG_X86_64
6142 unsigned long tmp;
6143#endif
fe3ef05c 6144
55d2375e
SC		 6145 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6146 desc = (gate_desc *)vmx->host_idt_base + vector;
6147 entry = gate_offset(desc);
6148 asm volatile(
6149#ifdef CONFIG_X86_64
6150 "mov %%" _ASM_SP ", %[sp]\n\t"
6151 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6152 "push $%c[ss]\n\t"
6153 "push %[sp]\n\t"
6154#endif
6155 "pushf\n\t"
6156 __ASM_SIZE(push) " $%c[cs]\n\t"
6157 CALL_NOSPEC
6158 :
6159#ifdef CONFIG_X86_64
6160 [sp]"=&r"(tmp),
6161#endif
6162 ASM_CALL_CONSTRAINT
6163 :
6164 THUNK_TARGET(entry),
6165 [ss]"i"(__KERNEL_DS),
6166 [cs]"i"(__KERNEL_CS)
6167 );
6168 }
6169}
6170STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
5a6a9748 6171
55d2375e
SC		 6172static bool vmx_has_emulated_msr(int index)
6173{
6174 switch (index) {
6175 case MSR_IA32_SMBASE:
6176 /*
6177 * We cannot do SMM unless we can run the guest in big
6178 * real mode.
6179 */
6180 return enable_unrestricted_guest || emulate_invalid_guest_state;
6181 case MSR_AMD64_VIRT_SPEC_CTRL:
6182 /* This is AMD only. */
6183 return false;
6184 default:
6185 return true;
3184a995 6186 }
55d2375e 6187}
2bb8cafe 6188
86f5201d
CP		 6189static bool vmx_pt_supported(void)
6190{
6191 return pt_mode == PT_MODE_HOST_GUEST;
6192}
6193
55d2375e
SC		 6194static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6195{
6196 u32 exit_intr_info;
6197 bool unblock_nmi;
6198 u8 vector;
6199 bool idtv_info_valid;
7ca29de2 6200
55d2375e 6201 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6202
55d2375e
SC		 6203 if (enable_vnmi) {
6204 if (vmx->loaded_vmcs->nmi_known_unmasked)
6205 return;
6206 /*
6207 * Can't use vmx->exit_intr_info since we're not sure what
6208 * the exit reason is.
6209 */
6210 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6211 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6212 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6213 /*
6214 * SDM 3: 27.7.1.2 (September 2008)
6215 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6216 * a guest IRET fault.
6217 * SDM 3: 23.2.2 (September 2008)
6218 * Bit 12 is undefined in any of the following cases:
6219 * If the VM exit sets the valid bit in the IDT-vectoring
6220 * information field.
6221 * If the VM exit is due to a double fault.
6222 */
6223 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6224 vector != DF_VECTOR && !idtv_info_valid)
6225 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6226 GUEST_INTR_STATE_NMI);
6227 else
6228 vmx->loaded_vmcs->nmi_known_unmasked =
6229 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6230 & GUEST_INTR_STATE_NMI);
6231 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6232 vmx->loaded_vmcs->vnmi_blocked_time +=
6233 ktime_to_ns(ktime_sub(ktime_get(),
6234 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6235}
6236
55d2375e
SC		 6237static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6238 u32 idt_vectoring_info,
6239 int instr_len_field,
6240 int error_code_field)
0c7f650e 6241{
55d2375e
SC		 6242 u8 vector;
6243 int type;
6244 bool idtv_info_valid;
0c7f650e 6245
55d2375e 6246 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6247
55d2375e
SC		 6248 vcpu->arch.nmi_injected = false;
6249 kvm_clear_exception_queue(vcpu);
6250 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6251
55d2375e
SC		 6252 if (!idtv_info_valid)
6253 return;
c7c2c709 6254
55d2375e 6255 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6256
55d2375e
SC		 6257 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6258 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6259
55d2375e
SC		 6260 switch (type) {
6261 case INTR_TYPE_NMI_INTR:
6262 vcpu->arch.nmi_injected = true;
6263 /*
6264 * SDM 3: 27.7.1.2 (September 2008)
6265 * Clear bit "block by NMI" before VM entry if a NMI
6266 * delivery faulted.
6267 */
6268 vmx_set_nmi_mask(vcpu, false);
6269 break;
6270 case INTR_TYPE_SOFT_EXCEPTION:
6271 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6272 /* fall through */
6273 case INTR_TYPE_HARD_EXCEPTION:
6274 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6275 u32 err = vmcs_read32(error_code_field);
6276 kvm_requeue_exception_e(vcpu, vector, err);
6277 } else
6278 kvm_requeue_exception(vcpu, vector);
6279 break;
6280 case INTR_TYPE_SOFT_INTR:
6281 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6282 /* fall through */
6283 case INTR_TYPE_EXT_INTR:
6284 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6285 break;
6286 default:
6287 break;
0447378a 6288 }
ca0bde28
JM		 6289}
6290
55d2375e 6291static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6292{
55d2375e
SC		 6293 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6294 VM_EXIT_INSTRUCTION_LEN,
6295 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6296}
6297
55d2375e 6298static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6299{
55d2375e
SC		 6300 __vmx_complete_interrupts(vcpu,
6301 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6302 VM_ENTRY_INSTRUCTION_LEN,
6303 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6304
55d2375e 6305 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6306}
6307
55d2375e 6308static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6309{
55d2375e
SC		 6310 int i, nr_msrs;
6311 struct perf_guest_switch_msr *msrs;
7c177938 6312
55d2375e 6313 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6314
55d2375e
SC		 6315 if (!msrs)
6316 return;
f1b026a3 6317
55d2375e
SC		 6318 for (i = 0; i < nr_msrs; i++)
6319 if (msrs[i].host == msrs[i].guest)
6320 clear_atomic_switch_msr(vmx, msrs[i].msr);
6321 else
6322 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6323 msrs[i].host, false);
ca0bde28 6324}
52017608 6325
55d2375e
SC		 6326static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
6327{
6328 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
6329 if (!vmx->loaded_vmcs->hv_timer_armed)
6330 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
6331 PIN_BASED_VMX_PREEMPTION_TIMER);
6332 vmx->loaded_vmcs->hv_timer_armed = true;
6333}
ca0bde28 6334
55d2375e 6335static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6336{
6337 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6338 u64 tscl;
6339 u32 delta_tsc;
52017608 6340
55d2375e
SC		 6341 if (vmx->req_immediate_exit) {
6342 vmx_arm_hv_timer(vmx, 0);
6343 return;
16fb9a46
SC		 6344 }
6345
55d2375e
SC		 6346 if (vmx->hv_deadline_tsc != -1) {
6347 tscl = rdtsc();
6348 if (vmx->hv_deadline_tsc > tscl)
6349 /* set_hv_timer ensures the delta fits in 32-bits */
6350 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6351 cpu_preemption_timer_multi);
6352 else
6353 delta_tsc = 0;
858e25c0 6354
55d2375e
SC		 6355 vmx_arm_hv_timer(vmx, delta_tsc);
6356 return;
7f7f1ba3 6357 }
858e25c0 6358
55d2375e
SC		 6359 if (vmx->loaded_vmcs->hv_timer_armed)
6360 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
6361 PIN_BASED_VMX_PREEMPTION_TIMER);
6362 vmx->loaded_vmcs->hv_timer_armed = false;
858e25c0
JM		 6363}
6364
c09b03eb 6365void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6366{
c09b03eb
SC		 6367 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6368 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6369 vmcs_writel(HOST_RSP, host_rsp);
6370 }
5ad6ece8 6371}
5f3d5799 6372
fc2ba5a2 6373bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6374
6375static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6376{
6377 struct vcpu_vmx *vmx = to_vmx(vcpu);
6378 unsigned long cr3, cr4;
6379
6380 /* Record the guest's net vcpu time for enforced NMI injections. */
6381 if (unlikely(!enable_vnmi &&
6382 vmx->loaded_vmcs->soft_vnmi_blocked))
6383 vmx->loaded_vmcs->entry_time = ktime_get();
6384
6385 /* Don't enter VMX if guest state is invalid, let the exit handler
6386 start emulation until we arrive back to a valid state */
6387 if (vmx->emulation_required)
6388 return;
6389
6390 if (vmx->ple_window_dirty) {
6391 vmx->ple_window_dirty = false;
6392 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6393 }
6394
6395 if (vmx->nested.need_vmcs12_sync)
6396 nested_sync_from_vmcs12(vcpu);
6397
6398 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6399 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6400 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6401 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6402
6403 cr3 = __get_current_cr3_fast();
6404 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6405 vmcs_writel(HOST_CR3, cr3);
6406 vmx->loaded_vmcs->host_state.cr3 = cr3;
6407 }
6408
6409 cr4 = cr4_read_shadow();
6410 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6411 vmcs_writel(HOST_CR4, cr4);
6412 vmx->loaded_vmcs->host_state.cr4 = cr4;
6413 }
6414
6415 /* When single-stepping over STI and MOV SS, we must clear the
6416 * corresponding interruptibility bits in the guest state. Otherwise
6417 * vmentry fails as it then expects bit 14 (BS) in pending debug
6418 * exceptions being set, but that's not correct for the guest debugging
6419 * case. */
6420 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6421 vmx_set_interrupt_shadow(vcpu, 0);
6422
1811d979
WC		 6423 kvm_load_guest_xcr0(vcpu);
6424
5ad6ece8
SC		 6425 if (static_cpu_has(X86_FEATURE_PKU) &&
6426 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6427 vcpu->arch.pkru != vmx->host_pkru)
6428 __write_pkru(vcpu->arch.pkru);
6429
6430 pt_guest_enter(vmx);
6431
6432 atomic_switch_perf_msrs(vmx);
6433
6434 vmx_update_hv_timer(vcpu);
6435
6436 /*
6437 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6438 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6439 * is no need to worry about the conditional branch over the wrmsr
6440 * being speculatively taken.
6441 */
6442 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6443
fa4bff16 6444 /* L1D Flush includes CPU buffer clear to mitigate MDS */
c823dd5c
SC		 6445 if (static_branch_unlikely(&vmx_l1d_should_flush))
6446 vmx_l1d_flush(vcpu);
fa4bff16
LT		 6447 else if (static_branch_unlikely(&mds_user_clear))
6448 mds_clear_cpu_buffers();
c823dd5c
SC		 6449
6450 if (vcpu->arch.cr2 != read_cr2())
6451 write_cr2(vcpu->arch.cr2);
6452
fc2ba5a2
SC		 6453 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6454 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6455
6456 vcpu->arch.cr2 = read_cr2();
b6b8a145 6457
55d2375e
SC		 6458 /*
6459 * We do not use IBRS in the kernel. If this vCPU has used the
6460 * SPEC_CTRL MSR it may have left it on; save the value and
6461 * turn it off. This is much more efficient than blindly adding
6462 * it to the atomic save/restore list. Especially as the former
6463 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6464 *
6465 * For non-nested case:
6466 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6467 * save it.
6468 *
6469 * For nested case:
6470 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6471 * save it.
6472 */
6473 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6474 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6475
55d2375e 6476 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6477
55d2375e
SC		 6478 /* All fields are clean at this point */
6479 if (static_branch_unlikely(&enable_evmcs))
6480 current_evmcs->hv_clean_fields |=
6481 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6482
55d2375e
SC		 6483 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6484 if (vmx->host_debugctlmsr)
6485 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6486
55d2375e
SC		 6487#ifndef CONFIG_X86_64
6488 /*
6489 * The sysexit path does not restore ds/es, so we must set them to
6490 * a reasonable value ourselves.
6491 *
6492 * We can't defer this to vmx_prepare_switch_to_host() since that
6493 * function may be executed in interrupt context, which saves and
6494 * restore segments around it, nullifying its effect.
6495 */
6496 loadsegment(ds, __USER_DS);
6497 loadsegment(es, __USER_DS);
6498#endif
4704d0be 6499
55d2375e
SC		 6500 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6501 | (1 << VCPU_EXREG_RFLAGS)
6502 | (1 << VCPU_EXREG_PDPTR)
6503 | (1 << VCPU_EXREG_SEGMENTS)
6504 | (1 << VCPU_EXREG_CR3));
6505 vcpu->arch.regs_dirty = 0;
7854cbca 6506
2ef444f1
CP		 6507 pt_guest_exit(vmx);
6508
3633cfc3 6509 /*
55d2375e
SC		 6510 * eager fpu is enabled if PKEY is supported and CR4 is switched
6511 * back on host, so it is safe to read guest PKRU from current
6512 * XSAVE.
3633cfc3 6513 */
55d2375e
SC		 6514 if (static_cpu_has(X86_FEATURE_PKU) &&
6515 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
c806e887 6516 vcpu->arch.pkru = rdpkru();
55d2375e
SC		 6517 if (vcpu->arch.pkru != vmx->host_pkru)
6518 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6519 }
6520
1811d979
WC		 6521 kvm_put_guest_xcr0(vcpu);
6522
55d2375e
SC		 6523 vmx->nested.nested_run_pending = 0;
6524 vmx->idt_vectoring_info = 0;
119a9c01 6525
55d2375e
SC		 6526 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6527 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6528 return;
608406e2 6529
55d2375e
SC		 6530 vmx->loaded_vmcs->launched = 1;
6531 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6532
55d2375e
SC		 6533 vmx_complete_atomic_exit(vmx);
6534 vmx_recover_nmi_blocking(vmx);
6535 vmx_complete_interrupts(vmx);
6536}
2996fca0 6537
55d2375e
SC		 6538static struct kvm *vmx_vm_alloc(void)
6539{
41836839
BG		 6540 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6541 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6542 PAGE_KERNEL);
55d2375e 6543 return &kvm_vmx->kvm;
cf8b84f4
JM		 6544}
6545
55d2375e
SC		 6546static void vmx_vm_free(struct kvm *kvm)
6547{
6548 vfree(to_kvm_vmx(kvm));
6549}
6550
6551static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6552{
55d2375e 6553 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6554
55d2375e
SC		 6555 if (enable_pml)
6556 vmx_destroy_pml_buffer(vmx);
6557 free_vpid(vmx->vpid);
55d2375e
SC		 6558 nested_vmx_free_vcpu(vcpu);
6559 free_loaded_vmcs(vmx->loaded_vmcs);
6560 kfree(vmx->guest_msrs);
6561 kvm_vcpu_uninit(vcpu);
b666a4b6 6562 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
55d2375e
SC		 6563 kmem_cache_free(kvm_vcpu_cache, vmx);
6564}
4704d0be 6565
55d2375e
SC		 6566static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6567{
6568 int err;
41836839 6569 struct vcpu_vmx *vmx;
55d2375e
SC		 6570 unsigned long *msr_bitmap;
6571 int cpu;
7313c698 6572
41836839 6573 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6574 if (!vmx)
6575 return ERR_PTR(-ENOMEM);
4704d0be 6576
41836839
BG		 6577 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6578 GFP_KERNEL_ACCOUNT);
b666a4b6
MO		 6579 if (!vmx->vcpu.arch.guest_fpu) {
6580 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6581 err = -ENOMEM;
6582 goto free_partial_vcpu;
6583 }
6584
55d2375e 6585 vmx->vpid = allocate_vpid();
7cdc2d62 6586
55d2375e
SC		 6587 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6588 if (err)
6589 goto free_vcpu;
5f3d5799 6590
55d2375e 6591 err = -ENOMEM;
5f3d5799
JK		 6592
6593 /*
55d2375e
SC		 6594 * If PML is turned on, failure on enabling PML just results in failure
6595 * of creating the vcpu, therefore we can simplify PML logic (by
6596 * avoiding dealing with cases, such as enabling PML partially on vcpus
6597 * for the guest, etc.
5f3d5799 6598 */
55d2375e 6599 if (enable_pml) {
41836839 6600 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e
SC		 6601 if (!vmx->pml_pg)
6602 goto uninit_vcpu;
6603 }
4704d0be 6604
41836839 6605 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6606 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6607 > PAGE_SIZE);
21feb4eb 6608
55d2375e
SC		 6609 if (!vmx->guest_msrs)
6610 goto free_pml;
4704d0be 6611
55d2375e
SC		 6612 err = alloc_loaded_vmcs(&vmx->vmcs01);
6613 if (err < 0)
6614 goto free_msrs;
cb61de2f 6615
55d2375e 6616 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6617 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6618 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6619 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6620 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6621 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6622 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6623 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6624 vmx->msr_bitmap_mode = 0;
4704d0be 6625
55d2375e
SC		 6626 vmx->loaded_vmcs = &vmx->vmcs01;
6627 cpu = get_cpu();
6628 vmx_vcpu_load(&vmx->vcpu, cpu);
6629 vmx->vcpu.cpu = cpu;
6630 vmx_vcpu_setup(vmx);
6631 vmx_vcpu_put(&vmx->vcpu);
6632 put_cpu();
6633 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6634 err = alloc_apic_access_page(kvm);
6635 if (err)
6636 goto free_vmcs;
6637 }
6638
6639 if (enable_ept && !enable_unrestricted_guest) {
6640 err = init_rmode_identity_map(kvm);
6641 if (err)
6642 goto free_vmcs;
6643 }
4704d0be 6644
55d2375e
SC		 6645 if (nested)
6646 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6647 vmx_capability.ept,
6648 kvm_vcpu_apicv_active(&vmx->vcpu));
6649 else
6650 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6651
55d2375e
SC		 6652 vmx->nested.posted_intr_nv = -1;
6653 vmx->nested.current_vmptr = -1ull;
bd18bffc 6654
55d2375e 6655 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
feaf0c7d 6656
6f1e03bc 6657 /*
55d2375e
SC		 6658 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6659 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6660 */
55d2375e
SC		 6661 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6662 vmx->pi_desc.sn = 1;
4704d0be 6663
53963a70
LT		 6664 vmx->ept_pointer = INVALID_PAGE;
6665
55d2375e 6666 return &vmx->vcpu;
4704d0be 6667
55d2375e
SC		 6668free_vmcs:
6669 free_loaded_vmcs(vmx->loaded_vmcs);
6670free_msrs:
6671 kfree(vmx->guest_msrs);
6672free_pml:
6673 vmx_destroy_pml_buffer(vmx);
6674uninit_vcpu:
6675 kvm_vcpu_uninit(&vmx->vcpu);
6676free_vcpu:
6677 free_vpid(vmx->vpid);
b666a4b6
MO		 6678 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6679free_partial_vcpu:
55d2375e
SC		 6680 kmem_cache_free(kvm_vcpu_cache, vmx);
6681 return ERR_PTR(err);
6682}
36be0b9d 6683
65fd4cb6
TG		 6684#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6685#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
21feb4eb 6686
55d2375e
SC		 6687static int vmx_vm_init(struct kvm *kvm)
6688{
6689 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6690
55d2375e
SC		 6691 if (!ple_gap)
6692 kvm->arch.pause_in_guest = true;
3af18d9c 6693
55d2375e
SC		 6694 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6695 switch (l1tf_mitigation) {
6696 case L1TF_MITIGATION_OFF:
6697 case L1TF_MITIGATION_FLUSH_NOWARN:
6698 /* 'I explicitly don't care' is set */
6699 break;
6700 case L1TF_MITIGATION_FLUSH:
6701 case L1TF_MITIGATION_FLUSH_NOSMT:
6702 case L1TF_MITIGATION_FULL:
6703 /*
6704 * Warn upon starting the first VM in a potentially
6705 * insecure environment.
6706 */
b284909a 6707 if (sched_smt_active())
55d2375e
SC		 6708 pr_warn_once(L1TF_MSG_SMT);
6709 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6710 pr_warn_once(L1TF_MSG_L1D);
6711 break;
6712 case L1TF_MITIGATION_FULL_FORCE:
6713 /* Flush is enforced */
6714 break;
6715 }
6716 }
6717 return 0;
4704d0be
NHE		 6718}
6719
55d2375e 6720static void __init vmx_check_processor_compat(void *rtn)
bd18bffc 6721{
55d2375e
SC		 6722 struct vmcs_config vmcs_conf;
6723 struct vmx_capability vmx_cap;
bd18bffc 6724
55d2375e
SC		 6725 *(int *)rtn = 0;
6726 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6727 *(int *)rtn = -EIO;
6728 if (nested)
6729 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6730 enable_apicv);
6731 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6732 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6733 smp_processor_id());
6734 *(int *)rtn = -EIO;
bd18bffc 6735 }
bd18bffc
SC		 6736}
6737
55d2375e 6738static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6739{
55d2375e
SC		 6740 u8 cache;
6741 u64 ipat = 0;
bd18bffc 6742
55d2375e
SC		 6743 /* For VT-d and EPT combination
6744 * 1. MMIO: always map as UC
6745 * 2. EPT with VT-d:
6746 * a. VT-d without snooping control feature: can't guarantee the
6747 * result, try to trust guest.
6748 * b. VT-d with snooping control feature: snooping control feature of
6749 * VT-d engine can guarantee the cache correctness. Just set it
6750 * to WB to keep consistent with host. So the same as item 3.
6751 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6752 * consistent with host MTRR
bd18bffc 6753 */
55d2375e
SC		 6754 if (is_mmio) {
6755 cache = MTRR_TYPE_UNCACHABLE;
6756 goto exit;
6757 }
bd18bffc 6758
55d2375e
SC		 6759 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6760 ipat = VMX_EPT_IPAT_BIT;
6761 cache = MTRR_TYPE_WRBACK;
6762 goto exit;
6763 }
bd18bffc 6764
55d2375e
SC		 6765 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6766 ipat = VMX_EPT_IPAT_BIT;
6767 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6768 cache = MTRR_TYPE_WRBACK;
6769 else
6770 cache = MTRR_TYPE_UNCACHABLE;
6771 goto exit;
6772 }
bd18bffc 6773
55d2375e 6774 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6775
55d2375e
SC		 6776exit:
6777 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6778}
bd18bffc 6779
55d2375e
SC		 6780static int vmx_get_lpage_level(void)
6781{
6782 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6783 return PT_DIRECTORY_LEVEL;
6784 else
6785 /* For shadow and EPT supported 1GB page */
6786 return PT_PDPE_LEVEL;
6787}
bd18bffc 6788
55d2375e
SC		 6789static void vmcs_set_secondary_exec_control(u32 new_ctl)
6790{
bd18bffc 6791 /*
55d2375e
SC		 6792 * These bits in the secondary execution controls field
6793 * are dynamic, the others are mostly based on the hypervisor
6794 * architecture and the guest's CPUID. Do not touch the
6795 * dynamic bits.
bd18bffc 6796 */
55d2375e
SC		 6797 u32 mask =
6798 SECONDARY_EXEC_SHADOW_VMCS |
6799 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6800 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6801 SECONDARY_EXEC_DESC;
bd18bffc 6802
55d2375e 6803 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
bd18bffc 6804
55d2375e
SC		 6805 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6806 (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6807}
6808
4704d0be 6809/*
55d2375e
SC		 6810 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6811 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6812 */
55d2375e 6813static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6814{
6815 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6816 struct kvm_cpuid_entry2 *entry;
4704d0be 6817
55d2375e
SC		 6818 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6819 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6820
55d2375e
SC		 6821#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6822 if (entry && (entry->_reg & (_cpuid_mask))) \
6823 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6824} while (0)
ff651cb6 6825
55d2375e
SC		 6826 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6827 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6828 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6829 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6830 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6831 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6832 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6833 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6834 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6835 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6836 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6837 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6838 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6839 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6840 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
61ada748 6841
55d2375e
SC		 6842 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6843 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6844 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6845 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6846 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6847 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
cf3215d9 6848
55d2375e
SC		 6849#undef cr4_fixed1_update
6850}
36c3cc42 6851
55d2375e
SC		 6852static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6853{
6854 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 6855
55d2375e
SC		 6856 if (kvm_mpx_supported()) {
6857 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 6858
55d2375e
SC		 6859 if (mpx_enabled) {
6860 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6861 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6862 } else {
6863 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6864 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6865 }
dccbfcf5 6866 }
55d2375e 6867}
4704d0be 6868
6c0f0bba
LK		 6869static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6870{
6871 struct vcpu_vmx *vmx = to_vmx(vcpu);
6872 struct kvm_cpuid_entry2 *best = NULL;
6873 int i;
6874
6875 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6876 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6877 if (!best)
6878 return;
6879 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6880 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6881 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6882 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
6883 }
6884
6885 /* Get the number of configurable Address Ranges for filtering */
6886 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
6887 PT_CAP_num_address_ranges);
6888
6889 /* Initialize and clear the no dependency bits */
6890 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
6891 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
6892
6893 /*
6894 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
6895 * will inject an #GP
6896 */
6897 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
6898 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
6899
6900 /*
6901 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
6902 * PSBFreq can be set
6903 */
6904 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
6905 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
6906 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
6907
6908 /*
6909 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
6910 * MTCFreq can be set
6911 */
6912 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
6913 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
6914 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
6915
6916 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
6917 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
6918 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
6919 RTIT_CTL_PTW_EN);
6920
6921 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
6922 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
6923 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
6924
6925 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
6926 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
6927 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
6928
6929 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
6930 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
6931 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
6932
6933 /* unmask address range configure area */
6934 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 6935 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 6936}
6937
55d2375e
SC		 6938static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6939{
6940 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6941
55d2375e
SC		 6942 if (cpu_has_secondary_exec_ctrls()) {
6943 vmx_compute_secondary_exec_control(vmx);
6944 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
705699a1 6945 }
4704d0be 6946
55d2375e
SC		 6947 if (nested_vmx_allowed(vcpu))
6948 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
6949 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6950 else
6951 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
6952 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4f350c6d 6953
55d2375e
SC		 6954 if (nested_vmx_allowed(vcpu)) {
6955 nested_vmx_cr_fixed1_bits_update(vcpu);
6956 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 6957 }
6c0f0bba
LK		 6958
6959 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
6960 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
6961 update_intel_pt_cfg(vcpu);
55d2375e 6962}
09abb5e3 6963
55d2375e
SC		 6964static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6965{
6966 if (func == 1 && nested)
6967 entry->ecx |= bit(X86_FEATURE_VMX);
4704d0be
NHE		 6968}
6969
55d2375e 6970static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 6971{
55d2375e 6972 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 6973}
6974
8a76d7f2
JR		 6975static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6976 struct x86_instruction_info *info,
6977 enum x86_intercept_stage stage)
6978{
fb6d4d34
PB		 6979 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6980 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6981
6982 /*
6983 * RDPID causes #UD if disabled through secondary execution controls.
6984 * Because it is marked as EmulateOnUD, we need to intercept it here.
6985 */
6986 if (info->intercept == x86_intercept_rdtscp &&
6987 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
6988 ctxt->exception.vector = UD_VECTOR;
6989 ctxt->exception.error_code_valid = false;
6990 return X86EMUL_PROPAGATE_FAULT;
6991 }
6992
6993 /* TODO: check more intercepts... */
8a76d7f2
JR		 6994 return X86EMUL_CONTINUE;
6995}
6996
64672c95
YJ		 6997#ifdef CONFIG_X86_64
6998/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
6999static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7000 u64 divisor, u64 *result)
7001{
7002 u64 low = a << shift, high = a >> (64 - shift);
7003
7004 /* To avoid the overflow on divq */
7005 if (high >= divisor)
7006 return 1;
7007
7008 /* Low hold the result, high hold rem which is discarded */
7009 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7010 "rm" (divisor), "0" (low), "1" (high));
7011 *result = low;
7012
7013 return 0;
7014}
7015
f9927982
SC		 7016static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7017 bool *expired)
64672c95 7018{
386c6ddb 7019 struct vcpu_vmx *vmx;
c5ce8235 7020 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
39497d76 7021 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
386c6ddb
KA		 7022
7023 if (kvm_mwait_in_guest(vcpu->kvm))
7024 return -EOPNOTSUPP;
7025
7026 vmx = to_vmx(vcpu);
7027 tscl = rdtsc();
7028 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7029 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
39497d76
SC		 7030 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7031 ktimer->timer_advance_ns);
c5ce8235
WL		 7032
7033 if (delta_tsc > lapic_timer_advance_cycles)
7034 delta_tsc -= lapic_timer_advance_cycles;
7035 else
7036 delta_tsc = 0;
64672c95
YJ		 7037
7038 /* Convert to host delta tsc if tsc scaling is enabled */
7039 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
0967fa1c 7040 delta_tsc && u64_shl_div_u64(delta_tsc,
64672c95 7041 kvm_tsc_scaling_ratio_frac_bits,
0967fa1c 7042 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
64672c95
YJ		 7043 return -ERANGE;
7044
7045 /*
7046 * If the delta tsc can't fit in the 32 bit after the multi shift,
7047 * we can't use the preemption timer.
7048 * It's possible that it fits on later vmentries, but checking
7049 * on every vmentry is costly so we just use an hrtimer.
7050 */
7051 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7052 return -ERANGE;
7053
7054 vmx->hv_deadline_tsc = tscl + delta_tsc;
f9927982
SC		 7055 *expired = !delta_tsc;
7056 return 0;
64672c95
YJ		 7057}
7058
7059static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7060{
f459a707 7061 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7062}
7063#endif
7064
48d89b92 7065static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7066{
b31c114b 7067 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7068 shrink_ple_window(vcpu);
ae97a3b8
RK		 7069}
7070
843e4330
KH		 7071static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7072 struct kvm_memory_slot *slot)
7073{
7074 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7075 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7076}
7077
7078static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7079 struct kvm_memory_slot *slot)
7080{
7081 kvm_mmu_slot_set_dirty(kvm, slot);
7082}
7083
7084static void vmx_flush_log_dirty(struct kvm *kvm)
7085{
7086 kvm_flush_pml_buffers(kvm);
7087}
7088
c5f983f6
BD		 7089static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7090{
7091 struct vmcs12 *vmcs12;
7092 struct vcpu_vmx *vmx = to_vmx(vcpu);
3d5f6beb 7093 gpa_t gpa, dst;
c5f983f6
BD		 7094
7095 if (is_guest_mode(vcpu)) {
7096 WARN_ON_ONCE(vmx->nested.pml_full);
7097
7098 /*
7099 * Check if PML is enabled for the nested guest.
7100 * Whether eptp bit 6 is set is already checked
7101 * as part of A/D emulation.
7102 */
7103 vmcs12 = get_vmcs12(vcpu);
7104 if (!nested_cpu_has_pml(vmcs12))
7105 return 0;
7106
4769886b 7107 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7108 vmx->nested.pml_full = true;
7109 return 1;
7110 }
7111
7112 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
3d5f6beb 7113 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
c5f983f6 7114
3d5f6beb
KA		 7115 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7116 offset_in_page(dst), sizeof(gpa)))
c5f983f6
BD		 7117 return 0;
7118
3d5f6beb 7119 vmcs12->guest_pml_index--;
c5f983f6
BD		 7120 }
7121
7122 return 0;
7123}
7124
843e4330
KH		 7125static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7126 struct kvm_memory_slot *memslot,
7127 gfn_t offset, unsigned long mask)
7128{
7129 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7130}
7131
cd39e117
PB		 7132static void __pi_post_block(struct kvm_vcpu *vcpu)
7133{
7134 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7135 struct pi_desc old, new;
7136 unsigned int dest;
cd39e117
PB		 7137
7138 do {
7139 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7140 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7141 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7142
7143 dest = cpu_physical_id(vcpu->cpu);
7144
7145 if (x2apic_enabled())
7146 new.ndst = dest;
7147 else
7148 new.ndst = (dest << 8) & 0xFF00;
7149
cd39e117
PB		 7150 /* set 'NV' to 'notification vector' */
7151 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7152 } while (cmpxchg64(&pi_desc->control, old.control,
7153 new.control) != old.control);
cd39e117 7154
8b306e2f
PB		 7155 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7156 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7157 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7158 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7159 vcpu->pre_pcpu = -1;
7160 }
7161}
7162
bf9f6ac8
FW		 7163/*
7164 * This routine does the following things for vCPU which is going
7165 * to be blocked if VT-d PI is enabled.
7166 * - Store the vCPU to the wakeup list, so when interrupts happen
7167 * we can find the right vCPU to wake up.
7168 * - Change the Posted-interrupt descriptor as below:
7169 * 'NDST' <-- vcpu->pre_pcpu
7170 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7171 * - If 'ON' is set during this process, which means at least one
7172 * interrupt is posted for this vCPU, we cannot block it, in
7173 * this case, return 1, otherwise, return 0.
7174 *
7175 */
bc22512b 7176static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7177{
bf9f6ac8
FW		 7178 unsigned int dest;
7179 struct pi_desc old, new;
7180 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7181
7182 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7183 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7184 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7185 return 0;
7186
8b306e2f
PB		 7187 WARN_ON(irqs_disabled());
7188 local_irq_disable();
7189 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7190 vcpu->pre_pcpu = vcpu->cpu;
7191 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7192 list_add_tail(&vcpu->blocked_vcpu_list,
7193 &per_cpu(blocked_vcpu_on_cpu,
7194 vcpu->pre_pcpu));
7195 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7196 }
bf9f6ac8
FW		 7197
7198 do {
7199 old.control = new.control = pi_desc->control;
7200
bf9f6ac8
FW		 7201 WARN((pi_desc->sn == 1),
7202 "Warning: SN field of posted-interrupts "
7203 "is set before blocking\n");
7204
7205 /*
7206 * Since vCPU can be preempted during this process,
7207 * vcpu->cpu could be different with pre_pcpu, we
7208 * need to set pre_pcpu as the destination of wakeup
7209 * notification event, then we can find the right vCPU
7210 * to wakeup in wakeup handler if interrupts happen
7211 * when the vCPU is in blocked state.
7212 */
7213 dest = cpu_physical_id(vcpu->pre_pcpu);
7214
7215 if (x2apic_enabled())
7216 new.ndst = dest;
7217 else
7218 new.ndst = (dest << 8) & 0xFF00;
7219
7220 /* set 'NV' to 'wakeup vector' */
7221 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7222 } while (cmpxchg64(&pi_desc->control, old.control,
7223 new.control) != old.control);
bf9f6ac8 7224
8b306e2f
PB		 7225 /* We should not block the vCPU if an interrupt is posted for it. */
7226 if (pi_test_on(pi_desc) == 1)
7227 __pi_post_block(vcpu);
7228
7229 local_irq_enable();
7230 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7231}
7232
bc22512b
YJ		 7233static int vmx_pre_block(struct kvm_vcpu *vcpu)
7234{
7235 if (pi_pre_block(vcpu))
7236 return 1;
7237
64672c95
YJ		 7238 if (kvm_lapic_hv_timer_in_use(vcpu))
7239 kvm_lapic_switch_to_sw_timer(vcpu);
7240
bc22512b
YJ		 7241 return 0;
7242}
7243
7244static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7245{
8b306e2f 7246 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7247 return;
7248
8b306e2f
PB		 7249 WARN_ON(irqs_disabled());
7250 local_irq_disable();
cd39e117 7251 __pi_post_block(vcpu);
8b306e2f 7252 local_irq_enable();
bf9f6ac8
FW		 7253}
7254
bc22512b
YJ		 7255static void vmx_post_block(struct kvm_vcpu *vcpu)
7256{
64672c95
YJ		 7257 if (kvm_x86_ops->set_hv_timer)
7258 kvm_lapic_switch_to_hv_timer(vcpu);
7259
bc22512b
YJ		 7260 pi_post_block(vcpu);
7261}
7262
efc64404
FW		 7263/*
7264 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7265 *
7266 * @kvm: kvm
7267 * @host_irq: host irq of the interrupt
7268 * @guest_irq: gsi of the interrupt
7269 * @set: set or unset PI
7270 * returns 0 on success, < 0 on failure
7271 */
7272static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7273 uint32_t guest_irq, bool set)
7274{
7275 struct kvm_kernel_irq_routing_entry *e;
7276 struct kvm_irq_routing_table *irq_rt;
7277 struct kvm_lapic_irq irq;
7278 struct kvm_vcpu *vcpu;
7279 struct vcpu_data vcpu_info;
3a8b0677 7280 int idx, ret = 0;
efc64404
FW		 7281
7282 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7283 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7284 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7285 return 0;
7286
7287 idx = srcu_read_lock(&kvm->irq_srcu);
7288 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7289 if (guest_irq >= irq_rt->nr_rt_entries ||
7290 hlist_empty(&irq_rt->map[guest_irq])) {
7291 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7292 guest_irq, irq_rt->nr_rt_entries);
7293 goto out;
7294 }
efc64404
FW		 7295
7296 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7297 if (e->type != KVM_IRQ_ROUTING_MSI)
7298 continue;
7299 /*
7300 * VT-d PI cannot support posting multicast/broadcast
7301 * interrupts to a vCPU, we still use interrupt remapping
7302 * for these kind of interrupts.
7303 *
7304 * For lowest-priority interrupts, we only support
7305 * those with single CPU as the destination, e.g. user
7306 * configures the interrupts via /proc/irq or uses
7307 * irqbalance to make the interrupts single-CPU.
7308 *
7309 * We will support full lowest-priority interrupt later.
7310 */
7311
37131313 7312 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW		 7313 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
7314 /*
7315 * Make sure the IRTE is in remapped mode if
7316 * we don't handle it in posted mode.
7317 */
7318 ret = irq_set_vcpu_affinity(host_irq, NULL);
7319 if (ret < 0) {
7320 printk(KERN_INFO
7321 "failed to back to remapped mode, irq: %u\n",
7322 host_irq);
7323 goto out;
7324 }
7325
efc64404 7326 continue;
23a1c257 7327 }
efc64404
FW		 7328
7329 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7330 vcpu_info.vector = irq.vector;
7331
2698d82e 7332 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7333 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7334
7335 if (set)
7336 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7337 else
efc64404 7338 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7339
7340 if (ret < 0) {
7341 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7342 __func__);
7343 goto out;
7344 }
7345 }
7346
7347 ret = 0;
7348out:
7349 srcu_read_unlock(&kvm->irq_srcu, idx);
7350 return ret;
7351}
7352
c45dcc71
AR		 7353static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7354{
7355 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7356 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7357 FEATURE_CONTROL_LMCE;
7358 else
7359 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7360 ~FEATURE_CONTROL_LMCE;
7361}
7362
72d7b374
LP		 7363static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7364{
72e9cbdb
LP		 7365 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7366 if (to_vmx(vcpu)->nested.nested_run_pending)
7367 return 0;
72d7b374
LP		 7368 return 1;
7369}
7370
0234bf88
LP		 7371static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7372{
72e9cbdb
LP		 7373 struct vcpu_vmx *vmx = to_vmx(vcpu);
7374
7375 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7376 if (vmx->nested.smm.guest_mode)
7377 nested_vmx_vmexit(vcpu, -1, 0, 0);
7378
7379 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7380 vmx->nested.vmxon = false;
caa057a2 7381 vmx_clear_hlt(vcpu);
0234bf88
LP		 7382 return 0;
7383}
7384
ed19321f 7385static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7386{
72e9cbdb
LP		 7387 struct vcpu_vmx *vmx = to_vmx(vcpu);
7388 int ret;
7389
7390 if (vmx->nested.smm.vmxon) {
7391 vmx->nested.vmxon = true;
7392 vmx->nested.smm.vmxon = false;
7393 }
7394
7395 if (vmx->nested.smm.guest_mode) {
a633e41e 7396 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7397 if (ret)
7398 return ret;
7399
7400 vmx->nested.smm.guest_mode = false;
7401 }
0234bf88
LP		 7402 return 0;
7403}
7404
cc3d967f
LP		 7405static int enable_smi_window(struct kvm_vcpu *vcpu)
7406{
7407 return 0;
7408}
7409
05d5a486
SB		 7410static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7411{
7412 return 0;
7413}
7414
a3203381
SC		 7415static __init int hardware_setup(void)
7416{
7417 unsigned long host_bndcfgs;
7418 int r, i;
7419
7420 rdmsrl_safe(MSR_EFER, &host_efer);
7421
7422 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7423 kvm_define_shared_msr(i, vmx_msr_index[i]);
7424
7425 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7426 return -EIO;
7427
7428 if (boot_cpu_has(X86_FEATURE_NX))
7429 kvm_enable_efer_bits(EFER_NX);
7430
7431 if (boot_cpu_has(X86_FEATURE_MPX)) {
7432 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7433 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7434 }
7435
7436 if (boot_cpu_has(X86_FEATURE_XSAVES))
7437 rdmsrl(MSR_IA32_XSS, host_xss);
7438
7439 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7440 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7441 enable_vpid = 0;
7442
7443 if (!cpu_has_vmx_ept() ||
7444 !cpu_has_vmx_ept_4levels() ||
7445 !cpu_has_vmx_ept_mt_wb() ||
7446 !cpu_has_vmx_invept_global())
7447 enable_ept = 0;
7448
7449 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7450 enable_ept_ad_bits = 0;
7451
7452 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7453 enable_unrestricted_guest = 0;
7454
7455 if (!cpu_has_vmx_flexpriority())
7456 flexpriority_enabled = 0;
7457
7458 if (!cpu_has_virtual_nmis())
7459 enable_vnmi = 0;
7460
7461 /*
7462 * set_apic_access_page_addr() is used to reload apic access
7463 * page upon invalidation. No need to do anything if not
7464 * using the APIC_ACCESS_ADDR VMCS field.
7465 */
7466 if (!flexpriority_enabled)
7467 kvm_x86_ops->set_apic_access_page_addr = NULL;
7468
7469 if (!cpu_has_vmx_tpr_shadow())
7470 kvm_x86_ops->update_cr8_intercept = NULL;
7471
7472 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7473 kvm_disable_largepages();
7474
7475#if IS_ENABLED(CONFIG_HYPERV)
7476 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7477 && enable_ept) {
7478 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7479 kvm_x86_ops->tlb_remote_flush_with_range =
7480 hv_remote_flush_tlb_with_range;
7481 }
a3203381
SC		 7482#endif
7483
7484 if (!cpu_has_vmx_ple()) {
7485 ple_gap = 0;
7486 ple_window = 0;
7487 ple_window_grow = 0;
7488 ple_window_max = 0;
7489 ple_window_shrink = 0;
7490 }
7491
7492 if (!cpu_has_vmx_apicv()) {
7493 enable_apicv = 0;
7494 kvm_x86_ops->sync_pir_to_irr = NULL;
7495 }
7496
7497 if (cpu_has_vmx_tsc_scaling()) {
7498 kvm_has_tsc_control = true;
7499 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7500 kvm_tsc_scaling_ratio_frac_bits = 48;
7501 }
7502
7503 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7504
7505 if (enable_ept)
7506 vmx_enable_tdp();
7507 else
7508 kvm_disable_tdp();
7509
a3203381
SC		 7510 /*
7511 * Only enable PML when hardware supports PML feature, and both EPT
7512 * and EPT A/D bit features are enabled -- PML depends on them to work.
7513 */
7514 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7515 enable_pml = 0;
7516
7517 if (!enable_pml) {
7518 kvm_x86_ops->slot_enable_log_dirty = NULL;
7519 kvm_x86_ops->slot_disable_log_dirty = NULL;
7520 kvm_x86_ops->flush_log_dirty = NULL;
7521 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7522 }
7523
7524 if (!cpu_has_vmx_preemption_timer())
7525 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7526
7527 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7528 u64 vmx_msr;
7529
7530 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7531 cpu_preemption_timer_multi =
7532 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7533 } else {
7534 kvm_x86_ops->set_hv_timer = NULL;
7535 kvm_x86_ops->cancel_hv_timer = NULL;
7536 }
7537
a3203381 7538 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7539
7540 kvm_mce_cap_supported |= MCG_LMCE_P;
7541
f99e3daf
CP		 7542 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7543 return -EINVAL;
7544 if (!enable_ept || !cpu_has_vmx_intel_pt())
7545 pt_mode = PT_MODE_SYSTEM;
7546
a3203381 7547 if (nested) {
3e8eaccc
SC		 7548 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7549 vmx_capability.ept, enable_apicv);
7550
e4027cfa 7551 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7552 if (r)
7553 return r;
7554 }
7555
7556 r = alloc_kvm_area();
7557 if (r)
7558 nested_vmx_hardware_unsetup();
7559 return r;
7560}
7561
7562static __exit void hardware_unsetup(void)
7563{
7564 if (nested)
7565 nested_vmx_hardware_unsetup();
7566
7567 free_kvm_area();
7568}
7569
404f6aac 7570static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7571 .cpu_has_kvm_support = cpu_has_kvm_support,
7572 .disabled_by_bios = vmx_disabled_by_bios,
7573 .hardware_setup = hardware_setup,
7574 .hardware_unsetup = hardware_unsetup,
002c7f7c 7575 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7576 .hardware_enable = hardware_enable,
7577 .hardware_disable = hardware_disable,
04547156 7578 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7579 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7580
b31c114b 7581 .vm_init = vmx_vm_init,
434a1e94
SC		 7582 .vm_alloc = vmx_vm_alloc,
7583 .vm_free = vmx_vm_free,
b31c114b 7584
6aa8b732
AK		 7585 .vcpu_create = vmx_create_vcpu,
7586 .vcpu_free = vmx_free_vcpu,
04d2cc77 7587 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7588
6d6095bd 7589 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7590 .vcpu_load = vmx_vcpu_load,
7591 .vcpu_put = vmx_vcpu_put,
7592
a96036b8 7593 .update_bp_intercept = update_exception_bitmap,
801e459a 7594 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7595 .get_msr = vmx_get_msr,
7596 .set_msr = vmx_set_msr,
7597 .get_segment_base = vmx_get_segment_base,
7598 .get_segment = vmx_get_segment,
7599 .set_segment = vmx_set_segment,
2e4d2653 7600 .get_cpl = vmx_get_cpl,
6aa8b732 7601 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7602 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7603 .decache_cr3 = vmx_decache_cr3,
25c4c276 7604 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7605 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7606 .set_cr3 = vmx_set_cr3,
7607 .set_cr4 = vmx_set_cr4,
6aa8b732 7608 .set_efer = vmx_set_efer,
6aa8b732
AK		 7609 .get_idt = vmx_get_idt,
7610 .set_idt = vmx_set_idt,
7611 .get_gdt = vmx_get_gdt,
7612 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7613 .get_dr6 = vmx_get_dr6,
7614 .set_dr6 = vmx_set_dr6,
020df079 7615 .set_dr7 = vmx_set_dr7,
81908bf4 7616 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7617 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7618 .get_rflags = vmx_get_rflags,
7619 .set_rflags = vmx_set_rflags,
be94f6b7 7620
6aa8b732 7621 .tlb_flush = vmx_flush_tlb,
faff8758 7622 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7623
6aa8b732 7624 .run = vmx_vcpu_run,
6062d012 7625 .handle_exit = vmx_handle_exit,
6aa8b732 7626 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7627 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7628 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7629 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7630 .set_irq = vmx_inject_irq,
95ba8273 7631 .set_nmi = vmx_inject_nmi,
298101da 7632 .queue_exception = vmx_queue_exception,
b463a6f7 7633 .cancel_injection = vmx_cancel_injection,
78646121 7634 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7635 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7636 .get_nmi_mask = vmx_get_nmi_mask,
7637 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7638 .enable_nmi_window = enable_nmi_window,
7639 .enable_irq_window = enable_irq_window,
7640 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7641 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7642 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS		 7643 .get_enable_apicv = vmx_get_enable_apicv,
7644 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7645 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7646 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ		 7647 .hwapic_irr_update = vmx_hwapic_irr_update,
7648 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7649 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7650 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7651 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 7652
cbc94022 7653 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7654 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7655 .get_tdp_level = get_ept_level,
4b12f0de 7656 .get_mt_mask = vmx_get_mt_mask,
229456fc 7657
586f9607 7658 .get_exit_info = vmx_get_exit_info,
586f9607 7659
17cc3935 7660 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7661
7662 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7663
7664 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7665 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7666
7667 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7668
7669 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7670
e79f245d 7671 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7672 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7673
7674 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7675
7676 .check_intercept = vmx_check_intercept,
a547c6db 7677 .handle_external_intr = vmx_handle_external_intr,
da8999d3 7678 .mpx_supported = vmx_mpx_supported,
55412b2e 7679 .xsaves_supported = vmx_xsaves_supported,
66336cab 7680 .umip_emulated = vmx_umip_emulated,
86f5201d 7681 .pt_supported = vmx_pt_supported,
b6b8a145 7682
d264ee0c 7683 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7684
7685 .sched_in = vmx_sched_in,
843e4330
KH		 7686
7687 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7688 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7689 .flush_log_dirty = vmx_flush_log_dirty,
7690 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7691 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7692
bf9f6ac8
FW		 7693 .pre_block = vmx_pre_block,
7694 .post_block = vmx_post_block,
7695
25462f7f 7696 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7697
7698 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7699
7700#ifdef CONFIG_X86_64
7701 .set_hv_timer = vmx_set_hv_timer,
7702 .cancel_hv_timer = vmx_cancel_hv_timer,
7703#endif
c45dcc71
AR		 7704
7705 .setup_mce = vmx_setup_mce,
0234bf88 7706
72d7b374 7707 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7708 .pre_enter_smm = vmx_pre_enter_smm,
7709 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7710 .enable_smi_window = enable_smi_window,
57b119da 7711
e4027cfa
SC		 7712 .check_nested_events = NULL,
7713 .get_nested_state = NULL,
7714 .set_nested_state = NULL,
7715 .get_vmcs12_pages = NULL,
7716 .nested_enable_evmcs = NULL,
05d5a486 7717 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
6aa8b732
AK		 7718};
7719
72c6d2db 7720static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7721{
7722 if (vmx_l1d_flush_pages) {
7723 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7724 vmx_l1d_flush_pages = NULL;
7725 }
72c6d2db
TG		 7726 /* Restore state so sysfs ignores VMX */
7727 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7728}
7729
a7b9020b
TG		 7730static void vmx_exit(void)
7731{
7732#ifdef CONFIG_KEXEC_CORE
7733 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7734 synchronize_rcu();
7735#endif
7736
7737 kvm_exit();
7738
7739#if IS_ENABLED(CONFIG_HYPERV)
7740 if (static_branch_unlikely(&enable_evmcs)) {
7741 int cpu;
7742 struct hv_vp_assist_page *vp_ap;
7743 /*
7744 * Reset everything to support using non-enlightened VMCS
7745 * access later (e.g. when we reload the module with
7746 * enlightened_vmcs=0)
7747 */
7748 for_each_online_cpu(cpu) {
7749 vp_ap = hv_get_vp_assist_page(cpu);
7750
7751 if (!vp_ap)
7752 continue;
7753
7754 vp_ap->current_nested_vmcs = 0;
7755 vp_ap->enlighten_vmentry = 0;
7756 }
7757
7758 static_branch_disable(&enable_evmcs);
7759 }
7760#endif
7761 vmx_cleanup_l1d_flush();
7762}
7763module_exit(vmx_exit);
7764
6aa8b732
AK		 7765static int __init vmx_init(void)
7766{
773e8a04
VK		 7767 int r;
7768
7769#if IS_ENABLED(CONFIG_HYPERV)
7770 /*
7771 * Enlightened VMCS usage should be recommended and the host needs
7772 * to support eVMCS v1 or above. We can also disable eVMCS support
7773 * with module parameter.
7774 */
7775 if (enlightened_vmcs &&
7776 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7777 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7778 KVM_EVMCS_VERSION) {
7779 int cpu;
7780
7781 /* Check that we have assist pages on all online CPUs */
7782 for_each_online_cpu(cpu) {
7783 if (!hv_get_vp_assist_page(cpu)) {
7784 enlightened_vmcs = false;
7785 break;
7786 }
7787 }
7788
7789 if (enlightened_vmcs) {
7790 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7791 static_branch_enable(&enable_evmcs);
7792 }
7793 } else {
7794 enlightened_vmcs = false;
7795 }
7796#endif
7797
7798 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 7799 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7800 if (r)
34a1cd60 7801 return r;
25c5f225 7802
a7b9020b 7803 /*
7db92e16
TG		 7804 * Must be called after kvm_init() so enable_ept is properly set
7805 * up. Hand the parameter mitigation value in which was stored in
7806 * the pre module init parser. If no parameter was given, it will
7807 * contain 'auto' which will be turned into the default 'cond'
7808 * mitigation mode.
7809 */
7810 if (boot_cpu_has(X86_BUG_L1TF)) {
7811 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7812 if (r) {
7813 vmx_exit();
7814 return r;
7815 }
a47dd5f0 7816 }
25c5f225 7817
2965faa5 7818#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 7819 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7820 crash_vmclear_local_loaded_vmcss);
7821#endif
21ebf53b 7822 vmx_check_vmcs12_offsets();
8f536b76 7823
fdef3ad1 7824 return 0;
6aa8b732 7825}
a7b9020b 7826module_init(vmx_init);
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