]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/x86/kvm/vmx/vmx.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: nVMX: Copy PDPTRs to/from vmcs12 only when necessary
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / vmx / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
199b118a
SC		 19#include <linux/frame.h>
20#include <linux/highmem.h>
21#include <linux/hrtimer.h>
22#include <linux/kernel.h>
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
c7addb90 25#include <linux/moduleparam.h>
e9bda3b3 26#include <linux/mod_devicetable.h>
199b118a 27#include <linux/mm.h>
199b118a 28#include <linux/sched.h>
b284909a 29#include <linux/sched/smt.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
199b118a 32#include <linux/trace_events.h>
e495606d 33
199b118a 34#include <asm/apic.h>
fd8ca6da 35#include <asm/asm.h>
28b835d6 36#include <asm/cpu.h>
199b118a 37#include <asm/debugreg.h>
3b3be0d1 38#include <asm/desc.h>
952f07ec 39#include <asm/fpu/internal.h>
199b118a 40#include <asm/io.h>
efc64404 41#include <asm/irq_remapping.h>
199b118a
SC		 42#include <asm/kexec.h>
43#include <asm/perf_event.h>
44#include <asm/mce.h>
d6e41f11 45#include <asm/mmu_context.h>
773e8a04 46#include <asm/mshyperv.h>
199b118a
SC		 47#include <asm/spec-ctrl.h>
48#include <asm/virtext.h>
49#include <asm/vmx.h>
6aa8b732 50
3077c191 51#include "capabilities.h"
199b118a 52#include "cpuid.h"
4cebd747 53#include "evmcs.h"
199b118a
SC		 54#include "irq.h"
55#include "kvm_cache_regs.h"
56#include "lapic.h"
57#include "mmu.h"
55d2375e 58#include "nested.h"
89b0c9f5 59#include "ops.h"
25462f7f 60#include "pmu.h"
199b118a 61#include "trace.h"
cb1d474b 62#include "vmcs.h"
609363cf 63#include "vmcs12.h"
89b0c9f5 64#include "vmx.h"
199b118a 65#include "x86.h"
229456fc 66
6aa8b732
AK		 67MODULE_AUTHOR("Qumranet");
68MODULE_LICENSE("GPL");
69
e9bda3b3
JT		 70static const struct x86_cpu_id vmx_cpu_id[] = {
71 X86_FEATURE_MATCH(X86_FEATURE_VMX),
72 {}
73};
74MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
75
2c4fd91d 76bool __read_mostly enable_vpid = 1;
736caefe 77module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 78
d02fcf50
PB		 79static bool __read_mostly enable_vnmi = 1;
80module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
81
2c4fd91d 82bool __read_mostly flexpriority_enabled = 1;
736caefe 83module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 84
2c4fd91d 85bool __read_mostly enable_ept = 1;
736caefe 86module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 87
2c4fd91d 88bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 89module_param_named(unrestricted_guest,
90 enable_unrestricted_guest, bool, S_IRUGO);
91
2c4fd91d 92bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 93module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
94
a27685c3 95static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 96module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 97
476bc001 98static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 99module_param(fasteoi, bool, S_IRUGO);
100
5a71785d 101static bool __read_mostly enable_apicv = 1;
01e439be 102module_param(enable_apicv, bool, S_IRUGO);
83d4c286 103
801d3424
NHE		 104/*
105 * If nested=1, nested virtualization is supported, i.e., guests may use
106 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
107 * use VMX instructions.
108 */
1e58e5e5 109static bool __read_mostly nested = 1;
801d3424
NHE		 110module_param(nested, bool, S_IRUGO);
111
20300099
WL		 112static u64 __read_mostly host_xss;
113
2c4fd91d 114bool __read_mostly enable_pml = 1;
843e4330
KH		 115module_param_named(pml, enable_pml, bool, S_IRUGO);
116
6f2f8453
PB		 117static bool __read_mostly dump_invalid_vmcs = 0;
118module_param(dump_invalid_vmcs, bool, 0644);
119
904e14fb
PB		 120#define MSR_BITMAP_MODE_X2APIC 1
121#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 122
64903d61
HZ		 123#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
124
64672c95
YJ		 125/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
126static int __read_mostly cpu_preemption_timer_multi;
127static bool __read_mostly enable_preemption_timer = 1;
128#ifdef CONFIG_X86_64
129module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
130#endif
131
3de6347b 132#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 133#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
134#define KVM_VM_CR0_ALWAYS_ON \
135 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
136 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 137#define KVM_CR4_GUEST_OWNED_BITS \
138 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 139 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 140
5dc1f044 141#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 142#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
143#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
144
78ac8b47
AK		 145#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
146
bf8c55d8
CP		 147#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
148 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
149 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
150 RTIT_STATUS_BYTECNT))
151
152#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
153 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
154
4b8d54f9
ZE		 155/*
156 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
157 * ple_gap: upper bound on the amount of time between two successive
158 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 159 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 160 * ple_window: upper bound on the amount of time a guest is allowed to execute
161 * in a PAUSE loop. Tests indicate that most spinlocks are held for
162 * less than 2^12 cycles
163 * Time is measured based on a counter that runs at the same rate as the TSC,
164 * refer SDM volume 3b section 21.6.13 & 22.1.3.
165 */
c8e88717 166static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 167module_param(ple_gap, uint, 0444);
b4a2d31d 168
7fbc85a5
BM		 169static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
170module_param(ple_window, uint, 0444);
4b8d54f9 171
b4a2d31d 172/* Default doubles per-vcpu window every exit. */
c8e88717 173static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 174module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 175
176/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 177static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 178module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 179
180/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 181static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
182module_param(ple_window_max, uint, 0444);
b4a2d31d 183
f99e3daf
CP		 184/* Default is SYSTEM mode, 1 for host-guest mode */
185int __read_mostly pt_mode = PT_MODE_SYSTEM;
186module_param(pt_mode, int, S_IRUGO);
187
a399477e 188static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 189static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 190static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 191
7db92e16
TG		 192/* Storage for pre module init parameter parsing */
193static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 194
195static const struct {
196 const char *option;
0027ff2a 197 bool for_parse;
a399477e 198} vmentry_l1d_param[] = {
0027ff2a
PB		 199 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
200 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
201 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
202 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
203 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
204 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 205};
206
7db92e16
TG		 207#define L1D_CACHE_ORDER 4
208static void *vmx_l1d_flush_pages;
209
210static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 211{
7db92e16 212 struct page *page;
288d152c 213 unsigned int i;
a399477e 214
7db92e16
TG		 215 if (!enable_ept) {
216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
217 return 0;
a399477e
KRW		 218 }
219
d806afa4
YW		 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
221 u64 msr;
222
223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
226 return 0;
227 }
228 }
8e0b2b91 229
d90a7a0e
JK		 230 /* If set to auto use the default l1tf mitigation method */
231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
232 switch (l1tf_mitigation) {
233 case L1TF_MITIGATION_OFF:
234 l1tf = VMENTER_L1D_FLUSH_NEVER;
235 break;
236 case L1TF_MITIGATION_FLUSH_NOWARN:
237 case L1TF_MITIGATION_FLUSH:
238 case L1TF_MITIGATION_FLUSH_NOSMT:
239 l1tf = VMENTER_L1D_FLUSH_COND;
240 break;
241 case L1TF_MITIGATION_FULL:
242 case L1TF_MITIGATION_FULL_FORCE:
243 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
244 break;
245 }
246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 }
249
7db92e16
TG		 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 252 /*
253 * This allocation for vmx_l1d_flush_pages is not tied to a VM
254 * lifetime and so should not be charged to a memcg.
255 */
7db92e16
TG		 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
257 if (!page)
258 return -ENOMEM;
259 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 260
261 /*
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
265 */
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
268 PAGE_SIZE);
269 }
7db92e16
TG		 270 }
271
272 l1tf_vmx_mitigation = l1tf;
273
895ae47f
TG		 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
276 else
277 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 278
427362a1
NS		 279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 281 else
427362a1 282 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 283 return 0;
284}
285
286static int vmentry_l1d_flush_parse(const char *s)
287{
288 unsigned int i;
289
290 if (s) {
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
294 return i;
7db92e16
TG		 295 }
296 }
a399477e
KRW		 297 return -EINVAL;
298}
299
7db92e16
TG		 300static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301{
dd4bfa73 302 int l1tf, ret;
7db92e16 303
7db92e16
TG		 304 l1tf = vmentry_l1d_flush_parse(s);
305 if (l1tf < 0)
306 return l1tf;
307
0027ff2a
PB		 308 if (!boot_cpu_has(X86_BUG_L1TF))
309 return 0;
310
7db92e16
TG		 311 /*
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
315 * established.
316 */
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
319 return 0;
320 }
321
dd4bfa73
TG		 322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
325 return ret;
7db92e16
TG		 326}
327
a399477e
KRW		 328static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
329{
0027ff2a
PB		 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
332
7db92e16 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 334}
335
336static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
339};
895ae47f 340module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 341
d99e4152
GN		 342static bool guest_state_valid(struct kvm_vcpu *vcpu);
343static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 344static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 345 u32 msr, int type);
75880a01 346
453eafbe
SC		 347void vmx_vmexit(void);
348
6aa8b732 349static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 350DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 351/*
352 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
353 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
354 */
355static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 356
bf9f6ac8
FW		 357/*
358 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
359 * can find which vCPU should be waken up.
360 */
361static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
362static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
363
2384d2b3
SY		 364static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
365static DEFINE_SPINLOCK(vmx_vpid_lock);
366
3077c191
SC		 367struct vmcs_config vmcs_config;
368struct vmx_capability vmx_capability;
d56f546d 369
6aa8b732
AK		 370#define VMX_SEGMENT_FIELD(seg) \
371 [VCPU_SREG_##seg] = { \
372 .selector = GUEST_##seg##_SELECTOR, \
373 .base = GUEST_##seg##_BASE, \
374 .limit = GUEST_##seg##_LIMIT, \
375 .ar_bytes = GUEST_##seg##_AR_BYTES, \
376 }
377
772e0318 378static const struct kvm_vmx_segment_field {
6aa8b732
AK		 379 unsigned selector;
380 unsigned base;
381 unsigned limit;
382 unsigned ar_bytes;
383} kvm_vmx_segment_fields[] = {
384 VMX_SEGMENT_FIELD(CS),
385 VMX_SEGMENT_FIELD(DS),
386 VMX_SEGMENT_FIELD(ES),
387 VMX_SEGMENT_FIELD(FS),
388 VMX_SEGMENT_FIELD(GS),
389 VMX_SEGMENT_FIELD(SS),
390 VMX_SEGMENT_FIELD(TR),
391 VMX_SEGMENT_FIELD(LDTR),
392};
393
cf3646eb 394u64 host_efer;
2342080c 395static unsigned long host_idt_base;
26bb0981 396
4d56c8a7 397/*
898a811f
JM		 398 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
399 * will emulate SYSCALL in legacy mode if the vendor string in guest
400 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
401 * support this emulation, IA32_STAR must always be included in
402 * vmx_msr_index[], even in i386 builds.
4d56c8a7 403 */
cf3646eb 404const u32 vmx_msr_index[] = {
05b3e0c2 405#ifdef CONFIG_X86_64
44ea2b17 406 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 407#endif
8c06585d 408 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 409};
6aa8b732 410
773e8a04
VK		 411#if IS_ENABLED(CONFIG_HYPERV)
412static bool __read_mostly enlightened_vmcs = true;
413module_param(enlightened_vmcs, bool, 0444);
414
877ad952
TL		 415/* check_ept_pointer() should be under protection of ept_pointer_lock. */
416static void check_ept_pointer_match(struct kvm *kvm)
417{
418 struct kvm_vcpu *vcpu;
419 u64 tmp_eptp = INVALID_PAGE;
420 int i;
421
422 kvm_for_each_vcpu(i, vcpu, kvm) {
423 if (!VALID_PAGE(tmp_eptp)) {
424 tmp_eptp = to_vmx(vcpu)->ept_pointer;
425 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
426 to_kvm_vmx(kvm)->ept_pointers_match
427 = EPT_POINTERS_MISMATCH;
428 return;
429 }
430 }
431
432 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
433}
434
8997f657 435static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 436 void *data)
437{
438 struct kvm_tlb_range *range = data;
439
440 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
441 range->pages);
442}
443
444static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
445 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
446{
447 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
448
449 /*
450 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
451 * of the base of EPT PML4 table, strip off EPT configuration
452 * information.
453 */
454 if (range)
455 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
456 kvm_fill_hv_flush_list_func, (void *)range);
457 else
458 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
459}
460
461static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
462 struct kvm_tlb_range *range)
877ad952 463{
a5c214da 464 struct kvm_vcpu *vcpu;
b7c1c226 465 int ret = 0, i;
877ad952
TL		 466
467 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
468
469 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
470 check_ept_pointer_match(kvm);
471
472 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 473 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 474 /* If ept_pointer is invalid pointer, bypass flush request. */
475 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
476 ret |= __hv_remote_flush_tlb_with_range(
477 kvm, vcpu, range);
53963a70 478 }
a5c214da 479 } else {
1f3a3e46
LT		 480 ret = __hv_remote_flush_tlb_with_range(kvm,
481 kvm_get_vcpu(kvm, 0), range);
877ad952 482 }
877ad952 483
877ad952
TL		 484 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
485 return ret;
486}
1f3a3e46
LT		 487static int hv_remote_flush_tlb(struct kvm *kvm)
488{
489 return hv_remote_flush_tlb_with_range(kvm, NULL);
490}
491
773e8a04
VK		 492#endif /* IS_ENABLED(CONFIG_HYPERV) */
493
64672c95
YJ		 494/*
495 * Comment's format: document - errata name - stepping - processor name.
496 * Refer from
497 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
498 */
499static u32 vmx_preemption_cpu_tfms[] = {
500/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
5010x000206E6,
502/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
503/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
504/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5050x00020652,
506/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5070x00020655,
508/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
509/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
510/*
511 * 320767.pdf - AAP86 - B1 -
512 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
513 */
5140x000106E5,
515/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5160x000106A0,
517/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5180x000106A1,
519/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5200x000106A4,
521 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
522 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
523 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5240x000106A5,
3d82c565
WH		 525 /* Xeon E3-1220 V2 */
5260x000306A8,
64672c95
YJ		 527};
528
529static inline bool cpu_has_broken_vmx_preemption_timer(void)
530{
531 u32 eax = cpuid_eax(0x00000001), i;
532
533 /* Clear the reserved bits */
534 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 535 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 536 if (eax == vmx_preemption_cpu_tfms[i])
537 return true;
538
539 return false;
540}
541
35754c98 542static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 543{
35754c98 544 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 545}
546
04547156
SY		 547static inline bool report_flexpriority(void)
548{
549 return flexpriority_enabled;
550}
551
97b7ead3 552static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 553{
554 int i;
555
a2fa3e9f 556 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 557 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 558 return i;
559 return -1;
560}
561
97b7ead3 562struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 563{
564 int i;
565
8b9cf98c 566 i = __find_msr_index(vmx, msr);
a75beee6 567 if (i >= 0)
a2fa3e9f 568 return &vmx->guest_msrs[i];
8b6d44c7 569 return NULL;
7725f0ba
AK		 570}
571
7c97fcb3
SC		 572void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
573{
574 vmcs_clear(loaded_vmcs->vmcs);
575 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
576 vmcs_clear(loaded_vmcs->shadow_vmcs);
577 loaded_vmcs->cpu = -1;
578 loaded_vmcs->launched = 0;
579}
580
2965faa5 581#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 582/*
583 * This bitmap is used to indicate whether the vmclear
584 * operation is enabled on all cpus. All disabled by
585 * default.
586 */
587static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
588
589static inline void crash_enable_local_vmclear(int cpu)
590{
591 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
592}
593
594static inline void crash_disable_local_vmclear(int cpu)
595{
596 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
597}
598
599static inline int crash_local_vmclear_enabled(int cpu)
600{
601 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
602}
603
604static void crash_vmclear_local_loaded_vmcss(void)
605{
606 int cpu = raw_smp_processor_id();
607 struct loaded_vmcs *v;
608
609 if (!crash_local_vmclear_enabled(cpu))
610 return;
611
612 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
613 loaded_vmcss_on_cpu_link)
614 vmcs_clear(v->vmcs);
615}
616#else
617static inline void crash_enable_local_vmclear(int cpu) { }
618static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 619#endif /* CONFIG_KEXEC_CORE */
8f536b76 620
d462b819 621static void __loaded_vmcs_clear(void *arg)
6aa8b732 622{
d462b819 623 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 624 int cpu = raw_smp_processor_id();
6aa8b732 625
d462b819
NHE		 626 if (loaded_vmcs->cpu != cpu)
627 return; /* vcpu migration can race with cpu offline */
628 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 629 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 630 crash_disable_local_vmclear(cpu);
d462b819 631 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 632
633 /*
634 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
635 * is before setting loaded_vmcs->vcpu to -1 which is done in
636 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
637 * then adds the vmcs into percpu list before it is deleted.
638 */
639 smp_wmb();
640
d462b819 641 loaded_vmcs_init(loaded_vmcs);
8f536b76 642 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 643}
644
89b0c9f5 645void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 646{
e6c7d321
XG		 647 int cpu = loaded_vmcs->cpu;
648
649 if (cpu != -1)
650 smp_call_function_single(cpu,
651 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 652}
653
2fb92db1
AK		 654static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
655 unsigned field)
656{
657 bool ret;
658 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
659
660 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
661 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
662 vmx->segment_cache.bitmask = 0;
663 }
664 ret = vmx->segment_cache.bitmask & mask;
665 vmx->segment_cache.bitmask |= mask;
666 return ret;
667}
668
669static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
670{
671 u16 *p = &vmx->segment_cache.seg[seg].selector;
672
673 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
674 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
675 return *p;
676}
677
678static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
679{
680 ulong *p = &vmx->segment_cache.seg[seg].base;
681
682 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
683 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
684 return *p;
685}
686
687static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
688{
689 u32 *p = &vmx->segment_cache.seg[seg].limit;
690
691 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
692 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
693 return *p;
694}
695
696static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
697{
698 u32 *p = &vmx->segment_cache.seg[seg].ar;
699
700 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
701 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
702 return *p;
703}
704
97b7ead3 705void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 706{
707 u32 eb;
708
fd7373cc 709 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 710 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 711 /*
712 * Guest access to VMware backdoor ports could legitimately
713 * trigger #GP because of TSS I/O permission bitmap.
714 * We intercept those #GP and allow access to them anyway
715 * as VMware does.
716 */
717 if (enable_vmware_backdoor)
718 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 719 if ((vcpu->guest_debug &
720 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
721 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
722 eb |= 1u << BP_VECTOR;
7ffd92c5 723 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 724 eb = ~0;
089d034e 725 if (enable_ept)
1439442c 726 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 727
728 /* When we are running a nested L2 guest and L1 specified for it a
729 * certain exception bitmap, we must trap the same exceptions and pass
730 * them to L1. When running L2, we will only handle the exceptions
731 * specified above if L1 did not want them.
732 */
733 if (is_guest_mode(vcpu))
734 eb |= get_vmcs12(vcpu)->exception_bitmap;
735
abd3f2d6
AK		 736 vmcs_write32(EXCEPTION_BITMAP, eb);
737}
738
d28b387f
KA		 739/*
740 * Check if MSR is intercepted for currently loaded MSR bitmap.
741 */
742static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
743{
744 unsigned long *msr_bitmap;
745 int f = sizeof(unsigned long);
746
747 if (!cpu_has_vmx_msr_bitmap())
748 return true;
749
750 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
751
752 if (msr <= 0x1fff) {
753 return !!test_bit(msr, msr_bitmap + 0x800 / f);
754 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
755 msr &= 0x1fff;
756 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
757 }
758
759 return true;
760}
761
2961e876
GN		 762static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
763 unsigned long entry, unsigned long exit)
8bf00a52 764{
2961e876
GN		 765 vm_entry_controls_clearbit(vmx, entry);
766 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 767}
768
ca83b4a7
KRW		 769static int find_msr(struct vmx_msrs *m, unsigned int msr)
770{
771 unsigned int i;
772
773 for (i = 0; i < m->nr; ++i) {
774 if (m->val[i].index == msr)
775 return i;
776 }
777 return -ENOENT;
778}
779
61d2ef2c
AK		 780static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
781{
ca83b4a7 782 int i;
61d2ef2c
AK		 783 struct msr_autoload *m = &vmx->msr_autoload;
784
8bf00a52
GN		 785 switch (msr) {
786 case MSR_EFER:
c73da3fc 787 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 788 clear_atomic_switch_msr_special(vmx,
789 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 790 VM_EXIT_LOAD_IA32_EFER);
791 return;
792 }
793 break;
794 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 795 if (cpu_has_load_perf_global_ctrl()) {
2961e876 796 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 797 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
798 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
799 return;
800 }
801 break;
110312c8 802 }
ca83b4a7
KRW		 803 i = find_msr(&m->guest, msr);
804 if (i < 0)
31907093 805 goto skip_guest;
33966dd6 806 --m->guest.nr;
33966dd6 807 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 808 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 809
31907093
KRW		 810skip_guest:
811 i = find_msr(&m->host, msr);
812 if (i < 0)
61d2ef2c 813 return;
31907093
KRW		 814
815 --m->host.nr;
816 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 817 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 818}
819
2961e876
GN		 820static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
821 unsigned long entry, unsigned long exit,
822 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
823 u64 guest_val, u64 host_val)
8bf00a52
GN		 824{
825 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 826 if (host_val_vmcs != HOST_IA32_EFER)
827 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 828 vm_entry_controls_setbit(vmx, entry);
829 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 830}
831
61d2ef2c 832static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 833 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 834{
989e3992 835 int i, j = 0;
61d2ef2c
AK		 836 struct msr_autoload *m = &vmx->msr_autoload;
837
8bf00a52
GN		 838 switch (msr) {
839 case MSR_EFER:
c73da3fc 840 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 841 add_atomic_switch_msr_special(vmx,
842 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 843 VM_EXIT_LOAD_IA32_EFER,
844 GUEST_IA32_EFER,
845 HOST_IA32_EFER,
846 guest_val, host_val);
847 return;
848 }
849 break;
850 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 851 if (cpu_has_load_perf_global_ctrl()) {
2961e876 852 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 853 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
854 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
855 GUEST_IA32_PERF_GLOBAL_CTRL,
856 HOST_IA32_PERF_GLOBAL_CTRL,
857 guest_val, host_val);
858 return;
859 }
860 break;
7099e2e1
RK		 861 case MSR_IA32_PEBS_ENABLE:
862 /* PEBS needs a quiescent period after being disabled (to write
863 * a record). Disabling PEBS through VMX MSR swapping doesn't
864 * provide that period, so a CPU could write host's record into
865 * guest's memory.
866 */
867 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 868 }
869
ca83b4a7 870 i = find_msr(&m->guest, msr);
989e3992
KRW		 871 if (!entry_only)
872 j = find_msr(&m->host, msr);
61d2ef2c 873
98ae70cc
XL		 874 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
875 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
60266204 876 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 877 "Can't add msr %x\n", msr);
878 return;
61d2ef2c 879 }
31907093 880 if (i < 0) {
ca83b4a7 881 i = m->guest.nr++;
33966dd6 882 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 883 }
989e3992
KRW		 884 m->guest.val[i].index = msr;
885 m->guest.val[i].value = guest_val;
886
887 if (entry_only)
888 return;
61d2ef2c 889
31907093
KRW		 890 if (j < 0) {
891 j = m->host.nr++;
33966dd6 892 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 893 }
31907093
KRW		 894 m->host.val[j].index = msr;
895 m->host.val[j].value = host_val;
61d2ef2c
AK		 896}
897
92c0d900 898static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 899{
844a5fe2
PB		 900 u64 guest_efer = vmx->vcpu.arch.efer;
901 u64 ignore_bits = 0;
902
903 if (!enable_ept) {
904 /*
905 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
906 * host CPUID is more efficient than testing guest CPUID
907 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
908 */
909 if (boot_cpu_has(X86_FEATURE_SMEP))
910 guest_efer |= EFER_NX;
911 else if (!(guest_efer & EFER_NX))
912 ignore_bits |= EFER_NX;
913 }
3a34a881 914
51c6cf66 915 /*
844a5fe2 916 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 917 */
844a5fe2 918 ignore_bits |= EFER_SCE;
51c6cf66
AK		 919#ifdef CONFIG_X86_64
920 ignore_bits |= EFER_LMA | EFER_LME;
921 /* SCE is meaningful only in long mode on Intel */
922 if (guest_efer & EFER_LMA)
923 ignore_bits &= ~(u64)EFER_SCE;
924#endif
84ad33ef 925
f6577a5f
AL		 926 /*
927 * On EPT, we can't emulate NX, so we must switch EFER atomically.
928 * On CPUs that support "load IA32_EFER", always switch EFER
929 * atomically, since it's faster than switching it manually.
930 */
c73da3fc 931 if (cpu_has_load_ia32_efer() ||
f6577a5f 932 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 933 if (!(guest_efer & EFER_LMA))
934 guest_efer &= ~EFER_LME;
54b98bff
AL		 935 if (guest_efer != host_efer)
936 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 937 guest_efer, host_efer, false);
02343cf2
SC		 938 else
939 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 940 return false;
844a5fe2 941 } else {
02343cf2
SC		 942 clear_atomic_switch_msr(vmx, MSR_EFER);
943
844a5fe2
PB		 944 guest_efer &= ~ignore_bits;
945 guest_efer |= host_efer & ignore_bits;
946
947 vmx->guest_msrs[efer_offset].data = guest_efer;
948 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 949
844a5fe2
PB		 950 return true;
951 }
51c6cf66
AK		 952}
953
e28baead
AL		 954#ifdef CONFIG_X86_32
955/*
956 * On 32-bit kernels, VM exits still load the FS and GS bases from the
957 * VMCS rather than the segment table. KVM uses this helper to figure
958 * out the current bases to poke them into the VMCS before entry.
959 */
2d49ec72
GN		 960static unsigned long segment_base(u16 selector)
961{
8c2e41f7 962 struct desc_struct *table;
2d49ec72
GN		 963 unsigned long v;
964
8c2e41f7 965 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 966 return 0;
967
45fc8757 968 table = get_current_gdt_ro();
2d49ec72 969
8c2e41f7 970 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 971 u16 ldt_selector = kvm_read_ldt();
972
8c2e41f7 973 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 974 return 0;
975
8c2e41f7 976 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 977 }
8c2e41f7 978 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 979 return v;
980}
e28baead 981#endif
2d49ec72 982
2ef444f1
CP		 983static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
984{
985 u32 i;
986
987 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
988 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
989 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
990 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
991 for (i = 0; i < addr_range; i++) {
992 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
993 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
994 }
995}
996
997static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
998{
999 u32 i;
1000
1001 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1002 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1003 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1004 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1005 for (i = 0; i < addr_range; i++) {
1006 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1007 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1008 }
1009}
1010
1011static void pt_guest_enter(struct vcpu_vmx *vmx)
1012{
1013 if (pt_mode == PT_MODE_SYSTEM)
1014 return;
1015
2ef444f1 1016 /*
b08c2896
CP		 1017 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1018 * Save host state before VM entry.
2ef444f1 1019 */
b08c2896 1020 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1021 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1022 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1023 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1024 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1025 }
1026}
1027
1028static void pt_guest_exit(struct vcpu_vmx *vmx)
1029{
1030 if (pt_mode == PT_MODE_SYSTEM)
1031 return;
1032
1033 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1034 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1035 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1036 }
1037
1038 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1039 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1040}
1041
13b964a2
SC		 1042void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1043 unsigned long fs_base, unsigned long gs_base)
1044{
1045 if (unlikely(fs_sel != host->fs_sel)) {
1046 if (!(fs_sel & 7))
1047 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1048 else
1049 vmcs_write16(HOST_FS_SELECTOR, 0);
1050 host->fs_sel = fs_sel;
1051 }
1052 if (unlikely(gs_sel != host->gs_sel)) {
1053 if (!(gs_sel & 7))
1054 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1055 else
1056 vmcs_write16(HOST_GS_SELECTOR, 0);
1057 host->gs_sel = gs_sel;
1058 }
1059 if (unlikely(fs_base != host->fs_base)) {
1060 vmcs_writel(HOST_FS_BASE, fs_base);
1061 host->fs_base = fs_base;
1062 }
1063 if (unlikely(gs_base != host->gs_base)) {
1064 vmcs_writel(HOST_GS_BASE, gs_base);
1065 host->gs_base = gs_base;
1066 }
1067}
1068
97b7ead3 1069void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1070{
04d2cc77 1071 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1072 struct vmcs_host_state *host_state;
51e8a8cc 1073#ifdef CONFIG_X86_64
35060ed6 1074 int cpu = raw_smp_processor_id();
51e8a8cc 1075#endif
e368b875
SC		 1076 unsigned long fs_base, gs_base;
1077 u16 fs_sel, gs_sel;
26bb0981 1078 int i;
04d2cc77 1079
d264ee0c
SC		 1080 vmx->req_immediate_exit = false;
1081
f48b4711
LA		 1082 /*
1083 * Note that guest MSRs to be saved/restored can also be changed
1084 * when guest state is loaded. This happens when guest transitions
1085 * to/from long-mode by setting MSR_EFER.LMA.
1086 */
b464f57e
PB		 1087 if (!vmx->guest_msrs_ready) {
1088 vmx->guest_msrs_ready = true;
f48b4711
LA		 1089 for (i = 0; i < vmx->save_nmsrs; ++i)
1090 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1091 vmx->guest_msrs[i].data,
1092 vmx->guest_msrs[i].mask);
1093
1094 }
b464f57e 1095 if (vmx->guest_state_loaded)
33ed6329
AK		 1096 return;
1097
b464f57e 1098 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1099
33ed6329
AK		 1100 /*
1101 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1102 * allow segment selectors with cpl > 0 or ti == 1.
1103 */
d7ee039e 1104 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1105
1106#ifdef CONFIG_X86_64
d7ee039e
SC		 1107 savesegment(ds, host_state->ds_sel);
1108 savesegment(es, host_state->es_sel);
e368b875
SC		 1109
1110 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1111 if (likely(is_64bit_mm(current->mm))) {
1112 save_fsgs_for_kvm();
e368b875
SC		 1113 fs_sel = current->thread.fsindex;
1114 gs_sel = current->thread.gsindex;
b062b794 1115 fs_base = current->thread.fsbase;
e368b875 1116 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1117 } else {
e368b875
SC		 1118 savesegment(fs, fs_sel);
1119 savesegment(gs, gs_sel);
b062b794 1120 fs_base = read_msr(MSR_FS_BASE);
e368b875 1121 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1122 }
b2da15ac 1123
4679b61f 1124 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1125#else
e368b875
SC		 1126 savesegment(fs, fs_sel);
1127 savesegment(gs, gs_sel);
1128 fs_base = segment_base(fs_sel);
1129 gs_base = segment_base(gs_sel);
707c0874 1130#endif
e368b875 1131
13b964a2 1132 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
b464f57e 1133 vmx->guest_state_loaded = true;
33ed6329
AK		 1134}
1135
6d6095bd 1136static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1137{
d7ee039e
SC		 1138 struct vmcs_host_state *host_state;
1139
b464f57e 1140 if (!vmx->guest_state_loaded)
33ed6329
AK		 1141 return;
1142
b464f57e 1143 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1144
e1beb1d3 1145 ++vmx->vcpu.stat.host_state_reload;
bd9966de 1146
c8770e7b 1147#ifdef CONFIG_X86_64
4679b61f 1148 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1149#endif
d7ee039e
SC		 1150 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1151 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1152#ifdef CONFIG_X86_64
d7ee039e 1153 load_gs_index(host_state->gs_sel);
9581d442 1154#else
d7ee039e 1155 loadsegment(gs, host_state->gs_sel);
33ed6329 1156#endif
33ed6329 1157 }
d7ee039e
SC		 1158 if (host_state->fs_sel & 7)
1159 loadsegment(fs, host_state->fs_sel);
b2da15ac 1160#ifdef CONFIG_X86_64
d7ee039e
SC		 1161 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1162 loadsegment(ds, host_state->ds_sel);
1163 loadsegment(es, host_state->es_sel);
b2da15ac 1164 }
b2da15ac 1165#endif
b7ffc44d 1166 invalidate_tss_limit();
44ea2b17 1167#ifdef CONFIG_X86_64
c8770e7b 1168 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1169#endif
45fc8757 1170 load_fixmap_gdt(raw_smp_processor_id());
b464f57e
PB		 1171 vmx->guest_state_loaded = false;
1172 vmx->guest_msrs_ready = false;
33ed6329
AK		 1173}
1174
678e315e
SC		 1175#ifdef CONFIG_X86_64
1176static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1177{
4679b61f 1178 preempt_disable();
b464f57e 1179 if (vmx->guest_state_loaded)
4679b61f
PB		 1180 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1181 preempt_enable();
678e315e 1182 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1183}
1184
678e315e
SC		 1185static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1186{
4679b61f 1187 preempt_disable();
b464f57e 1188 if (vmx->guest_state_loaded)
4679b61f
PB		 1189 wrmsrl(MSR_KERNEL_GS_BASE, data);
1190 preempt_enable();
678e315e
SC		 1191 vmx->msr_guest_kernel_gs_base = data;
1192}
1193#endif
1194
28b835d6
FW		 1195static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1196{
1197 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1198 struct pi_desc old, new;
1199 unsigned int dest;
1200
31afb2ea
PB		 1201 /*
1202 * In case of hot-plug or hot-unplug, we may have to undo
1203 * vmx_vcpu_pi_put even if there is no assigned device. And we
1204 * always keep PI.NDST up to date for simplicity: it makes the
1205 * code easier, and CPU migration is not a fast path.
1206 */
1207 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1208 return;
1209
31afb2ea 1210 /* The full case. */
28b835d6
FW		 1211 do {
1212 old.control = new.control = pi_desc->control;
1213
31afb2ea 1214 dest = cpu_physical_id(cpu);
28b835d6 1215
31afb2ea
PB		 1216 if (x2apic_enabled())
1217 new.ndst = dest;
1218 else
1219 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1220
28b835d6 1221 new.sn = 0;
c0a1666b
PB		 1222 } while (cmpxchg64(&pi_desc->control, old.control,
1223 new.control) != old.control);
c112b5f5
LK		 1224
1225 /*
1226 * Clear SN before reading the bitmap. The VT-d firmware
1227 * writes the bitmap and reads SN atomically (5.2.3 in the
1228 * spec), so it doesn't really have a memory barrier that
1229 * pairs with this, but we cannot do that and we need one.
1230 */
1231 smp_mb__after_atomic();
1232
1233 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1234 pi_set_on(pi_desc);
28b835d6 1235}
1be0e61c 1236
8ef863e6 1237void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1238{
a2fa3e9f 1239 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1240 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1241
b80c76ec 1242 if (!already_loaded) {
fe0e80be 1243 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1244 local_irq_disable();
8f536b76 1245 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1246
1247 /*
1248 * Read loaded_vmcs->cpu should be before fetching
1249 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1250 * See the comments in __loaded_vmcs_clear().
1251 */
1252 smp_rmb();
1253
d462b819
NHE		 1254 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1255 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1256 crash_enable_local_vmclear(cpu);
92fe13be 1257 local_irq_enable();
b80c76ec
JM		 1258 }
1259
1260 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1261 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1262 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1263 indirect_branch_prediction_barrier();
b80c76ec
JM		 1264 }
1265
1266 if (!already_loaded) {
59c58ceb 1267 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1268 unsigned long sysenter_esp;
1269
1270 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1271
6aa8b732
AK		 1272 /*
1273 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1274 * processors. See 22.2.4.
6aa8b732 1275 */
e0c23063 1276 vmcs_writel(HOST_TR_BASE,
72f5e08d 1277 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1278 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 1279
b7ffc44d
AL		 1280 /*
1281 * VM exits change the host TR limit to 0x67 after a VM
1282 * exit. This is okay, since 0x67 covers everything except
1283 * the IO bitmap and have have code to handle the IO bitmap
1284 * being lost after a VM exit.
1285 */
1286 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1287
6aa8b732
AK		 1288 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1289 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1290
d462b819 1291 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1292 }
28b835d6 1293
2680d6da
OH		 1294 /* Setup TSC multiplier */
1295 if (kvm_has_tsc_control &&
c95ba92a
PF		 1296 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1297 decache_tsc_multiplier(vmx);
8ef863e6
SC		 1298}
1299
1300/*
1301 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1302 * vcpu mutex is already taken.
1303 */
1304void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1305{
1306 struct vcpu_vmx *vmx = to_vmx(vcpu);
1307
1308 vmx_vcpu_load_vmcs(vcpu, cpu);
2680d6da 1309
28b835d6 1310 vmx_vcpu_pi_load(vcpu, cpu);
8ef863e6 1311
1be0e61c 1312 vmx->host_pkru = read_pkru();
74c55931 1313 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1314}
1315
1316static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1317{
1318 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1319
1320 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1321 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1322 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1323 return;
1324
1325 /* Set SN when the vCPU is preempted */
1326 if (vcpu->preempted)
1327 pi_set_sn(pi_desc);
6aa8b732
AK		 1328}
1329
13b964a2 1330static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1331{
28b835d6
FW		 1332 vmx_vcpu_pi_put(vcpu);
1333
6d6095bd 1334 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1335}
1336
f244deed
WL		 1337static bool emulation_required(struct kvm_vcpu *vcpu)
1338{
1339 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1340}
1341
edcafe3c
AK		 1342static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1343
97b7ead3 1344unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1345{
78ac8b47 1346 unsigned long rflags, save_rflags;
345dcaa8 1347
6de12732
AK		 1348 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1349 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1350 rflags = vmcs_readl(GUEST_RFLAGS);
1351 if (to_vmx(vcpu)->rmode.vm86_active) {
1352 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1353 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1354 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1355 }
1356 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1357 }
6de12732 1358 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1359}
1360
97b7ead3 1361void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1362{
f244deed
WL		 1363 unsigned long old_rflags = vmx_get_rflags(vcpu);
1364
6de12732
AK		 1365 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1366 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1367 if (to_vmx(vcpu)->rmode.vm86_active) {
1368 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1369 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1370 }
6aa8b732 1371 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed
WL		 1372
1373 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1374 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1375}
1376
97b7ead3 1377u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1378{
1379 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1380 int ret = 0;
1381
1382 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1383 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1384 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1385 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1386
37ccdcbe 1387 return ret;
2809f5d2
GC		 1388}
1389
97b7ead3 1390void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1391{
1392 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1393 u32 interruptibility = interruptibility_old;
1394
1395 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1396
48005f64 1397 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1398 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1399 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1400 interruptibility |= GUEST_INTR_STATE_STI;
1401
1402 if ((interruptibility != interruptibility_old))
1403 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1404}
1405
bf8c55d8
CP		 1406static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1407{
1408 struct vcpu_vmx *vmx = to_vmx(vcpu);
1409 unsigned long value;
1410
1411 /*
1412 * Any MSR write that attempts to change bits marked reserved will
1413 * case a #GP fault.
1414 */
1415 if (data & vmx->pt_desc.ctl_bitmask)
1416 return 1;
1417
1418 /*
1419 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1420 * result in a #GP unless the same write also clears TraceEn.
1421 */
1422 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1423 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1424 return 1;
1425
1426 /*
1427 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1428 * and FabricEn would cause #GP, if
1429 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1430 */
1431 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1432 !(data & RTIT_CTL_FABRIC_EN) &&
1433 !intel_pt_validate_cap(vmx->pt_desc.caps,
1434 PT_CAP_single_range_output))
1435 return 1;
1436
1437 /*
1438 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1439 * utilize encodings marked reserved will casue a #GP fault.
1440 */
1441 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1442 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1443 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1444 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1445 return 1;
1446 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1447 PT_CAP_cycle_thresholds);
1448 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1449 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1450 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1451 return 1;
1452 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1453 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1454 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1455 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1456 return 1;
1457
1458 /*
1459 * If ADDRx_CFG is reserved or the encodings is >2 will
1460 * cause a #GP fault.
1461 */
1462 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1463 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1464 return 1;
1465 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1466 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1467 return 1;
1468 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1469 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1470 return 1;
1471 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1472 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1473 return 1;
1474
1475 return 0;
1476}
1477
1478
6aa8b732
AK		 1479static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1480{
1481 unsigned long rip;
6aa8b732 1482
5fdbf976 1483 rip = kvm_rip_read(vcpu);
6aa8b732 1484 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1485 kvm_rip_write(vcpu, rip);
6aa8b732 1486
2809f5d2
GC		 1487 /* skipping an emulated instruction also counts */
1488 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1489}
1490
caa057a2
WL		 1491static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1492{
1493 /*
1494 * Ensure that we clear the HLT state in the VMCS. We don't need to
1495 * explicitly skip the instruction because if the HLT state is set,
1496 * then the instruction is already executing and RIP has already been
1497 * advanced.
1498 */
1499 if (kvm_hlt_in_guest(vcpu->kvm) &&
1500 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1501 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1502}
1503
cfcd20e5 1504static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1505{
77ab6db0 1506 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1507 unsigned nr = vcpu->arch.exception.nr;
1508 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1509 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1510 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1511
da998b46
JM		 1512 kvm_deliver_exception_payload(vcpu);
1513
8ab2d2e2 1514 if (has_error_code) {
77ab6db0 1515 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1516 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1517 }
77ab6db0 1518
7ffd92c5 1519 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1520 int inc_eip = 0;
1521 if (kvm_exception_is_soft(nr))
1522 inc_eip = vcpu->arch.event_exit_inst_len;
1523 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1524 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1525 return;
1526 }
1527
add5ff7a
SC		 1528 WARN_ON_ONCE(vmx->emulation_required);
1529
66fd3f7f
GN		 1530 if (kvm_exception_is_soft(nr)) {
1531 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1532 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1533 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1534 } else
1535 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1536
1537 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1538
1539 vmx_clear_hlt(vcpu);
298101da
AK		 1540}
1541
4e47c7a6
SY		 1542static bool vmx_rdtscp_supported(void)
1543{
1544 return cpu_has_vmx_rdtscp();
1545}
1546
ad756a16
MJ		 1547static bool vmx_invpcid_supported(void)
1548{
eb4b248e 1549 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1550}
1551
a75beee6
ED		 1552/*
1553 * Swap MSR entry in host/guest MSR entry array.
1554 */
8b9cf98c 1555static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1556{
26bb0981 1557 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1558
1559 tmp = vmx->guest_msrs[to];
1560 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1561 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1562}
1563
e38aea3e
AK		 1564/*
1565 * Set up the vmcs to automatically save and restore system
1566 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1567 * mode, as fiddling with msrs is very expensive.
1568 */
8b9cf98c 1569static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1570{
26bb0981 1571 int save_nmsrs, index;
e38aea3e 1572
a75beee6
ED		 1573 save_nmsrs = 0;
1574#ifdef CONFIG_X86_64
84c8c5b8
JM		 1575 /*
1576 * The SYSCALL MSRs are only needed on long mode guests, and only
1577 * when EFER.SCE is set.
1578 */
1579 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1580 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1581 if (index >= 0)
8b9cf98c
RR		 1582 move_msr_up(vmx, index, save_nmsrs++);
1583 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1584 if (index >= 0)
8b9cf98c 1585 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1586 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1587 if (index >= 0)
8b9cf98c 1588 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1589 }
1590#endif
92c0d900
AK		 1591 index = __find_msr_index(vmx, MSR_EFER);
1592 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1593 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1594 index = __find_msr_index(vmx, MSR_TSC_AUX);
1595 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1596 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1597
26bb0981 1598 vmx->save_nmsrs = save_nmsrs;
b464f57e 1599 vmx->guest_msrs_ready = false;
5897297b 1600
8d14695f 1601 if (cpu_has_vmx_msr_bitmap())
904e14fb 1602 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1603}
1604
e79f245d 1605static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1606{
e79f245d 1607 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1608
e79f245d
KA		 1609 if (is_guest_mode(vcpu) &&
1610 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1611 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1612
1613 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1614}
1615
326e7425 1616static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1617{
45c3af97
PB		 1618 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1619 u64 g_tsc_offset = 0;
1620
1621 /*
1622 * We're here if L1 chose not to trap WRMSR to TSC. According
1623 * to the spec, this should set L1's TSC; The offset that L1
1624 * set for L2 remains unchanged, and still needs to be added
1625 * to the newly set TSC to get L2's TSC.
1626 */
1627 if (is_guest_mode(vcpu) &&
1628 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1629 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1630
45c3af97
PB		 1631 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1632 vcpu->arch.tsc_offset - g_tsc_offset,
1633 offset);
1634 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1635 return offset + g_tsc_offset;
6aa8b732
AK		 1636}
1637
801d3424
NHE		 1638/*
1639 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1640 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1641 * all guests if the "nested" module option is off, and can also be disabled
1642 * for a single guest by disabling its VMX cpuid bit.
1643 */
7c97fcb3 1644bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1645{
d6321d49 1646 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1647}
1648
55d2375e
SC		 1649static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1650 uint64_t val)
62cc6b9d 1651{
55d2375e 1652 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1653
55d2375e 1654 return !(val & ~valid_bits);
62cc6b9d
DM		 1655}
1656
55d2375e 1657static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1658{
55d2375e
SC		 1659 switch (msr->index) {
1660 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1661 if (!nested)
1662 return 1;
1663 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1664 default:
1665 return 1;
1666 }
62cc6b9d 1667
62cc6b9d
DM		 1668 return 0;
1669}
1670
55d2375e
SC		 1671/*
1672 * Reads an msr value (of 'msr_index') into 'pdata'.
1673 * Returns 0 on success, non-0 otherwise.
1674 * Assumes vcpu_load() was already called.
1675 */
1676static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1677{
55d2375e
SC		 1678 struct vcpu_vmx *vmx = to_vmx(vcpu);
1679 struct shared_msr_entry *msr;
bf8c55d8 1680 u32 index;
62cc6b9d 1681
55d2375e
SC		 1682 switch (msr_info->index) {
1683#ifdef CONFIG_X86_64
1684 case MSR_FS_BASE:
1685 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1686 break;
55d2375e
SC		 1687 case MSR_GS_BASE:
1688 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1689 break;
55d2375e
SC		 1690 case MSR_KERNEL_GS_BASE:
1691 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1692 break;
55d2375e
SC		 1693#endif
1694 case MSR_EFER:
1695 return kvm_get_msr_common(vcpu, msr_info);
1696 case MSR_IA32_SPEC_CTRL:
1697 if (!msr_info->host_initiated &&
1698 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1699 return 1;
1700
1701 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1702 break;
6aa8b732 1703 case MSR_IA32_SYSENTER_CS:
609e36d3 1704 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1705 break;
1706 case MSR_IA32_SYSENTER_EIP:
609e36d3 1707 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1708 break;
1709 case MSR_IA32_SYSENTER_ESP:
609e36d3 1710 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1711 break;
0dd376e7 1712 case MSR_IA32_BNDCFGS:
691bd434 1713 if (!kvm_mpx_supported() ||
d6321d49
RK		 1714 (!msr_info->host_initiated &&
1715 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1716 return 1;
609e36d3 1717 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1718 break;
c45dcc71
AR		 1719 case MSR_IA32_MCG_EXT_CTL:
1720 if (!msr_info->host_initiated &&
a6cb099a 1721 !(vmx->msr_ia32_feature_control &
c45dcc71 1722 FEATURE_CONTROL_LMCE))
cae50139 1723 return 1;
c45dcc71
AR		 1724 msr_info->data = vcpu->arch.mcg_ext_ctl;
1725 break;
cae50139 1726 case MSR_IA32_FEATURE_CONTROL:
a6cb099a 1727 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1728 break;
1729 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1730 if (!nested_vmx_allowed(vcpu))
1731 return 1;
6677f3da
PB		 1732 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1733 &msr_info->data);
20300099
WL		 1734 case MSR_IA32_XSS:
1735 if (!vmx_xsaves_supported())
1736 return 1;
609e36d3 1737 msr_info->data = vcpu->arch.ia32_xss;
20300099 1738 break;
bf8c55d8
CP		 1739 case MSR_IA32_RTIT_CTL:
1740 if (pt_mode != PT_MODE_HOST_GUEST)
1741 return 1;
1742 msr_info->data = vmx->pt_desc.guest.ctl;
1743 break;
1744 case MSR_IA32_RTIT_STATUS:
1745 if (pt_mode != PT_MODE_HOST_GUEST)
1746 return 1;
1747 msr_info->data = vmx->pt_desc.guest.status;
1748 break;
1749 case MSR_IA32_RTIT_CR3_MATCH:
1750 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1751 !intel_pt_validate_cap(vmx->pt_desc.caps,
1752 PT_CAP_cr3_filtering))
1753 return 1;
1754 msr_info->data = vmx->pt_desc.guest.cr3_match;
1755 break;
1756 case MSR_IA32_RTIT_OUTPUT_BASE:
1757 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1758 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1759 PT_CAP_topa_output) &&
1760 !intel_pt_validate_cap(vmx->pt_desc.caps,
1761 PT_CAP_single_range_output)))
1762 return 1;
1763 msr_info->data = vmx->pt_desc.guest.output_base;
1764 break;
1765 case MSR_IA32_RTIT_OUTPUT_MASK:
1766 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1767 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1768 PT_CAP_topa_output) &&
1769 !intel_pt_validate_cap(vmx->pt_desc.caps,
1770 PT_CAP_single_range_output)))
1771 return 1;
1772 msr_info->data = vmx->pt_desc.guest.output_mask;
1773 break;
1774 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1775 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1776 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1777 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1778 PT_CAP_num_address_ranges)))
1779 return 1;
1780 if (index % 2)
1781 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1782 else
1783 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1784 break;
4e47c7a6 1785 case MSR_TSC_AUX:
d6321d49
RK		 1786 if (!msr_info->host_initiated &&
1787 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1788 return 1;
b2869f28 1789 /* Else, falls through */
6aa8b732 1790 default:
a6cb099a 1791 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1792 if (msr) {
609e36d3 1793 msr_info->data = msr->data;
3bab1f5d 1794 break;
6aa8b732 1795 }
609e36d3 1796 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1797 }
1798
6aa8b732
AK		 1799 return 0;
1800}
1801
1802/*
1803 * Writes msr value into into the appropriate "register".
1804 * Returns 0 on success, non-0 otherwise.
1805 * Assumes vcpu_load() was already called.
1806 */
8fe8ab46 1807static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1808{
a2fa3e9f 1809 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1810 struct shared_msr_entry *msr;
2cc51560 1811 int ret = 0;
8fe8ab46
WA		 1812 u32 msr_index = msr_info->index;
1813 u64 data = msr_info->data;
bf8c55d8 1814 u32 index;
2cc51560 1815
6aa8b732 1816 switch (msr_index) {
3bab1f5d 1817 case MSR_EFER:
8fe8ab46 1818 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1819 break;
16175a79 1820#ifdef CONFIG_X86_64
6aa8b732 1821 case MSR_FS_BASE:
2fb92db1 1822 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1823 vmcs_writel(GUEST_FS_BASE, data);
1824 break;
1825 case MSR_GS_BASE:
2fb92db1 1826 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1827 vmcs_writel(GUEST_GS_BASE, data);
1828 break;
44ea2b17 1829 case MSR_KERNEL_GS_BASE:
678e315e 1830 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1831 break;
6aa8b732
AK		 1832#endif
1833 case MSR_IA32_SYSENTER_CS:
de70d279
SC		 1834 if (is_guest_mode(vcpu))
1835 get_vmcs12(vcpu)->guest_sysenter_cs = data;
6aa8b732
AK		 1836 vmcs_write32(GUEST_SYSENTER_CS, data);
1837 break;
1838 case MSR_IA32_SYSENTER_EIP:
de70d279
SC		 1839 if (is_guest_mode(vcpu))
1840 get_vmcs12(vcpu)->guest_sysenter_eip = data;
f5b42c33 1841 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1842 break;
1843 case MSR_IA32_SYSENTER_ESP:
de70d279
SC		 1844 if (is_guest_mode(vcpu))
1845 get_vmcs12(vcpu)->guest_sysenter_esp = data;
f5b42c33 1846 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1847 break;
699a1ac2
SC		 1848 case MSR_IA32_DEBUGCTLMSR:
1849 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1850 VM_EXIT_SAVE_DEBUG_CONTROLS)
1851 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1852
1853 ret = kvm_set_msr_common(vcpu, msr_info);
1854 break;
1855
0dd376e7 1856 case MSR_IA32_BNDCFGS:
691bd434 1857 if (!kvm_mpx_supported() ||
d6321d49
RK		 1858 (!msr_info->host_initiated &&
1859 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1860 return 1;
fd8cb433 1861 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 1862 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 1863 return 1;
0dd376e7
LJ		 1864 vmcs_write64(GUEST_BNDCFGS, data);
1865 break;
d28b387f
KA		 1866 case MSR_IA32_SPEC_CTRL:
1867 if (!msr_info->host_initiated &&
d28b387f
KA		 1868 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1869 return 1;
1870
1871 /* The STIBP bit doesn't fault even if it's not advertised */
9f65fb29 1872 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
d28b387f
KA		 1873 return 1;
1874
1875 vmx->spec_ctrl = data;
1876
1877 if (!data)
1878 break;
1879
1880 /*
1881 * For non-nested:
1882 * When it's written (to non-zero) for the first time, pass
1883 * it through.
1884 *
1885 * For nested:
1886 * The handling of the MSR bitmap for L2 guests is done in
1887 * nested_vmx_merge_msr_bitmap. We should not touch the
1888 * vmcs02.msr_bitmap here since it gets completely overwritten
1889 * in the merging. We update the vmcs01 here for L1 as well
1890 * since it will end up touching the MSR anyway now.
1891 */
1892 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1893 MSR_IA32_SPEC_CTRL,
1894 MSR_TYPE_RW);
1895 break;
15d45071
AR		 1896 case MSR_IA32_PRED_CMD:
1897 if (!msr_info->host_initiated &&
15d45071
AR		 1898 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1899 return 1;
1900
1901 if (data & ~PRED_CMD_IBPB)
1902 return 1;
1903
1904 if (!data)
1905 break;
1906
1907 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1908
1909 /*
1910 * For non-nested:
1911 * When it's written (to non-zero) for the first time, pass
1912 * it through.
1913 *
1914 * For nested:
1915 * The handling of the MSR bitmap for L2 guests is done in
1916 * nested_vmx_merge_msr_bitmap. We should not touch the
1917 * vmcs02.msr_bitmap here since it gets completely overwritten
1918 * in the merging.
1919 */
1920 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1921 MSR_TYPE_W);
1922 break;
468d472f 1923 case MSR_IA32_CR_PAT:
d28f4290
SC		 1924 if (!kvm_pat_valid(data))
1925 return 1;
1926
142e4be7
SC		 1927 if (is_guest_mode(vcpu) &&
1928 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
1929 get_vmcs12(vcpu)->guest_ia32_pat = data;
1930
468d472f
SY		 1931 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1932 vmcs_write64(GUEST_IA32_PAT, data);
1933 vcpu->arch.pat = data;
1934 break;
1935 }
8fe8ab46 1936 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1937 break;
ba904635
WA		 1938 case MSR_IA32_TSC_ADJUST:
1939 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1940 break;
c45dcc71
AR		 1941 case MSR_IA32_MCG_EXT_CTL:
1942 if ((!msr_info->host_initiated &&
1943 !(to_vmx(vcpu)->msr_ia32_feature_control &
1944 FEATURE_CONTROL_LMCE)) ||
1945 (data & ~MCG_EXT_CTL_LMCE_EN))
1946 return 1;
1947 vcpu->arch.mcg_ext_ctl = data;
1948 break;
cae50139 1949 case MSR_IA32_FEATURE_CONTROL:
37e4c997 1950 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 1951 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK		 1952 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1953 return 1;
3b84080b 1954 vmx->msr_ia32_feature_control = data;
cae50139
JK		 1955 if (msr_info->host_initiated && data == 0)
1956 vmx_leave_nested(vcpu);
1957 break;
1958 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 1959 if (!msr_info->host_initiated)
1960 return 1; /* they are read-only */
1961 if (!nested_vmx_allowed(vcpu))
1962 return 1;
1963 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL		 1964 case MSR_IA32_XSS:
1965 if (!vmx_xsaves_supported())
1966 return 1;
1967 /*
1968 * The only supported bit as of Skylake is bit 8, but
1969 * it is not supported on KVM.
1970 */
1971 if (data != 0)
1972 return 1;
1973 vcpu->arch.ia32_xss = data;
1974 if (vcpu->arch.ia32_xss != host_xss)
1975 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
989e3992 1976 vcpu->arch.ia32_xss, host_xss, false);
20300099
WL		 1977 else
1978 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
1979 break;
bf8c55d8
CP		 1980 case MSR_IA32_RTIT_CTL:
1981 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 1982 vmx_rtit_ctl_check(vcpu, data) ||
1983 vmx->nested.vmxon)
bf8c55d8
CP		 1984 return 1;
1985 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
1986 vmx->pt_desc.guest.ctl = data;
b08c2896 1987 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 1988 break;
1989 case MSR_IA32_RTIT_STATUS:
1990 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1991 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1992 (data & MSR_IA32_RTIT_STATUS_MASK))
1993 return 1;
1994 vmx->pt_desc.guest.status = data;
1995 break;
1996 case MSR_IA32_RTIT_CR3_MATCH:
1997 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1998 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1999 !intel_pt_validate_cap(vmx->pt_desc.caps,
2000 PT_CAP_cr3_filtering))
2001 return 1;
2002 vmx->pt_desc.guest.cr3_match = data;
2003 break;
2004 case MSR_IA32_RTIT_OUTPUT_BASE:
2005 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2006 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2007 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2008 PT_CAP_topa_output) &&
2009 !intel_pt_validate_cap(vmx->pt_desc.caps,
2010 PT_CAP_single_range_output)) ||
2011 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2012 return 1;
2013 vmx->pt_desc.guest.output_base = data;
2014 break;
2015 case MSR_IA32_RTIT_OUTPUT_MASK:
2016 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2017 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2018 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2019 PT_CAP_topa_output) &&
2020 !intel_pt_validate_cap(vmx->pt_desc.caps,
2021 PT_CAP_single_range_output)))
2022 return 1;
2023 vmx->pt_desc.guest.output_mask = data;
2024 break;
2025 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2026 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2027 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2028 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2029 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2030 PT_CAP_num_address_ranges)))
2031 return 1;
2032 if (index % 2)
2033 vmx->pt_desc.guest.addr_b[index / 2] = data;
2034 else
2035 vmx->pt_desc.guest.addr_a[index / 2] = data;
2036 break;
4e47c7a6 2037 case MSR_TSC_AUX:
d6321d49
RK		 2038 if (!msr_info->host_initiated &&
2039 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2040 return 1;
2041 /* Check reserved bit, higher 32 bits should be zero */
2042 if ((data >> 32) != 0)
2043 return 1;
b2869f28 2044 /* Else, falls through */
6aa8b732 2045 default:
8b9cf98c 2046 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2047 if (msr) {
8b3c3104 2048 u64 old_msr_data = msr->data;
3bab1f5d 2049 msr->data = data;
2225fd56
AK		 2050 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2051 preempt_disable();
8b3c3104
AH		 2052 ret = kvm_set_shared_msr(msr->index, msr->data,
2053 msr->mask);
2225fd56 2054 preempt_enable();
8b3c3104
AH		 2055 if (ret)
2056 msr->data = old_msr_data;
2225fd56 2057 }
3bab1f5d 2058 break;
6aa8b732 2059 }
8fe8ab46 2060 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2061 }
2062
2cc51560 2063 return ret;
6aa8b732
AK		 2064}
2065
5fdbf976 2066static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2067{
5fdbf976
MT		 2068 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2069 switch (reg) {
2070 case VCPU_REGS_RSP:
2071 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2072 break;
2073 case VCPU_REGS_RIP:
2074 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2075 break;
6de4f3ad
AK		 2076 case VCPU_EXREG_PDPTR:
2077 if (enable_ept)
2078 ept_save_pdptrs(vcpu);
2079 break;
5fdbf976
MT		 2080 default:
2081 break;
2082 }
6aa8b732
AK		 2083}
2084
6aa8b732
AK		 2085static __init int cpu_has_kvm_support(void)
2086{
6210e37b 2087 return cpu_has_vmx();
6aa8b732
AK		 2088}
2089
2090static __init int vmx_disabled_by_bios(void)
2091{
2092 u64 msr;
2093
2094 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2095 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2096 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2097 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2098 && tboot_enabled())
2099 return 1;
23f3e991 2100 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2101 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2102 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2103 && !tboot_enabled()) {
2104 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2105 "activate TXT before enabling KVM\n");
cafd6659 2106 return 1;
f9335afe 2107 }
23f3e991
JC		 2108 /* launched w/o TXT and VMX disabled */
2109 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2110 && !tboot_enabled())
2111 return 1;
cafd6659
SW		 2112 }
2113
2114 return 0;
6aa8b732
AK		 2115}
2116
7725b894
DX		 2117static void kvm_cpu_vmxon(u64 addr)
2118{
fe0e80be 2119 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2120 intel_pt_handle_vmx(1);
2121
4b1e5478 2122 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2123}
2124
13a34e06 2125static int hardware_enable(void)
6aa8b732
AK		 2126{
2127 int cpu = raw_smp_processor_id();
2128 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2129 u64 old, test_bits;
6aa8b732 2130
1e02ce4c 2131 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2132 return -EBUSY;
2133
773e8a04
VK		 2134 /*
2135 * This can happen if we hot-added a CPU but failed to allocate
2136 * VP assist page for it.
2137 */
2138 if (static_branch_unlikely(&enable_evmcs) &&
2139 !hv_get_vp_assist_page(cpu))
2140 return -EFAULT;
2141
d462b819 2142 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2143 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2144 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2145
2146 /*
2147 * Now we can enable the vmclear operation in kdump
2148 * since the loaded_vmcss_on_cpu list on this cpu
2149 * has been initialized.
2150 *
2151 * Though the cpu is not in VMX operation now, there
2152 * is no problem to enable the vmclear operation
2153 * for the loaded_vmcss_on_cpu list is empty!
2154 */
2155 crash_enable_local_vmclear(cpu);
2156
6aa8b732 2157 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2158
2159 test_bits = FEATURE_CONTROL_LOCKED;
2160 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2161 if (tboot_enabled())
2162 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2163
2164 if ((old & test_bits) != test_bits) {
6aa8b732 2165 /* enable and lock */
cafd6659
SW		 2166 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2167 }
fe0e80be 2168 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2169 if (enable_ept)
2170 ept_sync_global();
10474ae8
AG		 2171
2172 return 0;
6aa8b732
AK		 2173}
2174
d462b819 2175static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2176{
2177 int cpu = raw_smp_processor_id();
d462b819 2178 struct loaded_vmcs *v, *n;
543e4243 2179
d462b819
NHE		 2180 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2181 loaded_vmcss_on_cpu_link)
2182 __loaded_vmcs_clear(v);
543e4243
AK		 2183}
2184
710ff4a8
EH		 2185
2186/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2187 * tricks.
2188 */
2189static void kvm_cpu_vmxoff(void)
6aa8b732 2190{
4b1e5478 2191 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2192
2193 intel_pt_handle_vmx(0);
fe0e80be 2194 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2195}
2196
13a34e06 2197static void hardware_disable(void)
710ff4a8 2198{
fe0e80be
DH		 2199 vmclear_local_loaded_vmcss();
2200 kvm_cpu_vmxoff();
710ff4a8
EH		 2201}
2202
1c3d14fe 2203static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2204 u32 msr, u32 *result)
1c3d14fe
YS		 2205{
2206 u32 vmx_msr_low, vmx_msr_high;
2207 u32 ctl = ctl_min | ctl_opt;
2208
2209 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2210
2211 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2212 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2213
2214 /* Ensure minimum (required) set of control bits are supported. */
2215 if (ctl_min & ~ctl)
002c7f7c 2216 return -EIO;
1c3d14fe
YS		 2217
2218 *result = ctl;
2219 return 0;
2220}
2221
7caaa711
SC		 2222static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2223 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2224{
2225 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2226 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2227 u32 _pin_based_exec_control = 0;
2228 u32 _cpu_based_exec_control = 0;
f78e0e2e 2229 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2230 u32 _vmexit_control = 0;
2231 u32 _vmentry_control = 0;
2232
1389309c 2233 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2234 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2235#ifdef CONFIG_X86_64
2236 CPU_BASED_CR8_LOAD_EXITING |
2237 CPU_BASED_CR8_STORE_EXITING |
2238#endif
d56f546d
SY		 2239 CPU_BASED_CR3_LOAD_EXITING |
2240 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2241 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2242 CPU_BASED_MOV_DR_EXITING |
a7052897 2243 CPU_BASED_USE_TSC_OFFSETING |
4d5422ce
WL		 2244 CPU_BASED_MWAIT_EXITING |
2245 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2246 CPU_BASED_INVLPG_EXITING |
2247 CPU_BASED_RDPMC_EXITING;
443381a8 2248
f78e0e2e 2249 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2250 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2251 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2252 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2253 &_cpu_based_exec_control) < 0)
002c7f7c 2254 return -EIO;
6e5d865c
YS		 2255#ifdef CONFIG_X86_64
2256 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2257 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2258 ~CPU_BASED_CR8_STORE_EXITING;
2259#endif
f78e0e2e 2260 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2261 min2 = 0;
2262 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2263 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2264 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2265 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2266 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2267 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2268 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2269 SECONDARY_EXEC_DESC |
ad756a16 2270 SECONDARY_EXEC_RDTSCP |
83d4c286 2271 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2272 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2273 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2274 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2275 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2276 SECONDARY_EXEC_RDSEED_EXITING |
2277 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2278 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2279 SECONDARY_EXEC_TSC_SCALING |
f99e3daf
CP		 2280 SECONDARY_EXEC_PT_USE_GPA |
2281 SECONDARY_EXEC_PT_CONCEAL_VMX |
0b665d30
SC		 2282 SECONDARY_EXEC_ENABLE_VMFUNC |
2283 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2284 if (adjust_vmx_controls(min2, opt2,
2285 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2286 &_cpu_based_2nd_exec_control) < 0)
2287 return -EIO;
2288 }
2289#ifndef CONFIG_X86_64
2290 if (!(_cpu_based_2nd_exec_control &
2291 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2292 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2293#endif
83d4c286
YZ		 2294
2295 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2296 _cpu_based_2nd_exec_control &= ~(
8d14695f 2297 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2298 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2299 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2300
61f1dd90 2301 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2302 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2303
d56f546d 2304 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2305 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2306 enabled */
5fff7d27
GN		 2307 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2308 CPU_BASED_CR3_STORE_EXITING |
2309 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2310 } else if (vmx_cap->ept) {
2311 vmx_cap->ept = 0;
61f1dd90
WL		 2312 pr_warn_once("EPT CAP should not exist if not support "
2313 "1-setting enable EPT VM-execution control\n");
2314 }
2315 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2316 vmx_cap->vpid) {
2317 vmx_cap->vpid = 0;
61f1dd90
WL		 2318 pr_warn_once("VPID CAP should not exist if not support "
2319 "1-setting enable VPID VM-execution control\n");
d56f546d 2320 }
1c3d14fe 2321
91fa0f8e 2322 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2323#ifdef CONFIG_X86_64
2324 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2325#endif
c73da3fc 2326 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2327 VM_EXIT_LOAD_IA32_PAT |
2328 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2329 VM_EXIT_CLEAR_BNDCFGS |
2330 VM_EXIT_PT_CONCEAL_PIP |
2331 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2332 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2333 &_vmexit_control) < 0)
002c7f7c 2334 return -EIO;
1c3d14fe 2335
8a1b4392
PB		 2336 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2337 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2338 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2339 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2340 &_pin_based_exec_control) < 0)
2341 return -EIO;
2342
1c17c3e6
PB		 2343 if (cpu_has_broken_vmx_preemption_timer())
2344 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2345 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2346 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2347 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2348
c845f9c6 2349 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2350 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2351 VM_ENTRY_LOAD_IA32_PAT |
2352 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2353 VM_ENTRY_LOAD_BNDCFGS |
2354 VM_ENTRY_PT_CONCEAL_PIP |
2355 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2356 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2357 &_vmentry_control) < 0)
002c7f7c 2358 return -EIO;
6aa8b732 2359
c73da3fc
SC		 2360 /*
2361 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2362 * can't be used due to an errata where VM Exit may incorrectly clear
2363 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2364 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2365 */
2366 if (boot_cpu_data.x86 == 0x6) {
2367 switch (boot_cpu_data.x86_model) {
2368 case 26: /* AAK155 */
2369 case 30: /* AAP115 */
2370 case 37: /* AAT100 */
2371 case 44: /* BC86,AAY89,BD102 */
2372 case 46: /* BA97 */
85ba2b16 2373 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2374 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2375 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2376 "does not work properly. Using workaround\n");
2377 break;
2378 default:
2379 break;
2380 }
2381 }
2382
2383
c68876fd 2384 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2385
2386 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2387 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2388 return -EIO;
1c3d14fe
YS		 2389
2390#ifdef CONFIG_X86_64
2391 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2392 if (vmx_msr_high & (1u<<16))
002c7f7c 2393 return -EIO;
1c3d14fe
YS		 2394#endif
2395
2396 /* Require Write-Back (WB) memory type for VMCS accesses. */
2397 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2398 return -EIO;
1c3d14fe 2399
002c7f7c 2400 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2401 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2402 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2403
2307af1c 2404 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2405
002c7f7c
YS		 2406 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2407 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2408 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2409 vmcs_conf->vmexit_ctrl = _vmexit_control;
2410 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2411
773e8a04
VK		 2412 if (static_branch_unlikely(&enable_evmcs))
2413 evmcs_sanitize_exec_ctrls(vmcs_conf);
2414
1c3d14fe 2415 return 0;
c68876fd 2416}
6aa8b732 2417
41836839 2418struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2419{
2420 int node = cpu_to_node(cpu);
2421 struct page *pages;
2422 struct vmcs *vmcs;
2423
41836839 2424 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2425 if (!pages)
2426 return NULL;
2427 vmcs = page_address(pages);
1c3d14fe 2428 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2429
2430 /* KVM supports Enlightened VMCS v1 only */
2431 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2432 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2433 else
392b2f25 2434 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2435
491a6038
LA		 2436 if (shadow)
2437 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2438 return vmcs;
2439}
2440
89b0c9f5 2441void free_vmcs(struct vmcs *vmcs)
6aa8b732 2442{
1c3d14fe 2443 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2444}
2445
d462b819
NHE		 2446/*
2447 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2448 */
89b0c9f5 2449void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2450{
2451 if (!loaded_vmcs->vmcs)
2452 return;
2453 loaded_vmcs_clear(loaded_vmcs);
2454 free_vmcs(loaded_vmcs->vmcs);
2455 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2456 if (loaded_vmcs->msr_bitmap)
2457 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2458 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2459}
2460
89b0c9f5 2461int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2462{
491a6038 2463 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2464 if (!loaded_vmcs->vmcs)
2465 return -ENOMEM;
2466
2467 loaded_vmcs->shadow_vmcs = NULL;
2468 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2469
2470 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2471 loaded_vmcs->msr_bitmap = (unsigned long *)
2472 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2473 if (!loaded_vmcs->msr_bitmap)
2474 goto out_vmcs;
2475 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2476
1f008e11
AB		 2477 if (IS_ENABLED(CONFIG_HYPERV) &&
2478 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2479 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2480 struct hv_enlightened_vmcs *evmcs =
2481 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2482
2483 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2484 }
904e14fb 2485 }
d7ee039e
SC		 2486
2487 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2488
f21f165e 2489 return 0;
904e14fb
PB		 2490
2491out_vmcs:
2492 free_loaded_vmcs(loaded_vmcs);
2493 return -ENOMEM;
f21f165e
PB		 2494}
2495
39959588 2496static void free_kvm_area(void)
6aa8b732
AK		 2497{
2498 int cpu;
2499
3230bb47 2500 for_each_possible_cpu(cpu) {
6aa8b732 2501 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2502 per_cpu(vmxarea, cpu) = NULL;
2503 }
6aa8b732
AK		 2504}
2505
6aa8b732
AK		 2506static __init int alloc_kvm_area(void)
2507{
2508 int cpu;
2509
3230bb47 2510 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2511 struct vmcs *vmcs;
2512
41836839 2513 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2514 if (!vmcs) {
2515 free_kvm_area();
2516 return -ENOMEM;
2517 }
2518
2307af1c
LA		 2519 /*
2520 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2521 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2522 * revision_id reported by MSR_IA32_VMX_BASIC.
2523 *
312a4661 2524 * However, even though not explicitly documented by
2307af1c
LA		 2525 * TLFS, VMXArea passed as VMXON argument should
2526 * still be marked with revision_id reported by
2527 * physical CPU.
2528 */
2529 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2530 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2531
6aa8b732
AK		 2532 per_cpu(vmxarea, cpu) = vmcs;
2533 }
2534 return 0;
2535}
2536
91b0aa2c 2537static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2538 struct kvm_segment *save)
6aa8b732 2539{
d99e4152
GN		 2540 if (!emulate_invalid_guest_state) {
2541 /*
2542 * CS and SS RPL should be equal during guest entry according
2543 * to VMX spec, but in reality it is not always so. Since vcpu
2544 * is in the middle of the transition from real mode to
2545 * protected mode it is safe to assume that RPL 0 is a good
2546 * default value.
2547 */
2548 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2549 save->selector &= ~SEGMENT_RPL_MASK;
2550 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2551 save->s = 1;
6aa8b732 2552 }
d99e4152 2553 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2554}
2555
2556static void enter_pmode(struct kvm_vcpu *vcpu)
2557{
2558 unsigned long flags;
a89a8fb9 2559 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2560
d99e4152
GN		 2561 /*
2562 * Update real mode segment cache. It may be not up-to-date if sement
2563 * register was written while vcpu was in a guest mode.
2564 */
2565 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2566 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2567 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2568 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2569 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2570 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2571
7ffd92c5 2572 vmx->rmode.vm86_active = 0;
6aa8b732 2573
2fb92db1
AK		 2574 vmx_segment_cache_clear(vmx);
2575
f5f7b2fe 2576 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2577
2578 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2579 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2580 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2581 vmcs_writel(GUEST_RFLAGS, flags);
2582
66aee91a
RR		 2583 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2584 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2585
2586 update_exception_bitmap(vcpu);
2587
91b0aa2c
GN		 2588 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2589 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2590 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2591 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2592 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2593 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2594}
2595
f5f7b2fe 2596static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2597{
772e0318 2598 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2599 struct kvm_segment var = *save;
2600
2601 var.dpl = 0x3;
2602 if (seg == VCPU_SREG_CS)
2603 var.type = 0x3;
2604
2605 if (!emulate_invalid_guest_state) {
2606 var.selector = var.base >> 4;
2607 var.base = var.base & 0xffff0;
2608 var.limit = 0xffff;
2609 var.g = 0;
2610 var.db = 0;
2611 var.present = 1;
2612 var.s = 1;
2613 var.l = 0;
2614 var.unusable = 0;
2615 var.type = 0x3;
2616 var.avl = 0;
2617 if (save->base & 0xf)
2618 printk_once(KERN_WARNING "kvm: segment base is not "
2619 "paragraph aligned when entering "
2620 "protected mode (seg=%d)", seg);
2621 }
6aa8b732 2622
d99e4152 2623 vmcs_write16(sf->selector, var.selector);
96794e4e 2624 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2625 vmcs_write32(sf->limit, var.limit);
2626 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2627}
2628
2629static void enter_rmode(struct kvm_vcpu *vcpu)
2630{
2631 unsigned long flags;
a89a8fb9 2632 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2633 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2634
f5f7b2fe
AK		 2635 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2636 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2637 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2638 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2639 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2640 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2641 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2642
7ffd92c5 2643 vmx->rmode.vm86_active = 1;
6aa8b732 2644
776e58ea
GN		 2645 /*
2646 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2647 * vcpu. Warn the user that an update is overdue.
776e58ea 2648 */
40bbb9d0 2649 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2650 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2651 "called before entering vcpu\n");
776e58ea 2652
2fb92db1
AK		 2653 vmx_segment_cache_clear(vmx);
2654
40bbb9d0 2655 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2656 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2657 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2658
2659 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2660 vmx->rmode.save_rflags = flags;
6aa8b732 2661
053de044 2662 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2663
2664 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2665 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2666 update_exception_bitmap(vcpu);
2667
d99e4152
GN		 2668 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2669 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2670 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2671 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2672 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2673 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2674
8668a3c4 2675 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2676}
2677
97b7ead3 2678void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2679{
2680 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2681 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2682
2683 if (!msr)
2684 return;
401d10de 2685
f6801dff 2686 vcpu->arch.efer = efer;
401d10de 2687 if (efer & EFER_LMA) {
2961e876 2688 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2689 msr->data = efer;
2690 } else {
2961e876 2691 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2692
2693 msr->data = efer & ~EFER_LME;
2694 }
2695 setup_msrs(vmx);
2696}
2697
05b3e0c2 2698#ifdef CONFIG_X86_64
6aa8b732
AK		 2699
2700static void enter_lmode(struct kvm_vcpu *vcpu)
2701{
2702 u32 guest_tr_ar;
2703
2fb92db1
AK		 2704 vmx_segment_cache_clear(to_vmx(vcpu));
2705
6aa8b732 2706 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2707 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2708 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2709 __func__);
6aa8b732 2710 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2711 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2712 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2713 }
da38f438 2714 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2715}
2716
2717static void exit_lmode(struct kvm_vcpu *vcpu)
2718{
2961e876 2719 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2720 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2721}
2722
2723#endif
2724
faff8758
JS		 2725static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2726{
2727 int vpid = to_vmx(vcpu)->vpid;
2728
2729 if (!vpid_sync_vcpu_addr(vpid, addr))
2730 vpid_sync_context(vpid);
2731
2732 /*
2733 * If VPIDs are not supported or enabled, then the above is a no-op.
2734 * But we don't really need a TLB flush in that case anyway, because
2735 * each VM entry/exit includes an implicit flush when VPID is 0.
2736 */
2737}
2738
e8467fda
AK		 2739static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2740{
2741 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2742
2743 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2744 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2745}
2746
aff48baa
AK		 2747static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2748{
b4d18517 2749 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
aff48baa
AK		 2750 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2751 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2752}
2753
25c4c276 2754static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2755{
fc78f519
AK		 2756 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2757
2758 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2759 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2760}
2761
1439442c
SY		 2762static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2763{
d0d538b9
GN		 2764 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2765
6de4f3ad
AK		 2766 if (!test_bit(VCPU_EXREG_PDPTR,
2767 (unsigned long *)&vcpu->arch.regs_dirty))
2768 return;
2769
bf03d4f9 2770 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2771 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2772 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2773 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2774 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2775 }
2776}
2777
97b7ead3 2778void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2779{
d0d538b9
GN		 2780 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2781
bf03d4f9 2782 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2783 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2784 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2785 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2786 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2787 }
6de4f3ad
AK		 2788
2789 __set_bit(VCPU_EXREG_PDPTR,
2790 (unsigned long *)&vcpu->arch.regs_avail);
2791 __set_bit(VCPU_EXREG_PDPTR,
2792 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2793}
2794
1439442c
SY		 2795static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2796 unsigned long cr0,
2797 struct kvm_vcpu *vcpu)
2798{
5233dd51
MT		 2799 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2800 vmx_decache_cr3(vcpu);
1439442c
SY		 2801 if (!(cr0 & X86_CR0_PG)) {
2802 /* From paging/starting to nonpaging */
2803 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2804 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2805 (CPU_BASED_CR3_LOAD_EXITING |
2806 CPU_BASED_CR3_STORE_EXITING));
2807 vcpu->arch.cr0 = cr0;
fc78f519 2808 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2809 } else if (!is_paging(vcpu)) {
2810 /* From nonpaging to paging */
2811 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2812 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2813 ~(CPU_BASED_CR3_LOAD_EXITING |
2814 CPU_BASED_CR3_STORE_EXITING));
2815 vcpu->arch.cr0 = cr0;
fc78f519 2816 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2817 }
95eb84a7
SY		 2818
2819 if (!(cr0 & X86_CR0_WP))
2820 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2821}
2822
97b7ead3 2823void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2824{
7ffd92c5 2825 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2826 unsigned long hw_cr0;
2827
3de6347b 2828 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2829 if (enable_unrestricted_guest)
5037878e 2830 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2831 else {
5037878e 2832 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2833
218e763f
GN		 2834 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2835 enter_pmode(vcpu);
6aa8b732 2836
218e763f
GN		 2837 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2838 enter_rmode(vcpu);
2839 }
6aa8b732 2840
05b3e0c2 2841#ifdef CONFIG_X86_64
f6801dff 2842 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2843 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2844 enter_lmode(vcpu);
707d92fa 2845 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2846 exit_lmode(vcpu);
2847 }
2848#endif
2849
b4d18517 2850 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2851 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2852
6aa8b732 2853 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2854 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2855 vcpu->arch.cr0 = cr0;
14168786
GN		 2856
2857 /* depends on vcpu->arch.cr0 to be set to a new value */
2858 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2859}
2860
855feb67
YZ		 2861static int get_ept_level(struct kvm_vcpu *vcpu)
2862{
2863 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2864 return 5;
2865 return 4;
2866}
2867
89b0c9f5 2868u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2869{
855feb67
YZ		 2870 u64 eptp = VMX_EPTP_MT_WB;
2871
2872 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 2873
995f00a6
PF		 2874 if (enable_ept_ad_bits &&
2875 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 2876 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 2877 eptp |= (root_hpa & PAGE_MASK);
2878
2879 return eptp;
2880}
2881
97b7ead3 2882void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 2883{
877ad952 2884 struct kvm *kvm = vcpu->kvm;
1439442c
SY		 2885 unsigned long guest_cr3;
2886 u64 eptp;
2887
2888 guest_cr3 = cr3;
089d034e 2889 if (enable_ept) {
995f00a6 2890 eptp = construct_eptp(vcpu, cr3);
1439442c 2891 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 2892
2893 if (kvm_x86_ops->tlb_remote_flush) {
2894 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2895 to_vmx(vcpu)->ept_pointer = eptp;
2896 to_kvm_vmx(kvm)->ept_pointers_match
2897 = EPT_POINTERS_CHECK;
2898 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2899 }
2900
e90008df
SC		 2901 if (enable_unrestricted_guest || is_paging(vcpu) ||
2902 is_guest_mode(vcpu))
59ab5a8f
JK		 2903 guest_cr3 = kvm_read_cr3(vcpu);
2904 else
877ad952 2905 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
7c93be44 2906 ept_load_pdptrs(vcpu);
1439442c
SY		 2907 }
2908
1439442c 2909 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2910}
2911
97b7ead3 2912int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2913{
085e68ee
BS		 2914 /*
2915 * Pass through host's Machine Check Enable value to hw_cr4, which
2916 * is in force while we are in guest mode. Do not let guests control
2917 * this bit, even if host CR4.MCE == 0.
2918 */
5dc1f044
SC		 2919 unsigned long hw_cr4;
2920
2921 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2922 if (enable_unrestricted_guest)
2923 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2924 else if (to_vmx(vcpu)->rmode.vm86_active)
2925 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2926 else
2927 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 2928
64f7a115
SC		 2929 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2930 if (cr4 & X86_CR4_UMIP) {
2931 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
0367f205 2932 SECONDARY_EXEC_DESC);
64f7a115
SC		 2933 hw_cr4 &= ~X86_CR4_UMIP;
2934 } else if (!is_guest_mode(vcpu) ||
2935 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
2936 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
2937 SECONDARY_EXEC_DESC);
2938 }
0367f205 2939
5e1746d6
NHE		 2940 if (cr4 & X86_CR4_VMXE) {
2941 /*
2942 * To use VMXON (and later other VMX instructions), a guest
2943 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2944 * So basically the check on whether to allow nested VMX
5bea5123
PB		 2945 * is here. We operate under the default treatment of SMM,
2946 * so VMX cannot be enabled under SMM.
5e1746d6 2947 */
5bea5123 2948 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 2949 return 1;
1a0d74e6 2950 }
3899152c
DM		 2951
2952 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 2953 return 1;
2954
ad312c7c 2955 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 2956
2957 if (!enable_unrestricted_guest) {
2958 if (enable_ept) {
2959 if (!is_paging(vcpu)) {
2960 hw_cr4 &= ~X86_CR4_PAE;
2961 hw_cr4 |= X86_CR4_PSE;
2962 } else if (!(cr4 & X86_CR4_PAE)) {
2963 hw_cr4 &= ~X86_CR4_PAE;
2964 }
bc23008b 2965 }
1439442c 2966
656ec4a4 2967 /*
ddba2628
HH		 2968 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
2969 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
2970 * to be manually disabled when guest switches to non-paging
2971 * mode.
2972 *
2973 * If !enable_unrestricted_guest, the CPU is always running
2974 * with CR0.PG=1 and CR4 needs to be modified.
2975 * If enable_unrestricted_guest, the CPU automatically
2976 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 2977 */
5dc1f044
SC		 2978 if (!is_paging(vcpu))
2979 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
2980 }
656ec4a4 2981
1439442c
SY		 2982 vmcs_writel(CR4_READ_SHADOW, cr4);
2983 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2984 return 0;
6aa8b732
AK		 2985}
2986
97b7ead3 2987void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 2988{
a9179499 2989 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2990 u32 ar;
2991
c6ad1153 2992 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 2993 *var = vmx->rmode.segs[seg];
a9179499 2994 if (seg == VCPU_SREG_TR
2fb92db1 2995 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 2996 return;
1390a28b
AK		 2997 var->base = vmx_read_guest_seg_base(vmx, seg);
2998 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2999 return;
a9179499 3000 }
2fb92db1
AK		 3001 var->base = vmx_read_guest_seg_base(vmx, seg);
3002 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3003 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3004 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3005 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3006 var->type = ar & 15;
3007 var->s = (ar >> 4) & 1;
3008 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3009 /*
3010 * Some userspaces do not preserve unusable property. Since usable
3011 * segment has to be present according to VMX spec we can use present
3012 * property to amend userspace bug by making unusable segment always
3013 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3014 * segment as unusable.
3015 */
3016 var->present = !var->unusable;
6aa8b732
AK		 3017 var->avl = (ar >> 12) & 1;
3018 var->l = (ar >> 13) & 1;
3019 var->db = (ar >> 14) & 1;
3020 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3021}
3022
a9179499
AK		 3023static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3024{
a9179499
AK		 3025 struct kvm_segment s;
3026
3027 if (to_vmx(vcpu)->rmode.vm86_active) {
3028 vmx_get_segment(vcpu, &s, seg);
3029 return s.base;
3030 }
2fb92db1 3031 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3032}
3033
97b7ead3 3034int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3035{
b09408d0
MT		 3036 struct vcpu_vmx *vmx = to_vmx(vcpu);
3037
ae9fedc7 3038 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3039 return 0;
ae9fedc7
PB		 3040 else {
3041 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3042 return VMX_AR_DPL(ar);
69c73028 3043 }
69c73028
AK		 3044}
3045
653e3108 3046static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3047{
6aa8b732
AK		 3048 u32 ar;
3049
f0495f9b 3050 if (var->unusable || !var->present)
6aa8b732
AK		 3051 ar = 1 << 16;
3052 else {
3053 ar = var->type & 15;
3054 ar |= (var->s & 1) << 4;
3055 ar |= (var->dpl & 3) << 5;
3056 ar |= (var->present & 1) << 7;
3057 ar |= (var->avl & 1) << 12;
3058 ar |= (var->l & 1) << 13;
3059 ar |= (var->db & 1) << 14;
3060 ar |= (var->g & 1) << 15;
3061 }
653e3108
AK		 3062
3063 return ar;
3064}
3065
97b7ead3 3066void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3067{
7ffd92c5 3068 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3069 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3070
2fb92db1
AK		 3071 vmx_segment_cache_clear(vmx);
3072
1ecd50a9
GN		 3073 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3074 vmx->rmode.segs[seg] = *var;
3075 if (seg == VCPU_SREG_TR)
3076 vmcs_write16(sf->selector, var->selector);
3077 else if (var->s)
3078 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3079 goto out;
653e3108 3080 }
1ecd50a9 3081
653e3108
AK		 3082 vmcs_writel(sf->base, var->base);
3083 vmcs_write32(sf->limit, var->limit);
3084 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3085
3086 /*
3087 * Fix the "Accessed" bit in AR field of segment registers for older
3088 * qemu binaries.
3089 * IA32 arch specifies that at the time of processor reset the
3090 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3091 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3092 * state vmexit when "unrestricted guest" mode is turned on.
3093 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3094 * tree. Newer qemu binaries with that qemu fix would not need this
3095 * kvm hack.
3096 */
3097 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3098 var->type |= 0x1; /* Accessed */
3a624e29 3099
f924d66d 3100 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3101
3102out:
98eb2f8b 3103 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3104}
3105
6aa8b732
AK		 3106static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3107{
2fb92db1 3108 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3109
3110 *db = (ar >> 14) & 1;
3111 *l = (ar >> 13) & 1;
3112}
3113
89a27f4d 3114static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3115{
89a27f4d
GN		 3116 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3117 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3118}
3119
89a27f4d 3120static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3121{
89a27f4d
GN		 3122 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3123 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3124}
3125
89a27f4d 3126static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3127{
89a27f4d
GN		 3128 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3129 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3130}
3131
89a27f4d 3132static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3133{
89a27f4d
GN		 3134 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3135 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3136}
3137
648dfaa7
MG		 3138static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3139{
3140 struct kvm_segment var;
3141 u32 ar;
3142
3143 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3144 var.dpl = 0x3;
0647f4aa
GN		 3145 if (seg == VCPU_SREG_CS)
3146 var.type = 0x3;
648dfaa7
MG		 3147 ar = vmx_segment_access_rights(&var);
3148
3149 if (var.base != (var.selector << 4))
3150 return false;
89efbed0 3151 if (var.limit != 0xffff)
648dfaa7 3152 return false;
07f42f5f 3153 if (ar != 0xf3)
648dfaa7
MG		 3154 return false;
3155
3156 return true;
3157}
3158
3159static bool code_segment_valid(struct kvm_vcpu *vcpu)
3160{
3161 struct kvm_segment cs;
3162 unsigned int cs_rpl;
3163
3164 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3165 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3166
1872a3f4
AK		 3167 if (cs.unusable)
3168 return false;
4d283ec9 3169 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3170 return false;
3171 if (!cs.s)
3172 return false;
4d283ec9 3173 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3174 if (cs.dpl > cs_rpl)
3175 return false;
1872a3f4 3176 } else {
648dfaa7
MG		 3177 if (cs.dpl != cs_rpl)
3178 return false;
3179 }
3180 if (!cs.present)
3181 return false;
3182
3183 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3184 return true;
3185}
3186
3187static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3188{
3189 struct kvm_segment ss;
3190 unsigned int ss_rpl;
3191
3192 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3193 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3194
1872a3f4
AK		 3195 if (ss.unusable)
3196 return true;
3197 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3198 return false;
3199 if (!ss.s)
3200 return false;
3201 if (ss.dpl != ss_rpl) /* DPL != RPL */
3202 return false;
3203 if (!ss.present)
3204 return false;
3205
3206 return true;
3207}
3208
3209static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3210{
3211 struct kvm_segment var;
3212 unsigned int rpl;
3213
3214 vmx_get_segment(vcpu, &var, seg);
b32a9918 3215 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3216
1872a3f4
AK		 3217 if (var.unusable)
3218 return true;
648dfaa7
MG		 3219 if (!var.s)
3220 return false;
3221 if (!var.present)
3222 return false;
4d283ec9 3223 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3224 if (var.dpl < rpl) /* DPL < RPL */
3225 return false;
3226 }
3227
3228 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3229 * rights flags
3230 */
3231 return true;
3232}
3233
3234static bool tr_valid(struct kvm_vcpu *vcpu)
3235{
3236 struct kvm_segment tr;
3237
3238 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3239
1872a3f4
AK		 3240 if (tr.unusable)
3241 return false;
b32a9918 3242 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3243 return false;
1872a3f4 3244 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3245 return false;
3246 if (!tr.present)
3247 return false;
3248
3249 return true;
3250}
3251
3252static bool ldtr_valid(struct kvm_vcpu *vcpu)
3253{
3254 struct kvm_segment ldtr;
3255
3256 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3257
1872a3f4
AK		 3258 if (ldtr.unusable)
3259 return true;
b32a9918 3260 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3261 return false;
3262 if (ldtr.type != 2)
3263 return false;
3264 if (!ldtr.present)
3265 return false;
3266
3267 return true;
3268}
3269
3270static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3271{
3272 struct kvm_segment cs, ss;
3273
3274 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3275 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3276
b32a9918
NA		 3277 return ((cs.selector & SEGMENT_RPL_MASK) ==
3278 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3279}
3280
3281/*
3282 * Check if guest state is valid. Returns true if valid, false if
3283 * not.
3284 * We assume that registers are always usable
3285 */
3286static bool guest_state_valid(struct kvm_vcpu *vcpu)
3287{
c5e97c80
GN		 3288 if (enable_unrestricted_guest)
3289 return true;
3290
648dfaa7 3291 /* real mode guest state checks */
f13882d8 3292 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3293 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3294 return false;
3295 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3296 return false;
3297 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3298 return false;
3299 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3300 return false;
3301 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3302 return false;
3303 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3304 return false;
3305 } else {
3306 /* protected mode guest state checks */
3307 if (!cs_ss_rpl_check(vcpu))
3308 return false;
3309 if (!code_segment_valid(vcpu))
3310 return false;
3311 if (!stack_segment_valid(vcpu))
3312 return false;
3313 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3314 return false;
3315 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3316 return false;
3317 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3318 return false;
3319 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3320 return false;
3321 if (!tr_valid(vcpu))
3322 return false;
3323 if (!ldtr_valid(vcpu))
3324 return false;
3325 }
3326 /* TODO:
3327 * - Add checks on RIP
3328 * - Add checks on RFLAGS
3329 */
3330
3331 return true;
3332}
3333
d77c26fc 3334static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3335{
40dcaa9f 3336 gfn_t fn;
195aefde 3337 u16 data = 0;
1f755a82 3338 int idx, r;
6aa8b732 3339
40dcaa9f 3340 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3341 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3342 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3343 if (r < 0)
10589a46 3344 goto out;
195aefde 3345 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3346 r = kvm_write_guest_page(kvm, fn++, &data,
3347 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3348 if (r < 0)
10589a46 3349 goto out;
195aefde
IE		 3350 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3351 if (r < 0)
10589a46 3352 goto out;
195aefde
IE		 3353 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3354 if (r < 0)
10589a46 3355 goto out;
195aefde 3356 data = ~0;
10589a46
MT		 3357 r = kvm_write_guest_page(kvm, fn, &data,
3358 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3359 sizeof(u8));
10589a46 3360out:
40dcaa9f 3361 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3362 return r;
6aa8b732
AK		 3363}
3364
b7ebfb05
SY		 3365static int init_rmode_identity_map(struct kvm *kvm)
3366{
40bbb9d0 3367 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
f51770ed 3368 int i, idx, r = 0;
ba049e93 3369 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3370 u32 tmp;
3371
40bbb9d0 3372 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3373 mutex_lock(&kvm->slots_lock);
3374
40bbb9d0 3375 if (likely(kvm_vmx->ept_identity_pagetable_done))
a255d479 3376 goto out2;
a255d479 3377
40bbb9d0
SC		 3378 if (!kvm_vmx->ept_identity_map_addr)
3379 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3380 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3381
d8a6e365 3382 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3383 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3384 if (r < 0)
a255d479
TC		 3385 goto out2;
3386
40dcaa9f 3387 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3388 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3389 if (r < 0)
3390 goto out;
3391 /* Set up identity-mapping pagetable for EPT in real mode */
3392 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3393 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3394 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3395 r = kvm_write_guest_page(kvm, identity_map_pfn,
3396 &tmp, i * sizeof(tmp), sizeof(tmp));
3397 if (r < 0)
3398 goto out;
3399 }
40bbb9d0 3400 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3401
b7ebfb05 3402out:
40dcaa9f 3403 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3404
3405out2:
3406 mutex_unlock(&kvm->slots_lock);
f51770ed 3407 return r;
b7ebfb05
SY		 3408}
3409
6aa8b732
AK		 3410static void seg_setup(int seg)
3411{
772e0318 3412 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3413 unsigned int ar;
6aa8b732
AK		 3414
3415 vmcs_write16(sf->selector, 0);
3416 vmcs_writel(sf->base, 0);
3417 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3418 ar = 0x93;
3419 if (seg == VCPU_SREG_CS)
3420 ar |= 0x08; /* code segment */
3a624e29
NK		 3421
3422 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3423}
3424
f78e0e2e
SY		 3425static int alloc_apic_access_page(struct kvm *kvm)
3426{
4484141a 3427 struct page *page;
f78e0e2e
SY		 3428 int r = 0;
3429
79fac95e 3430 mutex_lock(&kvm->slots_lock);
c24ae0dc 3431 if (kvm->arch.apic_access_page_done)
f78e0e2e 3432 goto out;
1d8007bd
PB		 3433 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3434 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3435 if (r)
3436 goto out;
72dc67a6 3437
73a6d941 3438 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3439 if (is_error_page(page)) {
3440 r = -EFAULT;
3441 goto out;
3442 }
3443
c24ae0dc
TC		 3444 /*
3445 * Do not pin the page in memory, so that memory hot-unplug
3446 * is able to migrate it.
3447 */
3448 put_page(page);
3449 kvm->arch.apic_access_page_done = true;
f78e0e2e 3450out:
79fac95e 3451 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3452 return r;
3453}
3454
97b7ead3 3455int allocate_vpid(void)
2384d2b3
SY		 3456{
3457 int vpid;
3458
919818ab 3459 if (!enable_vpid)
991e7a0e 3460 return 0;
2384d2b3
SY		 3461 spin_lock(&vmx_vpid_lock);
3462 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3463 if (vpid < VMX_NR_VPIDS)
2384d2b3 3464 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3465 else
3466 vpid = 0;
2384d2b3 3467 spin_unlock(&vmx_vpid_lock);
991e7a0e 3468 return vpid;
2384d2b3
SY		 3469}
3470
97b7ead3 3471void free_vpid(int vpid)
cdbecfc3 3472{
991e7a0e 3473 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3474 return;
3475 spin_lock(&vmx_vpid_lock);
991e7a0e 3476 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3477 spin_unlock(&vmx_vpid_lock);
3478}
3479
1e4329ee 3480static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3481 u32 msr, int type)
25c5f225 3482{
3e7c73e9 3483 int f = sizeof(unsigned long);
25c5f225
SY		 3484
3485 if (!cpu_has_vmx_msr_bitmap())
3486 return;
3487
ceef7d10
VK		 3488 if (static_branch_unlikely(&enable_evmcs))
3489 evmcs_touch_msr_bitmap();
3490
25c5f225
SY		 3491 /*
3492 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3493 * have the write-low and read-high bitmap offsets the wrong way round.
3494 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3495 */
25c5f225 3496 if (msr <= 0x1fff) {
8d14695f
YZ		 3497 if (type & MSR_TYPE_R)
3498 /* read-low */
3499 __clear_bit(msr, msr_bitmap + 0x000 / f);
3500
3501 if (type & MSR_TYPE_W)
3502 /* write-low */
3503 __clear_bit(msr, msr_bitmap + 0x800 / f);
3504
25c5f225
SY		 3505 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3506 msr &= 0x1fff;
8d14695f
YZ		 3507 if (type & MSR_TYPE_R)
3508 /* read-high */
3509 __clear_bit(msr, msr_bitmap + 0x400 / f);
3510
3511 if (type & MSR_TYPE_W)
3512 /* write-high */
3513 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3514
3515 }
3516}
3517
1e4329ee 3518static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3519 u32 msr, int type)
3520{
3521 int f = sizeof(unsigned long);
3522
3523 if (!cpu_has_vmx_msr_bitmap())
3524 return;
3525
ceef7d10
VK		 3526 if (static_branch_unlikely(&enable_evmcs))
3527 evmcs_touch_msr_bitmap();
3528
904e14fb
PB		 3529 /*
3530 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3531 * have the write-low and read-high bitmap offsets the wrong way round.
3532 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3533 */
3534 if (msr <= 0x1fff) {
3535 if (type & MSR_TYPE_R)
3536 /* read-low */
3537 __set_bit(msr, msr_bitmap + 0x000 / f);
3538
3539 if (type & MSR_TYPE_W)
3540 /* write-low */
3541 __set_bit(msr, msr_bitmap + 0x800 / f);
3542
3543 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3544 msr &= 0x1fff;
3545 if (type & MSR_TYPE_R)
3546 /* read-high */
3547 __set_bit(msr, msr_bitmap + 0x400 / f);
3548
3549 if (type & MSR_TYPE_W)
3550 /* write-high */
3551 __set_bit(msr, msr_bitmap + 0xc00 / f);
3552
3553 }
3554}
3555
1e4329ee 3556static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3557 u32 msr, int type, bool value)
3558{
3559 if (value)
3560 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3561 else
3562 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3563}
3564
904e14fb 3565static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3566{
904e14fb
PB		 3567 u8 mode = 0;
3568
3569 if (cpu_has_secondary_exec_ctrls() &&
3570 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
3571 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3572 mode |= MSR_BITMAP_MODE_X2APIC;
3573 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3574 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3575 }
3576
904e14fb 3577 return mode;
8d14695f
YZ		 3578}
3579
904e14fb
PB		 3580static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3581 u8 mode)
8d14695f 3582{
904e14fb
PB		 3583 int msr;
3584
3585 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3586 unsigned word = msr / BITS_PER_LONG;
3587 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3588 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3589 }
3590
3591 if (mode & MSR_BITMAP_MODE_X2APIC) {
3592 /*
3593 * TPR reads and writes can be virtualized even if virtual interrupt
3594 * delivery is not in use.
3595 */
3596 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3597 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3598 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3599 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3600 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3601 }
f6e90f9e 3602 }
5897297b
AK		 3603}
3604
97b7ead3 3605void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3606{
3607 struct vcpu_vmx *vmx = to_vmx(vcpu);
3608 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3609 u8 mode = vmx_msr_bitmap_mode(vcpu);
3610 u8 changed = mode ^ vmx->msr_bitmap_mode;
3611
3612 if (!changed)
3613 return;
3614
904e14fb
PB		 3615 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3616 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3617
3618 vmx->msr_bitmap_mode = mode;
3619}
3620
b08c2896
CP		 3621void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3622{
3623 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3624 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3625 u32 i;
3626
3627 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3628 MSR_TYPE_RW, flag);
3629 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3630 MSR_TYPE_RW, flag);
3631 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3632 MSR_TYPE_RW, flag);
3633 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3634 MSR_TYPE_RW, flag);
3635 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3636 vmx_set_intercept_for_msr(msr_bitmap,
3637 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3638 vmx_set_intercept_for_msr(msr_bitmap,
3639 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3640 }
3641}
3642
b2a05fef 3643static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
d50ab6c1 3644{
d62caabb 3645 return enable_apicv;
d50ab6c1
PB		 3646}
3647
e6c67d8c
LA		 3648static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3649{
3650 struct vcpu_vmx *vmx = to_vmx(vcpu);
3651 void *vapic_page;
3652 u32 vppr;
3653 int rvi;
3654
3655 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3656 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
96c66e87 3657 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
e6c67d8c
LA		 3658 return false;
3659
7e712684 3660 rvi = vmx_get_rvi();
e6c67d8c 3661
96c66e87 3662 vapic_page = vmx->nested.virtual_apic_map.hva;
e6c67d8c 3663 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
e6c67d8c
LA		 3664
3665 return ((rvi & 0xf0) > (vppr & 0xf0));
3666}
3667
06a5524f
WV		 3668static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3669 bool nested)
21bc8dc5
RK		 3670{
3671#ifdef CONFIG_SMP
06a5524f
WV		 3672 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3673
21bc8dc5 3674 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3675 /*
5753743f
HZ		 3676 * The vector of interrupt to be delivered to vcpu had
3677 * been set in PIR before this function.
3678 *
3679 * Following cases will be reached in this block, and
3680 * we always send a notification event in all cases as
3681 * explained below.
3682 *
3683 * Case 1: vcpu keeps in non-root mode. Sending a
3684 * notification event posts the interrupt to vcpu.
3685 *
3686 * Case 2: vcpu exits to root mode and is still
3687 * runnable. PIR will be synced to vIRR before the
3688 * next vcpu entry. Sending a notification event in
3689 * this case has no effect, as vcpu is not in root
3690 * mode.
28b835d6 3691 *
5753743f
HZ		 3692 * Case 3: vcpu exits to root mode and is blocked.
3693 * vcpu_block() has already synced PIR to vIRR and
3694 * never blocks vcpu if vIRR is not cleared. Therefore,
3695 * a blocked vcpu here does not wait for any requested
3696 * interrupts in PIR, and sending a notification event
3697 * which has no effect is safe here.
28b835d6 3698 */
28b835d6 3699
06a5524f 3700 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3701 return true;
3702 }
3703#endif
3704 return false;
3705}
3706
705699a1
WV		 3707static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3708 int vector)
3709{
3710 struct vcpu_vmx *vmx = to_vmx(vcpu);
3711
3712 if (is_guest_mode(vcpu) &&
3713 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3714 /*
3715 * If a posted intr is not recognized by hardware,
3716 * we will accomplish it in the next vmentry.
3717 */
3718 vmx->nested.pi_pending = true;
3719 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3720 /* the PIR and ON have been set by L1. */
3721 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3722 kvm_vcpu_kick(vcpu);
705699a1
WV		 3723 return 0;
3724 }
3725 return -1;
3726}
a20ed54d
YZ		 3727/*
3728 * Send interrupt to vcpu via posted interrupt way.
3729 * 1. If target vcpu is running(non-root mode), send posted interrupt
3730 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3731 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3732 * interrupt from PIR in next vmentry.
3733 */
3734static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3735{
3736 struct vcpu_vmx *vmx = to_vmx(vcpu);
3737 int r;
3738
705699a1
WV		 3739 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3740 if (!r)
3741 return;
3742
a20ed54d
YZ		 3743 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3744 return;
3745
b95234c8
PB		 3746 /* If a previous notification has sent the IPI, nothing to do. */
3747 if (pi_test_and_set_on(&vmx->pi_desc))
3748 return;
3749
06a5524f 3750 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ		 3751 kvm_vcpu_kick(vcpu);
3752}
3753
a3a8ff8e
NHE		 3754/*
3755 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3756 * will not change in the lifetime of the guest.
3757 * Note that host-state that does change is set elsewhere. E.g., host-state
3758 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3759 */
97b7ead3 3760void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3761{
3762 u32 low32, high32;
3763 unsigned long tmpl;
d6e41f11 3764 unsigned long cr0, cr3, cr4;
a3a8ff8e 3765
04ac88ab
AL		 3766 cr0 = read_cr0();
3767 WARN_ON(cr0 & X86_CR0_TS);
3768 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3769
3770 /*
3771 * Save the most likely value for this task's CR3 in the VMCS.
3772 * We can't use __get_current_cr3_fast() because we're not atomic.
3773 */
6c690ee1 3774 cr3 = __read_cr3();
d6e41f11 3775 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3776 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3777
d974baa3 3778 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3779 cr4 = cr4_read_shadow();
d974baa3 3780 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3781 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3782
a3a8ff8e 3783 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3784#ifdef CONFIG_X86_64
3785 /*
3786 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3787 * vmx_prepare_switch_to_host(), in case userspace uses
3788 * the null selectors too (the expected case).
b2da15ac
AK		 3789 */
3790 vmcs_write16(HOST_DS_SELECTOR, 0);
3791 vmcs_write16(HOST_ES_SELECTOR, 0);
3792#else
a3a8ff8e
NHE		 3793 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3794 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3795#endif
a3a8ff8e
NHE		 3796 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3797 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3798
2342080c 3799 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
a3a8ff8e 3800
453eafbe 3801 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3802
3803 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3804 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3805 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3806 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3807
3808 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3809 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3810 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3811 }
5a5e8a15 3812
c73da3fc 3813 if (cpu_has_load_ia32_efer())
5a5e8a15 3814 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3815}
3816
97b7ead3 3817void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3818{
3819 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3820 if (enable_ept)
3821 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3822 if (is_guest_mode(&vmx->vcpu))
3823 vmx->vcpu.arch.cr4_guest_owned_bits &=
3824 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3825 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3826}
3827
01e439be
YZ		 3828static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3829{
3830 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3831
d62caabb 3832 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3833 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3834
3835 if (!enable_vnmi)
3836 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3837
64672c95
YJ		 3838 /* Enable the preemption timer dynamically */
3839 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 3840 return pin_based_exec_ctrl;
3841}
3842
d62caabb
AS		 3843static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3844{
3845 struct vcpu_vmx *vmx = to_vmx(vcpu);
3846
3847 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3848 if (cpu_has_secondary_exec_ctrls()) {
3849 if (kvm_vcpu_apicv_active(vcpu))
3850 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
3851 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3852 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3853 else
3854 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
3855 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3856 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3857 }
3858
3859 if (cpu_has_vmx_msr_bitmap())
904e14fb 3860 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3861}
3862
89b0c9f5
SC		 3863u32 vmx_exec_control(struct vcpu_vmx *vmx)
3864{
3865 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3866
3867 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3868 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3869
3870 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3871 exec_control &= ~CPU_BASED_TPR_SHADOW;
3872#ifdef CONFIG_X86_64
3873 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3874 CPU_BASED_CR8_LOAD_EXITING;
3875#endif
3876 }
3877 if (!enable_ept)
3878 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3879 CPU_BASED_CR3_LOAD_EXITING |
3880 CPU_BASED_INVLPG_EXITING;
3881 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3882 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3883 CPU_BASED_MONITOR_EXITING);
3884 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3885 exec_control &= ~CPU_BASED_HLT_EXITING;
3886 return exec_control;
3887}
3888
3889
80154d77 3890static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 3891{
80154d77
PB		 3892 struct kvm_vcpu *vcpu = &vmx->vcpu;
3893
bf8179a0 3894 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 3895
f99e3daf
CP		 3896 if (pt_mode == PT_MODE_SYSTEM)
3897 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 3898 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 3899 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3900 if (vmx->vpid == 0)
3901 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3902 if (!enable_ept) {
3903 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3904 enable_unrestricted_guest = 0;
3905 }
3906 if (!enable_unrestricted_guest)
3907 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 3908 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 3909 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 3910 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 3911 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3912 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 3913 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 3914
3915 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3916 * in vmx_set_cr4. */
3917 exec_control &= ~SECONDARY_EXEC_DESC;
3918
abc4fc58
AG		 3919 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3920 (handle_vmptrld).
3921 We can NOT enable shadow_vmcs here because we don't have yet
3922 a current VMCS12
3923 */
3924 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 3925
3926 if (!enable_pml)
3927 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 3928
3db13480
PB		 3929 if (vmx_xsaves_supported()) {
3930 /* Exposing XSAVES only when XSAVE is exposed */
3931 bool xsaves_enabled =
3932 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3933 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3934
3935 if (!xsaves_enabled)
3936 exec_control &= ~SECONDARY_EXEC_XSAVES;
3937
3938 if (nested) {
3939 if (xsaves_enabled)
6677f3da 3940 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 3941 SECONDARY_EXEC_XSAVES;
3942 else
6677f3da 3943 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 3944 ~SECONDARY_EXEC_XSAVES;
3945 }
3946 }
3947
80154d77
PB		 3948 if (vmx_rdtscp_supported()) {
3949 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3950 if (!rdtscp_enabled)
3951 exec_control &= ~SECONDARY_EXEC_RDTSCP;
3952
3953 if (nested) {
3954 if (rdtscp_enabled)
6677f3da 3955 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3956 SECONDARY_EXEC_RDTSCP;
3957 else
6677f3da 3958 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3959 ~SECONDARY_EXEC_RDTSCP;
3960 }
3961 }
3962
3963 if (vmx_invpcid_supported()) {
3964 /* Exposing INVPCID only when PCID is exposed */
3965 bool invpcid_enabled =
3966 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
3967 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
3968
3969 if (!invpcid_enabled) {
3970 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3971 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
3972 }
3973
3974 if (nested) {
3975 if (invpcid_enabled)
6677f3da 3976 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3977 SECONDARY_EXEC_ENABLE_INVPCID;
3978 else
6677f3da 3979 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3980 ~SECONDARY_EXEC_ENABLE_INVPCID;
3981 }
3982 }
3983
45ec368c
JM		 3984 if (vmx_rdrand_supported()) {
3985 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
3986 if (rdrand_enabled)
736fdf72 3987 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3988
3989 if (nested) {
3990 if (rdrand_enabled)
6677f3da 3991 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 3992 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 3993 else
6677f3da 3994 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 3995 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3996 }
3997 }
3998
75f4fc8d
JM		 3999 if (vmx_rdseed_supported()) {
4000 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4001 if (rdseed_enabled)
736fdf72 4002 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4003
4004 if (nested) {
4005 if (rdseed_enabled)
6677f3da 4006 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4007 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 4008 else
6677f3da 4009 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4010 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4011 }
4012 }
4013
80154d77 4014 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 4015}
4016
ce88decf
XG		 4017static void ept_set_mmio_spte_mask(void)
4018{
4019 /*
4020 * EPT Misconfigurations can be generated if the value of bits 2:0
4021 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 4022 */
dcdca5fe
PF		 4023 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4024 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG		 4025}
4026
f53cd63c 4027#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 4028
944c3464
SC		 4029/*
4030 * Sets up the vmcs for emulated real mode.
4031 */
4032static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4033{
4034 int i;
4035
4036 if (nested)
4037 nested_vmx_vcpu_setup();
4038
25c5f225 4039 if (cpu_has_vmx_msr_bitmap())
904e14fb 4040 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4041
6aa8b732
AK		 4042 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4043
6aa8b732 4044 /* Control */
01e439be 4045 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 4046 vmx->hv_deadline_tsc = -1;
6e5d865c 4047
bf8179a0 4048 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4049
dfa169bb 4050 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4051 vmx_compute_secondary_exec_control(vmx);
bf8179a0 4052 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
80154d77 4053 vmx->secondary_exec_control);
dfa169bb 4054 }
f78e0e2e 4055
d62caabb 4056 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4057 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4058 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4059 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4060 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4061
4062 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4063
0bcf261c 4064 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4065 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4066 }
4067
b31c114b 4068 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4069 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4070 vmx->ple_window = ple_window;
4071 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4072 }
4073
c3707958
XG		 4074 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4075 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4076 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4077
9581d442
AK		 4078 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4079 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4080 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4081 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4082 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4083
2a499e49
BD		 4084 if (cpu_has_vmx_vmfunc())
4085 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4086
2cc51560
ED		 4087 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4088 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4089 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4090 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4091 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4092
74545705
RK		 4093 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4094 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4095
03916db9 4096 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4097 u32 index = vmx_msr_index[i];
4098 u32 data_low, data_high;
a2fa3e9f 4099 int j = vmx->nmsrs;
6aa8b732
AK		 4100
4101 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4102 continue;
432bd6cb
AK		 4103 if (wrmsr_safe(index, data_low, data_high) < 0)
4104 continue;
26bb0981
AK		 4105 vmx->guest_msrs[j].index = i;
4106 vmx->guest_msrs[j].data = 0;
d5696725 4107 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4108 ++vmx->nmsrs;
6aa8b732 4109 }
6aa8b732 4110
c73da3fc 4111 vm_exit_controls_init(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4112
4113 /* 22.2.1, 20.8.1 */
c73da3fc 4114 vm_entry_controls_init(vmx, vmx_vmentry_ctrl());
1c3d14fe 4115
bd7e5b08
PB		 4116 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4117 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4118
bf8179a0 4119 set_cr4_guest_host_mask(vmx);
e00c8cf2 4120
f53cd63c
WL		 4121 if (vmx_xsaves_supported())
4122 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4123
4e59516a 4124 if (enable_pml) {
4e59516a
PF		 4125 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4126 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4127 }
0b665d30
SC		 4128
4129 if (cpu_has_vmx_encls_vmexit())
4130 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4131
4132 if (pt_mode == PT_MODE_HOST_GUEST) {
4133 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4134 /* Bit[6~0] are forced to 1, writes are ignored. */
4135 vmx->pt_desc.guest.output_mask = 0x7F;
4136 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4137 }
e00c8cf2
AK		 4138}
4139
d28bc9dd 4140static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4141{
4142 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4143 struct msr_data apic_base_msr;
d28bc9dd 4144 u64 cr0;
e00c8cf2 4145
7ffd92c5 4146 vmx->rmode.vm86_active = 0;
d28b387f 4147 vmx->spec_ctrl = 0;
e00c8cf2 4148
518e7b94 4149 vcpu->arch.microcode_version = 0x100000000ULL;
ad312c7c 4150 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4151 kvm_set_cr8(vcpu, 0);
4152
4153 if (!init_event) {
4154 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4155 MSR_IA32_APICBASE_ENABLE;
4156 if (kvm_vcpu_is_reset_bsp(vcpu))
4157 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4158 apic_base_msr.host_initiated = true;
4159 kvm_set_apic_base(vcpu, &apic_base_msr);
4160 }
e00c8cf2 4161
2fb92db1
AK		 4162 vmx_segment_cache_clear(vmx);
4163
5706be0d 4164 seg_setup(VCPU_SREG_CS);
66450a21 4165 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4166 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4167
4168 seg_setup(VCPU_SREG_DS);
4169 seg_setup(VCPU_SREG_ES);
4170 seg_setup(VCPU_SREG_FS);
4171 seg_setup(VCPU_SREG_GS);
4172 seg_setup(VCPU_SREG_SS);
4173
4174 vmcs_write16(GUEST_TR_SELECTOR, 0);
4175 vmcs_writel(GUEST_TR_BASE, 0);
4176 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4177 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4178
4179 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4180 vmcs_writel(GUEST_LDTR_BASE, 0);
4181 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4182 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4183
d28bc9dd
NA		 4184 if (!init_event) {
4185 vmcs_write32(GUEST_SYSENTER_CS, 0);
4186 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4187 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4188 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4189 }
e00c8cf2 4190
c37c2873 4191 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4192 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4193
e00c8cf2
AK		 4194 vmcs_writel(GUEST_GDTR_BASE, 0);
4195 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4196
4197 vmcs_writel(GUEST_IDTR_BASE, 0);
4198 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4199
443381a8 4200 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4201 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4202 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4203 if (kvm_mpx_supported())
4204 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4205
e00c8cf2
AK		 4206 setup_msrs(vmx);
4207
6aa8b732
AK		 4208 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4209
d28bc9dd 4210 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4211 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4212 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4213 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4214 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4215 vmcs_write32(TPR_THRESHOLD, 0);
4216 }
4217
a73896cb 4218 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4219
2384d2b3
SY		 4220 if (vmx->vpid != 0)
4221 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4222
d28bc9dd 4223 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4224 vmx->vcpu.arch.cr0 = cr0;
f2463247 4225 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4226 vmx_set_cr4(vcpu, 0);
5690891b 4227 vmx_set_efer(vcpu, 0);
bd7e5b08 4228
d28bc9dd 4229 update_exception_bitmap(vcpu);
6aa8b732 4230
dd5f5341 4231 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4232 if (init_event)
4233 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4234}
4235
55d2375e 4236static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4237{
47c0152e
PB		 4238 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
4239 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK		 4240}
4241
c9a7953f 4242static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4243{
d02fcf50 4244 if (!enable_vnmi ||
8a1b4392 4245 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4246 enable_irq_window(vcpu);
4247 return;
4248 }
3b86cd99 4249
47c0152e
PB		 4250 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
4251 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK		 4252}
4253
66fd3f7f 4254static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4255{
9c8cba37 4256 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4257 uint32_t intr;
4258 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4259
229456fc 4260 trace_kvm_inj_virq(irq);
2714d1d3 4261
fa89a817 4262 ++vcpu->stat.irq_injections;
7ffd92c5 4263 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4264 int inc_eip = 0;
4265 if (vcpu->arch.interrupt.soft)
4266 inc_eip = vcpu->arch.event_exit_inst_len;
4267 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4268 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4269 return;
4270 }
66fd3f7f
GN		 4271 intr = irq | INTR_INFO_VALID_MASK;
4272 if (vcpu->arch.interrupt.soft) {
4273 intr |= INTR_TYPE_SOFT_INTR;
4274 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4275 vmx->vcpu.arch.event_exit_inst_len);
4276 } else
4277 intr |= INTR_TYPE_EXT_INTR;
4278 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4279
4280 vmx_clear_hlt(vcpu);
85f455f7
ED		 4281}
4282
f08864b4
SY		 4283static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4284{
66a5a347
JK		 4285 struct vcpu_vmx *vmx = to_vmx(vcpu);
4286
d02fcf50 4287 if (!enable_vnmi) {
8a1b4392
PB		 4288 /*
4289 * Tracking the NMI-blocked state in software is built upon
4290 * finding the next open IRQ window. This, in turn, depends on
4291 * well-behaving guests: They have to keep IRQs disabled at
4292 * least as long as the NMI handler runs. Otherwise we may
4293 * cause NMI nesting, maybe breaking the guest. But as this is
4294 * highly unlikely, we can live with the residual risk.
4295 */
4296 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4297 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4298 }
4299
4c4a6f79
PB		 4300 ++vcpu->stat.nmi_injections;
4301 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4302
7ffd92c5 4303 if (vmx->rmode.vm86_active) {
71f9833b 4304 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4305 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4306 return;
4307 }
c5a6d5f7 4308
f08864b4
SY		 4309 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4310 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4311
4312 vmx_clear_hlt(vcpu);
f08864b4
SY		 4313}
4314
97b7ead3 4315bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4316{
4c4a6f79
PB		 4317 struct vcpu_vmx *vmx = to_vmx(vcpu);
4318 bool masked;
4319
d02fcf50 4320 if (!enable_vnmi)
8a1b4392 4321 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4322 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4323 return false;
4c4a6f79
PB		 4324 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4325 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4326 return masked;
3cfc3092
JK		 4327}
4328
97b7ead3 4329void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4330{
4331 struct vcpu_vmx *vmx = to_vmx(vcpu);
4332
d02fcf50 4333 if (!enable_vnmi) {
8a1b4392
PB		 4334 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4335 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4336 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4337 }
4338 } else {
4339 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4340 if (masked)
4341 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4342 GUEST_INTR_STATE_NMI);
4343 else
4344 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4345 GUEST_INTR_STATE_NMI);
4346 }
3cfc3092
JK		 4347}
4348
2505dc9f
JK		 4349static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4350{
b6b8a145
JK		 4351 if (to_vmx(vcpu)->nested.nested_run_pending)
4352 return 0;
ea8ceb83 4353
d02fcf50 4354 if (!enable_vnmi &&
8a1b4392
PB		 4355 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4356 return 0;
4357
2505dc9f
JK		 4358 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4359 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4360 | GUEST_INTR_STATE_NMI));
4361}
4362
78646121
GN		 4363static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4364{
b6b8a145
JK		 4365 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4366 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4367 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4368 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4369}
4370
cbc94022
IE		 4371static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4372{
4373 int ret;
cbc94022 4374
f7eaeb0a
SC		 4375 if (enable_unrestricted_guest)
4376 return 0;
4377
1d8007bd
PB		 4378 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4379 PAGE_SIZE * 3);
cbc94022
IE		 4380 if (ret)
4381 return ret;
40bbb9d0 4382 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4383 return init_rmode_tss(kvm);
cbc94022
IE		 4384}
4385
2ac52ab8
SC		 4386static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4387{
40bbb9d0 4388 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4389 return 0;
4390}
4391
0ca1b4f4 4392static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4393{
77ab6db0 4394 switch (vec) {
77ab6db0 4395 case BP_VECTOR:
c573cd22
JK		 4396 /*
4397 * Update instruction length as we may reinject the exception
4398 * from user space while in guest debugging mode.
4399 */
4400 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4401 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4402 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4403 return false;
4404 /* fall through */
4405 case DB_VECTOR:
4406 if (vcpu->guest_debug &
4407 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4408 return false;
d0bfb940
JK		 4409 /* fall through */
4410 case DE_VECTOR:
77ab6db0
JK		 4411 case OF_VECTOR:
4412 case BR_VECTOR:
4413 case UD_VECTOR:
4414 case DF_VECTOR:
4415 case SS_VECTOR:
4416 case GP_VECTOR:
4417 case MF_VECTOR:
0ca1b4f4
GN		 4418 return true;
4419 break;
77ab6db0 4420 }
0ca1b4f4
GN		 4421 return false;
4422}
4423
4424static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4425 int vec, u32 err_code)
4426{
4427 /*
4428 * Instruction with address size override prefix opcode 0x67
4429 * Cause the #SS fault with 0 error code in VM86 mode.
4430 */
4431 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
0ce97a2b 4432 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
0ca1b4f4
GN		 4433 if (vcpu->arch.halt_request) {
4434 vcpu->arch.halt_request = 0;
5cb56059 4435 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4436 }
4437 return 1;
4438 }
4439 return 0;
4440 }
4441
4442 /*
4443 * Forward all other exceptions that are valid in real mode.
4444 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4445 * the required debugging infrastructure rework.
4446 */
4447 kvm_queue_exception(vcpu, vec);
4448 return 1;
6aa8b732
AK		 4449}
4450
a0861c02
AK		 4451/*
4452 * Trigger machine check on the host. We assume all the MSRs are already set up
4453 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4454 * We pass a fake environment to the machine check handler because we want
4455 * the guest to be always treated like user space, no matter what context
4456 * it used internally.
4457 */
4458static void kvm_machine_check(void)
4459{
4460#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4461 struct pt_regs regs = {
4462 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4463 .flags = X86_EFLAGS_IF,
4464 };
4465
4466 do_machine_check(&regs, 0);
4467#endif
4468}
4469
851ba692 4470static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02 4471{
95b5a48c 4472 /* handled by vmx_vcpu_run() */
a0861c02
AK		 4473 return 1;
4474}
4475
95b5a48c 4476static int handle_exception_nmi(struct kvm_vcpu *vcpu)
6aa8b732 4477{
1155f76a 4478 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4479 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4480 u32 intr_info, ex_no, error_code;
42dbaa5a 4481 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4482 u32 vect_info;
4483 enum emulation_result er;
4484
1155f76a 4485 vect_info = vmx->idt_vectoring_info;
88786475 4486 intr_info = vmx->exit_intr_info;
6aa8b732 4487
2ea72039 4488 if (is_machine_check(intr_info) || is_nmi(intr_info))
95b5a48c 4489 return 1; /* handled by handle_exception_nmi_irqoff() */
2ab455cc 4490
082d06ed
WL		 4491 if (is_invalid_opcode(intr_info))
4492 return handle_ud(vcpu);
7aa81cc0 4493
6aa8b732 4494 error_code = 0;
2e11384c 4495 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4496 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4497
9e869480
LA		 4498 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4499 WARN_ON_ONCE(!enable_vmware_backdoor);
0ce97a2b 4500 er = kvm_emulate_instruction(vcpu,
9e869480
LA		 4501 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
4502 if (er == EMULATE_USER_EXIT)
4503 return 0;
4504 else if (er != EMULATE_DONE)
4505 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4506 return 1;
4507 }
4508
bf4ca23e
XG		 4509 /*
4510 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4511 * MMIO, it is better to report an internal error.
4512 * See the comments in vmx_handle_exit.
4513 */
4514 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4515 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4516 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4517 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4518 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4519 vcpu->run->internal.data[0] = vect_info;
4520 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4521 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4522 return 0;
4523 }
4524
6aa8b732
AK		 4525 if (is_page_fault(intr_info)) {
4526 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4527 /* EPT won't cause page fault directly */
4528 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4529 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4530 }
4531
d0bfb940 4532 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4533
4534 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4535 return handle_rmode_exception(vcpu, ex_no, error_code);
4536
42dbaa5a 4537 switch (ex_no) {
54a20552
EN		 4538 case AC_VECTOR:
4539 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4540 return 1;
42dbaa5a
JK		 4541 case DB_VECTOR:
4542 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4543 if (!(vcpu->guest_debug &
4544 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1fc5d194 4545 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4546 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4547 if (is_icebp(intr_info))
fd2a445a
HD		 4548 skip_emulated_instruction(vcpu);
4549
42dbaa5a
JK		 4550 kvm_queue_exception(vcpu, DB_VECTOR);
4551 return 1;
4552 }
4553 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4554 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4555 /* fall through */
4556 case BP_VECTOR:
c573cd22
JK		 4557 /*
4558 * Update instruction length as we may reinject #BP from
4559 * user space while in guest debugging mode. Reading it for
4560 * #DB as well causes no harm, it is not used in that case.
4561 */
4562 vmx->vcpu.arch.event_exit_inst_len =
4563 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4564 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4565 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4566 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4567 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4568 break;
4569 default:
d0bfb940
JK		 4570 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4571 kvm_run->ex.exception = ex_no;
4572 kvm_run->ex.error_code = error_code;
42dbaa5a 4573 break;
6aa8b732 4574 }
6aa8b732
AK		 4575 return 0;
4576}
4577
851ba692 4578static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4579{
1165f5fe 4580 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4581 return 1;
4582}
4583
851ba692 4584static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4585{
851ba692 4586 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4587 vcpu->mmio_needed = 0;
988ad74f
AK		 4588 return 0;
4589}
6aa8b732 4590
851ba692 4591static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4592{
bfdaab09 4593 unsigned long exit_qualification;
dca7f128 4594 int size, in, string;
039576c0 4595 unsigned port;
6aa8b732 4596
bfdaab09 4597 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4598 string = (exit_qualification & 16) != 0;
e70669ab 4599
cf8f70bf 4600 ++vcpu->stat.io_exits;
e70669ab 4601
432baf60 4602 if (string)
0ce97a2b 4603 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4604
cf8f70bf
GN		 4605 port = exit_qualification >> 16;
4606 size = (exit_qualification & 7) + 1;
432baf60 4607 in = (exit_qualification & 8) != 0;
cf8f70bf 4608
dca7f128 4609 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4610}
4611
102d8325
IM		 4612static void
4613vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4614{
4615 /*
4616 * Patch in the VMCALL instruction:
4617 */
4618 hypercall[0] = 0x0f;
4619 hypercall[1] = 0x01;
4620 hypercall[2] = 0xc1;
102d8325
IM		 4621}
4622
0fa06071 4623/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4624static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4625{
eeadf9e7 4626 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4627 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4628 unsigned long orig_val = val;
4629
eeadf9e7
NHE		 4630 /*
4631 * We get here when L2 changed cr0 in a way that did not change
4632 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4633 * but did change L0 shadowed bits. So we first calculate the
4634 * effective cr0 value that L1 would like to write into the
4635 * hardware. It consists of the L2-owned bits from the new
4636 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4637 */
1a0d74e6
JK		 4638 val = (val & ~vmcs12->cr0_guest_host_mask) |
4639 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4640
3899152c 4641 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4642 return 1;
1a0d74e6
JK		 4643
4644 if (kvm_set_cr0(vcpu, val))
4645 return 1;
4646 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4647 return 0;
1a0d74e6
JK		 4648 } else {
4649 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4650 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4651 return 1;
3899152c 4652
eeadf9e7 4653 return kvm_set_cr0(vcpu, val);
1a0d74e6 4654 }
eeadf9e7
NHE		 4655}
4656
4657static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4658{
4659 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4660 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4661 unsigned long orig_val = val;
4662
4663 /* analogously to handle_set_cr0 */
4664 val = (val & ~vmcs12->cr4_guest_host_mask) |
4665 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4666 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4667 return 1;
1a0d74e6 4668 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4669 return 0;
4670 } else
4671 return kvm_set_cr4(vcpu, val);
4672}
4673
0367f205
PB		 4674static int handle_desc(struct kvm_vcpu *vcpu)
4675{
4676 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
0ce97a2b 4677 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
0367f205
PB		 4678}
4679
851ba692 4680static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4681{
229456fc 4682 unsigned long exit_qualification, val;
6aa8b732
AK		 4683 int cr;
4684 int reg;
49a9b07e 4685 int err;
6affcbed 4686 int ret;
6aa8b732 4687
bfdaab09 4688 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4689 cr = exit_qualification & 15;
4690 reg = (exit_qualification >> 8) & 15;
4691 switch ((exit_qualification >> 4) & 3) {
4692 case 0: /* mov to cr */
1e32c079 4693 val = kvm_register_readl(vcpu, reg);
229456fc 4694 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4695 switch (cr) {
4696 case 0:
eeadf9e7 4697 err = handle_set_cr0(vcpu, val);
6affcbed 4698 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4699 case 3:
e1de91cc 4700 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4701 err = kvm_set_cr3(vcpu, val);
6affcbed 4702 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4703 case 4:
eeadf9e7 4704 err = handle_set_cr4(vcpu, val);
6affcbed 4705 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4706 case 8: {
4707 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4708 u8 cr8 = (u8)val;
eea1cff9 4709 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4710 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4711 if (lapic_in_kernel(vcpu))
6affcbed 4712 return ret;
0a5fff19 4713 if (cr8_prev <= cr8)
6affcbed
KH		 4714 return ret;
4715 /*
4716 * TODO: we might be squashing a
4717 * KVM_GUESTDBG_SINGLESTEP-triggered
4718 * KVM_EXIT_DEBUG here.
4719 */
851ba692 4720 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4721 return 0;
4722 }
4b8073e4 4723 }
6aa8b732 4724 break;
25c4c276 4725 case 2: /* clts */
bd7e5b08
PB		 4726 WARN_ONCE(1, "Guest should always own CR0.TS");
4727 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4728 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4729 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4730 case 1: /*mov from cr*/
4731 switch (cr) {
4732 case 3:
e1de91cc 4733 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4734 val = kvm_read_cr3(vcpu);
4735 kvm_register_write(vcpu, reg, val);
4736 trace_kvm_cr_read(cr, val);
6affcbed 4737 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4738 case 8:
229456fc
MT		 4739 val = kvm_get_cr8(vcpu);
4740 kvm_register_write(vcpu, reg, val);
4741 trace_kvm_cr_read(cr, val);
6affcbed 4742 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4743 }
4744 break;
4745 case 3: /* lmsw */
a1f83a74 4746 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4747 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4748 kvm_lmsw(vcpu, val);
6aa8b732 4749
6affcbed 4750 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4751 default:
4752 break;
4753 }
851ba692 4754 vcpu->run->exit_reason = 0;
a737f256 4755 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4756 (int)(exit_qualification >> 4) & 3, cr);
4757 return 0;
4758}
4759
851ba692 4760static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4761{
bfdaab09 4762 unsigned long exit_qualification;
16f8a6f9
NA		 4763 int dr, dr7, reg;
4764
4765 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4766 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4767
4768 /* First, if DR does not exist, trigger UD */
4769 if (!kvm_require_dr(vcpu, dr))
4770 return 1;
6aa8b732 4771
f2483415 4772 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4773 if (!kvm_require_cpl(vcpu, 0))
4774 return 1;
16f8a6f9
NA		 4775 dr7 = vmcs_readl(GUEST_DR7);
4776 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4777 /*
4778 * As the vm-exit takes precedence over the debug trap, we
4779 * need to emulate the latter, either for the host or the
4780 * guest debugging itself.
4781 */
4782 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4783 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4784 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4785 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4786 vcpu->run->debug.arch.exception = DB_VECTOR;
4787 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4788 return 0;
4789 } else {
1fc5d194 4790 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4791 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4792 kvm_queue_exception(vcpu, DB_VECTOR);
4793 return 1;
4794 }
4795 }
4796
81908bf4 4797 if (vcpu->guest_debug == 0) {
8f22372f
PB		 4798 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4799 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4800
4801 /*
4802 * No more DR vmexits; force a reload of the debug registers
4803 * and reenter on this instruction. The next vmexit will
4804 * retrieve the full state of the debug registers.
4805 */
4806 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4807 return 1;
4808 }
4809
42dbaa5a
JK		 4810 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4811 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4812 unsigned long val;
4c4d563b
JK		 4813
4814 if (kvm_get_dr(vcpu, dr, &val))
4815 return 1;
4816 kvm_register_write(vcpu, reg, val);
020df079 4817 } else
5777392e 4818 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4819 return 1;
4820
6affcbed 4821 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4822}
4823
73aaf249
JK		 4824static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4825{
4826 return vcpu->arch.dr6;
4827}
4828
4829static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4830{
4831}
4832
81908bf4
PB		 4833static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4834{
81908bf4
PB		 4835 get_debugreg(vcpu->arch.db[0], 0);
4836 get_debugreg(vcpu->arch.db[1], 1);
4837 get_debugreg(vcpu->arch.db[2], 2);
4838 get_debugreg(vcpu->arch.db[3], 3);
4839 get_debugreg(vcpu->arch.dr6, 6);
4840 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4841
4842 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 4843 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4844}
4845
020df079
GN		 4846static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4847{
4848 vmcs_writel(GUEST_DR7, val);
4849}
4850
851ba692 4851static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4852{
6a908b62 4853 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK		 4854}
4855
851ba692 4856static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4857{
2b3eaf81 4858 u32 ecx = kvm_rcx_read(vcpu);
609e36d3 4859 struct msr_data msr_info;
6aa8b732 4860
609e36d3
PB		 4861 msr_info.index = ecx;
4862 msr_info.host_initiated = false;
4863 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 4864 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4865 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4866 return 1;
4867 }
4868
609e36d3 4869 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 4870
2b3eaf81
SC		 4871 kvm_rax_write(vcpu, msr_info.data & -1u);
4872 kvm_rdx_write(vcpu, (msr_info.data >> 32) & -1u);
6affcbed 4873 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4874}
4875
851ba692 4876static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4877{
8fe8ab46 4878 struct msr_data msr;
2b3eaf81
SC		 4879 u32 ecx = kvm_rcx_read(vcpu);
4880 u64 data = kvm_read_edx_eax(vcpu);
6aa8b732 4881
8fe8ab46
WA		 4882 msr.data = data;
4883 msr.index = ecx;
4884 msr.host_initiated = false;
854e8bb1 4885 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 4886 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4887 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4888 return 1;
4889 }
4890
59200273 4891 trace_kvm_msr_write(ecx, data);
6affcbed 4892 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4893}
4894
851ba692 4895static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4896{
eb90f341 4897 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4898 return 1;
4899}
4900
851ba692 4901static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4902{
47c0152e
PB		 4903 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4904 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 4905
3842d135
AK		 4906 kvm_make_request(KVM_REQ_EVENT, vcpu);
4907
a26bf12a 4908 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4909 return 1;
4910}
4911
851ba692 4912static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 4913{
d3bef15f 4914 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4915}
4916
851ba692 4917static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4918{
0d9c055e 4919 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 4920}
4921
ec25d5e6
GN		 4922static int handle_invd(struct kvm_vcpu *vcpu)
4923{
0ce97a2b 4924 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4925}
4926
851ba692 4927static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4928{
f9c617f6 4929 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4930
4931 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 4932 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 4933}
4934
fee84b07
AK		 4935static int handle_rdpmc(struct kvm_vcpu *vcpu)
4936{
4937 int err;
4938
4939 err = kvm_rdpmc(vcpu);
6affcbed 4940 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 4941}
4942
851ba692 4943static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 4944{
6affcbed 4945 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4946}
4947
2acf923e
DC		 4948static int handle_xsetbv(struct kvm_vcpu *vcpu)
4949{
4950 u64 new_bv = kvm_read_edx_eax(vcpu);
de3cd117 4951 u32 index = kvm_rcx_read(vcpu);
2acf923e
DC		 4952
4953 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 4954 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 4955 return 1;
4956}
4957
f53cd63c
WL		 4958static int handle_xsaves(struct kvm_vcpu *vcpu)
4959{
6affcbed 4960 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4961 WARN(1, "this should never happen\n");
4962 return 1;
4963}
4964
4965static int handle_xrstors(struct kvm_vcpu *vcpu)
4966{
6affcbed 4967 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4968 WARN(1, "this should never happen\n");
4969 return 1;
4970}
4971
851ba692 4972static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4973{
58fbbf26
KT		 4974 if (likely(fasteoi)) {
4975 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4976 int access_type, offset;
4977
4978 access_type = exit_qualification & APIC_ACCESS_TYPE;
4979 offset = exit_qualification & APIC_ACCESS_OFFSET;
4980 /*
4981 * Sane guest uses MOV to write EOI, with written value
4982 * not cared. So make a short-circuit here by avoiding
4983 * heavy instruction emulation.
4984 */
4985 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4986 (offset == APIC_EOI)) {
4987 kvm_lapic_set_eoi(vcpu);
6affcbed 4988 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 4989 }
4990 }
0ce97a2b 4991 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4992}
4993
c7c9c56c
YZ		 4994static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4995{
4996 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4997 int vector = exit_qualification & 0xff;
4998
4999 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5000 kvm_apic_set_eoi_accelerated(vcpu, vector);
5001 return 1;
5002}
5003
83d4c286
YZ		 5004static int handle_apic_write(struct kvm_vcpu *vcpu)
5005{
5006 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5007 u32 offset = exit_qualification & 0xfff;
5008
5009 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5010 kvm_apic_write_nodecode(vcpu, offset);
5011 return 1;
5012}
5013
851ba692 5014static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5015{
60637aac 5016 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5017 unsigned long exit_qualification;
e269fb21
JK		 5018 bool has_error_code = false;
5019 u32 error_code = 0;
37817f29 5020 u16 tss_selector;
7f3d35fd 5021 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5022
5023 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5024 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5025 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5026
5027 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5028
5029 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5030 if (reason == TASK_SWITCH_GATE && idt_v) {
5031 switch (type) {
5032 case INTR_TYPE_NMI_INTR:
5033 vcpu->arch.nmi_injected = false;
654f06fc 5034 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5035 break;
5036 case INTR_TYPE_EXT_INTR:
66fd3f7f 5037 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5038 kvm_clear_interrupt_queue(vcpu);
5039 break;
5040 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5041 if (vmx->idt_vectoring_info &
5042 VECTORING_INFO_DELIVER_CODE_MASK) {
5043 has_error_code = true;
5044 error_code =
5045 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5046 }
5047 /* fall through */
64a7ec06
GN		 5048 case INTR_TYPE_SOFT_EXCEPTION:
5049 kvm_clear_exception_queue(vcpu);
5050 break;
5051 default:
5052 break;
5053 }
60637aac 5054 }
37817f29
IE		 5055 tss_selector = exit_qualification;
5056
64a7ec06
GN		 5057 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5058 type != INTR_TYPE_EXT_INTR &&
5059 type != INTR_TYPE_NMI_INTR))
5060 skip_emulated_instruction(vcpu);
5061
7f3d35fd
KW		 5062 if (kvm_task_switch(vcpu, tss_selector,
5063 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5064 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5065 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5066 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5067 vcpu->run->internal.ndata = 0;
42dbaa5a 5068 return 0;
acb54517 5069 }
42dbaa5a 5070
42dbaa5a
JK		 5071 /*
5072 * TODO: What about debug traps on tss switch?
5073 * Are we supposed to inject them and update dr6?
5074 */
5075
5076 return 1;
37817f29
IE		 5077}
5078
851ba692 5079static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5080{
f9c617f6 5081 unsigned long exit_qualification;
1439442c 5082 gpa_t gpa;
eebed243 5083 u64 error_code;
1439442c 5084
f9c617f6 5085 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5086
0be9c7a8
GN		 5087 /*
5088 * EPT violation happened while executing iret from NMI,
5089 * "blocked by NMI" bit has to be set before next VM entry.
5090 * There are errata that may cause this bit to not be set:
5091 * AAK134, BY25.
5092 */
bcd1c294 5093 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5094 enable_vnmi &&
bcd1c294 5095 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5096 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5097
1439442c 5098 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5099 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5100
27959a44 5101 /* Is it a read fault? */
ab22a473 5102 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5103 ? PFERR_USER_MASK : 0;
5104 /* Is it a write fault? */
ab22a473 5105 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5106 ? PFERR_WRITE_MASK : 0;
5107 /* Is it a fetch fault? */
ab22a473 5108 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5109 ? PFERR_FETCH_MASK : 0;
5110 /* ept page table entry is present? */
5111 error_code |= (exit_qualification &
5112 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5113 EPT_VIOLATION_EXECUTABLE))
5114 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5115
eebed243
PB		 5116 error_code |= (exit_qualification & 0x100) != 0 ?
5117 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5118
25d92081 5119 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5120 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5121}
5122
851ba692 5123static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5124{
68f89400
MT		 5125 gpa_t gpa;
5126
9034e6e8
PB		 5127 /*
5128 * A nested guest cannot optimize MMIO vmexits, because we have an
5129 * nGPA here instead of the required GPA.
5130 */
68f89400 5131 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5132 if (!is_guest_mode(vcpu) &&
5133 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5134 trace_kvm_fast_mmio(gpa);
d391f120
VK		 5135 /*
5136 * Doing kvm_skip_emulated_instruction() depends on undefined
5137 * behavior: Intel's manual doesn't mandate
5138 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5139 * occurs and while on real hardware it was observed to be set,
5140 * other hypervisors (namely Hyper-V) don't set it, we end up
5141 * advancing IP with some random value. Disable fast mmio when
5142 * running nested and keep it for real hardware in hope that
5143 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5144 */
5145 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
5146 return kvm_skip_emulated_instruction(vcpu);
5147 else
0ce97a2b 5148 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
c4409905 5149 EMULATE_DONE;
68c3b4d1 5150 }
68f89400 5151
c75d0edc 5152 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5153}
5154
851ba692 5155static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5156{
d02fcf50 5157 WARN_ON_ONCE(!enable_vnmi);
47c0152e
PB		 5158 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5159 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 5160 ++vcpu->stat.nmi_window_exits;
3842d135 5161 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5162
5163 return 1;
5164}
5165
80ced186 5166static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5167{
8b3079a5
AK		 5168 struct vcpu_vmx *vmx = to_vmx(vcpu);
5169 enum emulation_result err = EMULATE_DONE;
80ced186 5170 int ret = 1;
49e9d557
AK		 5171 u32 cpu_exec_ctrl;
5172 bool intr_window_requested;
b8405c18 5173 unsigned count = 130;
49e9d557 5174
2bb8cafe
SC		 5175 /*
5176 * We should never reach the point where we are emulating L2
5177 * due to invalid guest state as that means we incorrectly
5178 * allowed a nested VMEntry with an invalid vmcs12.
5179 */
5180 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5181
49e9d557
AK		 5182 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5183 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5184
98eb2f8b 5185 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5186 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5187 return handle_interrupt_window(&vmx->vcpu);
5188
72875d8a 5189 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5190 return 1;
5191
0ce97a2b 5192 err = kvm_emulate_instruction(vcpu, 0);
ea953ef0 5193
ac0a48c3 5194 if (err == EMULATE_USER_EXIT) {
94452b9e 5195 ++vcpu->stat.mmio_exits;
80ced186
MG		 5196 ret = 0;
5197 goto out;
5198 }
1d5a4d9b 5199
add5ff7a
SC		 5200 if (err != EMULATE_DONE)
5201 goto emulation_error;
5202
5203 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5204 vcpu->arch.exception.pending)
5205 goto emulation_error;
ea953ef0 5206
8d76c49e
GN		 5207 if (vcpu->arch.halt_request) {
5208 vcpu->arch.halt_request = 0;
5cb56059 5209 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5210 goto out;
5211 }
5212
ea953ef0 5213 if (signal_pending(current))
80ced186 5214 goto out;
ea953ef0
MG		 5215 if (need_resched())
5216 schedule();
5217 }
5218
80ced186
MG		 5219out:
5220 return ret;
b4a2d31d 5221
add5ff7a
SC		 5222emulation_error:
5223 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5224 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5225 vcpu->run->internal.ndata = 0;
5226 return 0;
b4a2d31d
RK		 5227}
5228
5229static void grow_ple_window(struct kvm_vcpu *vcpu)
5230{
5231 struct vcpu_vmx *vmx = to_vmx(vcpu);
5232 int old = vmx->ple_window;
5233
c8e88717
BM		 5234 vmx->ple_window = __grow_ple_window(old, ple_window,
5235 ple_window_grow,
5236 ple_window_max);
b4a2d31d
RK		 5237
5238 if (vmx->ple_window != old)
5239 vmx->ple_window_dirty = true;
7b46268d
RK		 5240
5241 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5242}
5243
5244static void shrink_ple_window(struct kvm_vcpu *vcpu)
5245{
5246 struct vcpu_vmx *vmx = to_vmx(vcpu);
5247 int old = vmx->ple_window;
5248
c8e88717
BM		 5249 vmx->ple_window = __shrink_ple_window(old, ple_window,
5250 ple_window_shrink,
5251 ple_window);
b4a2d31d
RK		 5252
5253 if (vmx->ple_window != old)
5254 vmx->ple_window_dirty = true;
7b46268d
RK		 5255
5256 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5257}
5258
bf9f6ac8
FW		 5259/*
5260 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5261 */
5262static void wakeup_handler(void)
5263{
5264 struct kvm_vcpu *vcpu;
5265 int cpu = smp_processor_id();
5266
5267 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5268 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5269 blocked_vcpu_list) {
5270 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5271
5272 if (pi_test_on(pi_desc) == 1)
5273 kvm_vcpu_kick(vcpu);
5274 }
5275 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5276}
5277
e01bca2f 5278static void vmx_enable_tdp(void)
f160c7b7
JS		 5279{
5280 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5281 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5282 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5283 0ull, VMX_EPT_EXECUTABLE_MASK,
5284 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5285 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5286
5287 ept_set_mmio_spte_mask();
5288 kvm_enable_tdp();
5289}
5290
4b8d54f9
ZE		 5291/*
5292 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5293 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5294 */
9fb41ba8 5295static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5296{
b31c114b 5297 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5298 grow_ple_window(vcpu);
5299
de63ad4c
LM		 5300 /*
5301 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5302 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5303 * never set PAUSE_EXITING and just set PLE if supported,
5304 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5305 */
5306 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5307 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5308}
5309
87c00572 5310static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5311{
6affcbed 5312 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5313}
5314
87c00572
GS		 5315static int handle_mwait(struct kvm_vcpu *vcpu)
5316{
5317 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5318 return handle_nop(vcpu);
5319}
5320
45ec368c
JM		 5321static int handle_invalid_op(struct kvm_vcpu *vcpu)
5322{
5323 kvm_queue_exception(vcpu, UD_VECTOR);
5324 return 1;
5325}
5326
5f3d45e7
MD		 5327static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5328{
5329 return 1;
5330}
5331
87c00572
GS		 5332static int handle_monitor(struct kvm_vcpu *vcpu)
5333{
5334 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5335 return handle_nop(vcpu);
5336}
5337
55d2375e 5338static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5339{
55d2375e
SC		 5340 u32 vmx_instruction_info;
5341 unsigned long type;
5342 bool pcid_enabled;
5343 gva_t gva;
5344 struct x86_exception e;
5345 unsigned i;
5346 unsigned long roots_to_free = 0;
5347 struct {
5348 u64 pcid;
5349 u64 gla;
5350 } operand;
f9eb4af6 5351
55d2375e 5352 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5353 kvm_queue_exception(vcpu, UD_VECTOR);
5354 return 1;
5355 }
5356
55d2375e
SC		 5357 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5358 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5359
5360 if (type > 3) {
5361 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5362 return 1;
5363 }
5364
55d2375e
SC		 5365 /* According to the Intel instruction reference, the memory operand
5366 * is read even if it isn't needed (e.g., for type==all)
5367 */
3573e22c 5368 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
fdb28619
EK		 5369 vmx_instruction_info, false,
5370 sizeof(operand), &gva))
3573e22c
BD		 5371 return 1;
5372
55d2375e 5373 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5374 kvm_inject_page_fault(vcpu, &e);
5375 return 1;
5376 }
5377
55d2375e
SC		 5378 if (operand.pcid >> 12 != 0) {
5379 kvm_inject_gp(vcpu, 0);
5380 return 1;
abfc52c6 5381 }
e29acc55 5382
55d2375e 5383 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5384
55d2375e
SC		 5385 switch (type) {
5386 case INVPCID_TYPE_INDIV_ADDR:
5387 if ((!pcid_enabled && (operand.pcid != 0)) ||
5388 is_noncanonical_address(operand.gla, vcpu)) {
5389 kvm_inject_gp(vcpu, 0);
5390 return 1;
5391 }
5392 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5393 return kvm_skip_emulated_instruction(vcpu);
61ada748 5394
55d2375e
SC		 5395 case INVPCID_TYPE_SINGLE_CTXT:
5396 if (!pcid_enabled && (operand.pcid != 0)) {
5397 kvm_inject_gp(vcpu, 0);
5398 return 1;
5399 }
e29acc55 5400
55d2375e
SC		 5401 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5402 kvm_mmu_sync_roots(vcpu);
5403 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5404 }
e29acc55 5405
55d2375e
SC		 5406 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5407 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5408 == operand.pcid)
5409 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5410
55d2375e
SC		 5411 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5412 /*
5413 * If neither the current cr3 nor any of the prev_roots use the
5414 * given PCID, then nothing needs to be done here because a
5415 * resync will happen anyway before switching to any other CR3.
5416 */
e29acc55 5417
55d2375e 5418 return kvm_skip_emulated_instruction(vcpu);
61ada748 5419
55d2375e
SC		 5420 case INVPCID_TYPE_ALL_NON_GLOBAL:
5421 /*
5422 * Currently, KVM doesn't mark global entries in the shadow
5423 * page tables, so a non-global flush just degenerates to a
5424 * global flush. If needed, we could optimize this later by
5425 * keeping track of global entries in shadow page tables.
5426 */
e29acc55 5427
55d2375e
SC		 5428 /* fall-through */
5429 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5430 kvm_mmu_unload(vcpu);
5431 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5432
55d2375e
SC		 5433 default:
5434 BUG(); /* We have already checked above that type <= 3 */
5435 }
e29acc55
JM		 5436}
5437
55d2375e 5438static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5439{
55d2375e 5440 unsigned long exit_qualification;
b3897a49 5441
55d2375e 5442 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5443
55d2375e 5444 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5445
5446 /*
55d2375e
SC		 5447 * PML buffer FULL happened while executing iret from NMI,
5448 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5449 */
55d2375e
SC		 5450 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5451 enable_vnmi &&
5452 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5453 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5454 GUEST_INTR_STATE_NMI);
e49fcb8b 5455
55d2375e
SC		 5456 /*
5457 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5458 * here.., and there's no userspace involvement needed for PML.
5459 */
ec378aee
NHE		 5460 return 1;
5461}
5462
55d2375e 5463static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5464{
55d2375e
SC		 5465 if (!to_vmx(vcpu)->req_immediate_exit)
5466 kvm_lapic_expired_hv_timer(vcpu);
5467 return 1;
8ca44e88
DM		 5468}
5469
55d2375e
SC		 5470/*
5471 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5472 * are overwritten by nested_vmx_setup() when nested=1.
5473 */
5474static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5475{
55d2375e
SC		 5476 kvm_queue_exception(vcpu, UD_VECTOR);
5477 return 1;
b8bbab92
VK		 5478}
5479
55d2375e 5480static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5481{
55d2375e
SC		 5482 /*
5483 * SGX virtualization is not yet supported. There is no software
5484 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5485 * to prevent the guest from executing ENCLS.
5486 */
5487 kvm_queue_exception(vcpu, UD_VECTOR);
5488 return 1;
e7953d7f
AG		 5489}
5490
ec378aee 5491/*
55d2375e
SC		 5492 * The exit handlers return 1 if the exit was handled fully and guest execution
5493 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5494 * to be done to userspace and return 0.
ec378aee 5495 */
55d2375e 5496static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
95b5a48c 5497 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
55d2375e
SC		 5498 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5499 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5500 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5501 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5502 [EXIT_REASON_CR_ACCESS] = handle_cr,
5503 [EXIT_REASON_DR_ACCESS] = handle_dr,
5504 [EXIT_REASON_CPUID] = handle_cpuid,
5505 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5506 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5507 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5508 [EXIT_REASON_HLT] = handle_halt,
5509 [EXIT_REASON_INVD] = handle_invd,
5510 [EXIT_REASON_INVLPG] = handle_invlpg,
5511 [EXIT_REASON_RDPMC] = handle_rdpmc,
5512 [EXIT_REASON_VMCALL] = handle_vmcall,
5513 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5514 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5515 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5516 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5517 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5518 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5519 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5520 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5521 [EXIT_REASON_VMON] = handle_vmx_instruction,
5522 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5523 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5524 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5525 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5526 [EXIT_REASON_WBINVD] = handle_wbinvd,
5527 [EXIT_REASON_XSETBV] = handle_xsetbv,
5528 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5529 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5530 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5531 [EXIT_REASON_LDTR_TR] = handle_desc,
5532 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5533 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5534 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5535 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5536 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5537 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5538 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5539 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5540 [EXIT_REASON_RDRAND] = handle_invalid_op,
5541 [EXIT_REASON_RDSEED] = handle_invalid_op,
5542 [EXIT_REASON_XSAVES] = handle_xsaves,
5543 [EXIT_REASON_XRSTORS] = handle_xrstors,
5544 [EXIT_REASON_PML_FULL] = handle_pml_full,
5545 [EXIT_REASON_INVPCID] = handle_invpcid,
5546 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5547 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5548 [EXIT_REASON_ENCLS] = handle_encls,
5549};
b8bbab92 5550
55d2375e
SC		 5551static const int kvm_vmx_max_exit_handlers =
5552 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5553
55d2375e 5554static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5555{
55d2375e
SC		 5556 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5557 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5558}
5559
55d2375e 5560static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5561{
55d2375e
SC		 5562 if (vmx->pml_pg) {
5563 __free_page(vmx->pml_pg);
5564 vmx->pml_pg = NULL;
b8bbab92 5565 }
27d6c865
NHE		 5566}
5567
55d2375e 5568static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5569{
55d2375e
SC		 5570 struct vcpu_vmx *vmx = to_vmx(vcpu);
5571 u64 *pml_buf;
5572 u16 pml_idx;
cd232ad0 5573
55d2375e 5574 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5575
55d2375e
SC		 5576 /* Do nothing if PML buffer is empty */
5577 if (pml_idx == (PML_ENTITY_NUM - 1))
5578 return;
cd232ad0 5579
55d2375e
SC		 5580 /* PML index always points to next available PML buffer entity */
5581 if (pml_idx >= PML_ENTITY_NUM)
5582 pml_idx = 0;
5583 else
5584 pml_idx++;
945679e3 5585
55d2375e
SC		 5586 pml_buf = page_address(vmx->pml_pg);
5587 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5588 u64 gpa;
945679e3 5589
55d2375e
SC		 5590 gpa = pml_buf[pml_idx];
5591 WARN_ON(gpa & (PAGE_SIZE - 1));
5592 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5593 }
5594
55d2375e
SC		 5595 /* reset PML index */
5596 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5597}
5598
f4160e45 5599/*
55d2375e
SC		 5600 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5601 * Called before reporting dirty_bitmap to userspace.
f4160e45 5602 */
55d2375e 5603static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5604{
55d2375e
SC		 5605 int i;
5606 struct kvm_vcpu *vcpu;
49f705c5 5607 /*
55d2375e
SC		 5608 * We only need to kick vcpu out of guest mode here, as PML buffer
5609 * is flushed at beginning of all VMEXITs, and it's obvious that only
5610 * vcpus running in guest are possible to have unflushed GPAs in PML
5611 * buffer.
49f705c5 5612 */
55d2375e
SC		 5613 kvm_for_each_vcpu(i, vcpu, kvm)
5614 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5615}
5616
55d2375e 5617static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5618{
55d2375e
SC		 5619 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5620 name, vmcs_read16(sel),
5621 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5622 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5623 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5624}
5625
55d2375e 5626static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5627{
55d2375e
SC		 5628 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5629 name, vmcs_read32(limit),
5630 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5631}
5632
69090810 5633void dump_vmcs(void)
63846663 5634{
6f2f8453
PB		 5635 u32 vmentry_ctl, vmexit_ctl;
5636 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5637 unsigned long cr4;
5638 u64 efer;
55d2375e 5639 int i, n;
63846663 5640
6f2f8453
PB		 5641 if (!dump_invalid_vmcs) {
5642 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5643 return;
5644 }
5645
5646 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5647 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5648 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5649 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5650 cr4 = vmcs_readl(GUEST_CR4);
5651 efer = vmcs_read64(GUEST_IA32_EFER);
5652 secondary_exec_control = 0;
55d2375e
SC		 5653 if (cpu_has_secondary_exec_ctrls())
5654 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5655
55d2375e
SC		 5656 pr_err("*** Guest State ***\n");
5657 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5658 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5659 vmcs_readl(CR0_GUEST_HOST_MASK));
5660 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5661 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5662 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5663 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5664 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5665 {
5666 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5667 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5668 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5669 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5670 }
55d2375e
SC		 5671 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5672 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5673 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5674 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5675 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5676 vmcs_readl(GUEST_SYSENTER_ESP),
5677 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5678 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5679 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5680 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5681 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5682 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5683 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5684 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5685 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5686 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5687 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5688 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5689 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5690 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5691 efer, vmcs_read64(GUEST_IA32_PAT));
5692 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5693 vmcs_read64(GUEST_IA32_DEBUGCTL),
5694 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5695 if (cpu_has_load_perf_global_ctrl() &&
5696 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5697 pr_err("PerfGlobCtl = 0x%016llx\n",
5698 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5699 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5700 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5701 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5702 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5703 vmcs_read32(GUEST_ACTIVITY_STATE));
5704 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5705 pr_err("InterruptStatus = %04x\n",
5706 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5707
55d2375e
SC		 5708 pr_err("*** Host State ***\n");
5709 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5710 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5711 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5712 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5713 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5714 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5715 vmcs_read16(HOST_TR_SELECTOR));
5716 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5717 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5718 vmcs_readl(HOST_TR_BASE));
5719 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5720 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5721 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5722 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5723 vmcs_readl(HOST_CR4));
5724 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5725 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5726 vmcs_read32(HOST_IA32_SYSENTER_CS),
5727 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5728 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5729 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5730 vmcs_read64(HOST_IA32_EFER),
5731 vmcs_read64(HOST_IA32_PAT));
5732 if (cpu_has_load_perf_global_ctrl() &&
5733 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5734 pr_err("PerfGlobCtl = 0x%016llx\n",
5735 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5736
55d2375e
SC		 5737 pr_err("*** Control State ***\n");
5738 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5739 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5740 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5741 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5742 vmcs_read32(EXCEPTION_BITMAP),
5743 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5744 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5745 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5746 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5747 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5748 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5749 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5750 vmcs_read32(VM_EXIT_INTR_INFO),
5751 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5752 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5753 pr_err(" reason=%08x qualification=%016lx\n",
5754 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5755 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5756 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5757 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5758 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5759 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5760 pr_err("TSC Multiplier = 0x%016llx\n",
5761 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5762 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5763 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5764 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5765 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5766 }
d6a85c32 5767 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9d609649
PB		 5768 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5769 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
d6a85c32 5770 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
9d609649 5771 }
55d2375e
SC		 5772 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5773 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5774 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5775 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5776 n = vmcs_read32(CR3_TARGET_COUNT);
5777 for (i = 0; i + 1 < n; i += 4)
5778 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5779 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5780 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5781 if (i < n)
5782 pr_err("CR3 target%u=%016lx\n",
5783 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5784 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5785 pr_err("PLE Gap=%08x Window=%08x\n",
5786 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5787 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5788 pr_err("Virtual processor ID = 0x%04x\n",
5789 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5790}
5791
55d2375e
SC		 5792/*
5793 * The guest has exited. See if we can fix it or if we need userspace
5794 * assistance.
5795 */
5796static int vmx_handle_exit(struct kvm_vcpu *vcpu)
ff651cb6 5797{
55d2375e
SC		 5798 struct vcpu_vmx *vmx = to_vmx(vcpu);
5799 u32 exit_reason = vmx->exit_reason;
5800 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5801
55d2375e 5802 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5803
55d2375e
SC		 5804 /*
5805 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5806 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5807 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5808 * mode as if vcpus is in root mode, the PML buffer must has been
5809 * flushed already.
5810 */
5811 if (enable_pml)
5812 vmx_flush_pml_buffer(vcpu);
1dc35dac 5813
55d2375e
SC		 5814 /* If guest state is invalid, start emulating */
5815 if (vmx->emulation_required)
5816 return handle_invalid_guest_state(vcpu);
1dc35dac 5817
55d2375e
SC		 5818 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5819 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5820
55d2375e
SC		 5821 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5822 dump_vmcs();
5823 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5824 vcpu->run->fail_entry.hardware_entry_failure_reason
5825 = exit_reason;
5826 return 0;
9ed38ffa
LP		 5827 }
5828
55d2375e
SC		 5829 if (unlikely(vmx->fail)) {
5830 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5831 vcpu->run->fail_entry.hardware_entry_failure_reason
5832 = vmcs_read32(VM_INSTRUCTION_ERROR);
5833 return 0;
5834 }
50c28f21 5835
55d2375e
SC		 5836 /*
5837 * Note:
5838 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5839 * delivery event since it indicates guest is accessing MMIO.
5840 * The vm-exit can be triggered again after return to guest that
5841 * will cause infinite loop.
5842 */
5843 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5844 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5845 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5846 exit_reason != EXIT_REASON_PML_FULL &&
5847 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5848 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5849 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5850 vcpu->run->internal.ndata = 3;
5851 vcpu->run->internal.data[0] = vectoring_info;
5852 vcpu->run->internal.data[1] = exit_reason;
5853 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5854 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5855 vcpu->run->internal.ndata++;
5856 vcpu->run->internal.data[3] =
5857 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5858 }
5859 return 0;
5860 }
50c28f21 5861
55d2375e
SC		 5862 if (unlikely(!enable_vnmi &&
5863 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5864 if (vmx_interrupt_allowed(vcpu)) {
5865 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5866 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5867 vcpu->arch.nmi_pending) {
5868 /*
5869 * This CPU don't support us in finding the end of an
5870 * NMI-blocked window if the guest runs with IRQs
5871 * disabled. So we pull the trigger after 1 s of
5872 * futile waiting, but inform the user about this.
5873 */
5874 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5875 "state on VCPU %d after 1 s timeout\n",
5876 __func__, vcpu->vcpu_id);
5877 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5878 }
5879 }
50c28f21 5880
55d2375e
SC		 5881 if (exit_reason < kvm_vmx_max_exit_handlers
5882 && kvm_vmx_exit_handlers[exit_reason])
5883 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5884 else {
5885 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5886 exit_reason);
5887 kvm_queue_exception(vcpu, UD_VECTOR);
5888 return 1;
5889 }
9ed38ffa
LP		 5890}
5891
efebf0aa 5892/*
55d2375e
SC		 5893 * Software based L1D cache flush which is used when microcode providing
5894 * the cache control MSR is not loaded.
efebf0aa 5895 *
55d2375e
SC		 5896 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5897 * flush it is required to read in 64 KiB because the replacement algorithm
5898 * is not exactly LRU. This could be sized at runtime via topology
5899 * information but as all relevant affected CPUs have 32KiB L1D cache size
5900 * there is no point in doing so.
efebf0aa 5901 */
55d2375e 5902static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5903{
55d2375e 5904 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5905
5906 /*
55d2375e
SC		 5907 * This code is only executed when the the flush mode is 'cond' or
5908 * 'always'
25a2e4fe 5909 */
55d2375e
SC		 5910 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5911 bool flush_l1d;
25a2e4fe 5912
55d2375e
SC		 5913 /*
5914 * Clear the per-vcpu flush bit, it gets set again
5915 * either from vcpu_run() or from one of the unsafe
5916 * VMEXIT handlers.
5917 */
5918 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5919 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5920
55d2375e
SC		 5921 /*
5922 * Clear the per-cpu flush bit, it gets set again from
5923 * the interrupt handlers.
5924 */
5925 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5926 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 5927
55d2375e
SC		 5928 if (!flush_l1d)
5929 return;
5930 }
09abe320 5931
55d2375e 5932 vcpu->stat.l1d_flush++;
25a2e4fe 5933
55d2375e
SC		 5934 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5935 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5936 return;
5937 }
25a2e4fe 5938
55d2375e
SC		 5939 asm volatile(
5940 /* First ensure the pages are in the TLB */
5941 "xorl %%eax, %%eax\n"
5942 ".Lpopulate_tlb:\n\t"
5943 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5944 "addl $4096, %%eax\n\t"
5945 "cmpl %%eax, %[size]\n\t"
5946 "jne .Lpopulate_tlb\n\t"
5947 "xorl %%eax, %%eax\n\t"
5948 "cpuid\n\t"
5949 /* Now fill the cache */
5950 "xorl %%eax, %%eax\n"
5951 ".Lfill_cache:\n"
5952 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5953 "addl $64, %%eax\n\t"
5954 "cmpl %%eax, %[size]\n\t"
5955 "jne .Lfill_cache\n\t"
5956 "lfence\n"
5957 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5958 [size] "r" (size)
5959 : "eax", "ebx", "ecx", "edx");
09abe320 5960}
25a2e4fe 5961
55d2375e 5962static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 5963{
55d2375e 5964 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
09abe320 5965
55d2375e
SC		 5966 if (is_guest_mode(vcpu) &&
5967 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5968 return;
25a2e4fe 5969
55d2375e
SC		 5970 if (irr == -1 || tpr < irr) {
5971 vmcs_write32(TPR_THRESHOLD, 0);
5972 return;
25a2e4fe 5973 }
55d2375e
SC		 5974
5975 vmcs_write32(TPR_THRESHOLD, irr);
8665c3f9
PB		 5976}
5977
55d2375e 5978void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 5979{
55d2375e 5980 u32 sec_exec_control;
8665c3f9 5981
55d2375e
SC		 5982 if (!lapic_in_kernel(vcpu))
5983 return;
9314006d 5984
55d2375e
SC		 5985 if (!flexpriority_enabled &&
5986 !cpu_has_vmx_virtualize_x2apic_mode())
5987 return;
705699a1 5988
55d2375e
SC		 5989 /* Postpone execution until vmcs01 is the current VMCS. */
5990 if (is_guest_mode(vcpu)) {
5991 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
5992 return;
6beb7bd5 5993 }
fe3ef05c 5994
55d2375e
SC		 5995 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5996 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
5997 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 5998
55d2375e
SC		 5999 switch (kvm_get_apic_mode(vcpu)) {
6000 case LAPIC_MODE_INVALID:
6001 WARN_ONCE(true, "Invalid local APIC state");
6002 case LAPIC_MODE_DISABLED:
6003 break;
6004 case LAPIC_MODE_XAPIC:
6005 if (flexpriority_enabled) {
6006 sec_exec_control |=
6007 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6008 vmx_flush_tlb(vcpu, true);
6009 }
6010 break;
6011 case LAPIC_MODE_X2APIC:
6012 if (cpu_has_vmx_virtualize_x2apic_mode())
6013 sec_exec_control |=
6014 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6015 break;
09abe320 6016 }
55d2375e 6017 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
09abe320 6018
55d2375e
SC		 6019 vmx_update_msr_bitmap(vcpu);
6020}
0238ea91 6021
55d2375e
SC		 6022static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6023{
6024 if (!is_guest_mode(vcpu)) {
6025 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6026 vmx_flush_tlb(vcpu, true);
6027 }
6028}
fe3ef05c 6029
55d2375e
SC		 6030static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6031{
6032 u16 status;
6033 u8 old;
32c7acf0 6034
55d2375e
SC		 6035 if (max_isr == -1)
6036 max_isr = 0;
608406e2 6037
55d2375e
SC		 6038 status = vmcs_read16(GUEST_INTR_STATUS);
6039 old = status >> 8;
6040 if (max_isr != old) {
6041 status &= 0xff;
6042 status |= max_isr << 8;
6043 vmcs_write16(GUEST_INTR_STATUS, status);
6044 }
6045}
6beb7bd5 6046
55d2375e
SC		 6047static void vmx_set_rvi(int vector)
6048{
6049 u16 status;
6050 u8 old;
0b665d30 6051
55d2375e
SC		 6052 if (vector == -1)
6053 vector = 0;
fe3ef05c 6054
55d2375e
SC		 6055 status = vmcs_read16(GUEST_INTR_STATUS);
6056 old = (u8)status & 0xff;
6057 if ((u8)vector != old) {
6058 status &= ~0xff;
6059 status |= (u8)vector;
6060 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6061 }
55d2375e 6062}
09abe320 6063
55d2375e
SC		 6064static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6065{
09abe320 6066 /*
55d2375e
SC		 6067 * When running L2, updating RVI is only relevant when
6068 * vmcs12 virtual-interrupt-delivery enabled.
6069 * However, it can be enabled only when L1 also
6070 * intercepts external-interrupts and in that case
6071 * we should not update vmcs02 RVI but instead intercept
6072 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6073 */
55d2375e
SC		 6074 if (!is_guest_mode(vcpu))
6075 vmx_set_rvi(max_irr);
6076}
fe3ef05c 6077
55d2375e
SC		 6078static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6079{
6080 struct vcpu_vmx *vmx = to_vmx(vcpu);
6081 int max_irr;
6082 bool max_irr_updated;
a7c0b07d 6083
55d2375e
SC		 6084 WARN_ON(!vcpu->arch.apicv_active);
6085 if (pi_test_on(&vmx->pi_desc)) {
6086 pi_clear_on(&vmx->pi_desc);
6087 /*
6088 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6089 * But on x86 this is just a compiler barrier anyway.
6090 */
6091 smp_mb__after_atomic();
6092 max_irr_updated =
6093 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6094
6095 /*
55d2375e
SC		 6096 * If we are running L2 and L1 has a new pending interrupt
6097 * which can be injected, we should re-evaluate
6098 * what should be done with this new L1 interrupt.
6099 * If L1 intercepts external-interrupts, we should
6100 * exit from L2 to L1. Otherwise, interrupt should be
6101 * delivered directly to L2.
c4ebd629 6102 */
55d2375e
SC		 6103 if (is_guest_mode(vcpu) && max_irr_updated) {
6104 if (nested_exit_on_intr(vcpu))
6105 kvm_vcpu_exiting_guest_mode(vcpu);
6106 else
6107 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6108 }
55d2375e
SC		 6109 } else {
6110 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6111 }
55d2375e
SC		 6112 vmx_hwapic_irr_update(vcpu, max_irr);
6113 return max_irr;
6114}
a7c0b07d 6115
55d2375e
SC		 6116static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6117{
6118 if (!kvm_vcpu_apicv_active(vcpu))
6119 return;
25a2e4fe 6120
55d2375e
SC		 6121 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6122 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6123 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6124 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6125}
6126
55d2375e 6127static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6128{
6129 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6130
55d2375e
SC		 6131 pi_clear_on(&vmx->pi_desc);
6132 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6133}
8665c3f9 6134
95b5a48c 6135static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
55d2375e 6136{
beb8d93b 6137 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6138
55d2375e 6139 /* if exit due to PF check for async PF */
beb8d93b 6140 if (is_page_fault(vmx->exit_intr_info))
55d2375e 6141 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 6142
55d2375e 6143 /* Handle machine checks before interrupts are enabled */
beb8d93b 6144 if (is_machine_check(vmx->exit_intr_info))
55d2375e 6145 kvm_machine_check();
fe3ef05c 6146
55d2375e 6147 /* We need to handle NMIs before interrupts are enabled */
beb8d93b 6148 if (is_nmi(vmx->exit_intr_info)) {
55d2375e
SC		 6149 kvm_before_interrupt(&vmx->vcpu);
6150 asm("int $2");
6151 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6152 }
55d2375e 6153}
fe3ef05c 6154
95b5a48c 6155static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
55d2375e 6156{
49def500
SC		 6157 unsigned int vector;
6158 unsigned long entry;
55d2375e 6159#ifdef CONFIG_X86_64
49def500 6160 unsigned long tmp;
55d2375e 6161#endif
49def500
SC		 6162 gate_desc *desc;
6163 u32 intr_info;
fe3ef05c 6164
49def500
SC		 6165 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6166 if (WARN_ONCE(!is_external_intr(intr_info),
6167 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6168 return;
6169
6170 vector = intr_info & INTR_INFO_VECTOR_MASK;
2342080c 6171 desc = (gate_desc *)host_idt_base + vector;
49def500
SC		 6172 entry = gate_offset(desc);
6173
165072b0
SC		 6174 kvm_before_interrupt(vcpu);
6175
49def500 6176 asm volatile(
55d2375e 6177#ifdef CONFIG_X86_64
49def500
SC		 6178 "mov %%" _ASM_SP ", %[sp]\n\t"
6179 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6180 "push $%c[ss]\n\t"
6181 "push %[sp]\n\t"
55d2375e 6182#endif
49def500
SC		 6183 "pushf\n\t"
6184 __ASM_SIZE(push) " $%c[cs]\n\t"
6185 CALL_NOSPEC
6186 :
55d2375e 6187#ifdef CONFIG_X86_64
49def500 6188 [sp]"=&r"(tmp),
55d2375e 6189#endif
49def500
SC		 6190 ASM_CALL_CONSTRAINT
6191 :
6192 THUNK_TARGET(entry),
6193 [ss]"i"(__KERNEL_DS),
6194 [cs]"i"(__KERNEL_CS)
6195 );
165072b0
SC		 6196
6197 kvm_after_interrupt(vcpu);
55d2375e 6198}
95b5a48c
SC		 6199STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6200
6201static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6202{
6203 struct vcpu_vmx *vmx = to_vmx(vcpu);
6204
6205 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6206 handle_external_interrupt_irqoff(vcpu);
6207 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6208 handle_exception_nmi_irqoff(vmx);
6209}
5a6a9748 6210
55d2375e
SC		 6211static bool vmx_has_emulated_msr(int index)
6212{
6213 switch (index) {
6214 case MSR_IA32_SMBASE:
6215 /*
6216 * We cannot do SMM unless we can run the guest in big
6217 * real mode.
6218 */
6219 return enable_unrestricted_guest || emulate_invalid_guest_state;
6220 case MSR_AMD64_VIRT_SPEC_CTRL:
6221 /* This is AMD only. */
6222 return false;
6223 default:
6224 return true;
3184a995 6225 }
55d2375e 6226}
2bb8cafe 6227
86f5201d
CP		 6228static bool vmx_pt_supported(void)
6229{
6230 return pt_mode == PT_MODE_HOST_GUEST;
6231}
6232
55d2375e
SC		 6233static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6234{
6235 u32 exit_intr_info;
6236 bool unblock_nmi;
6237 u8 vector;
6238 bool idtv_info_valid;
7ca29de2 6239
55d2375e 6240 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6241
55d2375e
SC		 6242 if (enable_vnmi) {
6243 if (vmx->loaded_vmcs->nmi_known_unmasked)
6244 return;
6245 /*
6246 * Can't use vmx->exit_intr_info since we're not sure what
6247 * the exit reason is.
6248 */
6249 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6250 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6251 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6252 /*
6253 * SDM 3: 27.7.1.2 (September 2008)
6254 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6255 * a guest IRET fault.
6256 * SDM 3: 23.2.2 (September 2008)
6257 * Bit 12 is undefined in any of the following cases:
6258 * If the VM exit sets the valid bit in the IDT-vectoring
6259 * information field.
6260 * If the VM exit is due to a double fault.
6261 */
6262 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6263 vector != DF_VECTOR && !idtv_info_valid)
6264 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6265 GUEST_INTR_STATE_NMI);
6266 else
6267 vmx->loaded_vmcs->nmi_known_unmasked =
6268 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6269 & GUEST_INTR_STATE_NMI);
6270 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6271 vmx->loaded_vmcs->vnmi_blocked_time +=
6272 ktime_to_ns(ktime_sub(ktime_get(),
6273 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6274}
6275
55d2375e
SC		 6276static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6277 u32 idt_vectoring_info,
6278 int instr_len_field,
6279 int error_code_field)
0c7f650e 6280{
55d2375e
SC		 6281 u8 vector;
6282 int type;
6283 bool idtv_info_valid;
0c7f650e 6284
55d2375e 6285 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6286
55d2375e
SC		 6287 vcpu->arch.nmi_injected = false;
6288 kvm_clear_exception_queue(vcpu);
6289 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6290
55d2375e
SC		 6291 if (!idtv_info_valid)
6292 return;
c7c2c709 6293
55d2375e 6294 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6295
55d2375e
SC		 6296 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6297 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6298
55d2375e
SC		 6299 switch (type) {
6300 case INTR_TYPE_NMI_INTR:
6301 vcpu->arch.nmi_injected = true;
6302 /*
6303 * SDM 3: 27.7.1.2 (September 2008)
6304 * Clear bit "block by NMI" before VM entry if a NMI
6305 * delivery faulted.
6306 */
6307 vmx_set_nmi_mask(vcpu, false);
6308 break;
6309 case INTR_TYPE_SOFT_EXCEPTION:
6310 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6311 /* fall through */
6312 case INTR_TYPE_HARD_EXCEPTION:
6313 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6314 u32 err = vmcs_read32(error_code_field);
6315 kvm_requeue_exception_e(vcpu, vector, err);
6316 } else
6317 kvm_requeue_exception(vcpu, vector);
6318 break;
6319 case INTR_TYPE_SOFT_INTR:
6320 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6321 /* fall through */
6322 case INTR_TYPE_EXT_INTR:
6323 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6324 break;
6325 default:
6326 break;
0447378a 6327 }
ca0bde28
JM		 6328}
6329
55d2375e 6330static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6331{
55d2375e
SC		 6332 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6333 VM_EXIT_INSTRUCTION_LEN,
6334 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6335}
6336
55d2375e 6337static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6338{
55d2375e
SC		 6339 __vmx_complete_interrupts(vcpu,
6340 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6341 VM_ENTRY_INSTRUCTION_LEN,
6342 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6343
55d2375e 6344 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6345}
6346
55d2375e 6347static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6348{
55d2375e
SC		 6349 int i, nr_msrs;
6350 struct perf_guest_switch_msr *msrs;
7c177938 6351
55d2375e 6352 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6353
55d2375e
SC		 6354 if (!msrs)
6355 return;
f1b026a3 6356
55d2375e
SC		 6357 for (i = 0; i < nr_msrs; i++)
6358 if (msrs[i].host == msrs[i].guest)
6359 clear_atomic_switch_msr(vmx, msrs[i].msr);
6360 else
6361 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6362 msrs[i].host, false);
ca0bde28 6363}
52017608 6364
55d2375e
SC		 6365static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
6366{
6367 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
6368 if (!vmx->loaded_vmcs->hv_timer_armed)
6369 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
6370 PIN_BASED_VMX_PREEMPTION_TIMER);
6371 vmx->loaded_vmcs->hv_timer_armed = true;
6372}
ca0bde28 6373
55d2375e 6374static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6375{
6376 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6377 u64 tscl;
6378 u32 delta_tsc;
52017608 6379
55d2375e
SC		 6380 if (vmx->req_immediate_exit) {
6381 vmx_arm_hv_timer(vmx, 0);
6382 return;
16fb9a46
SC		 6383 }
6384
55d2375e
SC		 6385 if (vmx->hv_deadline_tsc != -1) {
6386 tscl = rdtsc();
6387 if (vmx->hv_deadline_tsc > tscl)
6388 /* set_hv_timer ensures the delta fits in 32-bits */
6389 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6390 cpu_preemption_timer_multi);
6391 else
6392 delta_tsc = 0;
858e25c0 6393
55d2375e
SC		 6394 vmx_arm_hv_timer(vmx, delta_tsc);
6395 return;
7f7f1ba3 6396 }
858e25c0 6397
55d2375e
SC		 6398 if (vmx->loaded_vmcs->hv_timer_armed)
6399 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
6400 PIN_BASED_VMX_PREEMPTION_TIMER);
6401 vmx->loaded_vmcs->hv_timer_armed = false;
858e25c0
JM		 6402}
6403
c09b03eb 6404void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6405{
c09b03eb
SC		 6406 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6407 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6408 vmcs_writel(HOST_RSP, host_rsp);
6409 }
5ad6ece8 6410}
5f3d5799 6411
fc2ba5a2 6412bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6413
6414static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6415{
6416 struct vcpu_vmx *vmx = to_vmx(vcpu);
6417 unsigned long cr3, cr4;
6418
6419 /* Record the guest's net vcpu time for enforced NMI injections. */
6420 if (unlikely(!enable_vnmi &&
6421 vmx->loaded_vmcs->soft_vnmi_blocked))
6422 vmx->loaded_vmcs->entry_time = ktime_get();
6423
6424 /* Don't enter VMX if guest state is invalid, let the exit handler
6425 start emulation until we arrive back to a valid state */
6426 if (vmx->emulation_required)
6427 return;
6428
6429 if (vmx->ple_window_dirty) {
6430 vmx->ple_window_dirty = false;
6431 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6432 }
6433
3731905e
SC		 6434 if (vmx->nested.need_vmcs12_to_shadow_sync)
6435 nested_sync_vmcs12_to_shadow(vcpu);
5ad6ece8
SC		 6436
6437 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6438 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6439 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6440 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6441
6442 cr3 = __get_current_cr3_fast();
6443 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6444 vmcs_writel(HOST_CR3, cr3);
6445 vmx->loaded_vmcs->host_state.cr3 = cr3;
6446 }
6447
6448 cr4 = cr4_read_shadow();
6449 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6450 vmcs_writel(HOST_CR4, cr4);
6451 vmx->loaded_vmcs->host_state.cr4 = cr4;
6452 }
6453
6454 /* When single-stepping over STI and MOV SS, we must clear the
6455 * corresponding interruptibility bits in the guest state. Otherwise
6456 * vmentry fails as it then expects bit 14 (BS) in pending debug
6457 * exceptions being set, but that's not correct for the guest debugging
6458 * case. */
6459 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6460 vmx_set_interrupt_shadow(vcpu, 0);
6461
1811d979
WC		 6462 kvm_load_guest_xcr0(vcpu);
6463
5ad6ece8
SC		 6464 if (static_cpu_has(X86_FEATURE_PKU) &&
6465 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6466 vcpu->arch.pkru != vmx->host_pkru)
6467 __write_pkru(vcpu->arch.pkru);
6468
6469 pt_guest_enter(vmx);
6470
6471 atomic_switch_perf_msrs(vmx);
6472
6473 vmx_update_hv_timer(vcpu);
6474
b6c4bc65
WL		 6475 if (lapic_in_kernel(vcpu) &&
6476 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6477 kvm_wait_lapic_expire(vcpu);
6478
5ad6ece8
SC		 6479 /*
6480 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6481 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6482 * is no need to worry about the conditional branch over the wrmsr
6483 * being speculatively taken.
6484 */
6485 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6486
fa4bff16 6487 /* L1D Flush includes CPU buffer clear to mitigate MDS */
c823dd5c
SC		 6488 if (static_branch_unlikely(&vmx_l1d_should_flush))
6489 vmx_l1d_flush(vcpu);
fa4bff16
LT		 6490 else if (static_branch_unlikely(&mds_user_clear))
6491 mds_clear_cpu_buffers();
c823dd5c
SC		 6492
6493 if (vcpu->arch.cr2 != read_cr2())
6494 write_cr2(vcpu->arch.cr2);
6495
fc2ba5a2
SC		 6496 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6497 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6498
6499 vcpu->arch.cr2 = read_cr2();
b6b8a145 6500
55d2375e
SC		 6501 /*
6502 * We do not use IBRS in the kernel. If this vCPU has used the
6503 * SPEC_CTRL MSR it may have left it on; save the value and
6504 * turn it off. This is much more efficient than blindly adding
6505 * it to the atomic save/restore list. Especially as the former
6506 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6507 *
6508 * For non-nested case:
6509 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6510 * save it.
6511 *
6512 * For nested case:
6513 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6514 * save it.
6515 */
6516 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6517 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6518
55d2375e 6519 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6520
55d2375e
SC		 6521 /* All fields are clean at this point */
6522 if (static_branch_unlikely(&enable_evmcs))
6523 current_evmcs->hv_clean_fields |=
6524 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6525
55d2375e
SC		 6526 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6527 if (vmx->host_debugctlmsr)
6528 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6529
55d2375e
SC		 6530#ifndef CONFIG_X86_64
6531 /*
6532 * The sysexit path does not restore ds/es, so we must set them to
6533 * a reasonable value ourselves.
6534 *
6535 * We can't defer this to vmx_prepare_switch_to_host() since that
6536 * function may be executed in interrupt context, which saves and
6537 * restore segments around it, nullifying its effect.
6538 */
6539 loadsegment(ds, __USER_DS);
6540 loadsegment(es, __USER_DS);
6541#endif
4704d0be 6542
55d2375e
SC		 6543 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6544 | (1 << VCPU_EXREG_RFLAGS)
6545 | (1 << VCPU_EXREG_PDPTR)
6546 | (1 << VCPU_EXREG_SEGMENTS)
6547 | (1 << VCPU_EXREG_CR3));
6548 vcpu->arch.regs_dirty = 0;
7854cbca 6549
2ef444f1
CP		 6550 pt_guest_exit(vmx);
6551
3633cfc3 6552 /*
55d2375e
SC		 6553 * eager fpu is enabled if PKEY is supported and CR4 is switched
6554 * back on host, so it is safe to read guest PKRU from current
6555 * XSAVE.
3633cfc3 6556 */
55d2375e
SC		 6557 if (static_cpu_has(X86_FEATURE_PKU) &&
6558 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
c806e887 6559 vcpu->arch.pkru = rdpkru();
55d2375e
SC		 6560 if (vcpu->arch.pkru != vmx->host_pkru)
6561 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6562 }
6563
1811d979
WC		 6564 kvm_put_guest_xcr0(vcpu);
6565
55d2375e
SC		 6566 vmx->nested.nested_run_pending = 0;
6567 vmx->idt_vectoring_info = 0;
119a9c01 6568
55d2375e 6569 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
beb8d93b
SC		 6570 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6571 kvm_machine_check();
6572
55d2375e
SC		 6573 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6574 return;
608406e2 6575
55d2375e
SC		 6576 vmx->loaded_vmcs->launched = 1;
6577 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6578
55d2375e
SC		 6579 vmx_recover_nmi_blocking(vmx);
6580 vmx_complete_interrupts(vmx);
6581}
2996fca0 6582
55d2375e
SC		 6583static struct kvm *vmx_vm_alloc(void)
6584{
41836839
BG		 6585 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6586 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6587 PAGE_KERNEL);
55d2375e 6588 return &kvm_vmx->kvm;
cf8b84f4
JM		 6589}
6590
55d2375e
SC		 6591static void vmx_vm_free(struct kvm *kvm)
6592{
6593 vfree(to_kvm_vmx(kvm));
6594}
6595
6596static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6597{
55d2375e 6598 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6599
55d2375e
SC		 6600 if (enable_pml)
6601 vmx_destroy_pml_buffer(vmx);
6602 free_vpid(vmx->vpid);
55d2375e
SC		 6603 nested_vmx_free_vcpu(vcpu);
6604 free_loaded_vmcs(vmx->loaded_vmcs);
6605 kfree(vmx->guest_msrs);
6606 kvm_vcpu_uninit(vcpu);
b666a4b6 6607 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
55d2375e
SC		 6608 kmem_cache_free(kvm_vcpu_cache, vmx);
6609}
4704d0be 6610
55d2375e
SC		 6611static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6612{
6613 int err;
41836839 6614 struct vcpu_vmx *vmx;
55d2375e
SC		 6615 unsigned long *msr_bitmap;
6616 int cpu;
7313c698 6617
41836839 6618 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6619 if (!vmx)
6620 return ERR_PTR(-ENOMEM);
4704d0be 6621
41836839
BG		 6622 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6623 GFP_KERNEL_ACCOUNT);
b666a4b6
MO		 6624 if (!vmx->vcpu.arch.guest_fpu) {
6625 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6626 err = -ENOMEM;
6627 goto free_partial_vcpu;
6628 }
6629
55d2375e 6630 vmx->vpid = allocate_vpid();
7cdc2d62 6631
55d2375e
SC		 6632 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6633 if (err)
6634 goto free_vcpu;
5f3d5799 6635
55d2375e 6636 err = -ENOMEM;
5f3d5799
JK		 6637
6638 /*
55d2375e
SC		 6639 * If PML is turned on, failure on enabling PML just results in failure
6640 * of creating the vcpu, therefore we can simplify PML logic (by
6641 * avoiding dealing with cases, such as enabling PML partially on vcpus
6642 * for the guest, etc.
5f3d5799 6643 */
55d2375e 6644 if (enable_pml) {
41836839 6645 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e
SC		 6646 if (!vmx->pml_pg)
6647 goto uninit_vcpu;
6648 }
4704d0be 6649
41836839 6650 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6651 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6652 > PAGE_SIZE);
21feb4eb 6653
55d2375e
SC		 6654 if (!vmx->guest_msrs)
6655 goto free_pml;
4704d0be 6656
55d2375e
SC		 6657 err = alloc_loaded_vmcs(&vmx->vmcs01);
6658 if (err < 0)
6659 goto free_msrs;
cb61de2f 6660
55d2375e 6661 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6662 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6663 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6664 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6665 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6666 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6667 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6668 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
b5170063
WL		 6669 if (kvm_cstate_in_guest(kvm)) {
6670 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6671 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6672 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6673 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6674 }
55d2375e 6675 vmx->msr_bitmap_mode = 0;
4704d0be 6676
55d2375e
SC		 6677 vmx->loaded_vmcs = &vmx->vmcs01;
6678 cpu = get_cpu();
6679 vmx_vcpu_load(&vmx->vcpu, cpu);
6680 vmx->vcpu.cpu = cpu;
6681 vmx_vcpu_setup(vmx);
6682 vmx_vcpu_put(&vmx->vcpu);
6683 put_cpu();
6684 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6685 err = alloc_apic_access_page(kvm);
6686 if (err)
6687 goto free_vmcs;
6688 }
6689
6690 if (enable_ept && !enable_unrestricted_guest) {
6691 err = init_rmode_identity_map(kvm);
6692 if (err)
6693 goto free_vmcs;
6694 }
4704d0be 6695
55d2375e
SC		 6696 if (nested)
6697 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6698 vmx_capability.ept,
6699 kvm_vcpu_apicv_active(&vmx->vcpu));
6700 else
6701 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6702
55d2375e
SC		 6703 vmx->nested.posted_intr_nv = -1;
6704 vmx->nested.current_vmptr = -1ull;
bd18bffc 6705
55d2375e 6706 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
feaf0c7d 6707
6f1e03bc 6708 /*
55d2375e
SC		 6709 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6710 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6711 */
55d2375e
SC		 6712 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6713 vmx->pi_desc.sn = 1;
4704d0be 6714
53963a70
LT		 6715 vmx->ept_pointer = INVALID_PAGE;
6716
55d2375e 6717 return &vmx->vcpu;
4704d0be 6718
55d2375e
SC		 6719free_vmcs:
6720 free_loaded_vmcs(vmx->loaded_vmcs);
6721free_msrs:
6722 kfree(vmx->guest_msrs);
6723free_pml:
6724 vmx_destroy_pml_buffer(vmx);
6725uninit_vcpu:
6726 kvm_vcpu_uninit(&vmx->vcpu);
6727free_vcpu:
6728 free_vpid(vmx->vpid);
b666a4b6
MO		 6729 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6730free_partial_vcpu:
55d2375e
SC		 6731 kmem_cache_free(kvm_vcpu_cache, vmx);
6732 return ERR_PTR(err);
6733}
36be0b9d 6734
65fd4cb6
TG		 6735#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6736#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
21feb4eb 6737
55d2375e
SC		 6738static int vmx_vm_init(struct kvm *kvm)
6739{
6740 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6741
55d2375e
SC		 6742 if (!ple_gap)
6743 kvm->arch.pause_in_guest = true;
3af18d9c 6744
55d2375e
SC		 6745 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6746 switch (l1tf_mitigation) {
6747 case L1TF_MITIGATION_OFF:
6748 case L1TF_MITIGATION_FLUSH_NOWARN:
6749 /* 'I explicitly don't care' is set */
6750 break;
6751 case L1TF_MITIGATION_FLUSH:
6752 case L1TF_MITIGATION_FLUSH_NOSMT:
6753 case L1TF_MITIGATION_FULL:
6754 /*
6755 * Warn upon starting the first VM in a potentially
6756 * insecure environment.
6757 */
b284909a 6758 if (sched_smt_active())
55d2375e
SC		 6759 pr_warn_once(L1TF_MSG_SMT);
6760 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6761 pr_warn_once(L1TF_MSG_L1D);
6762 break;
6763 case L1TF_MITIGATION_FULL_FORCE:
6764 /* Flush is enforced */
6765 break;
6766 }
6767 }
6768 return 0;
4704d0be
NHE		 6769}
6770
f257d6dc 6771static int __init vmx_check_processor_compat(void)
bd18bffc 6772{
55d2375e
SC		 6773 struct vmcs_config vmcs_conf;
6774 struct vmx_capability vmx_cap;
bd18bffc 6775
55d2375e 6776 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
f257d6dc 6777 return -EIO;
55d2375e
SC		 6778 if (nested)
6779 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6780 enable_apicv);
6781 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6782 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6783 smp_processor_id());
f257d6dc 6784 return -EIO;
bd18bffc 6785 }
f257d6dc 6786 return 0;
bd18bffc
SC		 6787}
6788
55d2375e 6789static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6790{
55d2375e
SC		 6791 u8 cache;
6792 u64 ipat = 0;
bd18bffc 6793
55d2375e
SC		 6794 /* For VT-d and EPT combination
6795 * 1. MMIO: always map as UC
6796 * 2. EPT with VT-d:
6797 * a. VT-d without snooping control feature: can't guarantee the
6798 * result, try to trust guest.
6799 * b. VT-d with snooping control feature: snooping control feature of
6800 * VT-d engine can guarantee the cache correctness. Just set it
6801 * to WB to keep consistent with host. So the same as item 3.
6802 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6803 * consistent with host MTRR
bd18bffc 6804 */
55d2375e
SC		 6805 if (is_mmio) {
6806 cache = MTRR_TYPE_UNCACHABLE;
6807 goto exit;
6808 }
bd18bffc 6809
55d2375e
SC		 6810 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6811 ipat = VMX_EPT_IPAT_BIT;
6812 cache = MTRR_TYPE_WRBACK;
6813 goto exit;
6814 }
bd18bffc 6815
55d2375e
SC		 6816 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6817 ipat = VMX_EPT_IPAT_BIT;
6818 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6819 cache = MTRR_TYPE_WRBACK;
6820 else
6821 cache = MTRR_TYPE_UNCACHABLE;
6822 goto exit;
6823 }
bd18bffc 6824
55d2375e 6825 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6826
55d2375e
SC		 6827exit:
6828 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6829}
bd18bffc 6830
55d2375e
SC		 6831static int vmx_get_lpage_level(void)
6832{
6833 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6834 return PT_DIRECTORY_LEVEL;
6835 else
6836 /* For shadow and EPT supported 1GB page */
6837 return PT_PDPE_LEVEL;
6838}
bd18bffc 6839
55d2375e
SC		 6840static void vmcs_set_secondary_exec_control(u32 new_ctl)
6841{
bd18bffc 6842 /*
55d2375e
SC		 6843 * These bits in the secondary execution controls field
6844 * are dynamic, the others are mostly based on the hypervisor
6845 * architecture and the guest's CPUID. Do not touch the
6846 * dynamic bits.
bd18bffc 6847 */
55d2375e
SC		 6848 u32 mask =
6849 SECONDARY_EXEC_SHADOW_VMCS |
6850 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6851 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6852 SECONDARY_EXEC_DESC;
bd18bffc 6853
55d2375e 6854 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
bd18bffc 6855
55d2375e
SC		 6856 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6857 (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6858}
6859
4704d0be 6860/*
55d2375e
SC		 6861 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6862 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6863 */
55d2375e 6864static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6865{
6866 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6867 struct kvm_cpuid_entry2 *entry;
4704d0be 6868
55d2375e
SC		 6869 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6870 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6871
55d2375e
SC		 6872#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6873 if (entry && (entry->_reg & (_cpuid_mask))) \
6874 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6875} while (0)
ff651cb6 6876
55d2375e
SC		 6877 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6878 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6879 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6880 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6881 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6882 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6883 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6884 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6885 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6886 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6887 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6888 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6889 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6890 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6891 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
61ada748 6892
55d2375e
SC		 6893 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6894 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6895 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6896 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6897 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6898 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
cf3215d9 6899
55d2375e
SC		 6900#undef cr4_fixed1_update
6901}
36c3cc42 6902
55d2375e
SC		 6903static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6904{
6905 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 6906
55d2375e
SC		 6907 if (kvm_mpx_supported()) {
6908 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 6909
55d2375e
SC		 6910 if (mpx_enabled) {
6911 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6912 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6913 } else {
6914 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6915 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6916 }
dccbfcf5 6917 }
55d2375e 6918}
4704d0be 6919
6c0f0bba
LK		 6920static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6921{
6922 struct vcpu_vmx *vmx = to_vmx(vcpu);
6923 struct kvm_cpuid_entry2 *best = NULL;
6924 int i;
6925
6926 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6927 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6928 if (!best)
6929 return;
6930 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6931 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6932 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6933 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
6934 }
6935
6936 /* Get the number of configurable Address Ranges for filtering */
6937 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
6938 PT_CAP_num_address_ranges);
6939
6940 /* Initialize and clear the no dependency bits */
6941 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
6942 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
6943
6944 /*
6945 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
6946 * will inject an #GP
6947 */
6948 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
6949 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
6950
6951 /*
6952 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
6953 * PSBFreq can be set
6954 */
6955 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
6956 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
6957 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
6958
6959 /*
6960 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
6961 * MTCFreq can be set
6962 */
6963 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
6964 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
6965 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
6966
6967 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
6968 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
6969 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
6970 RTIT_CTL_PTW_EN);
6971
6972 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
6973 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
6974 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
6975
6976 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
6977 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
6978 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
6979
6980 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
6981 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
6982 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
6983
6984 /* unmask address range configure area */
6985 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 6986 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 6987}
6988
55d2375e
SC		 6989static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6990{
6991 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6992
55d2375e
SC		 6993 if (cpu_has_secondary_exec_ctrls()) {
6994 vmx_compute_secondary_exec_control(vmx);
6995 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
705699a1 6996 }
4704d0be 6997
55d2375e
SC		 6998 if (nested_vmx_allowed(vcpu))
6999 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7000 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7001 else
7002 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7003 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4f350c6d 7004
55d2375e
SC		 7005 if (nested_vmx_allowed(vcpu)) {
7006 nested_vmx_cr_fixed1_bits_update(vcpu);
7007 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 7008 }
6c0f0bba
LK		 7009
7010 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7011 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7012 update_intel_pt_cfg(vcpu);
55d2375e 7013}
09abb5e3 7014
55d2375e
SC		 7015static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7016{
7017 if (func == 1 && nested)
7018 entry->ecx |= bit(X86_FEATURE_VMX);
4704d0be
NHE		 7019}
7020
55d2375e 7021static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 7022{
55d2375e 7023 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 7024}
7025
8a76d7f2
JR		 7026static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7027 struct x86_instruction_info *info,
7028 enum x86_intercept_stage stage)
7029{
fb6d4d34
PB		 7030 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7031 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7032
7033 /*
7034 * RDPID causes #UD if disabled through secondary execution controls.
7035 * Because it is marked as EmulateOnUD, we need to intercept it here.
7036 */
7037 if (info->intercept == x86_intercept_rdtscp &&
7038 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7039 ctxt->exception.vector = UD_VECTOR;
7040 ctxt->exception.error_code_valid = false;
7041 return X86EMUL_PROPAGATE_FAULT;
7042 }
7043
7044 /* TODO: check more intercepts... */
8a76d7f2
JR		 7045 return X86EMUL_CONTINUE;
7046}
7047
64672c95
YJ		 7048#ifdef CONFIG_X86_64
7049/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7050static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7051 u64 divisor, u64 *result)
7052{
7053 u64 low = a << shift, high = a >> (64 - shift);
7054
7055 /* To avoid the overflow on divq */
7056 if (high >= divisor)
7057 return 1;
7058
7059 /* Low hold the result, high hold rem which is discarded */
7060 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7061 "rm" (divisor), "0" (low), "1" (high));
7062 *result = low;
7063
7064 return 0;
7065}
7066
f9927982
SC		 7067static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7068 bool *expired)
64672c95 7069{
386c6ddb 7070 struct vcpu_vmx *vmx;
c5ce8235 7071 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
39497d76 7072 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
386c6ddb
KA		 7073
7074 if (kvm_mwait_in_guest(vcpu->kvm))
7075 return -EOPNOTSUPP;
7076
7077 vmx = to_vmx(vcpu);
7078 tscl = rdtsc();
7079 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7080 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
39497d76
SC		 7081 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7082 ktimer->timer_advance_ns);
c5ce8235
WL		 7083
7084 if (delta_tsc > lapic_timer_advance_cycles)
7085 delta_tsc -= lapic_timer_advance_cycles;
7086 else
7087 delta_tsc = 0;
64672c95
YJ		 7088
7089 /* Convert to host delta tsc if tsc scaling is enabled */
7090 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
0967fa1c 7091 delta_tsc && u64_shl_div_u64(delta_tsc,
64672c95 7092 kvm_tsc_scaling_ratio_frac_bits,
0967fa1c 7093 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
64672c95
YJ		 7094 return -ERANGE;
7095
7096 /*
7097 * If the delta tsc can't fit in the 32 bit after the multi shift,
7098 * we can't use the preemption timer.
7099 * It's possible that it fits on later vmentries, but checking
7100 * on every vmentry is costly so we just use an hrtimer.
7101 */
7102 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7103 return -ERANGE;
7104
7105 vmx->hv_deadline_tsc = tscl + delta_tsc;
f9927982
SC		 7106 *expired = !delta_tsc;
7107 return 0;
64672c95
YJ		 7108}
7109
7110static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7111{
f459a707 7112 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7113}
7114#endif
7115
48d89b92 7116static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7117{
b31c114b 7118 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7119 shrink_ple_window(vcpu);
ae97a3b8
RK		 7120}
7121
843e4330
KH		 7122static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7123 struct kvm_memory_slot *slot)
7124{
7125 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7126 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7127}
7128
7129static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7130 struct kvm_memory_slot *slot)
7131{
7132 kvm_mmu_slot_set_dirty(kvm, slot);
7133}
7134
7135static void vmx_flush_log_dirty(struct kvm *kvm)
7136{
7137 kvm_flush_pml_buffers(kvm);
7138}
7139
c5f983f6
BD		 7140static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7141{
7142 struct vmcs12 *vmcs12;
7143 struct vcpu_vmx *vmx = to_vmx(vcpu);
3d5f6beb 7144 gpa_t gpa, dst;
c5f983f6
BD		 7145
7146 if (is_guest_mode(vcpu)) {
7147 WARN_ON_ONCE(vmx->nested.pml_full);
7148
7149 /*
7150 * Check if PML is enabled for the nested guest.
7151 * Whether eptp bit 6 is set is already checked
7152 * as part of A/D emulation.
7153 */
7154 vmcs12 = get_vmcs12(vcpu);
7155 if (!nested_cpu_has_pml(vmcs12))
7156 return 0;
7157
4769886b 7158 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7159 vmx->nested.pml_full = true;
7160 return 1;
7161 }
7162
7163 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
3d5f6beb 7164 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
c5f983f6 7165
3d5f6beb
KA		 7166 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7167 offset_in_page(dst), sizeof(gpa)))
c5f983f6
BD		 7168 return 0;
7169
3d5f6beb 7170 vmcs12->guest_pml_index--;
c5f983f6
BD		 7171 }
7172
7173 return 0;
7174}
7175
843e4330
KH		 7176static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7177 struct kvm_memory_slot *memslot,
7178 gfn_t offset, unsigned long mask)
7179{
7180 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7181}
7182
cd39e117
PB		 7183static void __pi_post_block(struct kvm_vcpu *vcpu)
7184{
7185 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7186 struct pi_desc old, new;
7187 unsigned int dest;
cd39e117
PB		 7188
7189 do {
7190 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7191 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7192 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7193
7194 dest = cpu_physical_id(vcpu->cpu);
7195
7196 if (x2apic_enabled())
7197 new.ndst = dest;
7198 else
7199 new.ndst = (dest << 8) & 0xFF00;
7200
cd39e117
PB		 7201 /* set 'NV' to 'notification vector' */
7202 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7203 } while (cmpxchg64(&pi_desc->control, old.control,
7204 new.control) != old.control);
cd39e117 7205
8b306e2f
PB		 7206 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7207 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7208 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7209 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7210 vcpu->pre_pcpu = -1;
7211 }
7212}
7213
bf9f6ac8
FW		 7214/*
7215 * This routine does the following things for vCPU which is going
7216 * to be blocked if VT-d PI is enabled.
7217 * - Store the vCPU to the wakeup list, so when interrupts happen
7218 * we can find the right vCPU to wake up.
7219 * - Change the Posted-interrupt descriptor as below:
7220 * 'NDST' <-- vcpu->pre_pcpu
7221 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7222 * - If 'ON' is set during this process, which means at least one
7223 * interrupt is posted for this vCPU, we cannot block it, in
7224 * this case, return 1, otherwise, return 0.
7225 *
7226 */
bc22512b 7227static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7228{
bf9f6ac8
FW		 7229 unsigned int dest;
7230 struct pi_desc old, new;
7231 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7232
7233 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7234 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7235 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7236 return 0;
7237
8b306e2f
PB		 7238 WARN_ON(irqs_disabled());
7239 local_irq_disable();
7240 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7241 vcpu->pre_pcpu = vcpu->cpu;
7242 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7243 list_add_tail(&vcpu->blocked_vcpu_list,
7244 &per_cpu(blocked_vcpu_on_cpu,
7245 vcpu->pre_pcpu));
7246 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7247 }
bf9f6ac8
FW		 7248
7249 do {
7250 old.control = new.control = pi_desc->control;
7251
bf9f6ac8
FW		 7252 WARN((pi_desc->sn == 1),
7253 "Warning: SN field of posted-interrupts "
7254 "is set before blocking\n");
7255
7256 /*
7257 * Since vCPU can be preempted during this process,
7258 * vcpu->cpu could be different with pre_pcpu, we
7259 * need to set pre_pcpu as the destination of wakeup
7260 * notification event, then we can find the right vCPU
7261 * to wakeup in wakeup handler if interrupts happen
7262 * when the vCPU is in blocked state.
7263 */
7264 dest = cpu_physical_id(vcpu->pre_pcpu);
7265
7266 if (x2apic_enabled())
7267 new.ndst = dest;
7268 else
7269 new.ndst = (dest << 8) & 0xFF00;
7270
7271 /* set 'NV' to 'wakeup vector' */
7272 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7273 } while (cmpxchg64(&pi_desc->control, old.control,
7274 new.control) != old.control);
bf9f6ac8 7275
8b306e2f
PB		 7276 /* We should not block the vCPU if an interrupt is posted for it. */
7277 if (pi_test_on(pi_desc) == 1)
7278 __pi_post_block(vcpu);
7279
7280 local_irq_enable();
7281 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7282}
7283
bc22512b
YJ		 7284static int vmx_pre_block(struct kvm_vcpu *vcpu)
7285{
7286 if (pi_pre_block(vcpu))
7287 return 1;
7288
64672c95
YJ		 7289 if (kvm_lapic_hv_timer_in_use(vcpu))
7290 kvm_lapic_switch_to_sw_timer(vcpu);
7291
bc22512b
YJ		 7292 return 0;
7293}
7294
7295static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7296{
8b306e2f 7297 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7298 return;
7299
8b306e2f
PB		 7300 WARN_ON(irqs_disabled());
7301 local_irq_disable();
cd39e117 7302 __pi_post_block(vcpu);
8b306e2f 7303 local_irq_enable();
bf9f6ac8
FW		 7304}
7305
bc22512b
YJ		 7306static void vmx_post_block(struct kvm_vcpu *vcpu)
7307{
64672c95
YJ		 7308 if (kvm_x86_ops->set_hv_timer)
7309 kvm_lapic_switch_to_hv_timer(vcpu);
7310
bc22512b
YJ		 7311 pi_post_block(vcpu);
7312}
7313
efc64404
FW		 7314/*
7315 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7316 *
7317 * @kvm: kvm
7318 * @host_irq: host irq of the interrupt
7319 * @guest_irq: gsi of the interrupt
7320 * @set: set or unset PI
7321 * returns 0 on success, < 0 on failure
7322 */
7323static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7324 uint32_t guest_irq, bool set)
7325{
7326 struct kvm_kernel_irq_routing_entry *e;
7327 struct kvm_irq_routing_table *irq_rt;
7328 struct kvm_lapic_irq irq;
7329 struct kvm_vcpu *vcpu;
7330 struct vcpu_data vcpu_info;
3a8b0677 7331 int idx, ret = 0;
efc64404
FW		 7332
7333 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7334 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7335 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7336 return 0;
7337
7338 idx = srcu_read_lock(&kvm->irq_srcu);
7339 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7340 if (guest_irq >= irq_rt->nr_rt_entries ||
7341 hlist_empty(&irq_rt->map[guest_irq])) {
7342 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7343 guest_irq, irq_rt->nr_rt_entries);
7344 goto out;
7345 }
efc64404
FW		 7346
7347 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7348 if (e->type != KVM_IRQ_ROUTING_MSI)
7349 continue;
7350 /*
7351 * VT-d PI cannot support posting multicast/broadcast
7352 * interrupts to a vCPU, we still use interrupt remapping
7353 * for these kind of interrupts.
7354 *
7355 * For lowest-priority interrupts, we only support
7356 * those with single CPU as the destination, e.g. user
7357 * configures the interrupts via /proc/irq or uses
7358 * irqbalance to make the interrupts single-CPU.
7359 *
7360 * We will support full lowest-priority interrupt later.
7361 */
7362
37131313 7363 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW		 7364 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
7365 /*
7366 * Make sure the IRTE is in remapped mode if
7367 * we don't handle it in posted mode.
7368 */
7369 ret = irq_set_vcpu_affinity(host_irq, NULL);
7370 if (ret < 0) {
7371 printk(KERN_INFO
7372 "failed to back to remapped mode, irq: %u\n",
7373 host_irq);
7374 goto out;
7375 }
7376
efc64404 7377 continue;
23a1c257 7378 }
efc64404
FW		 7379
7380 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7381 vcpu_info.vector = irq.vector;
7382
2698d82e 7383 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7384 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7385
7386 if (set)
7387 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7388 else
efc64404 7389 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7390
7391 if (ret < 0) {
7392 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7393 __func__);
7394 goto out;
7395 }
7396 }
7397
7398 ret = 0;
7399out:
7400 srcu_read_unlock(&kvm->irq_srcu, idx);
7401 return ret;
7402}
7403
c45dcc71
AR		 7404static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7405{
7406 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7407 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7408 FEATURE_CONTROL_LMCE;
7409 else
7410 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7411 ~FEATURE_CONTROL_LMCE;
7412}
7413
72d7b374
LP		 7414static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7415{
72e9cbdb
LP		 7416 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7417 if (to_vmx(vcpu)->nested.nested_run_pending)
7418 return 0;
72d7b374
LP		 7419 return 1;
7420}
7421
0234bf88
LP		 7422static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7423{
72e9cbdb
LP		 7424 struct vcpu_vmx *vmx = to_vmx(vcpu);
7425
7426 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7427 if (vmx->nested.smm.guest_mode)
7428 nested_vmx_vmexit(vcpu, -1, 0, 0);
7429
7430 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7431 vmx->nested.vmxon = false;
caa057a2 7432 vmx_clear_hlt(vcpu);
0234bf88
LP		 7433 return 0;
7434}
7435
ed19321f 7436static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7437{
72e9cbdb
LP		 7438 struct vcpu_vmx *vmx = to_vmx(vcpu);
7439 int ret;
7440
7441 if (vmx->nested.smm.vmxon) {
7442 vmx->nested.vmxon = true;
7443 vmx->nested.smm.vmxon = false;
7444 }
7445
7446 if (vmx->nested.smm.guest_mode) {
a633e41e 7447 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7448 if (ret)
7449 return ret;
7450
7451 vmx->nested.smm.guest_mode = false;
7452 }
0234bf88
LP		 7453 return 0;
7454}
7455
cc3d967f
LP		 7456static int enable_smi_window(struct kvm_vcpu *vcpu)
7457{
7458 return 0;
7459}
7460
05d5a486
SB		 7461static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7462{
7463 return 0;
7464}
7465
a3203381
SC		 7466static __init int hardware_setup(void)
7467{
7468 unsigned long host_bndcfgs;
2342080c 7469 struct desc_ptr dt;
a3203381
SC		 7470 int r, i;
7471
7472 rdmsrl_safe(MSR_EFER, &host_efer);
7473
2342080c
SC		 7474 store_idt(&dt);
7475 host_idt_base = dt.address;
7476
a3203381
SC		 7477 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7478 kvm_define_shared_msr(i, vmx_msr_index[i]);
7479
7480 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7481 return -EIO;
7482
7483 if (boot_cpu_has(X86_FEATURE_NX))
7484 kvm_enable_efer_bits(EFER_NX);
7485
7486 if (boot_cpu_has(X86_FEATURE_MPX)) {
7487 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7488 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7489 }
7490
7491 if (boot_cpu_has(X86_FEATURE_XSAVES))
7492 rdmsrl(MSR_IA32_XSS, host_xss);
7493
7494 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7495 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7496 enable_vpid = 0;
7497
7498 if (!cpu_has_vmx_ept() ||
7499 !cpu_has_vmx_ept_4levels() ||
7500 !cpu_has_vmx_ept_mt_wb() ||
7501 !cpu_has_vmx_invept_global())
7502 enable_ept = 0;
7503
7504 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7505 enable_ept_ad_bits = 0;
7506
7507 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7508 enable_unrestricted_guest = 0;
7509
7510 if (!cpu_has_vmx_flexpriority())
7511 flexpriority_enabled = 0;
7512
7513 if (!cpu_has_virtual_nmis())
7514 enable_vnmi = 0;
7515
7516 /*
7517 * set_apic_access_page_addr() is used to reload apic access
7518 * page upon invalidation. No need to do anything if not
7519 * using the APIC_ACCESS_ADDR VMCS field.
7520 */
7521 if (!flexpriority_enabled)
7522 kvm_x86_ops->set_apic_access_page_addr = NULL;
7523
7524 if (!cpu_has_vmx_tpr_shadow())
7525 kvm_x86_ops->update_cr8_intercept = NULL;
7526
7527 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7528 kvm_disable_largepages();
7529
7530#if IS_ENABLED(CONFIG_HYPERV)
7531 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7532 && enable_ept) {
7533 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7534 kvm_x86_ops->tlb_remote_flush_with_range =
7535 hv_remote_flush_tlb_with_range;
7536 }
a3203381
SC		 7537#endif
7538
7539 if (!cpu_has_vmx_ple()) {
7540 ple_gap = 0;
7541 ple_window = 0;
7542 ple_window_grow = 0;
7543 ple_window_max = 0;
7544 ple_window_shrink = 0;
7545 }
7546
7547 if (!cpu_has_vmx_apicv()) {
7548 enable_apicv = 0;
7549 kvm_x86_ops->sync_pir_to_irr = NULL;
7550 }
7551
7552 if (cpu_has_vmx_tsc_scaling()) {
7553 kvm_has_tsc_control = true;
7554 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7555 kvm_tsc_scaling_ratio_frac_bits = 48;
7556 }
7557
7558 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7559
7560 if (enable_ept)
7561 vmx_enable_tdp();
7562 else
7563 kvm_disable_tdp();
7564
a3203381
SC		 7565 /*
7566 * Only enable PML when hardware supports PML feature, and both EPT
7567 * and EPT A/D bit features are enabled -- PML depends on them to work.
7568 */
7569 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7570 enable_pml = 0;
7571
7572 if (!enable_pml) {
7573 kvm_x86_ops->slot_enable_log_dirty = NULL;
7574 kvm_x86_ops->slot_disable_log_dirty = NULL;
7575 kvm_x86_ops->flush_log_dirty = NULL;
7576 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7577 }
7578
7579 if (!cpu_has_vmx_preemption_timer())
7580 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7581
7582 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7583 u64 vmx_msr;
7584
7585 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7586 cpu_preemption_timer_multi =
7587 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7588 } else {
7589 kvm_x86_ops->set_hv_timer = NULL;
7590 kvm_x86_ops->cancel_hv_timer = NULL;
7591 }
7592
a3203381 7593 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7594
7595 kvm_mce_cap_supported |= MCG_LMCE_P;
7596
f99e3daf
CP		 7597 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7598 return -EINVAL;
7599 if (!enable_ept || !cpu_has_vmx_intel_pt())
7600 pt_mode = PT_MODE_SYSTEM;
7601
a3203381 7602 if (nested) {
3e8eaccc
SC		 7603 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7604 vmx_capability.ept, enable_apicv);
7605
e4027cfa 7606 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7607 if (r)
7608 return r;
7609 }
7610
7611 r = alloc_kvm_area();
7612 if (r)
7613 nested_vmx_hardware_unsetup();
7614 return r;
7615}
7616
7617static __exit void hardware_unsetup(void)
7618{
7619 if (nested)
7620 nested_vmx_hardware_unsetup();
7621
7622 free_kvm_area();
7623}
7624
404f6aac 7625static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7626 .cpu_has_kvm_support = cpu_has_kvm_support,
7627 .disabled_by_bios = vmx_disabled_by_bios,
7628 .hardware_setup = hardware_setup,
7629 .hardware_unsetup = hardware_unsetup,
002c7f7c 7630 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7631 .hardware_enable = hardware_enable,
7632 .hardware_disable = hardware_disable,
04547156 7633 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7634 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7635
b31c114b 7636 .vm_init = vmx_vm_init,
434a1e94
SC		 7637 .vm_alloc = vmx_vm_alloc,
7638 .vm_free = vmx_vm_free,
b31c114b 7639
6aa8b732
AK		 7640 .vcpu_create = vmx_create_vcpu,
7641 .vcpu_free = vmx_free_vcpu,
04d2cc77 7642 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7643
6d6095bd 7644 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7645 .vcpu_load = vmx_vcpu_load,
7646 .vcpu_put = vmx_vcpu_put,
7647
a96036b8 7648 .update_bp_intercept = update_exception_bitmap,
801e459a 7649 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7650 .get_msr = vmx_get_msr,
7651 .set_msr = vmx_set_msr,
7652 .get_segment_base = vmx_get_segment_base,
7653 .get_segment = vmx_get_segment,
7654 .set_segment = vmx_set_segment,
2e4d2653 7655 .get_cpl = vmx_get_cpl,
6aa8b732 7656 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7657 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7658 .decache_cr3 = vmx_decache_cr3,
25c4c276 7659 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7660 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7661 .set_cr3 = vmx_set_cr3,
7662 .set_cr4 = vmx_set_cr4,
6aa8b732 7663 .set_efer = vmx_set_efer,
6aa8b732
AK		 7664 .get_idt = vmx_get_idt,
7665 .set_idt = vmx_set_idt,
7666 .get_gdt = vmx_get_gdt,
7667 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7668 .get_dr6 = vmx_get_dr6,
7669 .set_dr6 = vmx_set_dr6,
020df079 7670 .set_dr7 = vmx_set_dr7,
81908bf4 7671 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7672 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7673 .get_rflags = vmx_get_rflags,
7674 .set_rflags = vmx_set_rflags,
be94f6b7 7675
6aa8b732 7676 .tlb_flush = vmx_flush_tlb,
faff8758 7677 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7678
6aa8b732 7679 .run = vmx_vcpu_run,
6062d012 7680 .handle_exit = vmx_handle_exit,
6aa8b732 7681 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7682 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7683 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7684 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7685 .set_irq = vmx_inject_irq,
95ba8273 7686 .set_nmi = vmx_inject_nmi,
298101da 7687 .queue_exception = vmx_queue_exception,
b463a6f7 7688 .cancel_injection = vmx_cancel_injection,
78646121 7689 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7690 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7691 .get_nmi_mask = vmx_get_nmi_mask,
7692 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7693 .enable_nmi_window = enable_nmi_window,
7694 .enable_irq_window = enable_irq_window,
7695 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7696 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7697 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS		 7698 .get_enable_apicv = vmx_get_enable_apicv,
7699 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7700 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7701 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ		 7702 .hwapic_irr_update = vmx_hwapic_irr_update,
7703 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7704 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7705 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7706 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 7707
cbc94022 7708 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7709 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7710 .get_tdp_level = get_ept_level,
4b12f0de 7711 .get_mt_mask = vmx_get_mt_mask,
229456fc 7712
586f9607 7713 .get_exit_info = vmx_get_exit_info,
586f9607 7714
17cc3935 7715 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7716
7717 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7718
7719 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7720 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7721
7722 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7723
7724 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7725
e79f245d 7726 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7727 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7728
7729 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7730
7731 .check_intercept = vmx_check_intercept,
95b5a48c 7732 .handle_exit_irqoff = vmx_handle_exit_irqoff,
da8999d3 7733 .mpx_supported = vmx_mpx_supported,
55412b2e 7734 .xsaves_supported = vmx_xsaves_supported,
66336cab 7735 .umip_emulated = vmx_umip_emulated,
86f5201d 7736 .pt_supported = vmx_pt_supported,
b6b8a145 7737
d264ee0c 7738 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7739
7740 .sched_in = vmx_sched_in,
843e4330
KH		 7741
7742 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7743 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7744 .flush_log_dirty = vmx_flush_log_dirty,
7745 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7746 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7747
bf9f6ac8
FW		 7748 .pre_block = vmx_pre_block,
7749 .post_block = vmx_post_block,
7750
25462f7f 7751 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7752
7753 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7754
7755#ifdef CONFIG_X86_64
7756 .set_hv_timer = vmx_set_hv_timer,
7757 .cancel_hv_timer = vmx_cancel_hv_timer,
7758#endif
c45dcc71
AR		 7759
7760 .setup_mce = vmx_setup_mce,
0234bf88 7761
72d7b374 7762 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7763 .pre_enter_smm = vmx_pre_enter_smm,
7764 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7765 .enable_smi_window = enable_smi_window,
57b119da 7766
e4027cfa
SC		 7767 .check_nested_events = NULL,
7768 .get_nested_state = NULL,
7769 .set_nested_state = NULL,
7770 .get_vmcs12_pages = NULL,
7771 .nested_enable_evmcs = NULL,
05d5a486 7772 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
6aa8b732
AK		 7773};
7774
72c6d2db 7775static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7776{
7777 if (vmx_l1d_flush_pages) {
7778 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7779 vmx_l1d_flush_pages = NULL;
7780 }
72c6d2db
TG		 7781 /* Restore state so sysfs ignores VMX */
7782 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7783}
7784
a7b9020b
TG		 7785static void vmx_exit(void)
7786{
7787#ifdef CONFIG_KEXEC_CORE
7788 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7789 synchronize_rcu();
7790#endif
7791
7792 kvm_exit();
7793
7794#if IS_ENABLED(CONFIG_HYPERV)
7795 if (static_branch_unlikely(&enable_evmcs)) {
7796 int cpu;
7797 struct hv_vp_assist_page *vp_ap;
7798 /*
7799 * Reset everything to support using non-enlightened VMCS
7800 * access later (e.g. when we reload the module with
7801 * enlightened_vmcs=0)
7802 */
7803 for_each_online_cpu(cpu) {
7804 vp_ap = hv_get_vp_assist_page(cpu);
7805
7806 if (!vp_ap)
7807 continue;
7808
7809 vp_ap->current_nested_vmcs = 0;
7810 vp_ap->enlighten_vmentry = 0;
7811 }
7812
7813 static_branch_disable(&enable_evmcs);
7814 }
7815#endif
7816 vmx_cleanup_l1d_flush();
7817}
7818module_exit(vmx_exit);
7819
6aa8b732
AK		 7820static int __init vmx_init(void)
7821{
773e8a04
VK		 7822 int r;
7823
7824#if IS_ENABLED(CONFIG_HYPERV)
7825 /*
7826 * Enlightened VMCS usage should be recommended and the host needs
7827 * to support eVMCS v1 or above. We can also disable eVMCS support
7828 * with module parameter.
7829 */
7830 if (enlightened_vmcs &&
7831 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7832 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7833 KVM_EVMCS_VERSION) {
7834 int cpu;
7835
7836 /* Check that we have assist pages on all online CPUs */
7837 for_each_online_cpu(cpu) {
7838 if (!hv_get_vp_assist_page(cpu)) {
7839 enlightened_vmcs = false;
7840 break;
7841 }
7842 }
7843
7844 if (enlightened_vmcs) {
7845 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7846 static_branch_enable(&enable_evmcs);
7847 }
7848 } else {
7849 enlightened_vmcs = false;
7850 }
7851#endif
7852
7853 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 7854 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7855 if (r)
34a1cd60 7856 return r;
25c5f225 7857
a7b9020b 7858 /*
7db92e16
TG		 7859 * Must be called after kvm_init() so enable_ept is properly set
7860 * up. Hand the parameter mitigation value in which was stored in
7861 * the pre module init parser. If no parameter was given, it will
7862 * contain 'auto' which will be turned into the default 'cond'
7863 * mitigation mode.
7864 */
7865 if (boot_cpu_has(X86_BUG_L1TF)) {
7866 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7867 if (r) {
7868 vmx_exit();
7869 return r;
7870 }
a47dd5f0 7871 }
25c5f225 7872
2965faa5 7873#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 7874 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7875 crash_vmclear_local_loaded_vmcss);
7876#endif
21ebf53b 7877 vmx_check_vmcs12_offsets();
8f536b76 7878
fdef3ad1 7879 return 0;
6aa8b732 7880}
a7b9020b 7881module_init(vmx_init);
Ubuntu Hirsute Linux kernel mirror