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KVM: fix error handling in svm_hardware_setup
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / vmx / vmx.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732
AK		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * Copyright (C) 2006 Qumranet, Inc.
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
6aa8b732
AK		 14 */
15
199b118a
SC		 16#include <linux/frame.h>
17#include <linux/highmem.h>
18#include <linux/hrtimer.h>
19#include <linux/kernel.h>
edf88417 20#include <linux/kvm_host.h>
6aa8b732 21#include <linux/module.h>
c7addb90 22#include <linux/moduleparam.h>
e9bda3b3 23#include <linux/mod_devicetable.h>
199b118a 24#include <linux/mm.h>
199b118a 25#include <linux/sched.h>
b284909a 26#include <linux/sched/smt.h>
5a0e3ad6 27#include <linux/slab.h>
cafd6659 28#include <linux/tboot.h>
199b118a 29#include <linux/trace_events.h>
e495606d 30
199b118a 31#include <asm/apic.h>
fd8ca6da 32#include <asm/asm.h>
28b835d6 33#include <asm/cpu.h>
199b118a 34#include <asm/debugreg.h>
3b3be0d1 35#include <asm/desc.h>
952f07ec 36#include <asm/fpu/internal.h>
199b118a 37#include <asm/io.h>
efc64404 38#include <asm/irq_remapping.h>
199b118a
SC		 39#include <asm/kexec.h>
40#include <asm/perf_event.h>
41#include <asm/mce.h>
d6e41f11 42#include <asm/mmu_context.h>
773e8a04 43#include <asm/mshyperv.h>
199b118a
SC		 44#include <asm/spec-ctrl.h>
45#include <asm/virtext.h>
46#include <asm/vmx.h>
6aa8b732 47
3077c191 48#include "capabilities.h"
199b118a 49#include "cpuid.h"
4cebd747 50#include "evmcs.h"
199b118a
SC		 51#include "irq.h"
52#include "kvm_cache_regs.h"
53#include "lapic.h"
54#include "mmu.h"
55d2375e 55#include "nested.h"
89b0c9f5 56#include "ops.h"
25462f7f 57#include "pmu.h"
199b118a 58#include "trace.h"
cb1d474b 59#include "vmcs.h"
609363cf 60#include "vmcs12.h"
89b0c9f5 61#include "vmx.h"
199b118a 62#include "x86.h"
229456fc 63
6aa8b732
AK		 64MODULE_AUTHOR("Qumranet");
65MODULE_LICENSE("GPL");
66
e9bda3b3
JT		 67static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
69 {}
70};
71MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
72
2c4fd91d 73bool __read_mostly enable_vpid = 1;
736caefe 74module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 75
d02fcf50
PB		 76static bool __read_mostly enable_vnmi = 1;
77module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
78
2c4fd91d 79bool __read_mostly flexpriority_enabled = 1;
736caefe 80module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 81
2c4fd91d 82bool __read_mostly enable_ept = 1;
736caefe 83module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 84
2c4fd91d 85bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 86module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
88
2c4fd91d 89bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 90module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
91
a27685c3 92static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 93module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 94
476bc001 95static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 96module_param(fasteoi, bool, S_IRUGO);
97
a4443267 98bool __read_mostly enable_apicv = 1;
01e439be 99module_param(enable_apicv, bool, S_IRUGO);
83d4c286 100
801d3424
NHE		 101/*
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
105 */
1e58e5e5 106static bool __read_mostly nested = 1;
801d3424
NHE		 107module_param(nested, bool, S_IRUGO);
108
2c4fd91d 109bool __read_mostly enable_pml = 1;
843e4330
KH		 110module_param_named(pml, enable_pml, bool, S_IRUGO);
111
6f2f8453
PB		 112static bool __read_mostly dump_invalid_vmcs = 0;
113module_param(dump_invalid_vmcs, bool, 0644);
114
904e14fb
PB		 115#define MSR_BITMAP_MODE_X2APIC 1
116#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 117
64903d61
HZ		 118#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
119
64672c95
YJ		 120/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
121static int __read_mostly cpu_preemption_timer_multi;
122static bool __read_mostly enable_preemption_timer = 1;
123#ifdef CONFIG_X86_64
124module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
125#endif
126
3de6347b 127#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 128#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
129#define KVM_VM_CR0_ALWAYS_ON \
130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 132#define KVM_CR4_GUEST_OWNED_BITS \
133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 135
5dc1f044 136#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 137#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
138#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
139
78ac8b47
AK		 140#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
141
bf8c55d8
CP		 142#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
145 RTIT_STATUS_BYTECNT))
146
147#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
149
4b8d54f9
ZE		 150/*
151 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
152 * ple_gap: upper bound on the amount of time between two successive
153 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 154 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 155 * ple_window: upper bound on the amount of time a guest is allowed to execute
156 * in a PAUSE loop. Tests indicate that most spinlocks are held for
157 * less than 2^12 cycles
158 * Time is measured based on a counter that runs at the same rate as the TSC,
159 * refer SDM volume 3b section 21.6.13 & 22.1.3.
160 */
c8e88717 161static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 162module_param(ple_gap, uint, 0444);
b4a2d31d 163
7fbc85a5
BM		 164static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
165module_param(ple_window, uint, 0444);
4b8d54f9 166
b4a2d31d 167/* Default doubles per-vcpu window every exit. */
c8e88717 168static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 169module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 170
171/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 172static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 173module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 174
175/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 176static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177module_param(ple_window_max, uint, 0444);
b4a2d31d 178
f99e3daf
CP		 179/* Default is SYSTEM mode, 1 for host-guest mode */
180int __read_mostly pt_mode = PT_MODE_SYSTEM;
181module_param(pt_mode, int, S_IRUGO);
182
a399477e 183static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 184static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 185static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 186
7db92e16
TG		 187/* Storage for pre module init parameter parsing */
188static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 189
190static const struct {
191 const char *option;
0027ff2a 192 bool for_parse;
a399477e 193} vmentry_l1d_param[] = {
0027ff2a
PB		 194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
196 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 200};
201
7db92e16
TG		 202#define L1D_CACHE_ORDER 4
203static void *vmx_l1d_flush_pages;
204
205static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 206{
7db92e16 207 struct page *page;
288d152c 208 unsigned int i;
a399477e 209
19a36d32
WL		 210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
212 return 0;
213 }
214
7db92e16
TG		 215 if (!enable_ept) {
216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
217 return 0;
a399477e
KRW		 218 }
219
d806afa4
YW		 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
221 u64 msr;
222
223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
226 return 0;
227 }
228 }
8e0b2b91 229
d90a7a0e
JK		 230 /* If set to auto use the default l1tf mitigation method */
231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
232 switch (l1tf_mitigation) {
233 case L1TF_MITIGATION_OFF:
234 l1tf = VMENTER_L1D_FLUSH_NEVER;
235 break;
236 case L1TF_MITIGATION_FLUSH_NOWARN:
237 case L1TF_MITIGATION_FLUSH:
238 case L1TF_MITIGATION_FLUSH_NOSMT:
239 l1tf = VMENTER_L1D_FLUSH_COND;
240 break;
241 case L1TF_MITIGATION_FULL:
242 case L1TF_MITIGATION_FULL_FORCE:
243 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
244 break;
245 }
246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 }
249
7db92e16
TG		 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 252 /*
253 * This allocation for vmx_l1d_flush_pages is not tied to a VM
254 * lifetime and so should not be charged to a memcg.
255 */
7db92e16
TG		 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
257 if (!page)
258 return -ENOMEM;
259 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 260
261 /*
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
265 */
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
268 PAGE_SIZE);
269 }
7db92e16
TG		 270 }
271
272 l1tf_vmx_mitigation = l1tf;
273
895ae47f
TG		 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
276 else
277 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 278
427362a1
NS		 279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 281 else
427362a1 282 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 283 return 0;
284}
285
286static int vmentry_l1d_flush_parse(const char *s)
287{
288 unsigned int i;
289
290 if (s) {
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
294 return i;
7db92e16
TG		 295 }
296 }
a399477e
KRW		 297 return -EINVAL;
298}
299
7db92e16
TG		 300static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301{
dd4bfa73 302 int l1tf, ret;
7db92e16 303
7db92e16
TG		 304 l1tf = vmentry_l1d_flush_parse(s);
305 if (l1tf < 0)
306 return l1tf;
307
0027ff2a
PB		 308 if (!boot_cpu_has(X86_BUG_L1TF))
309 return 0;
310
7db92e16
TG		 311 /*
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
315 * established.
316 */
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
319 return 0;
320 }
321
dd4bfa73
TG		 322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
325 return ret;
7db92e16
TG		 326}
327
a399477e
KRW		 328static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
329{
0027ff2a
PB		 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
332
7db92e16 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 334}
335
336static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
339};
895ae47f 340module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 341
d99e4152
GN		 342static bool guest_state_valid(struct kvm_vcpu *vcpu);
343static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 344static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 345 u32 msr, int type);
75880a01 346
453eafbe
SC		 347void vmx_vmexit(void);
348
52a9fcbc
SC		 349#define vmx_insn_failed(fmt...) \
350do { \
351 WARN_ONCE(1, fmt); \
352 pr_warn_ratelimited(fmt); \
353} while (0)
354
6e202097
SC		 355asmlinkage void vmread_error(unsigned long field, bool fault)
356{
357 if (fault)
358 kvm_spurious_fault();
359 else
360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
361}
362
52a9fcbc
SC		 363noinline void vmwrite_error(unsigned long field, unsigned long value)
364{
365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
367}
368
369noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
370{
371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
372}
373
374noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
375{
376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
377}
378
379noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
380{
381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
382 ext, vpid, gva);
383}
384
385noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
386{
387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
388 ext, eptp, gpa);
389}
390
6aa8b732 391static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 392DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 393/*
394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
396 */
397static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 398
bf9f6ac8
FW		 399/*
400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
401 * can find which vCPU should be waken up.
402 */
403static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
404static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
405
2384d2b3
SY		 406static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
407static DEFINE_SPINLOCK(vmx_vpid_lock);
408
3077c191
SC		 409struct vmcs_config vmcs_config;
410struct vmx_capability vmx_capability;
d56f546d 411
6aa8b732
AK		 412#define VMX_SEGMENT_FIELD(seg) \
413 [VCPU_SREG_##seg] = { \
414 .selector = GUEST_##seg##_SELECTOR, \
415 .base = GUEST_##seg##_BASE, \
416 .limit = GUEST_##seg##_LIMIT, \
417 .ar_bytes = GUEST_##seg##_AR_BYTES, \
418 }
419
772e0318 420static const struct kvm_vmx_segment_field {
6aa8b732
AK		 421 unsigned selector;
422 unsigned base;
423 unsigned limit;
424 unsigned ar_bytes;
425} kvm_vmx_segment_fields[] = {
426 VMX_SEGMENT_FIELD(CS),
427 VMX_SEGMENT_FIELD(DS),
428 VMX_SEGMENT_FIELD(ES),
429 VMX_SEGMENT_FIELD(FS),
430 VMX_SEGMENT_FIELD(GS),
431 VMX_SEGMENT_FIELD(SS),
432 VMX_SEGMENT_FIELD(TR),
433 VMX_SEGMENT_FIELD(LDTR),
434};
435
cf3646eb 436u64 host_efer;
2342080c 437static unsigned long host_idt_base;
26bb0981 438
4d56c8a7 439/*
898a811f
JM		 440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
441 * will emulate SYSCALL in legacy mode if the vendor string in guest
442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
443 * support this emulation, IA32_STAR must always be included in
444 * vmx_msr_index[], even in i386 builds.
4d56c8a7 445 */
cf3646eb 446const u32 vmx_msr_index[] = {
05b3e0c2 447#ifdef CONFIG_X86_64
44ea2b17 448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 449#endif
8c06585d 450 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
c11f83e0 451 MSR_IA32_TSX_CTRL,
6aa8b732 452};
6aa8b732 453
773e8a04
VK		 454#if IS_ENABLED(CONFIG_HYPERV)
455static bool __read_mostly enlightened_vmcs = true;
456module_param(enlightened_vmcs, bool, 0444);
457
877ad952
TL		 458/* check_ept_pointer() should be under protection of ept_pointer_lock. */
459static void check_ept_pointer_match(struct kvm *kvm)
460{
461 struct kvm_vcpu *vcpu;
462 u64 tmp_eptp = INVALID_PAGE;
463 int i;
464
465 kvm_for_each_vcpu(i, vcpu, kvm) {
466 if (!VALID_PAGE(tmp_eptp)) {
467 tmp_eptp = to_vmx(vcpu)->ept_pointer;
468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
469 to_kvm_vmx(kvm)->ept_pointers_match
470 = EPT_POINTERS_MISMATCH;
471 return;
472 }
473 }
474
475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
476}
477
8997f657 478static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 479 void *data)
480{
481 struct kvm_tlb_range *range = data;
482
483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
484 range->pages);
485}
486
487static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
489{
490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
491
492 /*
493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
494 * of the base of EPT PML4 table, strip off EPT configuration
495 * information.
496 */
497 if (range)
498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
499 kvm_fill_hv_flush_list_func, (void *)range);
500 else
501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
502}
503
504static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
505 struct kvm_tlb_range *range)
877ad952 506{
a5c214da 507 struct kvm_vcpu *vcpu;
b7c1c226 508 int ret = 0, i;
877ad952
TL		 509
510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
511
512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
513 check_ept_pointer_match(kvm);
514
515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 516 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 517 /* If ept_pointer is invalid pointer, bypass flush request. */
518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
519 ret |= __hv_remote_flush_tlb_with_range(
520 kvm, vcpu, range);
53963a70 521 }
a5c214da 522 } else {
1f3a3e46
LT		 523 ret = __hv_remote_flush_tlb_with_range(kvm,
524 kvm_get_vcpu(kvm, 0), range);
877ad952 525 }
877ad952 526
877ad952
TL		 527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
528 return ret;
529}
1f3a3e46
LT		 530static int hv_remote_flush_tlb(struct kvm *kvm)
531{
532 return hv_remote_flush_tlb_with_range(kvm, NULL);
533}
534
6f6a657c
VK		 535static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
536{
537 struct hv_enlightened_vmcs *evmcs;
538 struct hv_partition_assist_pg **p_hv_pa_pg =
539 &vcpu->kvm->arch.hyperv.hv_pa_pg;
540 /*
541 * Synthetic VM-Exit is not enabled in current code and so All
542 * evmcs in singe VM shares same assist page.
543 */
cab01850 544 if (!*p_hv_pa_pg)
6f6a657c 545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
cab01850
VK		 546
547 if (!*p_hv_pa_pg)
548 return -ENOMEM;
6f6a657c
VK		 549
550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
551
552 evmcs->partition_assist_page =
553 __pa(*p_hv_pa_pg);
cab01850 554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
6f6a657c
VK		 555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
556
6f6a657c
VK		 557 return 0;
558}
559
773e8a04
VK		 560#endif /* IS_ENABLED(CONFIG_HYPERV) */
561
64672c95
YJ		 562/*
563 * Comment's format: document - errata name - stepping - processor name.
564 * Refer from
565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
566 */
567static u32 vmx_preemption_cpu_tfms[] = {
568/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
5690x000206E6,
570/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
571/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
572/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5730x00020652,
574/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5750x00020655,
576/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
577/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
578/*
579 * 320767.pdf - AAP86 - B1 -
580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
581 */
5820x000106E5,
583/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5840x000106A0,
585/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5860x000106A1,
587/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5880x000106A4,
589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5920x000106A5,
3d82c565
WH		 593 /* Xeon E3-1220 V2 */
5940x000306A8,
64672c95
YJ		 595};
596
597static inline bool cpu_has_broken_vmx_preemption_timer(void)
598{
599 u32 eax = cpuid_eax(0x00000001), i;
600
601 /* Clear the reserved bits */
602 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 604 if (eax == vmx_preemption_cpu_tfms[i])
605 return true;
606
607 return false;
608}
609
35754c98 610static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 611{
35754c98 612 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 613}
614
04547156
SY		 615static inline bool report_flexpriority(void)
616{
617 return flexpriority_enabled;
618}
619
97b7ead3 620static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 621{
622 int i;
623
a2fa3e9f 624 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 626 return i;
627 return -1;
628}
629
97b7ead3 630struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 631{
632 int i;
633
8b9cf98c 634 i = __find_msr_index(vmx, msr);
a75beee6 635 if (i >= 0)
a2fa3e9f 636 return &vmx->guest_msrs[i];
8b6d44c7 637 return NULL;
7725f0ba
AK		 638}
639
b07a5c53
PB		 640static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
641{
642 int ret = 0;
643
644 u64 old_msr_data = msr->data;
645 msr->data = data;
646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
647 preempt_disable();
648 ret = kvm_set_shared_msr(msr->index, msr->data,
649 msr->mask);
650 preempt_enable();
651 if (ret)
652 msr->data = old_msr_data;
653 }
654 return ret;
655}
656
7c97fcb3
SC		 657void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
658{
659 vmcs_clear(loaded_vmcs->vmcs);
660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
661 vmcs_clear(loaded_vmcs->shadow_vmcs);
662 loaded_vmcs->cpu = -1;
663 loaded_vmcs->launched = 0;
664}
665
2965faa5 666#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 667/*
668 * This bitmap is used to indicate whether the vmclear
669 * operation is enabled on all cpus. All disabled by
670 * default.
671 */
672static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
673
674static inline void crash_enable_local_vmclear(int cpu)
675{
676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
677}
678
679static inline void crash_disable_local_vmclear(int cpu)
680{
681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
682}
683
684static inline int crash_local_vmclear_enabled(int cpu)
685{
686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
687}
688
689static void crash_vmclear_local_loaded_vmcss(void)
690{
691 int cpu = raw_smp_processor_id();
692 struct loaded_vmcs *v;
693
694 if (!crash_local_vmclear_enabled(cpu))
695 return;
696
697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
698 loaded_vmcss_on_cpu_link)
699 vmcs_clear(v->vmcs);
700}
701#else
702static inline void crash_enable_local_vmclear(int cpu) { }
703static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 704#endif /* CONFIG_KEXEC_CORE */
8f536b76 705
d462b819 706static void __loaded_vmcs_clear(void *arg)
6aa8b732 707{
d462b819 708 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 709 int cpu = raw_smp_processor_id();
6aa8b732 710
d462b819
NHE		 711 if (loaded_vmcs->cpu != cpu)
712 return; /* vcpu migration can race with cpu offline */
713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 714 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 715 crash_disable_local_vmclear(cpu);
d462b819 716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 717
718 /*
719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
720 * is before setting loaded_vmcs->vcpu to -1 which is done in
721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
722 * then adds the vmcs into percpu list before it is deleted.
723 */
724 smp_wmb();
725
d462b819 726 loaded_vmcs_init(loaded_vmcs);
8f536b76 727 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 728}
729
89b0c9f5 730void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 731{
e6c7d321
XG		 732 int cpu = loaded_vmcs->cpu;
733
734 if (cpu != -1)
735 smp_call_function_single(cpu,
736 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 737}
738
2fb92db1
AK		 739static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
740 unsigned field)
741{
742 bool ret;
743 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
744
cb3c1e2f
SC		 745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
2fb92db1
AK		 747 vmx->segment_cache.bitmask = 0;
748 }
749 ret = vmx->segment_cache.bitmask & mask;
750 vmx->segment_cache.bitmask |= mask;
751 return ret;
752}
753
754static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
755{
756 u16 *p = &vmx->segment_cache.seg[seg].selector;
757
758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
760 return *p;
761}
762
763static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
764{
765 ulong *p = &vmx->segment_cache.seg[seg].base;
766
767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
769 return *p;
770}
771
772static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
773{
774 u32 *p = &vmx->segment_cache.seg[seg].limit;
775
776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
778 return *p;
779}
780
781static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
782{
783 u32 *p = &vmx->segment_cache.seg[seg].ar;
784
785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
787 return *p;
788}
789
97b7ead3 790void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 791{
792 u32 eb;
793
fd7373cc 794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 795 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 796 /*
797 * Guest access to VMware backdoor ports could legitimately
798 * trigger #GP because of TSS I/O permission bitmap.
799 * We intercept those #GP and allow access to them anyway
800 * as VMware does.
801 */
802 if (enable_vmware_backdoor)
803 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 804 if ((vcpu->guest_debug &
805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
807 eb |= 1u << BP_VECTOR;
7ffd92c5 808 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 809 eb = ~0;
089d034e 810 if (enable_ept)
1439442c 811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 812
813 /* When we are running a nested L2 guest and L1 specified for it a
814 * certain exception bitmap, we must trap the same exceptions and pass
815 * them to L1. When running L2, we will only handle the exceptions
816 * specified above if L1 did not want them.
817 */
818 if (is_guest_mode(vcpu))
819 eb |= get_vmcs12(vcpu)->exception_bitmap;
820
abd3f2d6
AK		 821 vmcs_write32(EXCEPTION_BITMAP, eb);
822}
823
d28b387f
KA		 824/*
825 * Check if MSR is intercepted for currently loaded MSR bitmap.
826 */
827static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
828{
829 unsigned long *msr_bitmap;
830 int f = sizeof(unsigned long);
831
832 if (!cpu_has_vmx_msr_bitmap())
833 return true;
834
835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
836
837 if (msr <= 0x1fff) {
838 return !!test_bit(msr, msr_bitmap + 0x800 / f);
839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
840 msr &= 0x1fff;
841 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
842 }
843
844 return true;
845}
846
2961e876
GN		 847static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
848 unsigned long entry, unsigned long exit)
8bf00a52 849{
2961e876
GN		 850 vm_entry_controls_clearbit(vmx, entry);
851 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 852}
853
662f1d1d 854int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
ca83b4a7
KRW		 855{
856 unsigned int i;
857
858 for (i = 0; i < m->nr; ++i) {
859 if (m->val[i].index == msr)
860 return i;
861 }
862 return -ENOENT;
863}
864
61d2ef2c
AK		 865static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
866{
ca83b4a7 867 int i;
61d2ef2c
AK		 868 struct msr_autoload *m = &vmx->msr_autoload;
869
8bf00a52
GN		 870 switch (msr) {
871 case MSR_EFER:
c73da3fc 872 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 873 clear_atomic_switch_msr_special(vmx,
874 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 875 VM_EXIT_LOAD_IA32_EFER);
876 return;
877 }
878 break;
879 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 880 if (cpu_has_load_perf_global_ctrl()) {
2961e876 881 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
884 return;
885 }
886 break;
110312c8 887 }
ef0fbcac 888 i = vmx_find_msr_index(&m->guest, msr);
ca83b4a7 889 if (i < 0)
31907093 890 goto skip_guest;
33966dd6 891 --m->guest.nr;
33966dd6 892 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 894
31907093 895skip_guest:
ef0fbcac 896 i = vmx_find_msr_index(&m->host, msr);
31907093 897 if (i < 0)
61d2ef2c 898 return;
31907093
KRW		 899
900 --m->host.nr;
901 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 903}
904
2961e876
GN		 905static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
906 unsigned long entry, unsigned long exit,
907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
908 u64 guest_val, u64 host_val)
8bf00a52
GN		 909{
910 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 911 if (host_val_vmcs != HOST_IA32_EFER)
912 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 913 vm_entry_controls_setbit(vmx, entry);
914 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 915}
916
61d2ef2c 917static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 918 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 919{
989e3992 920 int i, j = 0;
61d2ef2c
AK		 921 struct msr_autoload *m = &vmx->msr_autoload;
922
8bf00a52
GN		 923 switch (msr) {
924 case MSR_EFER:
c73da3fc 925 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 926 add_atomic_switch_msr_special(vmx,
927 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 928 VM_EXIT_LOAD_IA32_EFER,
929 GUEST_IA32_EFER,
930 HOST_IA32_EFER,
931 guest_val, host_val);
932 return;
933 }
934 break;
935 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 936 if (cpu_has_load_perf_global_ctrl()) {
2961e876 937 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
940 GUEST_IA32_PERF_GLOBAL_CTRL,
941 HOST_IA32_PERF_GLOBAL_CTRL,
942 guest_val, host_val);
943 return;
944 }
945 break;
7099e2e1
RK		 946 case MSR_IA32_PEBS_ENABLE:
947 /* PEBS needs a quiescent period after being disabled (to write
948 * a record). Disabling PEBS through VMX MSR swapping doesn't
949 * provide that period, so a CPU could write host's record into
950 * guest's memory.
951 */
952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 953 }
954
ef0fbcac 955 i = vmx_find_msr_index(&m->guest, msr);
989e3992 956 if (!entry_only)
ef0fbcac 957 j = vmx_find_msr_index(&m->host, msr);
61d2ef2c 958
7cfe0526
AL		 959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
60266204 961 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 962 "Can't add msr %x\n", msr);
963 return;
61d2ef2c 964 }
31907093 965 if (i < 0) {
ca83b4a7 966 i = m->guest.nr++;
33966dd6 967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 968 }
989e3992
KRW		 969 m->guest.val[i].index = msr;
970 m->guest.val[i].value = guest_val;
971
972 if (entry_only)
973 return;
61d2ef2c 974
31907093
KRW		 975 if (j < 0) {
976 j = m->host.nr++;
33966dd6 977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 978 }
31907093
KRW		 979 m->host.val[j].index = msr;
980 m->host.val[j].value = host_val;
61d2ef2c
AK		 981}
982
92c0d900 983static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 984{
844a5fe2
PB		 985 u64 guest_efer = vmx->vcpu.arch.efer;
986 u64 ignore_bits = 0;
987
9167ab79
PB		 988 /* Shadow paging assumes NX to be available. */
989 if (!enable_ept)
990 guest_efer |= EFER_NX;
3a34a881 991
51c6cf66 992 /*
844a5fe2 993 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 994 */
844a5fe2 995 ignore_bits |= EFER_SCE;
51c6cf66
AK		 996#ifdef CONFIG_X86_64
997 ignore_bits |= EFER_LMA | EFER_LME;
998 /* SCE is meaningful only in long mode on Intel */
999 if (guest_efer & EFER_LMA)
1000 ignore_bits &= ~(u64)EFER_SCE;
1001#endif
84ad33ef 1002
f6577a5f
AL		 1003 /*
1004 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1005 * On CPUs that support "load IA32_EFER", always switch EFER
1006 * atomically, since it's faster than switching it manually.
1007 */
c73da3fc 1008 if (cpu_has_load_ia32_efer() ||
f6577a5f 1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1010 if (!(guest_efer & EFER_LMA))
1011 guest_efer &= ~EFER_LME;
54b98bff
AL		 1012 if (guest_efer != host_efer)
1013 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 1014 guest_efer, host_efer, false);
02343cf2
SC		 1015 else
1016 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 1017 return false;
844a5fe2 1018 } else {
02343cf2
SC		 1019 clear_atomic_switch_msr(vmx, MSR_EFER);
1020
844a5fe2
PB		 1021 guest_efer &= ~ignore_bits;
1022 guest_efer |= host_efer & ignore_bits;
1023
1024 vmx->guest_msrs[efer_offset].data = guest_efer;
1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 1026
844a5fe2
PB		 1027 return true;
1028 }
51c6cf66
AK		 1029}
1030
e28baead
AL		 1031#ifdef CONFIG_X86_32
1032/*
1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1034 * VMCS rather than the segment table. KVM uses this helper to figure
1035 * out the current bases to poke them into the VMCS before entry.
1036 */
2d49ec72
GN		 1037static unsigned long segment_base(u16 selector)
1038{
8c2e41f7 1039 struct desc_struct *table;
2d49ec72
GN		 1040 unsigned long v;
1041
8c2e41f7 1042 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1043 return 0;
1044
45fc8757 1045 table = get_current_gdt_ro();
2d49ec72 1046
8c2e41f7 1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 1048 u16 ldt_selector = kvm_read_ldt();
1049
8c2e41f7 1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 1051 return 0;
1052
8c2e41f7 1053 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 1054 }
8c2e41f7 1055 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 1056 return v;
1057}
e28baead 1058#endif
2d49ec72 1059
e348ac7c
SC		 1060static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1061{
1062 return (pt_mode == PT_MODE_HOST_GUEST) &&
1063 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1064}
1065
2ef444f1
CP		 1066static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1067{
1068 u32 i;
1069
1070 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1071 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1072 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1073 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1074 for (i = 0; i < addr_range; i++) {
1075 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1076 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1077 }
1078}
1079
1080static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1081{
1082 u32 i;
1083
1084 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1085 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1086 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1087 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1088 for (i = 0; i < addr_range; i++) {
1089 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1090 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1091 }
1092}
1093
1094static void pt_guest_enter(struct vcpu_vmx *vmx)
1095{
1096 if (pt_mode == PT_MODE_SYSTEM)
1097 return;
1098
2ef444f1 1099 /*
b08c2896
CP		 1100 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1101 * Save host state before VM entry.
2ef444f1 1102 */
b08c2896 1103 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1104 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1105 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1106 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1107 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1108 }
1109}
1110
1111static void pt_guest_exit(struct vcpu_vmx *vmx)
1112{
1113 if (pt_mode == PT_MODE_SYSTEM)
1114 return;
1115
1116 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1117 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1118 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1119 }
1120
1121 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1122 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1123}
1124
13b964a2
SC		 1125void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1126 unsigned long fs_base, unsigned long gs_base)
1127{
1128 if (unlikely(fs_sel != host->fs_sel)) {
1129 if (!(fs_sel & 7))
1130 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1131 else
1132 vmcs_write16(HOST_FS_SELECTOR, 0);
1133 host->fs_sel = fs_sel;
1134 }
1135 if (unlikely(gs_sel != host->gs_sel)) {
1136 if (!(gs_sel & 7))
1137 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1138 else
1139 vmcs_write16(HOST_GS_SELECTOR, 0);
1140 host->gs_sel = gs_sel;
1141 }
1142 if (unlikely(fs_base != host->fs_base)) {
1143 vmcs_writel(HOST_FS_BASE, fs_base);
1144 host->fs_base = fs_base;
1145 }
1146 if (unlikely(gs_base != host->gs_base)) {
1147 vmcs_writel(HOST_GS_BASE, gs_base);
1148 host->gs_base = gs_base;
1149 }
1150}
1151
97b7ead3 1152void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1153{
04d2cc77 1154 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1155 struct vmcs_host_state *host_state;
51e8a8cc 1156#ifdef CONFIG_X86_64
35060ed6 1157 int cpu = raw_smp_processor_id();
51e8a8cc 1158#endif
e368b875
SC		 1159 unsigned long fs_base, gs_base;
1160 u16 fs_sel, gs_sel;
26bb0981 1161 int i;
04d2cc77 1162
d264ee0c
SC		 1163 vmx->req_immediate_exit = false;
1164
f48b4711
LA		 1165 /*
1166 * Note that guest MSRs to be saved/restored can also be changed
1167 * when guest state is loaded. This happens when guest transitions
1168 * to/from long-mode by setting MSR_EFER.LMA.
1169 */
b464f57e
PB		 1170 if (!vmx->guest_msrs_ready) {
1171 vmx->guest_msrs_ready = true;
f48b4711
LA		 1172 for (i = 0; i < vmx->save_nmsrs; ++i)
1173 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1174 vmx->guest_msrs[i].data,
1175 vmx->guest_msrs[i].mask);
1176
1177 }
c9dfd3fb 1178
1179 if (vmx->nested.need_vmcs12_to_shadow_sync)
1180 nested_sync_vmcs12_to_shadow(vcpu);
1181
b464f57e 1182 if (vmx->guest_state_loaded)
33ed6329
AK		 1183 return;
1184
b464f57e 1185 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1186
33ed6329
AK		 1187 /*
1188 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1189 * allow segment selectors with cpl > 0 or ti == 1.
1190 */
d7ee039e 1191 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1192
1193#ifdef CONFIG_X86_64
d7ee039e
SC		 1194 savesegment(ds, host_state->ds_sel);
1195 savesegment(es, host_state->es_sel);
e368b875
SC		 1196
1197 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1198 if (likely(is_64bit_mm(current->mm))) {
1199 save_fsgs_for_kvm();
e368b875
SC		 1200 fs_sel = current->thread.fsindex;
1201 gs_sel = current->thread.gsindex;
b062b794 1202 fs_base = current->thread.fsbase;
e368b875 1203 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1204 } else {
e368b875
SC		 1205 savesegment(fs, fs_sel);
1206 savesegment(gs, gs_sel);
b062b794 1207 fs_base = read_msr(MSR_FS_BASE);
e368b875 1208 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1209 }
b2da15ac 1210
4679b61f 1211 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1212#else
e368b875
SC		 1213 savesegment(fs, fs_sel);
1214 savesegment(gs, gs_sel);
1215 fs_base = segment_base(fs_sel);
1216 gs_base = segment_base(gs_sel);
707c0874 1217#endif
e368b875 1218
13b964a2 1219 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
b464f57e 1220 vmx->guest_state_loaded = true;
33ed6329
AK		 1221}
1222
6d6095bd 1223static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1224{
d7ee039e
SC		 1225 struct vmcs_host_state *host_state;
1226
b464f57e 1227 if (!vmx->guest_state_loaded)
33ed6329
AK		 1228 return;
1229
b464f57e 1230 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1231
e1beb1d3 1232 ++vmx->vcpu.stat.host_state_reload;
bd9966de 1233
c8770e7b 1234#ifdef CONFIG_X86_64
4679b61f 1235 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1236#endif
d7ee039e
SC		 1237 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1238 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1239#ifdef CONFIG_X86_64
d7ee039e 1240 load_gs_index(host_state->gs_sel);
9581d442 1241#else
d7ee039e 1242 loadsegment(gs, host_state->gs_sel);
33ed6329 1243#endif
33ed6329 1244 }
d7ee039e
SC		 1245 if (host_state->fs_sel & 7)
1246 loadsegment(fs, host_state->fs_sel);
b2da15ac 1247#ifdef CONFIG_X86_64
d7ee039e
SC		 1248 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1249 loadsegment(ds, host_state->ds_sel);
1250 loadsegment(es, host_state->es_sel);
b2da15ac 1251 }
b2da15ac 1252#endif
b7ffc44d 1253 invalidate_tss_limit();
44ea2b17 1254#ifdef CONFIG_X86_64
c8770e7b 1255 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1256#endif
45fc8757 1257 load_fixmap_gdt(raw_smp_processor_id());
b464f57e
PB		 1258 vmx->guest_state_loaded = false;
1259 vmx->guest_msrs_ready = false;
33ed6329
AK		 1260}
1261
678e315e
SC		 1262#ifdef CONFIG_X86_64
1263static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1264{
4679b61f 1265 preempt_disable();
b464f57e 1266 if (vmx->guest_state_loaded)
4679b61f
PB		 1267 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1268 preempt_enable();
678e315e 1269 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1270}
1271
678e315e
SC		 1272static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1273{
4679b61f 1274 preempt_disable();
b464f57e 1275 if (vmx->guest_state_loaded)
4679b61f
PB		 1276 wrmsrl(MSR_KERNEL_GS_BASE, data);
1277 preempt_enable();
678e315e
SC		 1278 vmx->msr_guest_kernel_gs_base = data;
1279}
1280#endif
1281
28b835d6
FW		 1282static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1283{
1284 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1285 struct pi_desc old, new;
1286 unsigned int dest;
1287
31afb2ea
PB		 1288 /*
1289 * In case of hot-plug or hot-unplug, we may have to undo
1290 * vmx_vcpu_pi_put even if there is no assigned device. And we
1291 * always keep PI.NDST up to date for simplicity: it makes the
1292 * code easier, and CPU migration is not a fast path.
1293 */
1294 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1295 return;
1296
132194ff
JM		 1297 /*
1298 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1299 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1300 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1301 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1302 * correctly.
1303 */
1304 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1305 pi_clear_sn(pi_desc);
1306 goto after_clear_sn;
1307 }
1308
31afb2ea 1309 /* The full case. */
28b835d6
FW		 1310 do {
1311 old.control = new.control = pi_desc->control;
1312
31afb2ea 1313 dest = cpu_physical_id(cpu);
28b835d6 1314
31afb2ea
PB		 1315 if (x2apic_enabled())
1316 new.ndst = dest;
1317 else
1318 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1319
28b835d6 1320 new.sn = 0;
c0a1666b
PB		 1321 } while (cmpxchg64(&pi_desc->control, old.control,
1322 new.control) != old.control);
c112b5f5 1323
132194ff
JM		 1324after_clear_sn:
1325
c112b5f5
LK		 1326 /*
1327 * Clear SN before reading the bitmap. The VT-d firmware
1328 * writes the bitmap and reads SN atomically (5.2.3 in the
1329 * spec), so it doesn't really have a memory barrier that
1330 * pairs with this, but we cannot do that and we need one.
1331 */
1332 smp_mb__after_atomic();
1333
29881b6e 1334 if (!pi_is_pir_empty(pi_desc))
c112b5f5 1335 pi_set_on(pi_desc);
28b835d6 1336}
1be0e61c 1337
8ef863e6 1338void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1339{
a2fa3e9f 1340 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1341 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1342
b80c76ec 1343 if (!already_loaded) {
fe0e80be 1344 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1345 local_irq_disable();
8f536b76 1346 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1347
1348 /*
1349 * Read loaded_vmcs->cpu should be before fetching
1350 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1351 * See the comments in __loaded_vmcs_clear().
1352 */
1353 smp_rmb();
1354
d462b819
NHE		 1355 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1356 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1357 crash_enable_local_vmclear(cpu);
92fe13be 1358 local_irq_enable();
b80c76ec
JM		 1359 }
1360
1361 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1362 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1363 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1364 indirect_branch_prediction_barrier();
b80c76ec
JM		 1365 }
1366
1367 if (!already_loaded) {
59c58ceb 1368 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1369 unsigned long sysenter_esp;
1370
1371 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1372
6aa8b732
AK		 1373 /*
1374 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1375 * processors. See 22.2.4.
6aa8b732 1376 */
e0c23063 1377 vmcs_writel(HOST_TR_BASE,
72f5e08d 1378 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1379 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732
AK		 1380
1381 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1382 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1383
d462b819 1384 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1385 }
28b835d6 1386
2680d6da
OH		 1387 /* Setup TSC multiplier */
1388 if (kvm_has_tsc_control &&
c95ba92a
PF		 1389 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1390 decache_tsc_multiplier(vmx);
8ef863e6
SC		 1391}
1392
1393/*
1394 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1395 * vcpu mutex is already taken.
1396 */
1397void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1398{
1399 struct vcpu_vmx *vmx = to_vmx(vcpu);
1400
1401 vmx_vcpu_load_vmcs(vcpu, cpu);
2680d6da 1402
28b835d6 1403 vmx_vcpu_pi_load(vcpu, cpu);
8ef863e6 1404
1be0e61c 1405 vmx->host_pkru = read_pkru();
74c55931 1406 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1407}
1408
1409static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1410{
1411 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1412
1413 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1414 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1415 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1416 return;
1417
1418 /* Set SN when the vCPU is preempted */
1419 if (vcpu->preempted)
1420 pi_set_sn(pi_desc);
6aa8b732
AK		 1421}
1422
13b964a2 1423static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1424{
28b835d6
FW		 1425 vmx_vcpu_pi_put(vcpu);
1426
6d6095bd 1427 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1428}
1429
f244deed
WL		 1430static bool emulation_required(struct kvm_vcpu *vcpu)
1431{
1432 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1433}
1434
97b7ead3 1435unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1436{
e7bddc52 1437 struct vcpu_vmx *vmx = to_vmx(vcpu);
78ac8b47 1438 unsigned long rflags, save_rflags;
345dcaa8 1439
cb3c1e2f
SC		 1440 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1441 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
6de12732 1442 rflags = vmcs_readl(GUEST_RFLAGS);
e7bddc52 1443 if (vmx->rmode.vm86_active) {
6de12732 1444 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
e7bddc52 1445 save_rflags = vmx->rmode.save_rflags;
6de12732
AK		 1446 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1447 }
e7bddc52 1448 vmx->rflags = rflags;
78ac8b47 1449 }
e7bddc52 1450 return vmx->rflags;
6aa8b732
AK		 1451}
1452
97b7ead3 1453void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1454{
e7bddc52 1455 struct vcpu_vmx *vmx = to_vmx(vcpu);
491c1ad1 1456 unsigned long old_rflags;
f244deed 1457
491c1ad1 1458 if (enable_unrestricted_guest) {
cb3c1e2f 1459 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
491c1ad1
SC		 1460 vmx->rflags = rflags;
1461 vmcs_writel(GUEST_RFLAGS, rflags);
1462 return;
1463 }
1464
1465 old_rflags = vmx_get_rflags(vcpu);
e7bddc52
SC		 1466 vmx->rflags = rflags;
1467 if (vmx->rmode.vm86_active) {
1468 vmx->rmode.save_rflags = rflags;
053de044 1469 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1470 }
6aa8b732 1471 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed 1472
e7bddc52
SC		 1473 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1474 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1475}
1476
97b7ead3 1477u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1478{
1479 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1480 int ret = 0;
1481
1482 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1483 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1484 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1485 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1486
37ccdcbe 1487 return ret;
2809f5d2
GC		 1488}
1489
97b7ead3 1490void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1491{
1492 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1493 u32 interruptibility = interruptibility_old;
1494
1495 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1496
48005f64 1497 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1498 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1499 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1500 interruptibility |= GUEST_INTR_STATE_STI;
1501
1502 if ((interruptibility != interruptibility_old))
1503 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1504}
1505
bf8c55d8
CP		 1506static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1507{
1508 struct vcpu_vmx *vmx = to_vmx(vcpu);
1509 unsigned long value;
1510
1511 /*
1512 * Any MSR write that attempts to change bits marked reserved will
1513 * case a #GP fault.
1514 */
1515 if (data & vmx->pt_desc.ctl_bitmask)
1516 return 1;
1517
1518 /*
1519 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1520 * result in a #GP unless the same write also clears TraceEn.
1521 */
1522 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1523 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1524 return 1;
1525
1526 /*
1527 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1528 * and FabricEn would cause #GP, if
1529 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1530 */
1531 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1532 !(data & RTIT_CTL_FABRIC_EN) &&
1533 !intel_pt_validate_cap(vmx->pt_desc.caps,
1534 PT_CAP_single_range_output))
1535 return 1;
1536
1537 /*
1538 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1539 * utilize encodings marked reserved will casue a #GP fault.
1540 */
1541 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1542 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1543 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1544 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1545 return 1;
1546 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1547 PT_CAP_cycle_thresholds);
1548 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1549 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1550 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1551 return 1;
1552 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1553 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1554 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1555 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1556 return 1;
1557
1558 /*
1559 * If ADDRx_CFG is reserved or the encodings is >2 will
1560 * cause a #GP fault.
1561 */
1562 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1563 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1564 return 1;
1565 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1566 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1567 return 1;
1568 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1569 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1570 return 1;
1571 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1572 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1573 return 1;
1574
1575 return 0;
1576}
1577
1957aa63 1578static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1579{
1580 unsigned long rip;
6aa8b732 1581
1957aa63
SC		 1582 /*
1583 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1584 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1585 * set when EPT misconfig occurs. In practice, real hardware updates
1586 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1587 * (namely Hyper-V) don't set it due to it being undefined behavior,
1588 * i.e. we end up advancing IP with some random value.
1589 */
1590 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1591 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1592 rip = kvm_rip_read(vcpu);
1593 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1594 kvm_rip_write(vcpu, rip);
1595 } else {
1596 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1597 return 0;
1598 }
6aa8b732 1599
2809f5d2
GC		 1600 /* skipping an emulated instruction also counts */
1601 vmx_set_interrupt_shadow(vcpu, 0);
f8ea7c60 1602
60fc3d02 1603 return 1;
f8ea7c60
VK		 1604}
1605
caa057a2
WL		 1606static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1607{
1608 /*
1609 * Ensure that we clear the HLT state in the VMCS. We don't need to
1610 * explicitly skip the instruction because if the HLT state is set,
1611 * then the instruction is already executing and RIP has already been
1612 * advanced.
1613 */
1614 if (kvm_hlt_in_guest(vcpu->kvm) &&
1615 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1616 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1617}
1618
cfcd20e5 1619static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1620{
77ab6db0 1621 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1622 unsigned nr = vcpu->arch.exception.nr;
1623 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1624 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1625 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1626
da998b46
JM		 1627 kvm_deliver_exception_payload(vcpu);
1628
8ab2d2e2 1629 if (has_error_code) {
77ab6db0 1630 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1631 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1632 }
77ab6db0 1633
7ffd92c5 1634 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1635 int inc_eip = 0;
1636 if (kvm_exception_is_soft(nr))
1637 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 1638 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
77ab6db0
JK		 1639 return;
1640 }
1641
add5ff7a
SC		 1642 WARN_ON_ONCE(vmx->emulation_required);
1643
66fd3f7f
GN		 1644 if (kvm_exception_is_soft(nr)) {
1645 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1646 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1647 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1648 } else
1649 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1650
1651 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1652
1653 vmx_clear_hlt(vcpu);
298101da
AK		 1654}
1655
4e47c7a6
SY		 1656static bool vmx_rdtscp_supported(void)
1657{
1658 return cpu_has_vmx_rdtscp();
1659}
1660
ad756a16
MJ		 1661static bool vmx_invpcid_supported(void)
1662{
eb4b248e 1663 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1664}
1665
a75beee6
ED		 1666/*
1667 * Swap MSR entry in host/guest MSR entry array.
1668 */
8b9cf98c 1669static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1670{
26bb0981 1671 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1672
1673 tmp = vmx->guest_msrs[to];
1674 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1675 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1676}
1677
e38aea3e
AK		 1678/*
1679 * Set up the vmcs to automatically save and restore system
1680 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1681 * mode, as fiddling with msrs is very expensive.
1682 */
8b9cf98c 1683static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1684{
26bb0981 1685 int save_nmsrs, index;
e38aea3e 1686
a75beee6
ED		 1687 save_nmsrs = 0;
1688#ifdef CONFIG_X86_64
84c8c5b8
JM		 1689 /*
1690 * The SYSCALL MSRs are only needed on long mode guests, and only
1691 * when EFER.SCE is set.
1692 */
1693 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1694 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1695 if (index >= 0)
8b9cf98c
RR		 1696 move_msr_up(vmx, index, save_nmsrs++);
1697 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1698 if (index >= 0)
8b9cf98c 1699 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1700 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1701 if (index >= 0)
8b9cf98c 1702 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1703 }
1704#endif
92c0d900
AK		 1705 index = __find_msr_index(vmx, MSR_EFER);
1706 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1707 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1708 index = __find_msr_index(vmx, MSR_TSC_AUX);
1709 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1710 move_msr_up(vmx, index, save_nmsrs++);
c11f83e0
PB		 1711 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1712 if (index >= 0)
1713 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1714
26bb0981 1715 vmx->save_nmsrs = save_nmsrs;
b464f57e 1716 vmx->guest_msrs_ready = false;
5897297b 1717
8d14695f 1718 if (cpu_has_vmx_msr_bitmap())
904e14fb 1719 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1720}
1721
e79f245d 1722static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1723{
e79f245d 1724 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1725
e79f245d 1726 if (is_guest_mode(vcpu) &&
5e3d394f 1727 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
e79f245d
KA		 1728 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1729
1730 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1731}
1732
326e7425 1733static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1734{
45c3af97
PB		 1735 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1736 u64 g_tsc_offset = 0;
1737
1738 /*
1739 * We're here if L1 chose not to trap WRMSR to TSC. According
1740 * to the spec, this should set L1's TSC; The offset that L1
1741 * set for L2 remains unchanged, and still needs to be added
1742 * to the newly set TSC to get L2's TSC.
1743 */
1744 if (is_guest_mode(vcpu) &&
5e3d394f 1745 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
45c3af97 1746 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1747
45c3af97
PB		 1748 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1749 vcpu->arch.tsc_offset - g_tsc_offset,
1750 offset);
1751 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1752 return offset + g_tsc_offset;
6aa8b732
AK		 1753}
1754
801d3424
NHE		 1755/*
1756 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1757 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1758 * all guests if the "nested" module option is off, and can also be disabled
1759 * for a single guest by disabling its VMX cpuid bit.
1760 */
7c97fcb3 1761bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1762{
d6321d49 1763 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1764}
1765
55d2375e
SC		 1766static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1767 uint64_t val)
62cc6b9d 1768{
55d2375e 1769 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1770
55d2375e 1771 return !(val & ~valid_bits);
62cc6b9d
DM		 1772}
1773
55d2375e 1774static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1775{
55d2375e
SC		 1776 switch (msr->index) {
1777 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1778 if (!nested)
1779 return 1;
1780 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1781 default:
1782 return 1;
1783 }
62cc6b9d
DM		 1784}
1785
55d2375e
SC		 1786/*
1787 * Reads an msr value (of 'msr_index') into 'pdata'.
1788 * Returns 0 on success, non-0 otherwise.
1789 * Assumes vcpu_load() was already called.
1790 */
1791static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1792{
55d2375e
SC		 1793 struct vcpu_vmx *vmx = to_vmx(vcpu);
1794 struct shared_msr_entry *msr;
bf8c55d8 1795 u32 index;
62cc6b9d 1796
55d2375e
SC		 1797 switch (msr_info->index) {
1798#ifdef CONFIG_X86_64
1799 case MSR_FS_BASE:
1800 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1801 break;
55d2375e
SC		 1802 case MSR_GS_BASE:
1803 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1804 break;
55d2375e
SC		 1805 case MSR_KERNEL_GS_BASE:
1806 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1807 break;
55d2375e
SC		 1808#endif
1809 case MSR_EFER:
1810 return kvm_get_msr_common(vcpu, msr_info);
c11f83e0
PB		 1811 case MSR_IA32_TSX_CTRL:
1812 if (!msr_info->host_initiated &&
1813 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1814 return 1;
1815 goto find_shared_msr;
6e3ba4ab
TX		 1816 case MSR_IA32_UMWAIT_CONTROL:
1817 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1818 return 1;
1819
1820 msr_info->data = vmx->msr_ia32_umwait_control;
1821 break;
55d2375e
SC		 1822 case MSR_IA32_SPEC_CTRL:
1823 if (!msr_info->host_initiated &&
1824 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1825 return 1;
1826
1827 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1828 break;
6aa8b732 1829 case MSR_IA32_SYSENTER_CS:
609e36d3 1830 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1831 break;
1832 case MSR_IA32_SYSENTER_EIP:
609e36d3 1833 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1834 break;
1835 case MSR_IA32_SYSENTER_ESP:
609e36d3 1836 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1837 break;
0dd376e7 1838 case MSR_IA32_BNDCFGS:
691bd434 1839 if (!kvm_mpx_supported() ||
d6321d49
RK		 1840 (!msr_info->host_initiated &&
1841 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1842 return 1;
609e36d3 1843 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1844 break;
c45dcc71
AR		 1845 case MSR_IA32_MCG_EXT_CTL:
1846 if (!msr_info->host_initiated &&
a6cb099a 1847 !(vmx->msr_ia32_feature_control &
32ad73db 1848 FEAT_CTL_LMCE_ENABLED))
cae50139 1849 return 1;
c45dcc71
AR		 1850 msr_info->data = vcpu->arch.mcg_ext_ctl;
1851 break;
32ad73db 1852 case MSR_IA32_FEAT_CTL:
a6cb099a 1853 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1854 break;
1855 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1856 if (!nested_vmx_allowed(vcpu))
1857 return 1;
31de3d25
VK		 1858 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1859 &msr_info->data))
1860 return 1;
1861 /*
1862 * Enlightened VMCS v1 doesn't have certain fields, but buggy
1863 * Hyper-V versions are still trying to use corresponding
1864 * features when they are exposed. Filter out the essential
1865 * minimum.
1866 */
1867 if (!msr_info->host_initiated &&
1868 vmx->nested.enlightened_vmcs_enabled)
1869 nested_evmcs_filter_control_msr(msr_info->index,
1870 &msr_info->data);
1871 break;
bf8c55d8
CP		 1872 case MSR_IA32_RTIT_CTL:
1873 if (pt_mode != PT_MODE_HOST_GUEST)
1874 return 1;
1875 msr_info->data = vmx->pt_desc.guest.ctl;
1876 break;
1877 case MSR_IA32_RTIT_STATUS:
1878 if (pt_mode != PT_MODE_HOST_GUEST)
1879 return 1;
1880 msr_info->data = vmx->pt_desc.guest.status;
1881 break;
1882 case MSR_IA32_RTIT_CR3_MATCH:
1883 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1884 !intel_pt_validate_cap(vmx->pt_desc.caps,
1885 PT_CAP_cr3_filtering))
1886 return 1;
1887 msr_info->data = vmx->pt_desc.guest.cr3_match;
1888 break;
1889 case MSR_IA32_RTIT_OUTPUT_BASE:
1890 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1891 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1892 PT_CAP_topa_output) &&
1893 !intel_pt_validate_cap(vmx->pt_desc.caps,
1894 PT_CAP_single_range_output)))
1895 return 1;
1896 msr_info->data = vmx->pt_desc.guest.output_base;
1897 break;
1898 case MSR_IA32_RTIT_OUTPUT_MASK:
1899 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1900 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1901 PT_CAP_topa_output) &&
1902 !intel_pt_validate_cap(vmx->pt_desc.caps,
1903 PT_CAP_single_range_output)))
1904 return 1;
1905 msr_info->data = vmx->pt_desc.guest.output_mask;
1906 break;
1907 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1908 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1909 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1910 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1911 PT_CAP_num_address_ranges)))
1912 return 1;
1913 if (index % 2)
1914 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1915 else
1916 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1917 break;
4e47c7a6 1918 case MSR_TSC_AUX:
d6321d49
RK		 1919 if (!msr_info->host_initiated &&
1920 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1921 return 1;
c11f83e0 1922 goto find_shared_msr;
6aa8b732 1923 default:
c11f83e0 1924 find_shared_msr:
a6cb099a 1925 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1926 if (msr) {
609e36d3 1927 msr_info->data = msr->data;
3bab1f5d 1928 break;
6aa8b732 1929 }
609e36d3 1930 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1931 }
1932
6aa8b732
AK		 1933 return 0;
1934}
1935
1936/*
311497e0 1937 * Writes msr value into the appropriate "register".
6aa8b732
AK		 1938 * Returns 0 on success, non-0 otherwise.
1939 * Assumes vcpu_load() was already called.
1940 */
8fe8ab46 1941static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1942{
a2fa3e9f 1943 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1944 struct shared_msr_entry *msr;
2cc51560 1945 int ret = 0;
8fe8ab46
WA		 1946 u32 msr_index = msr_info->index;
1947 u64 data = msr_info->data;
bf8c55d8 1948 u32 index;
2cc51560 1949
6aa8b732 1950 switch (msr_index) {
3bab1f5d 1951 case MSR_EFER:
8fe8ab46 1952 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1953 break;
16175a79 1954#ifdef CONFIG_X86_64
6aa8b732 1955 case MSR_FS_BASE:
2fb92db1 1956 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1957 vmcs_writel(GUEST_FS_BASE, data);
1958 break;
1959 case MSR_GS_BASE:
2fb92db1 1960 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1961 vmcs_writel(GUEST_GS_BASE, data);
1962 break;
44ea2b17 1963 case MSR_KERNEL_GS_BASE:
678e315e 1964 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1965 break;
6aa8b732
AK		 1966#endif
1967 case MSR_IA32_SYSENTER_CS:
de70d279
SC		 1968 if (is_guest_mode(vcpu))
1969 get_vmcs12(vcpu)->guest_sysenter_cs = data;
6aa8b732
AK		 1970 vmcs_write32(GUEST_SYSENTER_CS, data);
1971 break;
1972 case MSR_IA32_SYSENTER_EIP:
de70d279
SC		 1973 if (is_guest_mode(vcpu))
1974 get_vmcs12(vcpu)->guest_sysenter_eip = data;
f5b42c33 1975 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1976 break;
1977 case MSR_IA32_SYSENTER_ESP:
de70d279
SC		 1978 if (is_guest_mode(vcpu))
1979 get_vmcs12(vcpu)->guest_sysenter_esp = data;
f5b42c33 1980 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1981 break;
699a1ac2
SC		 1982 case MSR_IA32_DEBUGCTLMSR:
1983 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1984 VM_EXIT_SAVE_DEBUG_CONTROLS)
1985 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1986
1987 ret = kvm_set_msr_common(vcpu, msr_info);
1988 break;
1989
0dd376e7 1990 case MSR_IA32_BNDCFGS:
691bd434 1991 if (!kvm_mpx_supported() ||
d6321d49
RK		 1992 (!msr_info->host_initiated &&
1993 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1994 return 1;
fd8cb433 1995 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 1996 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 1997 return 1;
0dd376e7
LJ		 1998 vmcs_write64(GUEST_BNDCFGS, data);
1999 break;
6e3ba4ab
TX		 2000 case MSR_IA32_UMWAIT_CONTROL:
2001 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2002 return 1;
2003
2004 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2005 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2006 return 1;
2007
2008 vmx->msr_ia32_umwait_control = data;
2009 break;
d28b387f
KA		 2010 case MSR_IA32_SPEC_CTRL:
2011 if (!msr_info->host_initiated &&
d28b387f
KA		 2012 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2013 return 1;
2014
6441fa61 2015 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
d28b387f
KA		 2016 return 1;
2017
2018 vmx->spec_ctrl = data;
d28b387f
KA		 2019 if (!data)
2020 break;
2021
2022 /*
2023 * For non-nested:
2024 * When it's written (to non-zero) for the first time, pass
2025 * it through.
2026 *
2027 * For nested:
2028 * The handling of the MSR bitmap for L2 guests is done in
4d516fe7 2029 * nested_vmx_prepare_msr_bitmap. We should not touch the
d28b387f
KA		 2030 * vmcs02.msr_bitmap here since it gets completely overwritten
2031 * in the merging. We update the vmcs01 here for L1 as well
2032 * since it will end up touching the MSR anyway now.
2033 */
2034 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2035 MSR_IA32_SPEC_CTRL,
2036 MSR_TYPE_RW);
2037 break;
c11f83e0
PB		 2038 case MSR_IA32_TSX_CTRL:
2039 if (!msr_info->host_initiated &&
2040 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2041 return 1;
2042 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2043 return 1;
2044 goto find_shared_msr;
15d45071
AR		 2045 case MSR_IA32_PRED_CMD:
2046 if (!msr_info->host_initiated &&
15d45071
AR		 2047 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2048 return 1;
2049
2050 if (data & ~PRED_CMD_IBPB)
2051 return 1;
6441fa61
PB		 2052 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2053 return 1;
15d45071
AR		 2054 if (!data)
2055 break;
2056
2057 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2058
2059 /*
2060 * For non-nested:
2061 * When it's written (to non-zero) for the first time, pass
2062 * it through.
2063 *
2064 * For nested:
2065 * The handling of the MSR bitmap for L2 guests is done in
4d516fe7 2066 * nested_vmx_prepare_msr_bitmap. We should not touch the
15d45071
AR		 2067 * vmcs02.msr_bitmap here since it gets completely overwritten
2068 * in the merging.
2069 */
2070 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2071 MSR_TYPE_W);
2072 break;
468d472f 2073 case MSR_IA32_CR_PAT:
d28f4290
SC		 2074 if (!kvm_pat_valid(data))
2075 return 1;
2076
142e4be7
SC		 2077 if (is_guest_mode(vcpu) &&
2078 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2079 get_vmcs12(vcpu)->guest_ia32_pat = data;
2080
468d472f
SY		 2081 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2082 vmcs_write64(GUEST_IA32_PAT, data);
2083 vcpu->arch.pat = data;
2084 break;
2085 }
8fe8ab46 2086 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2087 break;
ba904635
WA		 2088 case MSR_IA32_TSC_ADJUST:
2089 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2090 break;
c45dcc71
AR		 2091 case MSR_IA32_MCG_EXT_CTL:
2092 if ((!msr_info->host_initiated &&
2093 !(to_vmx(vcpu)->msr_ia32_feature_control &
32ad73db 2094 FEAT_CTL_LMCE_ENABLED)) ||
c45dcc71
AR		 2095 (data & ~MCG_EXT_CTL_LMCE_EN))
2096 return 1;
2097 vcpu->arch.mcg_ext_ctl = data;
2098 break;
32ad73db 2099 case MSR_IA32_FEAT_CTL:
37e4c997 2100 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 2101 (to_vmx(vcpu)->msr_ia32_feature_control &
32ad73db 2102 FEAT_CTL_LOCKED && !msr_info->host_initiated))
cae50139 2103 return 1;
3b84080b 2104 vmx->msr_ia32_feature_control = data;
cae50139
JK		 2105 if (msr_info->host_initiated && data == 0)
2106 vmx_leave_nested(vcpu);
2107 break;
2108 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 2109 if (!msr_info->host_initiated)
2110 return 1; /* they are read-only */
2111 if (!nested_vmx_allowed(vcpu))
2112 return 1;
2113 return vmx_set_vmx_msr(vcpu, msr_index, data);
bf8c55d8
CP		 2114 case MSR_IA32_RTIT_CTL:
2115 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 2116 vmx_rtit_ctl_check(vcpu, data) ||
2117 vmx->nested.vmxon)
bf8c55d8
CP		 2118 return 1;
2119 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2120 vmx->pt_desc.guest.ctl = data;
b08c2896 2121 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 2122 break;
2123 case MSR_IA32_RTIT_STATUS:
e348ac7c
SC		 2124 if (!pt_can_write_msr(vmx))
2125 return 1;
2126 if (data & MSR_IA32_RTIT_STATUS_MASK)
bf8c55d8
CP		 2127 return 1;
2128 vmx->pt_desc.guest.status = data;
2129 break;
2130 case MSR_IA32_RTIT_CR3_MATCH:
e348ac7c
SC		 2131 if (!pt_can_write_msr(vmx))
2132 return 1;
2133 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2134 PT_CAP_cr3_filtering))
bf8c55d8
CP		 2135 return 1;
2136 vmx->pt_desc.guest.cr3_match = data;
2137 break;
2138 case MSR_IA32_RTIT_OUTPUT_BASE:
e348ac7c
SC		 2139 if (!pt_can_write_msr(vmx))
2140 return 1;
2141 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2142 PT_CAP_topa_output) &&
2143 !intel_pt_validate_cap(vmx->pt_desc.caps,
2144 PT_CAP_single_range_output))
2145 return 1;
2146 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
bf8c55d8
CP		 2147 return 1;
2148 vmx->pt_desc.guest.output_base = data;
2149 break;
2150 case MSR_IA32_RTIT_OUTPUT_MASK:
e348ac7c
SC		 2151 if (!pt_can_write_msr(vmx))
2152 return 1;
2153 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2154 PT_CAP_topa_output) &&
2155 !intel_pt_validate_cap(vmx->pt_desc.caps,
2156 PT_CAP_single_range_output))
bf8c55d8
CP		 2157 return 1;
2158 vmx->pt_desc.guest.output_mask = data;
2159 break;
2160 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
e348ac7c
SC		 2161 if (!pt_can_write_msr(vmx))
2162 return 1;
bf8c55d8 2163 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
e348ac7c
SC		 2164 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2165 PT_CAP_num_address_ranges))
bf8c55d8 2166 return 1;
fe6ed369 2167 if (is_noncanonical_address(data, vcpu))
bf8c55d8
CP		 2168 return 1;
2169 if (index % 2)
2170 vmx->pt_desc.guest.addr_b[index / 2] = data;
2171 else
2172 vmx->pt_desc.guest.addr_a[index / 2] = data;
2173 break;
4e47c7a6 2174 case MSR_TSC_AUX:
d6321d49
RK		 2175 if (!msr_info->host_initiated &&
2176 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2177 return 1;
2178 /* Check reserved bit, higher 32 bits should be zero */
2179 if ((data >> 32) != 0)
2180 return 1;
c11f83e0
PB		 2181 goto find_shared_msr;
2182
6aa8b732 2183 default:
c11f83e0 2184 find_shared_msr:
8b9cf98c 2185 msr = find_msr_entry(vmx, msr_index);
b07a5c53
PB		 2186 if (msr)
2187 ret = vmx_set_guest_msr(vmx, msr, data);
2188 else
2189 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2190 }
2191
2cc51560 2192 return ret;
6aa8b732
AK		 2193}
2194
5fdbf976 2195static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2196{
cb3c1e2f
SC		 2197 kvm_register_mark_available(vcpu, reg);
2198
5fdbf976
MT		 2199 switch (reg) {
2200 case VCPU_REGS_RSP:
2201 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2202 break;
2203 case VCPU_REGS_RIP:
2204 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2205 break;
6de4f3ad
AK		 2206 case VCPU_EXREG_PDPTR:
2207 if (enable_ept)
2208 ept_save_pdptrs(vcpu);
2209 break;
34059c25
SC		 2210 case VCPU_EXREG_CR3:
2211 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2212 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2213 break;
5fdbf976 2214 default:
34059c25 2215 WARN_ON_ONCE(1);
5fdbf976
MT		 2216 break;
2217 }
6aa8b732
AK		 2218}
2219
6aa8b732
AK		 2220static __init int cpu_has_kvm_support(void)
2221{
6210e37b 2222 return cpu_has_vmx();
6aa8b732
AK		 2223}
2224
2225static __init int vmx_disabled_by_bios(void)
2226{
a4d0b2fd
SC		 2227 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2228 !boot_cpu_has(X86_FEATURE_VMX);
6aa8b732
AK		 2229}
2230
7725b894
DX		 2231static void kvm_cpu_vmxon(u64 addr)
2232{
fe0e80be 2233 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2234 intel_pt_handle_vmx(1);
2235
4b1e5478 2236 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2237}
2238
13a34e06 2239static int hardware_enable(void)
6aa8b732
AK		 2240{
2241 int cpu = raw_smp_processor_id();
2242 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 2243
1e02ce4c 2244 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2245 return -EBUSY;
2246
773e8a04
VK		 2247 /*
2248 * This can happen if we hot-added a CPU but failed to allocate
2249 * VP assist page for it.
2250 */
2251 if (static_branch_unlikely(&enable_evmcs) &&
2252 !hv_get_vp_assist_page(cpu))
2253 return -EFAULT;
2254
d462b819 2255 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2256 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2257 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2258
2259 /*
2260 * Now we can enable the vmclear operation in kdump
2261 * since the loaded_vmcss_on_cpu list on this cpu
2262 * has been initialized.
2263 *
2264 * Though the cpu is not in VMX operation now, there
2265 * is no problem to enable the vmclear operation
2266 * for the loaded_vmcss_on_cpu list is empty!
2267 */
2268 crash_enable_local_vmclear(cpu);
2269
fe0e80be 2270 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2271 if (enable_ept)
2272 ept_sync_global();
10474ae8
AG		 2273
2274 return 0;
6aa8b732
AK		 2275}
2276
d462b819 2277static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2278{
2279 int cpu = raw_smp_processor_id();
d462b819 2280 struct loaded_vmcs *v, *n;
543e4243 2281
d462b819
NHE		 2282 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2283 loaded_vmcss_on_cpu_link)
2284 __loaded_vmcs_clear(v);
543e4243
AK		 2285}
2286
710ff4a8
EH		 2287
2288/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2289 * tricks.
2290 */
2291static void kvm_cpu_vmxoff(void)
6aa8b732 2292{
4b1e5478 2293 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2294
2295 intel_pt_handle_vmx(0);
fe0e80be 2296 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2297}
2298
13a34e06 2299static void hardware_disable(void)
710ff4a8 2300{
fe0e80be
DH		 2301 vmclear_local_loaded_vmcss();
2302 kvm_cpu_vmxoff();
710ff4a8
EH		 2303}
2304
1c3d14fe 2305static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2306 u32 msr, u32 *result)
1c3d14fe
YS		 2307{
2308 u32 vmx_msr_low, vmx_msr_high;
2309 u32 ctl = ctl_min | ctl_opt;
2310
2311 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2312
2313 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2314 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2315
2316 /* Ensure minimum (required) set of control bits are supported. */
2317 if (ctl_min & ~ctl)
002c7f7c 2318 return -EIO;
1c3d14fe
YS		 2319
2320 *result = ctl;
2321 return 0;
2322}
2323
7caaa711
SC		 2324static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2325 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2326{
2327 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2328 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2329 u32 _pin_based_exec_control = 0;
2330 u32 _cpu_based_exec_control = 0;
f78e0e2e 2331 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2332 u32 _vmexit_control = 0;
2333 u32 _vmentry_control = 0;
2334
1389309c 2335 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2336 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2337#ifdef CONFIG_X86_64
2338 CPU_BASED_CR8_LOAD_EXITING |
2339 CPU_BASED_CR8_STORE_EXITING |
2340#endif
d56f546d
SY		 2341 CPU_BASED_CR3_LOAD_EXITING |
2342 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2343 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2344 CPU_BASED_MOV_DR_EXITING |
5e3d394f 2345 CPU_BASED_USE_TSC_OFFSETTING |
4d5422ce
WL		 2346 CPU_BASED_MWAIT_EXITING |
2347 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2348 CPU_BASED_INVLPG_EXITING |
2349 CPU_BASED_RDPMC_EXITING;
443381a8 2350
f78e0e2e 2351 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2352 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2353 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2354 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2355 &_cpu_based_exec_control) < 0)
002c7f7c 2356 return -EIO;
6e5d865c
YS		 2357#ifdef CONFIG_X86_64
2358 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2359 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2360 ~CPU_BASED_CR8_STORE_EXITING;
2361#endif
f78e0e2e 2362 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2363 min2 = 0;
2364 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2365 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2366 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2367 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2368 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2369 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2370 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2371 SECONDARY_EXEC_DESC |
ad756a16 2372 SECONDARY_EXEC_RDTSCP |
83d4c286 2373 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2374 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2375 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2376 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2377 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2378 SECONDARY_EXEC_RDSEED_EXITING |
2379 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2380 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2381 SECONDARY_EXEC_TSC_SCALING |
e69e72fa 2382 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
f99e3daf
CP		 2383 SECONDARY_EXEC_PT_USE_GPA |
2384 SECONDARY_EXEC_PT_CONCEAL_VMX |
0b665d30
SC		 2385 SECONDARY_EXEC_ENABLE_VMFUNC |
2386 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2387 if (adjust_vmx_controls(min2, opt2,
2388 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2389 &_cpu_based_2nd_exec_control) < 0)
2390 return -EIO;
2391 }
2392#ifndef CONFIG_X86_64
2393 if (!(_cpu_based_2nd_exec_control &
2394 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2395 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2396#endif
83d4c286
YZ		 2397
2398 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2399 _cpu_based_2nd_exec_control &= ~(
8d14695f 2400 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2401 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2402 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2403
61f1dd90 2404 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2405 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2406
d56f546d 2407 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2408 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2409 enabled */
5fff7d27
GN		 2410 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2411 CPU_BASED_CR3_STORE_EXITING |
2412 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2413 } else if (vmx_cap->ept) {
2414 vmx_cap->ept = 0;
61f1dd90
WL		 2415 pr_warn_once("EPT CAP should not exist if not support "
2416 "1-setting enable EPT VM-execution control\n");
2417 }
2418 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2419 vmx_cap->vpid) {
2420 vmx_cap->vpid = 0;
61f1dd90
WL		 2421 pr_warn_once("VPID CAP should not exist if not support "
2422 "1-setting enable VPID VM-execution control\n");
d56f546d 2423 }
1c3d14fe 2424
91fa0f8e 2425 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2426#ifdef CONFIG_X86_64
2427 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2428#endif
c73da3fc 2429 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2430 VM_EXIT_LOAD_IA32_PAT |
2431 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2432 VM_EXIT_CLEAR_BNDCFGS |
2433 VM_EXIT_PT_CONCEAL_PIP |
2434 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2435 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2436 &_vmexit_control) < 0)
002c7f7c 2437 return -EIO;
1c3d14fe 2438
8a1b4392
PB		 2439 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2440 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2441 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2442 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2443 &_pin_based_exec_control) < 0)
2444 return -EIO;
2445
1c17c3e6
PB		 2446 if (cpu_has_broken_vmx_preemption_timer())
2447 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2448 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2449 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2450 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2451
c845f9c6 2452 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2453 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2454 VM_ENTRY_LOAD_IA32_PAT |
2455 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2456 VM_ENTRY_LOAD_BNDCFGS |
2457 VM_ENTRY_PT_CONCEAL_PIP |
2458 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2459 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2460 &_vmentry_control) < 0)
002c7f7c 2461 return -EIO;
6aa8b732 2462
c73da3fc
SC		 2463 /*
2464 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2465 * can't be used due to an errata where VM Exit may incorrectly clear
2466 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2467 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2468 */
2469 if (boot_cpu_data.x86 == 0x6) {
2470 switch (boot_cpu_data.x86_model) {
2471 case 26: /* AAK155 */
2472 case 30: /* AAP115 */
2473 case 37: /* AAT100 */
2474 case 44: /* BC86,AAY89,BD102 */
2475 case 46: /* BA97 */
85ba2b16 2476 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2477 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2478 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2479 "does not work properly. Using workaround\n");
2480 break;
2481 default:
2482 break;
2483 }
2484 }
2485
2486
c68876fd 2487 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2488
2489 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2490 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2491 return -EIO;
1c3d14fe
YS		 2492
2493#ifdef CONFIG_X86_64
2494 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2495 if (vmx_msr_high & (1u<<16))
002c7f7c 2496 return -EIO;
1c3d14fe
YS		 2497#endif
2498
2499 /* Require Write-Back (WB) memory type for VMCS accesses. */
2500 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2501 return -EIO;
1c3d14fe 2502
002c7f7c 2503 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2504 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2505 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2506
2307af1c 2507 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2508
002c7f7c
YS		 2509 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2510 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2511 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2512 vmcs_conf->vmexit_ctrl = _vmexit_control;
2513 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2514
773e8a04
VK		 2515 if (static_branch_unlikely(&enable_evmcs))
2516 evmcs_sanitize_exec_ctrls(vmcs_conf);
2517
1c3d14fe 2518 return 0;
c68876fd 2519}
6aa8b732 2520
41836839 2521struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2522{
2523 int node = cpu_to_node(cpu);
2524 struct page *pages;
2525 struct vmcs *vmcs;
2526
41836839 2527 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2528 if (!pages)
2529 return NULL;
2530 vmcs = page_address(pages);
1c3d14fe 2531 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2532
2533 /* KVM supports Enlightened VMCS v1 only */
2534 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2535 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2536 else
392b2f25 2537 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2538
491a6038
LA		 2539 if (shadow)
2540 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2541 return vmcs;
2542}
2543
89b0c9f5 2544void free_vmcs(struct vmcs *vmcs)
6aa8b732 2545{
1c3d14fe 2546 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2547}
2548
d462b819
NHE		 2549/*
2550 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2551 */
89b0c9f5 2552void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2553{
2554 if (!loaded_vmcs->vmcs)
2555 return;
2556 loaded_vmcs_clear(loaded_vmcs);
2557 free_vmcs(loaded_vmcs->vmcs);
2558 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2559 if (loaded_vmcs->msr_bitmap)
2560 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2561 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2562}
2563
89b0c9f5 2564int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2565{
491a6038 2566 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2567 if (!loaded_vmcs->vmcs)
2568 return -ENOMEM;
2569
2570 loaded_vmcs->shadow_vmcs = NULL;
804939ea 2571 loaded_vmcs->hv_timer_soft_disabled = false;
f21f165e 2572 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2573
2574 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2575 loaded_vmcs->msr_bitmap = (unsigned long *)
2576 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2577 if (!loaded_vmcs->msr_bitmap)
2578 goto out_vmcs;
2579 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2580
1f008e11
AB		 2581 if (IS_ENABLED(CONFIG_HYPERV) &&
2582 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2583 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2584 struct hv_enlightened_vmcs *evmcs =
2585 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2586
2587 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2588 }
904e14fb 2589 }
d7ee039e
SC		 2590
2591 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
3af80fec
SC		 2592 memset(&loaded_vmcs->controls_shadow, 0,
2593 sizeof(struct vmcs_controls_shadow));
d7ee039e 2594
f21f165e 2595 return 0;
904e14fb
PB		 2596
2597out_vmcs:
2598 free_loaded_vmcs(loaded_vmcs);
2599 return -ENOMEM;
f21f165e
PB		 2600}
2601
39959588 2602static void free_kvm_area(void)
6aa8b732
AK		 2603{
2604 int cpu;
2605
3230bb47 2606 for_each_possible_cpu(cpu) {
6aa8b732 2607 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2608 per_cpu(vmxarea, cpu) = NULL;
2609 }
6aa8b732
AK		 2610}
2611
6aa8b732
AK		 2612static __init int alloc_kvm_area(void)
2613{
2614 int cpu;
2615
3230bb47 2616 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2617 struct vmcs *vmcs;
2618
41836839 2619 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2620 if (!vmcs) {
2621 free_kvm_area();
2622 return -ENOMEM;
2623 }
2624
2307af1c
LA		 2625 /*
2626 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2627 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2628 * revision_id reported by MSR_IA32_VMX_BASIC.
2629 *
312a4661 2630 * However, even though not explicitly documented by
2307af1c
LA		 2631 * TLFS, VMXArea passed as VMXON argument should
2632 * still be marked with revision_id reported by
2633 * physical CPU.
2634 */
2635 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2636 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2637
6aa8b732
AK		 2638 per_cpu(vmxarea, cpu) = vmcs;
2639 }
2640 return 0;
2641}
2642
91b0aa2c 2643static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2644 struct kvm_segment *save)
6aa8b732 2645{
d99e4152
GN		 2646 if (!emulate_invalid_guest_state) {
2647 /*
2648 * CS and SS RPL should be equal during guest entry according
2649 * to VMX spec, but in reality it is not always so. Since vcpu
2650 * is in the middle of the transition from real mode to
2651 * protected mode it is safe to assume that RPL 0 is a good
2652 * default value.
2653 */
2654 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2655 save->selector &= ~SEGMENT_RPL_MASK;
2656 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2657 save->s = 1;
6aa8b732 2658 }
d99e4152 2659 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2660}
2661
2662static void enter_pmode(struct kvm_vcpu *vcpu)
2663{
2664 unsigned long flags;
a89a8fb9 2665 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2666
d99e4152
GN		 2667 /*
2668 * Update real mode segment cache. It may be not up-to-date if sement
2669 * register was written while vcpu was in a guest mode.
2670 */
2671 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2672 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2673 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2674 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2675 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2676 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2677
7ffd92c5 2678 vmx->rmode.vm86_active = 0;
6aa8b732 2679
f5f7b2fe 2680 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2681
2682 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2683 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2684 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2685 vmcs_writel(GUEST_RFLAGS, flags);
2686
66aee91a
RR		 2687 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2688 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2689
2690 update_exception_bitmap(vcpu);
2691
91b0aa2c
GN		 2692 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2693 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2694 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2695 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2696 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2697 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2698}
2699
f5f7b2fe 2700static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2701{
772e0318 2702 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2703 struct kvm_segment var = *save;
2704
2705 var.dpl = 0x3;
2706 if (seg == VCPU_SREG_CS)
2707 var.type = 0x3;
2708
2709 if (!emulate_invalid_guest_state) {
2710 var.selector = var.base >> 4;
2711 var.base = var.base & 0xffff0;
2712 var.limit = 0xffff;
2713 var.g = 0;
2714 var.db = 0;
2715 var.present = 1;
2716 var.s = 1;
2717 var.l = 0;
2718 var.unusable = 0;
2719 var.type = 0x3;
2720 var.avl = 0;
2721 if (save->base & 0xf)
2722 printk_once(KERN_WARNING "kvm: segment base is not "
2723 "paragraph aligned when entering "
2724 "protected mode (seg=%d)", seg);
2725 }
6aa8b732 2726
d99e4152 2727 vmcs_write16(sf->selector, var.selector);
96794e4e 2728 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2729 vmcs_write32(sf->limit, var.limit);
2730 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2731}
2732
2733static void enter_rmode(struct kvm_vcpu *vcpu)
2734{
2735 unsigned long flags;
a89a8fb9 2736 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2737 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2738
f5f7b2fe
AK		 2739 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2740 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2741 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2742 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2743 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2744 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2745 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2746
7ffd92c5 2747 vmx->rmode.vm86_active = 1;
6aa8b732 2748
776e58ea
GN		 2749 /*
2750 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2751 * vcpu. Warn the user that an update is overdue.
776e58ea 2752 */
40bbb9d0 2753 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2754 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2755 "called before entering vcpu\n");
776e58ea 2756
2fb92db1
AK		 2757 vmx_segment_cache_clear(vmx);
2758
40bbb9d0 2759 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2760 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2761 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2762
2763 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2764 vmx->rmode.save_rflags = flags;
6aa8b732 2765
053de044 2766 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2767
2768 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2769 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2770 update_exception_bitmap(vcpu);
2771
d99e4152
GN		 2772 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2773 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2774 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2775 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2776 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2777 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2778
8668a3c4 2779 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2780}
2781
97b7ead3 2782void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2783{
2784 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2785 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2786
2787 if (!msr)
2788 return;
401d10de 2789
f6801dff 2790 vcpu->arch.efer = efer;
401d10de 2791 if (efer & EFER_LMA) {
2961e876 2792 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2793 msr->data = efer;
2794 } else {
2961e876 2795 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2796
2797 msr->data = efer & ~EFER_LME;
2798 }
2799 setup_msrs(vmx);
2800}
2801
05b3e0c2 2802#ifdef CONFIG_X86_64
6aa8b732
AK		 2803
2804static void enter_lmode(struct kvm_vcpu *vcpu)
2805{
2806 u32 guest_tr_ar;
2807
2fb92db1
AK		 2808 vmx_segment_cache_clear(to_vmx(vcpu));
2809
6aa8b732 2810 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2811 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2812 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2813 __func__);
6aa8b732 2814 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2815 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2816 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2817 }
da38f438 2818 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2819}
2820
2821static void exit_lmode(struct kvm_vcpu *vcpu)
2822{
2961e876 2823 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2824 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2825}
2826
2827#endif
2828
faff8758
JS		 2829static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2830{
2831 int vpid = to_vmx(vcpu)->vpid;
2832
2833 if (!vpid_sync_vcpu_addr(vpid, addr))
2834 vpid_sync_context(vpid);
2835
2836 /*
2837 * If VPIDs are not supported or enabled, then the above is a no-op.
2838 * But we don't really need a TLB flush in that case anyway, because
2839 * each VM entry/exit includes an implicit flush when VPID is 0.
2840 */
2841}
2842
e8467fda
AK		 2843static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2844{
2845 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2846
2847 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2848 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2849}
2850
25c4c276 2851static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2852{
fc78f519
AK		 2853 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2854
2855 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2856 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2857}
2858
1439442c
SY		 2859static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2860{
d0d538b9
GN		 2861 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2862
cb3c1e2f 2863 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
6de4f3ad
AK		 2864 return;
2865
bf03d4f9 2866 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2867 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2868 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2869 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2870 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2871 }
2872}
2873
97b7ead3 2874void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2875{
d0d538b9
GN		 2876 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2877
bf03d4f9 2878 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2879 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2880 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2881 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2882 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2883 }
6de4f3ad 2884
cb3c1e2f 2885 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
8f5d549f
AK		 2886}
2887
1439442c
SY		 2888static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2889 unsigned long cr0,
2890 struct kvm_vcpu *vcpu)
2891{
2183f564
SC		 2892 struct vcpu_vmx *vmx = to_vmx(vcpu);
2893
cb3c1e2f 2894 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
34059c25 2895 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
1439442c
SY		 2896 if (!(cr0 & X86_CR0_PG)) {
2897 /* From paging/starting to nonpaging */
2183f564
SC		 2898 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2899 CPU_BASED_CR3_STORE_EXITING);
1439442c 2900 vcpu->arch.cr0 = cr0;
fc78f519 2901 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2902 } else if (!is_paging(vcpu)) {
2903 /* From nonpaging to paging */
2183f564
SC		 2904 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2905 CPU_BASED_CR3_STORE_EXITING);
1439442c 2906 vcpu->arch.cr0 = cr0;
fc78f519 2907 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2908 }
95eb84a7
SY		 2909
2910 if (!(cr0 & X86_CR0_WP))
2911 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2912}
2913
97b7ead3 2914void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2915{
7ffd92c5 2916 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2917 unsigned long hw_cr0;
2918
3de6347b 2919 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2920 if (enable_unrestricted_guest)
5037878e 2921 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2922 else {
5037878e 2923 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2924
218e763f
GN		 2925 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2926 enter_pmode(vcpu);
6aa8b732 2927
218e763f
GN		 2928 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2929 enter_rmode(vcpu);
2930 }
6aa8b732 2931
05b3e0c2 2932#ifdef CONFIG_X86_64
f6801dff 2933 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2934 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2935 enter_lmode(vcpu);
707d92fa 2936 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2937 exit_lmode(vcpu);
2938 }
2939#endif
2940
b4d18517 2941 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2942 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2943
6aa8b732 2944 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2945 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2946 vcpu->arch.cr0 = cr0;
14168786
GN		 2947
2948 /* depends on vcpu->arch.cr0 to be set to a new value */
2949 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2950}
2951
855feb67
YZ		 2952static int get_ept_level(struct kvm_vcpu *vcpu)
2953{
148d735e
SC		 2954 /* Nested EPT currently only supports 4-level walks. */
2955 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
2956 return 4;
855feb67
YZ		 2957 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2958 return 5;
2959 return 4;
2960}
2961
89b0c9f5 2962u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2963{
855feb67
YZ		 2964 u64 eptp = VMX_EPTP_MT_WB;
2965
2966 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 2967
995f00a6
PF		 2968 if (enable_ept_ad_bits &&
2969 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 2970 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 2971 eptp |= (root_hpa & PAGE_MASK);
2972
2973 return eptp;
2974}
2975
97b7ead3 2976void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 2977{
877ad952 2978 struct kvm *kvm = vcpu->kvm;
04f11ef4 2979 bool update_guest_cr3 = true;
1439442c
SY		 2980 unsigned long guest_cr3;
2981 u64 eptp;
2982
2983 guest_cr3 = cr3;
089d034e 2984 if (enable_ept) {
995f00a6 2985 eptp = construct_eptp(vcpu, cr3);
1439442c 2986 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 2987
2988 if (kvm_x86_ops->tlb_remote_flush) {
2989 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2990 to_vmx(vcpu)->ept_pointer = eptp;
2991 to_kvm_vmx(kvm)->ept_pointers_match
2992 = EPT_POINTERS_CHECK;
2993 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2994 }
2995
04f11ef4
SC		 2996 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
2997 if (is_guest_mode(vcpu))
2998 update_guest_cr3 = false;
b17b7436 2999 else if (!enable_unrestricted_guest && !is_paging(vcpu))
877ad952 3000 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
b17b7436
SC		 3001 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3002 guest_cr3 = vcpu->arch.cr3;
3003 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3004 update_guest_cr3 = false;
7c93be44 3005 ept_load_pdptrs(vcpu);
1439442c
SY		 3006 }
3007
04f11ef4
SC		 3008 if (update_guest_cr3)
3009 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3010}
3011
97b7ead3 3012int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3013{
fe7f895d 3014 struct vcpu_vmx *vmx = to_vmx(vcpu);
085e68ee
BS		 3015 /*
3016 * Pass through host's Machine Check Enable value to hw_cr4, which
3017 * is in force while we are in guest mode. Do not let guests control
3018 * this bit, even if host CR4.MCE == 0.
3019 */
5dc1f044
SC		 3020 unsigned long hw_cr4;
3021
3022 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3023 if (enable_unrestricted_guest)
3024 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
fe7f895d 3025 else if (vmx->rmode.vm86_active)
5dc1f044
SC		 3026 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3027 else
3028 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 3029
64f7a115
SC		 3030 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3031 if (cr4 & X86_CR4_UMIP) {
fe7f895d 3032 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
64f7a115
SC		 3033 hw_cr4 &= ~X86_CR4_UMIP;
3034 } else if (!is_guest_mode(vcpu) ||
fe7f895d
SC		 3035 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3036 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3037 }
64f7a115 3038 }
0367f205 3039
5e1746d6
NHE		 3040 if (cr4 & X86_CR4_VMXE) {
3041 /*
3042 * To use VMXON (and later other VMX instructions), a guest
3043 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3044 * So basically the check on whether to allow nested VMX
5bea5123
PB		 3045 * is here. We operate under the default treatment of SMM,
3046 * so VMX cannot be enabled under SMM.
5e1746d6 3047 */
5bea5123 3048 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 3049 return 1;
1a0d74e6 3050 }
3899152c 3051
fe7f895d 3052 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 3053 return 1;
3054
ad312c7c 3055 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 3056
3057 if (!enable_unrestricted_guest) {
3058 if (enable_ept) {
3059 if (!is_paging(vcpu)) {
3060 hw_cr4 &= ~X86_CR4_PAE;
3061 hw_cr4 |= X86_CR4_PSE;
3062 } else if (!(cr4 & X86_CR4_PAE)) {
3063 hw_cr4 &= ~X86_CR4_PAE;
3064 }
bc23008b 3065 }
1439442c 3066
656ec4a4 3067 /*
ddba2628
HH		 3068 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3069 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3070 * to be manually disabled when guest switches to non-paging
3071 * mode.
3072 *
3073 * If !enable_unrestricted_guest, the CPU is always running
3074 * with CR0.PG=1 and CR4 needs to be modified.
3075 * If enable_unrestricted_guest, the CPU automatically
3076 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 3077 */
5dc1f044
SC		 3078 if (!is_paging(vcpu))
3079 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3080 }
656ec4a4 3081
1439442c
SY		 3082 vmcs_writel(CR4_READ_SHADOW, cr4);
3083 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3084 return 0;
6aa8b732
AK		 3085}
3086
97b7ead3 3087void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 3088{
a9179499 3089 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3090 u32 ar;
3091
c6ad1153 3092 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3093 *var = vmx->rmode.segs[seg];
a9179499 3094 if (seg == VCPU_SREG_TR
2fb92db1 3095 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3096 return;
1390a28b
AK		 3097 var->base = vmx_read_guest_seg_base(vmx, seg);
3098 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3099 return;
a9179499 3100 }
2fb92db1
AK		 3101 var->base = vmx_read_guest_seg_base(vmx, seg);
3102 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3103 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3104 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3105 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3106 var->type = ar & 15;
3107 var->s = (ar >> 4) & 1;
3108 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3109 /*
3110 * Some userspaces do not preserve unusable property. Since usable
3111 * segment has to be present according to VMX spec we can use present
3112 * property to amend userspace bug by making unusable segment always
3113 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3114 * segment as unusable.
3115 */
3116 var->present = !var->unusable;
6aa8b732
AK		 3117 var->avl = (ar >> 12) & 1;
3118 var->l = (ar >> 13) & 1;
3119 var->db = (ar >> 14) & 1;
3120 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3121}
3122
a9179499
AK		 3123static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3124{
a9179499
AK		 3125 struct kvm_segment s;
3126
3127 if (to_vmx(vcpu)->rmode.vm86_active) {
3128 vmx_get_segment(vcpu, &s, seg);
3129 return s.base;
3130 }
2fb92db1 3131 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3132}
3133
97b7ead3 3134int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3135{
b09408d0
MT		 3136 struct vcpu_vmx *vmx = to_vmx(vcpu);
3137
ae9fedc7 3138 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3139 return 0;
ae9fedc7
PB		 3140 else {
3141 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3142 return VMX_AR_DPL(ar);
69c73028 3143 }
69c73028
AK		 3144}
3145
653e3108 3146static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3147{
6aa8b732
AK		 3148 u32 ar;
3149
f0495f9b 3150 if (var->unusable || !var->present)
6aa8b732
AK		 3151 ar = 1 << 16;
3152 else {
3153 ar = var->type & 15;
3154 ar |= (var->s & 1) << 4;
3155 ar |= (var->dpl & 3) << 5;
3156 ar |= (var->present & 1) << 7;
3157 ar |= (var->avl & 1) << 12;
3158 ar |= (var->l & 1) << 13;
3159 ar |= (var->db & 1) << 14;
3160 ar |= (var->g & 1) << 15;
3161 }
653e3108
AK		 3162
3163 return ar;
3164}
3165
97b7ead3 3166void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3167{
7ffd92c5 3168 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3169 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3170
2fb92db1
AK		 3171 vmx_segment_cache_clear(vmx);
3172
1ecd50a9
GN		 3173 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3174 vmx->rmode.segs[seg] = *var;
3175 if (seg == VCPU_SREG_TR)
3176 vmcs_write16(sf->selector, var->selector);
3177 else if (var->s)
3178 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3179 goto out;
653e3108 3180 }
1ecd50a9 3181
653e3108
AK		 3182 vmcs_writel(sf->base, var->base);
3183 vmcs_write32(sf->limit, var->limit);
3184 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3185
3186 /*
3187 * Fix the "Accessed" bit in AR field of segment registers for older
3188 * qemu binaries.
3189 * IA32 arch specifies that at the time of processor reset the
3190 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3191 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3192 * state vmexit when "unrestricted guest" mode is turned on.
3193 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3194 * tree. Newer qemu binaries with that qemu fix would not need this
3195 * kvm hack.
3196 */
3197 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3198 var->type |= 0x1; /* Accessed */
3a624e29 3199
f924d66d 3200 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3201
3202out:
98eb2f8b 3203 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3204}
3205
6aa8b732
AK		 3206static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3207{
2fb92db1 3208 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3209
3210 *db = (ar >> 14) & 1;
3211 *l = (ar >> 13) & 1;
3212}
3213
89a27f4d 3214static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3215{
89a27f4d
GN		 3216 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3217 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3218}
3219
89a27f4d 3220static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3221{
89a27f4d
GN		 3222 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3223 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3224}
3225
89a27f4d 3226static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3227{
89a27f4d
GN		 3228 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3229 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3230}
3231
89a27f4d 3232static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3233{
89a27f4d
GN		 3234 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3235 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3236}
3237
648dfaa7
MG		 3238static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3239{
3240 struct kvm_segment var;
3241 u32 ar;
3242
3243 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3244 var.dpl = 0x3;
0647f4aa
GN		 3245 if (seg == VCPU_SREG_CS)
3246 var.type = 0x3;
648dfaa7
MG		 3247 ar = vmx_segment_access_rights(&var);
3248
3249 if (var.base != (var.selector << 4))
3250 return false;
89efbed0 3251 if (var.limit != 0xffff)
648dfaa7 3252 return false;
07f42f5f 3253 if (ar != 0xf3)
648dfaa7
MG		 3254 return false;
3255
3256 return true;
3257}
3258
3259static bool code_segment_valid(struct kvm_vcpu *vcpu)
3260{
3261 struct kvm_segment cs;
3262 unsigned int cs_rpl;
3263
3264 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3265 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3266
1872a3f4
AK		 3267 if (cs.unusable)
3268 return false;
4d283ec9 3269 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3270 return false;
3271 if (!cs.s)
3272 return false;
4d283ec9 3273 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3274 if (cs.dpl > cs_rpl)
3275 return false;
1872a3f4 3276 } else {
648dfaa7
MG		 3277 if (cs.dpl != cs_rpl)
3278 return false;
3279 }
3280 if (!cs.present)
3281 return false;
3282
3283 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3284 return true;
3285}
3286
3287static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3288{
3289 struct kvm_segment ss;
3290 unsigned int ss_rpl;
3291
3292 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3293 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3294
1872a3f4
AK		 3295 if (ss.unusable)
3296 return true;
3297 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3298 return false;
3299 if (!ss.s)
3300 return false;
3301 if (ss.dpl != ss_rpl) /* DPL != RPL */
3302 return false;
3303 if (!ss.present)
3304 return false;
3305
3306 return true;
3307}
3308
3309static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3310{
3311 struct kvm_segment var;
3312 unsigned int rpl;
3313
3314 vmx_get_segment(vcpu, &var, seg);
b32a9918 3315 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3316
1872a3f4
AK		 3317 if (var.unusable)
3318 return true;
648dfaa7
MG		 3319 if (!var.s)
3320 return false;
3321 if (!var.present)
3322 return false;
4d283ec9 3323 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3324 if (var.dpl < rpl) /* DPL < RPL */
3325 return false;
3326 }
3327
3328 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3329 * rights flags
3330 */
3331 return true;
3332}
3333
3334static bool tr_valid(struct kvm_vcpu *vcpu)
3335{
3336 struct kvm_segment tr;
3337
3338 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3339
1872a3f4
AK		 3340 if (tr.unusable)
3341 return false;
b32a9918 3342 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3343 return false;
1872a3f4 3344 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3345 return false;
3346 if (!tr.present)
3347 return false;
3348
3349 return true;
3350}
3351
3352static bool ldtr_valid(struct kvm_vcpu *vcpu)
3353{
3354 struct kvm_segment ldtr;
3355
3356 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3357
1872a3f4
AK		 3358 if (ldtr.unusable)
3359 return true;
b32a9918 3360 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3361 return false;
3362 if (ldtr.type != 2)
3363 return false;
3364 if (!ldtr.present)
3365 return false;
3366
3367 return true;
3368}
3369
3370static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3371{
3372 struct kvm_segment cs, ss;
3373
3374 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3375 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3376
b32a9918
NA		 3377 return ((cs.selector & SEGMENT_RPL_MASK) ==
3378 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3379}
3380
3381/*
3382 * Check if guest state is valid. Returns true if valid, false if
3383 * not.
3384 * We assume that registers are always usable
3385 */
3386static bool guest_state_valid(struct kvm_vcpu *vcpu)
3387{
c5e97c80
GN		 3388 if (enable_unrestricted_guest)
3389 return true;
3390
648dfaa7 3391 /* real mode guest state checks */
f13882d8 3392 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3393 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3394 return false;
3395 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3396 return false;
3397 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3398 return false;
3399 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3400 return false;
3401 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3402 return false;
3403 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3404 return false;
3405 } else {
3406 /* protected mode guest state checks */
3407 if (!cs_ss_rpl_check(vcpu))
3408 return false;
3409 if (!code_segment_valid(vcpu))
3410 return false;
3411 if (!stack_segment_valid(vcpu))
3412 return false;
3413 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3414 return false;
3415 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3416 return false;
3417 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3418 return false;
3419 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3420 return false;
3421 if (!tr_valid(vcpu))
3422 return false;
3423 if (!ldtr_valid(vcpu))
3424 return false;
3425 }
3426 /* TODO:
3427 * - Add checks on RIP
3428 * - Add checks on RFLAGS
3429 */
3430
3431 return true;
3432}
3433
d77c26fc 3434static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3435{
40dcaa9f 3436 gfn_t fn;
195aefde 3437 u16 data = 0;
1f755a82 3438 int idx, r;
6aa8b732 3439
40dcaa9f 3440 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3441 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3442 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3443 if (r < 0)
10589a46 3444 goto out;
195aefde 3445 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3446 r = kvm_write_guest_page(kvm, fn++, &data,
3447 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3448 if (r < 0)
10589a46 3449 goto out;
195aefde
IE		 3450 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3451 if (r < 0)
10589a46 3452 goto out;
195aefde
IE		 3453 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3454 if (r < 0)
10589a46 3455 goto out;
195aefde 3456 data = ~0;
10589a46
MT		 3457 r = kvm_write_guest_page(kvm, fn, &data,
3458 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3459 sizeof(u8));
10589a46 3460out:
40dcaa9f 3461 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3462 return r;
6aa8b732
AK		 3463}
3464
b7ebfb05
SY		 3465static int init_rmode_identity_map(struct kvm *kvm)
3466{
40bbb9d0 3467 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
2a5755bb 3468 int i, r = 0;
ba049e93 3469 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3470 u32 tmp;
3471
40bbb9d0 3472 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3473 mutex_lock(&kvm->slots_lock);
3474
40bbb9d0 3475 if (likely(kvm_vmx->ept_identity_pagetable_done))
2a5755bb 3476 goto out;
a255d479 3477
40bbb9d0
SC		 3478 if (!kvm_vmx->ept_identity_map_addr)
3479 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3480 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3481
d8a6e365 3482 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3483 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3484 if (r < 0)
2a5755bb 3485 goto out;
a255d479 3486
b7ebfb05
SY		 3487 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3488 if (r < 0)
3489 goto out;
3490 /* Set up identity-mapping pagetable for EPT in real mode */
3491 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3492 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3493 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3494 r = kvm_write_guest_page(kvm, identity_map_pfn,
3495 &tmp, i * sizeof(tmp), sizeof(tmp));
3496 if (r < 0)
3497 goto out;
3498 }
40bbb9d0 3499 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3500
b7ebfb05 3501out:
a255d479 3502 mutex_unlock(&kvm->slots_lock);
f51770ed 3503 return r;
b7ebfb05
SY		 3504}
3505
6aa8b732
AK		 3506static void seg_setup(int seg)
3507{
772e0318 3508 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3509 unsigned int ar;
6aa8b732
AK		 3510
3511 vmcs_write16(sf->selector, 0);
3512 vmcs_writel(sf->base, 0);
3513 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3514 ar = 0x93;
3515 if (seg == VCPU_SREG_CS)
3516 ar |= 0x08; /* code segment */
3a624e29
NK		 3517
3518 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3519}
3520
f78e0e2e
SY		 3521static int alloc_apic_access_page(struct kvm *kvm)
3522{
4484141a 3523 struct page *page;
f78e0e2e
SY		 3524 int r = 0;
3525
79fac95e 3526 mutex_lock(&kvm->slots_lock);
c24ae0dc 3527 if (kvm->arch.apic_access_page_done)
f78e0e2e 3528 goto out;
1d8007bd
PB		 3529 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3530 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3531 if (r)
3532 goto out;
72dc67a6 3533
73a6d941 3534 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3535 if (is_error_page(page)) {
3536 r = -EFAULT;
3537 goto out;
3538 }
3539
c24ae0dc
TC		 3540 /*
3541 * Do not pin the page in memory, so that memory hot-unplug
3542 * is able to migrate it.
3543 */
3544 put_page(page);
3545 kvm->arch.apic_access_page_done = true;
f78e0e2e 3546out:
79fac95e 3547 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3548 return r;
3549}
3550
97b7ead3 3551int allocate_vpid(void)
2384d2b3
SY		 3552{
3553 int vpid;
3554
919818ab 3555 if (!enable_vpid)
991e7a0e 3556 return 0;
2384d2b3
SY		 3557 spin_lock(&vmx_vpid_lock);
3558 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3559 if (vpid < VMX_NR_VPIDS)
2384d2b3 3560 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3561 else
3562 vpid = 0;
2384d2b3 3563 spin_unlock(&vmx_vpid_lock);
991e7a0e 3564 return vpid;
2384d2b3
SY		 3565}
3566
97b7ead3 3567void free_vpid(int vpid)
cdbecfc3 3568{
991e7a0e 3569 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3570 return;
3571 spin_lock(&vmx_vpid_lock);
991e7a0e 3572 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3573 spin_unlock(&vmx_vpid_lock);
3574}
3575
1e4329ee 3576static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3577 u32 msr, int type)
25c5f225 3578{
3e7c73e9 3579 int f = sizeof(unsigned long);
25c5f225
SY		 3580
3581 if (!cpu_has_vmx_msr_bitmap())
3582 return;
3583
ceef7d10
VK		 3584 if (static_branch_unlikely(&enable_evmcs))
3585 evmcs_touch_msr_bitmap();
3586
25c5f225
SY		 3587 /*
3588 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3589 * have the write-low and read-high bitmap offsets the wrong way round.
3590 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3591 */
25c5f225 3592 if (msr <= 0x1fff) {
8d14695f
YZ		 3593 if (type & MSR_TYPE_R)
3594 /* read-low */
3595 __clear_bit(msr, msr_bitmap + 0x000 / f);
3596
3597 if (type & MSR_TYPE_W)
3598 /* write-low */
3599 __clear_bit(msr, msr_bitmap + 0x800 / f);
3600
25c5f225
SY		 3601 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3602 msr &= 0x1fff;
8d14695f
YZ		 3603 if (type & MSR_TYPE_R)
3604 /* read-high */
3605 __clear_bit(msr, msr_bitmap + 0x400 / f);
3606
3607 if (type & MSR_TYPE_W)
3608 /* write-high */
3609 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3610
3611 }
3612}
3613
1e4329ee 3614static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3615 u32 msr, int type)
3616{
3617 int f = sizeof(unsigned long);
3618
3619 if (!cpu_has_vmx_msr_bitmap())
3620 return;
3621
ceef7d10
VK		 3622 if (static_branch_unlikely(&enable_evmcs))
3623 evmcs_touch_msr_bitmap();
3624
904e14fb
PB		 3625 /*
3626 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3627 * have the write-low and read-high bitmap offsets the wrong way round.
3628 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3629 */
3630 if (msr <= 0x1fff) {
3631 if (type & MSR_TYPE_R)
3632 /* read-low */
3633 __set_bit(msr, msr_bitmap + 0x000 / f);
3634
3635 if (type & MSR_TYPE_W)
3636 /* write-low */
3637 __set_bit(msr, msr_bitmap + 0x800 / f);
3638
3639 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3640 msr &= 0x1fff;
3641 if (type & MSR_TYPE_R)
3642 /* read-high */
3643 __set_bit(msr, msr_bitmap + 0x400 / f);
3644
3645 if (type & MSR_TYPE_W)
3646 /* write-high */
3647 __set_bit(msr, msr_bitmap + 0xc00 / f);
3648
3649 }
3650}
3651
1e4329ee 3652static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3653 u32 msr, int type, bool value)
3654{
3655 if (value)
3656 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3657 else
3658 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3659}
3660
904e14fb 3661static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3662{
904e14fb
PB		 3663 u8 mode = 0;
3664
3665 if (cpu_has_secondary_exec_ctrls() &&
fe7f895d 3666 (secondary_exec_controls_get(to_vmx(vcpu)) &
904e14fb
PB		 3667 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3668 mode |= MSR_BITMAP_MODE_X2APIC;
3669 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3670 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3671 }
3672
904e14fb 3673 return mode;
8d14695f
YZ		 3674}
3675
904e14fb
PB		 3676static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3677 u8 mode)
8d14695f 3678{
904e14fb
PB		 3679 int msr;
3680
3681 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3682 unsigned word = msr / BITS_PER_LONG;
3683 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3684 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3685 }
3686
3687 if (mode & MSR_BITMAP_MODE_X2APIC) {
3688 /*
3689 * TPR reads and writes can be virtualized even if virtual interrupt
3690 * delivery is not in use.
3691 */
3692 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3693 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3694 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3695 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3696 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3697 }
f6e90f9e 3698 }
5897297b
AK		 3699}
3700
97b7ead3 3701void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3702{
3703 struct vcpu_vmx *vmx = to_vmx(vcpu);
3704 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3705 u8 mode = vmx_msr_bitmap_mode(vcpu);
3706 u8 changed = mode ^ vmx->msr_bitmap_mode;
3707
3708 if (!changed)
3709 return;
3710
904e14fb
PB		 3711 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3712 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3713
3714 vmx->msr_bitmap_mode = mode;
3715}
3716
b08c2896
CP		 3717void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3718{
3719 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3720 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3721 u32 i;
3722
3723 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3724 MSR_TYPE_RW, flag);
3725 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3726 MSR_TYPE_RW, flag);
3727 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3728 MSR_TYPE_RW, flag);
3729 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3730 MSR_TYPE_RW, flag);
3731 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3732 vmx_set_intercept_for_msr(msr_bitmap,
3733 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3734 vmx_set_intercept_for_msr(msr_bitmap,
3735 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3736 }
3737}
3738
e6c67d8c
LA		 3739static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3740{
3741 struct vcpu_vmx *vmx = to_vmx(vcpu);
3742 void *vapic_page;
3743 u32 vppr;
3744 int rvi;
3745
3746 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3747 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
96c66e87 3748 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
e6c67d8c
LA		 3749 return false;
3750
7e712684 3751 rvi = vmx_get_rvi();
e6c67d8c 3752
96c66e87 3753 vapic_page = vmx->nested.virtual_apic_map.hva;
e6c67d8c 3754 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
e6c67d8c
LA		 3755
3756 return ((rvi & 0xf0) > (vppr & 0xf0));
3757}
3758
06a5524f
WV		 3759static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3760 bool nested)
21bc8dc5
RK		 3761{
3762#ifdef CONFIG_SMP
06a5524f
WV		 3763 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3764
21bc8dc5 3765 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3766 /*
5753743f
HZ		 3767 * The vector of interrupt to be delivered to vcpu had
3768 * been set in PIR before this function.
3769 *
3770 * Following cases will be reached in this block, and
3771 * we always send a notification event in all cases as
3772 * explained below.
3773 *
3774 * Case 1: vcpu keeps in non-root mode. Sending a
3775 * notification event posts the interrupt to vcpu.
3776 *
3777 * Case 2: vcpu exits to root mode and is still
3778 * runnable. PIR will be synced to vIRR before the
3779 * next vcpu entry. Sending a notification event in
3780 * this case has no effect, as vcpu is not in root
3781 * mode.
28b835d6 3782 *
5753743f
HZ		 3783 * Case 3: vcpu exits to root mode and is blocked.
3784 * vcpu_block() has already synced PIR to vIRR and
3785 * never blocks vcpu if vIRR is not cleared. Therefore,
3786 * a blocked vcpu here does not wait for any requested
3787 * interrupts in PIR, and sending a notification event
3788 * which has no effect is safe here.
28b835d6 3789 */
28b835d6 3790
06a5524f 3791 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3792 return true;
3793 }
3794#endif
3795 return false;
3796}
3797
705699a1
WV		 3798static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3799 int vector)
3800{
3801 struct vcpu_vmx *vmx = to_vmx(vcpu);
3802
3803 if (is_guest_mode(vcpu) &&
3804 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3805 /*
3806 * If a posted intr is not recognized by hardware,
3807 * we will accomplish it in the next vmentry.
3808 */
3809 vmx->nested.pi_pending = true;
3810 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3811 /* the PIR and ON have been set by L1. */
3812 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3813 kvm_vcpu_kick(vcpu);
705699a1
WV		 3814 return 0;
3815 }
3816 return -1;
3817}
a20ed54d
YZ		 3818/*
3819 * Send interrupt to vcpu via posted interrupt way.
3820 * 1. If target vcpu is running(non-root mode), send posted interrupt
3821 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3822 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3823 * interrupt from PIR in next vmentry.
3824 */
91a5f413 3825static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
a20ed54d
YZ		 3826{
3827 struct vcpu_vmx *vmx = to_vmx(vcpu);
3828 int r;
3829
705699a1
WV		 3830 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3831 if (!r)
91a5f413
VK		 3832 return 0;
3833
3834 if (!vcpu->arch.apicv_active)
3835 return -1;
705699a1 3836
a20ed54d 3837 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
91a5f413 3838 return 0;
a20ed54d 3839
b95234c8
PB		 3840 /* If a previous notification has sent the IPI, nothing to do. */
3841 if (pi_test_and_set_on(&vmx->pi_desc))
91a5f413 3842 return 0;
b95234c8 3843
06a5524f 3844 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d 3845 kvm_vcpu_kick(vcpu);
91a5f413
VK		 3846
3847 return 0;
a20ed54d
YZ		 3848}
3849
a3a8ff8e
NHE		 3850/*
3851 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3852 * will not change in the lifetime of the guest.
3853 * Note that host-state that does change is set elsewhere. E.g., host-state
3854 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3855 */
97b7ead3 3856void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3857{
3858 u32 low32, high32;
3859 unsigned long tmpl;
d6e41f11 3860 unsigned long cr0, cr3, cr4;
a3a8ff8e 3861
04ac88ab
AL		 3862 cr0 = read_cr0();
3863 WARN_ON(cr0 & X86_CR0_TS);
3864 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3865
3866 /*
3867 * Save the most likely value for this task's CR3 in the VMCS.
3868 * We can't use __get_current_cr3_fast() because we're not atomic.
3869 */
6c690ee1 3870 cr3 = __read_cr3();
d6e41f11 3871 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3872 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3873
d974baa3 3874 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3875 cr4 = cr4_read_shadow();
d974baa3 3876 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3877 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3878
a3a8ff8e 3879 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3880#ifdef CONFIG_X86_64
3881 /*
3882 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3883 * vmx_prepare_switch_to_host(), in case userspace uses
3884 * the null selectors too (the expected case).
b2da15ac
AK		 3885 */
3886 vmcs_write16(HOST_DS_SELECTOR, 0);
3887 vmcs_write16(HOST_ES_SELECTOR, 0);
3888#else
a3a8ff8e
NHE		 3889 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3890 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3891#endif
a3a8ff8e
NHE		 3892 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3893 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3894
2342080c 3895 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
a3a8ff8e 3896
453eafbe 3897 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3898
3899 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3900 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3901 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3902 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3903
3904 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3905 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3906 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3907 }
5a5e8a15 3908
c73da3fc 3909 if (cpu_has_load_ia32_efer())
5a5e8a15 3910 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3911}
3912
97b7ead3 3913void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3914{
3915 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3916 if (enable_ept)
3917 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3918 if (is_guest_mode(&vmx->vcpu))
3919 vmx->vcpu.arch.cr4_guest_owned_bits &=
3920 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3921 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3922}
3923
c075c3e4 3924u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
01e439be
YZ		 3925{
3926 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3927
d62caabb 3928 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3929 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3930
3931 if (!enable_vnmi)
3932 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3933
804939ea
SC		 3934 if (!enable_preemption_timer)
3935 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3936
01e439be
YZ		 3937 return pin_based_exec_ctrl;
3938}
3939
d62caabb
AS		 3940static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3941{
3942 struct vcpu_vmx *vmx = to_vmx(vcpu);
3943
c5f2c766 3944 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3945 if (cpu_has_secondary_exec_ctrls()) {
3946 if (kvm_vcpu_apicv_active(vcpu))
fe7f895d 3947 secondary_exec_controls_setbit(vmx,
3ce424e4
RK		 3948 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3949 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3950 else
fe7f895d 3951 secondary_exec_controls_clearbit(vmx,
3ce424e4
RK		 3952 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3953 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3954 }
3955
3956 if (cpu_has_vmx_msr_bitmap())
904e14fb 3957 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3958}
3959
89b0c9f5
SC		 3960u32 vmx_exec_control(struct vcpu_vmx *vmx)
3961{
3962 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3963
3964 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3965 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3966
3967 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3968 exec_control &= ~CPU_BASED_TPR_SHADOW;
3969#ifdef CONFIG_X86_64
3970 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3971 CPU_BASED_CR8_LOAD_EXITING;
3972#endif
3973 }
3974 if (!enable_ept)
3975 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3976 CPU_BASED_CR3_LOAD_EXITING |
3977 CPU_BASED_INVLPG_EXITING;
3978 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3979 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3980 CPU_BASED_MONITOR_EXITING);
3981 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3982 exec_control &= ~CPU_BASED_HLT_EXITING;
3983 return exec_control;
3984}
3985
3986
80154d77 3987static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 3988{
80154d77
PB		 3989 struct kvm_vcpu *vcpu = &vmx->vcpu;
3990
bf8179a0 3991 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 3992
f99e3daf
CP		 3993 if (pt_mode == PT_MODE_SYSTEM)
3994 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 3995 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 3996 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3997 if (vmx->vpid == 0)
3998 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3999 if (!enable_ept) {
4000 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4001 enable_unrestricted_guest = 0;
4002 }
4003 if (!enable_unrestricted_guest)
4004 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 4005 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 4006 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 4007 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 4008 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4009 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4010 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 4011
4012 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4013 * in vmx_set_cr4. */
4014 exec_control &= ~SECONDARY_EXEC_DESC;
4015
abc4fc58
AG		 4016 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4017 (handle_vmptrld).
4018 We can NOT enable shadow_vmcs here because we don't have yet
4019 a current VMCS12
4020 */
4021 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 4022
4023 if (!enable_pml)
4024 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 4025
3db13480
PB		 4026 if (vmx_xsaves_supported()) {
4027 /* Exposing XSAVES only when XSAVE is exposed */
4028 bool xsaves_enabled =
96be4e06 4029 boot_cpu_has(X86_FEATURE_XSAVE) &&
3db13480
PB		 4030 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4031 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4032
7204160e
AL		 4033 vcpu->arch.xsaves_enabled = xsaves_enabled;
4034
3db13480
PB		 4035 if (!xsaves_enabled)
4036 exec_control &= ~SECONDARY_EXEC_XSAVES;
4037
4038 if (nested) {
4039 if (xsaves_enabled)
6677f3da 4040 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 4041 SECONDARY_EXEC_XSAVES;
4042 else
6677f3da 4043 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 4044 ~SECONDARY_EXEC_XSAVES;
4045 }
4046 }
4047
80154d77
PB		 4048 if (vmx_rdtscp_supported()) {
4049 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4050 if (!rdtscp_enabled)
4051 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4052
4053 if (nested) {
4054 if (rdtscp_enabled)
6677f3da 4055 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4056 SECONDARY_EXEC_RDTSCP;
4057 else
6677f3da 4058 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4059 ~SECONDARY_EXEC_RDTSCP;
4060 }
4061 }
4062
4063 if (vmx_invpcid_supported()) {
4064 /* Exposing INVPCID only when PCID is exposed */
4065 bool invpcid_enabled =
4066 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4067 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4068
4069 if (!invpcid_enabled) {
4070 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4071 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4072 }
4073
4074 if (nested) {
4075 if (invpcid_enabled)
6677f3da 4076 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 4077 SECONDARY_EXEC_ENABLE_INVPCID;
4078 else
6677f3da 4079 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 4080 ~SECONDARY_EXEC_ENABLE_INVPCID;
4081 }
4082 }
4083
45ec368c
JM		 4084 if (vmx_rdrand_supported()) {
4085 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4086 if (rdrand_enabled)
736fdf72 4087 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4088
4089 if (nested) {
4090 if (rdrand_enabled)
6677f3da 4091 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4092 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 4093 else
6677f3da 4094 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4095 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4096 }
4097 }
4098
75f4fc8d
JM		 4099 if (vmx_rdseed_supported()) {
4100 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4101 if (rdseed_enabled)
736fdf72 4102 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4103
4104 if (nested) {
4105 if (rdseed_enabled)
6677f3da 4106 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4107 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 4108 else
6677f3da 4109 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4110 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4111 }
4112 }
4113
e69e72fa
TX		 4114 if (vmx_waitpkg_supported()) {
4115 bool waitpkg_enabled =
4116 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4117
4118 if (!waitpkg_enabled)
4119 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4120
4121 if (nested) {
4122 if (waitpkg_enabled)
4123 vmx->nested.msrs.secondary_ctls_high |=
4124 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4125 else
4126 vmx->nested.msrs.secondary_ctls_high &=
4127 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4128 }
4129 }
4130
80154d77 4131 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 4132}
4133
ce88decf
XG		 4134static void ept_set_mmio_spte_mask(void)
4135{
4136 /*
4137 * EPT Misconfigurations can be generated if the value of bits 2:0
4138 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 4139 */
dcdca5fe 4140 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4af77151 4141 VMX_EPT_MISCONFIG_WX_VALUE, 0);
ce88decf
XG		 4142}
4143
f53cd63c 4144#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 4145
944c3464 4146/*
1b84292b
XL		 4147 * Noting that the initialization of Guest-state Area of VMCS is in
4148 * vmx_vcpu_reset().
944c3464 4149 */
1b84292b 4150static void init_vmcs(struct vcpu_vmx *vmx)
944c3464 4151{
944c3464 4152 if (nested)
1b84292b 4153 nested_vmx_set_vmcs_shadowing_bitmap();
944c3464 4154
25c5f225 4155 if (cpu_has_vmx_msr_bitmap())
904e14fb 4156 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4157
6aa8b732
AK		 4158 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4159
6aa8b732 4160 /* Control */
3af80fec 4161 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4162
3af80fec 4163 exec_controls_set(vmx, vmx_exec_control(vmx));
6aa8b732 4164
dfa169bb 4165 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4166 vmx_compute_secondary_exec_control(vmx);
3af80fec 4167 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
dfa169bb 4168 }
f78e0e2e 4169
d62caabb 4170 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4171 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4172 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4173 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4174 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4175
4176 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4177
0bcf261c 4178 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4179 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4180 }
4181
b31c114b 4182 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4183 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4184 vmx->ple_window = ple_window;
4185 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4186 }
4187
c3707958
XG		 4188 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4189 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4190 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4191
9581d442
AK		 4192 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4193 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4194 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4195 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4196 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4197
2a499e49
BD		 4198 if (cpu_has_vmx_vmfunc())
4199 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4200
2cc51560
ED		 4201 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4202 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4203 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4204 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4205 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4206
74545705
RK		 4207 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4208 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4209
3af80fec 4210 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4211
4212 /* 22.2.1, 20.8.1 */
3af80fec 4213 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
1c3d14fe 4214
bd7e5b08
PB		 4215 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4216 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4217
bf8179a0 4218 set_cr4_guest_host_mask(vmx);
e00c8cf2 4219
35fbe0d4
XL		 4220 if (vmx->vpid != 0)
4221 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4222
f53cd63c
WL		 4223 if (vmx_xsaves_supported())
4224 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4225
4e59516a 4226 if (enable_pml) {
4e59516a
PF		 4227 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4228 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4229 }
0b665d30
SC		 4230
4231 if (cpu_has_vmx_encls_vmexit())
4232 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4233
4234 if (pt_mode == PT_MODE_HOST_GUEST) {
4235 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4236 /* Bit[6~0] are forced to 1, writes are ignored. */
4237 vmx->pt_desc.guest.output_mask = 0x7F;
4238 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4239 }
e00c8cf2
AK		 4240}
4241
d28bc9dd 4242static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4243{
4244 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4245 struct msr_data apic_base_msr;
d28bc9dd 4246 u64 cr0;
e00c8cf2 4247
7ffd92c5 4248 vmx->rmode.vm86_active = 0;
d28b387f 4249 vmx->spec_ctrl = 0;
e00c8cf2 4250
6e3ba4ab
TX		 4251 vmx->msr_ia32_umwait_control = 0;
4252
ad312c7c 4253 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
95c06540 4254 vmx->hv_deadline_tsc = -1;
d28bc9dd
NA		 4255 kvm_set_cr8(vcpu, 0);
4256
4257 if (!init_event) {
4258 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4259 MSR_IA32_APICBASE_ENABLE;
4260 if (kvm_vcpu_is_reset_bsp(vcpu))
4261 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4262 apic_base_msr.host_initiated = true;
4263 kvm_set_apic_base(vcpu, &apic_base_msr);
4264 }
e00c8cf2 4265
2fb92db1
AK		 4266 vmx_segment_cache_clear(vmx);
4267
5706be0d 4268 seg_setup(VCPU_SREG_CS);
66450a21 4269 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4270 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4271
4272 seg_setup(VCPU_SREG_DS);
4273 seg_setup(VCPU_SREG_ES);
4274 seg_setup(VCPU_SREG_FS);
4275 seg_setup(VCPU_SREG_GS);
4276 seg_setup(VCPU_SREG_SS);
4277
4278 vmcs_write16(GUEST_TR_SELECTOR, 0);
4279 vmcs_writel(GUEST_TR_BASE, 0);
4280 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4281 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4282
4283 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4284 vmcs_writel(GUEST_LDTR_BASE, 0);
4285 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4286 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4287
d28bc9dd
NA		 4288 if (!init_event) {
4289 vmcs_write32(GUEST_SYSENTER_CS, 0);
4290 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4291 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4292 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4293 }
e00c8cf2 4294
c37c2873 4295 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4296 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4297
e00c8cf2
AK		 4298 vmcs_writel(GUEST_GDTR_BASE, 0);
4299 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4300
4301 vmcs_writel(GUEST_IDTR_BASE, 0);
4302 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4303
443381a8 4304 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4305 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4306 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4307 if (kvm_mpx_supported())
4308 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4309
e00c8cf2
AK		 4310 setup_msrs(vmx);
4311
6aa8b732
AK		 4312 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4313
d28bc9dd 4314 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4315 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4316 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4317 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4318 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4319 vmcs_write32(TPR_THRESHOLD, 0);
4320 }
4321
a73896cb 4322 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4323
d28bc9dd 4324 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4325 vmx->vcpu.arch.cr0 = cr0;
f2463247 4326 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4327 vmx_set_cr4(vcpu, 0);
5690891b 4328 vmx_set_efer(vcpu, 0);
bd7e5b08 4329
d28bc9dd 4330 update_exception_bitmap(vcpu);
6aa8b732 4331
dd5f5341 4332 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4333 if (init_event)
4334 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4335}
4336
55d2375e 4337static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4338{
9dadc2f9 4339 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
3b86cd99
JK		 4340}
4341
c9a7953f 4342static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4343{
d02fcf50 4344 if (!enable_vnmi ||
8a1b4392 4345 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4346 enable_irq_window(vcpu);
4347 return;
4348 }
3b86cd99 4349
4e2a0bc5 4350 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
3b86cd99
JK		 4351}
4352
66fd3f7f 4353static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4354{
9c8cba37 4355 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4356 uint32_t intr;
4357 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4358
229456fc 4359 trace_kvm_inj_virq(irq);
2714d1d3 4360
fa89a817 4361 ++vcpu->stat.irq_injections;
7ffd92c5 4362 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4363 int inc_eip = 0;
4364 if (vcpu->arch.interrupt.soft)
4365 inc_eip = vcpu->arch.event_exit_inst_len;
9497e1f2 4366 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
85f455f7
ED		 4367 return;
4368 }
66fd3f7f
GN		 4369 intr = irq | INTR_INFO_VALID_MASK;
4370 if (vcpu->arch.interrupt.soft) {
4371 intr |= INTR_TYPE_SOFT_INTR;
4372 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4373 vmx->vcpu.arch.event_exit_inst_len);
4374 } else
4375 intr |= INTR_TYPE_EXT_INTR;
4376 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4377
4378 vmx_clear_hlt(vcpu);
85f455f7
ED		 4379}
4380
f08864b4
SY		 4381static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4382{
66a5a347
JK		 4383 struct vcpu_vmx *vmx = to_vmx(vcpu);
4384
d02fcf50 4385 if (!enable_vnmi) {
8a1b4392
PB		 4386 /*
4387 * Tracking the NMI-blocked state in software is built upon
4388 * finding the next open IRQ window. This, in turn, depends on
4389 * well-behaving guests: They have to keep IRQs disabled at
4390 * least as long as the NMI handler runs. Otherwise we may
4391 * cause NMI nesting, maybe breaking the guest. But as this is
4392 * highly unlikely, we can live with the residual risk.
4393 */
4394 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4395 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4396 }
4397
4c4a6f79
PB		 4398 ++vcpu->stat.nmi_injections;
4399 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4400
7ffd92c5 4401 if (vmx->rmode.vm86_active) {
9497e1f2 4402 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
66a5a347
JK		 4403 return;
4404 }
c5a6d5f7 4405
f08864b4
SY		 4406 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4407 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4408
4409 vmx_clear_hlt(vcpu);
f08864b4
SY		 4410}
4411
97b7ead3 4412bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4413{
4c4a6f79
PB		 4414 struct vcpu_vmx *vmx = to_vmx(vcpu);
4415 bool masked;
4416
d02fcf50 4417 if (!enable_vnmi)
8a1b4392 4418 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4419 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4420 return false;
4c4a6f79
PB		 4421 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4422 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4423 return masked;
3cfc3092
JK		 4424}
4425
97b7ead3 4426void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4427{
4428 struct vcpu_vmx *vmx = to_vmx(vcpu);
4429
d02fcf50 4430 if (!enable_vnmi) {
8a1b4392
PB		 4431 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4432 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4433 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4434 }
4435 } else {
4436 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4437 if (masked)
4438 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4439 GUEST_INTR_STATE_NMI);
4440 else
4441 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4442 GUEST_INTR_STATE_NMI);
4443 }
3cfc3092
JK		 4444}
4445
2505dc9f
JK		 4446static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4447{
b6b8a145
JK		 4448 if (to_vmx(vcpu)->nested.nested_run_pending)
4449 return 0;
ea8ceb83 4450
d02fcf50 4451 if (!enable_vnmi &&
8a1b4392
PB		 4452 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4453 return 0;
4454
2505dc9f
JK		 4455 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4456 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4457 | GUEST_INTR_STATE_NMI));
4458}
4459
78646121
GN		 4460static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4461{
b6b8a145
JK		 4462 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4463 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4464 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4465 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4466}
4467
cbc94022
IE		 4468static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4469{
4470 int ret;
cbc94022 4471
f7eaeb0a
SC		 4472 if (enable_unrestricted_guest)
4473 return 0;
4474
6a3c623b
PX		 4475 mutex_lock(&kvm->slots_lock);
4476 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4477 PAGE_SIZE * 3);
4478 mutex_unlock(&kvm->slots_lock);
4479
cbc94022
IE		 4480 if (ret)
4481 return ret;
40bbb9d0 4482 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4483 return init_rmode_tss(kvm);
cbc94022
IE		 4484}
4485
2ac52ab8
SC		 4486static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4487{
40bbb9d0 4488 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4489 return 0;
4490}
4491
0ca1b4f4 4492static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4493{
77ab6db0 4494 switch (vec) {
77ab6db0 4495 case BP_VECTOR:
c573cd22
JK		 4496 /*
4497 * Update instruction length as we may reinject the exception
4498 * from user space while in guest debugging mode.
4499 */
4500 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4501 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4502 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4503 return false;
4504 /* fall through */
4505 case DB_VECTOR:
4506 if (vcpu->guest_debug &
4507 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4508 return false;
d0bfb940
JK		 4509 /* fall through */
4510 case DE_VECTOR:
77ab6db0
JK		 4511 case OF_VECTOR:
4512 case BR_VECTOR:
4513 case UD_VECTOR:
4514 case DF_VECTOR:
4515 case SS_VECTOR:
4516 case GP_VECTOR:
4517 case MF_VECTOR:
0ca1b4f4
GN		 4518 return true;
4519 break;
77ab6db0 4520 }
0ca1b4f4
GN		 4521 return false;
4522}
4523
4524static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4525 int vec, u32 err_code)
4526{
4527 /*
4528 * Instruction with address size override prefix opcode 0x67
4529 * Cause the #SS fault with 0 error code in VM86 mode.
4530 */
4531 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
60fc3d02 4532 if (kvm_emulate_instruction(vcpu, 0)) {
0ca1b4f4
GN		 4533 if (vcpu->arch.halt_request) {
4534 vcpu->arch.halt_request = 0;
5cb56059 4535 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4536 }
4537 return 1;
4538 }
4539 return 0;
4540 }
4541
4542 /*
4543 * Forward all other exceptions that are valid in real mode.
4544 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4545 * the required debugging infrastructure rework.
4546 */
4547 kvm_queue_exception(vcpu, vec);
4548 return 1;
6aa8b732
AK		 4549}
4550
a0861c02
AK		 4551/*
4552 * Trigger machine check on the host. We assume all the MSRs are already set up
4553 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4554 * We pass a fake environment to the machine check handler because we want
4555 * the guest to be always treated like user space, no matter what context
4556 * it used internally.
4557 */
4558static void kvm_machine_check(void)
4559{
4560#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4561 struct pt_regs regs = {
4562 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4563 .flags = X86_EFLAGS_IF,
4564 };
4565
4566 do_machine_check(&regs, 0);
4567#endif
4568}
4569
851ba692 4570static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02 4571{
95b5a48c 4572 /* handled by vmx_vcpu_run() */
a0861c02
AK		 4573 return 1;
4574}
4575
95b5a48c 4576static int handle_exception_nmi(struct kvm_vcpu *vcpu)
6aa8b732 4577{
1155f76a 4578 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4579 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4580 u32 intr_info, ex_no, error_code;
42dbaa5a 4581 unsigned long cr2, rip, dr6;
6aa8b732 4582 u32 vect_info;
6aa8b732 4583
1155f76a 4584 vect_info = vmx->idt_vectoring_info;
88786475 4585 intr_info = vmx->exit_intr_info;
6aa8b732 4586
2ea72039 4587 if (is_machine_check(intr_info) || is_nmi(intr_info))
95b5a48c 4588 return 1; /* handled by handle_exception_nmi_irqoff() */
2ab455cc 4589
082d06ed
WL		 4590 if (is_invalid_opcode(intr_info))
4591 return handle_ud(vcpu);
7aa81cc0 4592
6aa8b732 4593 error_code = 0;
2e11384c 4594 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4595 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4596
9e869480
LA		 4597 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4598 WARN_ON_ONCE(!enable_vmware_backdoor);
a6c6ed1e
SC		 4599
4600 /*
4601 * VMware backdoor emulation on #GP interception only handles
4602 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4603 * error code on #GP.
4604 */
4605 if (error_code) {
4606 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4607 return 1;
4608 }
60fc3d02 4609 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9e869480
LA		 4610 }
4611
bf4ca23e
XG		 4612 /*
4613 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4614 * MMIO, it is better to report an internal error.
4615 * See the comments in vmx_handle_exit.
4616 */
4617 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4618 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4619 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4620 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4621 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4622 vcpu->run->internal.data[0] = vect_info;
4623 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4624 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4625 return 0;
4626 }
4627
6aa8b732
AK		 4628 if (is_page_fault(intr_info)) {
4629 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4630 /* EPT won't cause page fault directly */
4631 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4632 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4633 }
4634
d0bfb940 4635 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4636
4637 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4638 return handle_rmode_exception(vcpu, ex_no, error_code);
4639
42dbaa5a 4640 switch (ex_no) {
54a20552
EN		 4641 case AC_VECTOR:
4642 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4643 return 1;
42dbaa5a
JK		 4644 case DB_VECTOR:
4645 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4646 if (!(vcpu->guest_debug &
4647 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1fc5d194 4648 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4649 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4650 if (is_icebp(intr_info))
1957aa63 4651 WARN_ON(!skip_emulated_instruction(vcpu));
fd2a445a 4652
42dbaa5a
JK		 4653 kvm_queue_exception(vcpu, DB_VECTOR);
4654 return 1;
4655 }
4656 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4657 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4658 /* fall through */
4659 case BP_VECTOR:
c573cd22
JK		 4660 /*
4661 * Update instruction length as we may reinject #BP from
4662 * user space while in guest debugging mode. Reading it for
4663 * #DB as well causes no harm, it is not used in that case.
4664 */
4665 vmx->vcpu.arch.event_exit_inst_len =
4666 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4667 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4668 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4669 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4670 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4671 break;
4672 default:
d0bfb940
JK		 4673 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4674 kvm_run->ex.exception = ex_no;
4675 kvm_run->ex.error_code = error_code;
42dbaa5a 4676 break;
6aa8b732 4677 }
6aa8b732
AK		 4678 return 0;
4679}
4680
f399e60c 4681static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4682{
1165f5fe 4683 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4684 return 1;
4685}
4686
851ba692 4687static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4688{
851ba692 4689 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4690 vcpu->mmio_needed = 0;
988ad74f
AK		 4691 return 0;
4692}
6aa8b732 4693
851ba692 4694static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4695{
bfdaab09 4696 unsigned long exit_qualification;
dca7f128 4697 int size, in, string;
039576c0 4698 unsigned port;
6aa8b732 4699
bfdaab09 4700 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4701 string = (exit_qualification & 16) != 0;
e70669ab 4702
cf8f70bf 4703 ++vcpu->stat.io_exits;
e70669ab 4704
432baf60 4705 if (string)
60fc3d02 4706 return kvm_emulate_instruction(vcpu, 0);
e70669ab 4707
cf8f70bf
GN		 4708 port = exit_qualification >> 16;
4709 size = (exit_qualification & 7) + 1;
432baf60 4710 in = (exit_qualification & 8) != 0;
cf8f70bf 4711
dca7f128 4712 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4713}
4714
102d8325
IM		 4715static void
4716vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4717{
4718 /*
4719 * Patch in the VMCALL instruction:
4720 */
4721 hypercall[0] = 0x0f;
4722 hypercall[1] = 0x01;
4723 hypercall[2] = 0xc1;
102d8325
IM		 4724}
4725
0fa06071 4726/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4727static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4728{
eeadf9e7 4729 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4730 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4731 unsigned long orig_val = val;
4732
eeadf9e7
NHE		 4733 /*
4734 * We get here when L2 changed cr0 in a way that did not change
4735 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4736 * but did change L0 shadowed bits. So we first calculate the
4737 * effective cr0 value that L1 would like to write into the
4738 * hardware. It consists of the L2-owned bits from the new
4739 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4740 */
1a0d74e6
JK		 4741 val = (val & ~vmcs12->cr0_guest_host_mask) |
4742 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4743
3899152c 4744 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4745 return 1;
1a0d74e6
JK		 4746
4747 if (kvm_set_cr0(vcpu, val))
4748 return 1;
4749 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4750 return 0;
1a0d74e6
JK		 4751 } else {
4752 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4753 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4754 return 1;
3899152c 4755
eeadf9e7 4756 return kvm_set_cr0(vcpu, val);
1a0d74e6 4757 }
eeadf9e7
NHE		 4758}
4759
4760static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4761{
4762 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4763 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4764 unsigned long orig_val = val;
4765
4766 /* analogously to handle_set_cr0 */
4767 val = (val & ~vmcs12->cr4_guest_host_mask) |
4768 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4769 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4770 return 1;
1a0d74e6 4771 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4772 return 0;
4773 } else
4774 return kvm_set_cr4(vcpu, val);
4775}
4776
0367f205
PB		 4777static int handle_desc(struct kvm_vcpu *vcpu)
4778{
4779 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
60fc3d02 4780 return kvm_emulate_instruction(vcpu, 0);
0367f205
PB		 4781}
4782
851ba692 4783static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4784{
229456fc 4785 unsigned long exit_qualification, val;
6aa8b732
AK		 4786 int cr;
4787 int reg;
49a9b07e 4788 int err;
6affcbed 4789 int ret;
6aa8b732 4790
bfdaab09 4791 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4792 cr = exit_qualification & 15;
4793 reg = (exit_qualification >> 8) & 15;
4794 switch ((exit_qualification >> 4) & 3) {
4795 case 0: /* mov to cr */
1e32c079 4796 val = kvm_register_readl(vcpu, reg);
229456fc 4797 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4798 switch (cr) {
4799 case 0:
eeadf9e7 4800 err = handle_set_cr0(vcpu, val);
6affcbed 4801 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4802 case 3:
e1de91cc 4803 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4804 err = kvm_set_cr3(vcpu, val);
6affcbed 4805 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4806 case 4:
eeadf9e7 4807 err = handle_set_cr4(vcpu, val);
6affcbed 4808 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4809 case 8: {
4810 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4811 u8 cr8 = (u8)val;
eea1cff9 4812 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4813 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4814 if (lapic_in_kernel(vcpu))
6affcbed 4815 return ret;
0a5fff19 4816 if (cr8_prev <= cr8)
6affcbed
KH		 4817 return ret;
4818 /*
4819 * TODO: we might be squashing a
4820 * KVM_GUESTDBG_SINGLESTEP-triggered
4821 * KVM_EXIT_DEBUG here.
4822 */
851ba692 4823 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4824 return 0;
4825 }
4b8073e4 4826 }
6aa8b732 4827 break;
25c4c276 4828 case 2: /* clts */
bd7e5b08
PB		 4829 WARN_ONCE(1, "Guest should always own CR0.TS");
4830 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4831 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4832 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4833 case 1: /*mov from cr*/
4834 switch (cr) {
4835 case 3:
e1de91cc 4836 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4837 val = kvm_read_cr3(vcpu);
4838 kvm_register_write(vcpu, reg, val);
4839 trace_kvm_cr_read(cr, val);
6affcbed 4840 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4841 case 8:
229456fc
MT		 4842 val = kvm_get_cr8(vcpu);
4843 kvm_register_write(vcpu, reg, val);
4844 trace_kvm_cr_read(cr, val);
6affcbed 4845 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4846 }
4847 break;
4848 case 3: /* lmsw */
a1f83a74 4849 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4850 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4851 kvm_lmsw(vcpu, val);
6aa8b732 4852
6affcbed 4853 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4854 default:
4855 break;
4856 }
851ba692 4857 vcpu->run->exit_reason = 0;
a737f256 4858 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4859 (int)(exit_qualification >> 4) & 3, cr);
4860 return 0;
4861}
4862
851ba692 4863static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4864{
bfdaab09 4865 unsigned long exit_qualification;
16f8a6f9
NA		 4866 int dr, dr7, reg;
4867
4868 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4869 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4870
4871 /* First, if DR does not exist, trigger UD */
4872 if (!kvm_require_dr(vcpu, dr))
4873 return 1;
6aa8b732 4874
f2483415 4875 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4876 if (!kvm_require_cpl(vcpu, 0))
4877 return 1;
16f8a6f9
NA		 4878 dr7 = vmcs_readl(GUEST_DR7);
4879 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4880 /*
4881 * As the vm-exit takes precedence over the debug trap, we
4882 * need to emulate the latter, either for the host or the
4883 * guest debugging itself.
4884 */
4885 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4886 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4887 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4888 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4889 vcpu->run->debug.arch.exception = DB_VECTOR;
4890 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4891 return 0;
4892 } else {
1fc5d194 4893 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4894 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4895 kvm_queue_exception(vcpu, DB_VECTOR);
4896 return 1;
4897 }
4898 }
4899
81908bf4 4900 if (vcpu->guest_debug == 0) {
2183f564 4901 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4902
4903 /*
4904 * No more DR vmexits; force a reload of the debug registers
4905 * and reenter on this instruction. The next vmexit will
4906 * retrieve the full state of the debug registers.
4907 */
4908 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4909 return 1;
4910 }
4911
42dbaa5a
JK		 4912 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4913 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4914 unsigned long val;
4c4d563b
JK		 4915
4916 if (kvm_get_dr(vcpu, dr, &val))
4917 return 1;
4918 kvm_register_write(vcpu, reg, val);
020df079 4919 } else
5777392e 4920 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4921 return 1;
4922
6affcbed 4923 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4924}
4925
73aaf249
JK		 4926static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4927{
4928 return vcpu->arch.dr6;
4929}
4930
4931static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4932{
4933}
4934
81908bf4
PB		 4935static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4936{
81908bf4
PB		 4937 get_debugreg(vcpu->arch.db[0], 0);
4938 get_debugreg(vcpu->arch.db[1], 1);
4939 get_debugreg(vcpu->arch.db[2], 2);
4940 get_debugreg(vcpu->arch.db[3], 3);
4941 get_debugreg(vcpu->arch.dr6, 6);
4942 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4943
4944 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2183f564 4945 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4946}
4947
020df079
GN		 4948static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4949{
4950 vmcs_writel(GUEST_DR7, val);
4951}
4952
851ba692 4953static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4954{
eb90f341 4955 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4956 return 1;
4957}
4958
851ba692 4959static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4960{
9dadc2f9 4961 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
2714d1d3 4962
3842d135
AK		 4963 kvm_make_request(KVM_REQ_EVENT, vcpu);
4964
a26bf12a 4965 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4966 return 1;
4967}
4968
851ba692 4969static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4970{
0d9c055e 4971 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 4972}
4973
ec25d5e6
GN		 4974static int handle_invd(struct kvm_vcpu *vcpu)
4975{
60fc3d02 4976 return kvm_emulate_instruction(vcpu, 0);
ec25d5e6
GN		 4977}
4978
851ba692 4979static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4980{
f9c617f6 4981 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4982
4983 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 4984 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 4985}
4986
fee84b07
AK		 4987static int handle_rdpmc(struct kvm_vcpu *vcpu)
4988{
4989 int err;
4990
4991 err = kvm_rdpmc(vcpu);
6affcbed 4992 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 4993}
4994
851ba692 4995static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 4996{
6affcbed 4997 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4998}
4999
2acf923e
DC		 5000static int handle_xsetbv(struct kvm_vcpu *vcpu)
5001{
5002 u64 new_bv = kvm_read_edx_eax(vcpu);
de3cd117 5003 u32 index = kvm_rcx_read(vcpu);
2acf923e
DC		 5004
5005 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 5006 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 5007 return 1;
5008}
5009
851ba692 5010static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5011{
58fbbf26
KT		 5012 if (likely(fasteoi)) {
5013 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5014 int access_type, offset;
5015
5016 access_type = exit_qualification & APIC_ACCESS_TYPE;
5017 offset = exit_qualification & APIC_ACCESS_OFFSET;
5018 /*
5019 * Sane guest uses MOV to write EOI, with written value
5020 * not cared. So make a short-circuit here by avoiding
5021 * heavy instruction emulation.
5022 */
5023 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5024 (offset == APIC_EOI)) {
5025 kvm_lapic_set_eoi(vcpu);
6affcbed 5026 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 5027 }
5028 }
60fc3d02 5029 return kvm_emulate_instruction(vcpu, 0);
f78e0e2e
SY		 5030}
5031
c7c9c56c
YZ		 5032static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5033{
5034 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5035 int vector = exit_qualification & 0xff;
5036
5037 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5038 kvm_apic_set_eoi_accelerated(vcpu, vector);
5039 return 1;
5040}
5041
83d4c286
YZ		 5042static int handle_apic_write(struct kvm_vcpu *vcpu)
5043{
5044 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5045 u32 offset = exit_qualification & 0xfff;
5046
5047 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5048 kvm_apic_write_nodecode(vcpu, offset);
5049 return 1;
5050}
5051
851ba692 5052static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5053{
60637aac 5054 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5055 unsigned long exit_qualification;
e269fb21
JK		 5056 bool has_error_code = false;
5057 u32 error_code = 0;
37817f29 5058 u16 tss_selector;
7f3d35fd 5059 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5060
5061 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5062 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5063 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5064
5065 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5066
5067 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5068 if (reason == TASK_SWITCH_GATE && idt_v) {
5069 switch (type) {
5070 case INTR_TYPE_NMI_INTR:
5071 vcpu->arch.nmi_injected = false;
654f06fc 5072 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5073 break;
5074 case INTR_TYPE_EXT_INTR:
66fd3f7f 5075 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5076 kvm_clear_interrupt_queue(vcpu);
5077 break;
5078 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5079 if (vmx->idt_vectoring_info &
5080 VECTORING_INFO_DELIVER_CODE_MASK) {
5081 has_error_code = true;
5082 error_code =
5083 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5084 }
5085 /* fall through */
64a7ec06
GN		 5086 case INTR_TYPE_SOFT_EXCEPTION:
5087 kvm_clear_exception_queue(vcpu);
5088 break;
5089 default:
5090 break;
5091 }
60637aac 5092 }
37817f29
IE		 5093 tss_selector = exit_qualification;
5094
64a7ec06
GN		 5095 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5096 type != INTR_TYPE_EXT_INTR &&
5097 type != INTR_TYPE_NMI_INTR))
1957aa63 5098 WARN_ON(!skip_emulated_instruction(vcpu));
64a7ec06 5099
42dbaa5a
JK		 5100 /*
5101 * TODO: What about debug traps on tss switch?
5102 * Are we supposed to inject them and update dr6?
5103 */
1051778f
SC		 5104 return kvm_task_switch(vcpu, tss_selector,
5105 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
60fc3d02 5106 reason, has_error_code, error_code);
37817f29
IE		 5107}
5108
851ba692 5109static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5110{
f9c617f6 5111 unsigned long exit_qualification;
1439442c 5112 gpa_t gpa;
eebed243 5113 u64 error_code;
1439442c 5114
f9c617f6 5115 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5116
0be9c7a8
GN		 5117 /*
5118 * EPT violation happened while executing iret from NMI,
5119 * "blocked by NMI" bit has to be set before next VM entry.
5120 * There are errata that may cause this bit to not be set:
5121 * AAK134, BY25.
5122 */
bcd1c294 5123 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5124 enable_vnmi &&
bcd1c294 5125 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5126 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5127
1439442c 5128 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5129 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5130
27959a44 5131 /* Is it a read fault? */
ab22a473 5132 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5133 ? PFERR_USER_MASK : 0;
5134 /* Is it a write fault? */
ab22a473 5135 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5136 ? PFERR_WRITE_MASK : 0;
5137 /* Is it a fetch fault? */
ab22a473 5138 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5139 ? PFERR_FETCH_MASK : 0;
5140 /* ept page table entry is present? */
5141 error_code |= (exit_qualification &
5142 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5143 EPT_VIOLATION_EXECUTABLE))
5144 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5145
eebed243
PB		 5146 error_code |= (exit_qualification & 0x100) != 0 ?
5147 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5148
25d92081 5149 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5150 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5151}
5152
851ba692 5153static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5154{
68f89400
MT		 5155 gpa_t gpa;
5156
9034e6e8
PB		 5157 /*
5158 * A nested guest cannot optimize MMIO vmexits, because we have an
5159 * nGPA here instead of the required GPA.
5160 */
68f89400 5161 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5162 if (!is_guest_mode(vcpu) &&
5163 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5164 trace_kvm_fast_mmio(gpa);
1957aa63 5165 return kvm_skip_emulated_instruction(vcpu);
68c3b4d1 5166 }
68f89400 5167
c75d0edc 5168 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5169}
5170
851ba692 5171static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5172{
d02fcf50 5173 WARN_ON_ONCE(!enable_vnmi);
4e2a0bc5 5174 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
f08864b4 5175 ++vcpu->stat.nmi_window_exits;
3842d135 5176 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5177
5178 return 1;
5179}
5180
80ced186 5181static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5182{
8b3079a5 5183 struct vcpu_vmx *vmx = to_vmx(vcpu);
49e9d557 5184 bool intr_window_requested;
b8405c18 5185 unsigned count = 130;
49e9d557 5186
2bb8cafe
SC		 5187 /*
5188 * We should never reach the point where we are emulating L2
5189 * due to invalid guest state as that means we incorrectly
5190 * allowed a nested VMEntry with an invalid vmcs12.
5191 */
5192 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5193
2183f564 5194 intr_window_requested = exec_controls_get(vmx) &
9dadc2f9 5195 CPU_BASED_INTR_WINDOW_EXITING;
ea953ef0 5196
98eb2f8b 5197 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5198 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5199 return handle_interrupt_window(&vmx->vcpu);
5200
72875d8a 5201 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5202 return 1;
5203
60fc3d02 5204 if (!kvm_emulate_instruction(vcpu, 0))
8fff2710 5205 return 0;
1d5a4d9b 5206
add5ff7a 5207 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
8fff2710
SC		 5208 vcpu->arch.exception.pending) {
5209 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5210 vcpu->run->internal.suberror =
5211 KVM_INTERNAL_ERROR_EMULATION;
5212 vcpu->run->internal.ndata = 0;
5213 return 0;
5214 }
ea953ef0 5215
8d76c49e
GN		 5216 if (vcpu->arch.halt_request) {
5217 vcpu->arch.halt_request = 0;
8fff2710 5218 return kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5219 }
5220
8fff2710
SC		 5221 /*
5222 * Note, return 1 and not 0, vcpu_run() is responsible for
5223 * morphing the pending signal into the proper return code.
5224 */
ea953ef0 5225 if (signal_pending(current))
8fff2710
SC		 5226 return 1;
5227
ea953ef0
MG		 5228 if (need_resched())
5229 schedule();
5230 }
5231
8fff2710 5232 return 1;
b4a2d31d
RK		 5233}
5234
5235static void grow_ple_window(struct kvm_vcpu *vcpu)
5236{
5237 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5238 unsigned int old = vmx->ple_window;
b4a2d31d 5239
c8e88717
BM		 5240 vmx->ple_window = __grow_ple_window(old, ple_window,
5241 ple_window_grow,
5242 ple_window_max);
b4a2d31d 5243
4f75bcc3 5244 if (vmx->ple_window != old) {
b4a2d31d 5245 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5246 trace_kvm_ple_window_update(vcpu->vcpu_id,
5247 vmx->ple_window, old);
5248 }
b4a2d31d
RK		 5249}
5250
5251static void shrink_ple_window(struct kvm_vcpu *vcpu)
5252{
5253 struct vcpu_vmx *vmx = to_vmx(vcpu);
c5c5d6fa 5254 unsigned int old = vmx->ple_window;
b4a2d31d 5255
c8e88717
BM		 5256 vmx->ple_window = __shrink_ple_window(old, ple_window,
5257 ple_window_shrink,
5258 ple_window);
b4a2d31d 5259
4f75bcc3 5260 if (vmx->ple_window != old) {
b4a2d31d 5261 vmx->ple_window_dirty = true;
4f75bcc3
PX		 5262 trace_kvm_ple_window_update(vcpu->vcpu_id,
5263 vmx->ple_window, old);
5264 }
b4a2d31d
RK		 5265}
5266
bf9f6ac8
FW		 5267/*
5268 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5269 */
5270static void wakeup_handler(void)
5271{
5272 struct kvm_vcpu *vcpu;
5273 int cpu = smp_processor_id();
5274
5275 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5276 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5277 blocked_vcpu_list) {
5278 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5279
5280 if (pi_test_on(pi_desc) == 1)
5281 kvm_vcpu_kick(vcpu);
5282 }
5283 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5284}
5285
e01bca2f 5286static void vmx_enable_tdp(void)
f160c7b7
JS		 5287{
5288 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5289 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5290 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5291 0ull, VMX_EPT_EXECUTABLE_MASK,
5292 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5293 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5294
5295 ept_set_mmio_spte_mask();
5296 kvm_enable_tdp();
5297}
5298
4b8d54f9
ZE		 5299/*
5300 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5301 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5302 */
9fb41ba8 5303static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5304{
b31c114b 5305 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5306 grow_ple_window(vcpu);
5307
de63ad4c
LM		 5308 /*
5309 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5310 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5311 * never set PAUSE_EXITING and just set PLE if supported,
5312 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5313 */
5314 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5315 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5316}
5317
87c00572 5318static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5319{
6affcbed 5320 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5321}
5322
87c00572
GS		 5323static int handle_mwait(struct kvm_vcpu *vcpu)
5324{
5325 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5326 return handle_nop(vcpu);
5327}
5328
45ec368c
JM		 5329static int handle_invalid_op(struct kvm_vcpu *vcpu)
5330{
5331 kvm_queue_exception(vcpu, UD_VECTOR);
5332 return 1;
5333}
5334
5f3d45e7
MD		 5335static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5336{
5337 return 1;
5338}
5339
87c00572
GS		 5340static int handle_monitor(struct kvm_vcpu *vcpu)
5341{
5342 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5343 return handle_nop(vcpu);
5344}
5345
55d2375e 5346static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5347{
55d2375e
SC		 5348 u32 vmx_instruction_info;
5349 unsigned long type;
5350 bool pcid_enabled;
5351 gva_t gva;
5352 struct x86_exception e;
5353 unsigned i;
5354 unsigned long roots_to_free = 0;
5355 struct {
5356 u64 pcid;
5357 u64 gla;
5358 } operand;
f9eb4af6 5359
55d2375e 5360 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5361 kvm_queue_exception(vcpu, UD_VECTOR);
5362 return 1;
5363 }
5364
55d2375e
SC		 5365 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5366 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5367
5368 if (type > 3) {
5369 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5370 return 1;
5371 }
5372
55d2375e
SC		 5373 /* According to the Intel instruction reference, the memory operand
5374 * is read even if it isn't needed (e.g., for type==all)
5375 */
3573e22c 5376 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
fdb28619
EK		 5377 vmx_instruction_info, false,
5378 sizeof(operand), &gva))
3573e22c
BD		 5379 return 1;
5380
55d2375e 5381 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5382 kvm_inject_page_fault(vcpu, &e);
5383 return 1;
5384 }
5385
55d2375e
SC		 5386 if (operand.pcid >> 12 != 0) {
5387 kvm_inject_gp(vcpu, 0);
5388 return 1;
abfc52c6 5389 }
e29acc55 5390
55d2375e 5391 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5392
55d2375e
SC		 5393 switch (type) {
5394 case INVPCID_TYPE_INDIV_ADDR:
5395 if ((!pcid_enabled && (operand.pcid != 0)) ||
5396 is_noncanonical_address(operand.gla, vcpu)) {
5397 kvm_inject_gp(vcpu, 0);
5398 return 1;
5399 }
5400 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5401 return kvm_skip_emulated_instruction(vcpu);
61ada748 5402
55d2375e
SC		 5403 case INVPCID_TYPE_SINGLE_CTXT:
5404 if (!pcid_enabled && (operand.pcid != 0)) {
5405 kvm_inject_gp(vcpu, 0);
5406 return 1;
5407 }
e29acc55 5408
55d2375e
SC		 5409 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5410 kvm_mmu_sync_roots(vcpu);
5411 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5412 }
e29acc55 5413
55d2375e
SC		 5414 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5415 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5416 == operand.pcid)
5417 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5418
55d2375e
SC		 5419 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5420 /*
5421 * If neither the current cr3 nor any of the prev_roots use the
5422 * given PCID, then nothing needs to be done here because a
5423 * resync will happen anyway before switching to any other CR3.
5424 */
e29acc55 5425
55d2375e 5426 return kvm_skip_emulated_instruction(vcpu);
61ada748 5427
55d2375e
SC		 5428 case INVPCID_TYPE_ALL_NON_GLOBAL:
5429 /*
5430 * Currently, KVM doesn't mark global entries in the shadow
5431 * page tables, so a non-global flush just degenerates to a
5432 * global flush. If needed, we could optimize this later by
5433 * keeping track of global entries in shadow page tables.
5434 */
e29acc55 5435
55d2375e
SC		 5436 /* fall-through */
5437 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5438 kvm_mmu_unload(vcpu);
5439 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5440
55d2375e
SC		 5441 default:
5442 BUG(); /* We have already checked above that type <= 3 */
5443 }
e29acc55
JM		 5444}
5445
55d2375e 5446static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5447{
55d2375e 5448 unsigned long exit_qualification;
b3897a49 5449
55d2375e 5450 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5451
55d2375e 5452 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5453
5454 /*
55d2375e
SC		 5455 * PML buffer FULL happened while executing iret from NMI,
5456 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5457 */
55d2375e
SC		 5458 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5459 enable_vnmi &&
5460 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5461 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5462 GUEST_INTR_STATE_NMI);
e49fcb8b 5463
55d2375e
SC		 5464 /*
5465 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5466 * here.., and there's no userspace involvement needed for PML.
5467 */
ec378aee
NHE		 5468 return 1;
5469}
5470
55d2375e 5471static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5472{
804939ea
SC		 5473 struct vcpu_vmx *vmx = to_vmx(vcpu);
5474
5475 if (!vmx->req_immediate_exit &&
5476 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
55d2375e 5477 kvm_lapic_expired_hv_timer(vcpu);
804939ea 5478
55d2375e 5479 return 1;
8ca44e88
DM		 5480}
5481
55d2375e
SC		 5482/*
5483 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5484 * are overwritten by nested_vmx_setup() when nested=1.
5485 */
5486static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5487{
55d2375e
SC		 5488 kvm_queue_exception(vcpu, UD_VECTOR);
5489 return 1;
b8bbab92
VK		 5490}
5491
55d2375e 5492static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5493{
55d2375e
SC		 5494 /*
5495 * SGX virtualization is not yet supported. There is no software
5496 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5497 * to prevent the guest from executing ENCLS.
5498 */
5499 kvm_queue_exception(vcpu, UD_VECTOR);
5500 return 1;
e7953d7f
AG		 5501}
5502
ec378aee 5503/*
55d2375e
SC		 5504 * The exit handlers return 1 if the exit was handled fully and guest execution
5505 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5506 * to be done to userspace and return 0.
ec378aee 5507 */
55d2375e 5508static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
95b5a48c 5509 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
55d2375e
SC		 5510 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5511 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5512 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5513 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5514 [EXIT_REASON_CR_ACCESS] = handle_cr,
5515 [EXIT_REASON_DR_ACCESS] = handle_dr,
f399e60c
AA		 5516 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5517 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5518 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
9dadc2f9 5519 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
f399e60c 5520 [EXIT_REASON_HLT] = kvm_emulate_halt,
55d2375e
SC		 5521 [EXIT_REASON_INVD] = handle_invd,
5522 [EXIT_REASON_INVLPG] = handle_invlpg,
5523 [EXIT_REASON_RDPMC] = handle_rdpmc,
5524 [EXIT_REASON_VMCALL] = handle_vmcall,
5525 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5526 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5527 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5528 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5529 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5530 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5531 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5532 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5533 [EXIT_REASON_VMON] = handle_vmx_instruction,
5534 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5535 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5536 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5537 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5538 [EXIT_REASON_WBINVD] = handle_wbinvd,
5539 [EXIT_REASON_XSETBV] = handle_xsetbv,
5540 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5541 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5542 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5543 [EXIT_REASON_LDTR_TR] = handle_desc,
5544 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5545 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5546 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5547 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5548 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5549 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5550 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5551 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5552 [EXIT_REASON_RDRAND] = handle_invalid_op,
5553 [EXIT_REASON_RDSEED] = handle_invalid_op,
55d2375e
SC		 5554 [EXIT_REASON_PML_FULL] = handle_pml_full,
5555 [EXIT_REASON_INVPCID] = handle_invpcid,
5556 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5557 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5558 [EXIT_REASON_ENCLS] = handle_encls,
5559};
b8bbab92 5560
55d2375e
SC		 5561static const int kvm_vmx_max_exit_handlers =
5562 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5563
55d2375e 5564static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5565{
55d2375e
SC		 5566 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5567 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5568}
5569
55d2375e 5570static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5571{
55d2375e
SC		 5572 if (vmx->pml_pg) {
5573 __free_page(vmx->pml_pg);
5574 vmx->pml_pg = NULL;
b8bbab92 5575 }
27d6c865
NHE		 5576}
5577
55d2375e 5578static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5579{
55d2375e
SC		 5580 struct vcpu_vmx *vmx = to_vmx(vcpu);
5581 u64 *pml_buf;
5582 u16 pml_idx;
cd232ad0 5583
55d2375e 5584 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5585
55d2375e
SC		 5586 /* Do nothing if PML buffer is empty */
5587 if (pml_idx == (PML_ENTITY_NUM - 1))
5588 return;
cd232ad0 5589
55d2375e
SC		 5590 /* PML index always points to next available PML buffer entity */
5591 if (pml_idx >= PML_ENTITY_NUM)
5592 pml_idx = 0;
5593 else
5594 pml_idx++;
945679e3 5595
55d2375e
SC		 5596 pml_buf = page_address(vmx->pml_pg);
5597 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5598 u64 gpa;
945679e3 5599
55d2375e
SC		 5600 gpa = pml_buf[pml_idx];
5601 WARN_ON(gpa & (PAGE_SIZE - 1));
5602 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5603 }
5604
55d2375e
SC		 5605 /* reset PML index */
5606 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5607}
5608
f4160e45 5609/*
55d2375e
SC		 5610 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5611 * Called before reporting dirty_bitmap to userspace.
f4160e45 5612 */
55d2375e 5613static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5614{
55d2375e
SC		 5615 int i;
5616 struct kvm_vcpu *vcpu;
49f705c5 5617 /*
55d2375e
SC		 5618 * We only need to kick vcpu out of guest mode here, as PML buffer
5619 * is flushed at beginning of all VMEXITs, and it's obvious that only
5620 * vcpus running in guest are possible to have unflushed GPAs in PML
5621 * buffer.
49f705c5 5622 */
55d2375e
SC		 5623 kvm_for_each_vcpu(i, vcpu, kvm)
5624 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5625}
5626
55d2375e 5627static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5628{
55d2375e
SC		 5629 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5630 name, vmcs_read16(sel),
5631 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5632 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5633 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5634}
5635
55d2375e 5636static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5637{
55d2375e
SC		 5638 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5639 name, vmcs_read32(limit),
5640 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5641}
5642
69090810 5643void dump_vmcs(void)
63846663 5644{
6f2f8453
PB		 5645 u32 vmentry_ctl, vmexit_ctl;
5646 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5647 unsigned long cr4;
5648 u64 efer;
55d2375e 5649 int i, n;
63846663 5650
6f2f8453
PB		 5651 if (!dump_invalid_vmcs) {
5652 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5653 return;
5654 }
5655
5656 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5657 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5658 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5659 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5660 cr4 = vmcs_readl(GUEST_CR4);
5661 efer = vmcs_read64(GUEST_IA32_EFER);
5662 secondary_exec_control = 0;
55d2375e
SC		 5663 if (cpu_has_secondary_exec_ctrls())
5664 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5665
55d2375e
SC		 5666 pr_err("*** Guest State ***\n");
5667 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5668 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5669 vmcs_readl(CR0_GUEST_HOST_MASK));
5670 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5671 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5672 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5673 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5674 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5675 {
5676 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5677 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5678 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5679 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5680 }
55d2375e
SC		 5681 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5682 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5683 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5684 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5685 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5686 vmcs_readl(GUEST_SYSENTER_ESP),
5687 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5688 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5689 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5690 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5691 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5692 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5693 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5694 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5695 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5696 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5697 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5698 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5699 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5700 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5701 efer, vmcs_read64(GUEST_IA32_PAT));
5702 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5703 vmcs_read64(GUEST_IA32_DEBUGCTL),
5704 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5705 if (cpu_has_load_perf_global_ctrl() &&
5706 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5707 pr_err("PerfGlobCtl = 0x%016llx\n",
5708 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5709 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5710 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5711 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5712 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5713 vmcs_read32(GUEST_ACTIVITY_STATE));
5714 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5715 pr_err("InterruptStatus = %04x\n",
5716 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5717
55d2375e
SC		 5718 pr_err("*** Host State ***\n");
5719 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5720 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5721 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5722 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5723 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5724 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5725 vmcs_read16(HOST_TR_SELECTOR));
5726 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5727 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5728 vmcs_readl(HOST_TR_BASE));
5729 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5730 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5731 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5732 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5733 vmcs_readl(HOST_CR4));
5734 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5735 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5736 vmcs_read32(HOST_IA32_SYSENTER_CS),
5737 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5738 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5739 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5740 vmcs_read64(HOST_IA32_EFER),
5741 vmcs_read64(HOST_IA32_PAT));
5742 if (cpu_has_load_perf_global_ctrl() &&
5743 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5744 pr_err("PerfGlobCtl = 0x%016llx\n",
5745 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5746
55d2375e
SC		 5747 pr_err("*** Control State ***\n");
5748 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5749 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5750 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5751 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5752 vmcs_read32(EXCEPTION_BITMAP),
5753 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5754 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5755 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5756 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5757 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5758 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5759 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5760 vmcs_read32(VM_EXIT_INTR_INFO),
5761 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5762 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5763 pr_err(" reason=%08x qualification=%016lx\n",
5764 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5765 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5766 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5767 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5768 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5769 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5770 pr_err("TSC Multiplier = 0x%016llx\n",
5771 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5772 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5773 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5774 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5775 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5776 }
d6a85c32 5777 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9d609649
PB		 5778 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5779 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
d6a85c32 5780 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
9d609649 5781 }
55d2375e
SC		 5782 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5783 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5784 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5785 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5786 n = vmcs_read32(CR3_TARGET_COUNT);
5787 for (i = 0; i + 1 < n; i += 4)
5788 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5789 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5790 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5791 if (i < n)
5792 pr_err("CR3 target%u=%016lx\n",
5793 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5794 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5795 pr_err("PLE Gap=%08x Window=%08x\n",
5796 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5797 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5798 pr_err("Virtual processor ID = 0x%04x\n",
5799 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5800}
5801
55d2375e
SC		 5802/*
5803 * The guest has exited. See if we can fix it or if we need userspace
5804 * assistance.
5805 */
1e9e2622
WL		 5806static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5807 enum exit_fastpath_completion exit_fastpath)
ff651cb6 5808{
55d2375e
SC		 5809 struct vcpu_vmx *vmx = to_vmx(vcpu);
5810 u32 exit_reason = vmx->exit_reason;
5811 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5812
55d2375e 5813 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5814
55d2375e
SC		 5815 /*
5816 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5817 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5818 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5819 * mode as if vcpus is in root mode, the PML buffer must has been
5820 * flushed already.
5821 */
5822 if (enable_pml)
5823 vmx_flush_pml_buffer(vcpu);
1dc35dac 5824
55d2375e
SC		 5825 /* If guest state is invalid, start emulating */
5826 if (vmx->emulation_required)
5827 return handle_invalid_guest_state(vcpu);
1dc35dac 5828
55d2375e
SC		 5829 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5830 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5831
55d2375e
SC		 5832 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5833 dump_vmcs();
5834 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5835 vcpu->run->fail_entry.hardware_entry_failure_reason
5836 = exit_reason;
5837 return 0;
9ed38ffa
LP		 5838 }
5839
55d2375e 5840 if (unlikely(vmx->fail)) {
3b20e03a 5841 dump_vmcs();
55d2375e
SC		 5842 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5843 vcpu->run->fail_entry.hardware_entry_failure_reason
5844 = vmcs_read32(VM_INSTRUCTION_ERROR);
5845 return 0;
5846 }
50c28f21 5847
55d2375e
SC		 5848 /*
5849 * Note:
5850 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5851 * delivery event since it indicates guest is accessing MMIO.
5852 * The vm-exit can be triggered again after return to guest that
5853 * will cause infinite loop.
5854 */
5855 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5856 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5857 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5858 exit_reason != EXIT_REASON_PML_FULL &&
5859 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5860 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5861 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5862 vcpu->run->internal.ndata = 3;
5863 vcpu->run->internal.data[0] = vectoring_info;
5864 vcpu->run->internal.data[1] = exit_reason;
5865 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5866 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5867 vcpu->run->internal.ndata++;
5868 vcpu->run->internal.data[3] =
5869 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5870 }
5871 return 0;
5872 }
50c28f21 5873
55d2375e
SC		 5874 if (unlikely(!enable_vnmi &&
5875 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5876 if (vmx_interrupt_allowed(vcpu)) {
5877 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5878 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5879 vcpu->arch.nmi_pending) {
5880 /*
5881 * This CPU don't support us in finding the end of an
5882 * NMI-blocked window if the guest runs with IRQs
5883 * disabled. So we pull the trigger after 1 s of
5884 * futile waiting, but inform the user about this.
5885 */
5886 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5887 "state on VCPU %d after 1 s timeout\n",
5888 __func__, vcpu->vcpu_id);
5889 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5890 }
5891 }
50c28f21 5892
1e9e2622
WL		 5893 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5894 kvm_skip_emulated_instruction(vcpu);
5895 return 1;
c926f2f7
MP		 5896 }
5897
5898 if (exit_reason >= kvm_vmx_max_exit_handlers)
5899 goto unexpected_vmexit;
4289d272 5900#ifdef CONFIG_RETPOLINE
c926f2f7
MP		 5901 if (exit_reason == EXIT_REASON_MSR_WRITE)
5902 return kvm_emulate_wrmsr(vcpu);
5903 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5904 return handle_preemption_timer(vcpu);
5905 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5906 return handle_interrupt_window(vcpu);
5907 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5908 return handle_external_interrupt(vcpu);
5909 else if (exit_reason == EXIT_REASON_HLT)
5910 return kvm_emulate_halt(vcpu);
5911 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5912 return handle_ept_misconfig(vcpu);
4289d272 5913#endif
c926f2f7
MP		 5914
5915 exit_reason = array_index_nospec(exit_reason,
5916 kvm_vmx_max_exit_handlers);
5917 if (!kvm_vmx_exit_handlers[exit_reason])
5918 goto unexpected_vmexit;
5919
5920 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5921
5922unexpected_vmexit:
5923 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
5924 dump_vmcs();
5925 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5926 vcpu->run->internal.suberror =
7396d337 5927 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
c926f2f7
MP		 5928 vcpu->run->internal.ndata = 1;
5929 vcpu->run->internal.data[0] = exit_reason;
5930 return 0;
9ed38ffa
LP		 5931}
5932
efebf0aa 5933/*
55d2375e
SC		 5934 * Software based L1D cache flush which is used when microcode providing
5935 * the cache control MSR is not loaded.
efebf0aa 5936 *
55d2375e
SC		 5937 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5938 * flush it is required to read in 64 KiB because the replacement algorithm
5939 * is not exactly LRU. This could be sized at runtime via topology
5940 * information but as all relevant affected CPUs have 32KiB L1D cache size
5941 * there is no point in doing so.
efebf0aa 5942 */
55d2375e 5943static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5944{
55d2375e 5945 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5946
5947 /*
55d2375e
SC		 5948 * This code is only executed when the the flush mode is 'cond' or
5949 * 'always'
25a2e4fe 5950 */
55d2375e
SC		 5951 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5952 bool flush_l1d;
25a2e4fe 5953
55d2375e
SC		 5954 /*
5955 * Clear the per-vcpu flush bit, it gets set again
5956 * either from vcpu_run() or from one of the unsafe
5957 * VMEXIT handlers.
5958 */
5959 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5960 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5961
55d2375e
SC		 5962 /*
5963 * Clear the per-cpu flush bit, it gets set again from
5964 * the interrupt handlers.
5965 */
5966 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5967 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 5968
55d2375e
SC		 5969 if (!flush_l1d)
5970 return;
5971 }
09abe320 5972
55d2375e 5973 vcpu->stat.l1d_flush++;
25a2e4fe 5974
55d2375e
SC		 5975 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5976 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5977 return;
5978 }
25a2e4fe 5979
55d2375e
SC		 5980 asm volatile(
5981 /* First ensure the pages are in the TLB */
5982 "xorl %%eax, %%eax\n"
5983 ".Lpopulate_tlb:\n\t"
5984 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5985 "addl $4096, %%eax\n\t"
5986 "cmpl %%eax, %[size]\n\t"
5987 "jne .Lpopulate_tlb\n\t"
5988 "xorl %%eax, %%eax\n\t"
5989 "cpuid\n\t"
5990 /* Now fill the cache */
5991 "xorl %%eax, %%eax\n"
5992 ".Lfill_cache:\n"
5993 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5994 "addl $64, %%eax\n\t"
5995 "cmpl %%eax, %[size]\n\t"
5996 "jne .Lfill_cache\n\t"
5997 "lfence\n"
5998 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5999 [size] "r" (size)
6000 : "eax", "ebx", "ecx", "edx");
09abe320 6001}
25a2e4fe 6002
55d2375e 6003static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 6004{
55d2375e 6005 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
132f4f7e 6006 int tpr_threshold;
09abe320 6007
55d2375e
SC		 6008 if (is_guest_mode(vcpu) &&
6009 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6010 return;
25a2e4fe 6011
132f4f7e 6012 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
02d496cf
LA		 6013 if (is_guest_mode(vcpu))
6014 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6015 else
6016 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
8665c3f9
PB		 6017}
6018
55d2375e 6019void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 6020{
fe7f895d 6021 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6022 u32 sec_exec_control;
8665c3f9 6023
55d2375e
SC		 6024 if (!lapic_in_kernel(vcpu))
6025 return;
9314006d 6026
55d2375e
SC		 6027 if (!flexpriority_enabled &&
6028 !cpu_has_vmx_virtualize_x2apic_mode())
6029 return;
705699a1 6030
55d2375e
SC		 6031 /* Postpone execution until vmcs01 is the current VMCS. */
6032 if (is_guest_mode(vcpu)) {
fe7f895d 6033 vmx->nested.change_vmcs01_virtual_apic_mode = true;
55d2375e 6034 return;
6beb7bd5 6035 }
fe3ef05c 6036
fe7f895d 6037 sec_exec_control = secondary_exec_controls_get(vmx);
55d2375e
SC		 6038 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6039 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 6040
55d2375e
SC		 6041 switch (kvm_get_apic_mode(vcpu)) {
6042 case LAPIC_MODE_INVALID:
6043 WARN_ONCE(true, "Invalid local APIC state");
6044 case LAPIC_MODE_DISABLED:
6045 break;
6046 case LAPIC_MODE_XAPIC:
6047 if (flexpriority_enabled) {
6048 sec_exec_control |=
6049 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6050 vmx_flush_tlb(vcpu, true);
6051 }
6052 break;
6053 case LAPIC_MODE_X2APIC:
6054 if (cpu_has_vmx_virtualize_x2apic_mode())
6055 sec_exec_control |=
6056 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6057 break;
09abe320 6058 }
fe7f895d 6059 secondary_exec_controls_set(vmx, sec_exec_control);
09abe320 6060
55d2375e
SC		 6061 vmx_update_msr_bitmap(vcpu);
6062}
0238ea91 6063
55d2375e
SC		 6064static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6065{
6066 if (!is_guest_mode(vcpu)) {
6067 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6068 vmx_flush_tlb(vcpu, true);
6069 }
6070}
fe3ef05c 6071
55d2375e
SC		 6072static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6073{
6074 u16 status;
6075 u8 old;
32c7acf0 6076
55d2375e
SC		 6077 if (max_isr == -1)
6078 max_isr = 0;
608406e2 6079
55d2375e
SC		 6080 status = vmcs_read16(GUEST_INTR_STATUS);
6081 old = status >> 8;
6082 if (max_isr != old) {
6083 status &= 0xff;
6084 status |= max_isr << 8;
6085 vmcs_write16(GUEST_INTR_STATUS, status);
6086 }
6087}
6beb7bd5 6088
55d2375e
SC		 6089static void vmx_set_rvi(int vector)
6090{
6091 u16 status;
6092 u8 old;
0b665d30 6093
55d2375e
SC		 6094 if (vector == -1)
6095 vector = 0;
fe3ef05c 6096
55d2375e
SC		 6097 status = vmcs_read16(GUEST_INTR_STATUS);
6098 old = (u8)status & 0xff;
6099 if ((u8)vector != old) {
6100 status &= ~0xff;
6101 status |= (u8)vector;
6102 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6103 }
55d2375e 6104}
09abe320 6105
55d2375e
SC		 6106static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6107{
09abe320 6108 /*
55d2375e
SC		 6109 * When running L2, updating RVI is only relevant when
6110 * vmcs12 virtual-interrupt-delivery enabled.
6111 * However, it can be enabled only when L1 also
6112 * intercepts external-interrupts and in that case
6113 * we should not update vmcs02 RVI but instead intercept
6114 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6115 */
55d2375e
SC		 6116 if (!is_guest_mode(vcpu))
6117 vmx_set_rvi(max_irr);
6118}
fe3ef05c 6119
55d2375e
SC		 6120static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6121{
6122 struct vcpu_vmx *vmx = to_vmx(vcpu);
6123 int max_irr;
6124 bool max_irr_updated;
a7c0b07d 6125
55d2375e
SC		 6126 WARN_ON(!vcpu->arch.apicv_active);
6127 if (pi_test_on(&vmx->pi_desc)) {
6128 pi_clear_on(&vmx->pi_desc);
6129 /*
d9ff2744 6130 * IOMMU can write to PID.ON, so the barrier matters even on UP.
55d2375e
SC		 6131 * But on x86 this is just a compiler barrier anyway.
6132 */
6133 smp_mb__after_atomic();
6134 max_irr_updated =
6135 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6136
6137 /*
55d2375e
SC		 6138 * If we are running L2 and L1 has a new pending interrupt
6139 * which can be injected, we should re-evaluate
6140 * what should be done with this new L1 interrupt.
6141 * If L1 intercepts external-interrupts, we should
6142 * exit from L2 to L1. Otherwise, interrupt should be
6143 * delivered directly to L2.
c4ebd629 6144 */
55d2375e
SC		 6145 if (is_guest_mode(vcpu) && max_irr_updated) {
6146 if (nested_exit_on_intr(vcpu))
6147 kvm_vcpu_exiting_guest_mode(vcpu);
6148 else
6149 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6150 }
55d2375e
SC		 6151 } else {
6152 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6153 }
55d2375e
SC		 6154 vmx_hwapic_irr_update(vcpu, max_irr);
6155 return max_irr;
6156}
a7c0b07d 6157
17e433b5
WL		 6158static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6159{
9482ae45
JM		 6160 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6161
6162 return pi_test_on(pi_desc) ||
29881b6e 6163 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
17e433b5
WL		 6164}
6165
55d2375e
SC		 6166static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6167{
6168 if (!kvm_vcpu_apicv_active(vcpu))
6169 return;
25a2e4fe 6170
55d2375e
SC		 6171 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6172 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6173 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6174 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6175}
6176
55d2375e 6177static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6178{
6179 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6180
55d2375e
SC		 6181 pi_clear_on(&vmx->pi_desc);
6182 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6183}
8665c3f9 6184
95b5a48c 6185static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
55d2375e 6186{
beb8d93b 6187 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6188
55d2375e 6189 /* if exit due to PF check for async PF */
beb8d93b 6190 if (is_page_fault(vmx->exit_intr_info))
55d2375e 6191 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 6192
55d2375e 6193 /* Handle machine checks before interrupts are enabled */
beb8d93b 6194 if (is_machine_check(vmx->exit_intr_info))
55d2375e 6195 kvm_machine_check();
fe3ef05c 6196
55d2375e 6197 /* We need to handle NMIs before interrupts are enabled */
beb8d93b 6198 if (is_nmi(vmx->exit_intr_info)) {
55d2375e
SC		 6199 kvm_before_interrupt(&vmx->vcpu);
6200 asm("int $2");
6201 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6202 }
55d2375e 6203}
fe3ef05c 6204
95b5a48c 6205static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
55d2375e 6206{
49def500
SC		 6207 unsigned int vector;
6208 unsigned long entry;
55d2375e 6209#ifdef CONFIG_X86_64
49def500 6210 unsigned long tmp;
55d2375e 6211#endif
49def500
SC		 6212 gate_desc *desc;
6213 u32 intr_info;
fe3ef05c 6214
49def500
SC		 6215 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6216 if (WARN_ONCE(!is_external_intr(intr_info),
6217 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6218 return;
6219
6220 vector = intr_info & INTR_INFO_VECTOR_MASK;
2342080c 6221 desc = (gate_desc *)host_idt_base + vector;
49def500
SC		 6222 entry = gate_offset(desc);
6223
165072b0
SC		 6224 kvm_before_interrupt(vcpu);
6225
49def500 6226 asm volatile(
55d2375e 6227#ifdef CONFIG_X86_64
49def500
SC		 6228 "mov %%" _ASM_SP ", %[sp]\n\t"
6229 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6230 "push $%c[ss]\n\t"
6231 "push %[sp]\n\t"
55d2375e 6232#endif
49def500
SC		 6233 "pushf\n\t"
6234 __ASM_SIZE(push) " $%c[cs]\n\t"
6235 CALL_NOSPEC
6236 :
55d2375e 6237#ifdef CONFIG_X86_64
49def500 6238 [sp]"=&r"(tmp),
55d2375e 6239#endif
49def500
SC		 6240 ASM_CALL_CONSTRAINT
6241 :
6242 THUNK_TARGET(entry),
6243 [ss]"i"(__KERNEL_DS),
6244 [cs]"i"(__KERNEL_CS)
6245 );
165072b0
SC		 6246
6247 kvm_after_interrupt(vcpu);
55d2375e 6248}
95b5a48c
SC		 6249STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6250
1e9e2622
WL		 6251static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6252 enum exit_fastpath_completion *exit_fastpath)
95b5a48c
SC		 6253{
6254 struct vcpu_vmx *vmx = to_vmx(vcpu);
6255
6256 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6257 handle_external_interrupt_irqoff(vcpu);
6258 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6259 handle_exception_nmi_irqoff(vmx);
1e9e2622
WL		 6260 else if (!is_guest_mode(vcpu) &&
6261 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6262 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
95b5a48c 6263}
5a6a9748 6264
55d2375e
SC		 6265static bool vmx_has_emulated_msr(int index)
6266{
6267 switch (index) {
6268 case MSR_IA32_SMBASE:
6269 /*
6270 * We cannot do SMM unless we can run the guest in big
6271 * real mode.
6272 */
6273 return enable_unrestricted_guest || emulate_invalid_guest_state;
95c5c7c7
PB		 6274 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6275 return nested;
55d2375e
SC		 6276 case MSR_AMD64_VIRT_SPEC_CTRL:
6277 /* This is AMD only. */
6278 return false;
6279 default:
6280 return true;
3184a995 6281 }
55d2375e 6282}
2bb8cafe 6283
86f5201d
CP		 6284static bool vmx_pt_supported(void)
6285{
6286 return pt_mode == PT_MODE_HOST_GUEST;
6287}
6288
55d2375e
SC		 6289static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6290{
6291 u32 exit_intr_info;
6292 bool unblock_nmi;
6293 u8 vector;
6294 bool idtv_info_valid;
7ca29de2 6295
55d2375e 6296 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6297
55d2375e
SC		 6298 if (enable_vnmi) {
6299 if (vmx->loaded_vmcs->nmi_known_unmasked)
6300 return;
6301 /*
6302 * Can't use vmx->exit_intr_info since we're not sure what
6303 * the exit reason is.
6304 */
6305 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6306 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6307 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6308 /*
6309 * SDM 3: 27.7.1.2 (September 2008)
6310 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6311 * a guest IRET fault.
6312 * SDM 3: 23.2.2 (September 2008)
6313 * Bit 12 is undefined in any of the following cases:
6314 * If the VM exit sets the valid bit in the IDT-vectoring
6315 * information field.
6316 * If the VM exit is due to a double fault.
6317 */
6318 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6319 vector != DF_VECTOR && !idtv_info_valid)
6320 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6321 GUEST_INTR_STATE_NMI);
6322 else
6323 vmx->loaded_vmcs->nmi_known_unmasked =
6324 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6325 & GUEST_INTR_STATE_NMI);
6326 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6327 vmx->loaded_vmcs->vnmi_blocked_time +=
6328 ktime_to_ns(ktime_sub(ktime_get(),
6329 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6330}
6331
55d2375e
SC		 6332static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6333 u32 idt_vectoring_info,
6334 int instr_len_field,
6335 int error_code_field)
0c7f650e 6336{
55d2375e
SC		 6337 u8 vector;
6338 int type;
6339 bool idtv_info_valid;
0c7f650e 6340
55d2375e 6341 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6342
55d2375e
SC		 6343 vcpu->arch.nmi_injected = false;
6344 kvm_clear_exception_queue(vcpu);
6345 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6346
55d2375e
SC		 6347 if (!idtv_info_valid)
6348 return;
c7c2c709 6349
55d2375e 6350 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6351
55d2375e
SC		 6352 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6353 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6354
55d2375e
SC		 6355 switch (type) {
6356 case INTR_TYPE_NMI_INTR:
6357 vcpu->arch.nmi_injected = true;
6358 /*
6359 * SDM 3: 27.7.1.2 (September 2008)
6360 * Clear bit "block by NMI" before VM entry if a NMI
6361 * delivery faulted.
6362 */
6363 vmx_set_nmi_mask(vcpu, false);
6364 break;
6365 case INTR_TYPE_SOFT_EXCEPTION:
6366 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6367 /* fall through */
6368 case INTR_TYPE_HARD_EXCEPTION:
6369 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6370 u32 err = vmcs_read32(error_code_field);
6371 kvm_requeue_exception_e(vcpu, vector, err);
6372 } else
6373 kvm_requeue_exception(vcpu, vector);
6374 break;
6375 case INTR_TYPE_SOFT_INTR:
6376 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6377 /* fall through */
6378 case INTR_TYPE_EXT_INTR:
6379 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6380 break;
6381 default:
6382 break;
0447378a 6383 }
ca0bde28
JM		 6384}
6385
55d2375e 6386static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6387{
55d2375e
SC		 6388 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6389 VM_EXIT_INSTRUCTION_LEN,
6390 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6391}
6392
55d2375e 6393static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6394{
55d2375e
SC		 6395 __vmx_complete_interrupts(vcpu,
6396 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6397 VM_ENTRY_INSTRUCTION_LEN,
6398 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6399
55d2375e 6400 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6401}
6402
55d2375e 6403static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6404{
55d2375e
SC		 6405 int i, nr_msrs;
6406 struct perf_guest_switch_msr *msrs;
7c177938 6407
55d2375e 6408 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6409
55d2375e
SC		 6410 if (!msrs)
6411 return;
f1b026a3 6412
55d2375e
SC		 6413 for (i = 0; i < nr_msrs; i++)
6414 if (msrs[i].host == msrs[i].guest)
6415 clear_atomic_switch_msr(vmx, msrs[i].msr);
6416 else
6417 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6418 msrs[i].host, false);
ca0bde28 6419}
52017608 6420
6e3ba4ab
TX		 6421static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6422{
6423 u32 host_umwait_control;
6424
6425 if (!vmx_has_waitpkg(vmx))
6426 return;
6427
6428 host_umwait_control = get_umwait_control_msr();
6429
6430 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6431 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6432 vmx->msr_ia32_umwait_control,
6433 host_umwait_control, false);
6434 else
6435 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6436}
6437
55d2375e 6438static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6439{
6440 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6441 u64 tscl;
6442 u32 delta_tsc;
52017608 6443
55d2375e 6444 if (vmx->req_immediate_exit) {
804939ea
SC		 6445 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6446 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6447 } else if (vmx->hv_deadline_tsc != -1) {
55d2375e
SC		 6448 tscl = rdtsc();
6449 if (vmx->hv_deadline_tsc > tscl)
6450 /* set_hv_timer ensures the delta fits in 32-bits */
6451 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6452 cpu_preemption_timer_multi);
6453 else
6454 delta_tsc = 0;
858e25c0 6455
804939ea
SC		 6456 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6457 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6458 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6459 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6460 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
7f7f1ba3 6461 }
858e25c0
JM		 6462}
6463
c09b03eb 6464void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6465{
c09b03eb
SC		 6466 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6467 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6468 vmcs_writel(HOST_RSP, host_rsp);
6469 }
5ad6ece8 6470}
5f3d5799 6471
fc2ba5a2 6472bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6473
6474static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6475{
6476 struct vcpu_vmx *vmx = to_vmx(vcpu);
6477 unsigned long cr3, cr4;
6478
6479 /* Record the guest's net vcpu time for enforced NMI injections. */
6480 if (unlikely(!enable_vnmi &&
6481 vmx->loaded_vmcs->soft_vnmi_blocked))
6482 vmx->loaded_vmcs->entry_time = ktime_get();
6483
6484 /* Don't enter VMX if guest state is invalid, let the exit handler
6485 start emulation until we arrive back to a valid state */
6486 if (vmx->emulation_required)
6487 return;
6488
6489 if (vmx->ple_window_dirty) {
6490 vmx->ple_window_dirty = false;
6491 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6492 }
6493
c9dfd3fb 6494 /*
6495 * We did this in prepare_switch_to_guest, because it needs to
6496 * be within srcu_read_lock.
6497 */
6498 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
5ad6ece8 6499
cb3c1e2f 6500 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
5ad6ece8 6501 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
cb3c1e2f 6502 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
5ad6ece8
SC		 6503 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6504
6505 cr3 = __get_current_cr3_fast();
6506 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6507 vmcs_writel(HOST_CR3, cr3);
6508 vmx->loaded_vmcs->host_state.cr3 = cr3;
6509 }
6510
6511 cr4 = cr4_read_shadow();
6512 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6513 vmcs_writel(HOST_CR4, cr4);
6514 vmx->loaded_vmcs->host_state.cr4 = cr4;
6515 }
6516
6517 /* When single-stepping over STI and MOV SS, we must clear the
6518 * corresponding interruptibility bits in the guest state. Otherwise
6519 * vmentry fails as it then expects bit 14 (BS) in pending debug
6520 * exceptions being set, but that's not correct for the guest debugging
6521 * case. */
6522 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6523 vmx_set_interrupt_shadow(vcpu, 0);
6524
139a12cf 6525 kvm_load_guest_xsave_state(vcpu);
1811d979 6526
5ad6ece8
SC		 6527 if (static_cpu_has(X86_FEATURE_PKU) &&
6528 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6529 vcpu->arch.pkru != vmx->host_pkru)
6530 __write_pkru(vcpu->arch.pkru);
6531
6532 pt_guest_enter(vmx);
6533
6534 atomic_switch_perf_msrs(vmx);
6e3ba4ab 6535 atomic_switch_umwait_control_msr(vmx);
5ad6ece8 6536
804939ea
SC		 6537 if (enable_preemption_timer)
6538 vmx_update_hv_timer(vcpu);
5ad6ece8 6539
b6c4bc65
WL		 6540 if (lapic_in_kernel(vcpu) &&
6541 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6542 kvm_wait_lapic_expire(vcpu);
6543
5ad6ece8
SC		 6544 /*
6545 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6546 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6547 * is no need to worry about the conditional branch over the wrmsr
6548 * being speculatively taken.
6549 */
6550 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6551
fa4bff16 6552 /* L1D Flush includes CPU buffer clear to mitigate MDS */
c823dd5c
SC		 6553 if (static_branch_unlikely(&vmx_l1d_should_flush))
6554 vmx_l1d_flush(vcpu);
fa4bff16
LT		 6555 else if (static_branch_unlikely(&mds_user_clear))
6556 mds_clear_cpu_buffers();
c823dd5c
SC		 6557
6558 if (vcpu->arch.cr2 != read_cr2())
6559 write_cr2(vcpu->arch.cr2);
6560
fc2ba5a2
SC		 6561 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6562 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6563
6564 vcpu->arch.cr2 = read_cr2();
b6b8a145 6565
55d2375e
SC		 6566 /*
6567 * We do not use IBRS in the kernel. If this vCPU has used the
6568 * SPEC_CTRL MSR it may have left it on; save the value and
6569 * turn it off. This is much more efficient than blindly adding
6570 * it to the atomic save/restore list. Especially as the former
6571 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6572 *
6573 * For non-nested case:
6574 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6575 * save it.
6576 *
6577 * For nested case:
6578 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6579 * save it.
6580 */
6581 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6582 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6583
55d2375e 6584 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6585
55d2375e
SC		 6586 /* All fields are clean at this point */
6587 if (static_branch_unlikely(&enable_evmcs))
6588 current_evmcs->hv_clean_fields |=
6589 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6590
6f6a657c
VK		 6591 if (static_branch_unlikely(&enable_evmcs))
6592 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6593
55d2375e
SC		 6594 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6595 if (vmx->host_debugctlmsr)
6596 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6597
55d2375e
SC		 6598#ifndef CONFIG_X86_64
6599 /*
6600 * The sysexit path does not restore ds/es, so we must set them to
6601 * a reasonable value ourselves.
6602 *
6603 * We can't defer this to vmx_prepare_switch_to_host() since that
6604 * function may be executed in interrupt context, which saves and
6605 * restore segments around it, nullifying its effect.
6606 */
6607 loadsegment(ds, __USER_DS);
6608 loadsegment(es, __USER_DS);
6609#endif
4704d0be 6610
55d2375e
SC		 6611 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6612 | (1 << VCPU_EXREG_RFLAGS)
6613 | (1 << VCPU_EXREG_PDPTR)
6614 | (1 << VCPU_EXREG_SEGMENTS)
6615 | (1 << VCPU_EXREG_CR3));
6616 vcpu->arch.regs_dirty = 0;
7854cbca 6617
2ef444f1
CP		 6618 pt_guest_exit(vmx);
6619
3633cfc3 6620 /*
55d2375e
SC		 6621 * eager fpu is enabled if PKEY is supported and CR4 is switched
6622 * back on host, so it is safe to read guest PKRU from current
6623 * XSAVE.
3633cfc3 6624 */
55d2375e
SC		 6625 if (static_cpu_has(X86_FEATURE_PKU) &&
6626 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
c806e887 6627 vcpu->arch.pkru = rdpkru();
55d2375e
SC		 6628 if (vcpu->arch.pkru != vmx->host_pkru)
6629 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6630 }
6631
139a12cf 6632 kvm_load_host_xsave_state(vcpu);
1811d979 6633
55d2375e
SC		 6634 vmx->nested.nested_run_pending = 0;
6635 vmx->idt_vectoring_info = 0;
119a9c01 6636
55d2375e 6637 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
beb8d93b
SC		 6638 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6639 kvm_machine_check();
6640
55d2375e
SC		 6641 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6642 return;
608406e2 6643
55d2375e
SC		 6644 vmx->loaded_vmcs->launched = 1;
6645 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6646
55d2375e
SC		 6647 vmx_recover_nmi_blocking(vmx);
6648 vmx_complete_interrupts(vmx);
6649}
2996fca0 6650
55d2375e
SC		 6651static struct kvm *vmx_vm_alloc(void)
6652{
41836839
BG		 6653 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6654 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6655 PAGE_KERNEL);
55d2375e 6656 return &kvm_vmx->kvm;
cf8b84f4
JM		 6657}
6658
55d2375e
SC		 6659static void vmx_vm_free(struct kvm *kvm)
6660{
6f6a657c 6661 kfree(kvm->arch.hyperv.hv_pa_pg);
55d2375e
SC		 6662 vfree(to_kvm_vmx(kvm));
6663}
6664
6665static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6666{
55d2375e 6667 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6668
55d2375e
SC		 6669 if (enable_pml)
6670 vmx_destroy_pml_buffer(vmx);
6671 free_vpid(vmx->vpid);
55d2375e
SC		 6672 nested_vmx_free_vcpu(vcpu);
6673 free_loaded_vmcs(vmx->loaded_vmcs);
55d2375e 6674}
4704d0be 6675
987b2594 6676static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
55d2375e 6677{
41836839 6678 struct vcpu_vmx *vmx;
55d2375e 6679 unsigned long *msr_bitmap;
34109c04 6680 int i, cpu, err;
4704d0be 6681
a9dd6f09
SC		 6682 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6683 vmx = to_vmx(vcpu);
d9a710e5 6684
55d2375e 6685 err = -ENOMEM;
b666a4b6 6686
55d2375e 6687 vmx->vpid = allocate_vpid();
7cdc2d62 6688
5f3d5799 6689 /*
55d2375e
SC		 6690 * If PML is turned on, failure on enabling PML just results in failure
6691 * of creating the vcpu, therefore we can simplify PML logic (by
6692 * avoiding dealing with cases, such as enabling PML partially on vcpus
67b0ae43 6693 * for the guest), etc.
5f3d5799 6694 */
55d2375e 6695 if (enable_pml) {
41836839 6696 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e 6697 if (!vmx->pml_pg)
987b2594 6698 goto free_vpid;
55d2375e 6699 }
4704d0be 6700
7d73710d 6701 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
4704d0be 6702
4be53410
XL		 6703 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6704 u32 index = vmx_msr_index[i];
6705 u32 data_low, data_high;
6706 int j = vmx->nmsrs;
6707
6708 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6709 continue;
6710 if (wrmsr_safe(index, data_low, data_high) < 0)
6711 continue;
46f4f0aa 6712
4be53410
XL		 6713 vmx->guest_msrs[j].index = i;
6714 vmx->guest_msrs[j].data = 0;
46f4f0aa
PB		 6715 switch (index) {
6716 case MSR_IA32_TSX_CTRL:
6717 /*
6718 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6719 * let's avoid changing CPUID bits under the host
6720 * kernel's feet.
6721 */
6722 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6723 break;
6724 default:
6725 vmx->guest_msrs[j].mask = -1ull;
6726 break;
6727 }
4be53410
XL		 6728 ++vmx->nmsrs;
6729 }
6730
55d2375e
SC		 6731 err = alloc_loaded_vmcs(&vmx->vmcs01);
6732 if (err < 0)
7d73710d 6733 goto free_pml;
cb61de2f 6734
55d2375e 6735 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6736 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6737 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6738 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6739 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6740 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6741 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6742 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
987b2594 6743 if (kvm_cstate_in_guest(vcpu->kvm)) {
b5170063
WL		 6744 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6745 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6746 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6747 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6748 }
55d2375e 6749 vmx->msr_bitmap_mode = 0;
4704d0be 6750
55d2375e
SC		 6751 vmx->loaded_vmcs = &vmx->vmcs01;
6752 cpu = get_cpu();
34109c04
SC		 6753 vmx_vcpu_load(vcpu, cpu);
6754 vcpu->cpu = cpu;
1b84292b 6755 init_vmcs(vmx);
34109c04 6756 vmx_vcpu_put(vcpu);
55d2375e 6757 put_cpu();
34109c04 6758 if (cpu_need_virtualize_apic_accesses(vcpu)) {
987b2594 6759 err = alloc_apic_access_page(vcpu->kvm);
55d2375e
SC		 6760 if (err)
6761 goto free_vmcs;
6762 }
6763
6764 if (enable_ept && !enable_unrestricted_guest) {
987b2594 6765 err = init_rmode_identity_map(vcpu->kvm);
55d2375e
SC		 6766 if (err)
6767 goto free_vmcs;
6768 }
4704d0be 6769
55d2375e
SC		 6770 if (nested)
6771 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
a4443267 6772 vmx_capability.ept);
55d2375e
SC		 6773 else
6774 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6775
55d2375e
SC		 6776 vmx->nested.posted_intr_nv = -1;
6777 vmx->nested.current_vmptr = -1ull;
bd18bffc 6778
bab0c318 6779 vcpu->arch.microcode_version = 0x100000000ULL;
32ad73db 6780 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
feaf0c7d 6781
6f1e03bc 6782 /*
55d2375e
SC		 6783 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6784 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6785 */
55d2375e
SC		 6786 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6787 vmx->pi_desc.sn = 1;
4704d0be 6788
53963a70
LT		 6789 vmx->ept_pointer = INVALID_PAGE;
6790
a9dd6f09 6791 return 0;
4704d0be 6792
55d2375e
SC		 6793free_vmcs:
6794 free_loaded_vmcs(vmx->loaded_vmcs);
55d2375e
SC		 6795free_pml:
6796 vmx_destroy_pml_buffer(vmx);
987b2594 6797free_vpid:
55d2375e 6798 free_vpid(vmx->vpid);
a9dd6f09 6799 return err;
55d2375e 6800}
36be0b9d 6801
65fd4cb6
TG		 6802#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6803#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
21feb4eb 6804
55d2375e
SC		 6805static int vmx_vm_init(struct kvm *kvm)
6806{
6807 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6808
55d2375e
SC		 6809 if (!ple_gap)
6810 kvm->arch.pause_in_guest = true;
3af18d9c 6811
55d2375e
SC		 6812 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6813 switch (l1tf_mitigation) {
6814 case L1TF_MITIGATION_OFF:
6815 case L1TF_MITIGATION_FLUSH_NOWARN:
6816 /* 'I explicitly don't care' is set */
6817 break;
6818 case L1TF_MITIGATION_FLUSH:
6819 case L1TF_MITIGATION_FLUSH_NOSMT:
6820 case L1TF_MITIGATION_FULL:
6821 /*
6822 * Warn upon starting the first VM in a potentially
6823 * insecure environment.
6824 */
b284909a 6825 if (sched_smt_active())
55d2375e
SC		 6826 pr_warn_once(L1TF_MSG_SMT);
6827 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6828 pr_warn_once(L1TF_MSG_L1D);
6829 break;
6830 case L1TF_MITIGATION_FULL_FORCE:
6831 /* Flush is enforced */
6832 break;
6833 }
6834 }
4e19c36f 6835 kvm_apicv_init(kvm, enable_apicv);
55d2375e 6836 return 0;
4704d0be
NHE		 6837}
6838
f257d6dc 6839static int __init vmx_check_processor_compat(void)
bd18bffc 6840{
55d2375e
SC		 6841 struct vmcs_config vmcs_conf;
6842 struct vmx_capability vmx_cap;
bd18bffc 6843
ff10e22e
SC		 6844 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6845 !this_cpu_has(X86_FEATURE_VMX)) {
6846 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6847 return -EIO;
6848 }
6849
55d2375e 6850 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
f257d6dc 6851 return -EIO;
55d2375e 6852 if (nested)
a4443267 6853 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
55d2375e
SC		 6854 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6855 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6856 smp_processor_id());
f257d6dc 6857 return -EIO;
bd18bffc 6858 }
f257d6dc 6859 return 0;
bd18bffc
SC		 6860}
6861
55d2375e 6862static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6863{
55d2375e
SC		 6864 u8 cache;
6865 u64 ipat = 0;
bd18bffc 6866
55d2375e
SC		 6867 /* For VT-d and EPT combination
6868 * 1. MMIO: always map as UC
6869 * 2. EPT with VT-d:
6870 * a. VT-d without snooping control feature: can't guarantee the
6871 * result, try to trust guest.
6872 * b. VT-d with snooping control feature: snooping control feature of
6873 * VT-d engine can guarantee the cache correctness. Just set it
6874 * to WB to keep consistent with host. So the same as item 3.
6875 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6876 * consistent with host MTRR
bd18bffc 6877 */
55d2375e
SC		 6878 if (is_mmio) {
6879 cache = MTRR_TYPE_UNCACHABLE;
6880 goto exit;
6881 }
bd18bffc 6882
55d2375e
SC		 6883 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6884 ipat = VMX_EPT_IPAT_BIT;
6885 cache = MTRR_TYPE_WRBACK;
6886 goto exit;
6887 }
bd18bffc 6888
55d2375e
SC		 6889 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6890 ipat = VMX_EPT_IPAT_BIT;
6891 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6892 cache = MTRR_TYPE_WRBACK;
6893 else
6894 cache = MTRR_TYPE_UNCACHABLE;
6895 goto exit;
6896 }
bd18bffc 6897
55d2375e 6898 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6899
55d2375e
SC		 6900exit:
6901 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6902}
bd18bffc 6903
55d2375e
SC		 6904static int vmx_get_lpage_level(void)
6905{
6906 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6907 return PT_DIRECTORY_LEVEL;
6908 else
6909 /* For shadow and EPT supported 1GB page */
6910 return PT_PDPE_LEVEL;
6911}
bd18bffc 6912
fe7f895d 6913static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
55d2375e 6914{
bd18bffc 6915 /*
55d2375e
SC		 6916 * These bits in the secondary execution controls field
6917 * are dynamic, the others are mostly based on the hypervisor
6918 * architecture and the guest's CPUID. Do not touch the
6919 * dynamic bits.
bd18bffc 6920 */
55d2375e
SC		 6921 u32 mask =
6922 SECONDARY_EXEC_SHADOW_VMCS |
6923 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6924 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6925 SECONDARY_EXEC_DESC;
bd18bffc 6926
fe7f895d
SC		 6927 u32 new_ctl = vmx->secondary_exec_control;
6928 u32 cur_ctl = secondary_exec_controls_get(vmx);
bd18bffc 6929
fe7f895d 6930 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6931}
6932
4704d0be 6933/*
55d2375e
SC		 6934 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6935 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6936 */
55d2375e 6937static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6938{
6939 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6940 struct kvm_cpuid_entry2 *entry;
4704d0be 6941
55d2375e
SC		 6942 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6943 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6944
55d2375e
SC		 6945#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6946 if (entry && (entry->_reg & (_cpuid_mask))) \
6947 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6948} while (0)
ff651cb6 6949
55d2375e 6950 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
87382003
SC		 6951 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
6952 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
6953 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
6954 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
6955 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
6956 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
6957 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
6958 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
6959 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
6960 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
6961 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
6962 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
6963 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
6964 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
61ada748 6965
55d2375e 6966 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
87382003
SC		 6967 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
6968 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
6969 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
6970 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
6971 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
6972 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
cf3215d9 6973
55d2375e
SC		 6974#undef cr4_fixed1_update
6975}
36c3cc42 6976
55d2375e
SC		 6977static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6978{
6979 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 6980
55d2375e
SC		 6981 if (kvm_mpx_supported()) {
6982 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 6983
55d2375e
SC		 6984 if (mpx_enabled) {
6985 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6986 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6987 } else {
6988 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6989 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6990 }
dccbfcf5 6991 }
55d2375e 6992}
4704d0be 6993
6c0f0bba
LK		 6994static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6995{
6996 struct vcpu_vmx *vmx = to_vmx(vcpu);
6997 struct kvm_cpuid_entry2 *best = NULL;
6998 int i;
6999
7000 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7001 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7002 if (!best)
7003 return;
7004 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7005 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7006 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7007 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7008 }
7009
7010 /* Get the number of configurable Address Ranges for filtering */
7011 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7012 PT_CAP_num_address_ranges);
7013
7014 /* Initialize and clear the no dependency bits */
7015 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7016 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7017
7018 /*
7019 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7020 * will inject an #GP
7021 */
7022 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7023 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7024
7025 /*
7026 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7027 * PSBFreq can be set
7028 */
7029 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7030 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7031 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7032
7033 /*
7034 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7035 * MTCFreq can be set
7036 */
7037 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7038 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7039 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7040
7041 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7042 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7043 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7044 RTIT_CTL_PTW_EN);
7045
7046 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7047 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7048 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7049
7050 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7051 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7052 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7053
7054 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7055 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7056 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7057
7058 /* unmask address range configure area */
7059 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 7060 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 7061}
7062
55d2375e
SC		 7063static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7064{
7065 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 7066
7204160e
AL		 7067 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7068 vcpu->arch.xsaves_enabled = false;
7069
55d2375e
SC		 7070 if (cpu_has_secondary_exec_ctrls()) {
7071 vmx_compute_secondary_exec_control(vmx);
fe7f895d 7072 vmcs_set_secondary_exec_control(vmx);
705699a1 7073 }
4704d0be 7074
55d2375e
SC		 7075 if (nested_vmx_allowed(vcpu))
7076 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
32ad73db
SC		 7077 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7078 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
55d2375e
SC		 7079 else
7080 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
32ad73db
SC		 7081 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7082 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
4f350c6d 7083
55d2375e
SC		 7084 if (nested_vmx_allowed(vcpu)) {
7085 nested_vmx_cr_fixed1_bits_update(vcpu);
7086 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 7087 }
6c0f0bba
LK		 7088
7089 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7090 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7091 update_intel_pt_cfg(vcpu);
b07a5c53
PB		 7092
7093 if (boot_cpu_has(X86_FEATURE_RTM)) {
7094 struct shared_msr_entry *msr;
7095 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7096 if (msr) {
7097 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7098 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7099 }
7100 }
55d2375e 7101}
09abb5e3 7102
55d2375e
SC		 7103static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7104{
7105 if (func == 1 && nested)
87382003 7106 entry->ecx |= feature_bit(VMX);
4704d0be
NHE		 7107}
7108
55d2375e 7109static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 7110{
55d2375e 7111 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 7112}
7113
8a76d7f2
JR		 7114static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7115 struct x86_instruction_info *info,
7116 enum x86_intercept_stage stage)
7117{
fb6d4d34
PB		 7118 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7119 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7120
7121 /*
7122 * RDPID causes #UD if disabled through secondary execution controls.
7123 * Because it is marked as EmulateOnUD, we need to intercept it here.
7124 */
7125 if (info->intercept == x86_intercept_rdtscp &&
7126 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7127 ctxt->exception.vector = UD_VECTOR;
7128 ctxt->exception.error_code_valid = false;
7129 return X86EMUL_PROPAGATE_FAULT;
7130 }
7131
7132 /* TODO: check more intercepts... */
8a76d7f2
JR		 7133 return X86EMUL_CONTINUE;
7134}
7135
64672c95
YJ		 7136#ifdef CONFIG_X86_64
7137/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7138static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7139 u64 divisor, u64 *result)
7140{
7141 u64 low = a << shift, high = a >> (64 - shift);
7142
7143 /* To avoid the overflow on divq */
7144 if (high >= divisor)
7145 return 1;
7146
7147 /* Low hold the result, high hold rem which is discarded */
7148 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7149 "rm" (divisor), "0" (low), "1" (high));
7150 *result = low;
7151
7152 return 0;
7153}
7154
f9927982
SC		 7155static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7156 bool *expired)
64672c95 7157{
386c6ddb 7158 struct vcpu_vmx *vmx;
c5ce8235 7159 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
39497d76 7160 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
386c6ddb 7161
0c5f81da
WL		 7162 if (kvm_mwait_in_guest(vcpu->kvm) ||
7163 kvm_can_post_timer_interrupt(vcpu))
386c6ddb
KA		 7164 return -EOPNOTSUPP;
7165
7166 vmx = to_vmx(vcpu);
7167 tscl = rdtsc();
7168 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7169 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
39497d76
SC		 7170 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7171 ktimer->timer_advance_ns);
c5ce8235
WL		 7172
7173 if (delta_tsc > lapic_timer_advance_cycles)
7174 delta_tsc -= lapic_timer_advance_cycles;
7175 else
7176 delta_tsc = 0;
64672c95
YJ		 7177
7178 /* Convert to host delta tsc if tsc scaling is enabled */
7179 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
0967fa1c 7180 delta_tsc && u64_shl_div_u64(delta_tsc,
64672c95 7181 kvm_tsc_scaling_ratio_frac_bits,
0967fa1c 7182 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
64672c95
YJ		 7183 return -ERANGE;
7184
7185 /*
7186 * If the delta tsc can't fit in the 32 bit after the multi shift,
7187 * we can't use the preemption timer.
7188 * It's possible that it fits on later vmentries, but checking
7189 * on every vmentry is costly so we just use an hrtimer.
7190 */
7191 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7192 return -ERANGE;
7193
7194 vmx->hv_deadline_tsc = tscl + delta_tsc;
f9927982
SC		 7195 *expired = !delta_tsc;
7196 return 0;
64672c95
YJ		 7197}
7198
7199static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7200{
f459a707 7201 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7202}
7203#endif
7204
48d89b92 7205static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7206{
b31c114b 7207 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7208 shrink_ple_window(vcpu);
ae97a3b8
RK		 7209}
7210
843e4330
KH		 7211static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7212 struct kvm_memory_slot *slot)
7213{
7214 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7215 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7216}
7217
7218static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7219 struct kvm_memory_slot *slot)
7220{
7221 kvm_mmu_slot_set_dirty(kvm, slot);
7222}
7223
7224static void vmx_flush_log_dirty(struct kvm *kvm)
7225{
7226 kvm_flush_pml_buffers(kvm);
7227}
7228
c5f983f6
BD		 7229static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7230{
7231 struct vmcs12 *vmcs12;
7232 struct vcpu_vmx *vmx = to_vmx(vcpu);
3d5f6beb 7233 gpa_t gpa, dst;
c5f983f6
BD		 7234
7235 if (is_guest_mode(vcpu)) {
7236 WARN_ON_ONCE(vmx->nested.pml_full);
7237
7238 /*
7239 * Check if PML is enabled for the nested guest.
7240 * Whether eptp bit 6 is set is already checked
7241 * as part of A/D emulation.
7242 */
7243 vmcs12 = get_vmcs12(vcpu);
7244 if (!nested_cpu_has_pml(vmcs12))
7245 return 0;
7246
4769886b 7247 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7248 vmx->nested.pml_full = true;
7249 return 1;
7250 }
7251
7252 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
3d5f6beb 7253 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
c5f983f6 7254
3d5f6beb
KA		 7255 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7256 offset_in_page(dst), sizeof(gpa)))
c5f983f6
BD		 7257 return 0;
7258
3d5f6beb 7259 vmcs12->guest_pml_index--;
c5f983f6
BD		 7260 }
7261
7262 return 0;
7263}
7264
843e4330
KH		 7265static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7266 struct kvm_memory_slot *memslot,
7267 gfn_t offset, unsigned long mask)
7268{
7269 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7270}
7271
cd39e117
PB		 7272static void __pi_post_block(struct kvm_vcpu *vcpu)
7273{
7274 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7275 struct pi_desc old, new;
7276 unsigned int dest;
cd39e117
PB		 7277
7278 do {
7279 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7280 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7281 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7282
7283 dest = cpu_physical_id(vcpu->cpu);
7284
7285 if (x2apic_enabled())
7286 new.ndst = dest;
7287 else
7288 new.ndst = (dest << 8) & 0xFF00;
7289
cd39e117
PB		 7290 /* set 'NV' to 'notification vector' */
7291 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7292 } while (cmpxchg64(&pi_desc->control, old.control,
7293 new.control) != old.control);
cd39e117 7294
8b306e2f
PB		 7295 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7296 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7297 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7298 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7299 vcpu->pre_pcpu = -1;
7300 }
7301}
7302
bf9f6ac8
FW		 7303/*
7304 * This routine does the following things for vCPU which is going
7305 * to be blocked if VT-d PI is enabled.
7306 * - Store the vCPU to the wakeup list, so when interrupts happen
7307 * we can find the right vCPU to wake up.
7308 * - Change the Posted-interrupt descriptor as below:
7309 * 'NDST' <-- vcpu->pre_pcpu
7310 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7311 * - If 'ON' is set during this process, which means at least one
7312 * interrupt is posted for this vCPU, we cannot block it, in
7313 * this case, return 1, otherwise, return 0.
7314 *
7315 */
bc22512b 7316static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7317{
bf9f6ac8
FW		 7318 unsigned int dest;
7319 struct pi_desc old, new;
7320 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7321
7322 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7323 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7324 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7325 return 0;
7326
8b306e2f
PB		 7327 WARN_ON(irqs_disabled());
7328 local_irq_disable();
7329 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7330 vcpu->pre_pcpu = vcpu->cpu;
7331 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7332 list_add_tail(&vcpu->blocked_vcpu_list,
7333 &per_cpu(blocked_vcpu_on_cpu,
7334 vcpu->pre_pcpu));
7335 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7336 }
bf9f6ac8
FW		 7337
7338 do {
7339 old.control = new.control = pi_desc->control;
7340
bf9f6ac8
FW		 7341 WARN((pi_desc->sn == 1),
7342 "Warning: SN field of posted-interrupts "
7343 "is set before blocking\n");
7344
7345 /*
7346 * Since vCPU can be preempted during this process,
7347 * vcpu->cpu could be different with pre_pcpu, we
7348 * need to set pre_pcpu as the destination of wakeup
7349 * notification event, then we can find the right vCPU
7350 * to wakeup in wakeup handler if interrupts happen
7351 * when the vCPU is in blocked state.
7352 */
7353 dest = cpu_physical_id(vcpu->pre_pcpu);
7354
7355 if (x2apic_enabled())
7356 new.ndst = dest;
7357 else
7358 new.ndst = (dest << 8) & 0xFF00;
7359
7360 /* set 'NV' to 'wakeup vector' */
7361 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7362 } while (cmpxchg64(&pi_desc->control, old.control,
7363 new.control) != old.control);
bf9f6ac8 7364
8b306e2f
PB		 7365 /* We should not block the vCPU if an interrupt is posted for it. */
7366 if (pi_test_on(pi_desc) == 1)
7367 __pi_post_block(vcpu);
7368
7369 local_irq_enable();
7370 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7371}
7372
bc22512b
YJ		 7373static int vmx_pre_block(struct kvm_vcpu *vcpu)
7374{
7375 if (pi_pre_block(vcpu))
7376 return 1;
7377
64672c95
YJ		 7378 if (kvm_lapic_hv_timer_in_use(vcpu))
7379 kvm_lapic_switch_to_sw_timer(vcpu);
7380
bc22512b
YJ		 7381 return 0;
7382}
7383
7384static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7385{
8b306e2f 7386 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7387 return;
7388
8b306e2f
PB		 7389 WARN_ON(irqs_disabled());
7390 local_irq_disable();
cd39e117 7391 __pi_post_block(vcpu);
8b306e2f 7392 local_irq_enable();
bf9f6ac8
FW		 7393}
7394
bc22512b
YJ		 7395static void vmx_post_block(struct kvm_vcpu *vcpu)
7396{
64672c95
YJ		 7397 if (kvm_x86_ops->set_hv_timer)
7398 kvm_lapic_switch_to_hv_timer(vcpu);
7399
bc22512b
YJ		 7400 pi_post_block(vcpu);
7401}
7402
efc64404
FW		 7403/*
7404 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7405 *
7406 * @kvm: kvm
7407 * @host_irq: host irq of the interrupt
7408 * @guest_irq: gsi of the interrupt
7409 * @set: set or unset PI
7410 * returns 0 on success, < 0 on failure
7411 */
7412static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7413 uint32_t guest_irq, bool set)
7414{
7415 struct kvm_kernel_irq_routing_entry *e;
7416 struct kvm_irq_routing_table *irq_rt;
7417 struct kvm_lapic_irq irq;
7418 struct kvm_vcpu *vcpu;
7419 struct vcpu_data vcpu_info;
3a8b0677 7420 int idx, ret = 0;
efc64404
FW		 7421
7422 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7423 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7424 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7425 return 0;
7426
7427 idx = srcu_read_lock(&kvm->irq_srcu);
7428 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7429 if (guest_irq >= irq_rt->nr_rt_entries ||
7430 hlist_empty(&irq_rt->map[guest_irq])) {
7431 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7432 guest_irq, irq_rt->nr_rt_entries);
7433 goto out;
7434 }
efc64404
FW		 7435
7436 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7437 if (e->type != KVM_IRQ_ROUTING_MSI)
7438 continue;
7439 /*
7440 * VT-d PI cannot support posting multicast/broadcast
7441 * interrupts to a vCPU, we still use interrupt remapping
7442 * for these kind of interrupts.
7443 *
7444 * For lowest-priority interrupts, we only support
7445 * those with single CPU as the destination, e.g. user
7446 * configures the interrupts via /proc/irq or uses
7447 * irqbalance to make the interrupts single-CPU.
7448 *
7449 * We will support full lowest-priority interrupt later.
fdcf7562
AG		 7450 *
7451 * In addition, we can only inject generic interrupts using
7452 * the PI mechanism, refuse to route others through it.
efc64404
FW		 7453 */
7454
37131313 7455 kvm_set_msi_irq(kvm, e, &irq);
fdcf7562
AG		 7456 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7457 !kvm_irq_is_postable(&irq)) {
23a1c257
FW		 7458 /*
7459 * Make sure the IRTE is in remapped mode if
7460 * we don't handle it in posted mode.
7461 */
7462 ret = irq_set_vcpu_affinity(host_irq, NULL);
7463 if (ret < 0) {
7464 printk(KERN_INFO
7465 "failed to back to remapped mode, irq: %u\n",
7466 host_irq);
7467 goto out;
7468 }
7469
efc64404 7470 continue;
23a1c257 7471 }
efc64404
FW		 7472
7473 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7474 vcpu_info.vector = irq.vector;
7475
2698d82e 7476 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7477 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7478
7479 if (set)
7480 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7481 else
efc64404 7482 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7483
7484 if (ret < 0) {
7485 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7486 __func__);
7487 goto out;
7488 }
7489 }
7490
7491 ret = 0;
7492out:
7493 srcu_read_unlock(&kvm->irq_srcu, idx);
7494 return ret;
7495}
7496
c45dcc71
AR		 7497static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7498{
7499 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7500 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
32ad73db 7501 FEAT_CTL_LMCE_ENABLED;
c45dcc71
AR		 7502 else
7503 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
32ad73db 7504 ~FEAT_CTL_LMCE_ENABLED;
c45dcc71
AR		 7505}
7506
72d7b374
LP		 7507static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7508{
72e9cbdb
LP		 7509 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7510 if (to_vmx(vcpu)->nested.nested_run_pending)
7511 return 0;
72d7b374
LP		 7512 return 1;
7513}
7514
0234bf88
LP		 7515static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7516{
72e9cbdb
LP		 7517 struct vcpu_vmx *vmx = to_vmx(vcpu);
7518
7519 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7520 if (vmx->nested.smm.guest_mode)
7521 nested_vmx_vmexit(vcpu, -1, 0, 0);
7522
7523 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7524 vmx->nested.vmxon = false;
caa057a2 7525 vmx_clear_hlt(vcpu);
0234bf88
LP		 7526 return 0;
7527}
7528
ed19321f 7529static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7530{
72e9cbdb
LP		 7531 struct vcpu_vmx *vmx = to_vmx(vcpu);
7532 int ret;
7533
7534 if (vmx->nested.smm.vmxon) {
7535 vmx->nested.vmxon = true;
7536 vmx->nested.smm.vmxon = false;
7537 }
7538
7539 if (vmx->nested.smm.guest_mode) {
a633e41e 7540 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7541 if (ret)
7542 return ret;
7543
7544 vmx->nested.smm.guest_mode = false;
7545 }
0234bf88
LP		 7546 return 0;
7547}
7548
cc3d967f
LP		 7549static int enable_smi_window(struct kvm_vcpu *vcpu)
7550{
7551 return 0;
7552}
7553
05d5a486
SB		 7554static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7555{
9481b7f1 7556 return false;
05d5a486
SB		 7557}
7558
4b9852f4
LA		 7559static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7560{
7561 return to_vmx(vcpu)->nested.vmxon;
7562}
7563
a3203381
SC		 7564static __init int hardware_setup(void)
7565{
7566 unsigned long host_bndcfgs;
2342080c 7567 struct desc_ptr dt;
a3203381
SC		 7568 int r, i;
7569
7570 rdmsrl_safe(MSR_EFER, &host_efer);
7571
2342080c
SC		 7572 store_idt(&dt);
7573 host_idt_base = dt.address;
7574
a3203381
SC		 7575 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7576 kvm_define_shared_msr(i, vmx_msr_index[i]);
7577
7578 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7579 return -EIO;
7580
7581 if (boot_cpu_has(X86_FEATURE_NX))
7582 kvm_enable_efer_bits(EFER_NX);
7583
7584 if (boot_cpu_has(X86_FEATURE_MPX)) {
7585 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7586 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7587 }
7588
a3203381
SC		 7589 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7590 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7591 enable_vpid = 0;
7592
7593 if (!cpu_has_vmx_ept() ||
7594 !cpu_has_vmx_ept_4levels() ||
7595 !cpu_has_vmx_ept_mt_wb() ||
7596 !cpu_has_vmx_invept_global())
7597 enable_ept = 0;
7598
7599 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7600 enable_ept_ad_bits = 0;
7601
7602 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7603 enable_unrestricted_guest = 0;
7604
7605 if (!cpu_has_vmx_flexpriority())
7606 flexpriority_enabled = 0;
7607
7608 if (!cpu_has_virtual_nmis())
7609 enable_vnmi = 0;
7610
7611 /*
7612 * set_apic_access_page_addr() is used to reload apic access
7613 * page upon invalidation. No need to do anything if not
7614 * using the APIC_ACCESS_ADDR VMCS field.
7615 */
7616 if (!flexpriority_enabled)
7617 kvm_x86_ops->set_apic_access_page_addr = NULL;
7618
7619 if (!cpu_has_vmx_tpr_shadow())
7620 kvm_x86_ops->update_cr8_intercept = NULL;
7621
7622 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7623 kvm_disable_largepages();
7624
7625#if IS_ENABLED(CONFIG_HYPERV)
7626 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7627 && enable_ept) {
7628 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7629 kvm_x86_ops->tlb_remote_flush_with_range =
7630 hv_remote_flush_tlb_with_range;
7631 }
a3203381
SC		 7632#endif
7633
7634 if (!cpu_has_vmx_ple()) {
7635 ple_gap = 0;
7636 ple_window = 0;
7637 ple_window_grow = 0;
7638 ple_window_max = 0;
7639 ple_window_shrink = 0;
7640 }
7641
7642 if (!cpu_has_vmx_apicv()) {
7643 enable_apicv = 0;
7644 kvm_x86_ops->sync_pir_to_irr = NULL;
7645 }
7646
7647 if (cpu_has_vmx_tsc_scaling()) {
7648 kvm_has_tsc_control = true;
7649 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7650 kvm_tsc_scaling_ratio_frac_bits = 48;
7651 }
7652
7653 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7654
7655 if (enable_ept)
7656 vmx_enable_tdp();
7657 else
7658 kvm_disable_tdp();
7659
a3203381
SC		 7660 /*
7661 * Only enable PML when hardware supports PML feature, and both EPT
7662 * and EPT A/D bit features are enabled -- PML depends on them to work.
7663 */
7664 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7665 enable_pml = 0;
7666
7667 if (!enable_pml) {
7668 kvm_x86_ops->slot_enable_log_dirty = NULL;
7669 kvm_x86_ops->slot_disable_log_dirty = NULL;
7670 kvm_x86_ops->flush_log_dirty = NULL;
7671 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7672 }
7673
7674 if (!cpu_has_vmx_preemption_timer())
804939ea 7675 enable_preemption_timer = false;
a3203381 7676
804939ea
SC		 7677 if (enable_preemption_timer) {
7678 u64 use_timer_freq = 5000ULL * 1000 * 1000;
a3203381
SC		 7679 u64 vmx_msr;
7680
7681 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7682 cpu_preemption_timer_multi =
7683 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
804939ea
SC		 7684
7685 if (tsc_khz)
7686 use_timer_freq = (u64)tsc_khz * 1000;
7687 use_timer_freq >>= cpu_preemption_timer_multi;
7688
7689 /*
7690 * KVM "disables" the preemption timer by setting it to its max
7691 * value. Don't use the timer if it might cause spurious exits
7692 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7693 */
7694 if (use_timer_freq > 0xffffffffu / 10)
7695 enable_preemption_timer = false;
7696 }
7697
7698 if (!enable_preemption_timer) {
a3203381
SC		 7699 kvm_x86_ops->set_hv_timer = NULL;
7700 kvm_x86_ops->cancel_hv_timer = NULL;
804939ea 7701 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
a3203381
SC		 7702 }
7703
a3203381 7704 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7705
7706 kvm_mce_cap_supported |= MCG_LMCE_P;
7707
f99e3daf
CP		 7708 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7709 return -EINVAL;
7710 if (!enable_ept || !cpu_has_vmx_intel_pt())
7711 pt_mode = PT_MODE_SYSTEM;
7712
a3203381 7713 if (nested) {
3e8eaccc 7714 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
a4443267 7715 vmx_capability.ept);
3e8eaccc 7716
e4027cfa 7717 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7718 if (r)
7719 return r;
7720 }
7721
7722 r = alloc_kvm_area();
7723 if (r)
7724 nested_vmx_hardware_unsetup();
7725 return r;
7726}
7727
7728static __exit void hardware_unsetup(void)
7729{
7730 if (nested)
7731 nested_vmx_hardware_unsetup();
7732
7733 free_kvm_area();
7734}
7735
ef8efd7a
SS		 7736static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7737{
f4fdc0a2
SS		 7738 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7739 BIT(APICV_INHIBIT_REASON_HYPERV);
ef8efd7a
SS		 7740
7741 return supported & BIT(bit);
7742}
7743
404f6aac 7744static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7745 .cpu_has_kvm_support = cpu_has_kvm_support,
7746 .disabled_by_bios = vmx_disabled_by_bios,
7747 .hardware_setup = hardware_setup,
7748 .hardware_unsetup = hardware_unsetup,
002c7f7c 7749 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7750 .hardware_enable = hardware_enable,
7751 .hardware_disable = hardware_disable,
04547156 7752 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7753 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7754
b31c114b 7755 .vm_init = vmx_vm_init,
434a1e94
SC		 7756 .vm_alloc = vmx_vm_alloc,
7757 .vm_free = vmx_vm_free,
b31c114b 7758
6aa8b732
AK		 7759 .vcpu_create = vmx_create_vcpu,
7760 .vcpu_free = vmx_free_vcpu,
04d2cc77 7761 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7762
6d6095bd 7763 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7764 .vcpu_load = vmx_vcpu_load,
7765 .vcpu_put = vmx_vcpu_put,
7766
a96036b8 7767 .update_bp_intercept = update_exception_bitmap,
801e459a 7768 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7769 .get_msr = vmx_get_msr,
7770 .set_msr = vmx_set_msr,
7771 .get_segment_base = vmx_get_segment_base,
7772 .get_segment = vmx_get_segment,
7773 .set_segment = vmx_set_segment,
2e4d2653 7774 .get_cpl = vmx_get_cpl,
6aa8b732 7775 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7776 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 7777 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7778 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7779 .set_cr3 = vmx_set_cr3,
7780 .set_cr4 = vmx_set_cr4,
6aa8b732 7781 .set_efer = vmx_set_efer,
6aa8b732
AK		 7782 .get_idt = vmx_get_idt,
7783 .set_idt = vmx_set_idt,
7784 .get_gdt = vmx_get_gdt,
7785 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7786 .get_dr6 = vmx_get_dr6,
7787 .set_dr6 = vmx_set_dr6,
020df079 7788 .set_dr7 = vmx_set_dr7,
81908bf4 7789 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7790 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7791 .get_rflags = vmx_get_rflags,
7792 .set_rflags = vmx_set_rflags,
be94f6b7 7793
6aa8b732 7794 .tlb_flush = vmx_flush_tlb,
faff8758 7795 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7796
6aa8b732 7797 .run = vmx_vcpu_run,
6062d012 7798 .handle_exit = vmx_handle_exit,
1957aa63 7799 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7800 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7801 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7802 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7803 .set_irq = vmx_inject_irq,
95ba8273 7804 .set_nmi = vmx_inject_nmi,
298101da 7805 .queue_exception = vmx_queue_exception,
b463a6f7 7806 .cancel_injection = vmx_cancel_injection,
78646121 7807 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7808 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7809 .get_nmi_mask = vmx_get_nmi_mask,
7810 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7811 .enable_nmi_window = enable_nmi_window,
7812 .enable_irq_window = enable_irq_window,
7813 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7814 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7815 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb 7816 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7817 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7818 .apicv_post_state_restore = vmx_apicv_post_state_restore,
ef8efd7a 7819 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
c7c9c56c
YZ		 7820 .hwapic_irr_update = vmx_hwapic_irr_update,
7821 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7822 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7823 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7824 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
17e433b5 7825 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
95ba8273 7826
cbc94022 7827 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7828 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7829 .get_tdp_level = get_ept_level,
4b12f0de 7830 .get_mt_mask = vmx_get_mt_mask,
229456fc 7831
586f9607 7832 .get_exit_info = vmx_get_exit_info,
586f9607 7833
17cc3935 7834 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7835
7836 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7837
7838 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7839 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7840
7841 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7842
7843 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7844
e79f245d 7845 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7846 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7847
7848 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7849
7850 .check_intercept = vmx_check_intercept,
95b5a48c 7851 .handle_exit_irqoff = vmx_handle_exit_irqoff,
da8999d3 7852 .mpx_supported = vmx_mpx_supported,
55412b2e 7853 .xsaves_supported = vmx_xsaves_supported,
66336cab 7854 .umip_emulated = vmx_umip_emulated,
86f5201d 7855 .pt_supported = vmx_pt_supported,
a47970ed 7856 .pku_supported = vmx_pku_supported,
b6b8a145 7857
d264ee0c 7858 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7859
7860 .sched_in = vmx_sched_in,
843e4330
KH		 7861
7862 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7863 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7864 .flush_log_dirty = vmx_flush_log_dirty,
7865 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7866 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7867
bf9f6ac8
FW		 7868 .pre_block = vmx_pre_block,
7869 .post_block = vmx_post_block,
7870
25462f7f 7871 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7872
7873 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7874
7875#ifdef CONFIG_X86_64
7876 .set_hv_timer = vmx_set_hv_timer,
7877 .cancel_hv_timer = vmx_cancel_hv_timer,
7878#endif
c45dcc71
AR		 7879
7880 .setup_mce = vmx_setup_mce,
0234bf88 7881
72d7b374 7882 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7883 .pre_enter_smm = vmx_pre_enter_smm,
7884 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7885 .enable_smi_window = enable_smi_window,
57b119da 7886
e4027cfa
SC		 7887 .check_nested_events = NULL,
7888 .get_nested_state = NULL,
7889 .set_nested_state = NULL,
7890 .get_vmcs12_pages = NULL,
7891 .nested_enable_evmcs = NULL,
ea152987 7892 .nested_get_evmcs_version = NULL,
05d5a486 7893 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
4b9852f4 7894 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
6aa8b732
AK		 7895};
7896
72c6d2db 7897static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7898{
7899 if (vmx_l1d_flush_pages) {
7900 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7901 vmx_l1d_flush_pages = NULL;
7902 }
72c6d2db
TG		 7903 /* Restore state so sysfs ignores VMX */
7904 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7905}
7906
a7b9020b
TG		 7907static void vmx_exit(void)
7908{
7909#ifdef CONFIG_KEXEC_CORE
7910 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7911 synchronize_rcu();
7912#endif
7913
7914 kvm_exit();
7915
7916#if IS_ENABLED(CONFIG_HYPERV)
7917 if (static_branch_unlikely(&enable_evmcs)) {
7918 int cpu;
7919 struct hv_vp_assist_page *vp_ap;
7920 /*
7921 * Reset everything to support using non-enlightened VMCS
7922 * access later (e.g. when we reload the module with
7923 * enlightened_vmcs=0)
7924 */
7925 for_each_online_cpu(cpu) {
7926 vp_ap = hv_get_vp_assist_page(cpu);
7927
7928 if (!vp_ap)
7929 continue;
7930
6f6a657c 7931 vp_ap->nested_control.features.directhypercall = 0;
a7b9020b
TG		 7932 vp_ap->current_nested_vmcs = 0;
7933 vp_ap->enlighten_vmentry = 0;
7934 }
7935
7936 static_branch_disable(&enable_evmcs);
7937 }
7938#endif
7939 vmx_cleanup_l1d_flush();
7940}
7941module_exit(vmx_exit);
7942
6aa8b732
AK		 7943static int __init vmx_init(void)
7944{
773e8a04
VK		 7945 int r;
7946
7947#if IS_ENABLED(CONFIG_HYPERV)
7948 /*
7949 * Enlightened VMCS usage should be recommended and the host needs
7950 * to support eVMCS v1 or above. We can also disable eVMCS support
7951 * with module parameter.
7952 */
7953 if (enlightened_vmcs &&
7954 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7955 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7956 KVM_EVMCS_VERSION) {
7957 int cpu;
7958
7959 /* Check that we have assist pages on all online CPUs */
7960 for_each_online_cpu(cpu) {
7961 if (!hv_get_vp_assist_page(cpu)) {
7962 enlightened_vmcs = false;
7963 break;
7964 }
7965 }
7966
7967 if (enlightened_vmcs) {
7968 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7969 static_branch_enable(&enable_evmcs);
7970 }
6f6a657c
VK		 7971
7972 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7973 vmx_x86_ops.enable_direct_tlbflush
7974 = hv_enable_direct_tlbflush;
7975
773e8a04
VK		 7976 } else {
7977 enlightened_vmcs = false;
7978 }
7979#endif
7980
7981 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 7982 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7983 if (r)
34a1cd60 7984 return r;
25c5f225 7985
a7b9020b 7986 /*
7db92e16
TG		 7987 * Must be called after kvm_init() so enable_ept is properly set
7988 * up. Hand the parameter mitigation value in which was stored in
7989 * the pre module init parser. If no parameter was given, it will
7990 * contain 'auto' which will be turned into the default 'cond'
7991 * mitigation mode.
7992 */
19a36d32
WL		 7993 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7994 if (r) {
7995 vmx_exit();
7996 return r;
a47dd5f0 7997 }
25c5f225 7998
2965faa5 7999#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 8000 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8001 crash_vmclear_local_loaded_vmcss);
8002#endif
21ebf53b 8003 vmx_check_vmcs12_offsets();
8f536b76 8004
fdef3ad1 8005 return 0;
6aa8b732 8006}
a7b9020b 8007module_init(vmx_init);
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