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KVM: remove pre_task_link setting in save_state_to_tss16
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
a2fa3e9f
GH		 64struct vmcs {
65 u32 revision_id;
66 u32 abort;
67 char data[0];
68};
69
70struct vcpu_vmx {
fb3f0f51 71 struct kvm_vcpu vcpu;
543e4243 72 struct list_head local_vcpus_link;
313dbd49 73 unsigned long host_rsp;
a2fa3e9f 74 int launched;
29bd8a78 75 u8 fail;
1155f76a 76 u32 idt_vectoring_info;
a2fa3e9f
GH		 77 struct kvm_msr_entry *guest_msrs;
78 struct kvm_msr_entry *host_msrs;
79 int nmsrs;
80 int save_nmsrs;
81 int msr_offset_efer;
82#ifdef CONFIG_X86_64
83 int msr_offset_kernel_gs_base;
84#endif
85 struct vmcs *vmcs;
86 struct {
87 int loaded;
88 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 89 int gs_ldt_reload_needed;
90 int fs_reload_needed;
51c6cf66 91 int guest_efer_loaded;
d77c26fc 92 } host_state;
9c8cba37 93 struct {
7ffd92c5
AK		 94 int vm86_active;
95 u8 save_iopl;
96 struct kvm_save_segment {
97 u16 selector;
98 unsigned long base;
99 u32 limit;
100 u32 ar;
101 } tr, es, ds, fs, gs;
9c8cba37
AK		 102 struct {
103 bool pending;
104 u8 vector;
105 unsigned rip;
106 } irq;
107 } rmode;
2384d2b3 108 int vpid;
04fa4d32 109 bool emulation_required;
3b86cd99
JK		 110
111 /* Support for vnmi-less CPUs */
112 int soft_vnmi_blocked;
113 ktime_t entry_time;
114 s64 vnmi_blocked_time;
a0861c02 115 u32 exit_reason;
a2fa3e9f
GH		 116};
117
118static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
119{
fb3f0f51 120 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 121}
122
b7ebfb05 123static int init_rmode(struct kvm *kvm);
4e1096d2 124static u64 construct_eptp(unsigned long root_hpa);
75880a01 125
6aa8b732
AK		 126static DEFINE_PER_CPU(struct vmcs *, vmxarea);
127static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 128static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 129
3e7c73e9
AK		 130static unsigned long *vmx_io_bitmap_a;
131static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 132static unsigned long *vmx_msr_bitmap_legacy;
133static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 134
2384d2b3
SY		 135static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
136static DEFINE_SPINLOCK(vmx_vpid_lock);
137
1c3d14fe 138static struct vmcs_config {
6aa8b732
AK		 139 int size;
140 int order;
141 u32 revision_id;
1c3d14fe
YS		 142 u32 pin_based_exec_ctrl;
143 u32 cpu_based_exec_ctrl;
f78e0e2e 144 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 145 u32 vmexit_ctrl;
146 u32 vmentry_ctrl;
147} vmcs_config;
6aa8b732 148
efff9e53 149static struct vmx_capability {
d56f546d
SY		 150 u32 ept;
151 u32 vpid;
152} vmx_capability;
153
6aa8b732
AK		 154#define VMX_SEGMENT_FIELD(seg) \
155 [VCPU_SREG_##seg] = { \
156 .selector = GUEST_##seg##_SELECTOR, \
157 .base = GUEST_##seg##_BASE, \
158 .limit = GUEST_##seg##_LIMIT, \
159 .ar_bytes = GUEST_##seg##_AR_BYTES, \
160 }
161
162static struct kvm_vmx_segment_field {
163 unsigned selector;
164 unsigned base;
165 unsigned limit;
166 unsigned ar_bytes;
167} kvm_vmx_segment_fields[] = {
168 VMX_SEGMENT_FIELD(CS),
169 VMX_SEGMENT_FIELD(DS),
170 VMX_SEGMENT_FIELD(ES),
171 VMX_SEGMENT_FIELD(FS),
172 VMX_SEGMENT_FIELD(GS),
173 VMX_SEGMENT_FIELD(SS),
174 VMX_SEGMENT_FIELD(TR),
175 VMX_SEGMENT_FIELD(LDTR),
176};
177
6de4f3ad
AK		 178static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
179
4d56c8a7
AK		 180/*
181 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
182 * away by decrementing the array size.
183 */
6aa8b732 184static const u32 vmx_msr_index[] = {
05b3e0c2 185#ifdef CONFIG_X86_64
6aa8b732
AK		 186 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
187#endif
188 MSR_EFER, MSR_K6_STAR,
189};
9d8f549d 190#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 191
a2fa3e9f
GH		 192static void load_msrs(struct kvm_msr_entry *e, int n)
193{
194 int i;
195
196 for (i = 0; i < n; ++i)
197 wrmsrl(e[i].index, e[i].data);
198}
199
200static void save_msrs(struct kvm_msr_entry *e, int n)
201{
202 int i;
203
204 for (i = 0; i < n; ++i)
205 rdmsrl(e[i].index, e[i].data);
206}
207
6aa8b732
AK		 208static inline int is_page_fault(u32 intr_info)
209{
210 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
211 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 212 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 213}
214
2ab455cc
AL		 215static inline int is_no_device(u32 intr_info)
216{
217 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
218 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 219 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 220}
221
7aa81cc0
AL		 222static inline int is_invalid_opcode(u32 intr_info)
223{
224 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
225 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 226 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 227}
228
6aa8b732
AK		 229static inline int is_external_interrupt(u32 intr_info)
230{
231 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
232 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
233}
234
a0861c02
AK		 235static inline int is_machine_check(u32 intr_info)
236{
237 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
238 INTR_INFO_VALID_MASK)) ==
239 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
240}
241
25c5f225
SY		 242static inline int cpu_has_vmx_msr_bitmap(void)
243{
04547156 244 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 245}
246
6e5d865c
YS		 247static inline int cpu_has_vmx_tpr_shadow(void)
248{
04547156 249 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 250}
251
252static inline int vm_need_tpr_shadow(struct kvm *kvm)
253{
04547156 254 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 255}
256
f78e0e2e
SY		 257static inline int cpu_has_secondary_exec_ctrls(void)
258{
04547156
SY		 259 return vmcs_config.cpu_based_exec_ctrl &
260 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 261}
262
774ead3a 263static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 264{
04547156
SY		 265 return vmcs_config.cpu_based_2nd_exec_ctrl &
266 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
267}
268
269static inline bool cpu_has_vmx_flexpriority(void)
270{
271 return cpu_has_vmx_tpr_shadow() &&
272 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 273}
274
e799794e
MT		 275static inline bool cpu_has_vmx_ept_execute_only(void)
276{
277 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
278}
279
280static inline bool cpu_has_vmx_eptp_uncacheable(void)
281{
282 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
283}
284
285static inline bool cpu_has_vmx_eptp_writeback(void)
286{
287 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
288}
289
290static inline bool cpu_has_vmx_ept_2m_page(void)
291{
292 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
293}
294
d56f546d
SY		 295static inline int cpu_has_vmx_invept_individual_addr(void)
296{
04547156 297 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 298}
299
300static inline int cpu_has_vmx_invept_context(void)
301{
04547156 302 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 303}
304
305static inline int cpu_has_vmx_invept_global(void)
306{
04547156 307 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 308}
309
310static inline int cpu_has_vmx_ept(void)
311{
04547156
SY		 312 return vmcs_config.cpu_based_2nd_exec_ctrl &
313 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 314}
315
3a624e29
NK		 316static inline int cpu_has_vmx_unrestricted_guest(void)
317{
318 return vmcs_config.cpu_based_2nd_exec_ctrl &
319 SECONDARY_EXEC_UNRESTRICTED_GUEST;
320}
321
f78e0e2e
SY		 322static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
323{
04547156
SY		 324 return flexpriority_enabled &&
325 (cpu_has_vmx_virtualize_apic_accesses()) &&
326 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 327}
328
2384d2b3
SY		 329static inline int cpu_has_vmx_vpid(void)
330{
04547156
SY		 331 return vmcs_config.cpu_based_2nd_exec_ctrl &
332 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 333}
334
f08864b4
SY		 335static inline int cpu_has_virtual_nmis(void)
336{
337 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
338}
339
04547156
SY		 340static inline bool report_flexpriority(void)
341{
342 return flexpriority_enabled;
343}
344
8b9cf98c 345static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 346{
347 int i;
348
a2fa3e9f
GH		 349 for (i = 0; i < vmx->nmsrs; ++i)
350 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 351 return i;
352 return -1;
353}
354
2384d2b3
SY		 355static inline void __invvpid(int ext, u16 vpid, gva_t gva)
356{
357 struct {
358 u64 vpid : 16;
359 u64 rsvd : 48;
360 u64 gva;
361 } operand = { vpid, 0, gva };
362
4ecac3fd 363 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 364 /* CF==1 or ZF==1 --> rc = -1 */
365 "; ja 1f ; ud2 ; 1:"
366 : : "a"(&operand), "c"(ext) : "cc", "memory");
367}
368
1439442c
SY		 369static inline void __invept(int ext, u64 eptp, gpa_t gpa)
370{
371 struct {
372 u64 eptp, gpa;
373 } operand = {eptp, gpa};
374
4ecac3fd 375 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 376 /* CF==1 or ZF==1 --> rc = -1 */
377 "; ja 1f ; ud2 ; 1:\n"
378 : : "a" (&operand), "c" (ext) : "cc", "memory");
379}
380
8b9cf98c 381static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 382{
383 int i;
384
8b9cf98c 385 i = __find_msr_index(vmx, msr);
a75beee6 386 if (i >= 0)
a2fa3e9f 387 return &vmx->guest_msrs[i];
8b6d44c7 388 return NULL;
7725f0ba
AK		 389}
390
6aa8b732
AK		 391static void vmcs_clear(struct vmcs *vmcs)
392{
393 u64 phys_addr = __pa(vmcs);
394 u8 error;
395
4ecac3fd 396 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 397 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
398 : "cc", "memory");
399 if (error)
400 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
401 vmcs, phys_addr);
402}
403
404static void __vcpu_clear(void *arg)
405{
8b9cf98c 406 struct vcpu_vmx *vmx = arg;
d3b2c338 407 int cpu = raw_smp_processor_id();
6aa8b732 408
8b9cf98c 409 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 410 vmcs_clear(vmx->vmcs);
411 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 412 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 413 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 414 list_del(&vmx->local_vcpus_link);
415 vmx->vcpu.cpu = -1;
416 vmx->launched = 0;
6aa8b732
AK		 417}
418
8b9cf98c 419static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 420{
eae5ecb5
AK		 421 if (vmx->vcpu.cpu == -1)
422 return;
8691e5a8 423 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 424}
425
2384d2b3
SY		 426static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
427{
428 if (vmx->vpid == 0)
429 return;
430
431 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
432}
433
1439442c
SY		 434static inline void ept_sync_global(void)
435{
436 if (cpu_has_vmx_invept_global())
437 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
438}
439
440static inline void ept_sync_context(u64 eptp)
441{
089d034e 442 if (enable_ept) {
1439442c
SY		 443 if (cpu_has_vmx_invept_context())
444 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
445 else
446 ept_sync_global();
447 }
448}
449
450static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
451{
089d034e 452 if (enable_ept) {
1439442c
SY		 453 if (cpu_has_vmx_invept_individual_addr())
454 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
455 eptp, gpa);
456 else
457 ept_sync_context(eptp);
458 }
459}
460
6aa8b732
AK		 461static unsigned long vmcs_readl(unsigned long field)
462{
463 unsigned long value;
464
4ecac3fd 465 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 466 : "=a"(value) : "d"(field) : "cc");
467 return value;
468}
469
470static u16 vmcs_read16(unsigned long field)
471{
472 return vmcs_readl(field);
473}
474
475static u32 vmcs_read32(unsigned long field)
476{
477 return vmcs_readl(field);
478}
479
480static u64 vmcs_read64(unsigned long field)
481{
05b3e0c2 482#ifdef CONFIG_X86_64
6aa8b732
AK		 483 return vmcs_readl(field);
484#else
485 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
486#endif
487}
488
e52de1b8
AK		 489static noinline void vmwrite_error(unsigned long field, unsigned long value)
490{
491 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
492 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
493 dump_stack();
494}
495
6aa8b732
AK		 496static void vmcs_writel(unsigned long field, unsigned long value)
497{
498 u8 error;
499
4ecac3fd 500 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 501 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 502 if (unlikely(error))
503 vmwrite_error(field, value);
6aa8b732
AK		 504}
505
506static void vmcs_write16(unsigned long field, u16 value)
507{
508 vmcs_writel(field, value);
509}
510
511static void vmcs_write32(unsigned long field, u32 value)
512{
513 vmcs_writel(field, value);
514}
515
516static void vmcs_write64(unsigned long field, u64 value)
517{
6aa8b732 518 vmcs_writel(field, value);
7682f2d0 519#ifndef CONFIG_X86_64
6aa8b732
AK		 520 asm volatile ("");
521 vmcs_writel(field+1, value >> 32);
522#endif
523}
524
2ab455cc
AL		 525static void vmcs_clear_bits(unsigned long field, u32 mask)
526{
527 vmcs_writel(field, vmcs_readl(field) & ~mask);
528}
529
530static void vmcs_set_bits(unsigned long field, u32 mask)
531{
532 vmcs_writel(field, vmcs_readl(field) | mask);
533}
534
abd3f2d6
AK		 535static void update_exception_bitmap(struct kvm_vcpu *vcpu)
536{
537 u32 eb;
538
a0861c02 539 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 540 if (!vcpu->fpu_active)
541 eb |= 1u << NM_VECTOR;
e8a48342
AK		 542 /*
543 * Unconditionally intercept #DB so we can maintain dr6 without
544 * reading it every exit.
545 */
546 eb |= 1u << DB_VECTOR;
d0bfb940 547 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 548 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
549 eb |= 1u << BP_VECTOR;
550 }
7ffd92c5 551 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 552 eb = ~0;
089d034e 553 if (enable_ept)
1439442c 554 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 555 vmcs_write32(EXCEPTION_BITMAP, eb);
556}
557
33ed6329
AK		 558static void reload_tss(void)
559{
33ed6329
AK		 560 /*
561 * VT restores TR but not its size. Useless.
562 */
563 struct descriptor_table gdt;
a5f61300 564 struct desc_struct *descs;
33ed6329 565
d6e88aec 566 kvm_get_gdt(&gdt);
33ed6329
AK		 567 descs = (void *)gdt.base;
568 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
569 load_TR_desc();
33ed6329
AK		 570}
571
8b9cf98c 572static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 573{
a2fa3e9f 574 int efer_offset = vmx->msr_offset_efer;
3a34a881
RK		 575 u64 host_efer;
576 u64 guest_efer;
51c6cf66
AK		 577 u64 ignore_bits;
578
579 if (efer_offset < 0)
580 return;
3a34a881
RK		 581 host_efer = vmx->host_msrs[efer_offset].data;
582 guest_efer = vmx->guest_msrs[efer_offset].data;
583
51c6cf66
AK		 584 /*
585 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
586 * outside long mode
587 */
588 ignore_bits = EFER_NX | EFER_SCE;
589#ifdef CONFIG_X86_64
590 ignore_bits |= EFER_LMA | EFER_LME;
591 /* SCE is meaningful only in long mode on Intel */
592 if (guest_efer & EFER_LMA)
593 ignore_bits &= ~(u64)EFER_SCE;
594#endif
595 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
596 return;
2cc51560 597
51c6cf66
AK		 598 vmx->host_state.guest_efer_loaded = 1;
599 guest_efer &= ~ignore_bits;
600 guest_efer |= host_efer & ignore_bits;
601 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 602 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 603}
604
51c6cf66
AK		 605static void reload_host_efer(struct vcpu_vmx *vmx)
606{
607 if (vmx->host_state.guest_efer_loaded) {
608 vmx->host_state.guest_efer_loaded = 0;
609 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
610 }
611}
612
04d2cc77 613static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 614{
04d2cc77
AK		 615 struct vcpu_vmx *vmx = to_vmx(vcpu);
616
a2fa3e9f 617 if (vmx->host_state.loaded)
33ed6329
AK		 618 return;
619
a2fa3e9f 620 vmx->host_state.loaded = 1;
33ed6329
AK		 621 /*
622 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
623 * allow segment selectors with cpl > 0 or ti == 1.
624 */
d6e88aec 625 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 626 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 627 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 628 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 629 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 630 vmx->host_state.fs_reload_needed = 0;
631 } else {
33ed6329 632 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 633 vmx->host_state.fs_reload_needed = 1;
33ed6329 634 }
d6e88aec 635 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 636 if (!(vmx->host_state.gs_sel & 7))
637 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 638 else {
639 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 640 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 641 }
642
643#ifdef CONFIG_X86_64
644 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
645 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
646#else
a2fa3e9f
GH		 647 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
648 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 649#endif
707c0874
AK		 650
651#ifdef CONFIG_X86_64
d77c26fc 652 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 653 save_msrs(vmx->host_msrs +
654 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 655
707c0874 656#endif
a2fa3e9f 657 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 658 load_transition_efer(vmx);
33ed6329
AK		 659}
660
a9b21b62 661static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 662{
15ad7146 663 unsigned long flags;
33ed6329 664
a2fa3e9f 665 if (!vmx->host_state.loaded)
33ed6329
AK		 666 return;
667
e1beb1d3 668 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 669 vmx->host_state.loaded = 0;
152d3f2f 670 if (vmx->host_state.fs_reload_needed)
d6e88aec 671 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 672 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 673 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 674 /*
675 * If we have to reload gs, we must take care to
676 * preserve our gs base.
677 */
15ad7146 678 local_irq_save(flags);
d6e88aec 679 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 680#ifdef CONFIG_X86_64
681 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
682#endif
15ad7146 683 local_irq_restore(flags);
33ed6329 684 }
152d3f2f 685 reload_tss();
a2fa3e9f
GH		 686 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
687 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 688 reload_host_efer(vmx);
33ed6329
AK		 689}
690
a9b21b62
AK		 691static void vmx_load_host_state(struct vcpu_vmx *vmx)
692{
693 preempt_disable();
694 __vmx_load_host_state(vmx);
695 preempt_enable();
696}
697
6aa8b732
AK		 698/*
699 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
700 * vcpu mutex is already taken.
701 */
15ad7146 702static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 703{
a2fa3e9f
GH		 704 struct vcpu_vmx *vmx = to_vmx(vcpu);
705 u64 phys_addr = __pa(vmx->vmcs);
019960ae 706 u64 tsc_this, delta, new_offset;
6aa8b732 707
a3d7f85f 708 if (vcpu->cpu != cpu) {
8b9cf98c 709 vcpu_clear(vmx);
2f599714 710 kvm_migrate_timers(vcpu);
eb5109e3 711 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 712 local_irq_disable();
713 list_add(&vmx->local_vcpus_link,
714 &per_cpu(vcpus_on_cpu, cpu));
715 local_irq_enable();
a3d7f85f 716 }
6aa8b732 717
a2fa3e9f 718 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 719 u8 error;
720
a2fa3e9f 721 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 722 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 723 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
724 : "cc");
725 if (error)
726 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 727 vmx->vmcs, phys_addr);
6aa8b732
AK		 728 }
729
730 if (vcpu->cpu != cpu) {
731 struct descriptor_table dt;
732 unsigned long sysenter_esp;
733
734 vcpu->cpu = cpu;
735 /*
736 * Linux uses per-cpu TSS and GDT, so set these when switching
737 * processors.
738 */
d6e88aec
AK		 739 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
740 kvm_get_gdt(&dt);
6aa8b732
AK		 741 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
742
743 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
744 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 745
746 /*
747 * Make sure the time stamp counter is monotonous.
748 */
749 rdtscll(tsc_this);
019960ae
AK		 750 if (tsc_this < vcpu->arch.host_tsc) {
751 delta = vcpu->arch.host_tsc - tsc_this;
752 new_offset = vmcs_read64(TSC_OFFSET) + delta;
753 vmcs_write64(TSC_OFFSET, new_offset);
754 }
6aa8b732 755 }
6aa8b732
AK		 756}
757
758static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
759{
a9b21b62 760 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 761}
762
5fd86fcf
AK		 763static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
764{
765 if (vcpu->fpu_active)
766 return;
767 vcpu->fpu_active = 1;
707d92fa 768 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 769 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 770 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 771 update_exception_bitmap(vcpu);
772}
773
774static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
775{
776 if (!vcpu->fpu_active)
777 return;
778 vcpu->fpu_active = 0;
707d92fa 779 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 780 update_exception_bitmap(vcpu);
781}
782
6aa8b732
AK		 783static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
784{
345dcaa8
AK		 785 unsigned long rflags;
786
787 rflags = vmcs_readl(GUEST_RFLAGS);
788 if (to_vmx(vcpu)->rmode.vm86_active)
789 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
790 return rflags;
6aa8b732
AK		 791}
792
793static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
794{
7ffd92c5 795 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 796 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 797 vmcs_writel(GUEST_RFLAGS, rflags);
798}
799
2809f5d2
GC		 800static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
801{
802 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
803 int ret = 0;
804
805 if (interruptibility & GUEST_INTR_STATE_STI)
806 ret |= X86_SHADOW_INT_STI;
807 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
808 ret |= X86_SHADOW_INT_MOV_SS;
809
810 return ret & mask;
811}
812
813static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
814{
815 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
816 u32 interruptibility = interruptibility_old;
817
818 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
819
820 if (mask & X86_SHADOW_INT_MOV_SS)
821 interruptibility |= GUEST_INTR_STATE_MOV_SS;
822 if (mask & X86_SHADOW_INT_STI)
823 interruptibility |= GUEST_INTR_STATE_STI;
824
825 if ((interruptibility != interruptibility_old))
826 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
827}
828
6aa8b732
AK		 829static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
830{
831 unsigned long rip;
6aa8b732 832
5fdbf976 833 rip = kvm_rip_read(vcpu);
6aa8b732 834 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 835 kvm_rip_write(vcpu, rip);
6aa8b732 836
2809f5d2
GC		 837 /* skipping an emulated instruction also counts */
838 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 839}
840
298101da
AK		 841static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
842 bool has_error_code, u32 error_code)
843{
77ab6db0 844 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 845 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 846
8ab2d2e2 847 if (has_error_code) {
77ab6db0 848 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 849 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
850 }
77ab6db0 851
7ffd92c5 852 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 853 vmx->rmode.irq.pending = true;
854 vmx->rmode.irq.vector = nr;
855 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 856 if (kvm_exception_is_soft(nr))
857 vmx->rmode.irq.rip +=
858 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 859 intr_info |= INTR_TYPE_SOFT_INTR;
860 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 861 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
862 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
863 return;
864 }
865
66fd3f7f
GN		 866 if (kvm_exception_is_soft(nr)) {
867 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
868 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 869 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
870 } else
871 intr_info |= INTR_TYPE_HARD_EXCEPTION;
872
873 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 874}
875
a75beee6
ED		 876/*
877 * Swap MSR entry in host/guest MSR entry array.
878 */
54e11fa1 879#ifdef CONFIG_X86_64
8b9cf98c 880static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 881{
a2fa3e9f
GH		 882 struct kvm_msr_entry tmp;
883
884 tmp = vmx->guest_msrs[to];
885 vmx->guest_msrs[to] = vmx->guest_msrs[from];
886 vmx->guest_msrs[from] = tmp;
887 tmp = vmx->host_msrs[to];
888 vmx->host_msrs[to] = vmx->host_msrs[from];
889 vmx->host_msrs[from] = tmp;
a75beee6 890}
54e11fa1 891#endif
a75beee6 892
e38aea3e
AK		 893/*
894 * Set up the vmcs to automatically save and restore system
895 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
896 * mode, as fiddling with msrs is very expensive.
897 */
8b9cf98c 898static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 899{
2cc51560 900 int save_nmsrs;
5897297b 901 unsigned long *msr_bitmap;
e38aea3e 902
33f9c505 903 vmx_load_host_state(vmx);
a75beee6
ED		 904 save_nmsrs = 0;
905#ifdef CONFIG_X86_64
8b9cf98c 906 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 907 int index;
908
8b9cf98c 909 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 910 if (index >= 0)
8b9cf98c
RR		 911 move_msr_up(vmx, index, save_nmsrs++);
912 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 913 if (index >= 0)
8b9cf98c
RR		 914 move_msr_up(vmx, index, save_nmsrs++);
915 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 916 if (index >= 0)
8b9cf98c
RR		 917 move_msr_up(vmx, index, save_nmsrs++);
918 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 919 if (index >= 0)
8b9cf98c 920 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 921 /*
922 * MSR_K6_STAR is only needed on long mode guests, and only
923 * if efer.sce is enabled.
924 */
8b9cf98c 925 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 926 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 927 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 928 }
929#endif
a2fa3e9f 930 vmx->save_nmsrs = save_nmsrs;
e38aea3e 931
4d56c8a7 932#ifdef CONFIG_X86_64
a2fa3e9f 933 vmx->msr_offset_kernel_gs_base =
8b9cf98c 934 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 935#endif
8b9cf98c 936 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
5897297b
AK		 937
938 if (cpu_has_vmx_msr_bitmap()) {
939 if (is_long_mode(&vmx->vcpu))
940 msr_bitmap = vmx_msr_bitmap_longmode;
941 else
942 msr_bitmap = vmx_msr_bitmap_legacy;
943
944 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
945 }
e38aea3e
AK		 946}
947
6aa8b732
AK		 948/*
949 * reads and returns guest's timestamp counter "register"
950 * guest_tsc = host_tsc + tsc_offset -- 21.3
951 */
952static u64 guest_read_tsc(void)
953{
954 u64 host_tsc, tsc_offset;
955
956 rdtscll(host_tsc);
957 tsc_offset = vmcs_read64(TSC_OFFSET);
958 return host_tsc + tsc_offset;
959}
960
961/*
962 * writes 'guest_tsc' into guest's timestamp counter "register"
963 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
964 */
53f658b3 965static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 966{
6aa8b732
AK		 967 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
968}
969
6aa8b732
AK		 970/*
971 * Reads an msr value (of 'msr_index') into 'pdata'.
972 * Returns 0 on success, non-0 otherwise.
973 * Assumes vcpu_load() was already called.
974 */
975static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
976{
977 u64 data;
a2fa3e9f 978 struct kvm_msr_entry *msr;
6aa8b732
AK		 979
980 if (!pdata) {
981 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
982 return -EINVAL;
983 }
984
985 switch (msr_index) {
05b3e0c2 986#ifdef CONFIG_X86_64
6aa8b732
AK		 987 case MSR_FS_BASE:
988 data = vmcs_readl(GUEST_FS_BASE);
989 break;
990 case MSR_GS_BASE:
991 data = vmcs_readl(GUEST_GS_BASE);
992 break;
993 case MSR_EFER:
3bab1f5d 994 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732 995#endif
af24a4e4 996 case MSR_IA32_TSC:
6aa8b732
AK		 997 data = guest_read_tsc();
998 break;
999 case MSR_IA32_SYSENTER_CS:
1000 data = vmcs_read32(GUEST_SYSENTER_CS);
1001 break;
1002 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1003 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1004 break;
1005 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1006 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1007 break;
6aa8b732 1008 default:
8b9cf98c 1009 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1010 if (msr) {
542423b0 1011 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1012 data = msr->data;
1013 break;
6aa8b732 1014 }
3bab1f5d 1015 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1016 }
1017
1018 *pdata = data;
1019 return 0;
1020}
1021
1022/*
1023 * Writes msr value into into the appropriate "register".
1024 * Returns 0 on success, non-0 otherwise.
1025 * Assumes vcpu_load() was already called.
1026 */
1027static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1028{
a2fa3e9f
GH		 1029 struct vcpu_vmx *vmx = to_vmx(vcpu);
1030 struct kvm_msr_entry *msr;
53f658b3 1031 u64 host_tsc;
2cc51560
ED		 1032 int ret = 0;
1033
6aa8b732 1034 switch (msr_index) {
3bab1f5d 1035 case MSR_EFER:
a9b21b62 1036 vmx_load_host_state(vmx);
2cc51560 1037 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1038 break;
16175a79 1039#ifdef CONFIG_X86_64
6aa8b732
AK		 1040 case MSR_FS_BASE:
1041 vmcs_writel(GUEST_FS_BASE, data);
1042 break;
1043 case MSR_GS_BASE:
1044 vmcs_writel(GUEST_GS_BASE, data);
1045 break;
1046#endif
1047 case MSR_IA32_SYSENTER_CS:
1048 vmcs_write32(GUEST_SYSENTER_CS, data);
1049 break;
1050 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1051 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1052 break;
1053 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1054 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1055 break;
af24a4e4 1056 case MSR_IA32_TSC:
53f658b3
MT		 1057 rdtscll(host_tsc);
1058 guest_write_tsc(data, host_tsc);
6aa8b732 1059 break;
468d472f
SY		 1060 case MSR_IA32_CR_PAT:
1061 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1062 vmcs_write64(GUEST_IA32_PAT, data);
1063 vcpu->arch.pat = data;
1064 break;
1065 }
1066 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1067 default:
8b9cf98c 1068 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1069 if (msr) {
542423b0 1070 vmx_load_host_state(vmx);
3bab1f5d
AK		 1071 msr->data = data;
1072 break;
6aa8b732 1073 }
2cc51560 1074 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1075 }
1076
2cc51560 1077 return ret;
6aa8b732
AK		 1078}
1079
5fdbf976 1080static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1081{
5fdbf976
MT		 1082 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1083 switch (reg) {
1084 case VCPU_REGS_RSP:
1085 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1086 break;
1087 case VCPU_REGS_RIP:
1088 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1089 break;
6de4f3ad
AK		 1090 case VCPU_EXREG_PDPTR:
1091 if (enable_ept)
1092 ept_save_pdptrs(vcpu);
1093 break;
5fdbf976
MT		 1094 default:
1095 break;
1096 }
6aa8b732
AK		 1097}
1098
d0bfb940 1099static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1100{
d0bfb940
JK		 1101 int old_debug = vcpu->guest_debug;
1102 unsigned long flags;
6aa8b732 1103
d0bfb940
JK		 1104 vcpu->guest_debug = dbg->control;
1105 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1106 vcpu->guest_debug = 0;
6aa8b732 1107
ae675ef0
JK		 1108 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1109 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1110 else
1111 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1112
d0bfb940
JK		 1113 flags = vmcs_readl(GUEST_RFLAGS);
1114 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1115 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1116 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1117 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1118 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1119
abd3f2d6 1120 update_exception_bitmap(vcpu);
6aa8b732
AK		 1121
1122 return 0;
1123}
1124
1125static __init int cpu_has_kvm_support(void)
1126{
6210e37b 1127 return cpu_has_vmx();
6aa8b732
AK		 1128}
1129
1130static __init int vmx_disabled_by_bios(void)
1131{
1132 u64 msr;
1133
1134 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1135 return (msr & (FEATURE_CONTROL_LOCKED |
1136 FEATURE_CONTROL_VMXON_ENABLED))
1137 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1138 /* locked but not enabled */
6aa8b732
AK		 1139}
1140
10474ae8 1141static int hardware_enable(void *garbage)
6aa8b732
AK		 1142{
1143 int cpu = raw_smp_processor_id();
1144 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1145 u64 old;
1146
10474ae8
AG		 1147 if (read_cr4() & X86_CR4_VMXE)
1148 return -EBUSY;
1149
543e4243 1150 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1151 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1152 if ((old & (FEATURE_CONTROL_LOCKED |
1153 FEATURE_CONTROL_VMXON_ENABLED))
1154 != (FEATURE_CONTROL_LOCKED |
1155 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1156 /* enable and lock */
62b3ffb8 1157 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1158 FEATURE_CONTROL_LOCKED |
1159 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1160 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1161 asm volatile (ASM_VMX_VMXON_RAX
1162 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1163 : "memory", "cc");
10474ae8
AG		 1164
1165 ept_sync_global();
1166
1167 return 0;
6aa8b732
AK		 1168}
1169
543e4243
AK		 1170static void vmclear_local_vcpus(void)
1171{
1172 int cpu = raw_smp_processor_id();
1173 struct vcpu_vmx *vmx, *n;
1174
1175 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1176 local_vcpus_link)
1177 __vcpu_clear(vmx);
1178}
1179
710ff4a8
EH		 1180
1181/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1182 * tricks.
1183 */
1184static void kvm_cpu_vmxoff(void)
6aa8b732 1185{
4ecac3fd 1186 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1187 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1188}
1189
710ff4a8
EH		 1190static void hardware_disable(void *garbage)
1191{
1192 vmclear_local_vcpus();
1193 kvm_cpu_vmxoff();
1194}
1195
1c3d14fe 1196static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1197 u32 msr, u32 *result)
1c3d14fe
YS		 1198{
1199 u32 vmx_msr_low, vmx_msr_high;
1200 u32 ctl = ctl_min | ctl_opt;
1201
1202 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1203
1204 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1205 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1206
1207 /* Ensure minimum (required) set of control bits are supported. */
1208 if (ctl_min & ~ctl)
002c7f7c 1209 return -EIO;
1c3d14fe
YS		 1210
1211 *result = ctl;
1212 return 0;
1213}
1214
002c7f7c 1215static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1216{
1217 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1218 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1219 u32 _pin_based_exec_control = 0;
1220 u32 _cpu_based_exec_control = 0;
f78e0e2e 1221 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1222 u32 _vmexit_control = 0;
1223 u32 _vmentry_control = 0;
1224
1225 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1226 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1227 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1228 &_pin_based_exec_control) < 0)
002c7f7c 1229 return -EIO;
1c3d14fe
YS		 1230
1231 min = CPU_BASED_HLT_EXITING |
1232#ifdef CONFIG_X86_64
1233 CPU_BASED_CR8_LOAD_EXITING |
1234 CPU_BASED_CR8_STORE_EXITING |
1235#endif
d56f546d
SY		 1236 CPU_BASED_CR3_LOAD_EXITING |
1237 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1238 CPU_BASED_USE_IO_BITMAPS |
1239 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1240 CPU_BASED_USE_TSC_OFFSETING |
1241 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1242 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1243 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1244 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1245 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1246 &_cpu_based_exec_control) < 0)
002c7f7c 1247 return -EIO;
6e5d865c
YS		 1248#ifdef CONFIG_X86_64
1249 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1250 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1251 ~CPU_BASED_CR8_STORE_EXITING;
1252#endif
f78e0e2e 1253 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1254 min2 = 0;
1255 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1256 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1257 SECONDARY_EXEC_ENABLE_VPID |
3a624e29
NK		 1258 SECONDARY_EXEC_ENABLE_EPT |
1259 SECONDARY_EXEC_UNRESTRICTED_GUEST;
d56f546d
SY		 1260 if (adjust_vmx_controls(min2, opt2,
1261 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1262 &_cpu_based_2nd_exec_control) < 0)
1263 return -EIO;
1264 }
1265#ifndef CONFIG_X86_64
1266 if (!(_cpu_based_2nd_exec_control &
1267 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1268 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1269#endif
d56f546d 1270 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1271 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1272 enabled */
5fff7d27
GN		 1273 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1274 CPU_BASED_CR3_STORE_EXITING |
1275 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1276 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1277 vmx_capability.ept, vmx_capability.vpid);
1278 }
1c3d14fe
YS		 1279
1280 min = 0;
1281#ifdef CONFIG_X86_64
1282 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1283#endif
468d472f 1284 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1285 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1286 &_vmexit_control) < 0)
002c7f7c 1287 return -EIO;
1c3d14fe 1288
468d472f
SY		 1289 min = 0;
1290 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1291 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1292 &_vmentry_control) < 0)
002c7f7c 1293 return -EIO;
6aa8b732 1294
c68876fd 1295 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1296
1297 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1298 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1299 return -EIO;
1c3d14fe
YS		 1300
1301#ifdef CONFIG_X86_64
1302 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1303 if (vmx_msr_high & (1u<<16))
002c7f7c 1304 return -EIO;
1c3d14fe
YS		 1305#endif
1306
1307 /* Require Write-Back (WB) memory type for VMCS accesses. */
1308 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1309 return -EIO;
1c3d14fe 1310
002c7f7c
YS		 1311 vmcs_conf->size = vmx_msr_high & 0x1fff;
1312 vmcs_conf->order = get_order(vmcs_config.size);
1313 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1314
002c7f7c
YS		 1315 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1316 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1317 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1318 vmcs_conf->vmexit_ctrl = _vmexit_control;
1319 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1320
1321 return 0;
c68876fd 1322}
6aa8b732
AK		 1323
1324static struct vmcs *alloc_vmcs_cpu(int cpu)
1325{
1326 int node = cpu_to_node(cpu);
1327 struct page *pages;
1328 struct vmcs *vmcs;
1329
6484eb3e 1330 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1331 if (!pages)
1332 return NULL;
1333 vmcs = page_address(pages);
1c3d14fe
YS		 1334 memset(vmcs, 0, vmcs_config.size);
1335 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1336 return vmcs;
1337}
1338
1339static struct vmcs *alloc_vmcs(void)
1340{
d3b2c338 1341 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1342}
1343
1344static void free_vmcs(struct vmcs *vmcs)
1345{
1c3d14fe 1346 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1347}
1348
39959588 1349static void free_kvm_area(void)
6aa8b732
AK		 1350{
1351 int cpu;
1352
3230bb47 1353 for_each_possible_cpu(cpu) {
6aa8b732 1354 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1355 per_cpu(vmxarea, cpu) = NULL;
1356 }
6aa8b732
AK		 1357}
1358
6aa8b732
AK		 1359static __init int alloc_kvm_area(void)
1360{
1361 int cpu;
1362
3230bb47 1363 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1364 struct vmcs *vmcs;
1365
1366 vmcs = alloc_vmcs_cpu(cpu);
1367 if (!vmcs) {
1368 free_kvm_area();
1369 return -ENOMEM;
1370 }
1371
1372 per_cpu(vmxarea, cpu) = vmcs;
1373 }
1374 return 0;
1375}
1376
1377static __init int hardware_setup(void)
1378{
002c7f7c
YS		 1379 if (setup_vmcs_config(&vmcs_config) < 0)
1380 return -EIO;
50a37eb4
JR		 1381
1382 if (boot_cpu_has(X86_FEATURE_NX))
1383 kvm_enable_efer_bits(EFER_NX);
1384
93ba03c2
SY		 1385 if (!cpu_has_vmx_vpid())
1386 enable_vpid = 0;
1387
3a624e29 1388 if (!cpu_has_vmx_ept()) {
93ba03c2 1389 enable_ept = 0;
3a624e29
NK		 1390 enable_unrestricted_guest = 0;
1391 }
1392
1393 if (!cpu_has_vmx_unrestricted_guest())
1394 enable_unrestricted_guest = 0;
93ba03c2
SY		 1395
1396 if (!cpu_has_vmx_flexpriority())
1397 flexpriority_enabled = 0;
1398
95ba8273
GN		 1399 if (!cpu_has_vmx_tpr_shadow())
1400 kvm_x86_ops->update_cr8_intercept = NULL;
1401
54dee993
MT		 1402 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1403 kvm_disable_largepages();
1404
6aa8b732
AK		 1405 return alloc_kvm_area();
1406}
1407
1408static __exit void hardware_unsetup(void)
1409{
1410 free_kvm_area();
1411}
1412
6aa8b732
AK		 1413static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1414{
1415 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1416
6af11b9e 1417 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1418 vmcs_write16(sf->selector, save->selector);
1419 vmcs_writel(sf->base, save->base);
1420 vmcs_write32(sf->limit, save->limit);
1421 vmcs_write32(sf->ar_bytes, save->ar);
1422 } else {
1423 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1424 << AR_DPL_SHIFT;
1425 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1426 }
1427}
1428
1429static void enter_pmode(struct kvm_vcpu *vcpu)
1430{
1431 unsigned long flags;
a89a8fb9 1432 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1433
a89a8fb9 1434 vmx->emulation_required = 1;
7ffd92c5 1435 vmx->rmode.vm86_active = 0;
6aa8b732 1436
7ffd92c5
AK		 1437 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1438 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1439 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1440
1441 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1442 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1443 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1444 vmcs_writel(GUEST_RFLAGS, flags);
1445
66aee91a
RR		 1446 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1447 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1448
1449 update_exception_bitmap(vcpu);
1450
a89a8fb9
MG		 1451 if (emulate_invalid_guest_state)
1452 return;
1453
7ffd92c5
AK		 1454 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1455 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1456 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1457 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1458
1459 vmcs_write16(GUEST_SS_SELECTOR, 0);
1460 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1461
1462 vmcs_write16(GUEST_CS_SELECTOR,
1463 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1464 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1465}
1466
d77c26fc 1467static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1468{
bfc6d222 1469 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1470 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1471 kvm->memslots[0].npages - 3;
1472 return base_gfn << PAGE_SHIFT;
1473 }
bfc6d222 1474 return kvm->arch.tss_addr;
6aa8b732
AK		 1475}
1476
1477static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1478{
1479 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1480
1481 save->selector = vmcs_read16(sf->selector);
1482 save->base = vmcs_readl(sf->base);
1483 save->limit = vmcs_read32(sf->limit);
1484 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1485 vmcs_write16(sf->selector, save->base >> 4);
1486 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1487 vmcs_write32(sf->limit, 0xffff);
1488 vmcs_write32(sf->ar_bytes, 0xf3);
1489}
1490
1491static void enter_rmode(struct kvm_vcpu *vcpu)
1492{
1493 unsigned long flags;
a89a8fb9 1494 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1495
3a624e29
NK		 1496 if (enable_unrestricted_guest)
1497 return;
1498
a89a8fb9 1499 vmx->emulation_required = 1;
7ffd92c5 1500 vmx->rmode.vm86_active = 1;
6aa8b732 1501
7ffd92c5 1502 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1503 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1504
7ffd92c5 1505 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1506 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1507
7ffd92c5 1508 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1509 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1510
1511 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1512 vmx->rmode.save_iopl
ad312c7c 1513 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1514
053de044 1515 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1516
1517 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1518 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1519 update_exception_bitmap(vcpu);
1520
a89a8fb9
MG		 1521 if (emulate_invalid_guest_state)
1522 goto continue_rmode;
1523
6aa8b732
AK		 1524 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1525 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1526 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1527
1528 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1529 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1530 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1531 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1532 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1533
7ffd92c5
AK		 1534 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1535 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1536 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1537 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1538
a89a8fb9 1539continue_rmode:
8668a3c4 1540 kvm_mmu_reset_context(vcpu);
b7ebfb05 1541 init_rmode(vcpu->kvm);
6aa8b732
AK		 1542}
1543
401d10de
AS		 1544static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1545{
1546 struct vcpu_vmx *vmx = to_vmx(vcpu);
1547 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1548
1549 vcpu->arch.shadow_efer = efer;
1550 if (!msr)
1551 return;
1552 if (efer & EFER_LMA) {
1553 vmcs_write32(VM_ENTRY_CONTROLS,
1554 vmcs_read32(VM_ENTRY_CONTROLS) |
1555 VM_ENTRY_IA32E_MODE);
1556 msr->data = efer;
1557 } else {
1558 vmcs_write32(VM_ENTRY_CONTROLS,
1559 vmcs_read32(VM_ENTRY_CONTROLS) &
1560 ~VM_ENTRY_IA32E_MODE);
1561
1562 msr->data = efer & ~EFER_LME;
1563 }
1564 setup_msrs(vmx);
1565}
1566
05b3e0c2 1567#ifdef CONFIG_X86_64
6aa8b732
AK		 1568
1569static void enter_lmode(struct kvm_vcpu *vcpu)
1570{
1571 u32 guest_tr_ar;
1572
1573 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1574 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1575 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1576 __func__);
6aa8b732
AK		 1577 vmcs_write32(GUEST_TR_AR_BYTES,
1578 (guest_tr_ar & ~AR_TYPE_MASK)
1579 | AR_TYPE_BUSY_64_TSS);
1580 }
ad312c7c 1581 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1582 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1583}
1584
1585static void exit_lmode(struct kvm_vcpu *vcpu)
1586{
ad312c7c 1587 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1588
1589 vmcs_write32(VM_ENTRY_CONTROLS,
1590 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1591 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1592}
1593
1594#endif
1595
2384d2b3
SY		 1596static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1597{
1598 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1599 if (enable_ept)
4e1096d2 1600 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1601}
1602
25c4c276 1603static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1604{
ad312c7c
ZX		 1605 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1606 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1607}
1608
1439442c
SY		 1609static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1610{
6de4f3ad
AK		 1611 if (!test_bit(VCPU_EXREG_PDPTR,
1612 (unsigned long *)&vcpu->arch.regs_dirty))
1613 return;
1614
1439442c 1615 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1616 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1617 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1618 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1619 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1620 }
1621}
1622
8f5d549f
AK		 1623static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1624{
1625 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1626 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1627 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1628 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1629 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1630 }
6de4f3ad
AK		 1631
1632 __set_bit(VCPU_EXREG_PDPTR,
1633 (unsigned long *)&vcpu->arch.regs_avail);
1634 __set_bit(VCPU_EXREG_PDPTR,
1635 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1636}
1637
1439442c
SY		 1638static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1639
1640static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1641 unsigned long cr0,
1642 struct kvm_vcpu *vcpu)
1643{
1644 if (!(cr0 & X86_CR0_PG)) {
1645 /* From paging/starting to nonpaging */
1646 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1647 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1648 (CPU_BASED_CR3_LOAD_EXITING |
1649 CPU_BASED_CR3_STORE_EXITING));
1650 vcpu->arch.cr0 = cr0;
1651 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c
SY		 1652 } else if (!is_paging(vcpu)) {
1653 /* From nonpaging to paging */
1654 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1655 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1656 ~(CPU_BASED_CR3_LOAD_EXITING |
1657 CPU_BASED_CR3_STORE_EXITING));
1658 vcpu->arch.cr0 = cr0;
1659 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c 1660 }
95eb84a7
SY		 1661
1662 if (!(cr0 & X86_CR0_WP))
1663 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1664}
1665
1666static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1667 struct kvm_vcpu *vcpu)
1668{
1669 if (!is_paging(vcpu)) {
1670 *hw_cr4 &= ~X86_CR4_PAE;
1671 *hw_cr4 |= X86_CR4_PSE;
1672 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1673 *hw_cr4 &= ~X86_CR4_PAE;
1674}
1675
6aa8b732
AK		 1676static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1677{
7ffd92c5 1678 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1679 unsigned long hw_cr0;
1680
1681 if (enable_unrestricted_guest)
1682 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1683 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1684 else
1685 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1686
5fd86fcf
AK		 1687 vmx_fpu_deactivate(vcpu);
1688
7ffd92c5 1689 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1690 enter_pmode(vcpu);
1691
7ffd92c5 1692 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1693 enter_rmode(vcpu);
1694
05b3e0c2 1695#ifdef CONFIG_X86_64
ad312c7c 1696 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1697 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1698 enter_lmode(vcpu);
707d92fa 1699 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1700 exit_lmode(vcpu);
1701 }
1702#endif
1703
089d034e 1704 if (enable_ept)
1439442c
SY		 1705 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1706
6aa8b732 1707 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1708 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1709 vcpu->arch.cr0 = cr0;
5fd86fcf 1710
707d92fa 1711 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1712 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1713}
1714
1439442c
SY		 1715static u64 construct_eptp(unsigned long root_hpa)
1716{
1717 u64 eptp;
1718
1719 /* TODO write the value reading from MSR */
1720 eptp = VMX_EPT_DEFAULT_MT |
1721 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1722 eptp |= (root_hpa & PAGE_MASK);
1723
1724 return eptp;
1725}
1726
6aa8b732
AK		 1727static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1728{
1439442c
SY		 1729 unsigned long guest_cr3;
1730 u64 eptp;
1731
1732 guest_cr3 = cr3;
089d034e 1733 if (enable_ept) {
1439442c
SY		 1734 eptp = construct_eptp(cr3);
1735 vmcs_write64(EPT_POINTER, eptp);
1439442c 1736 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1737 vcpu->kvm->arch.ept_identity_map_addr;
1439442c
SY		 1738 }
1739
2384d2b3 1740 vmx_flush_tlb(vcpu);
1439442c 1741 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1742 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1743 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1744}
1745
1746static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1747{
7ffd92c5 1748 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1749 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1750
ad312c7c 1751 vcpu->arch.cr4 = cr4;
089d034e 1752 if (enable_ept)
1439442c
SY		 1753 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1754
1755 vmcs_writel(CR4_READ_SHADOW, cr4);
1756 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1757}
1758
6aa8b732
AK		 1759static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1760{
1761 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1762
1763 return vmcs_readl(sf->base);
1764}
1765
1766static void vmx_get_segment(struct kvm_vcpu *vcpu,
1767 struct kvm_segment *var, int seg)
1768{
1769 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1770 u32 ar;
1771
1772 var->base = vmcs_readl(sf->base);
1773 var->limit = vmcs_read32(sf->limit);
1774 var->selector = vmcs_read16(sf->selector);
1775 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1776 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1777 ar = 0;
1778 var->type = ar & 15;
1779 var->s = (ar >> 4) & 1;
1780 var->dpl = (ar >> 5) & 3;
1781 var->present = (ar >> 7) & 1;
1782 var->avl = (ar >> 12) & 1;
1783 var->l = (ar >> 13) & 1;
1784 var->db = (ar >> 14) & 1;
1785 var->g = (ar >> 15) & 1;
1786 var->unusable = (ar >> 16) & 1;
1787}
1788
2e4d2653
IE		 1789static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1790{
2e4d2653
IE		 1791 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1792 return 0;
1793
1794 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1795 return 3;
1796
eab4b8aa 1797 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1798}
1799
653e3108 1800static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1801{
6aa8b732
AK		 1802 u32 ar;
1803
653e3108 1804 if (var->unusable)
6aa8b732
AK		 1805 ar = 1 << 16;
1806 else {
1807 ar = var->type & 15;
1808 ar |= (var->s & 1) << 4;
1809 ar |= (var->dpl & 3) << 5;
1810 ar |= (var->present & 1) << 7;
1811 ar |= (var->avl & 1) << 12;
1812 ar |= (var->l & 1) << 13;
1813 ar |= (var->db & 1) << 14;
1814 ar |= (var->g & 1) << 15;
1815 }
f7fbf1fd
UL		 1816 if (ar == 0) /* a 0 value means unusable */
1817 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1818
1819 return ar;
1820}
1821
1822static void vmx_set_segment(struct kvm_vcpu *vcpu,
1823 struct kvm_segment *var, int seg)
1824{
7ffd92c5 1825 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1826 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1827 u32 ar;
1828
7ffd92c5
AK		 1829 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1830 vmx->rmode.tr.selector = var->selector;
1831 vmx->rmode.tr.base = var->base;
1832 vmx->rmode.tr.limit = var->limit;
1833 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1834 return;
1835 }
1836 vmcs_writel(sf->base, var->base);
1837 vmcs_write32(sf->limit, var->limit);
1838 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1839 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1840 /*
1841 * Hack real-mode segments into vm86 compatibility.
1842 */
1843 if (var->base == 0xffff0000 && var->selector == 0xf000)
1844 vmcs_writel(sf->base, 0xf0000);
1845 ar = 0xf3;
1846 } else
1847 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1848
1849 /*
1850 * Fix the "Accessed" bit in AR field of segment registers for older
1851 * qemu binaries.
1852 * IA32 arch specifies that at the time of processor reset the
1853 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1854 * is setting it to 0 in the usedland code. This causes invalid guest
1855 * state vmexit when "unrestricted guest" mode is turned on.
1856 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1857 * tree. Newer qemu binaries with that qemu fix would not need this
1858 * kvm hack.
1859 */
1860 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1861 ar |= 0x1; /* Accessed */
1862
6aa8b732
AK		 1863 vmcs_write32(sf->ar_bytes, ar);
1864}
1865
6aa8b732
AK		 1866static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1867{
1868 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1869
1870 *db = (ar >> 14) & 1;
1871 *l = (ar >> 13) & 1;
1872}
1873
1874static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1875{
1876 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1877 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1878}
1879
1880static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1881{
1882 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1883 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1884}
1885
1886static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1887{
1888 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1889 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1890}
1891
1892static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1893{
1894 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1895 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1896}
1897
648dfaa7
MG		 1898static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1899{
1900 struct kvm_segment var;
1901 u32 ar;
1902
1903 vmx_get_segment(vcpu, &var, seg);
1904 ar = vmx_segment_access_rights(&var);
1905
1906 if (var.base != (var.selector << 4))
1907 return false;
1908 if (var.limit != 0xffff)
1909 return false;
1910 if (ar != 0xf3)
1911 return false;
1912
1913 return true;
1914}
1915
1916static bool code_segment_valid(struct kvm_vcpu *vcpu)
1917{
1918 struct kvm_segment cs;
1919 unsigned int cs_rpl;
1920
1921 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1922 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1923
1872a3f4
AK		 1924 if (cs.unusable)
1925 return false;
648dfaa7
MG		 1926 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1927 return false;
1928 if (!cs.s)
1929 return false;
1872a3f4 1930 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1931 if (cs.dpl > cs_rpl)
1932 return false;
1872a3f4 1933 } else {
648dfaa7
MG		 1934 if (cs.dpl != cs_rpl)
1935 return false;
1936 }
1937 if (!cs.present)
1938 return false;
1939
1940 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1941 return true;
1942}
1943
1944static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1945{
1946 struct kvm_segment ss;
1947 unsigned int ss_rpl;
1948
1949 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1950 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1951
1872a3f4
AK		 1952 if (ss.unusable)
1953 return true;
1954 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1955 return false;
1956 if (!ss.s)
1957 return false;
1958 if (ss.dpl != ss_rpl) /* DPL != RPL */
1959 return false;
1960 if (!ss.present)
1961 return false;
1962
1963 return true;
1964}
1965
1966static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1967{
1968 struct kvm_segment var;
1969 unsigned int rpl;
1970
1971 vmx_get_segment(vcpu, &var, seg);
1972 rpl = var.selector & SELECTOR_RPL_MASK;
1973
1872a3f4
AK		 1974 if (var.unusable)
1975 return true;
648dfaa7
MG		 1976 if (!var.s)
1977 return false;
1978 if (!var.present)
1979 return false;
1980 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1981 if (var.dpl < rpl) /* DPL < RPL */
1982 return false;
1983 }
1984
1985 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1986 * rights flags
1987 */
1988 return true;
1989}
1990
1991static bool tr_valid(struct kvm_vcpu *vcpu)
1992{
1993 struct kvm_segment tr;
1994
1995 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1996
1872a3f4
AK		 1997 if (tr.unusable)
1998 return false;
648dfaa7
MG		 1999 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2000 return false;
1872a3f4 2001 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2002 return false;
2003 if (!tr.present)
2004 return false;
2005
2006 return true;
2007}
2008
2009static bool ldtr_valid(struct kvm_vcpu *vcpu)
2010{
2011 struct kvm_segment ldtr;
2012
2013 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2014
1872a3f4
AK		 2015 if (ldtr.unusable)
2016 return true;
648dfaa7
MG		 2017 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2018 return false;
2019 if (ldtr.type != 2)
2020 return false;
2021 if (!ldtr.present)
2022 return false;
2023
2024 return true;
2025}
2026
2027static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2028{
2029 struct kvm_segment cs, ss;
2030
2031 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2032 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2033
2034 return ((cs.selector & SELECTOR_RPL_MASK) ==
2035 (ss.selector & SELECTOR_RPL_MASK));
2036}
2037
2038/*
2039 * Check if guest state is valid. Returns true if valid, false if
2040 * not.
2041 * We assume that registers are always usable
2042 */
2043static bool guest_state_valid(struct kvm_vcpu *vcpu)
2044{
2045 /* real mode guest state checks */
2046 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2047 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2048 return false;
2049 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2050 return false;
2051 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2052 return false;
2053 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2054 return false;
2055 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2056 return false;
2057 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2058 return false;
2059 } else {
2060 /* protected mode guest state checks */
2061 if (!cs_ss_rpl_check(vcpu))
2062 return false;
2063 if (!code_segment_valid(vcpu))
2064 return false;
2065 if (!stack_segment_valid(vcpu))
2066 return false;
2067 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2068 return false;
2069 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2070 return false;
2071 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2072 return false;
2073 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2074 return false;
2075 if (!tr_valid(vcpu))
2076 return false;
2077 if (!ldtr_valid(vcpu))
2078 return false;
2079 }
2080 /* TODO:
2081 * - Add checks on RIP
2082 * - Add checks on RFLAGS
2083 */
2084
2085 return true;
2086}
2087
d77c26fc 2088static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2089{
6aa8b732 2090 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2091 u16 data = 0;
10589a46 2092 int ret = 0;
195aefde 2093 int r;
6aa8b732 2094
195aefde
IE		 2095 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2096 if (r < 0)
10589a46 2097 goto out;
195aefde 2098 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2099 r = kvm_write_guest_page(kvm, fn++, &data,
2100 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2101 if (r < 0)
10589a46 2102 goto out;
195aefde
IE		 2103 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2104 if (r < 0)
10589a46 2105 goto out;
195aefde
IE		 2106 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2107 if (r < 0)
10589a46 2108 goto out;
195aefde 2109 data = ~0;
10589a46
MT		 2110 r = kvm_write_guest_page(kvm, fn, &data,
2111 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2112 sizeof(u8));
195aefde 2113 if (r < 0)
10589a46
MT		 2114 goto out;
2115
2116 ret = 1;
2117out:
10589a46 2118 return ret;
6aa8b732
AK		 2119}
2120
b7ebfb05
SY		 2121static int init_rmode_identity_map(struct kvm *kvm)
2122{
2123 int i, r, ret;
2124 pfn_t identity_map_pfn;
2125 u32 tmp;
2126
089d034e 2127 if (!enable_ept)
b7ebfb05
SY		 2128 return 1;
2129 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2130 printk(KERN_ERR "EPT: identity-mapping pagetable "
2131 "haven't been allocated!\n");
2132 return 0;
2133 }
2134 if (likely(kvm->arch.ept_identity_pagetable_done))
2135 return 1;
2136 ret = 0;
b927a3ce 2137 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2138 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2139 if (r < 0)
2140 goto out;
2141 /* Set up identity-mapping pagetable for EPT in real mode */
2142 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2143 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2144 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2145 r = kvm_write_guest_page(kvm, identity_map_pfn,
2146 &tmp, i * sizeof(tmp), sizeof(tmp));
2147 if (r < 0)
2148 goto out;
2149 }
2150 kvm->arch.ept_identity_pagetable_done = true;
2151 ret = 1;
2152out:
2153 return ret;
2154}
2155
6aa8b732
AK		 2156static void seg_setup(int seg)
2157{
2158 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2159 unsigned int ar;
6aa8b732
AK		 2160
2161 vmcs_write16(sf->selector, 0);
2162 vmcs_writel(sf->base, 0);
2163 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2164 if (enable_unrestricted_guest) {
2165 ar = 0x93;
2166 if (seg == VCPU_SREG_CS)
2167 ar |= 0x08; /* code segment */
2168 } else
2169 ar = 0xf3;
2170
2171 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2172}
2173
f78e0e2e
SY		 2174static int alloc_apic_access_page(struct kvm *kvm)
2175{
2176 struct kvm_userspace_memory_region kvm_userspace_mem;
2177 int r = 0;
2178
72dc67a6 2179 down_write(&kvm->slots_lock);
bfc6d222 2180 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2181 goto out;
2182 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2183 kvm_userspace_mem.flags = 0;
2184 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2185 kvm_userspace_mem.memory_size = PAGE_SIZE;
2186 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2187 if (r)
2188 goto out;
72dc67a6 2189
bfc6d222 2190 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2191out:
72dc67a6 2192 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2193 return r;
2194}
2195
b7ebfb05
SY		 2196static int alloc_identity_pagetable(struct kvm *kvm)
2197{
2198 struct kvm_userspace_memory_region kvm_userspace_mem;
2199 int r = 0;
2200
2201 down_write(&kvm->slots_lock);
2202 if (kvm->arch.ept_identity_pagetable)
2203 goto out;
2204 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2205 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2206 kvm_userspace_mem.guest_phys_addr =
2207 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2208 kvm_userspace_mem.memory_size = PAGE_SIZE;
2209 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2210 if (r)
2211 goto out;
2212
b7ebfb05 2213 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2214 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2215out:
2216 up_write(&kvm->slots_lock);
2217 return r;
2218}
2219
2384d2b3
SY		 2220static void allocate_vpid(struct vcpu_vmx *vmx)
2221{
2222 int vpid;
2223
2224 vmx->vpid = 0;
919818ab 2225 if (!enable_vpid)
2384d2b3
SY		 2226 return;
2227 spin_lock(&vmx_vpid_lock);
2228 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2229 if (vpid < VMX_NR_VPIDS) {
2230 vmx->vpid = vpid;
2231 __set_bit(vpid, vmx_vpid_bitmap);
2232 }
2233 spin_unlock(&vmx_vpid_lock);
2234}
2235
5897297b 2236static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2237{
3e7c73e9 2238 int f = sizeof(unsigned long);
25c5f225
SY		 2239
2240 if (!cpu_has_vmx_msr_bitmap())
2241 return;
2242
2243 /*
2244 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2245 * have the write-low and read-high bitmap offsets the wrong way round.
2246 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2247 */
25c5f225 2248 if (msr <= 0x1fff) {
3e7c73e9
AK		 2249 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2250 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2251 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2252 msr &= 0x1fff;
3e7c73e9
AK		 2253 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2254 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2255 }
25c5f225
SY		 2256}
2257
5897297b
AK		 2258static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2259{
2260 if (!longmode_only)
2261 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2262 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2263}
2264
6aa8b732
AK		 2265/*
2266 * Sets up the vmcs for emulated real mode.
2267 */
8b9cf98c 2268static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2269{
468d472f 2270 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2271 u32 junk;
53f658b3 2272 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2273 unsigned long a;
2274 struct descriptor_table dt;
2275 int i;
cd2276a7 2276 unsigned long kvm_vmx_return;
6e5d865c 2277 u32 exec_control;
6aa8b732 2278
6aa8b732 2279 /* I/O */
3e7c73e9
AK		 2280 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2281 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2282
25c5f225 2283 if (cpu_has_vmx_msr_bitmap())
5897297b 2284 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2285
6aa8b732
AK		 2286 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2287
6aa8b732 2288 /* Control */
1c3d14fe
YS		 2289 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2290 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2291
2292 exec_control = vmcs_config.cpu_based_exec_ctrl;
2293 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2294 exec_control &= ~CPU_BASED_TPR_SHADOW;
2295#ifdef CONFIG_X86_64
2296 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2297 CPU_BASED_CR8_LOAD_EXITING;
2298#endif
2299 }
089d034e 2300 if (!enable_ept)
d56f546d 2301 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2302 CPU_BASED_CR3_LOAD_EXITING |
2303 CPU_BASED_INVLPG_EXITING;
6e5d865c 2304 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2305
83ff3b9d
SY		 2306 if (cpu_has_secondary_exec_ctrls()) {
2307 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2308 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2309 exec_control &=
2310 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2311 if (vmx->vpid == 0)
2312 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
089d034e 2313 if (!enable_ept)
d56f546d 2314 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3a624e29
NK		 2315 if (!enable_unrestricted_guest)
2316 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
83ff3b9d
SY		 2317 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2318 }
f78e0e2e 2319
c7addb90
AK		 2320 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2321 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2322 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2323
2324 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2325 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2326 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2327
2328 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2329 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2330 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2331 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2332 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2333 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2334#ifdef CONFIG_X86_64
6aa8b732
AK		 2335 rdmsrl(MSR_FS_BASE, a);
2336 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2337 rdmsrl(MSR_GS_BASE, a);
2338 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2339#else
2340 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2341 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2342#endif
2343
2344 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2345
d6e88aec 2346 kvm_get_idt(&dt);
6aa8b732
AK		 2347 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2348
d77c26fc 2349 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2350 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2351 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2352 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2353 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2354
2355 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2356 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2357 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2358 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2359 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2360 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2361
468d472f
SY		 2362 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2363 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2364 host_pat = msr_low | ((u64) msr_high << 32);
2365 vmcs_write64(HOST_IA32_PAT, host_pat);
2366 }
2367 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2368 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2369 host_pat = msr_low | ((u64) msr_high << 32);
2370 /* Write the default value follow host pat */
2371 vmcs_write64(GUEST_IA32_PAT, host_pat);
2372 /* Keep arch.pat sync with GUEST_IA32_PAT */
2373 vmx->vcpu.arch.pat = host_pat;
2374 }
2375
6aa8b732
AK		 2376 for (i = 0; i < NR_VMX_MSR; ++i) {
2377 u32 index = vmx_msr_index[i];
2378 u32 data_low, data_high;
2379 u64 data;
a2fa3e9f 2380 int j = vmx->nmsrs;
6aa8b732
AK		 2381
2382 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2383 continue;
432bd6cb
AK		 2384 if (wrmsr_safe(index, data_low, data_high) < 0)
2385 continue;
6aa8b732 2386 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2387 vmx->host_msrs[j].index = index;
2388 vmx->host_msrs[j].reserved = 0;
2389 vmx->host_msrs[j].data = data;
2390 vmx->guest_msrs[j] = vmx->host_msrs[j];
2391 ++vmx->nmsrs;
6aa8b732 2392 }
6aa8b732 2393
1c3d14fe 2394 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2395
2396 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2397 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2398
e00c8cf2
AK		 2399 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2400 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2401
53f658b3
MT		 2402 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2403 rdtscll(tsc_this);
2404 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2405 tsc_base = tsc_this;
2406
2407 guest_write_tsc(0, tsc_base);
f78e0e2e 2408
e00c8cf2
AK		 2409 return 0;
2410}
2411
b7ebfb05
SY		 2412static int init_rmode(struct kvm *kvm)
2413{
2414 if (!init_rmode_tss(kvm))
2415 return 0;
2416 if (!init_rmode_identity_map(kvm))
2417 return 0;
2418 return 1;
2419}
2420
e00c8cf2
AK		 2421static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2422{
2423 struct vcpu_vmx *vmx = to_vmx(vcpu);
2424 u64 msr;
2425 int ret;
2426
5fdbf976 2427 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2428 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2429 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2430 ret = -ENOMEM;
2431 goto out;
2432 }
2433
7ffd92c5 2434 vmx->rmode.vm86_active = 0;
e00c8cf2 2435
3b86cd99
JK		 2436 vmx->soft_vnmi_blocked = 0;
2437
ad312c7c 2438 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2439 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2440 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2441 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2442 msr |= MSR_IA32_APICBASE_BSP;
2443 kvm_set_apic_base(&vmx->vcpu, msr);
2444
2445 fx_init(&vmx->vcpu);
2446
5706be0d 2447 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2448 /*
2449 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2450 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2451 */
c5af89b6 2452 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2453 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2454 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2455 } else {
ad312c7c
ZX		 2456 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2457 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2458 }
e00c8cf2
AK		 2459
2460 seg_setup(VCPU_SREG_DS);
2461 seg_setup(VCPU_SREG_ES);
2462 seg_setup(VCPU_SREG_FS);
2463 seg_setup(VCPU_SREG_GS);
2464 seg_setup(VCPU_SREG_SS);
2465
2466 vmcs_write16(GUEST_TR_SELECTOR, 0);
2467 vmcs_writel(GUEST_TR_BASE, 0);
2468 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2469 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2470
2471 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2472 vmcs_writel(GUEST_LDTR_BASE, 0);
2473 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2474 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2475
2476 vmcs_write32(GUEST_SYSENTER_CS, 0);
2477 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2478 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2479
2480 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2481 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2482 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2483 else
5fdbf976
MT		 2484 kvm_rip_write(vcpu, 0);
2485 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2486
e00c8cf2
AK		 2487 vmcs_writel(GUEST_DR7, 0x400);
2488
2489 vmcs_writel(GUEST_GDTR_BASE, 0);
2490 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2491
2492 vmcs_writel(GUEST_IDTR_BASE, 0);
2493 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2494
2495 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2496 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2497 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2498
e00c8cf2
AK		 2499 /* Special registers */
2500 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2501
2502 setup_msrs(vmx);
2503
6aa8b732
AK		 2504 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2505
f78e0e2e
SY		 2506 if (cpu_has_vmx_tpr_shadow()) {
2507 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2508 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2509 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2510 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2511 vmcs_write32(TPR_THRESHOLD, 0);
2512 }
2513
2514 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2515 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2516 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2517
2384d2b3
SY		 2518 if (vmx->vpid != 0)
2519 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2520
ad312c7c
ZX		 2521 vmx->vcpu.arch.cr0 = 0x60000010;
2522 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2523 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2524 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2525 vmx_fpu_activate(&vmx->vcpu);
2526 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2527
2384d2b3
SY		 2528 vpid_sync_vcpu_all(vmx);
2529
3200f405 2530 ret = 0;
6aa8b732 2531
a89a8fb9
MG		 2532 /* HACK: Don't enable emulation on guest boot/reset */
2533 vmx->emulation_required = 0;
2534
6aa8b732 2535out:
3200f405 2536 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2537 return ret;
2538}
2539
3b86cd99
JK		 2540static void enable_irq_window(struct kvm_vcpu *vcpu)
2541{
2542 u32 cpu_based_vm_exec_control;
2543
2544 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2545 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2546 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2547}
2548
2549static void enable_nmi_window(struct kvm_vcpu *vcpu)
2550{
2551 u32 cpu_based_vm_exec_control;
2552
2553 if (!cpu_has_virtual_nmis()) {
2554 enable_irq_window(vcpu);
2555 return;
2556 }
2557
2558 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2559 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2560 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2561}
2562
66fd3f7f 2563static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2564{
9c8cba37 2565 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2566 uint32_t intr;
2567 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2568
229456fc 2569 trace_kvm_inj_virq(irq);
2714d1d3 2570
fa89a817 2571 ++vcpu->stat.irq_injections;
7ffd92c5 2572 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2573 vmx->rmode.irq.pending = true;
2574 vmx->rmode.irq.vector = irq;
5fdbf976 2575 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2576 if (vcpu->arch.interrupt.soft)
2577 vmx->rmode.irq.rip +=
2578 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2579 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2580 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2581 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2582 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2583 return;
2584 }
66fd3f7f
GN		 2585 intr = irq | INTR_INFO_VALID_MASK;
2586 if (vcpu->arch.interrupt.soft) {
2587 intr |= INTR_TYPE_SOFT_INTR;
2588 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2589 vmx->vcpu.arch.event_exit_inst_len);
2590 } else
2591 intr |= INTR_TYPE_EXT_INTR;
2592 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2593}
2594
f08864b4
SY		 2595static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2596{
66a5a347
JK		 2597 struct vcpu_vmx *vmx = to_vmx(vcpu);
2598
3b86cd99
JK		 2599 if (!cpu_has_virtual_nmis()) {
2600 /*
2601 * Tracking the NMI-blocked state in software is built upon
2602 * finding the next open IRQ window. This, in turn, depends on
2603 * well-behaving guests: They have to keep IRQs disabled at
2604 * least as long as the NMI handler runs. Otherwise we may
2605 * cause NMI nesting, maybe breaking the guest. But as this is
2606 * highly unlikely, we can live with the residual risk.
2607 */
2608 vmx->soft_vnmi_blocked = 1;
2609 vmx->vnmi_blocked_time = 0;
2610 }
2611
487b391d 2612 ++vcpu->stat.nmi_injections;
7ffd92c5 2613 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2614 vmx->rmode.irq.pending = true;
2615 vmx->rmode.irq.vector = NMI_VECTOR;
2616 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2617 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2618 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2619 INTR_INFO_VALID_MASK);
2620 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2621 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2622 return;
2623 }
f08864b4
SY		 2624 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2625 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2626}
2627
c4282df9 2628static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2629{
3b86cd99 2630 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2631 return 0;
33f089ca 2632
c4282df9
GN		 2633 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2634 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2635 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2636}
2637
78646121
GN		 2638static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2639{
c4282df9
GN		 2640 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2641 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2642 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2643}
2644
cbc94022
IE		 2645static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2646{
2647 int ret;
2648 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2649 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2650 .guest_phys_addr = addr,
2651 .memory_size = PAGE_SIZE * 3,
2652 .flags = 0,
2653 };
2654
2655 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2656 if (ret)
2657 return ret;
bfc6d222 2658 kvm->arch.tss_addr = addr;
cbc94022
IE		 2659 return 0;
2660}
2661
6aa8b732
AK		 2662static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2663 int vec, u32 err_code)
2664{
b3f37707
NK		 2665 /*
2666 * Instruction with address size override prefix opcode 0x67
2667 * Cause the #SS fault with 0 error code in VM86 mode.
2668 */
2669 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2670 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2671 return 1;
77ab6db0
JK		 2672 /*
2673 * Forward all other exceptions that are valid in real mode.
2674 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2675 * the required debugging infrastructure rework.
2676 */
2677 switch (vec) {
77ab6db0 2678 case DB_VECTOR:
d0bfb940
JK		 2679 if (vcpu->guest_debug &
2680 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2681 return 0;
2682 kvm_queue_exception(vcpu, vec);
2683 return 1;
77ab6db0 2684 case BP_VECTOR:
d0bfb940
JK		 2685 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2686 return 0;
2687 /* fall through */
2688 case DE_VECTOR:
77ab6db0
JK		 2689 case OF_VECTOR:
2690 case BR_VECTOR:
2691 case UD_VECTOR:
2692 case DF_VECTOR:
2693 case SS_VECTOR:
2694 case GP_VECTOR:
2695 case MF_VECTOR:
2696 kvm_queue_exception(vcpu, vec);
2697 return 1;
2698 }
6aa8b732
AK		 2699 return 0;
2700}
2701
a0861c02
AK		 2702/*
2703 * Trigger machine check on the host. We assume all the MSRs are already set up
2704 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2705 * We pass a fake environment to the machine check handler because we want
2706 * the guest to be always treated like user space, no matter what context
2707 * it used internally.
2708 */
2709static void kvm_machine_check(void)
2710{
2711#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2712 struct pt_regs regs = {
2713 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2714 .flags = X86_EFLAGS_IF,
2715 };
2716
2717 do_machine_check(&regs, 0);
2718#endif
2719}
2720
851ba692 2721static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2722{
2723 /* already handled by vcpu_run */
2724 return 1;
2725}
2726
851ba692 2727static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2728{
1155f76a 2729 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2730 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2731 u32 intr_info, ex_no, error_code;
42dbaa5a 2732 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2733 u32 vect_info;
2734 enum emulation_result er;
2735
1155f76a 2736 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2737 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2738
a0861c02 2739 if (is_machine_check(intr_info))
851ba692 2740 return handle_machine_check(vcpu);
a0861c02 2741
6aa8b732 2742 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2743 !is_page_fault(intr_info))
6aa8b732 2744 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2745 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2746
e4a41889 2747 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2748 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2749
2750 if (is_no_device(intr_info)) {
5fd86fcf 2751 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2752 return 1;
2753 }
2754
7aa81cc0 2755 if (is_invalid_opcode(intr_info)) {
851ba692 2756 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2757 if (er != EMULATE_DONE)
7ee5d940 2758 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2759 return 1;
2760 }
2761
6aa8b732 2762 error_code = 0;
5fdbf976 2763 rip = kvm_rip_read(vcpu);
2e11384c 2764 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2765 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2766 if (is_page_fault(intr_info)) {
1439442c 2767 /* EPT won't cause page fault directly */
089d034e 2768 if (enable_ept)
1439442c 2769 BUG();
6aa8b732 2770 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2771 trace_kvm_page_fault(cr2, error_code);
2772
3298b75c 2773 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2774 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2775 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2776 }
2777
7ffd92c5 2778 if (vmx->rmode.vm86_active &&
6aa8b732 2779 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2780 error_code)) {
ad312c7c
ZX		 2781 if (vcpu->arch.halt_request) {
2782 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2783 return kvm_emulate_halt(vcpu);
2784 }
6aa8b732 2785 return 1;
72d6e5a0 2786 }
6aa8b732 2787
d0bfb940 2788 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2789 switch (ex_no) {
2790 case DB_VECTOR:
2791 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2792 if (!(vcpu->guest_debug &
2793 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2794 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2795 kvm_queue_exception(vcpu, DB_VECTOR);
2796 return 1;
2797 }
2798 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2799 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2800 /* fall through */
2801 case BP_VECTOR:
6aa8b732 2802 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2803 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2804 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2805 break;
2806 default:
d0bfb940
JK		 2807 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2808 kvm_run->ex.exception = ex_no;
2809 kvm_run->ex.error_code = error_code;
42dbaa5a 2810 break;
6aa8b732 2811 }
6aa8b732
AK		 2812 return 0;
2813}
2814
851ba692 2815static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2816{
1165f5fe 2817 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2818 return 1;
2819}
2820
851ba692 2821static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2822{
851ba692 2823 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2824 return 0;
2825}
6aa8b732 2826
851ba692 2827static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2828{
bfdaab09 2829 unsigned long exit_qualification;
34c33d16 2830 int size, in, string;
039576c0 2831 unsigned port;
6aa8b732 2832
1165f5fe 2833 ++vcpu->stat.io_exits;
bfdaab09 2834 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2835 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2836
2837 if (string) {
851ba692 2838 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2839 return 0;
2840 return 1;
2841 }
2842
2843 size = (exit_qualification & 7) + 1;
2844 in = (exit_qualification & 8) != 0;
039576c0 2845 port = exit_qualification >> 16;
e70669ab 2846
e93f36bc 2847 skip_emulated_instruction(vcpu);
851ba692 2848 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2849}
2850
102d8325
IM		 2851static void
2852vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2853{
2854 /*
2855 * Patch in the VMCALL instruction:
2856 */
2857 hypercall[0] = 0x0f;
2858 hypercall[1] = 0x01;
2859 hypercall[2] = 0xc1;
102d8325
IM		 2860}
2861
851ba692 2862static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2863{
229456fc 2864 unsigned long exit_qualification, val;
6aa8b732
AK		 2865 int cr;
2866 int reg;
2867
bfdaab09 2868 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2869 cr = exit_qualification & 15;
2870 reg = (exit_qualification >> 8) & 15;
2871 switch ((exit_qualification >> 4) & 3) {
2872 case 0: /* mov to cr */
229456fc
MT		 2873 val = kvm_register_read(vcpu, reg);
2874 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2875 switch (cr) {
2876 case 0:
229456fc 2877 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2878 skip_emulated_instruction(vcpu);
2879 return 1;
2880 case 3:
229456fc 2881 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2882 skip_emulated_instruction(vcpu);
2883 return 1;
2884 case 4:
229456fc 2885 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2886 skip_emulated_instruction(vcpu);
2887 return 1;
0a5fff19
GN		 2888 case 8: {
2889 u8 cr8_prev = kvm_get_cr8(vcpu);
2890 u8 cr8 = kvm_register_read(vcpu, reg);
2891 kvm_set_cr8(vcpu, cr8);
2892 skip_emulated_instruction(vcpu);
2893 if (irqchip_in_kernel(vcpu->kvm))
2894 return 1;
2895 if (cr8_prev <= cr8)
2896 return 1;
851ba692 2897 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 2898 return 0;
2899 }
6aa8b732
AK		 2900 };
2901 break;
25c4c276 2902 case 2: /* clts */
5fd86fcf 2903 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2904 vcpu->arch.cr0 &= ~X86_CR0_TS;
2905 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2906 vmx_fpu_activate(vcpu);
25c4c276
AL		 2907 skip_emulated_instruction(vcpu);
2908 return 1;
6aa8b732
AK		 2909 case 1: /*mov from cr*/
2910 switch (cr) {
2911 case 3:
5fdbf976 2912 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2913 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2914 skip_emulated_instruction(vcpu);
2915 return 1;
2916 case 8:
229456fc
MT		 2917 val = kvm_get_cr8(vcpu);
2918 kvm_register_write(vcpu, reg, val);
2919 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2920 skip_emulated_instruction(vcpu);
2921 return 1;
2922 }
2923 break;
2924 case 3: /* lmsw */
2d3ad1f4 2925 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2926
2927 skip_emulated_instruction(vcpu);
2928 return 1;
2929 default:
2930 break;
2931 }
851ba692 2932 vcpu->run->exit_reason = 0;
f0242478 2933 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2934 (int)(exit_qualification >> 4) & 3, cr);
2935 return 0;
2936}
2937
851ba692 2938static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 2939{
bfdaab09 2940 unsigned long exit_qualification;
6aa8b732
AK		 2941 unsigned long val;
2942 int dr, reg;
2943
0a79b009
AK		 2944 if (!kvm_require_cpl(vcpu, 0))
2945 return 1;
42dbaa5a
JK		 2946 dr = vmcs_readl(GUEST_DR7);
2947 if (dr & DR7_GD) {
2948 /*
2949 * As the vm-exit takes precedence over the debug trap, we
2950 * need to emulate the latter, either for the host or the
2951 * guest debugging itself.
2952 */
2953 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 2954 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2955 vcpu->run->debug.arch.dr7 = dr;
2956 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 2957 vmcs_readl(GUEST_CS_BASE) +
2958 vmcs_readl(GUEST_RIP);
851ba692
AK		 2959 vcpu->run->debug.arch.exception = DB_VECTOR;
2960 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 2961 return 0;
2962 } else {
2963 vcpu->arch.dr7 &= ~DR7_GD;
2964 vcpu->arch.dr6 |= DR6_BD;
2965 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2966 kvm_queue_exception(vcpu, DB_VECTOR);
2967 return 1;
2968 }
2969 }
2970
bfdaab09 2971 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2972 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2973 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2974 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2975 switch (dr) {
42dbaa5a
JK		 2976 case 0 ... 3:
2977 val = vcpu->arch.db[dr];
2978 break;
6aa8b732 2979 case 6:
42dbaa5a 2980 val = vcpu->arch.dr6;
6aa8b732
AK		 2981 break;
2982 case 7:
42dbaa5a 2983 val = vcpu->arch.dr7;
6aa8b732
AK		 2984 break;
2985 default:
2986 val = 0;
2987 }
5fdbf976 2988 kvm_register_write(vcpu, reg, val);
6aa8b732 2989 } else {
42dbaa5a
JK		 2990 val = vcpu->arch.regs[reg];
2991 switch (dr) {
2992 case 0 ... 3:
2993 vcpu->arch.db[dr] = val;
2994 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2995 vcpu->arch.eff_db[dr] = val;
2996 break;
2997 case 4 ... 5:
2998 if (vcpu->arch.cr4 & X86_CR4_DE)
2999 kvm_queue_exception(vcpu, UD_VECTOR);
3000 break;
3001 case 6:
3002 if (val & 0xffffffff00000000ULL) {
3003 kvm_queue_exception(vcpu, GP_VECTOR);
3004 break;
3005 }
3006 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3007 break;
3008 case 7:
3009 if (val & 0xffffffff00000000ULL) {
3010 kvm_queue_exception(vcpu, GP_VECTOR);
3011 break;
3012 }
3013 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3014 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3015 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3016 vcpu->arch.switch_db_regs =
3017 (val & DR7_BP_EN_MASK);
3018 }
3019 break;
3020 }
6aa8b732 3021 }
6aa8b732
AK		 3022 skip_emulated_instruction(vcpu);
3023 return 1;
3024}
3025
851ba692 3026static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3027{
06465c5a
AK		 3028 kvm_emulate_cpuid(vcpu);
3029 return 1;
6aa8b732
AK		 3030}
3031
851ba692 3032static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3033{
ad312c7c 3034 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3035 u64 data;
3036
3037 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3038 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3039 return 1;
3040 }
3041
229456fc 3042 trace_kvm_msr_read(ecx, data);
2714d1d3 3043
6aa8b732 3044 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3045 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3046 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3047 skip_emulated_instruction(vcpu);
3048 return 1;
3049}
3050
851ba692 3051static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3052{
ad312c7c
ZX		 3053 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3054 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3055 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3056
229456fc 3057 trace_kvm_msr_write(ecx, data);
2714d1d3 3058
6aa8b732 3059 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3060 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3061 return 1;
3062 }
3063
3064 skip_emulated_instruction(vcpu);
3065 return 1;
3066}
3067
851ba692 3068static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3069{
3070 return 1;
3071}
3072
851ba692 3073static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3074{
85f455f7
ED		 3075 u32 cpu_based_vm_exec_control;
3076
3077 /* clear pending irq */
3078 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3079 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3080 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3081
a26bf12a 3082 ++vcpu->stat.irq_window_exits;
2714d1d3 3083
c1150d8c
DL		 3084 /*
3085 * If the user space waits to inject interrupts, exit as soon as
3086 * possible
3087 */
8061823a 3088 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3089 vcpu->run->request_interrupt_window &&
8061823a 3090 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3091 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3092 return 0;
3093 }
6aa8b732
AK		 3094 return 1;
3095}
3096
851ba692 3097static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3098{
3099 skip_emulated_instruction(vcpu);
d3bef15f 3100 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3101}
3102
851ba692 3103static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3104{
510043da 3105 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3106 kvm_emulate_hypercall(vcpu);
3107 return 1;
c21415e8
IM		 3108}
3109
851ba692 3110static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3111{
3112 kvm_queue_exception(vcpu, UD_VECTOR);
3113 return 1;
3114}
3115
851ba692 3116static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3117{
f9c617f6 3118 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3119
3120 kvm_mmu_invlpg(vcpu, exit_qualification);
3121 skip_emulated_instruction(vcpu);
3122 return 1;
3123}
3124
851ba692 3125static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3126{
3127 skip_emulated_instruction(vcpu);
3128 /* TODO: Add support for VT-d/pass-through device */
3129 return 1;
3130}
3131
851ba692 3132static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3133{
f9c617f6 3134 unsigned long exit_qualification;
f78e0e2e
SY		 3135 enum emulation_result er;
3136 unsigned long offset;
3137
f9c617f6 3138 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3139 offset = exit_qualification & 0xffful;
3140
851ba692 3141 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3142
3143 if (er != EMULATE_DONE) {
3144 printk(KERN_ERR
3145 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3146 offset);
7f582ab6 3147 return -ENOEXEC;
f78e0e2e
SY		 3148 }
3149 return 1;
3150}
3151
851ba692 3152static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3153{
60637aac 3154 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3155 unsigned long exit_qualification;
3156 u16 tss_selector;
64a7ec06
GN		 3157 int reason, type, idt_v;
3158
3159 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3160 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3161
3162 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3163
3164 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3165 if (reason == TASK_SWITCH_GATE && idt_v) {
3166 switch (type) {
3167 case INTR_TYPE_NMI_INTR:
3168 vcpu->arch.nmi_injected = false;
3169 if (cpu_has_virtual_nmis())
3170 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3171 GUEST_INTR_STATE_NMI);
3172 break;
3173 case INTR_TYPE_EXT_INTR:
66fd3f7f 3174 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3175 kvm_clear_interrupt_queue(vcpu);
3176 break;
3177 case INTR_TYPE_HARD_EXCEPTION:
3178 case INTR_TYPE_SOFT_EXCEPTION:
3179 kvm_clear_exception_queue(vcpu);
3180 break;
3181 default:
3182 break;
3183 }
60637aac 3184 }
37817f29
IE		 3185 tss_selector = exit_qualification;
3186
64a7ec06
GN		 3187 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3188 type != INTR_TYPE_EXT_INTR &&
3189 type != INTR_TYPE_NMI_INTR))
3190 skip_emulated_instruction(vcpu);
3191
42dbaa5a
JK		 3192 if (!kvm_task_switch(vcpu, tss_selector, reason))
3193 return 0;
3194
3195 /* clear all local breakpoint enable flags */
3196 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3197
3198 /*
3199 * TODO: What about debug traps on tss switch?
3200 * Are we supposed to inject them and update dr6?
3201 */
3202
3203 return 1;
37817f29
IE		 3204}
3205
851ba692 3206static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3207{
f9c617f6 3208 unsigned long exit_qualification;
1439442c 3209 gpa_t gpa;
1439442c 3210 int gla_validity;
1439442c 3211
f9c617f6 3212 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3213
3214 if (exit_qualification & (1 << 6)) {
3215 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3216 return -EINVAL;
1439442c
SY		 3217 }
3218
3219 gla_validity = (exit_qualification >> 7) & 0x3;
3220 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3221 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3222 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3223 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3224 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3225 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3226 (long unsigned int)exit_qualification);
851ba692
AK		 3227 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3228 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3229 return 0;
1439442c
SY		 3230 }
3231
3232 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3233 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3234 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3235}
3236
68f89400
MT		 3237static u64 ept_rsvd_mask(u64 spte, int level)
3238{
3239 int i;
3240 u64 mask = 0;
3241
3242 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3243 mask |= (1ULL << i);
3244
3245 if (level > 2)
3246 /* bits 7:3 reserved */
3247 mask |= 0xf8;
3248 else if (level == 2) {
3249 if (spte & (1ULL << 7))
3250 /* 2MB ref, bits 20:12 reserved */
3251 mask |= 0x1ff000;
3252 else
3253 /* bits 6:3 reserved */
3254 mask |= 0x78;
3255 }
3256
3257 return mask;
3258}
3259
3260static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3261 int level)
3262{
3263 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3264
3265 /* 010b (write-only) */
3266 WARN_ON((spte & 0x7) == 0x2);
3267
3268 /* 110b (write/execute) */
3269 WARN_ON((spte & 0x7) == 0x6);
3270
3271 /* 100b (execute-only) and value not supported by logical processor */
3272 if (!cpu_has_vmx_ept_execute_only())
3273 WARN_ON((spte & 0x7) == 0x4);
3274
3275 /* not 000b */
3276 if ((spte & 0x7)) {
3277 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3278
3279 if (rsvd_bits != 0) {
3280 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3281 __func__, rsvd_bits);
3282 WARN_ON(1);
3283 }
3284
3285 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3286 u64 ept_mem_type = (spte & 0x38) >> 3;
3287
3288 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3289 ept_mem_type == 7) {
3290 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3291 __func__, ept_mem_type);
3292 WARN_ON(1);
3293 }
3294 }
3295 }
3296}
3297
851ba692 3298static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3299{
3300 u64 sptes[4];
3301 int nr_sptes, i;
3302 gpa_t gpa;
3303
3304 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3305
3306 printk(KERN_ERR "EPT: Misconfiguration.\n");
3307 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3308
3309 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3310
3311 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3312 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3313
851ba692
AK		 3314 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3315 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3316
3317 return 0;
3318}
3319
851ba692 3320static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3321{
3322 u32 cpu_based_vm_exec_control;
3323
3324 /* clear pending NMI */
3325 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3326 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3327 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3328 ++vcpu->stat.nmi_window_exits;
3329
3330 return 1;
3331}
3332
80ced186 3333static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3334{
8b3079a5
AK		 3335 struct vcpu_vmx *vmx = to_vmx(vcpu);
3336 enum emulation_result err = EMULATE_DONE;
80ced186 3337 int ret = 1;
ea953ef0
MG		 3338
3339 while (!guest_state_valid(vcpu)) {
851ba692 3340 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3341
80ced186
MG		 3342 if (err == EMULATE_DO_MMIO) {
3343 ret = 0;
3344 goto out;
3345 }
1d5a4d9b
GT		 3346
3347 if (err != EMULATE_DONE) {
3348 kvm_report_emulation_failure(vcpu, "emulation failure");
80ced186
MG		 3349 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3350 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3351 ret = 0;
3352 goto out;
ea953ef0
MG		 3353 }
3354
3355 if (signal_pending(current))
80ced186 3356 goto out;
ea953ef0
MG		 3357 if (need_resched())
3358 schedule();
3359 }
3360
80ced186
MG		 3361 vmx->emulation_required = 0;
3362out:
3363 return ret;
ea953ef0
MG		 3364}
3365
6aa8b732
AK		 3366/*
3367 * The exit handlers return 1 if the exit was handled fully and guest execution
3368 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3369 * to be done to userspace and return 0.
3370 */
851ba692 3371static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3372 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3373 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3374 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3375 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3376 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3377 [EXIT_REASON_CR_ACCESS] = handle_cr,
3378 [EXIT_REASON_DR_ACCESS] = handle_dr,
3379 [EXIT_REASON_CPUID] = handle_cpuid,
3380 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3381 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3382 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3383 [EXIT_REASON_HLT] = handle_halt,
a7052897 3384 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3385 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3386 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3387 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3388 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3389 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3390 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3391 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3392 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3393 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3394 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3395 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3396 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3397 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3398 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3399 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3400 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3401 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
6aa8b732
AK		 3402};
3403
3404static const int kvm_vmx_max_exit_handlers =
50a3485c 3405 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3406
3407/*
3408 * The guest has exited. See if we can fix it or if we need userspace
3409 * assistance.
3410 */
851ba692 3411static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3412{
29bd8a78 3413 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3414 u32 exit_reason = vmx->exit_reason;
1155f76a 3415 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3416
229456fc 3417 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3418
80ced186
MG		 3419 /* If guest state is invalid, start emulating */
3420 if (vmx->emulation_required && emulate_invalid_guest_state)
3421 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3422
1439442c
SY		 3423 /* Access CR3 don't cause VMExit in paging mode, so we need
3424 * to sync with guest real CR3. */
6de4f3ad 3425 if (enable_ept && is_paging(vcpu))
1439442c 3426 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3427
29bd8a78 3428 if (unlikely(vmx->fail)) {
851ba692
AK		 3429 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3430 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3431 = vmcs_read32(VM_INSTRUCTION_ERROR);
3432 return 0;
3433 }
6aa8b732 3434
d77c26fc 3435 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3436 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3437 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3438 exit_reason != EXIT_REASON_TASK_SWITCH))
3439 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3440 "(0x%x) and exit reason is 0x%x\n",
3441 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3442
3443 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3444 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3445 vmx->soft_vnmi_blocked = 0;
3b86cd99 3446 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3447 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3448 /*
3449 * This CPU don't support us in finding the end of an
3450 * NMI-blocked window if the guest runs with IRQs
3451 * disabled. So we pull the trigger after 1 s of
3452 * futile waiting, but inform the user about this.
3453 */
3454 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3455 "state on VCPU %d after 1 s timeout\n",
3456 __func__, vcpu->vcpu_id);
3457 vmx->soft_vnmi_blocked = 0;
3b86cd99 3458 }
3b86cd99
JK		 3459 }
3460
6aa8b732
AK		 3461 if (exit_reason < kvm_vmx_max_exit_handlers
3462 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3463 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3464 else {
851ba692
AK		 3465 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3466 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3467 }
3468 return 0;
3469}
3470
95ba8273 3471static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3472{
95ba8273 3473 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3474 vmcs_write32(TPR_THRESHOLD, 0);
3475 return;
3476 }
3477
95ba8273 3478 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3479}
3480
cf393f75
AK		 3481static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3482{
3483 u32 exit_intr_info;
7b4a25cb 3484 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3485 bool unblock_nmi;
3486 u8 vector;
668f612f
AK		 3487 int type;
3488 bool idtv_info_valid;
cf393f75
AK		 3489
3490 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3491
a0861c02
AK		 3492 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3493
3494 /* Handle machine checks before interrupts are enabled */
3495 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3496 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3497 && is_machine_check(exit_intr_info)))
3498 kvm_machine_check();
3499
20f65983
GN		 3500 /* We need to handle NMIs before interrupts are enabled */
3501 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3502 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3503 asm("int $2");
20f65983
GN		 3504
3505 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3506
cf393f75
AK		 3507 if (cpu_has_virtual_nmis()) {
3508 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3509 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3510 /*
7b4a25cb 3511 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3512 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3513 * a guest IRET fault.
7b4a25cb
GN		 3514 * SDM 3: 23.2.2 (September 2008)
3515 * Bit 12 is undefined in any of the following cases:
3516 * If the VM exit sets the valid bit in the IDT-vectoring
3517 * information field.
3518 * If the VM exit is due to a double fault.
cf393f75 3519 */
7b4a25cb
GN		 3520 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3521 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3522 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3523 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3524 } else if (unlikely(vmx->soft_vnmi_blocked))
3525 vmx->vnmi_blocked_time +=
3526 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3527
37b96e98
GN		 3528 vmx->vcpu.arch.nmi_injected = false;
3529 kvm_clear_exception_queue(&vmx->vcpu);
3530 kvm_clear_interrupt_queue(&vmx->vcpu);
3531
3532 if (!idtv_info_valid)
3533 return;
3534
668f612f
AK		 3535 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3536 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3537
64a7ec06 3538 switch (type) {
37b96e98
GN		 3539 case INTR_TYPE_NMI_INTR:
3540 vmx->vcpu.arch.nmi_injected = true;
668f612f 3541 /*
7b4a25cb 3542 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3543 * Clear bit "block by NMI" before VM entry if a NMI
3544 * delivery faulted.
668f612f 3545 */
37b96e98
GN		 3546 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3547 GUEST_INTR_STATE_NMI);
3548 break;
37b96e98 3549 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3550 vmx->vcpu.arch.event_exit_inst_len =
3551 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3552 /* fall through */
3553 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3554 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3555 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3556 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3557 } else
3558 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3559 break;
66fd3f7f
GN		 3560 case INTR_TYPE_SOFT_INTR:
3561 vmx->vcpu.arch.event_exit_inst_len =
3562 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3563 /* fall through */
37b96e98 3564 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3565 kvm_queue_interrupt(&vmx->vcpu, vector,
3566 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3567 break;
3568 default:
3569 break;
f7d9238f 3570 }
cf393f75
AK		 3571}
3572
9c8cba37
AK		 3573/*
3574 * Failure to inject an interrupt should give us the information
3575 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3576 * when fetching the interrupt redirection bitmap in the real-mode
3577 * tss, this doesn't happen. So we do it ourselves.
3578 */
3579static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3580{
3581 vmx->rmode.irq.pending = 0;
5fdbf976 3582 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3583 return;
5fdbf976 3584 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3585 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3586 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3587 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3588 return;
3589 }
3590 vmx->idt_vectoring_info =
3591 VECTORING_INFO_VALID_MASK
3592 | INTR_TYPE_EXT_INTR
3593 | vmx->rmode.irq.vector;
3594}
3595
c801949d
AK		 3596#ifdef CONFIG_X86_64
3597#define R "r"
3598#define Q "q"
3599#else
3600#define R "e"
3601#define Q "l"
3602#endif
3603
851ba692 3604static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3605{
a2fa3e9f 3606 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3607
8f5d549f
AK		 3608 if (enable_ept && is_paging(vcpu)) {
3609 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3610 ept_load_pdptrs(vcpu);
3611 }
3b86cd99
JK		 3612 /* Record the guest's net vcpu time for enforced NMI injections. */
3613 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3614 vmx->entry_time = ktime_get();
3615
80ced186
MG		 3616 /* Don't enter VMX if guest state is invalid, let the exit handler
3617 start emulation until we arrive back to a valid state */
3618 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3619 return;
a89a8fb9 3620
5fdbf976
MT		 3621 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3622 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3623 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3624 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3625
787ff736
GN		 3626 /* When single-stepping over STI and MOV SS, we must clear the
3627 * corresponding interruptibility bits in the guest state. Otherwise
3628 * vmentry fails as it then expects bit 14 (BS) in pending debug
3629 * exceptions being set, but that's not correct for the guest debugging
3630 * case. */
3631 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3632 vmx_set_interrupt_shadow(vcpu, 0);
3633
e6adf283
AK		 3634 /*
3635 * Loading guest fpu may have cleared host cr0.ts
3636 */
3637 vmcs_writel(HOST_CR0, read_cr0());
3638
e8a48342
AK		 3639 if (vcpu->arch.switch_db_regs)
3640 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3641
d77c26fc 3642 asm(
6aa8b732 3643 /* Store host registers */
c801949d
AK		 3644 "push %%"R"dx; push %%"R"bp;"
3645 "push %%"R"cx \n\t"
313dbd49
AK		 3646 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3647 "je 1f \n\t"
3648 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3649 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3650 "1: \n\t"
d3edefc0
AK		 3651 /* Reload cr2 if changed */
3652 "mov %c[cr2](%0), %%"R"ax \n\t"
3653 "mov %%cr2, %%"R"dx \n\t"
3654 "cmp %%"R"ax, %%"R"dx \n\t"
3655 "je 2f \n\t"
3656 "mov %%"R"ax, %%cr2 \n\t"
3657 "2: \n\t"
6aa8b732 3658 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3659 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3660 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3661 "mov %c[rax](%0), %%"R"ax \n\t"
3662 "mov %c[rbx](%0), %%"R"bx \n\t"
3663 "mov %c[rdx](%0), %%"R"dx \n\t"
3664 "mov %c[rsi](%0), %%"R"si \n\t"
3665 "mov %c[rdi](%0), %%"R"di \n\t"
3666 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3667#ifdef CONFIG_X86_64
e08aa78a
AK		 3668 "mov %c[r8](%0), %%r8 \n\t"
3669 "mov %c[r9](%0), %%r9 \n\t"
3670 "mov %c[r10](%0), %%r10 \n\t"
3671 "mov %c[r11](%0), %%r11 \n\t"
3672 "mov %c[r12](%0), %%r12 \n\t"
3673 "mov %c[r13](%0), %%r13 \n\t"
3674 "mov %c[r14](%0), %%r14 \n\t"
3675 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3676#endif
c801949d
AK		 3677 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3678
6aa8b732 3679 /* Enter guest mode */
cd2276a7 3680 "jne .Llaunched \n\t"
4ecac3fd 3681 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3682 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3683 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3684 ".Lkvm_vmx_return: "
6aa8b732 3685 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3686 "xchg %0, (%%"R"sp) \n\t"
3687 "mov %%"R"ax, %c[rax](%0) \n\t"
3688 "mov %%"R"bx, %c[rbx](%0) \n\t"
3689 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3690 "mov %%"R"dx, %c[rdx](%0) \n\t"
3691 "mov %%"R"si, %c[rsi](%0) \n\t"
3692 "mov %%"R"di, %c[rdi](%0) \n\t"
3693 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3694#ifdef CONFIG_X86_64
e08aa78a
AK		 3695 "mov %%r8, %c[r8](%0) \n\t"
3696 "mov %%r9, %c[r9](%0) \n\t"
3697 "mov %%r10, %c[r10](%0) \n\t"
3698 "mov %%r11, %c[r11](%0) \n\t"
3699 "mov %%r12, %c[r12](%0) \n\t"
3700 "mov %%r13, %c[r13](%0) \n\t"
3701 "mov %%r14, %c[r14](%0) \n\t"
3702 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3703#endif
c801949d
AK		 3704 "mov %%cr2, %%"R"ax \n\t"
3705 "mov %%"R"ax, %c[cr2](%0) \n\t"
3706
3707 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3708 "setbe %c[fail](%0) \n\t"
3709 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3710 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3711 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3712 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3713 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3714 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3715 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3716 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3717 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3718 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3719 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3720#ifdef CONFIG_X86_64
ad312c7c
ZX		 3721 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3722 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3723 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3724 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3725 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3726 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3727 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3728 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3729#endif
ad312c7c 3730 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3731 : "cc", "memory"
c801949d 3732 , R"bx", R"di", R"si"
c2036300 3733#ifdef CONFIG_X86_64
c2036300
LV		 3734 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3735#endif
3736 );
6aa8b732 3737
6de4f3ad
AK		 3738 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3739 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3740 vcpu->arch.regs_dirty = 0;
3741
e8a48342
AK		 3742 if (vcpu->arch.switch_db_regs)
3743 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3744
1155f76a 3745 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3746 if (vmx->rmode.irq.pending)
3747 fixup_rmode_irq(vmx);
1155f76a 3748
d77c26fc 3749 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3750 vmx->launched = 1;
1b6269db 3751
cf393f75 3752 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3753}
3754
c801949d
AK		 3755#undef R
3756#undef Q
3757
6aa8b732
AK		 3758static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3759{
a2fa3e9f
GH		 3760 struct vcpu_vmx *vmx = to_vmx(vcpu);
3761
3762 if (vmx->vmcs) {
543e4243 3763 vcpu_clear(vmx);
a2fa3e9f
GH		 3764 free_vmcs(vmx->vmcs);
3765 vmx->vmcs = NULL;
6aa8b732
AK		 3766 }
3767}
3768
3769static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3770{
fb3f0f51
RR		 3771 struct vcpu_vmx *vmx = to_vmx(vcpu);
3772
2384d2b3
SY		 3773 spin_lock(&vmx_vpid_lock);
3774 if (vmx->vpid != 0)
3775 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3776 spin_unlock(&vmx_vpid_lock);
6aa8b732 3777 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3778 kfree(vmx->host_msrs);
3779 kfree(vmx->guest_msrs);
3780 kvm_vcpu_uninit(vcpu);
a4770347 3781 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3782}
3783
fb3f0f51 3784static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3785{
fb3f0f51 3786 int err;
c16f862d 3787 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3788 int cpu;
6aa8b732 3789
a2fa3e9f 3790 if (!vmx)
fb3f0f51
RR		 3791 return ERR_PTR(-ENOMEM);
3792
2384d2b3
SY		 3793 allocate_vpid(vmx);
3794
fb3f0f51
RR		 3795 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3796 if (err)
3797 goto free_vcpu;
965b58a5 3798
a2fa3e9f 3799 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3800 if (!vmx->guest_msrs) {
3801 err = -ENOMEM;
3802 goto uninit_vcpu;
3803 }
965b58a5 3804
a2fa3e9f
GH		 3805 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3806 if (!vmx->host_msrs)
fb3f0f51 3807 goto free_guest_msrs;
965b58a5 3808
a2fa3e9f
GH		 3809 vmx->vmcs = alloc_vmcs();
3810 if (!vmx->vmcs)
fb3f0f51 3811 goto free_msrs;
a2fa3e9f
GH		 3812
3813 vmcs_clear(vmx->vmcs);
3814
15ad7146
AK		 3815 cpu = get_cpu();
3816 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3817 err = vmx_vcpu_setup(vmx);
fb3f0f51 3818 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3819 put_cpu();
fb3f0f51
RR		 3820 if (err)
3821 goto free_vmcs;
5e4a0b3c
MT		 3822 if (vm_need_virtualize_apic_accesses(kvm))
3823 if (alloc_apic_access_page(kvm) != 0)
3824 goto free_vmcs;
fb3f0f51 3825
b927a3ce
SY		 3826 if (enable_ept) {
3827 if (!kvm->arch.ept_identity_map_addr)
3828 kvm->arch.ept_identity_map_addr =
3829 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3830 if (alloc_identity_pagetable(kvm) != 0)
3831 goto free_vmcs;
b927a3ce 3832 }
b7ebfb05 3833
fb3f0f51
RR		 3834 return &vmx->vcpu;
3835
3836free_vmcs:
3837 free_vmcs(vmx->vmcs);
3838free_msrs:
3839 kfree(vmx->host_msrs);
3840free_guest_msrs:
3841 kfree(vmx->guest_msrs);
3842uninit_vcpu:
3843 kvm_vcpu_uninit(&vmx->vcpu);
3844free_vcpu:
a4770347 3845 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3846 return ERR_PTR(err);
6aa8b732
AK		 3847}
3848
002c7f7c
YS		 3849static void __init vmx_check_processor_compat(void *rtn)
3850{
3851 struct vmcs_config vmcs_conf;
3852
3853 *(int *)rtn = 0;
3854 if (setup_vmcs_config(&vmcs_conf) < 0)
3855 *(int *)rtn = -EIO;
3856 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3857 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3858 smp_processor_id());
3859 *(int *)rtn = -EIO;
3860 }
3861}
3862
67253af5
SY		 3863static int get_ept_level(void)
3864{
3865 return VMX_EPT_DEFAULT_GAW + 1;
3866}
3867
4b12f0de 3868static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3869{
4b12f0de
SY		 3870 u64 ret;
3871
522c68c4
SY		 3872 /* For VT-d and EPT combination
3873 * 1. MMIO: always map as UC
3874 * 2. EPT with VT-d:
3875 * a. VT-d without snooping control feature: can't guarantee the
3876 * result, try to trust guest.
3877 * b. VT-d with snooping control feature: snooping control feature of
3878 * VT-d engine can guarantee the cache correctness. Just set it
3879 * to WB to keep consistent with host. So the same as item 3.
3880 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3881 * consistent with host MTRR
3882 */
4b12f0de
SY		 3883 if (is_mmio)
3884 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3885 else if (vcpu->kvm->arch.iommu_domain &&
3886 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3887 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3888 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3889 else
522c68c4
SY		 3890 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3891 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3892
3893 return ret;
64d4d521
SY		 3894}
3895
229456fc
MT		 3896static const struct trace_print_flags vmx_exit_reasons_str[] = {
3897 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3898 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3899 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3900 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3901 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3902 { EXIT_REASON_CR_ACCESS, "cr_access" },
3903 { EXIT_REASON_DR_ACCESS, "dr_access" },
3904 { EXIT_REASON_CPUID, "cpuid" },
3905 { EXIT_REASON_MSR_READ, "rdmsr" },
3906 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3907 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3908 { EXIT_REASON_HLT, "halt" },
3909 { EXIT_REASON_INVLPG, "invlpg" },
3910 { EXIT_REASON_VMCALL, "hypercall" },
3911 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3912 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3913 { EXIT_REASON_WBINVD, "wbinvd" },
3914 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3915 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3916 { -1, NULL }
3917};
3918
344f414f
JR		 3919static bool vmx_gb_page_enable(void)
3920{
3921 return false;
3922}
3923
cbdd1bea 3924static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3925 .cpu_has_kvm_support = cpu_has_kvm_support,
3926 .disabled_by_bios = vmx_disabled_by_bios,
3927 .hardware_setup = hardware_setup,
3928 .hardware_unsetup = hardware_unsetup,
002c7f7c 3929 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3930 .hardware_enable = hardware_enable,
3931 .hardware_disable = hardware_disable,
04547156 3932 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3933
3934 .vcpu_create = vmx_create_vcpu,
3935 .vcpu_free = vmx_free_vcpu,
04d2cc77 3936 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3937
04d2cc77 3938 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3939 .vcpu_load = vmx_vcpu_load,
3940 .vcpu_put = vmx_vcpu_put,
3941
3942 .set_guest_debug = set_guest_debug,
3943 .get_msr = vmx_get_msr,
3944 .set_msr = vmx_set_msr,
3945 .get_segment_base = vmx_get_segment_base,
3946 .get_segment = vmx_get_segment,
3947 .set_segment = vmx_set_segment,
2e4d2653 3948 .get_cpl = vmx_get_cpl,
6aa8b732 3949 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3950 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3951 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3952 .set_cr3 = vmx_set_cr3,
3953 .set_cr4 = vmx_set_cr4,
6aa8b732 3954 .set_efer = vmx_set_efer,
6aa8b732
AK		 3955 .get_idt = vmx_get_idt,
3956 .set_idt = vmx_set_idt,
3957 .get_gdt = vmx_get_gdt,
3958 .set_gdt = vmx_set_gdt,
5fdbf976 3959 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3960 .get_rflags = vmx_get_rflags,
3961 .set_rflags = vmx_set_rflags,
3962
3963 .tlb_flush = vmx_flush_tlb,
6aa8b732 3964
6aa8b732 3965 .run = vmx_vcpu_run,
6062d012 3966 .handle_exit = vmx_handle_exit,
6aa8b732 3967 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3968 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3969 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 3970 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 3971 .set_irq = vmx_inject_irq,
95ba8273 3972 .set_nmi = vmx_inject_nmi,
298101da 3973 .queue_exception = vmx_queue_exception,
78646121 3974 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273
GN		 3975 .nmi_allowed = vmx_nmi_allowed,
3976 .enable_nmi_window = enable_nmi_window,
3977 .enable_irq_window = enable_irq_window,
3978 .update_cr8_intercept = update_cr8_intercept,
95ba8273 3979
cbc94022 3980 .set_tss_addr = vmx_set_tss_addr,
67253af5 3981 .get_tdp_level = get_ept_level,
4b12f0de 3982 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 3983
3984 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 3985 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 3986};
3987
3988static int __init vmx_init(void)
3989{
fdef3ad1
HQ		 3990 int r;
3991
3e7c73e9 3992 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3993 if (!vmx_io_bitmap_a)
3994 return -ENOMEM;
3995
3e7c73e9 3996 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3997 if (!vmx_io_bitmap_b) {
3998 r = -ENOMEM;
3999 goto out;
4000 }
4001
5897297b
AK		 4002 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4003 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4004 r = -ENOMEM;
4005 goto out1;
4006 }
4007
5897297b
AK		 4008 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4009 if (!vmx_msr_bitmap_longmode) {
4010 r = -ENOMEM;
4011 goto out2;
4012 }
4013
fdef3ad1
HQ		 4014 /*
4015 * Allow direct access to the PC debug port (it is often used for I/O
4016 * delays, but the vmexits simply slow things down).
4017 */
3e7c73e9
AK		 4018 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4019 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4020
3e7c73e9 4021 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4022
5897297b
AK		 4023 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4024 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4025
2384d2b3
SY		 4026 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4027
cb498ea2 4028 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4029 if (r)
5897297b 4030 goto out3;
25c5f225 4031
5897297b
AK		 4032 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4033 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4034 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4035 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4036 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4037 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4038
089d034e 4039 if (enable_ept) {
1439442c 4040 bypass_guest_pf = 0;
5fdbcb9d 4041 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4042 VMX_EPT_WRITABLE_MASK);
534e38b4 4043 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4044 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4045 kvm_enable_tdp();
4046 } else
4047 kvm_disable_tdp();
1439442c 4048
c7addb90
AK		 4049 if (bypass_guest_pf)
4050 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4051
fdef3ad1
HQ		 4052 return 0;
4053
5897297b
AK		 4054out3:
4055 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4056out2:
5897297b 4057 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4058out1:
3e7c73e9 4059 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4060out:
3e7c73e9 4061 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4062 return r;
6aa8b732
AK		 4063}
4064
4065static void __exit vmx_exit(void)
4066{
5897297b
AK		 4067 free_page((unsigned long)vmx_msr_bitmap_legacy);
4068 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4069 free_page((unsigned long)vmx_io_bitmap_b);
4070 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4071
cb498ea2 4072 kvm_exit();
6aa8b732
AK		 4073}
4074
4075module_init(vmx_init)
4076module_exit(vmx_exit)
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